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1 @c Copyright (C) 1996 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
4 @ifset GENERIC
5 @page
6 @node D10V-Dependent
7 @chapter D10V Dependent Features
8 @end ifset
9 @ifclear GENERIC
10 @node Machine Dependencies
11 @chapter D10V Dependent Features
12 @end ifclear
14 @cindex D10V support
15 @menu
16 * D10V-Opts:: D10V Options
17 * D10V-Syntax:: Syntax
18 * D10V-Float:: Floating Point
19 * D10V-Opcodes:: Opcodes
20 @end menu
22 @node D10V-Opts
23 @section D10V Options
24 @cindex options, D10V
25 @cindex D10V options
26 The Mitsubishi D10V version of @code{@value{AS}} has a few machine
27 dependent options.
29 @table @samp
30 @item -O
31 The D10V can often execute two sub-instructions in parallel. When this option
32 is used, @code{@value{AS}} will attempt to optimize its output by detecting when
33 instructions can be executed in parallel.
34 @item --nowarnswap
35 To optimize execution performance, @code{@value{AS}} will sometimes swap the
36 order of instructions. Normally this generates a warning. When this option
37 is used, no warning will be generated when instructions are swapped.
38 @end table
40 @node D10V-Syntax
41 @section Syntax
42 @cindex D10V syntax
43 @cindex syntax, D10V
45 The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual.
46 The differences are detailed below.
48 @menu
49 * D10V-Size:: Size Modifiers
50 * D10V-Subs:: Sub-Instructions
51 * D10V-Chars:: Special Characters
52 * D10V-Regs:: Register Names
53 * D10V-Addressing:: Addressing Modes
54 * D10V-Word:: @@WORD Modifier
55 @end menu
58 @node D10V-Size
59 @subsection Size Modifiers
60 @cindex D10V size modifiers
61 @cindex size modifiers, D10V
62 The D10V version of @code{@value{AS}} uses the instruction names in the D10V
63 Architecture Manual. However, the names in the manual are sometimes ambiguous.
64 There are instruction names that can assemble to a short or long form opcode.
65 How does the assembler pick the correct form? @code{@value{AS}} will always pick the
66 smallest form if it can. When dealing with a symbol that is not defined yet when a
67 line is being assembled, it will always use the long form. If you need to force the
68 assembler to use either the short or long form of the instruction, you can append
69 either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
70 an assembly program and you want to do a branch to a symbol that is defined later
71 in your program, you can write @samp{bra.s foo}.
72 Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
73 have both short and long forms.
75 @node D10V-Subs
76 @subsection Sub-Instructions
77 @cindex D10V sub-instructions
78 @cindex sub-instructions, D10V
79 The D10V assembler takes as input a series of instructions, either one-per-line,
80 or in the special two-per-line format described in the next section. Some of these
81 instructions will be short-form or sub-instructions. These sub-instructions can be packed
82 into a single instruction. The assembler will do this automatically. It will also detect
83 when it should not pack instructions. For example, when a label is defined, the next
84 instruction will never be packaged with the previous one. Whenever a branch and link
85 instruction is called, it will not be packaged with the next instruction so the return
86 address will be valid. Nops are automatically inserted when necessary.
88 If you do not want the assembler automatically making these decisions, you can control
89 the packaging and execution type (parallel or sequential) with the special execution
90 symbols described in the next section.
92 @node D10V-Chars
93 @subsection Special Characters
94 @cindex line comment character, D10V
95 @cindex D10V line comment character
96 @samp{;} and @samp{#} are the line comment characters.
97 @cindex sub-instruction ordering, D10V
98 @cindex D10V sub-instruction ordering
99 Sub-instructions may be executed in order, in reverse-order, or in parallel.
100 Instructions listed in the standard one-per-line format will be executed sequentially.
101 To specify the executing order, use the following symbols:
102 @table @samp
103 @item ->
104 Sequential with instruction on the left first.
105 @item <-
106 Sequential with instruction on the right first.
107 @item ||
108 Parallel
109 @end table
110 The D10V syntax allows either one instruction per line, one instruction per line with
111 the execution symbol, or two instructions per line. For example
112 @table @code
113 @item abs a1 -> abs r0
114 Execute these sequentially. The instruction on the right is in the right
115 container and is executed second.
116 @item abs r0 <- abs a1
117 Execute these reverse-sequentially. The instruction on the right is in the right
118 container, and is executed first.
119 @item ld2w r2,@@r8+ || mac a0,r0,r7
120 Execute these in parallel.
121 @item ld2w r2,@@r8+ ||
122 @itemx mac a0,r0,r7
123 Two-line format. Execute these in parallel.
124 @item ld2w r2,@@r8+
125 @itemx mac a0,r0,r7
126 Two-line format. Execute these sequentially. Assembler will
127 put them in the proper containers.
128 @item ld2w r2,@@r8+ ->
129 @itemx mac a0,r0,r7
130 Two-line format. Execute these sequentially. Same as above but
131 second instruction will always go into right container.
132 @end table
133 @cindex symbol names, @samp{$} in
134 @cindex @code{$} in symbol names
135 Since @samp{$} has no special meaning, you may use it in symbol names.
137 @node D10V-Regs
138 @subsection Register Names
139 @cindex D10V registers
140 @cindex registers, D10V
141 You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V
142 registers. You can also use @samp{sp} as an alias for @samp{r15}. The accumulators
143 are @samp{a0} and @samp{a1}. There are special register-pair names that may
144 optionally be used in opcodes that require even-numbered registers. Register names are
145 not case sensitive.
147 Register Pairs
148 @table @code
149 @item r0-r1
150 @item r2-r3
151 @item r4-r5
152 @item r6-r7
153 @item r8-r9
154 @item r10-r11
155 @item r12-r13
156 @item r14-r15
157 @end table
159 The D10V also has predefined symbols for these control registers and status bits:
160 @table @code
161 @item psw
162 Processor Status Word
163 @item bpsw
164 Backup Processor Status Word
165 @item pc
166 Program Counter
167 @item bpc
168 Backup Program Counter
169 @item rpt_c
170 Repeat Count
171 @item rpt_s
172 Repeat Start address
173 @item rpt_e
174 Repeat End address
175 @item mod_s
176 Modulo Start address
177 @item mod_e
178 Modulo End address
179 @item iba
180 Instruction Break Address
181 @item f0
182 Flag 0
183 @item f1
184 Flag 1
185 @item c
186 Carry flag
187 @end table
189 @node D10V-Addressing
190 @subsection Addressing Modes
191 @cindex addressing modes, D10V
192 @cindex D10V addressing modes
193 @code{@value{AS}} understands the following addressing modes for the D10V.
194 @code{R@var{n}} in the following refers to any of the numbered
195 registers, but @emph{not} the control registers.
196 @table @code
197 @item R@var{n}
198 Register direct
199 @item @@R@var{n}
200 Register indirect
201 @item @@R@var{n}+
202 Register indirect with post-increment
203 @item @@R@var{n}-
204 Register indirect with post-decrement
205 @item @@-SP
206 Register indirect with pre-decrement
207 @item @@(@var{disp}, R@var{n})
208 Register indirect with displacement
209 @item @var{addr}
210 PC relative address (for branch or rep).
211 @item #@var{imm}
212 Immediate data (the @samp{#} is optional and ignored)
213 @end table
215 @node D10V-Word
216 @subsection @@WORD Modifier
217 @cindex D10V @@word modifier
218 @cindex @@word modifier, D10V
219 Any symbol followed by @code{@@word} will be replaced by the symbol's value
220 shifted right by 2. This is used in situations such as loading a register
221 with the address of a function (or any other code fragment). For example, if
222 you want to load a register with the location of the function @code{main} then
223 jump to that function, you could do it as follws:
224 @smallexample
225 @group
226 ldi r2, main@@word
227 jmp r2
228 @end group
229 @end smallexample
231 @node D10V-Float
232 @section Floating Point
233 @cindex floating point, D10V
234 @cindex D10V floating point
235 The D10V has no hardware floating point, but the @code{.float} and @code{.double}
236 directives generates @sc{ieee} floating-point numbers for compatibility
237 with other development tools.
239 @node D10V-Opcodes
240 @section Opcodes
241 @cindex D10V opcode summary
242 @cindex opcode summary, D10V
243 @cindex mnemonics, D10V
244 @cindex instruction summary, D10V
245 For detailed information on the D10V machine instruction set, see
246 @cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications}
247 (Mitsubishi Electric Corp.).
248 @code{@value{AS}} implements all the standard D10V opcodes. The only changes are those
249 described in the section on size modifiers