1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Whether we are assembling for the mips16 processor. 0 if we are
152 not, 1 if we are, and -1 if the value has not been initialized.
153 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
154 -nomips16 command line options, and the default CPU. */
156 /* Non-zero if we should not reorder instructions. Changed by `.set
157 reorder' and `.set noreorder'. */
159 /* Non-zero if we should not permit the $at ($1) register to be used
160 in instructions. Changed by `.set at' and `.set noat'. */
162 /* Non-zero if we should warn when a macro instruction expands into
163 more than one machine instruction. Changed by `.set nomacro' and
165 int warn_about_macros
;
166 /* Non-zero if we should not move instructions. Changed by `.set
167 move', `.set volatile', `.set nomove', and `.set novolatile'. */
169 /* Non-zero if we should not optimize branches by moving the target
170 of the branch into the delay slot. Actually, we don't perform
171 this optimization anyhow. Changed by `.set bopt' and `.set
174 /* Non-zero if we should not autoextend mips16 instructions.
175 Changed by `.set autoextend' and `.set noautoextend'. */
179 /* This is the struct we use to hold the current set of options. Note
180 that we must set the isa and mips16 fields to -1 to indicate that
181 they have not been initialized. */
183 static struct mips_set_options mips_opts
= { -1, -1 };
185 /* These variables are filled in with the masks of registers used.
186 The object format code reads them and puts them in the appropriate
188 unsigned long mips_gprmask
;
189 unsigned long mips_cprmask
[4];
191 /* MIPS ISA we are using for this output file. */
192 static int file_mips_isa
;
194 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
195 static int mips_cpu
= -1;
197 /* The argument of the -mabi= flag. */
198 static char* mips_abi_string
= 0;
200 /* Wether we should mark the file EABI64 or EABI32. */
201 static int mips_eabi64
= 0;
203 /* If they asked for mips1 or mips2 and a cpu that is
204 mips3 or greater, then mark the object file 32BITMODE. */
205 static int mips_32bitmode
= 0;
207 /* Whether the processor uses hardware interlocks to protect
208 reads from the HI and LO registers, and thus does not
209 require nops to be inserted.
211 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
212 -mcpu=FOO schedules for FOO, but still produces code that meets the
213 requirements of MIPS ISA I. For example, it won't generate any
214 FOO-specific instructions, and it will still assume that any
215 scheduling hazards described in MIPS ISA I are there, even if FOO
216 has interlocks. -mFOO gives GCC permission to generate code that
217 will only run on a FOO; it will generate FOO-specific instructions,
218 and assume interlocks provided by a FOO.
220 However, GAS currently doesn't make this distinction; before Jan 28
221 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
222 assumptions. The GCC driver passes these flags through to GAS, so
223 if GAS actually does anything that doesn't meet MIPS ISA I with
224 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
226 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
227 which seems senseless --- why generate code which will only run on
228 a FOO, but schedule for something else?
230 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
232 -- Jim Blandy <jimb@cygnus.com> */
234 #define hilo_interlocks (mips_cpu == 4010 \
237 /* Whether the processor uses hardware interlocks to protect reads
238 from the GPRs, and thus does not require nops to be inserted. */
239 #define gpr_interlocks \
240 (mips_opts.isa >= 2 \
243 /* As with other "interlocks" this is used by hardware that has FP
244 (co-processor) interlocks. */
245 /* Itbl support may require additional care here. */
246 #define cop_interlocks (mips_cpu == 4300 \
249 /* MIPS PIC level. */
253 /* Do not generate PIC code. */
256 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
257 not sure what it is supposed to do. */
260 /* Generate PIC code as in the SVR4 MIPS ABI. */
263 /* Generate PIC code without using a global offset table: the data
264 segment has a maximum size of 64K, all data references are off
265 the $gp register, and all text references are PC relative. This
266 is used on some embedded systems. */
270 static enum mips_pic_level mips_pic
;
272 /* 1 if we should generate 32 bit offsets from the GP register in
273 SVR4_PIC mode. Currently has no meaning in other modes. */
274 static int mips_big_got
;
276 /* 1 if trap instructions should used for overflow rather than break
278 static int mips_trap
;
280 /* Non-zero if any .set noreorder directives were used. */
282 static int mips_any_noreorder
;
284 /* The size of the small data section. */
285 static int g_switch_value
= 8;
286 /* Whether the -G option was used. */
287 static int g_switch_seen
= 0;
292 /* If we can determine in advance that GP optimization won't be
293 possible, we can skip the relaxation stuff that tries to produce
294 GP-relative references. This makes delay slot optimization work
297 This function can only provide a guess, but it seems to work for
298 gcc output. If it guesses wrong, the only loss should be in
299 efficiency; it shouldn't introduce any bugs.
301 I don't know if a fix is needed for the SVR4_PIC mode. I've only
302 fixed it for the non-PIC mode. KR 95/04/07 */
303 static int nopic_need_relax
PARAMS ((symbolS
*, int));
305 /* handle of the OPCODE hash table */
306 static struct hash_control
*op_hash
= NULL
;
308 /* The opcode hash table we use for the mips16. */
309 static struct hash_control
*mips16_op_hash
= NULL
;
311 /* This array holds the chars that always start a comment. If the
312 pre-processor is disabled, these aren't very useful */
313 const char comment_chars
[] = "#";
315 /* This array holds the chars that only start a comment at the beginning of
316 a line. If the line seems to have the form '# 123 filename'
317 .line and .file directives will appear in the pre-processed output */
318 /* Note that input_file.c hand checks for '#' at the beginning of the
319 first line of the input file. This is because the compiler outputs
320 #NO_APP at the beginning of its output. */
321 /* Also note that C style comments are always supported. */
322 const char line_comment_chars
[] = "#";
324 /* This array holds machine specific line separator characters. */
325 const char line_separator_chars
[] = "";
327 /* Chars that can be used to separate mant from exp in floating point nums */
328 const char EXP_CHARS
[] = "eE";
330 /* Chars that mean this number is a floating point constant */
333 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
335 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
336 changed in read.c . Ideally it shouldn't have to know about it at all,
337 but nothing is ideal around here.
340 static char *insn_error
;
342 static int auto_align
= 1;
344 /* When outputting SVR4 PIC code, the assembler needs to know the
345 offset in the stack frame from which to restore the $gp register.
346 This is set by the .cprestore pseudo-op, and saved in this
348 static offsetT mips_cprestore_offset
= -1;
350 /* This is the register which holds the stack frame, as set by the
351 .frame pseudo-op. This is needed to implement .cprestore. */
352 static int mips_frame_reg
= SP
;
354 /* To output NOP instructions correctly, we need to keep information
355 about the previous two instructions. */
357 /* Whether we are optimizing. The default value of 2 means to remove
358 unneeded NOPs and swap branch instructions when possible. A value
359 of 1 means to not swap branches. A value of 0 means to always
361 static int mips_optimize
= 2;
363 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
364 equivalent to seeing no -g option at all. */
365 static int mips_debug
= 0;
367 /* The previous instruction. */
368 static struct mips_cl_insn prev_insn
;
370 /* The instruction before prev_insn. */
371 static struct mips_cl_insn prev_prev_insn
;
373 /* If we don't want information for prev_insn or prev_prev_insn, we
374 point the insn_mo field at this dummy integer. */
375 static const struct mips_opcode dummy_opcode
= { 0 };
377 /* Non-zero if prev_insn is valid. */
378 static int prev_insn_valid
;
380 /* The frag for the previous instruction. */
381 static struct frag
*prev_insn_frag
;
383 /* The offset into prev_insn_frag for the previous instruction. */
384 static long prev_insn_where
;
386 /* The reloc type for the previous instruction, if any. */
387 static bfd_reloc_code_real_type prev_insn_reloc_type
;
389 /* The reloc for the previous instruction, if any. */
390 static fixS
*prev_insn_fixp
;
392 /* Non-zero if the previous instruction was in a delay slot. */
393 static int prev_insn_is_delay_slot
;
395 /* Non-zero if the previous instruction was in a .set noreorder. */
396 static int prev_insn_unreordered
;
398 /* Non-zero if the previous instruction uses an extend opcode (if
400 static int prev_insn_extended
;
402 /* Non-zero if the previous previous instruction was in a .set
404 static int prev_prev_insn_unreordered
;
406 /* If this is set, it points to a frag holding nop instructions which
407 were inserted before the start of a noreorder section. If those
408 nops turn out to be unnecessary, the size of the frag can be
410 static fragS
*prev_nop_frag
;
412 /* The number of nop instructions we created in prev_nop_frag. */
413 static int prev_nop_frag_holds
;
415 /* The number of nop instructions that we know we need in
417 static int prev_nop_frag_required
;
419 /* The number of instructions we've seen since prev_nop_frag. */
420 static int prev_nop_frag_since
;
422 /* For ECOFF and ELF, relocations against symbols are done in two
423 parts, with a HI relocation and a LO relocation. Each relocation
424 has only 16 bits of space to store an addend. This means that in
425 order for the linker to handle carries correctly, it must be able
426 to locate both the HI and the LO relocation. This means that the
427 relocations must appear in order in the relocation table.
429 In order to implement this, we keep track of each unmatched HI
430 relocation. We then sort them so that they immediately precede the
431 corresponding LO relocation. */
436 struct mips_hi_fixup
*next
;
439 /* The section this fixup is in. */
443 /* The list of unmatched HI relocs. */
445 static struct mips_hi_fixup
*mips_hi_fixup_list
;
447 /* Map normal MIPS register numbers to mips16 register numbers. */
449 #define X ILLEGAL_REG
450 static const int mips32_to_16_reg_map
[] =
452 X
, X
, 2, 3, 4, 5, 6, 7,
453 X
, X
, X
, X
, X
, X
, X
, X
,
454 0, 1, X
, X
, X
, X
, X
, X
,
455 X
, X
, X
, X
, X
, X
, X
, X
459 /* Map mips16 register numbers to normal MIPS register numbers. */
461 static const int mips16_to_32_reg_map
[] =
463 16, 17, 2, 3, 4, 5, 6, 7
466 /* Since the MIPS does not have multiple forms of PC relative
467 instructions, we do not have to do relaxing as is done on other
468 platforms. However, we do have to handle GP relative addressing
469 correctly, which turns out to be a similar problem.
471 Every macro that refers to a symbol can occur in (at least) two
472 forms, one with GP relative addressing and one without. For
473 example, loading a global variable into a register generally uses
474 a macro instruction like this:
476 If i can be addressed off the GP register (this is true if it is in
477 the .sbss or .sdata section, or if it is known to be smaller than
478 the -G argument) this will generate the following instruction:
480 This instruction will use a GPREL reloc. If i can not be addressed
481 off the GP register, the following instruction sequence will be used:
484 In this case the first instruction will have a HI16 reloc, and the
485 second reloc will have a LO16 reloc. Both relocs will be against
488 The issue here is that we may not know whether i is GP addressable
489 until after we see the instruction that uses it. Therefore, we
490 want to be able to choose the final instruction sequence only at
491 the end of the assembly. This is similar to the way other
492 platforms choose the size of a PC relative instruction only at the
495 When generating position independent code we do not use GP
496 addressing in quite the same way, but the issue still arises as
497 external symbols and local symbols must be handled differently.
499 We handle these issues by actually generating both possible
500 instruction sequences. The longer one is put in a frag_var with
501 type rs_machine_dependent. We encode what to do with the frag in
502 the subtype field. We encode (1) the number of existing bytes to
503 replace, (2) the number of new bytes to use, (3) the offset from
504 the start of the existing bytes to the first reloc we must generate
505 (that is, the offset is applied from the start of the existing
506 bytes after they are replaced by the new bytes, if any), (4) the
507 offset from the start of the existing bytes to the second reloc,
508 (5) whether a third reloc is needed (the third reloc is always four
509 bytes after the second reloc), and (6) whether to warn if this
510 variant is used (this is sometimes needed if .set nomacro or .set
511 noat is in effect). All these numbers are reasonably small.
513 Generating two instruction sequences must be handled carefully to
514 ensure that delay slots are handled correctly. Fortunately, there
515 are a limited number of cases. When the second instruction
516 sequence is generated, append_insn is directed to maintain the
517 existing delay slot information, so it continues to apply to any
518 code after the second instruction sequence. This means that the
519 second instruction sequence must not impose any requirements not
520 required by the first instruction sequence.
522 These variant frags are then handled in functions called by the
523 machine independent code. md_estimate_size_before_relax returns
524 the final size of the frag. md_convert_frag sets up the final form
525 of the frag. tc_gen_reloc adjust the first reloc and adds a second
527 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
531 | (((reloc1) + 64) << 9) \
532 | (((reloc2) + 64) << 2) \
533 | ((reloc3) ? (1 << 1) : 0) \
535 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
536 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
537 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
538 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
539 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
540 #define RELAX_WARN(i) ((i) & 1)
542 /* For mips16 code, we use an entirely different form of relaxation.
543 mips16 supports two versions of most instructions which take
544 immediate values: a small one which takes some small value, and a
545 larger one which takes a 16 bit value. Since branches also follow
546 this pattern, relaxing these values is required.
548 We can assemble both mips16 and normal MIPS code in a single
549 object. Therefore, we need to support this type of relaxation at
550 the same time that we support the relaxation described above. We
551 use the high bit of the subtype field to distinguish these cases.
553 The information we store for this type of relaxation is the
554 argument code found in the opcode file for this relocation, whether
555 the user explicitly requested a small or extended form, and whether
556 the relocation is in a jump or jal delay slot. That tells us the
557 size of the value, and how it should be stored. We also store
558 whether the fragment is considered to be extended or not. We also
559 store whether this is known to be a branch to a different section,
560 whether we have tried to relax this frag yet, and whether we have
561 ever extended a PC relative fragment because of a shift count. */
562 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
565 | ((small) ? 0x100 : 0) \
566 | ((ext) ? 0x200 : 0) \
567 | ((dslot) ? 0x400 : 0) \
568 | ((jal_dslot) ? 0x800 : 0))
569 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
570 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
571 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
572 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
573 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
574 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
575 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
576 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
577 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
578 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
579 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
580 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
582 /* Prototypes for static functions. */
585 #define internalError() \
586 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
588 #define internalError() as_fatal (_("MIPS internal Error"));
591 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
593 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
594 unsigned int reg
, enum mips_regclass
class));
595 static int reg_needs_delay
PARAMS ((int));
596 static void mips16_mark_labels
PARAMS ((void));
597 static void append_insn
PARAMS ((char *place
,
598 struct mips_cl_insn
* ip
,
600 bfd_reloc_code_real_type r
,
602 static void mips_no_prev_insn
PARAMS ((int));
603 static void mips_emit_delays
PARAMS ((boolean
));
605 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
606 const char *name
, const char *fmt
,
609 static void macro_build ();
611 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
612 const char *, const char *,
614 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
615 expressionS
* ep
, int regnum
));
616 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
617 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
619 static void load_register
PARAMS ((int *, int, expressionS
*, int));
620 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
621 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
622 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
623 #ifdef LOSING_COMPILER
624 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
626 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
627 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
628 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
629 boolean
, boolean
, unsigned long *,
630 boolean
*, unsigned short *));
631 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
632 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
633 static symbolS
*get_symbol
PARAMS ((void));
634 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
635 static void s_align
PARAMS ((int));
636 static void s_change_sec
PARAMS ((int));
637 static void s_cons
PARAMS ((int));
638 static void s_float_cons
PARAMS ((int));
639 static void s_mips_globl
PARAMS ((int));
640 static void s_option
PARAMS ((int));
641 static void s_mipsset
PARAMS ((int));
642 static void s_abicalls
PARAMS ((int));
643 static void s_cpload
PARAMS ((int));
644 static void s_cprestore
PARAMS ((int));
645 static void s_gpword
PARAMS ((int));
646 static void s_cpadd
PARAMS ((int));
647 static void s_insn
PARAMS ((int));
648 static void md_obj_begin
PARAMS ((void));
649 static void md_obj_end
PARAMS ((void));
650 static long get_number
PARAMS ((void));
651 static void s_mips_ent
PARAMS ((int));
652 static void s_mips_end
PARAMS ((int));
653 static void s_mips_frame
PARAMS ((int));
654 static void s_mips_mask
PARAMS ((int));
655 static void s_mips_stab
PARAMS ((int));
656 static void s_mips_weakext
PARAMS ((int));
657 static void s_file
PARAMS ((int));
658 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
661 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
665 The following pseudo-ops from the Kane and Heinrich MIPS book
666 should be defined here, but are currently unsupported: .alias,
667 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
669 The following pseudo-ops from the Kane and Heinrich MIPS book are
670 specific to the type of debugging information being generated, and
671 should be defined by the object format: .aent, .begin, .bend,
672 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
675 The following pseudo-ops from the Kane and Heinrich MIPS book are
676 not MIPS CPU specific, but are also not specific to the object file
677 format. This file is probably the best place to define them, but
678 they are not currently supported: .asm0, .endr, .lab, .repeat,
681 static const pseudo_typeS mips_pseudo_table
[] =
683 /* MIPS specific pseudo-ops. */
684 {"option", s_option
, 0},
685 {"set", s_mipsset
, 0},
686 {"rdata", s_change_sec
, 'r'},
687 {"sdata", s_change_sec
, 's'},
688 {"livereg", s_ignore
, 0},
689 {"abicalls", s_abicalls
, 0},
690 {"cpload", s_cpload
, 0},
691 {"cprestore", s_cprestore
, 0},
692 {"gpword", s_gpword
, 0},
693 {"cpadd", s_cpadd
, 0},
696 /* Relatively generic pseudo-ops that happen to be used on MIPS
698 {"asciiz", stringer
, 1},
699 {"bss", s_change_sec
, 'b'},
702 {"dword", s_cons
, 3},
703 {"weakext", s_mips_weakext
, 0},
705 /* These pseudo-ops are defined in read.c, but must be overridden
706 here for one reason or another. */
707 {"align", s_align
, 0},
709 {"data", s_change_sec
, 'd'},
710 {"double", s_float_cons
, 'd'},
711 {"float", s_float_cons
, 'f'},
712 {"globl", s_mips_globl
, 0},
713 {"global", s_mips_globl
, 0},
714 {"hword", s_cons
, 1},
719 {"short", s_cons
, 1},
720 {"single", s_float_cons
, 'f'},
721 {"stabn", s_mips_stab
, 'n'},
722 {"text", s_change_sec
, 't'},
727 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
728 /* These pseudo-ops should be defined by the object file format.
729 However, a.out doesn't support them, so we have versions here. */
730 {"aent", s_mips_ent
, 1},
731 {"bgnb", s_ignore
, 0},
732 {"end", s_mips_end
, 0},
733 {"endb", s_ignore
, 0},
734 {"ent", s_mips_ent
, 0},
736 {"fmask", s_mips_mask
, 'F'},
737 {"frame", s_mips_frame
, 0},
738 {"loc", s_ignore
, 0},
739 {"mask", s_mips_mask
, 'R'},
740 {"verstamp", s_ignore
, 0},
744 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
749 pop_insert (mips_pseudo_table
);
750 if (! ECOFF_DEBUGGING
)
751 pop_insert (mips_nonecoff_pseudo_table
);
754 /* Symbols labelling the current insn. */
756 struct insn_label_list
758 struct insn_label_list
*next
;
762 static struct insn_label_list
*insn_labels
;
763 static struct insn_label_list
*free_insn_labels
;
765 static void mips_clear_insn_labels
PARAMS ((void));
768 mips_clear_insn_labels ()
770 register struct insn_label_list
**pl
;
772 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
778 static char *expr_end
;
780 /* Expressions which appear in instructions. These are set by
783 static expressionS imm_expr
;
784 static expressionS offset_expr
;
786 /* Relocs associated with imm_expr and offset_expr. */
788 static bfd_reloc_code_real_type imm_reloc
;
789 static bfd_reloc_code_real_type offset_reloc
;
791 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
793 static boolean imm_unmatched_hi
;
795 /* These are set by mips16_ip if an explicit extension is used. */
797 static boolean mips16_small
, mips16_ext
;
799 #ifdef MIPS_STABS_ELF
800 /* The pdr segment for per procedure frame/regmask info */
806 * This function is called once, at assembler startup time. It should
807 * set up all the tables, etc. that the MD part of the assembler will need.
813 register const char *retval
= NULL
;
814 register unsigned int i
= 0;
818 int mips_isa_from_cpu
;
821 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
823 a
= xmalloc (sizeof TARGET_CPU
);
824 strcpy (a
, TARGET_CPU
);
825 a
[(sizeof TARGET_CPU
) - 3] = '\0';
831 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
832 just the generic 'mips', in which case set mips_cpu based
833 on the given ISA, if any. */
835 if (strcmp (cpu
, "mips") == 0)
837 if (mips_opts
.isa
< 0)
840 else if (mips_opts
.isa
== 2)
843 else if (mips_opts
.isa
== 3)
846 else if (mips_opts
.isa
== 4)
853 else if (strcmp (cpu
, "r3900") == 0
854 || strcmp (cpu
, "mipstx39") == 0
858 else if (strcmp (cpu
, "r6000") == 0
859 || strcmp (cpu
, "mips2") == 0)
862 else if (strcmp (cpu
, "mips64") == 0
863 || strcmp (cpu
, "r4000") == 0
864 || strcmp (cpu
, "mips3") == 0)
867 else if (strcmp (cpu
, "r4400") == 0)
870 else if (strcmp (cpu
, "mips64orion") == 0
871 || strcmp (cpu
, "r4600") == 0)
874 else if (strcmp (cpu
, "r4650") == 0)
877 else if (strcmp (cpu
, "mips64vr4300") == 0)
880 else if (strcmp (cpu
, "mips64vr4111") == 0)
883 else if (strcmp (cpu
, "mips64vr4100") == 0)
886 else if (strcmp (cpu
, "r4010") == 0)
890 else if (strcmp (cpu
, "r5000") == 0
891 || strcmp (cpu
, "mips64vr5000") == 0)
896 else if (strcmp (cpu
, "r8000") == 0
897 || strcmp (cpu
, "mips4") == 0)
900 else if (strcmp (cpu
, "r10000") == 0)
903 else if (strcmp (cpu
, "mips16") == 0)
904 mips_cpu
= 0; /* FIXME */
912 mips_isa_from_cpu
= 1;
914 else if (mips_cpu
== 6000
916 mips_isa_from_cpu
= 2;
918 else if (mips_cpu
== 4000
925 mips_isa_from_cpu
= 3;
927 else if (mips_cpu
== 5000
929 || mips_cpu
== 10000)
930 mips_isa_from_cpu
= 4;
933 mips_isa_from_cpu
= -1;
935 if (mips_opts
.isa
== -1)
937 if (mips_isa_from_cpu
!= -1)
938 mips_opts
.isa
= mips_isa_from_cpu
;
943 if (mips_opts
.mips16
< 0)
945 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
946 mips_opts
.mips16
= 1;
948 mips_opts
.mips16
= 0;
951 /* End of TARGET_CPU processing, get rid of malloced memory
960 if (mips_opts
.isa
< 2 && mips_trap
)
961 as_bad (_("trap exception not supported at ISA 1"));
963 /* Set the EABI kind based on the ISA before the user gets
964 to change the ISA with directives. This isn't really
965 the best, but then neither is basing the abi on the isa. */
966 if (mips_opts
.isa
> 2
968 && 0 == strcmp (mips_abi_string
,"eabi"))
971 if (mips_cpu
!= 0 && mips_cpu
!= -1)
973 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
975 /* If they asked for mips1 or mips2 and a cpu that is
976 mips3 or greater, then mark the object file 32BITMODE. */
977 if (mips_isa_from_cpu
!= -1
978 && mips_opts
.isa
<= 2 && mips_isa_from_cpu
> 2)
983 switch (mips_opts
.isa
)
986 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
989 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
992 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
995 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1001 as_warn (_("Could not set architecture and machine"));
1003 file_mips_isa
= mips_opts
.isa
;
1005 op_hash
= hash_new ();
1007 for (i
= 0; i
< NUMOPCODES
;)
1009 const char *name
= mips_opcodes
[i
].name
;
1011 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1014 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1015 mips_opcodes
[i
].name
, retval
);
1016 /* Probably a memory allocation problem? Give up now. */
1017 as_fatal (_("Broken assembler. No assembly attempted."));
1021 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1023 if (!validate_mips_insn (&mips_opcodes
[i
]))
1028 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1031 mips16_op_hash
= hash_new ();
1034 while (i
< bfd_mips16_num_opcodes
)
1036 const char *name
= mips16_opcodes
[i
].name
;
1038 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1040 as_fatal (_("internal: can't hash `%s': %s"),
1041 mips16_opcodes
[i
].name
, retval
);
1044 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1045 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1046 != mips16_opcodes
[i
].match
))
1048 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1049 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1054 while (i
< bfd_mips16_num_opcodes
1055 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1059 as_fatal (_("Broken assembler. No assembly attempted."));
1061 /* We add all the general register names to the symbol table. This
1062 helps us detect invalid uses of them. */
1063 for (i
= 0; i
< 32; i
++)
1067 sprintf (buf
, "$%d", i
);
1068 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1069 &zero_address_frag
));
1071 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1072 &zero_address_frag
));
1073 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1074 &zero_address_frag
));
1075 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1076 &zero_address_frag
));
1077 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1078 &zero_address_frag
));
1079 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1080 &zero_address_frag
));
1081 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1082 &zero_address_frag
));
1083 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1084 &zero_address_frag
));
1086 mips_no_prev_insn (false);
1089 mips_cprmask
[0] = 0;
1090 mips_cprmask
[1] = 0;
1091 mips_cprmask
[2] = 0;
1092 mips_cprmask
[3] = 0;
1094 /* set the default alignment for the text section (2**2) */
1095 record_alignment (text_section
, 2);
1097 if (USE_GLOBAL_POINTER_OPT
)
1098 bfd_set_gp_size (stdoutput
, g_switch_value
);
1100 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1102 /* On a native system, sections must be aligned to 16 byte
1103 boundaries. When configured for an embedded ELF target, we
1105 if (strcmp (TARGET_OS
, "elf") != 0)
1107 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1108 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1109 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1112 /* Create a .reginfo section for register masks and a .mdebug
1113 section for debugging information. */
1121 subseg
= now_subseg
;
1123 /* The ABI says this section should be loaded so that the
1124 running program can access it. However, we don't load it
1125 if we are configured for an embedded target */
1126 flags
= SEC_READONLY
| SEC_DATA
;
1127 if (strcmp (TARGET_OS
, "elf") != 0)
1128 flags
|= SEC_ALLOC
| SEC_LOAD
;
1132 sec
= subseg_new (".reginfo", (subsegT
) 0);
1135 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1136 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1139 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1144 /* The 64-bit ABI uses a .MIPS.options section rather than
1145 .reginfo section. */
1146 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1147 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1148 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1151 /* Set up the option header. */
1153 Elf_Internal_Options opthdr
;
1156 opthdr
.kind
= ODK_REGINFO
;
1157 opthdr
.size
= (sizeof (Elf_External_Options
)
1158 + sizeof (Elf64_External_RegInfo
));
1161 f
= frag_more (sizeof (Elf_External_Options
));
1162 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1163 (Elf_External_Options
*) f
);
1165 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1170 if (ECOFF_DEBUGGING
)
1172 sec
= subseg_new (".mdebug", (subsegT
) 0);
1173 (void) bfd_set_section_flags (stdoutput
, sec
,
1174 SEC_HAS_CONTENTS
| SEC_READONLY
);
1175 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1178 #ifdef MIPS_STABS_ELF
1179 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1180 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1181 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1182 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1185 subseg_set (seg
, subseg
);
1189 if (! ECOFF_DEBUGGING
)
1196 if (! ECOFF_DEBUGGING
)
1204 struct mips_cl_insn insn
;
1206 imm_expr
.X_op
= O_absent
;
1207 imm_reloc
= BFD_RELOC_UNUSED
;
1208 imm_unmatched_hi
= false;
1209 offset_expr
.X_op
= O_absent
;
1210 offset_reloc
= BFD_RELOC_UNUSED
;
1212 if (mips_opts
.mips16
)
1213 mips16_ip (str
, &insn
);
1216 mips_ip (str
, &insn
);
1217 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1218 str
, insn
.insn_opcode
));
1223 as_bad ("%s `%s'", insn_error
, str
);
1227 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1229 if (mips_opts
.mips16
)
1230 mips16_macro (&insn
);
1236 if (imm_expr
.X_op
!= O_absent
)
1237 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1239 else if (offset_expr
.X_op
!= O_absent
)
1240 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1242 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1246 /* See whether instruction IP reads register REG. CLASS is the type
1250 insn_uses_reg (ip
, reg
, class)
1251 struct mips_cl_insn
*ip
;
1253 enum mips_regclass
class;
1255 if (class == MIPS16_REG
)
1257 assert (mips_opts
.mips16
);
1258 reg
= mips16_to_32_reg_map
[reg
];
1259 class = MIPS_GR_REG
;
1262 /* Don't report on general register 0, since it never changes. */
1263 if (class == MIPS_GR_REG
&& reg
== 0)
1266 if (class == MIPS_FP_REG
)
1268 assert (! mips_opts
.mips16
);
1269 /* If we are called with either $f0 or $f1, we must check $f0.
1270 This is not optimal, because it will introduce an unnecessary
1271 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1272 need to distinguish reading both $f0 and $f1 or just one of
1273 them. Note that we don't have to check the other way,
1274 because there is no instruction that sets both $f0 and $f1
1275 and requires a delay. */
1276 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1277 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1278 == (reg
&~ (unsigned) 1)))
1280 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1281 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1282 == (reg
&~ (unsigned) 1)))
1285 else if (! mips_opts
.mips16
)
1287 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1288 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1290 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1291 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1296 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1297 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1298 & MIPS16OP_MASK_RX
)]
1301 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1302 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1303 & MIPS16OP_MASK_RY
)]
1306 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1307 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1308 & MIPS16OP_MASK_MOVE32Z
)]
1311 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1313 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1315 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1317 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1318 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1319 & MIPS16OP_MASK_REGR32
) == reg
)
1326 /* This function returns true if modifying a register requires a
1330 reg_needs_delay (reg
)
1333 unsigned long prev_pinfo
;
1335 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1336 if (! mips_opts
.noreorder
1337 && mips_opts
.isa
< 4
1338 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1339 || (! gpr_interlocks
1340 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1342 /* A load from a coprocessor or from memory. All load
1343 delays delay the use of general register rt for one
1344 instruction on the r3000. The r6000 and r4000 use
1346 /* Itbl support may require additional care here. */
1347 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1348 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1355 /* Mark instruction labels in mips16 mode. This permits the linker to
1356 handle them specially, such as generating jalx instructions when
1357 needed. We also make them odd for the duration of the assembly, in
1358 order to generate the right sort of code. We will make them even
1359 in the adjust_symtab routine, while leaving them marked. This is
1360 convenient for the debugger and the disassembler. The linker knows
1361 to make them odd again. */
1364 mips16_mark_labels ()
1366 if (mips_opts
.mips16
)
1368 struct insn_label_list
*l
;
1370 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1373 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1374 S_SET_OTHER (l
->label
, STO_MIPS16
);
1376 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1377 ++l
->label
->sy_value
.X_add_number
;
1382 /* Output an instruction. PLACE is where to put the instruction; if
1383 it is NULL, this uses frag_more to get room. IP is the instruction
1384 information. ADDRESS_EXPR is an operand of the instruction to be
1385 used with RELOC_TYPE. */
1388 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1390 struct mips_cl_insn
*ip
;
1391 expressionS
*address_expr
;
1392 bfd_reloc_code_real_type reloc_type
;
1393 boolean unmatched_hi
;
1395 register unsigned long prev_pinfo
, pinfo
;
1400 /* Mark instruction labels in mips16 mode. */
1401 if (mips_opts
.mips16
)
1402 mips16_mark_labels ();
1404 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1405 pinfo
= ip
->insn_mo
->pinfo
;
1407 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1411 /* If the previous insn required any delay slots, see if we need
1412 to insert a NOP or two. There are eight kinds of possible
1413 hazards, of which an instruction can have at most one type.
1414 (1) a load from memory delay
1415 (2) a load from a coprocessor delay
1416 (3) an unconditional branch delay
1417 (4) a conditional branch delay
1418 (5) a move to coprocessor register delay
1419 (6) a load coprocessor register from memory delay
1420 (7) a coprocessor condition code delay
1421 (8) a HI/LO special register delay
1423 There are a lot of optimizations we could do that we don't.
1424 In particular, we do not, in general, reorder instructions.
1425 If you use gcc with optimization, it will reorder
1426 instructions and generally do much more optimization then we
1427 do here; repeating all that work in the assembler would only
1428 benefit hand written assembly code, and does not seem worth
1431 /* This is how a NOP is emitted. */
1432 #define emit_nop() \
1434 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1435 : md_number_to_chars (frag_more (4), 0, 4))
1437 /* The previous insn might require a delay slot, depending upon
1438 the contents of the current insn. */
1439 if (! mips_opts
.mips16
1440 && mips_opts
.isa
< 4
1441 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1442 && ! cop_interlocks
)
1443 || (! gpr_interlocks
1444 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1446 /* A load from a coprocessor or from memory. All load
1447 delays delay the use of general register rt for one
1448 instruction on the r3000. The r6000 and r4000 use
1450 /* Itbl support may require additional care here. */
1451 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1452 if (mips_optimize
== 0
1453 || insn_uses_reg (ip
,
1454 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1459 else if (! mips_opts
.mips16
1460 && mips_opts
.isa
< 4
1461 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1462 && ! cop_interlocks
)
1463 || (mips_opts
.isa
< 2
1464 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1466 /* A generic coprocessor delay. The previous instruction
1467 modified a coprocessor general or control register. If
1468 it modified a control register, we need to avoid any
1469 coprocessor instruction (this is probably not always
1470 required, but it sometimes is). If it modified a general
1471 register, we avoid using that register.
1473 On the r6000 and r4000 loading a coprocessor register
1474 from memory is interlocked, and does not require a delay.
1476 This case is not handled very well. There is no special
1477 knowledge of CP0 handling, and the coprocessors other
1478 than the floating point unit are not distinguished at
1480 /* Itbl support may require additional care here. FIXME!
1481 Need to modify this to include knowledge about
1482 user specified delays! */
1483 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1485 if (mips_optimize
== 0
1486 || insn_uses_reg (ip
,
1487 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1492 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1494 if (mips_optimize
== 0
1495 || insn_uses_reg (ip
,
1496 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1503 /* We don't know exactly what the previous instruction
1504 does. If the current instruction uses a coprocessor
1505 register, we must insert a NOP. If previous
1506 instruction may set the condition codes, and the
1507 current instruction uses them, we must insert two
1509 /* Itbl support may require additional care here. */
1510 if (mips_optimize
== 0
1511 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1512 && (pinfo
& INSN_READ_COND_CODE
)))
1514 else if (pinfo
& INSN_COP
)
1518 else if (! mips_opts
.mips16
1519 && mips_opts
.isa
< 4
1520 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1521 && ! cop_interlocks
)
1523 /* The previous instruction sets the coprocessor condition
1524 codes, but does not require a general coprocessor delay
1525 (this means it is a floating point comparison
1526 instruction). If this instruction uses the condition
1527 codes, we need to insert a single NOP. */
1528 /* Itbl support may require additional care here. */
1529 if (mips_optimize
== 0
1530 || (pinfo
& INSN_READ_COND_CODE
))
1533 else if (prev_pinfo
& INSN_READ_LO
)
1535 /* The previous instruction reads the LO register; if the
1536 current instruction writes to the LO register, we must
1537 insert two NOPS. Some newer processors have interlocks.
1538 Also the tx39's multiply instructions can be exectuted
1539 immediatly after a read from HI/LO (without the delay),
1540 though the tx39's divide insns still do require the
1542 if (! (hilo_interlocks
1543 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1544 && (mips_optimize
== 0
1545 || (pinfo
& INSN_WRITE_LO
)))
1547 /* Most mips16 branch insns don't have a delay slot.
1548 If a read from LO is immediately followed by a branch
1549 to a write to LO we have a read followed by a write
1550 less than 2 insns away. We assume the target of
1551 a branch might be a write to LO, and insert a nop
1552 between a read and an immediately following branch. */
1553 else if (mips_opts
.mips16
1554 && (mips_optimize
== 0
1555 || (pinfo
& MIPS16_INSN_BRANCH
)))
1558 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1560 /* The previous instruction reads the HI register; if the
1561 current instruction writes to the HI register, we must
1562 insert a NOP. Some newer processors have interlocks.
1563 Also the note tx39's multiply above. */
1564 if (! (hilo_interlocks
1565 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1566 && (mips_optimize
== 0
1567 || (pinfo
& INSN_WRITE_HI
)))
1569 /* Most mips16 branch insns don't have a delay slot.
1570 If a read from HI is immediately followed by a branch
1571 to a write to HI we have a read followed by a write
1572 less than 2 insns away. We assume the target of
1573 a branch might be a write to HI, and insert a nop
1574 between a read and an immediately following branch. */
1575 else if (mips_opts
.mips16
1576 && (mips_optimize
== 0
1577 || (pinfo
& MIPS16_INSN_BRANCH
)))
1581 /* If the previous instruction was in a noreorder section, then
1582 we don't want to insert the nop after all. */
1583 /* Itbl support may require additional care here. */
1584 if (prev_insn_unreordered
)
1587 /* There are two cases which require two intervening
1588 instructions: 1) setting the condition codes using a move to
1589 coprocessor instruction which requires a general coprocessor
1590 delay and then reading the condition codes 2) reading the HI
1591 or LO register and then writing to it (except on processors
1592 which have interlocks). If we are not already emitting a NOP
1593 instruction, we must check for these cases compared to the
1594 instruction previous to the previous instruction. */
1595 if ((! mips_opts
.mips16
1596 && mips_opts
.isa
< 4
1597 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1598 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1599 && (pinfo
& INSN_READ_COND_CODE
)
1600 && ! cop_interlocks
)
1601 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1602 && (pinfo
& INSN_WRITE_LO
)
1603 && ! (hilo_interlocks
1604 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
))))
1605 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1606 && (pinfo
& INSN_WRITE_HI
)
1607 && ! (hilo_interlocks
1608 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))))
1613 if (prev_prev_insn_unreordered
)
1616 if (prev_prev_nop
&& nops
== 0)
1619 /* If we are being given a nop instruction, don't bother with
1620 one of the nops we would otherwise output. This will only
1621 happen when a nop instruction is used with mips_optimize set
1624 && ! mips_opts
.noreorder
1625 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1628 /* Now emit the right number of NOP instructions. */
1629 if (nops
> 0 && ! mips_opts
.noreorder
)
1632 unsigned long old_frag_offset
;
1634 struct insn_label_list
*l
;
1636 old_frag
= frag_now
;
1637 old_frag_offset
= frag_now_fix ();
1639 for (i
= 0; i
< nops
; i
++)
1644 listing_prev_line ();
1645 /* We may be at the start of a variant frag. In case we
1646 are, make sure there is enough space for the frag
1647 after the frags created by listing_prev_line. The
1648 argument to frag_grow here must be at least as large
1649 as the argument to all other calls to frag_grow in
1650 this file. We don't have to worry about being in the
1651 middle of a variant frag, because the variants insert
1652 all needed nop instructions themselves. */
1656 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1658 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1659 l
->label
->sy_frag
= frag_now
;
1660 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1661 /* mips16 text labels are stored as odd. */
1662 if (mips_opts
.mips16
)
1663 ++l
->label
->sy_value
.X_add_number
;
1666 #ifndef NO_ECOFF_DEBUGGING
1667 if (ECOFF_DEBUGGING
)
1668 ecoff_fix_loc (old_frag
, old_frag_offset
);
1671 else if (prev_nop_frag
!= NULL
)
1673 /* We have a frag holding nops we may be able to remove. If
1674 we don't need any nops, we can decrease the size of
1675 prev_nop_frag by the size of one instruction. If we do
1676 need some nops, we count them in prev_nops_required. */
1677 if (prev_nop_frag_since
== 0)
1681 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1682 --prev_nop_frag_holds
;
1685 prev_nop_frag_required
+= nops
;
1689 if (prev_prev_nop
== 0)
1691 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1692 --prev_nop_frag_holds
;
1695 ++prev_nop_frag_required
;
1698 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1699 prev_nop_frag
= NULL
;
1701 ++prev_nop_frag_since
;
1703 /* Sanity check: by the time we reach the second instruction
1704 after prev_nop_frag, we should have used up all the nops
1705 one way or another. */
1706 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1710 if (reloc_type
> BFD_RELOC_UNUSED
)
1712 /* We need to set up a variant frag. */
1713 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1714 f
= frag_var (rs_machine_dependent
, 4, 0,
1715 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1716 mips16_small
, mips16_ext
,
1718 & INSN_UNCOND_BRANCH_DELAY
),
1719 (prev_insn_reloc_type
1720 == BFD_RELOC_MIPS16_JMP
)),
1721 make_expr_symbol (address_expr
), (offsetT
) 0,
1724 else if (place
!= NULL
)
1726 else if (mips_opts
.mips16
1728 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1730 /* Make sure there is enough room to swap this instruction with
1731 a following jump instruction. */
1737 if (mips_opts
.mips16
1738 && mips_opts
.noreorder
1739 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1740 as_warn (_("extended instruction in delay slot"));
1746 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1748 if (address_expr
->X_op
== O_constant
)
1753 ip
->insn_opcode
|= address_expr
->X_add_number
;
1756 case BFD_RELOC_LO16
:
1757 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1760 case BFD_RELOC_MIPS_JMP
:
1761 if ((address_expr
->X_add_number
& 3) != 0)
1762 as_bad (_("jump to misaligned address (0x%lx)"),
1763 (unsigned long) address_expr
->X_add_number
);
1764 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1767 case BFD_RELOC_MIPS16_JMP
:
1768 if ((address_expr
->X_add_number
& 3) != 0)
1769 as_bad (_("jump to misaligned address (0x%lx)"),
1770 (unsigned long) address_expr
->X_add_number
);
1772 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1773 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1774 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1778 case BFD_RELOC_16_PCREL_S2
:
1788 /* Don't generate a reloc if we are writing into a variant
1792 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1794 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1798 struct mips_hi_fixup
*hi_fixup
;
1800 assert (reloc_type
== BFD_RELOC_HI16_S
);
1801 hi_fixup
= ((struct mips_hi_fixup
*)
1802 xmalloc (sizeof (struct mips_hi_fixup
)));
1803 hi_fixup
->fixp
= fixp
;
1804 hi_fixup
->seg
= now_seg
;
1805 hi_fixup
->next
= mips_hi_fixup_list
;
1806 mips_hi_fixup_list
= hi_fixup
;
1812 if (! mips_opts
.mips16
)
1813 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1814 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1816 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1817 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1823 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1826 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1829 /* Update the register mask information. */
1830 if (! mips_opts
.mips16
)
1832 if (pinfo
& INSN_WRITE_GPR_D
)
1833 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1834 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1835 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1836 if (pinfo
& INSN_READ_GPR_S
)
1837 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1838 if (pinfo
& INSN_WRITE_GPR_31
)
1839 mips_gprmask
|= 1 << 31;
1840 if (pinfo
& INSN_WRITE_FPR_D
)
1841 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1842 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1843 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1844 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1845 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1846 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1847 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1848 if (pinfo
& INSN_COP
)
1850 /* We don't keep enough information to sort these cases out.
1851 The itbl support does keep this information however, although
1852 we currently don't support itbl fprmats as part of the cop
1853 instruction. May want to add this support in the future. */
1855 /* Never set the bit for $0, which is always zero. */
1856 mips_gprmask
&=~ 1 << 0;
1860 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1861 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1862 & MIPS16OP_MASK_RX
);
1863 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1864 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1865 & MIPS16OP_MASK_RY
);
1866 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1867 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1868 & MIPS16OP_MASK_RZ
);
1869 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1870 mips_gprmask
|= 1 << TREG
;
1871 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1872 mips_gprmask
|= 1 << SP
;
1873 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1874 mips_gprmask
|= 1 << RA
;
1875 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1876 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1877 if (pinfo
& MIPS16_INSN_READ_Z
)
1878 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1879 & MIPS16OP_MASK_MOVE32Z
);
1880 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1881 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1882 & MIPS16OP_MASK_REGR32
);
1885 if (place
== NULL
&& ! mips_opts
.noreorder
)
1887 /* Filling the branch delay slot is more complex. We try to
1888 switch the branch with the previous instruction, which we can
1889 do if the previous instruction does not set up a condition
1890 that the branch tests and if the branch is not itself the
1891 target of any branch. */
1892 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1893 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1895 if (mips_optimize
< 2
1896 /* If we have seen .set volatile or .set nomove, don't
1898 || mips_opts
.nomove
!= 0
1899 /* If we had to emit any NOP instructions, then we
1900 already know we can not swap. */
1902 /* If we don't even know the previous insn, we can not
1904 || ! prev_insn_valid
1905 /* If the previous insn is already in a branch delay
1906 slot, then we can not swap. */
1907 || prev_insn_is_delay_slot
1908 /* If the previous previous insn was in a .set
1909 noreorder, we can't swap. Actually, the MIPS
1910 assembler will swap in this situation. However, gcc
1911 configured -with-gnu-as will generate code like
1917 in which we can not swap the bne and INSN. If gcc is
1918 not configured -with-gnu-as, it does not output the
1919 .set pseudo-ops. We don't have to check
1920 prev_insn_unreordered, because prev_insn_valid will
1921 be 0 in that case. We don't want to use
1922 prev_prev_insn_valid, because we do want to be able
1923 to swap at the start of a function. */
1924 || prev_prev_insn_unreordered
1925 /* If the branch is itself the target of a branch, we
1926 can not swap. We cheat on this; all we check for is
1927 whether there is a label on this instruction. If
1928 there are any branches to anything other than a
1929 label, users must use .set noreorder. */
1930 || insn_labels
!= NULL
1931 /* If the previous instruction is in a variant frag, we
1932 can not do the swap. This does not apply to the
1933 mips16, which uses variant frags for different
1935 || (! mips_opts
.mips16
1936 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1937 /* If the branch reads the condition codes, we don't
1938 even try to swap, because in the sequence
1943 we can not swap, and I don't feel like handling that
1945 || (! mips_opts
.mips16
1946 && mips_opts
.isa
< 4
1947 && (pinfo
& INSN_READ_COND_CODE
))
1948 /* We can not swap with an instruction that requires a
1949 delay slot, becase the target of the branch might
1950 interfere with that instruction. */
1951 || (! mips_opts
.mips16
1952 && mips_opts
.isa
< 4
1954 /* Itbl support may require additional care here. */
1955 & (INSN_LOAD_COPROC_DELAY
1956 | INSN_COPROC_MOVE_DELAY
1957 | INSN_WRITE_COND_CODE
)))
1958 || (! (hilo_interlocks
1959 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1963 || (! mips_opts
.mips16
1965 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1966 || (! mips_opts
.mips16
1967 && mips_opts
.isa
< 2
1968 /* Itbl support may require additional care here. */
1969 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1970 /* We can not swap with a branch instruction. */
1972 & (INSN_UNCOND_BRANCH_DELAY
1973 | INSN_COND_BRANCH_DELAY
1974 | INSN_COND_BRANCH_LIKELY
))
1975 /* We do not swap with a trap instruction, since it
1976 complicates trap handlers to have the trap
1977 instruction be in a delay slot. */
1978 || (prev_pinfo
& INSN_TRAP
)
1979 /* If the branch reads a register that the previous
1980 instruction sets, we can not swap. */
1981 || (! mips_opts
.mips16
1982 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1983 && insn_uses_reg (ip
,
1984 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1987 || (! mips_opts
.mips16
1988 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1989 && insn_uses_reg (ip
,
1990 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1993 || (mips_opts
.mips16
1994 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1995 && insn_uses_reg (ip
,
1996 ((prev_insn
.insn_opcode
1998 & MIPS16OP_MASK_RX
),
2000 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2001 && insn_uses_reg (ip
,
2002 ((prev_insn
.insn_opcode
2004 & MIPS16OP_MASK_RY
),
2006 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2007 && insn_uses_reg (ip
,
2008 ((prev_insn
.insn_opcode
2010 & MIPS16OP_MASK_RZ
),
2012 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2013 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2014 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2015 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2016 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2017 && insn_uses_reg (ip
,
2018 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2021 /* If the branch writes a register that the previous
2022 instruction sets, we can not swap (we know that
2023 branches write only to RD or to $31). */
2024 || (! mips_opts
.mips16
2025 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2026 && (((pinfo
& INSN_WRITE_GPR_D
)
2027 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2028 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2029 || ((pinfo
& INSN_WRITE_GPR_31
)
2030 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2033 || (! mips_opts
.mips16
2034 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2035 && (((pinfo
& INSN_WRITE_GPR_D
)
2036 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2037 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2038 || ((pinfo
& INSN_WRITE_GPR_31
)
2039 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2042 || (mips_opts
.mips16
2043 && (pinfo
& MIPS16_INSN_WRITE_31
)
2044 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2045 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2046 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2048 /* If the branch writes a register that the previous
2049 instruction reads, we can not swap (we know that
2050 branches only write to RD or to $31). */
2051 || (! mips_opts
.mips16
2052 && (pinfo
& INSN_WRITE_GPR_D
)
2053 && insn_uses_reg (&prev_insn
,
2054 ((ip
->insn_opcode
>> OP_SH_RD
)
2057 || (! mips_opts
.mips16
2058 && (pinfo
& INSN_WRITE_GPR_31
)
2059 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2060 || (mips_opts
.mips16
2061 && (pinfo
& MIPS16_INSN_WRITE_31
)
2062 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2063 /* If we are generating embedded PIC code, the branch
2064 might be expanded into a sequence which uses $at, so
2065 we can't swap with an instruction which reads it. */
2066 || (mips_pic
== EMBEDDED_PIC
2067 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2068 /* If the previous previous instruction has a load
2069 delay, and sets a register that the branch reads, we
2071 || (! mips_opts
.mips16
2072 && mips_opts
.isa
< 4
2073 /* Itbl support may require additional care here. */
2074 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2075 || (! gpr_interlocks
2076 && (prev_prev_insn
.insn_mo
->pinfo
2077 & INSN_LOAD_MEMORY_DELAY
)))
2078 && insn_uses_reg (ip
,
2079 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2082 /* If one instruction sets a condition code and the
2083 other one uses a condition code, we can not swap. */
2084 || ((pinfo
& INSN_READ_COND_CODE
)
2085 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2086 || ((pinfo
& INSN_WRITE_COND_CODE
)
2087 && (prev_pinfo
& INSN_READ_COND_CODE
))
2088 /* If the previous instruction uses the PC, we can not
2090 || (mips_opts
.mips16
2091 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2092 /* If the previous instruction was extended, we can not
2094 || (mips_opts
.mips16
&& prev_insn_extended
)
2095 /* If the previous instruction had a fixup in mips16
2096 mode, we can not swap. This normally means that the
2097 previous instruction was a 4 byte branch anyhow. */
2098 || (mips_opts
.mips16
&& prev_insn_fixp
)
2099 /* If the previous instruction is a sync, sync.l, or
2100 sync.p, we can not swap. */
2101 || (prev_pinfo
&& INSN_SYNC
))
2103 /* We could do even better for unconditional branches to
2104 portions of this object file; we could pick up the
2105 instruction at the destination, put it in the delay
2106 slot, and bump the destination address. */
2108 /* Update the previous insn information. */
2109 prev_prev_insn
= *ip
;
2110 prev_insn
.insn_mo
= &dummy_opcode
;
2114 /* It looks like we can actually do the swap. */
2115 if (! mips_opts
.mips16
)
2120 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2121 memcpy (temp
, prev_f
, 4);
2122 memcpy (prev_f
, f
, 4);
2123 memcpy (f
, temp
, 4);
2126 prev_insn_fixp
->fx_frag
= frag_now
;
2127 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2131 fixp
->fx_frag
= prev_insn_frag
;
2132 fixp
->fx_where
= prev_insn_where
;
2140 assert (prev_insn_fixp
== NULL
);
2141 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2142 memcpy (temp
, prev_f
, 2);
2143 memcpy (prev_f
, f
, 2);
2144 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2146 assert (reloc_type
== BFD_RELOC_UNUSED
);
2147 memcpy (f
, temp
, 2);
2151 memcpy (f
, f
+ 2, 2);
2152 memcpy (f
+ 2, temp
, 2);
2156 fixp
->fx_frag
= prev_insn_frag
;
2157 fixp
->fx_where
= prev_insn_where
;
2161 /* Update the previous insn information; leave prev_insn
2163 prev_prev_insn
= *ip
;
2165 prev_insn_is_delay_slot
= 1;
2167 /* If that was an unconditional branch, forget the previous
2168 insn information. */
2169 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2171 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2172 prev_insn
.insn_mo
= &dummy_opcode
;
2175 prev_insn_fixp
= NULL
;
2176 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2177 prev_insn_extended
= 0;
2179 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2181 /* We don't yet optimize a branch likely. What we should do
2182 is look at the target, copy the instruction found there
2183 into the delay slot, and increment the branch to jump to
2184 the next instruction. */
2186 /* Update the previous insn information. */
2187 prev_prev_insn
= *ip
;
2188 prev_insn
.insn_mo
= &dummy_opcode
;
2189 prev_insn_fixp
= NULL
;
2190 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2191 prev_insn_extended
= 0;
2195 /* Update the previous insn information. */
2197 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2199 prev_prev_insn
= prev_insn
;
2202 /* Any time we see a branch, we always fill the delay slot
2203 immediately; since this insn is not a branch, we know it
2204 is not in a delay slot. */
2205 prev_insn_is_delay_slot
= 0;
2207 prev_insn_fixp
= fixp
;
2208 prev_insn_reloc_type
= reloc_type
;
2209 if (mips_opts
.mips16
)
2210 prev_insn_extended
= (ip
->use_extend
2211 || reloc_type
> BFD_RELOC_UNUSED
);
2214 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2215 prev_insn_unreordered
= 0;
2216 prev_insn_frag
= frag_now
;
2217 prev_insn_where
= f
- frag_now
->fr_literal
;
2218 prev_insn_valid
= 1;
2220 else if (place
== NULL
)
2222 /* We need to record a bit of information even when we are not
2223 reordering, in order to determine the base address for mips16
2224 PC relative relocs. */
2225 prev_prev_insn
= prev_insn
;
2227 prev_insn_reloc_type
= reloc_type
;
2228 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2229 prev_insn_unreordered
= 1;
2232 /* We just output an insn, so the next one doesn't have a label. */
2233 mips_clear_insn_labels ();
2235 /* We must ensure that a fixup associated with an unmatched %hi
2236 reloc does not become a variant frag. Otherwise, the
2237 rearrangement of %hi relocs in frob_file may confuse
2241 frag_wane (frag_now
);
2246 /* This function forgets that there was any previous instruction or
2247 label. If PRESERVE is non-zero, it remembers enough information to
2248 know whether nops are needed before a noreorder section. */
2251 mips_no_prev_insn (preserve
)
2256 prev_insn
.insn_mo
= &dummy_opcode
;
2257 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2258 prev_nop_frag
= NULL
;
2259 prev_nop_frag_holds
= 0;
2260 prev_nop_frag_required
= 0;
2261 prev_nop_frag_since
= 0;
2263 prev_insn_valid
= 0;
2264 prev_insn_is_delay_slot
= 0;
2265 prev_insn_unreordered
= 0;
2266 prev_insn_extended
= 0;
2267 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2268 prev_prev_insn_unreordered
= 0;
2269 mips_clear_insn_labels ();
2272 /* This function must be called whenever we turn on noreorder or emit
2273 something other than instructions. It inserts any NOPS which might
2274 be needed by the previous instruction, and clears the information
2275 kept for the previous instructions. The INSNS parameter is true if
2276 instructions are to follow. */
2279 mips_emit_delays (insns
)
2282 if (! mips_opts
.noreorder
)
2287 if ((! mips_opts
.mips16
2288 && mips_opts
.isa
< 4
2289 && (! cop_interlocks
2290 && (prev_insn
.insn_mo
->pinfo
2291 & (INSN_LOAD_COPROC_DELAY
2292 | INSN_COPROC_MOVE_DELAY
2293 | INSN_WRITE_COND_CODE
))))
2294 || (! hilo_interlocks
2295 && (prev_insn
.insn_mo
->pinfo
2298 || (! mips_opts
.mips16
2300 && (prev_insn
.insn_mo
->pinfo
2301 & INSN_LOAD_MEMORY_DELAY
))
2302 || (! mips_opts
.mips16
2303 && mips_opts
.isa
< 2
2304 && (prev_insn
.insn_mo
->pinfo
2305 & INSN_COPROC_MEMORY_DELAY
)))
2307 /* Itbl support may require additional care here. */
2309 if ((! mips_opts
.mips16
2310 && mips_opts
.isa
< 4
2311 && (! cop_interlocks
2312 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2313 || (! hilo_interlocks
2314 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2315 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2318 if (prev_insn_unreordered
)
2321 else if ((! mips_opts
.mips16
2322 && mips_opts
.isa
< 4
2323 && (! cop_interlocks
2324 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2325 || (! hilo_interlocks
2326 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2327 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2329 /* Itbl support may require additional care here. */
2330 if (! prev_prev_insn_unreordered
)
2336 struct insn_label_list
*l
;
2340 /* Record the frag which holds the nop instructions, so
2341 that we can remove them if we don't need them. */
2342 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2343 prev_nop_frag
= frag_now
;
2344 prev_nop_frag_holds
= nops
;
2345 prev_nop_frag_required
= 0;
2346 prev_nop_frag_since
= 0;
2349 for (; nops
> 0; --nops
)
2354 /* Move on to a new frag, so that it is safe to simply
2355 decrease the size of prev_nop_frag. */
2356 frag_wane (frag_now
);
2360 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2362 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2363 l
->label
->sy_frag
= frag_now
;
2364 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2365 /* mips16 text labels are stored as odd. */
2366 if (mips_opts
.mips16
)
2367 ++l
->label
->sy_value
.X_add_number
;
2372 /* Mark instruction labels in mips16 mode. */
2373 if (mips_opts
.mips16
&& insns
)
2374 mips16_mark_labels ();
2376 mips_no_prev_insn (insns
);
2379 /* Build an instruction created by a macro expansion. This is passed
2380 a pointer to the count of instructions created so far, an
2381 expression, the name of the instruction to build, an operand format
2382 string, and corresponding arguments. */
2386 macro_build (char *place
,
2394 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2403 struct mips_cl_insn insn
;
2404 bfd_reloc_code_real_type r
;
2409 va_start (args
, fmt
);
2415 * If the macro is about to expand into a second instruction,
2416 * print a warning if needed. We need to pass ip as a parameter
2417 * to generate a better warning message here...
2419 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2420 as_warn (_("Macro instruction expanded into multiple instructions"));
2423 *counter
+= 1; /* bump instruction counter */
2425 if (mips_opts
.mips16
)
2427 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2432 r
= BFD_RELOC_UNUSED
;
2433 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2434 assert (insn
.insn_mo
);
2435 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2437 /* Search until we get a match for NAME. */
2440 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2442 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2444 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2446 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2451 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2452 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2453 && (insn_isa
<= mips_opts
.isa
2454 || (mips_cpu
== 4650
2455 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2456 || (mips_cpu
== 4010
2457 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2458 || ((mips_cpu
== 4100
2461 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2462 || (mips_cpu
== 3900
2463 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2464 && (mips_cpu
!= 4650 || (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2468 assert (insn
.insn_mo
->name
);
2469 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2472 insn
.insn_opcode
= insn
.insn_mo
->match
;
2488 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2494 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2499 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2504 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2511 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2515 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2519 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2523 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2530 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2536 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2537 assert (r
== BFD_RELOC_MIPS_GPREL
2538 || r
== BFD_RELOC_MIPS_LITERAL
2539 || r
== BFD_RELOC_LO16
2540 || r
== BFD_RELOC_MIPS_GOT16
2541 || r
== BFD_RELOC_MIPS_CALL16
2542 || r
== BFD_RELOC_MIPS_GOT_LO16
2543 || r
== BFD_RELOC_MIPS_CALL_LO16
2544 || (ep
->X_op
== O_subtract
2545 && now_seg
== text_section
2546 && r
== BFD_RELOC_PCREL_LO16
));
2550 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2552 && (ep
->X_op
== O_constant
2553 || (ep
->X_op
== O_symbol
2554 && (r
== BFD_RELOC_HI16_S
2555 || r
== BFD_RELOC_HI16
2556 || r
== BFD_RELOC_MIPS_GOT_HI16
2557 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2558 || (ep
->X_op
== O_subtract
2559 && now_seg
== text_section
2560 && r
== BFD_RELOC_PCREL_HI16_S
)));
2561 if (ep
->X_op
== O_constant
)
2563 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2565 r
= BFD_RELOC_UNUSED
;
2570 assert (ep
!= NULL
);
2572 * This allows macro() to pass an immediate expression for
2573 * creating short branches without creating a symbol.
2574 * Note that the expression still might come from the assembly
2575 * input, in which case the value is not checked for range nor
2576 * is a relocation entry generated (yuck).
2578 if (ep
->X_op
== O_constant
)
2580 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2584 r
= BFD_RELOC_16_PCREL_S2
;
2588 assert (ep
!= NULL
);
2589 r
= BFD_RELOC_MIPS_JMP
;
2593 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2602 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2604 append_insn (place
, &insn
, ep
, r
, false);
2608 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2616 struct mips_cl_insn insn
;
2617 bfd_reloc_code_real_type r
;
2619 r
= BFD_RELOC_UNUSED
;
2620 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2621 assert (insn
.insn_mo
);
2622 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2624 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2625 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2628 assert (insn
.insn_mo
->name
);
2629 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2632 insn
.insn_opcode
= insn
.insn_mo
->match
;
2633 insn
.use_extend
= false;
2652 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2657 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2661 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2665 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2675 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2682 regno
= va_arg (args
, int);
2683 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2684 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2705 assert (ep
!= NULL
);
2707 if (ep
->X_op
!= O_constant
)
2708 r
= BFD_RELOC_UNUSED
+ c
;
2711 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2712 false, false, &insn
.insn_opcode
,
2713 &insn
.use_extend
, &insn
.extend
);
2715 r
= BFD_RELOC_UNUSED
;
2721 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2728 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2730 append_insn (place
, &insn
, ep
, r
, false);
2734 * Generate a "lui" instruction.
2737 macro_build_lui (place
, counter
, ep
, regnum
)
2743 expressionS high_expr
;
2744 struct mips_cl_insn insn
;
2745 bfd_reloc_code_real_type r
;
2746 CONST
char *name
= "lui";
2747 CONST
char *fmt
= "t,u";
2749 assert (! mips_opts
.mips16
);
2755 high_expr
.X_op
= O_constant
;
2756 high_expr
.X_add_number
= ep
->X_add_number
;
2759 if (high_expr
.X_op
== O_constant
)
2761 /* we can compute the instruction now without a relocation entry */
2762 if (high_expr
.X_add_number
& 0x8000)
2763 high_expr
.X_add_number
+= 0x10000;
2764 high_expr
.X_add_number
=
2765 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2766 r
= BFD_RELOC_UNUSED
;
2770 assert (ep
->X_op
== O_symbol
);
2771 /* _gp_disp is a special case, used from s_cpload. */
2772 assert (mips_pic
== NO_PIC
2773 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2774 r
= BFD_RELOC_HI16_S
;
2778 * If the macro is about to expand into a second instruction,
2779 * print a warning if needed. We need to pass ip as a parameter
2780 * to generate a better warning message here...
2782 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2783 as_warn (_("Macro instruction expanded into multiple instructions"));
2786 *counter
+= 1; /* bump instruction counter */
2788 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2789 assert (insn
.insn_mo
);
2790 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2791 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2793 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2794 if (r
== BFD_RELOC_UNUSED
)
2796 insn
.insn_opcode
|= high_expr
.X_add_number
;
2797 append_insn (place
, &insn
, NULL
, r
, false);
2800 append_insn (place
, &insn
, &high_expr
, r
, false);
2804 * Generates code to set the $at register to true (one)
2805 * if reg is less than the immediate expression.
2808 set_at (counter
, reg
, unsignedp
)
2813 if (imm_expr
.X_op
== O_constant
2814 && imm_expr
.X_add_number
>= -0x8000
2815 && imm_expr
.X_add_number
< 0x8000)
2816 macro_build ((char *) NULL
, counter
, &imm_expr
,
2817 unsignedp
? "sltiu" : "slti",
2818 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2821 load_register (counter
, AT
, &imm_expr
, 0);
2822 macro_build ((char *) NULL
, counter
, NULL
,
2823 unsignedp
? "sltu" : "slt",
2824 "d,v,t", AT
, reg
, AT
);
2828 /* Warn if an expression is not a constant. */
2831 check_absolute_expr (ip
, ex
)
2832 struct mips_cl_insn
*ip
;
2835 if (ex
->X_op
== O_big
)
2836 as_bad (_("unsupported large constant"));
2837 else if (ex
->X_op
!= O_constant
)
2838 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2841 /* Count the leading zeroes by performing a binary chop. This is a
2842 bulky bit of source, but performance is a LOT better for the
2843 majority of values than a simple loop to count the bits:
2844 for (lcnt = 0; (lcnt < 32); lcnt++)
2845 if ((v) & (1 << (31 - lcnt)))
2847 However it is not code size friendly, and the gain will drop a bit
2848 on certain cached systems.
2850 #define COUNT_TOP_ZEROES(v) \
2851 (((v) & ~0xffff) == 0 \
2852 ? ((v) & ~0xff) == 0 \
2853 ? ((v) & ~0xf) == 0 \
2854 ? ((v) & ~0x3) == 0 \
2855 ? ((v) & ~0x1) == 0 \
2860 : ((v) & ~0x7) == 0 \
2863 : ((v) & ~0x3f) == 0 \
2864 ? ((v) & ~0x1f) == 0 \
2867 : ((v) & ~0x7f) == 0 \
2870 : ((v) & ~0xfff) == 0 \
2871 ? ((v) & ~0x3ff) == 0 \
2872 ? ((v) & ~0x1ff) == 0 \
2875 : ((v) & ~0x7ff) == 0 \
2878 : ((v) & ~0x3fff) == 0 \
2879 ? ((v) & ~0x1fff) == 0 \
2882 : ((v) & ~0x7fff) == 0 \
2885 : ((v) & ~0xffffff) == 0 \
2886 ? ((v) & ~0xfffff) == 0 \
2887 ? ((v) & ~0x3ffff) == 0 \
2888 ? ((v) & ~0x1ffff) == 0 \
2891 : ((v) & ~0x7ffff) == 0 \
2894 : ((v) & ~0x3fffff) == 0 \
2895 ? ((v) & ~0x1fffff) == 0 \
2898 : ((v) & ~0x7fffff) == 0 \
2901 : ((v) & ~0xfffffff) == 0 \
2902 ? ((v) & ~0x3ffffff) == 0 \
2903 ? ((v) & ~0x1ffffff) == 0 \
2906 : ((v) & ~0x7ffffff) == 0 \
2909 : ((v) & ~0x3fffffff) == 0 \
2910 ? ((v) & ~0x1fffffff) == 0 \
2913 : ((v) & ~0x7fffffff) == 0 \
2918 * This routine generates the least number of instructions neccessary to load
2919 * an absolute expression value into a register.
2922 load_register (counter
, reg
, ep
, dbl
)
2929 expressionS hi32
, lo32
;
2931 if (ep
->X_op
!= O_big
)
2933 assert (ep
->X_op
== O_constant
);
2934 if (ep
->X_add_number
< 0x8000
2935 && (ep
->X_add_number
>= 0
2936 || (ep
->X_add_number
>= -0x8000
2939 || sizeof (ep
->X_add_number
) > 4))))
2941 /* We can handle 16 bit signed values with an addiu to
2942 $zero. No need to ever use daddiu here, since $zero and
2943 the result are always correct in 32 bit mode. */
2944 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2945 (int) BFD_RELOC_LO16
);
2948 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2950 /* We can handle 16 bit unsigned values with an ori to
2952 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2953 (int) BFD_RELOC_LO16
);
2956 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2957 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2958 == ~ (offsetT
) 0x7fffffff))
2961 || sizeof (ep
->X_add_number
) > 4
2962 || (ep
->X_add_number
& 0x80000000) == 0))
2963 || ((mips_opts
.isa
< 3 || ! dbl
)
2964 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2965 || (mips_opts
.isa
< 3
2967 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2968 == ~ (offsetT
) 0xffffffff)))
2970 /* 32 bit values require an lui. */
2971 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2972 (int) BFD_RELOC_HI16
);
2973 if ((ep
->X_add_number
& 0xffff) != 0)
2974 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2975 (int) BFD_RELOC_LO16
);
2980 /* The value is larger than 32 bits. */
2982 if (mips_opts
.isa
< 3)
2984 as_bad (_("Number larger than 32 bits"));
2985 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2986 (int) BFD_RELOC_LO16
);
2990 if (ep
->X_op
!= O_big
)
2993 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2994 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2995 hi32
.X_add_number
&= 0xffffffff;
2997 lo32
.X_add_number
&= 0xffffffff;
3001 assert (ep
->X_add_number
> 2);
3002 if (ep
->X_add_number
== 3)
3003 generic_bignum
[3] = 0;
3004 else if (ep
->X_add_number
> 4)
3005 as_bad (_("Number larger than 64 bits"));
3006 lo32
.X_op
= O_constant
;
3007 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3008 hi32
.X_op
= O_constant
;
3009 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3012 if (hi32
.X_add_number
== 0)
3017 unsigned long hi
, lo
;
3019 if (hi32
.X_add_number
== 0xffffffff)
3021 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3023 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3024 reg
, 0, (int) BFD_RELOC_LO16
);
3027 if (lo32
.X_add_number
& 0x80000000)
3029 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3030 (int) BFD_RELOC_HI16
);
3031 if (lo32
.X_add_number
& 0xffff)
3032 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3033 reg
, reg
, (int) BFD_RELOC_LO16
);
3038 /* Check for 16bit shifted constant. We know that hi32 is
3039 non-zero, so start the mask on the first bit of the hi32
3044 unsigned long himask
, lomask
;
3048 himask
= 0xffff >> (32 - shift
);
3049 lomask
= (0xffff << shift
) & 0xffffffff;
3053 himask
= 0xffff << (shift
- 32);
3056 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3057 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3061 tmp
.X_op
= O_constant
;
3063 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3064 | (lo32
.X_add_number
>> shift
));
3066 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3067 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3068 (int) BFD_RELOC_LO16
);
3069 macro_build ((char *) NULL
, counter
, NULL
,
3070 (shift
>= 32) ? "dsll32" : "dsll",
3072 (shift
>= 32) ? shift
- 32 : shift
);
3076 } while (shift
<= (64 - 16));
3078 /* Find the bit number of the lowest one bit, and store the
3079 shifted value in hi/lo. */
3080 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3081 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3085 while ((lo
& 1) == 0)
3090 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3096 while ((hi
& 1) == 0)
3105 /* Optimize if the shifted value is a (power of 2) - 1. */
3106 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3107 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3109 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3114 /* This instruction will set the register to be all
3116 tmp
.X_op
= O_constant
;
3117 tmp
.X_add_number
= (offsetT
) -1;
3118 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3119 reg
, 0, (int) BFD_RELOC_LO16
);
3123 macro_build ((char *) NULL
, counter
, NULL
,
3124 (bit
>= 32) ? "dsll32" : "dsll",
3126 (bit
>= 32) ? bit
- 32 : bit
);
3128 macro_build ((char *) NULL
, counter
, NULL
,
3129 (shift
>= 32) ? "dsrl32" : "dsrl",
3131 (shift
>= 32) ? shift
- 32 : shift
);
3136 /* Sign extend hi32 before calling load_register, because we can
3137 generally get better code when we load a sign extended value. */
3138 if ((hi32
.X_add_number
& 0x80000000) != 0)
3139 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3140 load_register (counter
, reg
, &hi32
, 0);
3143 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3147 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3156 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3158 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3159 (int) BFD_RELOC_HI16
);
3160 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3167 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3172 mid16
.X_add_number
>>= 16;
3173 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3174 freg
, (int) BFD_RELOC_LO16
);
3175 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3179 if ((lo32
.X_add_number
& 0xffff) != 0)
3180 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3181 (int) BFD_RELOC_LO16
);
3184 /* Load an address into a register. */
3187 load_address (counter
, reg
, ep
)
3194 if (ep
->X_op
!= O_constant
3195 && ep
->X_op
!= O_symbol
)
3197 as_bad (_("expression too complex"));
3198 ep
->X_op
= O_constant
;
3201 if (ep
->X_op
== O_constant
)
3203 load_register (counter
, reg
, ep
, 0);
3207 if (mips_pic
== NO_PIC
)
3209 /* If this is a reference to a GP relative symbol, we want
3210 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3212 lui $reg,<sym> (BFD_RELOC_HI16_S)
3213 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3214 If we have an addend, we always use the latter form. */
3215 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3216 || nopic_need_relax (ep
->X_add_symbol
, 1))
3221 macro_build ((char *) NULL
, counter
, ep
,
3222 ((bfd_arch_bits_per_address (stdoutput
) == 32
3223 || mips_opts
.isa
< 3)
3224 ? "addiu" : "daddiu"),
3225 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3226 p
= frag_var (rs_machine_dependent
, 8, 0,
3227 RELAX_ENCODE (4, 8, 0, 4, 0,
3228 mips_opts
.warn_about_macros
),
3229 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3231 macro_build_lui (p
, counter
, ep
, reg
);
3234 macro_build (p
, counter
, ep
,
3235 ((bfd_arch_bits_per_address (stdoutput
) == 32
3236 || mips_opts
.isa
< 3)
3237 ? "addiu" : "daddiu"),
3238 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3240 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3244 /* If this is a reference to an external symbol, we want
3245 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3247 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3249 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3250 If there is a constant, it must be added in after. */
3251 ex
.X_add_number
= ep
->X_add_number
;
3252 ep
->X_add_number
= 0;
3254 macro_build ((char *) NULL
, counter
, ep
,
3255 ((bfd_arch_bits_per_address (stdoutput
) == 32
3256 || mips_opts
.isa
< 3)
3258 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3259 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3260 p
= frag_var (rs_machine_dependent
, 4, 0,
3261 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3262 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3263 macro_build (p
, counter
, ep
,
3264 ((bfd_arch_bits_per_address (stdoutput
) == 32
3265 || mips_opts
.isa
< 3)
3266 ? "addiu" : "daddiu"),
3267 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3268 if (ex
.X_add_number
!= 0)
3270 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3271 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3272 ex
.X_op
= O_constant
;
3273 macro_build ((char *) NULL
, counter
, &ex
,
3274 ((bfd_arch_bits_per_address (stdoutput
) == 32
3275 || mips_opts
.isa
< 3)
3276 ? "addiu" : "daddiu"),
3277 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3280 else if (mips_pic
== SVR4_PIC
)
3285 /* This is the large GOT case. If this is a reference to an
3286 external symbol, we want
3287 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3289 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3290 Otherwise, for a reference to a local symbol, we want
3291 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3293 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3294 If there is a constant, it must be added in after. */
3295 ex
.X_add_number
= ep
->X_add_number
;
3296 ep
->X_add_number
= 0;
3297 if (reg_needs_delay (GP
))
3302 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3303 (int) BFD_RELOC_MIPS_GOT_HI16
);
3304 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3305 ((bfd_arch_bits_per_address (stdoutput
) == 32
3306 || mips_opts
.isa
< 3)
3307 ? "addu" : "daddu"),
3308 "d,v,t", reg
, reg
, GP
);
3309 macro_build ((char *) NULL
, counter
, ep
,
3310 ((bfd_arch_bits_per_address (stdoutput
) == 32
3311 || mips_opts
.isa
< 3)
3313 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3314 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3315 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3316 mips_opts
.warn_about_macros
),
3317 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3320 /* We need a nop before loading from $gp. This special
3321 check is required because the lui which starts the main
3322 instruction stream does not refer to $gp, and so will not
3323 insert the nop which may be required. */
3324 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3327 macro_build (p
, counter
, ep
,
3328 ((bfd_arch_bits_per_address (stdoutput
) == 32
3329 || mips_opts
.isa
< 3)
3331 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3333 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3335 macro_build (p
, counter
, ep
,
3336 ((bfd_arch_bits_per_address (stdoutput
) == 32
3337 || mips_opts
.isa
< 3)
3338 ? "addiu" : "daddiu"),
3339 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3340 if (ex
.X_add_number
!= 0)
3342 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3343 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3344 ex
.X_op
= O_constant
;
3345 macro_build ((char *) NULL
, counter
, &ex
,
3346 ((bfd_arch_bits_per_address (stdoutput
) == 32
3347 || mips_opts
.isa
< 3)
3348 ? "addiu" : "daddiu"),
3349 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3352 else if (mips_pic
== EMBEDDED_PIC
)
3355 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3357 macro_build ((char *) NULL
, counter
, ep
,
3358 ((bfd_arch_bits_per_address (stdoutput
) == 32
3359 || mips_opts
.isa
< 3)
3360 ? "addiu" : "daddiu"),
3361 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3369 * This routine implements the seemingly endless macro or synthesized
3370 * instructions and addressing modes in the mips assembly language. Many
3371 * of these macros are simple and are similar to each other. These could
3372 * probably be handled by some kind of table or grammer aproach instead of
3373 * this verbose method. Others are not simple macros but are more like
3374 * optimizing code generation.
3375 * One interesting optimization is when several store macros appear
3376 * consecutivly that would load AT with the upper half of the same address.
3377 * The ensuing load upper instructions are ommited. This implies some kind
3378 * of global optimization. We currently only optimize within a single macro.
3379 * For many of the load and store macros if the address is specified as a
3380 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3381 * first load register 'at' with zero and use it as the base register. The
3382 * mips assembler simply uses register $zero. Just one tiny optimization
3387 struct mips_cl_insn
*ip
;
3389 register int treg
, sreg
, dreg
, breg
;
3405 bfd_reloc_code_real_type r
;
3407 int hold_mips_optimize
;
3409 assert (! mips_opts
.mips16
);
3411 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3412 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3413 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3414 mask
= ip
->insn_mo
->mask
;
3416 expr1
.X_op
= O_constant
;
3417 expr1
.X_op_symbol
= NULL
;
3418 expr1
.X_add_symbol
= NULL
;
3419 expr1
.X_add_number
= 1;
3431 mips_emit_delays (true);
3432 ++mips_opts
.noreorder
;
3433 mips_any_noreorder
= 1;
3435 expr1
.X_add_number
= 8;
3436 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3438 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3440 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3441 macro_build ((char *) NULL
, &icnt
, NULL
,
3442 dbl
? "dsub" : "sub",
3443 "d,v,t", dreg
, 0, sreg
);
3445 --mips_opts
.noreorder
;
3466 if (imm_expr
.X_op
== O_constant
3467 && imm_expr
.X_add_number
>= -0x8000
3468 && imm_expr
.X_add_number
< 0x8000)
3470 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3471 (int) BFD_RELOC_LO16
);
3474 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3475 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3494 if (imm_expr
.X_op
== O_constant
3495 && imm_expr
.X_add_number
>= 0
3496 && imm_expr
.X_add_number
< 0x10000)
3498 if (mask
!= M_NOR_I
)
3499 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3500 sreg
, (int) BFD_RELOC_LO16
);
3503 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3504 treg
, sreg
, (int) BFD_RELOC_LO16
);
3505 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3511 load_register (&icnt
, AT
, &imm_expr
, 0);
3512 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3529 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3531 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3535 load_register (&icnt
, AT
, &imm_expr
, 0);
3536 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3544 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3545 likely
? "bgezl" : "bgez",
3551 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3552 likely
? "blezl" : "blez",
3556 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3557 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3558 likely
? "beql" : "beq",
3565 /* check for > max integer */
3566 maxnum
= 0x7fffffff;
3567 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3574 if (imm_expr
.X_op
== O_constant
3575 && imm_expr
.X_add_number
>= maxnum
3576 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3579 /* result is always false */
3582 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3583 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3587 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3588 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3593 if (imm_expr
.X_op
!= O_constant
)
3594 as_bad (_("Unsupported large constant"));
3595 imm_expr
.X_add_number
++;
3599 if (mask
== M_BGEL_I
)
3601 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3603 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3604 likely
? "bgezl" : "bgez",
3608 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3610 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3611 likely
? "bgtzl" : "bgtz",
3615 maxnum
= 0x7fffffff;
3616 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3623 maxnum
= - maxnum
- 1;
3624 if (imm_expr
.X_op
== O_constant
3625 && imm_expr
.X_add_number
<= maxnum
3626 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3629 /* result is always true */
3630 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3631 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3634 set_at (&icnt
, sreg
, 0);
3635 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3636 likely
? "beql" : "beq",
3647 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3648 likely
? "beql" : "beq",
3652 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3654 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3655 likely
? "beql" : "beq",
3663 || (mips_opts
.isa
< 3
3664 && imm_expr
.X_op
== O_constant
3665 && imm_expr
.X_add_number
== 0xffffffff))
3667 if (imm_expr
.X_op
!= O_constant
)
3668 as_bad (_("Unsupported large constant"));
3669 imm_expr
.X_add_number
++;
3673 if (mask
== M_BGEUL_I
)
3675 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3677 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3679 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3680 likely
? "bnel" : "bne",
3684 set_at (&icnt
, sreg
, 1);
3685 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3686 likely
? "beql" : "beq",
3695 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3696 likely
? "bgtzl" : "bgtz",
3702 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3703 likely
? "bltzl" : "bltz",
3707 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3708 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3709 likely
? "bnel" : "bne",
3718 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3719 likely
? "bnel" : "bne",
3725 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3727 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3728 likely
? "bnel" : "bne",
3737 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3738 likely
? "blezl" : "blez",
3744 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3745 likely
? "bgezl" : "bgez",
3749 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3751 likely
? "beql" : "beq",
3758 maxnum
= 0x7fffffff;
3759 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3766 if (imm_expr
.X_op
== O_constant
3767 && imm_expr
.X_add_number
>= maxnum
3768 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3770 if (imm_expr
.X_op
!= O_constant
)
3771 as_bad (_("Unsupported large constant"));
3772 imm_expr
.X_add_number
++;
3776 if (mask
== M_BLTL_I
)
3778 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3781 likely
? "bltzl" : "bltz",
3785 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3787 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3788 likely
? "blezl" : "blez",
3792 set_at (&icnt
, sreg
, 0);
3793 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3794 likely
? "bnel" : "bne",
3803 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3804 likely
? "beql" : "beq",
3810 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3812 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3813 likely
? "beql" : "beq",
3821 || (mips_opts
.isa
< 3
3822 && imm_expr
.X_op
== O_constant
3823 && imm_expr
.X_add_number
== 0xffffffff))
3825 if (imm_expr
.X_op
!= O_constant
)
3826 as_bad (_("Unsupported large constant"));
3827 imm_expr
.X_add_number
++;
3831 if (mask
== M_BLTUL_I
)
3833 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3835 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3837 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3838 likely
? "beql" : "beq",
3842 set_at (&icnt
, sreg
, 1);
3843 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3844 likely
? "bnel" : "bne",
3853 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3854 likely
? "bltzl" : "bltz",
3860 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3861 likely
? "bgtzl" : "bgtz",
3865 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3866 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3867 likely
? "bnel" : "bne",
3878 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3879 likely
? "bnel" : "bne",
3883 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3885 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3886 likely
? "bnel" : "bne",
3902 as_warn (_("Divide by zero."));
3904 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3906 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3910 mips_emit_delays (true);
3911 ++mips_opts
.noreorder
;
3912 mips_any_noreorder
= 1;
3915 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3916 macro_build ((char *) NULL
, &icnt
, NULL
,
3917 dbl
? "ddiv" : "div",
3918 "z,s,t", sreg
, treg
);
3922 expr1
.X_add_number
= 8;
3923 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3924 macro_build ((char *) NULL
, &icnt
, NULL
,
3925 dbl
? "ddiv" : "div",
3926 "z,s,t", sreg
, treg
);
3927 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3929 expr1
.X_add_number
= -1;
3930 macro_build ((char *) NULL
, &icnt
, &expr1
,
3931 dbl
? "daddiu" : "addiu",
3932 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3933 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3934 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3937 expr1
.X_add_number
= 1;
3938 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3939 (int) BFD_RELOC_LO16
);
3940 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3945 expr1
.X_add_number
= 0x80000000;
3946 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3947 (int) BFD_RELOC_HI16
);
3951 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3952 /* We want to close the noreorder block as soon as possible, so
3953 that later insns are available for delay slot filling. */
3954 --mips_opts
.noreorder
;
3958 expr1
.X_add_number
= 8;
3959 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3960 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3962 /* We want to close the noreorder block as soon as possible, so
3963 that later insns are available for delay slot filling. */
3964 --mips_opts
.noreorder
;
3966 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3968 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4007 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4009 as_warn (_("Divide by zero."));
4011 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4013 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4016 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4018 if (strcmp (s2
, "mflo") == 0)
4019 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4022 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4025 if (imm_expr
.X_op
== O_constant
4026 && imm_expr
.X_add_number
== -1
4027 && s
[strlen (s
) - 1] != 'u')
4029 if (strcmp (s2
, "mflo") == 0)
4032 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4035 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4039 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4043 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4044 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4045 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4064 mips_emit_delays (true);
4065 ++mips_opts
.noreorder
;
4066 mips_any_noreorder
= 1;
4069 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4070 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4071 /* We want to close the noreorder block as soon as possible, so
4072 that later insns are available for delay slot filling. */
4073 --mips_opts
.noreorder
;
4077 expr1
.X_add_number
= 8;
4078 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4079 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4081 /* We want to close the noreorder block as soon as possible, so
4082 that later insns are available for delay slot filling. */
4083 --mips_opts
.noreorder
;
4084 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4086 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4092 /* Load the address of a symbol into a register. If breg is not
4093 zero, we then add a base register to it. */
4095 /* When generating embedded PIC code, we permit expressions of
4098 where bar is an address in the .text section. These are used
4099 when getting the addresses of functions. We don't permit
4100 X_add_number to be non-zero, because if the symbol is
4101 external the relaxing code needs to know that any addend is
4102 purely the offset to X_op_symbol. */
4103 if (mips_pic
== EMBEDDED_PIC
4104 && offset_expr
.X_op
== O_subtract
4105 && now_seg
== text_section
4106 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4107 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4108 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4109 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4110 ->sy_value
.X_add_symbol
)
4113 && offset_expr
.X_add_number
== 0)
4115 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4116 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4117 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4118 ((bfd_arch_bits_per_address (stdoutput
) == 32
4119 || mips_opts
.isa
< 3)
4120 ? "addiu" : "daddiu"),
4121 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4125 if (offset_expr
.X_op
!= O_symbol
4126 && offset_expr
.X_op
!= O_constant
)
4128 as_bad (_("expression too complex"));
4129 offset_expr
.X_op
= O_constant
;
4143 if (offset_expr
.X_op
== O_constant
)
4144 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4145 else if (mips_pic
== NO_PIC
)
4147 /* If this is a reference to an GP relative symbol, we want
4148 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4150 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4151 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4152 If we have a constant, we need two instructions anyhow,
4153 so we may as well always use the latter form. */
4154 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4155 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4160 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4161 ((bfd_arch_bits_per_address (stdoutput
) == 32
4162 || mips_opts
.isa
< 3)
4163 ? "addiu" : "daddiu"),
4164 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4165 p
= frag_var (rs_machine_dependent
, 8, 0,
4166 RELAX_ENCODE (4, 8, 0, 4, 0,
4167 mips_opts
.warn_about_macros
),
4168 offset_expr
.X_add_symbol
, (offsetT
) 0,
4171 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4174 macro_build (p
, &icnt
, &offset_expr
,
4175 ((bfd_arch_bits_per_address (stdoutput
) == 32
4176 || mips_opts
.isa
< 3)
4177 ? "addiu" : "daddiu"),
4178 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4180 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4182 /* If this is a reference to an external symbol, and there
4183 is no constant, we want
4184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4185 For a local symbol, we want
4186 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4188 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4190 If we have a small constant, and this is a reference to
4191 an external symbol, we want
4192 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4194 addiu $tempreg,$tempreg,<constant>
4195 For a local symbol, we want the same instruction
4196 sequence, but we output a BFD_RELOC_LO16 reloc on the
4199 If we have a large constant, and this is a reference to
4200 an external symbol, we want
4201 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4202 lui $at,<hiconstant>
4203 addiu $at,$at,<loconstant>
4204 addu $tempreg,$tempreg,$at
4205 For a local symbol, we want the same instruction
4206 sequence, but we output a BFD_RELOC_LO16 reloc on the
4207 addiu instruction. */
4208 expr1
.X_add_number
= offset_expr
.X_add_number
;
4209 offset_expr
.X_add_number
= 0;
4211 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4213 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4214 if (expr1
.X_add_number
== 0)
4222 /* We're going to put in an addu instruction using
4223 tempreg, so we may as well insert the nop right
4225 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4229 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4230 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4232 ? mips_opts
.warn_about_macros
4234 offset_expr
.X_add_symbol
, (offsetT
) 0,
4238 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4241 macro_build (p
, &icnt
, &expr1
,
4242 ((bfd_arch_bits_per_address (stdoutput
) == 32
4243 || mips_opts
.isa
< 3)
4244 ? "addiu" : "daddiu"),
4245 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4246 /* FIXME: If breg == 0, and the next instruction uses
4247 $tempreg, then if this variant case is used an extra
4248 nop will be generated. */
4250 else if (expr1
.X_add_number
>= -0x8000
4251 && expr1
.X_add_number
< 0x8000)
4253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4255 macro_build ((char *) NULL
, &icnt
, &expr1
,
4256 ((bfd_arch_bits_per_address (stdoutput
) == 32
4257 || mips_opts
.isa
< 3)
4258 ? "addiu" : "daddiu"),
4259 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4260 (void) frag_var (rs_machine_dependent
, 0, 0,
4261 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4262 offset_expr
.X_add_symbol
, (offsetT
) 0,
4269 /* If we are going to add in a base register, and the
4270 target register and the base register are the same,
4271 then we are using AT as a temporary register. Since
4272 we want to load the constant into AT, we add our
4273 current AT (from the global offset table) and the
4274 register into the register now, and pretend we were
4275 not using a base register. */
4280 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4282 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4283 ((bfd_arch_bits_per_address (stdoutput
) == 32
4284 || mips_opts
.isa
< 3)
4285 ? "addu" : "daddu"),
4286 "d,v,t", treg
, AT
, breg
);
4292 /* Set mips_optimize around the lui instruction to avoid
4293 inserting an unnecessary nop after the lw. */
4294 hold_mips_optimize
= mips_optimize
;
4296 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4297 mips_optimize
= hold_mips_optimize
;
4299 macro_build ((char *) NULL
, &icnt
, &expr1
,
4300 ((bfd_arch_bits_per_address (stdoutput
) == 32
4301 || mips_opts
.isa
< 3)
4302 ? "addiu" : "daddiu"),
4303 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4305 ((bfd_arch_bits_per_address (stdoutput
) == 32
4306 || mips_opts
.isa
< 3)
4307 ? "addu" : "daddu"),
4308 "d,v,t", tempreg
, tempreg
, AT
);
4309 (void) frag_var (rs_machine_dependent
, 0, 0,
4310 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4311 offset_expr
.X_add_symbol
, (offsetT
) 0,
4316 else if (mips_pic
== SVR4_PIC
)
4320 /* This is the large GOT case. If this is a reference to an
4321 external symbol, and there is no constant, we want
4322 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4323 addu $tempreg,$tempreg,$gp
4324 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4325 For a local symbol, we want
4326 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4328 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4330 If we have a small constant, and this is a reference to
4331 an external symbol, we want
4332 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4333 addu $tempreg,$tempreg,$gp
4334 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4336 addiu $tempreg,$tempreg,<constant>
4337 For a local symbol, we want
4338 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4340 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4342 If we have a large constant, and this is a reference to
4343 an external symbol, we want
4344 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4345 addu $tempreg,$tempreg,$gp
4346 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4347 lui $at,<hiconstant>
4348 addiu $at,$at,<loconstant>
4349 addu $tempreg,$tempreg,$at
4350 For a local symbol, we want
4351 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4352 lui $at,<hiconstant>
4353 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4354 addu $tempreg,$tempreg,$at
4356 expr1
.X_add_number
= offset_expr
.X_add_number
;
4357 offset_expr
.X_add_number
= 0;
4359 if (reg_needs_delay (GP
))
4363 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4364 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4365 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4366 ((bfd_arch_bits_per_address (stdoutput
) == 32
4367 || mips_opts
.isa
< 3)
4368 ? "addu" : "daddu"),
4369 "d,v,t", tempreg
, tempreg
, GP
);
4370 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4372 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4374 if (expr1
.X_add_number
== 0)
4382 /* We're going to put in an addu instruction using
4383 tempreg, so we may as well insert the nop right
4385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4390 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4391 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4394 ? mips_opts
.warn_about_macros
4396 offset_expr
.X_add_symbol
, (offsetT
) 0,
4399 else if (expr1
.X_add_number
>= -0x8000
4400 && expr1
.X_add_number
< 0x8000)
4402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4404 macro_build ((char *) NULL
, &icnt
, &expr1
,
4405 ((bfd_arch_bits_per_address (stdoutput
) == 32
4406 || mips_opts
.isa
< 3)
4407 ? "addiu" : "daddiu"),
4408 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4410 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4411 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4413 ? mips_opts
.warn_about_macros
4415 offset_expr
.X_add_symbol
, (offsetT
) 0,
4422 /* If we are going to add in a base register, and the
4423 target register and the base register are the same,
4424 then we are using AT as a temporary register. Since
4425 we want to load the constant into AT, we add our
4426 current AT (from the global offset table) and the
4427 register into the register now, and pretend we were
4428 not using a base register. */
4436 assert (tempreg
== AT
);
4437 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4440 ((bfd_arch_bits_per_address (stdoutput
) == 32
4441 || mips_opts
.isa
< 3)
4442 ? "addu" : "daddu"),
4443 "d,v,t", treg
, AT
, breg
);
4448 /* Set mips_optimize around the lui instruction to avoid
4449 inserting an unnecessary nop after the lw. */
4450 hold_mips_optimize
= mips_optimize
;
4452 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4453 mips_optimize
= hold_mips_optimize
;
4455 macro_build ((char *) NULL
, &icnt
, &expr1
,
4456 ((bfd_arch_bits_per_address (stdoutput
) == 32
4457 || mips_opts
.isa
< 3)
4458 ? "addiu" : "daddiu"),
4459 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4460 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4461 ((bfd_arch_bits_per_address (stdoutput
) == 32
4462 || mips_opts
.isa
< 3)
4463 ? "addu" : "daddu"),
4464 "d,v,t", dreg
, dreg
, AT
);
4466 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4467 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4470 ? mips_opts
.warn_about_macros
4472 offset_expr
.X_add_symbol
, (offsetT
) 0,
4480 /* This is needed because this instruction uses $gp, but
4481 the first instruction on the main stream does not. */
4482 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4485 macro_build (p
, &icnt
, &offset_expr
,
4487 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4489 if (expr1
.X_add_number
>= -0x8000
4490 && expr1
.X_add_number
< 0x8000)
4492 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4494 macro_build (p
, &icnt
, &expr1
,
4495 ((bfd_arch_bits_per_address (stdoutput
) == 32
4496 || mips_opts
.isa
< 3)
4497 ? "addiu" : "daddiu"),
4498 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4499 /* FIXME: If add_number is 0, and there was no base
4500 register, the external symbol case ended with a load,
4501 so if the symbol turns out to not be external, and
4502 the next instruction uses tempreg, an unnecessary nop
4503 will be inserted. */
4509 /* We must add in the base register now, as in the
4510 external symbol case. */
4511 assert (tempreg
== AT
);
4512 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4514 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4515 ((bfd_arch_bits_per_address (stdoutput
) == 32
4516 || mips_opts
.isa
< 3)
4517 ? "addu" : "daddu"),
4518 "d,v,t", treg
, AT
, breg
);
4521 /* We set breg to 0 because we have arranged to add
4522 it in in both cases. */
4526 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4528 macro_build (p
, &icnt
, &expr1
,
4529 ((bfd_arch_bits_per_address (stdoutput
) == 32
4530 || mips_opts
.isa
< 3)
4531 ? "addiu" : "daddiu"),
4532 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4534 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4535 ((bfd_arch_bits_per_address (stdoutput
) == 32
4536 || mips_opts
.isa
< 3)
4537 ? "addu" : "daddu"),
4538 "d,v,t", tempreg
, tempreg
, AT
);
4542 else if (mips_pic
== EMBEDDED_PIC
)
4545 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4547 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4548 ((bfd_arch_bits_per_address (stdoutput
) == 32
4549 || mips_opts
.isa
< 3)
4550 ? "addiu" : "daddiu"),
4551 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4557 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4558 ((bfd_arch_bits_per_address (stdoutput
) == 32
4559 || mips_opts
.isa
< 3)
4560 ? "addu" : "daddu"),
4561 "d,v,t", treg
, tempreg
, breg
);
4569 /* The j instruction may not be used in PIC code, since it
4570 requires an absolute address. We convert it to a b
4572 if (mips_pic
== NO_PIC
)
4573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4575 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4578 /* The jal instructions must be handled as macros because when
4579 generating PIC code they expand to multi-instruction
4580 sequences. Normally they are simple instructions. */
4585 if (mips_pic
== NO_PIC
4586 || mips_pic
== EMBEDDED_PIC
)
4587 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4589 else if (mips_pic
== SVR4_PIC
)
4591 if (sreg
!= PIC_CALL_REG
)
4592 as_warn (_("MIPS PIC call to register other than $25"));
4594 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4596 if (mips_cprestore_offset
< 0)
4597 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4600 expr1
.X_add_number
= mips_cprestore_offset
;
4601 macro_build ((char *) NULL
, &icnt
, &expr1
,
4602 ((bfd_arch_bits_per_address (stdoutput
) == 32
4603 || mips_opts
.isa
< 3)
4605 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4614 if (mips_pic
== NO_PIC
)
4615 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4616 else if (mips_pic
== SVR4_PIC
)
4618 /* If this is a reference to an external symbol, and we are
4619 using a small GOT, we want
4620 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4624 lw $gp,cprestore($sp)
4625 The cprestore value is set using the .cprestore
4626 pseudo-op. If we are using a big GOT, we want
4627 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4629 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4633 lw $gp,cprestore($sp)
4634 If the symbol is not external, we want
4635 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4637 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4640 lw $gp,cprestore($sp) */
4644 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4645 ((bfd_arch_bits_per_address (stdoutput
) == 32
4646 || mips_opts
.isa
< 3)
4648 "t,o(b)", PIC_CALL_REG
,
4649 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4650 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4652 p
= frag_var (rs_machine_dependent
, 4, 0,
4653 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4654 offset_expr
.X_add_symbol
, (offsetT
) 0,
4661 if (reg_needs_delay (GP
))
4665 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4666 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4667 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4668 ((bfd_arch_bits_per_address (stdoutput
) == 32
4669 || mips_opts
.isa
< 3)
4670 ? "addu" : "daddu"),
4671 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4672 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4673 ((bfd_arch_bits_per_address (stdoutput
) == 32
4674 || mips_opts
.isa
< 3)
4676 "t,o(b)", PIC_CALL_REG
,
4677 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4678 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4680 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4681 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4683 offset_expr
.X_add_symbol
, (offsetT
) 0,
4687 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4690 macro_build (p
, &icnt
, &offset_expr
,
4691 ((bfd_arch_bits_per_address (stdoutput
) == 32
4692 || mips_opts
.isa
< 3)
4694 "t,o(b)", PIC_CALL_REG
,
4695 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4697 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4700 macro_build (p
, &icnt
, &offset_expr
,
4701 ((bfd_arch_bits_per_address (stdoutput
) == 32
4702 || mips_opts
.isa
< 3)
4703 ? "addiu" : "daddiu"),
4704 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4705 (int) BFD_RELOC_LO16
);
4706 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4707 "jalr", "s", PIC_CALL_REG
);
4708 if (mips_cprestore_offset
< 0)
4709 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4712 if (mips_opts
.noreorder
)
4713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4715 expr1
.X_add_number
= mips_cprestore_offset
;
4716 macro_build ((char *) NULL
, &icnt
, &expr1
,
4717 ((bfd_arch_bits_per_address (stdoutput
) == 32
4718 || mips_opts
.isa
< 3)
4720 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4724 else if (mips_pic
== EMBEDDED_PIC
)
4726 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4727 /* The linker may expand the call to a longer sequence which
4728 uses $at, so we must break rather than return. */
4753 /* Itbl support may require additional care here. */
4758 /* Itbl support may require additional care here. */
4763 /* Itbl support may require additional care here. */
4768 /* Itbl support may require additional care here. */
4780 if (mips_cpu
== 4650)
4782 as_bad (_("opcode not supported on this processor"));
4786 /* Itbl support may require additional care here. */
4791 /* Itbl support may require additional care here. */
4796 /* Itbl support may require additional care here. */
4816 if (breg
== treg
|| coproc
|| lr
)
4838 /* Itbl support may require additional care here. */
4843 /* Itbl support may require additional care here. */
4848 /* Itbl support may require additional care here. */
4853 /* Itbl support may require additional care here. */
4869 if (mips_cpu
== 4650)
4871 as_bad (_("opcode not supported on this processor"));
4876 /* Itbl support may require additional care here. */
4880 /* Itbl support may require additional care here. */
4885 /* Itbl support may require additional care here. */
4897 /* Itbl support may require additional care here. */
4898 if (mask
== M_LWC1_AB
4899 || mask
== M_SWC1_AB
4900 || mask
== M_LDC1_AB
4901 || mask
== M_SDC1_AB
4910 if (offset_expr
.X_op
!= O_constant
4911 && offset_expr
.X_op
!= O_symbol
)
4913 as_bad (_("expression too complex"));
4914 offset_expr
.X_op
= O_constant
;
4917 /* A constant expression in PIC code can be handled just as it
4918 is in non PIC code. */
4919 if (mips_pic
== NO_PIC
4920 || offset_expr
.X_op
== O_constant
)
4922 /* If this is a reference to a GP relative symbol, and there
4923 is no base register, we want
4924 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4925 Otherwise, if there is no base register, we want
4926 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4927 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4928 If we have a constant, we need two instructions anyhow,
4929 so we always use the latter form.
4931 If we have a base register, and this is a reference to a
4932 GP relative symbol, we want
4933 addu $tempreg,$breg,$gp
4934 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4936 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4937 addu $tempreg,$tempreg,$breg
4938 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4939 With a constant we always use the latter case. */
4942 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4943 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4948 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4949 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4950 p
= frag_var (rs_machine_dependent
, 8, 0,
4951 RELAX_ENCODE (4, 8, 0, 4, 0,
4952 (mips_opts
.warn_about_macros
4954 && mips_opts
.noat
))),
4955 offset_expr
.X_add_symbol
, (offsetT
) 0,
4959 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4962 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4963 (int) BFD_RELOC_LO16
, tempreg
);
4967 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4968 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4974 ((bfd_arch_bits_per_address (stdoutput
) == 32
4975 || mips_opts
.isa
< 3)
4976 ? "addu" : "daddu"),
4977 "d,v,t", tempreg
, breg
, GP
);
4978 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4979 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4980 p
= frag_var (rs_machine_dependent
, 12, 0,
4981 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4982 offset_expr
.X_add_symbol
, (offsetT
) 0,
4985 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4988 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4989 ((bfd_arch_bits_per_address (stdoutput
) == 32
4990 || mips_opts
.isa
< 3)
4991 ? "addu" : "daddu"),
4992 "d,v,t", tempreg
, tempreg
, breg
);
4995 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4996 (int) BFD_RELOC_LO16
, tempreg
);
4999 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5001 /* If this is a reference to an external symbol, we want
5002 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5004 <op> $treg,0($tempreg)
5006 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5008 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5009 <op> $treg,0($tempreg)
5010 If there is a base register, we add it to $tempreg before
5011 the <op>. If there is a constant, we stick it in the
5012 <op> instruction. We don't handle constants larger than
5013 16 bits, because we have no way to load the upper 16 bits
5014 (actually, we could handle them for the subset of cases
5015 in which we are not using $at). */
5016 assert (offset_expr
.X_op
== O_symbol
);
5017 expr1
.X_add_number
= offset_expr
.X_add_number
;
5018 offset_expr
.X_add_number
= 0;
5019 if (expr1
.X_add_number
< -0x8000
5020 || expr1
.X_add_number
>= 0x8000)
5021 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5024 ((bfd_arch_bits_per_address (stdoutput
) == 32
5025 || mips_opts
.isa
< 3)
5027 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5029 p
= frag_var (rs_machine_dependent
, 4, 0,
5030 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5031 offset_expr
.X_add_symbol
, (offsetT
) 0,
5033 macro_build (p
, &icnt
, &offset_expr
,
5034 ((bfd_arch_bits_per_address (stdoutput
) == 32
5035 || mips_opts
.isa
< 3)
5036 ? "addiu" : "daddiu"),
5037 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5040 ((bfd_arch_bits_per_address (stdoutput
) == 32
5041 || mips_opts
.isa
< 3)
5042 ? "addu" : "daddu"),
5043 "d,v,t", tempreg
, tempreg
, breg
);
5044 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5045 (int) BFD_RELOC_LO16
, tempreg
);
5047 else if (mips_pic
== SVR4_PIC
)
5051 /* If this is a reference to an external symbol, we want
5052 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5053 addu $tempreg,$tempreg,$gp
5054 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5055 <op> $treg,0($tempreg)
5057 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5059 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5060 <op> $treg,0($tempreg)
5061 If there is a base register, we add it to $tempreg before
5062 the <op>. If there is a constant, we stick it in the
5063 <op> instruction. We don't handle constants larger than
5064 16 bits, because we have no way to load the upper 16 bits
5065 (actually, we could handle them for the subset of cases
5066 in which we are not using $at). */
5067 assert (offset_expr
.X_op
== O_symbol
);
5068 expr1
.X_add_number
= offset_expr
.X_add_number
;
5069 offset_expr
.X_add_number
= 0;
5070 if (expr1
.X_add_number
< -0x8000
5071 || expr1
.X_add_number
>= 0x8000)
5072 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5073 if (reg_needs_delay (GP
))
5078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5079 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5081 ((bfd_arch_bits_per_address (stdoutput
) == 32
5082 || mips_opts
.isa
< 3)
5083 ? "addu" : "daddu"),
5084 "d,v,t", tempreg
, tempreg
, GP
);
5085 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5086 ((bfd_arch_bits_per_address (stdoutput
) == 32
5087 || mips_opts
.isa
< 3)
5089 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5091 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5092 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5093 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5096 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5099 macro_build (p
, &icnt
, &offset_expr
,
5100 ((bfd_arch_bits_per_address (stdoutput
) == 32
5101 || mips_opts
.isa
< 3)
5103 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5105 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5107 macro_build (p
, &icnt
, &offset_expr
,
5108 ((bfd_arch_bits_per_address (stdoutput
) == 32
5109 || mips_opts
.isa
< 3)
5110 ? "addiu" : "daddiu"),
5111 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5113 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5114 ((bfd_arch_bits_per_address (stdoutput
) == 32
5115 || mips_opts
.isa
< 3)
5116 ? "addu" : "daddu"),
5117 "d,v,t", tempreg
, tempreg
, breg
);
5118 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5119 (int) BFD_RELOC_LO16
, tempreg
);
5121 else if (mips_pic
== EMBEDDED_PIC
)
5123 /* If there is no base register, we want
5124 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5125 If there is a base register, we want
5126 addu $tempreg,$breg,$gp
5127 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5129 assert (offset_expr
.X_op
== O_symbol
);
5132 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5133 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5138 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5139 ((bfd_arch_bits_per_address (stdoutput
) == 32
5140 || mips_opts
.isa
< 3)
5141 ? "addu" : "daddu"),
5142 "d,v,t", tempreg
, breg
, GP
);
5143 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5144 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5157 load_register (&icnt
, treg
, &imm_expr
, 0);
5161 load_register (&icnt
, treg
, &imm_expr
, 1);
5165 if (imm_expr
.X_op
== O_constant
)
5167 load_register (&icnt
, AT
, &imm_expr
, 0);
5168 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5169 "mtc1", "t,G", AT
, treg
);
5174 assert (offset_expr
.X_op
== O_symbol
5175 && strcmp (segment_name (S_GET_SEGMENT
5176 (offset_expr
.X_add_symbol
)),
5178 && offset_expr
.X_add_number
== 0);
5179 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5180 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5185 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5186 the entire value, and in mips1 mode it is the high order 32
5187 bits of the value and the low order 32 bits are either zero
5188 or in offset_expr. */
5189 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5191 if (mips_opts
.isa
>= 3)
5192 load_register (&icnt
, treg
, &imm_expr
, 1);
5197 if (target_big_endian
)
5209 load_register (&icnt
, hreg
, &imm_expr
, 0);
5212 if (offset_expr
.X_op
== O_absent
)
5213 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5217 assert (offset_expr
.X_op
== O_constant
);
5218 load_register (&icnt
, lreg
, &offset_expr
, 0);
5225 /* We know that sym is in the .rdata section. First we get the
5226 upper 16 bits of the address. */
5227 if (mips_pic
== NO_PIC
)
5229 /* FIXME: This won't work for a 64 bit address. */
5230 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5232 else if (mips_pic
== SVR4_PIC
)
5234 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5235 ((bfd_arch_bits_per_address (stdoutput
) == 32
5236 || mips_opts
.isa
< 3)
5238 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5240 else if (mips_pic
== EMBEDDED_PIC
)
5242 /* For embedded PIC we pick up the entire address off $gp in
5243 a single instruction. */
5244 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5245 ((bfd_arch_bits_per_address (stdoutput
) == 32
5246 || mips_opts
.isa
< 3)
5247 ? "addiu" : "daddiu"),
5248 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5249 offset_expr
.X_op
= O_constant
;
5250 offset_expr
.X_add_number
= 0;
5255 /* Now we load the register(s). */
5256 if (mips_opts
.isa
>= 3)
5257 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5258 treg
, (int) BFD_RELOC_LO16
, AT
);
5261 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5262 treg
, (int) BFD_RELOC_LO16
, AT
);
5265 /* FIXME: How in the world do we deal with the possible
5267 offset_expr
.X_add_number
+= 4;
5268 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5269 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5273 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5274 does not become a variant frag. */
5275 frag_wane (frag_now
);
5281 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5282 the entire value, and in mips1 mode it is the high order 32
5283 bits of the value and the low order 32 bits are either zero
5284 or in offset_expr. */
5285 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5287 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5288 if (mips_opts
.isa
>= 3)
5289 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5290 "dmtc1", "t,S", AT
, treg
);
5293 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5294 "mtc1", "t,G", AT
, treg
+ 1);
5295 if (offset_expr
.X_op
== O_absent
)
5296 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5297 "mtc1", "t,G", 0, treg
);
5300 assert (offset_expr
.X_op
== O_constant
);
5301 load_register (&icnt
, AT
, &offset_expr
, 0);
5302 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5303 "mtc1", "t,G", AT
, treg
);
5309 assert (offset_expr
.X_op
== O_symbol
5310 && offset_expr
.X_add_number
== 0);
5311 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5312 if (strcmp (s
, ".lit8") == 0)
5314 if (mips_opts
.isa
>= 2)
5316 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5317 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5321 r
= BFD_RELOC_MIPS_LITERAL
;
5326 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5327 if (mips_pic
== SVR4_PIC
)
5328 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5329 ((bfd_arch_bits_per_address (stdoutput
) == 32
5330 || mips_opts
.isa
< 3)
5332 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5335 /* FIXME: This won't work for a 64 bit address. */
5336 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5339 if (mips_opts
.isa
>= 2)
5341 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5342 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5344 /* To avoid confusion in tc_gen_reloc, we must ensure
5345 that this does not become a variant frag. */
5346 frag_wane (frag_now
);
5357 if (mips_cpu
== 4650)
5359 as_bad (_("opcode not supported on this processor"));
5362 /* Even on a big endian machine $fn comes before $fn+1. We have
5363 to adjust when loading from memory. */
5366 assert (mips_opts
.isa
< 2);
5367 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5368 target_big_endian
? treg
+ 1 : treg
,
5370 /* FIXME: A possible overflow which I don't know how to deal
5372 offset_expr
.X_add_number
+= 4;
5373 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5374 target_big_endian
? treg
: treg
+ 1,
5377 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5378 does not become a variant frag. */
5379 frag_wane (frag_now
);
5388 * The MIPS assembler seems to check for X_add_number not
5389 * being double aligned and generating:
5392 * addiu at,at,%lo(foo+1)
5395 * But, the resulting address is the same after relocation so why
5396 * generate the extra instruction?
5398 if (mips_cpu
== 4650)
5400 as_bad (_("opcode not supported on this processor"));
5403 /* Itbl support may require additional care here. */
5405 if (mips_opts
.isa
>= 2)
5416 if (mips_cpu
== 4650)
5418 as_bad (_("opcode not supported on this processor"));
5422 if (mips_opts
.isa
>= 2)
5430 /* Itbl support may require additional care here. */
5435 if (mips_opts
.isa
>= 3)
5446 if (mips_opts
.isa
>= 3)
5456 if (offset_expr
.X_op
!= O_symbol
5457 && offset_expr
.X_op
!= O_constant
)
5459 as_bad (_("expression too complex"));
5460 offset_expr
.X_op
= O_constant
;
5463 /* Even on a big endian machine $fn comes before $fn+1. We have
5464 to adjust when loading from memory. We set coproc if we must
5465 load $fn+1 first. */
5466 /* Itbl support may require additional care here. */
5467 if (! target_big_endian
)
5470 if (mips_pic
== NO_PIC
5471 || offset_expr
.X_op
== O_constant
)
5473 /* If this is a reference to a GP relative symbol, we want
5474 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5475 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5476 If we have a base register, we use this
5478 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5479 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5480 If this is not a GP relative symbol, we want
5481 lui $at,<sym> (BFD_RELOC_HI16_S)
5482 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5483 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5484 If there is a base register, we add it to $at after the
5485 lui instruction. If there is a constant, we always use
5487 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5488 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5508 ((bfd_arch_bits_per_address (stdoutput
) == 32
5509 || mips_opts
.isa
< 3)
5510 ? "addu" : "daddu"),
5511 "d,v,t", AT
, breg
, GP
);
5517 /* Itbl support may require additional care here. */
5518 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5519 coproc
? treg
+ 1 : treg
,
5520 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5521 offset_expr
.X_add_number
+= 4;
5523 /* Set mips_optimize to 2 to avoid inserting an
5525 hold_mips_optimize
= mips_optimize
;
5527 /* Itbl support may require additional care here. */
5528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5529 coproc
? treg
: treg
+ 1,
5530 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5531 mips_optimize
= hold_mips_optimize
;
5533 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5534 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5535 used_at
&& mips_opts
.noat
),
5536 offset_expr
.X_add_symbol
, (offsetT
) 0,
5539 /* We just generated two relocs. When tc_gen_reloc
5540 handles this case, it will skip the first reloc and
5541 handle the second. The second reloc already has an
5542 extra addend of 4, which we added above. We must
5543 subtract it out, and then subtract another 4 to make
5544 the first reloc come out right. The second reloc
5545 will come out right because we are going to add 4 to
5546 offset_expr when we build its instruction below.
5548 If we have a symbol, then we don't want to include
5549 the offset, because it will wind up being included
5550 when we generate the reloc. */
5552 if (offset_expr
.X_op
== O_constant
)
5553 offset_expr
.X_add_number
-= 8;
5556 offset_expr
.X_add_number
= -4;
5557 offset_expr
.X_op
= O_constant
;
5560 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5565 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5566 ((bfd_arch_bits_per_address (stdoutput
) == 32
5567 || mips_opts
.isa
< 3)
5568 ? "addu" : "daddu"),
5569 "d,v,t", AT
, breg
, AT
);
5573 /* Itbl support may require additional care here. */
5574 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5575 coproc
? treg
+ 1 : treg
,
5576 (int) BFD_RELOC_LO16
, AT
);
5579 /* FIXME: How do we handle overflow here? */
5580 offset_expr
.X_add_number
+= 4;
5581 /* Itbl support may require additional care here. */
5582 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5583 coproc
? treg
: treg
+ 1,
5584 (int) BFD_RELOC_LO16
, AT
);
5586 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5590 /* If this is a reference to an external symbol, we want
5591 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5596 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5598 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5599 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5600 If there is a base register we add it to $at before the
5601 lwc1 instructions. If there is a constant we include it
5602 in the lwc1 instructions. */
5604 expr1
.X_add_number
= offset_expr
.X_add_number
;
5605 offset_expr
.X_add_number
= 0;
5606 if (expr1
.X_add_number
< -0x8000
5607 || expr1
.X_add_number
>= 0x8000 - 4)
5608 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5613 frag_grow (24 + off
);
5614 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5615 ((bfd_arch_bits_per_address (stdoutput
) == 32
5616 || mips_opts
.isa
< 3)
5618 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5619 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5621 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5622 ((bfd_arch_bits_per_address (stdoutput
) == 32
5623 || mips_opts
.isa
< 3)
5624 ? "addu" : "daddu"),
5625 "d,v,t", AT
, breg
, AT
);
5626 /* Itbl support may require additional care here. */
5627 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5628 coproc
? treg
+ 1 : treg
,
5629 (int) BFD_RELOC_LO16
, AT
);
5630 expr1
.X_add_number
+= 4;
5632 /* Set mips_optimize to 2 to avoid inserting an undesired
5634 hold_mips_optimize
= mips_optimize
;
5636 /* Itbl support may require additional care here. */
5637 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5638 coproc
? treg
: treg
+ 1,
5639 (int) BFD_RELOC_LO16
, AT
);
5640 mips_optimize
= hold_mips_optimize
;
5642 (void) frag_var (rs_machine_dependent
, 0, 0,
5643 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5644 offset_expr
.X_add_symbol
, (offsetT
) 0,
5647 else if (mips_pic
== SVR4_PIC
)
5651 /* If this is a reference to an external symbol, we want
5652 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5654 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5659 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5661 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5662 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5663 If there is a base register we add it to $at before the
5664 lwc1 instructions. If there is a constant we include it
5665 in the lwc1 instructions. */
5667 expr1
.X_add_number
= offset_expr
.X_add_number
;
5668 offset_expr
.X_add_number
= 0;
5669 if (expr1
.X_add_number
< -0x8000
5670 || expr1
.X_add_number
>= 0x8000 - 4)
5671 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5672 if (reg_needs_delay (GP
))
5681 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5682 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5684 ((bfd_arch_bits_per_address (stdoutput
) == 32
5685 || mips_opts
.isa
< 3)
5686 ? "addu" : "daddu"),
5687 "d,v,t", AT
, AT
, GP
);
5688 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5689 ((bfd_arch_bits_per_address (stdoutput
) == 32
5690 || mips_opts
.isa
< 3)
5692 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5693 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5695 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5696 ((bfd_arch_bits_per_address (stdoutput
) == 32
5697 || mips_opts
.isa
< 3)
5698 ? "addu" : "daddu"),
5699 "d,v,t", AT
, breg
, AT
);
5700 /* Itbl support may require additional care here. */
5701 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5702 coproc
? treg
+ 1 : treg
,
5703 (int) BFD_RELOC_LO16
, AT
);
5704 expr1
.X_add_number
+= 4;
5706 /* Set mips_optimize to 2 to avoid inserting an undesired
5708 hold_mips_optimize
= mips_optimize
;
5710 /* Itbl support may require additional care here. */
5711 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5712 coproc
? treg
: treg
+ 1,
5713 (int) BFD_RELOC_LO16
, AT
);
5714 mips_optimize
= hold_mips_optimize
;
5715 expr1
.X_add_number
-= 4;
5717 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5718 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5719 8 + gpdel
+ off
, 1, 0),
5720 offset_expr
.X_add_symbol
, (offsetT
) 0,
5724 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5727 macro_build (p
, &icnt
, &offset_expr
,
5728 ((bfd_arch_bits_per_address (stdoutput
) == 32
5729 || mips_opts
.isa
< 3)
5731 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5733 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5737 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5738 ((bfd_arch_bits_per_address (stdoutput
) == 32
5739 || mips_opts
.isa
< 3)
5740 ? "addu" : "daddu"),
5741 "d,v,t", AT
, breg
, AT
);
5744 /* Itbl support may require additional care here. */
5745 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5746 coproc
? treg
+ 1 : treg
,
5747 (int) BFD_RELOC_LO16
, AT
);
5749 expr1
.X_add_number
+= 4;
5751 /* Set mips_optimize to 2 to avoid inserting an undesired
5753 hold_mips_optimize
= mips_optimize
;
5755 /* Itbl support may require additional care here. */
5756 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5757 coproc
? treg
: treg
+ 1,
5758 (int) BFD_RELOC_LO16
, AT
);
5759 mips_optimize
= hold_mips_optimize
;
5761 else if (mips_pic
== EMBEDDED_PIC
)
5763 /* If there is no base register, we use
5764 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5765 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5766 If we have a base register, we use
5768 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5769 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5779 ((bfd_arch_bits_per_address (stdoutput
) == 32
5780 || mips_opts
.isa
< 3)
5781 ? "addu" : "daddu"),
5782 "d,v,t", AT
, breg
, GP
);
5787 /* Itbl support may require additional care here. */
5788 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5789 coproc
? treg
+ 1 : treg
,
5790 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5791 offset_expr
.X_add_number
+= 4;
5792 /* Itbl support may require additional care here. */
5793 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5794 coproc
? treg
: treg
+ 1,
5795 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5811 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
5812 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5813 (int) BFD_RELOC_LO16
, breg
);
5814 offset_expr
.X_add_number
+= 4;
5815 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5816 (int) BFD_RELOC_LO16
, breg
);
5819 /* New code added to support COPZ instructions.
5820 This code builds table entries out of the macros in mip_opcodes.
5821 R4000 uses interlocks to handle coproc delays.
5822 Other chips (like the R3000) require nops to be inserted for delays.
5824 FIXME: Currently, we require that the user handle delays.
5825 In order to fill delay slots for non-interlocked chips,
5826 we must have a way to specify delays based on the coprocessor.
5827 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5828 What are the side-effects of the cop instruction?
5829 What cache support might we have and what are its effects?
5830 Both coprocessor & memory require delays. how long???
5831 What registers are read/set/modified?
5833 If an itbl is provided to interpret cop instructions,
5834 this knowledge can be encoded in the itbl spec. */
5848 /* For now we just do C (same as Cz). The parameter will be
5849 stored in insn_opcode by mips_ip. */
5850 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5854 #ifdef LOSING_COMPILER
5856 /* Try and see if this is a new itbl instruction.
5857 This code builds table entries out of the macros in mip_opcodes.
5858 FIXME: For now we just assemble the expression and pass it's
5859 value along as a 32-bit immediate.
5860 We may want to have the assembler assemble this value,
5861 so that we gain the assembler's knowledge of delay slots,
5863 Would it be more efficient to use mask (id) here? */
5864 if (itbl_have_entries
5865 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5867 s
= ip
->insn_mo
->name
;
5869 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5870 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5877 as_warn (_("Macro used $at after \".set noat\""));
5882 struct mips_cl_insn
*ip
;
5884 register int treg
, sreg
, dreg
, breg
;
5900 bfd_reloc_code_real_type r
;
5903 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5904 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5905 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5906 mask
= ip
->insn_mo
->mask
;
5908 expr1
.X_op
= O_constant
;
5909 expr1
.X_op_symbol
= NULL
;
5910 expr1
.X_add_symbol
= NULL
;
5911 expr1
.X_add_number
= 1;
5915 #endif /* LOSING_COMPILER */
5920 macro_build ((char *) NULL
, &icnt
, NULL
,
5921 dbl
? "dmultu" : "multu",
5923 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5929 /* The MIPS assembler some times generates shifts and adds. I'm
5930 not trying to be that fancy. GCC should do this for us
5932 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5933 macro_build ((char *) NULL
, &icnt
, NULL
,
5934 dbl
? "dmult" : "mult",
5936 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5949 mips_emit_delays (true);
5950 ++mips_opts
.noreorder
;
5951 mips_any_noreorder
= 1;
5953 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5954 macro_build ((char *) NULL
, &icnt
, NULL
,
5955 dbl
? "dmult" : "mult",
5956 "s,t", sreg
, imm
? AT
: treg
);
5957 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5958 macro_build ((char *) NULL
, &icnt
, NULL
,
5959 dbl
? "dsra32" : "sra",
5960 "d,w,<", dreg
, dreg
, 31);
5961 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5963 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5966 expr1
.X_add_number
= 8;
5967 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5968 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5969 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5971 --mips_opts
.noreorder
;
5972 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5985 mips_emit_delays (true);
5986 ++mips_opts
.noreorder
;
5987 mips_any_noreorder
= 1;
5989 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5990 macro_build ((char *) NULL
, &icnt
, NULL
,
5991 dbl
? "dmultu" : "multu",
5992 "s,t", sreg
, imm
? AT
: treg
);
5993 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5994 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5996 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5999 expr1
.X_add_number
= 8;
6000 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6001 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6002 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6004 --mips_opts
.noreorder
;
6008 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6009 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6010 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6012 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6016 if (imm_expr
.X_op
!= O_constant
)
6017 as_bad (_("rotate count too large"));
6018 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6019 (int) (imm_expr
.X_add_number
& 0x1f));
6020 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6021 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6022 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6026 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6027 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6028 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6030 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6034 if (imm_expr
.X_op
!= O_constant
)
6035 as_bad (_("rotate count too large"));
6036 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6037 (int) (imm_expr
.X_add_number
& 0x1f));
6038 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6039 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6040 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6044 if (mips_cpu
== 4650)
6046 as_bad (_("opcode not supported on this processor"));
6049 assert (mips_opts
.isa
< 2);
6050 /* Even on a big endian machine $fn comes before $fn+1. We have
6051 to adjust when storing to memory. */
6052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6053 target_big_endian
? treg
+ 1 : treg
,
6054 (int) BFD_RELOC_LO16
, breg
);
6055 offset_expr
.X_add_number
+= 4;
6056 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6057 target_big_endian
? treg
: treg
+ 1,
6058 (int) BFD_RELOC_LO16
, breg
);
6063 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6064 treg
, (int) BFD_RELOC_LO16
);
6066 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6067 sreg
, (int) BFD_RELOC_LO16
);
6070 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6072 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6073 dreg
, (int) BFD_RELOC_LO16
);
6078 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6080 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6081 sreg
, (int) BFD_RELOC_LO16
);
6086 as_warn (_("Instruction %s: result is always false"),
6088 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6091 if (imm_expr
.X_op
== O_constant
6092 && imm_expr
.X_add_number
>= 0
6093 && imm_expr
.X_add_number
< 0x10000)
6095 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6096 sreg
, (int) BFD_RELOC_LO16
);
6099 else if (imm_expr
.X_op
== O_constant
6100 && imm_expr
.X_add_number
> -0x8000
6101 && imm_expr
.X_add_number
< 0)
6103 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6104 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6105 ((bfd_arch_bits_per_address (stdoutput
) == 32
6106 || mips_opts
.isa
< 3)
6107 ? "addiu" : "daddiu"),
6108 "t,r,j", dreg
, sreg
,
6109 (int) BFD_RELOC_LO16
);
6114 load_register (&icnt
, AT
, &imm_expr
, 0);
6115 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6119 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6120 (int) BFD_RELOC_LO16
);
6125 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6131 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6132 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6133 (int) BFD_RELOC_LO16
);
6136 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6138 if (imm_expr
.X_op
== O_constant
6139 && imm_expr
.X_add_number
>= -0x8000
6140 && imm_expr
.X_add_number
< 0x8000)
6142 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6143 mask
== M_SGE_I
? "slti" : "sltiu",
6144 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6149 load_register (&icnt
, AT
, &imm_expr
, 0);
6150 macro_build ((char *) NULL
, &icnt
, NULL
,
6151 mask
== M_SGE_I
? "slt" : "sltu",
6152 "d,v,t", dreg
, sreg
, AT
);
6155 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6156 (int) BFD_RELOC_LO16
);
6161 case M_SGT
: /* sreg > treg <==> treg < sreg */
6167 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6170 case M_SGT_I
: /* sreg > I <==> I < sreg */
6176 load_register (&icnt
, AT
, &imm_expr
, 0);
6177 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6180 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6186 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6187 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6188 (int) BFD_RELOC_LO16
);
6191 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6197 load_register (&icnt
, AT
, &imm_expr
, 0);
6198 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6199 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6200 (int) BFD_RELOC_LO16
);
6204 if (imm_expr
.X_op
== O_constant
6205 && imm_expr
.X_add_number
>= -0x8000
6206 && imm_expr
.X_add_number
< 0x8000)
6208 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6209 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6212 load_register (&icnt
, AT
, &imm_expr
, 0);
6213 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6217 if (imm_expr
.X_op
== O_constant
6218 && imm_expr
.X_add_number
>= -0x8000
6219 && imm_expr
.X_add_number
< 0x8000)
6221 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6222 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6225 load_register (&icnt
, AT
, &imm_expr
, 0);
6226 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6232 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6235 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6239 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6241 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6247 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6249 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6255 as_warn (_("Instruction %s: result is always true"),
6257 macro_build ((char *) NULL
, &icnt
, &expr1
,
6258 ((bfd_arch_bits_per_address (stdoutput
) == 32
6259 || mips_opts
.isa
< 3)
6260 ? "addiu" : "daddiu"),
6261 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6264 if (imm_expr
.X_op
== O_constant
6265 && imm_expr
.X_add_number
>= 0
6266 && imm_expr
.X_add_number
< 0x10000)
6268 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6269 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6272 else if (imm_expr
.X_op
== O_constant
6273 && imm_expr
.X_add_number
> -0x8000
6274 && imm_expr
.X_add_number
< 0)
6276 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6277 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6278 ((bfd_arch_bits_per_address (stdoutput
) == 32
6279 || mips_opts
.isa
< 3)
6280 ? "addiu" : "daddiu"),
6281 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6286 load_register (&icnt
, AT
, &imm_expr
, 0);
6287 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6291 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6299 if (imm_expr
.X_op
== O_constant
6300 && imm_expr
.X_add_number
> -0x8000
6301 && imm_expr
.X_add_number
<= 0x8000)
6303 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6304 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6305 dbl
? "daddi" : "addi",
6306 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6309 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6310 macro_build ((char *) NULL
, &icnt
, NULL
,
6311 dbl
? "dsub" : "sub",
6312 "d,v,t", dreg
, sreg
, AT
);
6318 if (imm_expr
.X_op
== O_constant
6319 && imm_expr
.X_add_number
> -0x8000
6320 && imm_expr
.X_add_number
<= 0x8000)
6322 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6323 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6324 dbl
? "daddiu" : "addiu",
6325 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6328 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6329 macro_build ((char *) NULL
, &icnt
, NULL
,
6330 dbl
? "dsubu" : "subu",
6331 "d,v,t", dreg
, sreg
, AT
);
6352 load_register (&icnt
, AT
, &imm_expr
, 0);
6353 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6358 assert (mips_opts
.isa
< 2);
6359 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6360 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6363 * Is the double cfc1 instruction a bug in the mips assembler;
6364 * or is there a reason for it?
6366 mips_emit_delays (true);
6367 ++mips_opts
.noreorder
;
6368 mips_any_noreorder
= 1;
6369 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6370 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6371 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6372 expr1
.X_add_number
= 3;
6373 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6374 (int) BFD_RELOC_LO16
);
6375 expr1
.X_add_number
= 2;
6376 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6377 (int) BFD_RELOC_LO16
);
6378 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6379 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6380 macro_build ((char *) NULL
, &icnt
, NULL
,
6381 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6382 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6383 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6384 --mips_opts
.noreorder
;
6393 if (offset_expr
.X_add_number
>= 0x7fff)
6394 as_bad (_("operand overflow"));
6395 /* avoid load delay */
6396 if (! target_big_endian
)
6397 offset_expr
.X_add_number
+= 1;
6398 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6399 (int) BFD_RELOC_LO16
, breg
);
6400 if (! target_big_endian
)
6401 offset_expr
.X_add_number
-= 1;
6403 offset_expr
.X_add_number
+= 1;
6404 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6405 (int) BFD_RELOC_LO16
, breg
);
6406 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6407 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6420 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6421 as_bad (_("operand overflow"));
6422 if (! target_big_endian
)
6423 offset_expr
.X_add_number
+= off
;
6424 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6425 (int) BFD_RELOC_LO16
, breg
);
6426 if (! target_big_endian
)
6427 offset_expr
.X_add_number
-= off
;
6429 offset_expr
.X_add_number
+= off
;
6430 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6431 (int) BFD_RELOC_LO16
, breg
);
6444 load_address (&icnt
, AT
, &offset_expr
);
6446 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6447 ((bfd_arch_bits_per_address (stdoutput
) == 32
6448 || mips_opts
.isa
< 3)
6449 ? "addu" : "daddu"),
6450 "d,v,t", AT
, AT
, breg
);
6451 if (! target_big_endian
)
6452 expr1
.X_add_number
= off
;
6454 expr1
.X_add_number
= 0;
6455 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6456 (int) BFD_RELOC_LO16
, AT
);
6457 if (! target_big_endian
)
6458 expr1
.X_add_number
= 0;
6460 expr1
.X_add_number
= off
;
6461 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6462 (int) BFD_RELOC_LO16
, AT
);
6467 load_address (&icnt
, AT
, &offset_expr
);
6469 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6470 ((bfd_arch_bits_per_address (stdoutput
) == 32
6471 || mips_opts
.isa
< 3)
6472 ? "addu" : "daddu"),
6473 "d,v,t", AT
, AT
, breg
);
6474 if (target_big_endian
)
6475 expr1
.X_add_number
= 0;
6476 macro_build ((char *) NULL
, &icnt
, &expr1
,
6477 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6478 (int) BFD_RELOC_LO16
, AT
);
6479 if (target_big_endian
)
6480 expr1
.X_add_number
= 1;
6482 expr1
.X_add_number
= 0;
6483 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6484 (int) BFD_RELOC_LO16
, AT
);
6485 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6487 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6492 if (offset_expr
.X_add_number
>= 0x7fff)
6493 as_bad (_("operand overflow"));
6494 if (target_big_endian
)
6495 offset_expr
.X_add_number
+= 1;
6496 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6497 (int) BFD_RELOC_LO16
, breg
);
6498 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6499 if (target_big_endian
)
6500 offset_expr
.X_add_number
-= 1;
6502 offset_expr
.X_add_number
+= 1;
6503 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6504 (int) BFD_RELOC_LO16
, breg
);
6517 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6518 as_bad (_("operand overflow"));
6519 if (! target_big_endian
)
6520 offset_expr
.X_add_number
+= off
;
6521 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6522 (int) BFD_RELOC_LO16
, breg
);
6523 if (! target_big_endian
)
6524 offset_expr
.X_add_number
-= off
;
6526 offset_expr
.X_add_number
+= off
;
6527 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6528 (int) BFD_RELOC_LO16
, breg
);
6541 load_address (&icnt
, AT
, &offset_expr
);
6543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6544 ((bfd_arch_bits_per_address (stdoutput
) == 32
6545 || mips_opts
.isa
< 3)
6546 ? "addu" : "daddu"),
6547 "d,v,t", AT
, AT
, breg
);
6548 if (! target_big_endian
)
6549 expr1
.X_add_number
= off
;
6551 expr1
.X_add_number
= 0;
6552 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6553 (int) BFD_RELOC_LO16
, AT
);
6554 if (! target_big_endian
)
6555 expr1
.X_add_number
= 0;
6557 expr1
.X_add_number
= off
;
6558 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6559 (int) BFD_RELOC_LO16
, AT
);
6563 load_address (&icnt
, AT
, &offset_expr
);
6565 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6566 ((bfd_arch_bits_per_address (stdoutput
) == 32
6567 || mips_opts
.isa
< 3)
6568 ? "addu" : "daddu"),
6569 "d,v,t", AT
, AT
, breg
);
6570 if (! target_big_endian
)
6571 expr1
.X_add_number
= 0;
6572 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6573 (int) BFD_RELOC_LO16
, AT
);
6574 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6576 if (! target_big_endian
)
6577 expr1
.X_add_number
= 1;
6579 expr1
.X_add_number
= 0;
6580 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6581 (int) BFD_RELOC_LO16
, AT
);
6582 if (! target_big_endian
)
6583 expr1
.X_add_number
= 0;
6585 expr1
.X_add_number
= 1;
6586 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6587 (int) BFD_RELOC_LO16
, AT
);
6588 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6590 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6595 /* FIXME: Check if this is one of the itbl macros, since they
6596 are added dynamically. */
6597 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6601 as_warn (_("Macro used $at after \".set noat\""));
6604 /* Implement macros in mips16 mode. */
6608 struct mips_cl_insn
*ip
;
6611 int xreg
, yreg
, zreg
, tmp
;
6615 const char *s
, *s2
, *s3
;
6617 mask
= ip
->insn_mo
->mask
;
6619 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6620 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6621 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6625 expr1
.X_op
= O_constant
;
6626 expr1
.X_op_symbol
= NULL
;
6627 expr1
.X_add_symbol
= NULL
;
6628 expr1
.X_add_number
= 1;
6647 mips_emit_delays (true);
6648 ++mips_opts
.noreorder
;
6649 mips_any_noreorder
= 1;
6650 macro_build ((char *) NULL
, &icnt
, NULL
,
6651 dbl
? "ddiv" : "div",
6652 "0,x,y", xreg
, yreg
);
6653 expr1
.X_add_number
= 2;
6654 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6655 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6657 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6658 since that causes an overflow. We should do that as well,
6659 but I don't see how to do the comparisons without a temporary
6661 --mips_opts
.noreorder
;
6662 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6681 mips_emit_delays (true);
6682 ++mips_opts
.noreorder
;
6683 mips_any_noreorder
= 1;
6684 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6685 expr1
.X_add_number
= 2;
6686 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6687 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6688 --mips_opts
.noreorder
;
6689 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6695 macro_build ((char *) NULL
, &icnt
, NULL
,
6696 dbl
? "dmultu" : "multu",
6698 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6706 if (imm_expr
.X_op
!= O_constant
)
6707 as_bad (_("Unsupported large constant"));
6708 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6709 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6710 dbl
? "daddiu" : "addiu",
6711 "y,x,4", yreg
, xreg
);
6715 if (imm_expr
.X_op
!= O_constant
)
6716 as_bad (_("Unsupported large constant"));
6717 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6718 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6723 if (imm_expr
.X_op
!= O_constant
)
6724 as_bad (_("Unsupported large constant"));
6725 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6726 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6749 goto do_reverse_branch
;
6753 goto do_reverse_branch
;
6765 goto do_reverse_branch
;
6776 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6778 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6805 goto do_addone_branch_i
;
6810 goto do_addone_branch_i
;
6825 goto do_addone_branch_i
;
6832 if (imm_expr
.X_op
!= O_constant
)
6833 as_bad (_("Unsupported large constant"));
6834 ++imm_expr
.X_add_number
;
6837 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6838 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6842 expr1
.X_add_number
= 0;
6843 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6845 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6846 "move", "y,X", xreg
, yreg
);
6847 expr1
.X_add_number
= 2;
6848 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6849 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6850 "neg", "x,w", xreg
, xreg
);
6854 /* For consistency checking, verify that all bits are specified either
6855 by the match/mask part of the instruction definition, or by the
6858 validate_mips_insn (opc
)
6859 const struct mips_opcode
*opc
;
6861 const char *p
= opc
->args
;
6863 unsigned long used_bits
= opc
->mask
;
6865 if ((used_bits
& opc
->match
) != opc
->match
)
6867 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6868 opc
->name
, opc
->args
);
6871 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6878 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6879 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6881 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6882 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6883 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6884 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6886 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6889 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6890 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6891 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6892 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6893 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6894 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6895 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6896 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6897 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6898 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6899 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6901 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6902 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6903 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6904 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6906 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6907 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6908 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6909 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6910 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6911 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6912 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6913 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6914 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6917 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6919 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6920 c
, opc
->name
, opc
->args
);
6924 if (used_bits
!= 0xffffffff)
6926 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6927 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6933 /* This routine assembles an instruction into its binary format. As a
6934 side effect, it sets one of the global variables imm_reloc or
6935 offset_reloc to the type of relocation to do if one of the operands
6936 is an address expression. */
6941 struct mips_cl_insn
*ip
;
6946 struct mips_opcode
*insn
;
6949 unsigned int lastregno
= 0;
6952 int full_opcode_match
= 1;
6956 /* If the instruction contains a '.', we first try to match an instruction
6957 including the '.'. Then we try again without the '.'. */
6959 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6962 /* If we stopped on whitespace, then replace the whitespace with null for
6963 the call to hash_find. Save the character we replaced just in case we
6964 have to re-parse the instruction. */
6971 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
6973 /* If we didn't find the instruction in the opcode table, try again, but
6974 this time with just the instruction up to, but not including the
6978 /* Restore the character we overwrite above (if any). */
6982 /* Scan up to the first '.' or whitespace. */
6983 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace (*s
); ++s
)
6986 /* If we did not find a '.', then we can quit now. */
6989 insn_error
= "unrecognized opcode";
6993 /* Lookup the instruction in the hash table. */
6995 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6997 insn_error
= "unrecognized opcode";
7001 full_opcode_match
= 0;
7010 assert (strcmp (insn
->name
, str
) == 0);
7012 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
7014 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
7016 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
7018 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7023 if (insn_isa
<= mips_opts
.isa
)
7025 else if (insn
->pinfo
== INSN_MACRO
)
7027 else if ((mips_cpu
== 4650 && (insn
->membership
& INSN_4650
) != 0)
7028 || (mips_cpu
== 4010 && (insn
->membership
& INSN_4010
) != 0)
7029 || ((mips_cpu
== 4100
7032 && (insn
->membership
& INSN_4100
) != 0)
7033 || (mips_cpu
== 3900 && (insn
->membership
& INSN_3900
) != 0))
7038 if (insn
->pinfo
!= INSN_MACRO
)
7040 if (mips_cpu
== 4650 && (insn
->pinfo
& FP_D
) != 0)
7046 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7047 && strcmp (insn
->name
, insn
[1].name
) == 0)
7053 || insn_isa
<= mips_opts
.isa
)
7054 insn_error
= _("opcode not supported on this processor");
7057 static char buf
[100];
7059 sprintf (buf
, _("opcode requires -mips%d or greater"), insn_isa
);
7066 ip
->insn_opcode
= insn
->match
;
7067 for (args
= insn
->args
;; ++args
)
7073 case '\0': /* end of args */
7086 ip
->insn_opcode
|= lastregno
<< 21;
7091 ip
->insn_opcode
|= lastregno
<< 16;
7095 ip
->insn_opcode
|= lastregno
<< 11;
7101 /* Handle optional base register.
7102 Either the base register is omitted or
7103 we must have a left paren. */
7104 /* This is dependent on the next operand specifier
7105 is a base register specification. */
7106 assert (args
[1] == 'b' || args
[1] == '5'
7107 || args
[1] == '-' || args
[1] == '4');
7111 case ')': /* these must match exactly */
7116 case '<': /* must be at least one digit */
7118 * According to the manual, if the shift amount is greater
7119 * than 31 or less than 0 the the shift amount should be
7120 * mod 32. In reality the mips assembler issues an error.
7121 * We issue a warning and mask out all but the low 5 bits.
7123 my_getExpression (&imm_expr
, s
);
7124 check_absolute_expr (ip
, &imm_expr
);
7125 if ((unsigned long) imm_expr
.X_add_number
> 31)
7127 as_warn (_("Improper shift amount (%ld)"),
7128 (long) imm_expr
.X_add_number
);
7129 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7131 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7132 imm_expr
.X_op
= O_absent
;
7136 case '>': /* shift amount minus 32 */
7137 my_getExpression (&imm_expr
, s
);
7138 check_absolute_expr (ip
, &imm_expr
);
7139 if ((unsigned long) imm_expr
.X_add_number
< 32
7140 || (unsigned long) imm_expr
.X_add_number
> 63)
7142 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7143 imm_expr
.X_op
= O_absent
;
7148 case 'k': /* cache code */
7149 case 'h': /* prefx code */
7150 my_getExpression (&imm_expr
, s
);
7151 check_absolute_expr (ip
, &imm_expr
);
7152 if ((unsigned long) imm_expr
.X_add_number
> 31)
7154 as_warn (_("Invalid value for `%s' (%lu)"),
7156 (unsigned long) imm_expr
.X_add_number
);
7157 imm_expr
.X_add_number
&= 0x1f;
7160 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7162 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7163 imm_expr
.X_op
= O_absent
;
7167 case 'c': /* break code */
7168 my_getExpression (&imm_expr
, s
);
7169 check_absolute_expr (ip
, &imm_expr
);
7170 if ((unsigned) imm_expr
.X_add_number
> 1023)
7172 as_warn (_("Illegal break code (%ld)"),
7173 (long) imm_expr
.X_add_number
);
7174 imm_expr
.X_add_number
&= 0x3ff;
7176 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7177 imm_expr
.X_op
= O_absent
;
7181 case 'q': /* lower break code */
7182 my_getExpression (&imm_expr
, s
);
7183 check_absolute_expr (ip
, &imm_expr
);
7184 if ((unsigned) imm_expr
.X_add_number
> 1023)
7186 as_warn (_("Illegal lower break code (%ld)"),
7187 (long) imm_expr
.X_add_number
);
7188 imm_expr
.X_add_number
&= 0x3ff;
7190 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7191 imm_expr
.X_op
= O_absent
;
7195 case 'B': /* syscall code */
7196 my_getExpression (&imm_expr
, s
);
7197 check_absolute_expr (ip
, &imm_expr
);
7198 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7199 as_warn (_("Illegal syscall code (%ld)"),
7200 (long) imm_expr
.X_add_number
);
7201 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7202 imm_expr
.X_op
= O_absent
;
7206 case 'C': /* Coprocessor code */
7207 my_getExpression (&imm_expr
, s
);
7208 check_absolute_expr (ip
, &imm_expr
);
7209 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7211 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7212 (long) imm_expr
.X_add_number
);
7213 imm_expr
.X_add_number
&= ((1<<25) - 1);
7215 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7216 imm_expr
.X_op
= O_absent
;
7220 case 'P': /* Performance register */
7221 my_getExpression (&imm_expr
, s
);
7222 check_absolute_expr (ip
, &imm_expr
);
7223 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7225 as_warn (_("Invalidate performance regster (%ld)"),
7226 (long) imm_expr
.X_add_number
);
7227 imm_expr
.X_add_number
&= 1;
7229 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7230 imm_expr
.X_op
= O_absent
;
7234 case 'b': /* base register */
7235 case 'd': /* destination register */
7236 case 's': /* source register */
7237 case 't': /* target register */
7238 case 'r': /* both target and source */
7239 case 'v': /* both dest and source */
7240 case 'w': /* both dest and target */
7241 case 'E': /* coprocessor target register */
7242 case 'G': /* coprocessor destination register */
7243 case 'x': /* ignore register name */
7244 case 'z': /* must be zero register */
7259 while (isdigit (*s
));
7261 as_bad (_("Invalid register number (%d)"), regno
);
7263 else if (*args
== 'E' || *args
== 'G')
7267 if (s
[1] == 'f' && s
[2] == 'p')
7272 else if (s
[1] == 's' && s
[2] == 'p')
7277 else if (s
[1] == 'g' && s
[2] == 'p')
7282 else if (s
[1] == 'a' && s
[2] == 't')
7287 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7292 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7297 else if (itbl_have_entries
)
7302 p
= s
+1; /* advance past '$' */
7303 n
= itbl_get_field (&p
); /* n is name */
7305 /* See if this is a register defined in an
7307 r
= itbl_get_reg_val (n
);
7310 /* Get_field advances to the start of
7311 the next field, so we need to back
7312 rack to the end of the last field. */
7316 s
= strchr (s
,'\0');
7329 as_warn (_("Used $at without \".set noat\""));
7335 if (c
== 'r' || c
== 'v' || c
== 'w')
7342 /* 'z' only matches $0. */
7343 if (c
== 'z' && regno
!= 0)
7346 /* Now that we have assembled one operand, we use the args string
7347 * to figure out where it goes in the instruction. */
7354 ip
->insn_opcode
|= regno
<< 21;
7358 ip
->insn_opcode
|= regno
<< 11;
7363 ip
->insn_opcode
|= regno
<< 16;
7366 /* This case exists because on the r3000 trunc
7367 expands into a macro which requires a gp
7368 register. On the r6000 or r4000 it is
7369 assembled into a single instruction which
7370 ignores the register. Thus the insn version
7371 is MIPS_ISA2 and uses 'x', and the macro
7372 version is MIPS_ISA1 and uses 't'. */
7375 /* This case is for the div instruction, which
7376 acts differently if the destination argument
7377 is $0. This only matches $0, and is checked
7378 outside the switch. */
7381 /* Itbl operand; not yet implemented. FIXME ?? */
7383 /* What about all other operands like 'i', which
7384 can be specified in the opcode table? */
7394 ip
->insn_opcode
|= lastregno
<< 21;
7397 ip
->insn_opcode
|= lastregno
<< 16;
7402 case 'D': /* floating point destination register */
7403 case 'S': /* floating point source register */
7404 case 'T': /* floating point target register */
7405 case 'R': /* floating point source register */
7409 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7419 while (isdigit (*s
));
7422 as_bad (_("Invalid float register number (%d)"), regno
);
7424 if ((regno
& 1) != 0
7425 && mips_opts
.isa
< 3
7426 && ! (strcmp (str
, "mtc1") == 0
7427 || strcmp (str
, "mfc1") == 0
7428 || strcmp (str
, "lwc1") == 0
7429 || strcmp (str
, "swc1") == 0
7430 || strcmp (str
, "l.s") == 0
7431 || strcmp (str
, "s.s") == 0))
7432 as_warn (_("Float register should be even, was %d"),
7440 if (c
== 'V' || c
== 'W')
7450 ip
->insn_opcode
|= regno
<< 6;
7454 ip
->insn_opcode
|= regno
<< 11;
7458 ip
->insn_opcode
|= regno
<< 16;
7461 ip
->insn_opcode
|= regno
<< 21;
7472 ip
->insn_opcode
|= lastregno
<< 11;
7475 ip
->insn_opcode
|= lastregno
<< 16;
7481 my_getExpression (&imm_expr
, s
);
7482 if (imm_expr
.X_op
!= O_big
7483 && imm_expr
.X_op
!= O_constant
)
7484 insn_error
= _("absolute expression required");
7489 my_getExpression (&offset_expr
, s
);
7490 imm_reloc
= BFD_RELOC_32
;
7502 unsigned char temp
[8];
7504 unsigned int length
;
7509 /* These only appear as the last operand in an
7510 instruction, and every instruction that accepts
7511 them in any variant accepts them in all variants.
7512 This means we don't have to worry about backing out
7513 any changes if the instruction does not match.
7515 The difference between them is the size of the
7516 floating point constant and where it goes. For 'F'
7517 and 'L' the constant is 64 bits; for 'f' and 'l' it
7518 is 32 bits. Where the constant is placed is based
7519 on how the MIPS assembler does things:
7522 f -- immediate value
7525 The .lit4 and .lit8 sections are only used if
7526 permitted by the -G argument.
7528 When generating embedded PIC code, we use the
7529 .lit8 section but not the .lit4 section (we can do
7530 .lit4 inline easily; we need to put .lit8
7531 somewhere in the data segment, and using .lit8
7532 permits the linker to eventually combine identical
7535 f64
= *args
== 'F' || *args
== 'L';
7537 save_in
= input_line_pointer
;
7538 input_line_pointer
= s
;
7539 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7541 s
= input_line_pointer
;
7542 input_line_pointer
= save_in
;
7543 if (err
!= NULL
&& *err
!= '\0')
7545 as_bad (_("Bad floating point constant: %s"), err
);
7546 memset (temp
, '\0', sizeof temp
);
7547 length
= f64
? 8 : 4;
7550 assert (length
== (f64
? 8 : 4));
7554 && (! USE_GLOBAL_POINTER_OPT
7555 || mips_pic
== EMBEDDED_PIC
7556 || g_switch_value
< 4
7557 || (temp
[0] == 0 && temp
[1] == 0)
7558 || (temp
[2] == 0 && temp
[3] == 0))))
7560 imm_expr
.X_op
= O_constant
;
7561 if (! target_big_endian
)
7562 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7564 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7567 && ((temp
[0] == 0 && temp
[1] == 0)
7568 || (temp
[2] == 0 && temp
[3] == 0))
7569 && ((temp
[4] == 0 && temp
[5] == 0)
7570 || (temp
[6] == 0 && temp
[7] == 0)))
7572 /* The value is simple enough to load with a
7573 couple of instructions. In mips1 mode, set
7574 imm_expr to the high order 32 bits and
7575 offset_expr to the low order 32 bits.
7576 Otherwise, set imm_expr to the entire 64 bit
7578 if (mips_opts
.isa
< 3)
7580 imm_expr
.X_op
= O_constant
;
7581 offset_expr
.X_op
= O_constant
;
7582 if (! target_big_endian
)
7584 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7585 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7589 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7590 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7592 if (offset_expr
.X_add_number
== 0)
7593 offset_expr
.X_op
= O_absent
;
7595 else if (sizeof (imm_expr
.X_add_number
) > 4)
7597 imm_expr
.X_op
= O_constant
;
7598 if (! target_big_endian
)
7599 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7601 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7605 imm_expr
.X_op
= O_big
;
7606 imm_expr
.X_add_number
= 4;
7607 if (! target_big_endian
)
7609 generic_bignum
[0] = bfd_getl16 (temp
);
7610 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7611 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7612 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7616 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7617 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7618 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7619 generic_bignum
[3] = bfd_getb16 (temp
);
7625 const char *newname
;
7628 /* Switch to the right section. */
7630 subseg
= now_subseg
;
7633 default: /* unused default case avoids warnings. */
7635 newname
= RDATA_SECTION_NAME
;
7636 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7640 newname
= RDATA_SECTION_NAME
;
7643 assert (!USE_GLOBAL_POINTER_OPT
7644 || g_switch_value
>= 4);
7648 new_seg
= subseg_new (newname
, (subsegT
) 0);
7649 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7650 bfd_set_section_flags (stdoutput
, new_seg
,
7655 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7656 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7657 && strcmp (TARGET_OS
, "elf") != 0)
7658 record_alignment (new_seg
, 4);
7660 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7662 as_bad (_("Can't use floating point insn in this section"));
7664 /* Set the argument to the current address in the
7666 offset_expr
.X_op
= O_symbol
;
7667 offset_expr
.X_add_symbol
=
7668 symbol_new ("L0\001", now_seg
,
7669 (valueT
) frag_now_fix (), frag_now
);
7670 offset_expr
.X_add_number
= 0;
7672 /* Put the floating point number into the section. */
7673 p
= frag_more ((int) length
);
7674 memcpy (p
, temp
, length
);
7676 /* Switch back to the original section. */
7677 subseg_set (seg
, subseg
);
7682 case 'i': /* 16 bit unsigned immediate */
7683 case 'j': /* 16 bit signed immediate */
7684 imm_reloc
= BFD_RELOC_LO16
;
7685 c
= my_getSmallExpression (&imm_expr
, s
);
7690 if (imm_expr
.X_op
== O_constant
)
7691 imm_expr
.X_add_number
=
7692 (imm_expr
.X_add_number
>> 16) & 0xffff;
7695 imm_reloc
= BFD_RELOC_HI16_S
;
7696 imm_unmatched_hi
= true;
7699 imm_reloc
= BFD_RELOC_HI16
;
7701 else if (imm_expr
.X_op
== O_constant
)
7702 imm_expr
.X_add_number
&= 0xffff;
7706 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7707 || ((imm_expr
.X_add_number
< 0
7708 || imm_expr
.X_add_number
>= 0x10000)
7709 && imm_expr
.X_op
== O_constant
))
7711 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7712 !strcmp (insn
->name
, insn
[1].name
))
7714 if (imm_expr
.X_op
!= O_constant
7715 && imm_expr
.X_op
!= O_big
)
7716 insn_error
= _("absolute expression required");
7718 as_bad (_("16 bit expression not in range 0..65535"));
7726 /* The upper bound should be 0x8000, but
7727 unfortunately the MIPS assembler accepts numbers
7728 from 0x8000 to 0xffff and sign extends them, and
7729 we want to be compatible. We only permit this
7730 extended range for an instruction which does not
7731 provide any further alternates, since those
7732 alternates may handle other cases. People should
7733 use the numbers they mean, rather than relying on
7734 a mysterious sign extension. */
7735 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7736 strcmp (insn
->name
, insn
[1].name
) == 0);
7741 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7742 || ((imm_expr
.X_add_number
< -0x8000
7743 || imm_expr
.X_add_number
>= max
)
7744 && imm_expr
.X_op
== O_constant
)
7746 && imm_expr
.X_add_number
< 0
7747 && mips_opts
.isa
>= 3
7748 && imm_expr
.X_unsigned
7749 && sizeof (imm_expr
.X_add_number
) <= 4))
7753 if (imm_expr
.X_op
!= O_constant
7754 && imm_expr
.X_op
!= O_big
)
7755 insn_error
= _("absolute expression required");
7757 as_bad (_("16 bit expression not in range -32768..32767"));
7763 case 'o': /* 16 bit offset */
7764 c
= my_getSmallExpression (&offset_expr
, s
);
7766 /* If this value won't fit into a 16 bit offset, then go
7767 find a macro that will generate the 32 bit offset
7768 code pattern. As a special hack, we accept the
7769 difference of two local symbols as a constant. This
7770 is required to suppose embedded PIC switches, which
7771 use an instruction which looks like
7772 lw $4,$L12-$LS12($4)
7773 The problem with handling this in a more general
7774 fashion is that the macro function doesn't expect to
7775 see anything which can be handled in a single
7776 constant instruction. */
7778 && (offset_expr
.X_op
!= O_constant
7779 || offset_expr
.X_add_number
>= 0x8000
7780 || offset_expr
.X_add_number
< -0x8000)
7781 && (mips_pic
!= EMBEDDED_PIC
7782 || offset_expr
.X_op
!= O_subtract
7783 || now_seg
!= text_section
7784 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7788 if (c
== 'h' || c
== 'H')
7790 if (offset_expr
.X_op
!= O_constant
)
7792 offset_expr
.X_add_number
=
7793 (offset_expr
.X_add_number
>> 16) & 0xffff;
7795 offset_reloc
= BFD_RELOC_LO16
;
7799 case 'p': /* pc relative offset */
7800 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7801 my_getExpression (&offset_expr
, s
);
7805 case 'u': /* upper 16 bits */
7806 c
= my_getSmallExpression (&imm_expr
, s
);
7807 imm_reloc
= BFD_RELOC_LO16
;
7812 if (imm_expr
.X_op
== O_constant
)
7813 imm_expr
.X_add_number
=
7814 (imm_expr
.X_add_number
>> 16) & 0xffff;
7817 imm_reloc
= BFD_RELOC_HI16_S
;
7818 imm_unmatched_hi
= true;
7821 imm_reloc
= BFD_RELOC_HI16
;
7823 else if (imm_expr
.X_op
== O_constant
)
7824 imm_expr
.X_add_number
&= 0xffff;
7826 if (imm_expr
.X_op
== O_constant
7827 && (imm_expr
.X_add_number
< 0
7828 || imm_expr
.X_add_number
>= 0x10000))
7829 as_bad (_("lui expression not in range 0..65535"));
7833 case 'a': /* 26 bit address */
7834 my_getExpression (&offset_expr
, s
);
7836 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7839 case 'N': /* 3 bit branch condition code */
7840 case 'M': /* 3 bit compare condition code */
7841 if (strncmp (s
, "$fcc", 4) != 0)
7851 while (isdigit (*s
));
7853 as_bad (_("invalid condition code register $fcc%d"), regno
);
7855 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7857 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7861 as_bad (_("bad char = '%c'\n"), *args
);
7866 /* Args don't match. */
7867 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7868 !strcmp (insn
->name
, insn
[1].name
))
7874 insn_error
= _("illegal operands");
7879 /* This routine assembles an instruction into its binary format when
7880 assembling for the mips16. As a side effect, it sets one of the
7881 global variables imm_reloc or offset_reloc to the type of
7882 relocation to do if one of the operands is an address expression.
7883 It also sets mips16_small and mips16_ext if the user explicitly
7884 requested a small or extended instruction. */
7889 struct mips_cl_insn
*ip
;
7893 struct mips_opcode
*insn
;
7896 unsigned int lastregno
= 0;
7901 mips16_small
= false;
7904 for (s
= str
; islower (*s
); ++s
)
7916 if (s
[1] == 't' && s
[2] == ' ')
7919 mips16_small
= true;
7923 else if (s
[1] == 'e' && s
[2] == ' ')
7932 insn_error
= _("unknown opcode");
7936 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7937 mips16_small
= true;
7939 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7941 insn_error
= _("unrecognized opcode");
7948 assert (strcmp (insn
->name
, str
) == 0);
7951 ip
->insn_opcode
= insn
->match
;
7952 ip
->use_extend
= false;
7953 imm_expr
.X_op
= O_absent
;
7954 imm_reloc
= BFD_RELOC_UNUSED
;
7955 offset_expr
.X_op
= O_absent
;
7956 offset_reloc
= BFD_RELOC_UNUSED
;
7957 for (args
= insn
->args
; 1; ++args
)
7964 /* In this switch statement we call break if we did not find
7965 a match, continue if we did find a match, or return if we
7974 /* Stuff the immediate value in now, if we can. */
7975 if (imm_expr
.X_op
== O_constant
7976 && imm_reloc
> BFD_RELOC_UNUSED
7977 && insn
->pinfo
!= INSN_MACRO
)
7979 mips16_immed ((char *) NULL
, 0,
7980 imm_reloc
- BFD_RELOC_UNUSED
,
7981 imm_expr
.X_add_number
, true, mips16_small
,
7982 mips16_ext
, &ip
->insn_opcode
,
7983 &ip
->use_extend
, &ip
->extend
);
7984 imm_expr
.X_op
= O_absent
;
7985 imm_reloc
= BFD_RELOC_UNUSED
;
7999 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8002 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8018 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8020 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8047 while (isdigit (*s
));
8050 as_bad (_("invalid register number (%d)"), regno
);
8056 if (s
[1] == 'f' && s
[2] == 'p')
8061 else if (s
[1] == 's' && s
[2] == 'p')
8066 else if (s
[1] == 'g' && s
[2] == 'p')
8071 else if (s
[1] == 'a' && s
[2] == 't')
8076 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8081 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8094 if (c
== 'v' || c
== 'w')
8096 regno
= mips16_to_32_reg_map
[lastregno
];
8110 regno
= mips32_to_16_reg_map
[regno
];
8115 regno
= ILLEGAL_REG
;
8120 regno
= ILLEGAL_REG
;
8125 regno
= ILLEGAL_REG
;
8130 if (regno
== AT
&& ! mips_opts
.noat
)
8131 as_warn (_("used $at without \".set noat\""));
8138 if (regno
== ILLEGAL_REG
)
8145 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8149 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8152 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8155 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8161 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8164 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8165 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8175 if (strncmp (s
, "$pc", 3) == 0)
8199 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8201 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8202 and generate the appropriate reloc. If the text
8203 inside %gprel is not a symbol name with an
8204 optional offset, then we generate a normal reloc
8205 and will probably fail later. */
8206 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8207 if (imm_expr
.X_op
== O_symbol
)
8210 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8212 ip
->use_extend
= true;
8219 /* Just pick up a normal expression. */
8220 my_getExpression (&imm_expr
, s
);
8223 if (imm_expr
.X_op
== O_register
)
8225 /* What we thought was an expression turned out to
8228 if (s
[0] == '(' && args
[1] == '(')
8230 /* It looks like the expression was omitted
8231 before a register indirection, which means
8232 that the expression is implicitly zero. We
8233 still set up imm_expr, so that we handle
8234 explicit extensions correctly. */
8235 imm_expr
.X_op
= O_constant
;
8236 imm_expr
.X_add_number
= 0;
8237 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8244 /* We need to relax this instruction. */
8245 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8254 /* We use offset_reloc rather than imm_reloc for the PC
8255 relative operands. This lets macros with both
8256 immediate and address operands work correctly. */
8257 my_getExpression (&offset_expr
, s
);
8259 if (offset_expr
.X_op
== O_register
)
8262 /* We need to relax this instruction. */
8263 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8267 case '6': /* break code */
8268 my_getExpression (&imm_expr
, s
);
8269 check_absolute_expr (ip
, &imm_expr
);
8270 if ((unsigned long) imm_expr
.X_add_number
> 63)
8272 as_warn (_("Invalid value for `%s' (%lu)"),
8274 (unsigned long) imm_expr
.X_add_number
);
8275 imm_expr
.X_add_number
&= 0x3f;
8277 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8278 imm_expr
.X_op
= O_absent
;
8282 case 'a': /* 26 bit address */
8283 my_getExpression (&offset_expr
, s
);
8285 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8286 ip
->insn_opcode
<<= 16;
8289 case 'l': /* register list for entry macro */
8290 case 'L': /* register list for exit macro */
8300 int freg
, reg1
, reg2
;
8302 while (*s
== ' ' || *s
== ',')
8306 as_bad (_("can't parse register list"));
8318 while (isdigit (*s
))
8340 as_bad (_("invalid register list"));
8345 while (isdigit (*s
))
8352 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8357 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8362 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8363 mask
|= (reg2
- 3) << 3;
8364 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8365 mask
|= (reg2
- 15) << 1;
8366 else if (reg1
== 31 && reg2
== 31)
8370 as_bad (_("invalid register list"));
8374 /* The mask is filled in in the opcode table for the
8375 benefit of the disassembler. We remove it before
8376 applying the actual mask. */
8377 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8378 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8382 case 'e': /* extend code */
8383 my_getExpression (&imm_expr
, s
);
8384 check_absolute_expr (ip
, &imm_expr
);
8385 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8387 as_warn (_("Invalid value for `%s' (%lu)"),
8389 (unsigned long) imm_expr
.X_add_number
);
8390 imm_expr
.X_add_number
&= 0x7ff;
8392 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8393 imm_expr
.X_op
= O_absent
;
8403 /* Args don't match. */
8404 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8405 strcmp (insn
->name
, insn
[1].name
) == 0)
8412 insn_error
= _("illegal operands");
8418 /* This structure holds information we know about a mips16 immediate
8421 struct mips16_immed_operand
8423 /* The type code used in the argument string in the opcode table. */
8425 /* The number of bits in the short form of the opcode. */
8427 /* The number of bits in the extended form of the opcode. */
8429 /* The amount by which the short form is shifted when it is used;
8430 for example, the sw instruction has a shift count of 2. */
8432 /* The amount by which the short form is shifted when it is stored
8433 into the instruction code. */
8435 /* Non-zero if the short form is unsigned. */
8437 /* Non-zero if the extended form is unsigned. */
8439 /* Non-zero if the value is PC relative. */
8443 /* The mips16 immediate operand types. */
8445 static const struct mips16_immed_operand mips16_immed_operands
[] =
8447 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8448 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8449 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8450 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8451 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8452 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8453 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8454 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8455 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8456 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8457 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8458 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8459 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8460 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8461 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8462 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8463 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8464 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8465 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8466 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8467 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8470 #define MIPS16_NUM_IMMED \
8471 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8473 /* Handle a mips16 instruction with an immediate value. This or's the
8474 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8475 whether an extended value is needed; if one is needed, it sets
8476 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8477 If SMALL is true, an unextended opcode was explicitly requested.
8478 If EXT is true, an extended opcode was explicitly requested. If
8479 WARN is true, warn if EXT does not match reality. */
8482 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8491 unsigned long *insn
;
8492 boolean
*use_extend
;
8493 unsigned short *extend
;
8495 register const struct mips16_immed_operand
*op
;
8496 int mintiny
, maxtiny
;
8499 op
= mips16_immed_operands
;
8500 while (op
->type
!= type
)
8503 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8508 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8511 maxtiny
= 1 << op
->nbits
;
8516 maxtiny
= (1 << op
->nbits
) - 1;
8521 mintiny
= - (1 << (op
->nbits
- 1));
8522 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8525 /* Branch offsets have an implicit 0 in the lowest bit. */
8526 if (type
== 'p' || type
== 'q')
8529 if ((val
& ((1 << op
->shift
) - 1)) != 0
8530 || val
< (mintiny
<< op
->shift
)
8531 || val
> (maxtiny
<< op
->shift
))
8536 if (warn
&& ext
&& ! needext
)
8537 as_warn_where (file
, line
, _("extended operand requested but not required"));
8538 if (small
&& needext
)
8539 as_bad_where (file
, line
, _("invalid unextended operand value"));
8541 if (small
|| (! ext
&& ! needext
))
8545 *use_extend
= false;
8546 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8547 insnval
<<= op
->op_shift
;
8552 long minext
, maxext
;
8558 maxext
= (1 << op
->extbits
) - 1;
8562 minext
= - (1 << (op
->extbits
- 1));
8563 maxext
= (1 << (op
->extbits
- 1)) - 1;
8565 if (val
< minext
|| val
> maxext
)
8566 as_bad_where (file
, line
,
8567 _("operand value out of range for instruction"));
8570 if (op
->extbits
== 16)
8572 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8575 else if (op
->extbits
== 15)
8577 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8582 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8586 *extend
= (unsigned short) extval
;
8595 my_getSmallExpression (ep
, str
)
8606 ((str
[1] == 'h' && str
[2] == 'i')
8607 || (str
[1] == 'H' && str
[2] == 'I')
8608 || (str
[1] == 'l' && str
[2] == 'o'))
8620 * A small expression may be followed by a base register.
8621 * Scan to the end of this operand, and then back over a possible
8622 * base register. Then scan the small expression up to that
8623 * point. (Based on code in sparc.c...)
8625 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8627 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8629 if (isdigit (sp
[-2]))
8631 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8633 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8639 else if (sp
- 5 >= str
8642 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8643 || (sp
[-3] == 's' && sp
[-2] == 'p')
8644 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8645 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8651 /* no expression means zero offset */
8654 /* %xx(reg) is an error */
8655 ep
->X_op
= O_absent
;
8660 ep
->X_op
= O_constant
;
8663 ep
->X_add_symbol
= NULL
;
8664 ep
->X_op_symbol
= NULL
;
8665 ep
->X_add_number
= 0;
8670 my_getExpression (ep
, str
);
8677 my_getExpression (ep
, str
);
8678 return c
; /* => %hi or %lo encountered */
8682 my_getExpression (ep
, str
)
8688 save_in
= input_line_pointer
;
8689 input_line_pointer
= str
;
8691 expr_end
= input_line_pointer
;
8692 input_line_pointer
= save_in
;
8694 /* If we are in mips16 mode, and this is an expression based on `.',
8695 then we bump the value of the symbol by 1 since that is how other
8696 text symbols are handled. We don't bother to handle complex
8697 expressions, just `.' plus or minus a constant. */
8698 if (mips_opts
.mips16
8699 && ep
->X_op
== O_symbol
8700 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8701 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8702 && ep
->X_add_symbol
->sy_frag
== frag_now
8703 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8704 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8705 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8708 /* Turn a string in input_line_pointer into a floating point constant
8709 of type type, and store the appropriate bytes in *litP. The number
8710 of LITTLENUMS emitted is stored in *sizeP . An error message is
8711 returned, or NULL on OK. */
8714 md_atof (type
, litP
, sizeP
)
8720 LITTLENUM_TYPE words
[4];
8736 return _("bad call to md_atof");
8739 t
= atof_ieee (input_line_pointer
, type
, words
);
8741 input_line_pointer
= t
;
8745 if (! target_big_endian
)
8747 for (i
= prec
- 1; i
>= 0; i
--)
8749 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8755 for (i
= 0; i
< prec
; i
++)
8757 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8766 md_number_to_chars (buf
, val
, n
)
8771 if (target_big_endian
)
8772 number_to_chars_bigendian (buf
, val
, n
);
8774 number_to_chars_littleendian (buf
, val
, n
);
8777 CONST
char *md_shortopts
= "O::g::G:";
8779 struct option md_longopts
[] = {
8780 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8781 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8782 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8783 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8784 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8785 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8786 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8787 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8788 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8789 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8790 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8791 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8792 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8793 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8794 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8795 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8796 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8797 {"break", no_argument
, NULL
, OPTION_BREAK
},
8798 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8799 #define OPTION_EB (OPTION_MD_BASE + 11)
8800 {"EB", no_argument
, NULL
, OPTION_EB
},
8801 #define OPTION_EL (OPTION_MD_BASE + 12)
8802 {"EL", no_argument
, NULL
, OPTION_EL
},
8803 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8804 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8805 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8806 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8807 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8808 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8809 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8810 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8811 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8812 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8813 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8814 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8815 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8816 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8817 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8818 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8819 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8820 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8821 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8822 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8825 #define OPTION_MABI (OPTION_MD_BASE + 38)
8826 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8828 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8829 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8830 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8831 #define OPTION_32 (OPTION_MD_BASE + 20)
8832 #define OPTION_64 (OPTION_MD_BASE + 21)
8834 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8835 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8836 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8837 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8838 {"32", no_argument
, NULL
, OPTION_32
},
8839 {"64", no_argument
, NULL
, OPTION_64
},
8842 {NULL
, no_argument
, NULL
, 0}
8844 size_t md_longopts_size
= sizeof(md_longopts
);
8847 md_parse_option (c
, arg
)
8862 target_big_endian
= 1;
8866 target_big_endian
= 0;
8870 if (arg
&& arg
[1] == '0')
8880 mips_debug
= atoi (arg
);
8881 /* When the MIPS assembler sees -g or -g2, it does not do
8882 optimizations which limit full symbolic debugging. We take
8883 that to be equivalent to -O0. */
8884 if (mips_debug
== 2)
8908 /* Identify the processor type */
8910 if (strcmp (p
, "default") == 0
8911 || strcmp (p
, "DEFAULT") == 0)
8917 /* We need to cope with the various "vr" prefixes for the 4300
8919 if (*p
== 'v' || *p
== 'V')
8925 if (*p
== 'r' || *p
== 'R')
8932 if (strcmp (p
, "10000") == 0
8933 || strcmp (p
, "10k") == 0
8934 || strcmp (p
, "10K") == 0)
8939 if (strcmp (p
, "2000") == 0
8940 || strcmp (p
, "2k") == 0
8941 || strcmp (p
, "2K") == 0)
8946 if (strcmp (p
, "3000") == 0
8947 || strcmp (p
, "3k") == 0
8948 || strcmp (p
, "3K") == 0)
8950 else if (strcmp (p
, "3900") == 0)
8955 if (strcmp (p
, "4000") == 0
8956 || strcmp (p
, "4k") == 0
8957 || strcmp (p
, "4K") == 0)
8959 else if (strcmp (p
, "4100") == 0)
8961 else if (strcmp (p
, "4111") == 0)
8963 else if (strcmp (p
, "4300") == 0)
8965 else if (strcmp (p
, "4400") == 0)
8967 else if (strcmp (p
, "4600") == 0)
8969 else if (strcmp (p
, "4650") == 0)
8971 else if (strcmp (p
, "4010") == 0)
8976 if (strcmp (p
, "5000") == 0
8977 || strcmp (p
, "5k") == 0
8978 || strcmp (p
, "5K") == 0)
8983 if (strcmp (p
, "6000") == 0
8984 || strcmp (p
, "6k") == 0
8985 || strcmp (p
, "6K") == 0)
8990 if (strcmp (p
, "8000") == 0
8991 || strcmp (p
, "8k") == 0
8992 || strcmp (p
, "8K") == 0)
8997 if (strcmp (p
, "orion") == 0)
9003 && (mips_cpu
!= 4300
9006 && mips_cpu
!= 5000))
9008 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9014 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9025 case OPTION_NO_M4650
:
9032 case OPTION_NO_M4010
:
9039 case OPTION_NO_M4100
:
9047 case OPTION_NO_M3900
:
9051 mips_opts
.mips16
= 1;
9052 mips_no_prev_insn (false);
9055 case OPTION_NO_MIPS16
:
9056 mips_opts
.mips16
= 0;
9057 mips_no_prev_insn (false);
9060 case OPTION_MEMBEDDED_PIC
:
9061 mips_pic
= EMBEDDED_PIC
;
9062 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9064 as_bad (_("-G may not be used with embedded PIC code"));
9067 g_switch_value
= 0x7fffffff;
9070 /* When generating ELF code, we permit -KPIC and -call_shared to
9071 select SVR4_PIC, and -non_shared to select no PIC. This is
9072 intended to be compatible with Irix 5. */
9073 case OPTION_CALL_SHARED
:
9074 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9076 as_bad (_("-call_shared is supported only for ELF format"));
9079 mips_pic
= SVR4_PIC
;
9080 if (g_switch_seen
&& g_switch_value
!= 0)
9082 as_bad (_("-G may not be used with SVR4 PIC code"));
9088 case OPTION_NON_SHARED
:
9089 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9091 as_bad (_("-non_shared is supported only for ELF format"));
9097 /* The -xgot option tells the assembler to use 32 offsets when
9098 accessing the got in SVR4_PIC mode. It is for Irix
9105 if (! USE_GLOBAL_POINTER_OPT
)
9107 as_bad (_("-G is not supported for this configuration"));
9110 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9112 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9116 g_switch_value
= atoi (arg
);
9120 /* The -32 and -64 options tell the assembler to output the 32
9121 bit or the 64 bit MIPS ELF format. */
9128 const char **list
, **l
;
9130 list
= bfd_target_list ();
9131 for (l
= list
; *l
!= NULL
; l
++)
9132 if (strcmp (*l
, "elf64-bigmips") == 0
9133 || strcmp (*l
, "elf64-littlemips") == 0)
9136 as_fatal (_("No compiled in support for 64 bit object file format"));
9144 if (strcmp (arg
,"32") == 0
9145 || strcmp (arg
,"n32") == 0
9146 || strcmp (arg
,"64") == 0
9147 || strcmp (arg
,"o64") == 0
9148 || strcmp (arg
,"eabi") == 0)
9149 mips_abi_string
= arg
;
9161 show (stream
, string
, col_p
, first_p
)
9169 fprintf (stream
, "%24s", "");
9174 fprintf (stream
, ", ");
9178 if (*col_p
+ strlen (string
) > 72)
9180 fprintf (stream
, "\n%24s", "");
9184 fprintf (stream
, "%s", string
);
9185 *col_p
+= strlen (string
);
9192 md_show_usage (stream
)
9197 fprintf(stream
, _("\
9199 -membedded-pic generate embedded position independent code\n\
9200 -EB generate big endian output\n\
9201 -EL generate little endian output\n\
9202 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9203 -G NUM allow referencing objects up to NUM bytes\n\
9204 implicitly with the gp register [default 8]\n"));
9205 fprintf(stream
, _("\
9206 -mips1 generate MIPS ISA I instructions\n\
9207 -mips2 generate MIPS ISA II instructions\n\
9208 -mips3 generate MIPS ISA III instructions\n\
9209 -mips4 generate MIPS ISA IV instructions\n\
9210 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9214 show (stream
, "2000", &column
, &first
);
9215 show (stream
, "3000", &column
, &first
);
9216 show (stream
, "3900", &column
, &first
);
9217 show (stream
, "4000", &column
, &first
);
9218 show (stream
, "4010", &column
, &first
);
9219 show (stream
, "4100", &column
, &first
);
9220 show (stream
, "4111", &column
, &first
);
9221 show (stream
, "4300", &column
, &first
);
9222 show (stream
, "4400", &column
, &first
);
9223 show (stream
, "4600", &column
, &first
);
9224 show (stream
, "4650", &column
, &first
);
9225 show (stream
, "5000", &column
, &first
);
9226 show (stream
, "6000", &column
, &first
);
9227 show (stream
, "8000", &column
, &first
);
9228 show (stream
, "10000", &column
, &first
);
9229 fputc ('\n', stream
);
9231 fprintf (stream
, _("\
9232 -mCPU equivalent to -mcpu=CPU.\n\
9233 -no-mCPU don't generate code specific to CPU.\n\
9234 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9238 show (stream
, "3900", &column
, &first
);
9239 show (stream
, "4010", &column
, &first
);
9240 show (stream
, "4100", &column
, &first
);
9241 show (stream
, "4650", &column
, &first
);
9242 fputc ('\n', stream
);
9244 fprintf(stream
, _("\
9245 -mips16 generate mips16 instructions\n\
9246 -no-mips16 do not generate mips16 instructions\n"));
9247 fprintf(stream
, _("\
9248 -O0 remove unneeded NOPs, do not swap branches\n\
9249 -O remove unneeded NOPs and swap branches\n\
9250 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9251 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9253 fprintf(stream
, _("\
9254 -KPIC, -call_shared generate SVR4 position independent code\n\
9255 -non_shared do not generate position independent code\n\
9256 -xgot assume a 32 bit GOT\n\
9257 -32 create 32 bit object file (default)\n\
9258 -64 create 64 bit object file\n"));
9263 mips_init_after_args ()
9265 /* initialize opcodes */
9266 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9267 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9271 md_pcrel_from (fixP
)
9274 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9275 && fixP
->fx_addsy
!= (symbolS
*) NULL
9276 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9278 /* This makes a branch to an undefined symbol be a branch to the
9279 current location. */
9283 /* return the address of the delay slot */
9284 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9287 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9288 reloc for a cons. We could use the definition there, except that
9289 we want to handle 64 bit relocs specially. */
9292 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9295 unsigned int nbytes
;
9299 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9301 if (nbytes
== 8 && ! mips_64
)
9303 if (target_big_endian
)
9309 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9310 as_bad (_("Unsupported reloc size %d"), nbytes
);
9312 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9315 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9318 /* This is called before the symbol table is processed. In order to
9319 work with gcc when using mips-tfile, we must keep all local labels.
9320 However, in other cases, we want to discard them. If we were
9321 called with -g, but we didn't see any debugging information, it may
9322 mean that gcc is smuggling debugging information through to
9323 mips-tfile, in which case we must generate all local labels. */
9326 mips_frob_file_before_adjust ()
9328 #ifndef NO_ECOFF_DEBUGGING
9331 && ! ecoff_debugging_seen
)
9332 flag_keep_locals
= 1;
9336 /* Sort any unmatched HI16_S relocs so that they immediately precede
9337 the corresponding LO reloc. This is called before md_apply_fix and
9338 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9339 explicit use of the %hi modifier. */
9344 struct mips_hi_fixup
*l
;
9346 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9348 segment_info_type
*seginfo
;
9351 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9353 /* Check quickly whether the next fixup happens to be a matching
9355 if (l
->fixp
->fx_next
!= NULL
9356 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9357 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9358 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9361 /* Look through the fixups for this segment for a matching %lo.
9362 When we find one, move the %hi just in front of it. We do
9363 this in two passes. In the first pass, we try to find a
9364 unique %lo. In the second pass, we permit multiple %hi
9365 relocs for a single %lo (this is a GNU extension). */
9366 seginfo
= seg_info (l
->seg
);
9367 for (pass
= 0; pass
< 2; pass
++)
9372 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9374 /* Check whether this is a %lo fixup which matches l->fixp. */
9375 if (f
->fx_r_type
== BFD_RELOC_LO16
9376 && f
->fx_addsy
== l
->fixp
->fx_addsy
9377 && f
->fx_offset
== l
->fixp
->fx_offset
9380 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9381 || prev
->fx_addsy
!= f
->fx_addsy
9382 || prev
->fx_offset
!= f
->fx_offset
))
9386 /* Move l->fixp before f. */
9387 for (pf
= &seginfo
->fix_root
;
9389 pf
= &(*pf
)->fx_next
)
9390 assert (*pf
!= NULL
);
9392 *pf
= l
->fixp
->fx_next
;
9394 l
->fixp
->fx_next
= f
;
9396 seginfo
->fix_root
= l
->fixp
;
9398 prev
->fx_next
= l
->fixp
;
9409 #if 0 /* GCC code motion plus incomplete dead code elimination
9410 can leave a %hi without a %lo. */
9412 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9413 _("Unmatched %%hi reloc"));
9419 /* When generating embedded PIC code we need to use a special
9420 relocation to represent the difference of two symbols in the .text
9421 section (switch tables use a difference of this sort). See
9422 include/coff/mips.h for details. This macro checks whether this
9423 fixup requires the special reloc. */
9424 #define SWITCH_TABLE(fixp) \
9425 ((fixp)->fx_r_type == BFD_RELOC_32 \
9426 && (fixp)->fx_addsy != NULL \
9427 && (fixp)->fx_subsy != NULL \
9428 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9429 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9431 /* When generating embedded PIC code we must keep all PC relative
9432 relocations, in case the linker has to relax a call. We also need
9433 to keep relocations for switch table entries. */
9437 mips_force_relocation (fixp
)
9440 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9441 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9444 return (mips_pic
== EMBEDDED_PIC
9446 || SWITCH_TABLE (fixp
)
9447 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9448 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9451 /* Apply a fixup to the object file. */
9454 md_apply_fix (fixP
, valueP
)
9461 assert (fixP
->fx_size
== 4
9462 || fixP
->fx_r_type
== BFD_RELOC_16
9463 || fixP
->fx_r_type
== BFD_RELOC_64
9464 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9465 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9469 /* If we aren't adjusting this fixup to be against the section
9470 symbol, we need to adjust the value. */
9472 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9473 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9474 || S_IS_WEAK (fixP
->fx_addsy
)
9475 || (fixP
->fx_addsy
->sy_used_in_reloc
9476 && (bfd_get_section_flags (stdoutput
,
9477 S_GET_SEGMENT (fixP
->fx_addsy
))
9478 & SEC_LINK_ONCE
!= 0)
9479 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9481 sizeof (".gnu.linkonce") - 1)))
9484 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9485 if (value
!= 0 && ! fixP
->fx_pcrel
)
9487 /* In this case, the bfd_install_relocation routine will
9488 incorrectly add the symbol value back in. We just want
9489 the addend to appear in the object file. */
9490 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9496 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9498 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9501 switch (fixP
->fx_r_type
)
9503 case BFD_RELOC_MIPS_JMP
:
9504 case BFD_RELOC_HI16
:
9505 case BFD_RELOC_HI16_S
:
9506 case BFD_RELOC_MIPS_GPREL
:
9507 case BFD_RELOC_MIPS_LITERAL
:
9508 case BFD_RELOC_MIPS_CALL16
:
9509 case BFD_RELOC_MIPS_GOT16
:
9510 case BFD_RELOC_MIPS_GPREL32
:
9511 case BFD_RELOC_MIPS_GOT_HI16
:
9512 case BFD_RELOC_MIPS_GOT_LO16
:
9513 case BFD_RELOC_MIPS_CALL_HI16
:
9514 case BFD_RELOC_MIPS_CALL_LO16
:
9515 case BFD_RELOC_MIPS16_GPREL
:
9517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9518 _("Invalid PC relative reloc"));
9519 /* Nothing needed to do. The value comes from the reloc entry */
9522 case BFD_RELOC_MIPS16_JMP
:
9523 /* We currently always generate a reloc against a symbol, which
9524 means that we don't want an addend even if the symbol is
9526 fixP
->fx_addnumber
= 0;
9529 case BFD_RELOC_PCREL_HI16_S
:
9530 /* The addend for this is tricky if it is internal, so we just
9531 do everything here rather than in bfd_install_relocation. */
9532 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9534 /* For an external symbol adjust by the address to make it
9535 pcrel_offset. We use the address of the RELLO reloc
9536 which follows this one. */
9537 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9538 + fixP
->fx_next
->fx_where
);
9543 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9544 if (target_big_endian
)
9546 md_number_to_chars (buf
, value
, 2);
9549 case BFD_RELOC_PCREL_LO16
:
9550 /* The addend for this is tricky if it is internal, so we just
9551 do everything here rather than in bfd_install_relocation. */
9552 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9553 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9554 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9555 if (target_big_endian
)
9557 md_number_to_chars (buf
, value
, 2);
9561 /* This is handled like BFD_RELOC_32, but we output a sign
9562 extended value if we are only 32 bits. */
9564 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9566 if (8 <= sizeof (valueT
))
9567 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9574 w1
= w2
= fixP
->fx_where
;
9575 if (target_big_endian
)
9579 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9580 if ((value
& 0x80000000) != 0)
9584 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9590 /* If we are deleting this reloc entry, we must fill in the
9591 value now. This can happen if we have a .word which is not
9592 resolved when it appears but is later defined. We also need
9593 to fill in the value if this is an embedded PIC switch table
9596 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9597 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9602 /* If we are deleting this reloc entry, we must fill in the
9604 assert (fixP
->fx_size
== 2);
9606 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9610 case BFD_RELOC_LO16
:
9611 /* When handling an embedded PIC switch statement, we can wind
9612 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9615 if (value
< -0x8000 || value
> 0x7fff)
9616 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9617 _("relocation overflow"));
9618 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9619 if (target_big_endian
)
9621 md_number_to_chars (buf
, value
, 2);
9625 case BFD_RELOC_16_PCREL_S2
:
9627 * We need to save the bits in the instruction since fixup_segment()
9628 * might be deleting the relocation entry (i.e., a branch within
9629 * the current segment).
9631 if ((value
& 0x3) != 0)
9632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9633 _("Branch to odd address (%lx)"), value
);
9636 /* update old instruction data */
9637 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9638 if (target_big_endian
)
9639 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9641 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9643 if (value
>= -0x8000 && value
< 0x8000)
9644 insn
|= value
& 0xffff;
9647 /* The branch offset is too large. If this is an
9648 unconditional branch, and we are not generating PIC code,
9649 we can convert it to an absolute jump instruction. */
9650 if (mips_pic
== NO_PIC
9652 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9653 && (fixP
->fx_frag
->fr_address
9654 < text_section
->vma
+ text_section
->_raw_size
)
9655 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9656 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9657 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9659 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9660 insn
= 0x0c000000; /* jal */
9662 insn
= 0x08000000; /* j */
9663 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9665 fixP
->fx_addsy
= section_symbol (text_section
);
9666 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9670 /* FIXME. It would be possible in principle to handle
9671 conditional branches which overflow. They could be
9672 transformed into a branch around a jump. This would
9673 require setting up variant frags for each different
9674 branch type. The native MIPS assembler attempts to
9675 handle these cases, but it appears to do it
9677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9678 _("Branch out of range"));
9682 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9685 case BFD_RELOC_VTABLE_INHERIT
:
9688 && !S_IS_DEFINED (fixP
->fx_addsy
)
9689 && !S_IS_WEAK (fixP
->fx_addsy
))
9690 S_SET_WEAK (fixP
->fx_addsy
);
9693 case BFD_RELOC_VTABLE_ENTRY
:
9709 const struct mips_opcode
*p
;
9710 int treg
, sreg
, dreg
, shamt
;
9715 for (i
= 0; i
< NUMOPCODES
; ++i
)
9717 p
= &mips_opcodes
[i
];
9718 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9720 printf ("%08lx %s\t", oc
, p
->name
);
9721 treg
= (oc
>> 16) & 0x1f;
9722 sreg
= (oc
>> 21) & 0x1f;
9723 dreg
= (oc
>> 11) & 0x1f;
9724 shamt
= (oc
>> 6) & 0x1f;
9726 for (args
= p
->args
;; ++args
)
9737 printf ("%c", *args
);
9741 assert (treg
== sreg
);
9742 printf ("$%d,$%d", treg
, sreg
);
9747 printf ("$%d", dreg
);
9752 printf ("$%d", treg
);
9756 printf ("0x%x", treg
);
9761 printf ("$%d", sreg
);
9765 printf ("0x%08lx", oc
& 0x1ffffff);
9777 printf ("$%d", shamt
);
9788 printf (_("%08lx UNDEFINED\n"), oc
);
9799 name
= input_line_pointer
;
9800 c
= get_symbol_end ();
9801 p
= (symbolS
*) symbol_find_or_make (name
);
9802 *input_line_pointer
= c
;
9806 /* Align the current frag to a given power of two. The MIPS assembler
9807 also automatically adjusts any preceding label. */
9810 mips_align (to
, fill
, label
)
9815 mips_emit_delays (false);
9816 frag_align (to
, fill
, 0);
9817 record_alignment (now_seg
, to
);
9820 assert (S_GET_SEGMENT (label
) == now_seg
);
9821 label
->sy_frag
= frag_now
;
9822 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9826 /* Align to a given power of two. .align 0 turns off the automatic
9827 alignment used by the data creating pseudo-ops. */
9834 register long temp_fill
;
9835 long max_alignment
= 15;
9839 o Note that the assembler pulls down any immediately preceeding label
9840 to the aligned address.
9841 o It's not documented but auto alignment is reinstated by
9842 a .align pseudo instruction.
9843 o Note also that after auto alignment is turned off the mips assembler
9844 issues an error on attempt to assemble an improperly aligned data item.
9849 temp
= get_absolute_expression ();
9850 if (temp
> max_alignment
)
9851 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9854 as_warn (_("Alignment negative: 0 assumed."));
9857 if (*input_line_pointer
== ',')
9859 input_line_pointer
++;
9860 temp_fill
= get_absolute_expression ();
9867 mips_align (temp
, (int) temp_fill
,
9868 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9875 demand_empty_rest_of_line ();
9879 mips_flush_pending_output ()
9881 mips_emit_delays (false);
9882 mips_clear_insn_labels ();
9891 /* When generating embedded PIC code, we only use the .text, .lit8,
9892 .sdata and .sbss sections. We change the .data and .rdata
9893 pseudo-ops to use .sdata. */
9894 if (mips_pic
== EMBEDDED_PIC
9895 && (sec
== 'd' || sec
== 'r'))
9899 /* The ELF backend needs to know that we are changing sections, so
9900 that .previous works correctly. We could do something like check
9901 for a obj_section_change_hook macro, but that might be confusing
9902 as it would not be appropriate to use it in the section changing
9903 functions in read.c, since obj-elf.c intercepts those. FIXME:
9904 This should be cleaner, somehow. */
9905 obj_elf_section_change_hook ();
9908 mips_emit_delays (false);
9918 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9919 demand_empty_rest_of_line ();
9923 if (USE_GLOBAL_POINTER_OPT
)
9925 seg
= subseg_new (RDATA_SECTION_NAME
,
9926 (subsegT
) get_absolute_expression ());
9927 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9929 bfd_set_section_flags (stdoutput
, seg
,
9935 if (strcmp (TARGET_OS
, "elf") != 0)
9936 bfd_set_section_alignment (stdoutput
, seg
, 4);
9938 demand_empty_rest_of_line ();
9942 as_bad (_("No read only data section in this object file format"));
9943 demand_empty_rest_of_line ();
9949 if (USE_GLOBAL_POINTER_OPT
)
9951 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9952 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9954 bfd_set_section_flags (stdoutput
, seg
,
9955 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9957 if (strcmp (TARGET_OS
, "elf") != 0)
9958 bfd_set_section_alignment (stdoutput
, seg
, 4);
9960 demand_empty_rest_of_line ();
9965 as_bad (_("Global pointers not supported; recompile -G 0"));
9966 demand_empty_rest_of_line ();
9975 mips_enable_auto_align ()
9986 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9987 mips_emit_delays (false);
9988 if (log_size
> 0 && auto_align
)
9989 mips_align (log_size
, 0, label
);
9990 mips_clear_insn_labels ();
9991 cons (1 << log_size
);
10000 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10002 mips_emit_delays (false);
10006 mips_align (3, 0, label
);
10008 mips_align (2, 0, label
);
10010 mips_clear_insn_labels ();
10015 /* Handle .globl. We need to override it because on Irix 5 you are
10018 where foo is an undefined symbol, to mean that foo should be
10019 considered to be the address of a function. */
10030 name
= input_line_pointer
;
10031 c
= get_symbol_end ();
10032 symbolP
= symbol_find_or_make (name
);
10033 *input_line_pointer
= c
;
10034 SKIP_WHITESPACE ();
10036 /* On Irix 5, every global symbol that is not explicitly labelled as
10037 being a function is apparently labelled as being an object. */
10040 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10045 secname
= input_line_pointer
;
10046 c
= get_symbol_end ();
10047 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10049 as_bad (_("%s: no such section"), secname
);
10050 *input_line_pointer
= c
;
10052 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10053 flag
= BSF_FUNCTION
;
10056 symbolP
->bsym
->flags
|= flag
;
10058 S_SET_EXTERNAL (symbolP
);
10059 demand_empty_rest_of_line ();
10069 opt
= input_line_pointer
;
10070 c
= get_symbol_end ();
10074 /* FIXME: What does this mean? */
10076 else if (strncmp (opt
, "pic", 3) == 0)
10080 i
= atoi (opt
+ 3);
10084 mips_pic
= SVR4_PIC
;
10086 as_bad (_(".option pic%d not supported"), i
);
10088 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10090 if (g_switch_seen
&& g_switch_value
!= 0)
10091 as_warn (_("-G may not be used with SVR4 PIC code"));
10092 g_switch_value
= 0;
10093 bfd_set_gp_size (stdoutput
, 0);
10097 as_warn (_("Unrecognized option \"%s\""), opt
);
10099 *input_line_pointer
= c
;
10100 demand_empty_rest_of_line ();
10103 /* This structure is used to hold a stack of .set values. */
10105 struct mips_option_stack
10107 struct mips_option_stack
*next
;
10108 struct mips_set_options options
;
10111 static struct mips_option_stack
*mips_opts_stack
;
10113 /* Handle the .set pseudo-op. */
10119 char *name
= input_line_pointer
, ch
;
10121 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10122 input_line_pointer
++;
10123 ch
= *input_line_pointer
;
10124 *input_line_pointer
= '\0';
10126 if (strcmp (name
, "reorder") == 0)
10128 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10130 /* If we still have pending nops, we can discard them. The
10131 usual nop handling will insert any that are still
10133 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10134 * (mips_opts
.mips16
? 2 : 4));
10135 prev_nop_frag
= NULL
;
10137 mips_opts
.noreorder
= 0;
10139 else if (strcmp (name
, "noreorder") == 0)
10141 mips_emit_delays (true);
10142 mips_opts
.noreorder
= 1;
10143 mips_any_noreorder
= 1;
10145 else if (strcmp (name
, "at") == 0)
10147 mips_opts
.noat
= 0;
10149 else if (strcmp (name
, "noat") == 0)
10151 mips_opts
.noat
= 1;
10153 else if (strcmp (name
, "macro") == 0)
10155 mips_opts
.warn_about_macros
= 0;
10157 else if (strcmp (name
, "nomacro") == 0)
10159 if (mips_opts
.noreorder
== 0)
10160 as_bad (_("`noreorder' must be set before `nomacro'"));
10161 mips_opts
.warn_about_macros
= 1;
10163 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10165 mips_opts
.nomove
= 0;
10167 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10169 mips_opts
.nomove
= 1;
10171 else if (strcmp (name
, "bopt") == 0)
10173 mips_opts
.nobopt
= 0;
10175 else if (strcmp (name
, "nobopt") == 0)
10177 mips_opts
.nobopt
= 1;
10179 else if (strcmp (name
, "mips16") == 0
10180 || strcmp (name
, "MIPS-16") == 0)
10181 mips_opts
.mips16
= 1;
10182 else if (strcmp (name
, "nomips16") == 0
10183 || strcmp (name
, "noMIPS-16") == 0)
10184 mips_opts
.mips16
= 0;
10185 else if (strncmp (name
, "mips", 4) == 0)
10189 /* Permit the user to change the ISA on the fly. Needless to
10190 say, misuse can cause serious problems. */
10191 isa
= atoi (name
+ 4);
10193 mips_opts
.isa
= file_mips_isa
;
10194 else if (isa
< 1 || isa
> 4)
10195 as_bad (_("unknown ISA level"));
10197 mips_opts
.isa
= isa
;
10199 else if (strcmp (name
, "autoextend") == 0)
10200 mips_opts
.noautoextend
= 0;
10201 else if (strcmp (name
, "noautoextend") == 0)
10202 mips_opts
.noautoextend
= 1;
10203 else if (strcmp (name
, "push") == 0)
10205 struct mips_option_stack
*s
;
10207 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10208 s
->next
= mips_opts_stack
;
10209 s
->options
= mips_opts
;
10210 mips_opts_stack
= s
;
10212 else if (strcmp (name
, "pop") == 0)
10214 struct mips_option_stack
*s
;
10216 s
= mips_opts_stack
;
10218 as_bad (_(".set pop with no .set push"));
10221 /* If we're changing the reorder mode we need to handle
10222 delay slots correctly. */
10223 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10224 mips_emit_delays (true);
10225 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10227 if (prev_nop_frag
!= NULL
)
10229 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10230 * (mips_opts
.mips16
? 2 : 4));
10231 prev_nop_frag
= NULL
;
10235 mips_opts
= s
->options
;
10236 mips_opts_stack
= s
->next
;
10242 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10244 *input_line_pointer
= ch
;
10245 demand_empty_rest_of_line ();
10248 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10249 .option pic2. It means to generate SVR4 PIC calls. */
10252 s_abicalls (ignore
)
10255 mips_pic
= SVR4_PIC
;
10256 if (USE_GLOBAL_POINTER_OPT
)
10258 if (g_switch_seen
&& g_switch_value
!= 0)
10259 as_warn (_("-G may not be used with SVR4 PIC code"));
10260 g_switch_value
= 0;
10262 bfd_set_gp_size (stdoutput
, 0);
10263 demand_empty_rest_of_line ();
10266 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10267 PIC code. It sets the $gp register for the function based on the
10268 function address, which is in the register named in the argument.
10269 This uses a relocation against _gp_disp, which is handled specially
10270 by the linker. The result is:
10271 lui $gp,%hi(_gp_disp)
10272 addiu $gp,$gp,%lo(_gp_disp)
10273 addu $gp,$gp,.cpload argument
10274 The .cpload argument is normally $25 == $t9. */
10283 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10284 if (mips_pic
!= SVR4_PIC
)
10290 /* .cpload should be a in .set noreorder section. */
10291 if (mips_opts
.noreorder
== 0)
10292 as_warn (_(".cpload not in noreorder section"));
10294 ex
.X_op
= O_symbol
;
10295 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10296 ex
.X_op_symbol
= NULL
;
10297 ex
.X_add_number
= 0;
10299 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10300 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10302 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10303 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10304 (int) BFD_RELOC_LO16
);
10306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10307 GP
, GP
, tc_get_register (0));
10309 demand_empty_rest_of_line ();
10312 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10313 offset from $sp. The offset is remembered, and after making a PIC
10314 call $gp is restored from that location. */
10317 s_cprestore (ignore
)
10323 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10324 if (mips_pic
!= SVR4_PIC
)
10330 mips_cprestore_offset
= get_absolute_expression ();
10332 ex
.X_op
= O_constant
;
10333 ex
.X_add_symbol
= NULL
;
10334 ex
.X_op_symbol
= NULL
;
10335 ex
.X_add_number
= mips_cprestore_offset
;
10337 macro_build ((char *) NULL
, &icnt
, &ex
,
10338 ((bfd_arch_bits_per_address (stdoutput
) == 32
10339 || mips_opts
.isa
< 3)
10341 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10343 demand_empty_rest_of_line ();
10346 /* Handle the .gpword pseudo-op. This is used when generating PIC
10347 code. It generates a 32 bit GP relative reloc. */
10357 /* When not generating PIC code, this is treated as .word. */
10358 if (mips_pic
!= SVR4_PIC
)
10364 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10365 mips_emit_delays (true);
10367 mips_align (2, 0, label
);
10368 mips_clear_insn_labels ();
10372 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10374 as_bad (_("Unsupported use of .gpword"));
10375 ignore_rest_of_line ();
10379 md_number_to_chars (p
, (valueT
) 0, 4);
10380 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10381 BFD_RELOC_MIPS_GPREL32
);
10383 demand_empty_rest_of_line ();
10386 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10387 tables in SVR4 PIC code. */
10396 /* This is ignored when not generating SVR4 PIC code. */
10397 if (mips_pic
!= SVR4_PIC
)
10403 /* Add $gp to the register named as an argument. */
10404 reg
= tc_get_register (0);
10405 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10406 ((bfd_arch_bits_per_address (stdoutput
) == 32
10407 || mips_opts
.isa
< 3)
10408 ? "addu" : "daddu"),
10409 "d,v,t", reg
, reg
, GP
);
10411 demand_empty_rest_of_line ();
10414 /* Handle the .insn pseudo-op. This marks instruction labels in
10415 mips16 mode. This permits the linker to handle them specially,
10416 such as generating jalx instructions when needed. We also make
10417 them odd for the duration of the assembly, in order to generate the
10418 right sort of code. We will make them even in the adjust_symtab
10419 routine, while leaving them marked. This is convenient for the
10420 debugger and the disassembler. The linker knows to make them odd
10427 if (mips_opts
.mips16
)
10428 mips16_mark_labels ();
10430 demand_empty_rest_of_line ();
10433 /* Handle a .stabn directive. We need these in order to mark a label
10434 as being a mips16 text label correctly. Sometimes the compiler
10435 will emit a label, followed by a .stabn, and then switch sections.
10436 If the label and .stabn are in mips16 mode, then the label is
10437 really a mips16 text label. */
10443 if (type
== 'n' && mips_opts
.mips16
)
10444 mips16_mark_labels ();
10449 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10453 s_mips_weakext (ignore
)
10461 name
= input_line_pointer
;
10462 c
= get_symbol_end ();
10463 symbolP
= symbol_find_or_make (name
);
10464 S_SET_WEAK (symbolP
);
10465 *input_line_pointer
= c
;
10467 SKIP_WHITESPACE ();
10469 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10471 if (S_IS_DEFINED (symbolP
))
10473 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10474 S_GET_NAME (symbolP
));
10475 ignore_rest_of_line ();
10479 if (*input_line_pointer
== ',')
10481 ++input_line_pointer
;
10482 SKIP_WHITESPACE ();
10486 if (exp
.X_op
!= O_symbol
)
10488 as_bad ("bad .weakext directive");
10489 ignore_rest_of_line();
10492 symbolP
->sy_value
= exp
;
10495 demand_empty_rest_of_line ();
10498 /* Parse a register string into a number. Called from the ECOFF code
10499 to parse .frame. The argument is non-zero if this is the frame
10500 register, so that we can record it in mips_frame_reg. */
10503 tc_get_register (frame
)
10508 SKIP_WHITESPACE ();
10509 if (*input_line_pointer
++ != '$')
10511 as_warn (_("expected `$'"));
10514 else if (isdigit ((unsigned char) *input_line_pointer
))
10516 reg
= get_absolute_expression ();
10517 if (reg
< 0 || reg
>= 32)
10519 as_warn (_("Bad register number"));
10525 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10527 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10529 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10531 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10535 as_warn (_("Unrecognized register name"));
10538 input_line_pointer
+= 2;
10541 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10546 md_section_align (seg
, addr
)
10550 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10553 /* We don't need to align ELF sections to the full alignment.
10554 However, Irix 5 may prefer that we align them at least to a 16
10555 byte boundary. We don't bother to align the sections if we are
10556 targeted for an embedded system. */
10557 if (strcmp (TARGET_OS
, "elf") == 0)
10563 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10566 /* Utility routine, called from above as well. If called while the
10567 input file is still being read, it's only an approximation. (For
10568 example, a symbol may later become defined which appeared to be
10569 undefined earlier.) */
10572 nopic_need_relax (sym
, before_relaxing
)
10574 int before_relaxing
;
10579 if (USE_GLOBAL_POINTER_OPT
)
10581 const char *symname
;
10584 /* Find out whether this symbol can be referenced off the GP
10585 register. It can be if it is smaller than the -G size or if
10586 it is in the .sdata or .sbss section. Certain symbols can
10587 not be referenced off the GP, although it appears as though
10589 symname
= S_GET_NAME (sym
);
10590 if (symname
!= (const char *) NULL
10591 && (strcmp (symname
, "eprol") == 0
10592 || strcmp (symname
, "etext") == 0
10593 || strcmp (symname
, "_gp") == 0
10594 || strcmp (symname
, "edata") == 0
10595 || strcmp (symname
, "_fbss") == 0
10596 || strcmp (symname
, "_fdata") == 0
10597 || strcmp (symname
, "_ftext") == 0
10598 || strcmp (symname
, "end") == 0
10599 || strcmp (symname
, "_gp_disp") == 0))
10601 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10603 #ifndef NO_ECOFF_DEBUGGING
10604 || (sym
->ecoff_extern_size
!= 0
10605 && sym
->ecoff_extern_size
<= g_switch_value
)
10607 /* We must defer this decision until after the whole
10608 file has been read, since there might be a .extern
10609 after the first use of this symbol. */
10610 || (before_relaxing
10611 #ifndef NO_ECOFF_DEBUGGING
10612 && sym
->ecoff_extern_size
== 0
10614 && S_GET_VALUE (sym
) == 0)
10615 || (S_GET_VALUE (sym
) != 0
10616 && S_GET_VALUE (sym
) <= g_switch_value
)))
10620 const char *segname
;
10622 segname
= segment_name (S_GET_SEGMENT (sym
));
10623 assert (strcmp (segname
, ".lit8") != 0
10624 && strcmp (segname
, ".lit4") != 0);
10625 change
= (strcmp (segname
, ".sdata") != 0
10626 && strcmp (segname
, ".sbss") != 0);
10631 /* We are not optimizing for the GP register. */
10635 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10636 extended opcode. SEC is the section the frag is in. */
10639 mips16_extended_frag (fragp
, sec
, stretch
)
10645 register const struct mips16_immed_operand
*op
;
10647 int mintiny
, maxtiny
;
10650 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10652 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10655 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10656 op
= mips16_immed_operands
;
10657 while (op
->type
!= type
)
10660 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10665 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10668 maxtiny
= 1 << op
->nbits
;
10673 maxtiny
= (1 << op
->nbits
) - 1;
10678 mintiny
= - (1 << (op
->nbits
- 1));
10679 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10682 /* We can't call S_GET_VALUE here, because we don't want to lock in
10683 a particular frag address. */
10684 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10686 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10687 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10688 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10690 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10691 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10694 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10695 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10696 + fragp
->fr_symbol
->sy_value
.X_add_number
10697 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10698 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10707 /* We won't have the section when we are called from
10708 mips_relax_frag. However, we will always have been called
10709 from md_estimate_size_before_relax first. If this is a
10710 branch to a different section, we mark it as such. If SEC is
10711 NULL, and the frag is not marked, then it must be a branch to
10712 the same section. */
10715 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10722 fragp
->fr_subtype
=
10723 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10725 /* FIXME: We should support this, and let the linker
10726 catch branches and loads that are out of range. */
10727 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10728 _("unsupported PC relative reference to different section"));
10734 /* In this case, we know for sure that the symbol fragment is in
10735 the same section. If the fr_address of the symbol fragment
10736 is greater then the address of this fragment we want to add
10737 in STRETCH in order to get a better estimate of the address.
10738 This particularly matters because of the shift bits. */
10740 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10744 /* Adjust stretch for any alignment frag. Note that if have
10745 been expanding the earlier code, the symbol may be
10746 defined in what appears to be an earlier frag. FIXME:
10747 This doesn't handle the fr_subtype field, which specifies
10748 a maximum number of bytes to skip when doing an
10751 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10754 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10757 stretch
= - ((- stretch
)
10758 & ~ ((1 << (int) f
->fr_offset
) - 1));
10760 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10769 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10771 /* The base address rules are complicated. The base address of
10772 a branch is the following instruction. The base address of a
10773 PC relative load or add is the instruction itself, but if it
10774 is in a delay slot (in which case it can not be extended) use
10775 the address of the instruction whose delay slot it is in. */
10776 if (type
== 'p' || type
== 'q')
10780 /* If we are currently assuming that this frag should be
10781 extended, then, the current address is two bytes
10783 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10786 /* Ignore the low bit in the target, since it will be set
10787 for a text label. */
10788 if ((val
& 1) != 0)
10791 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10793 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10796 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10798 /* Branch offsets have an implicit 0 in the lowest bit. */
10799 if (type
== 'p' || type
== 'q')
10802 /* If any of the shifted bits are set, we must use an extended
10803 opcode. If the address depends on the size of this
10804 instruction, this can lead to a loop, so we arrange to always
10805 use an extended opcode. We only check this when we are in
10806 the main relaxation loop, when SEC is NULL. */
10807 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10809 fragp
->fr_subtype
=
10810 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10814 /* If we are about to mark a frag as extended because the value
10815 is precisely maxtiny + 1, then there is a chance of an
10816 infinite loop as in the following code:
10821 In this case when the la is extended, foo is 0x3fc bytes
10822 away, so the la can be shrunk, but then foo is 0x400 away, so
10823 the la must be extended. To avoid this loop, we mark the
10824 frag as extended if it was small, and is about to become
10825 extended with a value of maxtiny + 1. */
10826 if (val
== ((maxtiny
+ 1) << op
->shift
)
10827 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10830 fragp
->fr_subtype
=
10831 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10835 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10836 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10838 if ((val
& ((1 << op
->shift
) - 1)) != 0
10839 || val
< (mintiny
<< op
->shift
)
10840 || val
> (maxtiny
<< op
->shift
))
10846 /* Estimate the size of a frag before relaxing. Unless this is the
10847 mips16, we are not really relaxing here, and the final size is
10848 encoded in the subtype information. For the mips16, we have to
10849 decide whether we are using an extended opcode or not. */
10853 md_estimate_size_before_relax (fragp
, segtype
)
10859 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10861 if (mips16_extended_frag (fragp
, segtype
, 0))
10863 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10868 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10873 if (mips_pic
== NO_PIC
)
10875 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10877 else if (mips_pic
== SVR4_PIC
)
10882 sym
= fragp
->fr_symbol
;
10884 /* Handle the case of a symbol equated to another symbol. */
10885 while (sym
->sy_value
.X_op
== O_symbol
10886 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10890 /* It's possible to get a loop here in a badly written
10892 n
= sym
->sy_value
.X_add_symbol
;
10898 symsec
= S_GET_SEGMENT (sym
);
10900 /* This must duplicate the test in adjust_reloc_syms. */
10901 change
= (symsec
!= &bfd_und_section
10902 && symsec
!= &bfd_abs_section
10903 && ! bfd_is_com_section (symsec
));
10910 /* Record the offset to the first reloc in the fr_opcode field.
10911 This lets md_convert_frag and tc_gen_reloc know that the code
10912 must be expanded. */
10913 fragp
->fr_opcode
= (fragp
->fr_literal
10915 - RELAX_OLD (fragp
->fr_subtype
)
10916 + RELAX_RELOC1 (fragp
->fr_subtype
));
10917 /* FIXME: This really needs as_warn_where. */
10918 if (RELAX_WARN (fragp
->fr_subtype
))
10919 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
10925 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10928 /* This is called to see whether a reloc against a defined symbol
10929 should be converted into a reloc against a section. Don't adjust
10930 MIPS16 jump relocations, so we don't have to worry about the format
10931 of the offset in the .o file. Don't adjust relocations against
10932 mips16 symbols, so that the linker can find them if it needs to set
10936 mips_fix_adjustable (fixp
)
10939 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10941 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10942 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10944 if (fixp
->fx_addsy
== NULL
)
10947 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10948 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10949 && fixp
->fx_subsy
== NULL
)
10955 /* Translate internal representation of relocation info to BFD target
10959 tc_gen_reloc (section
, fixp
)
10963 static arelent
*retval
[4];
10965 bfd_reloc_code_real_type code
;
10967 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10970 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10971 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10973 if (mips_pic
== EMBEDDED_PIC
10974 && SWITCH_TABLE (fixp
))
10976 /* For a switch table entry we use a special reloc. The addend
10977 is actually the difference between the reloc address and the
10979 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10980 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10981 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
10982 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10984 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10986 /* We use a special addend for an internal RELLO reloc. */
10987 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10988 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10990 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10992 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10994 assert (fixp
->fx_next
!= NULL
10995 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10996 /* We use a special addend for an internal RELHI reloc. The
10997 reloc is relative to the RELLO; adjust the addend
10999 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11000 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11001 + fixp
->fx_next
->fx_where
11002 - S_GET_VALUE (fixp
->fx_subsy
));
11004 reloc
->addend
= (fixp
->fx_addnumber
11005 + fixp
->fx_next
->fx_frag
->fr_address
11006 + fixp
->fx_next
->fx_where
);
11008 else if (fixp
->fx_pcrel
== 0)
11009 reloc
->addend
= fixp
->fx_addnumber
;
11012 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11013 /* A gruesome hack which is a result of the gruesome gas reloc
11015 reloc
->addend
= reloc
->address
;
11017 reloc
->addend
= -reloc
->address
;
11020 /* If this is a variant frag, we may need to adjust the existing
11021 reloc and generate a new one. */
11022 if (fixp
->fx_frag
->fr_opcode
!= NULL
11023 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11024 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11025 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11026 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11027 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11028 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11029 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11033 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11035 /* If this is not the last reloc in this frag, then we have two
11036 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11037 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11038 the second one handle all of them. */
11039 if (fixp
->fx_next
!= NULL
11040 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11042 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11043 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11044 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11045 && (fixp
->fx_next
->fx_r_type
11046 == BFD_RELOC_MIPS_GOT_LO16
))
11047 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11048 && (fixp
->fx_next
->fx_r_type
11049 == BFD_RELOC_MIPS_CALL_LO16
)));
11054 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11055 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11056 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11058 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11059 reloc2
->address
= (reloc
->address
11060 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11061 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11062 reloc2
->addend
= fixp
->fx_addnumber
;
11063 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11064 assert (reloc2
->howto
!= NULL
);
11066 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11070 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11073 reloc3
->address
+= 4;
11076 if (mips_pic
== NO_PIC
)
11078 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11079 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11081 else if (mips_pic
== SVR4_PIC
)
11083 switch (fixp
->fx_r_type
)
11087 case BFD_RELOC_MIPS_GOT16
:
11089 case BFD_RELOC_MIPS_CALL16
:
11090 case BFD_RELOC_MIPS_GOT_LO16
:
11091 case BFD_RELOC_MIPS_CALL_LO16
:
11092 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11100 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11101 to be used in the relocation's section offset. */
11102 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11104 reloc
->address
= reloc
->addend
;
11108 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11109 fixup_segment converted a non-PC relative reloc into a PC
11110 relative reloc. In such a case, we need to convert the reloc
11112 code
= fixp
->fx_r_type
;
11113 if (fixp
->fx_pcrel
)
11118 code
= BFD_RELOC_8_PCREL
;
11121 code
= BFD_RELOC_16_PCREL
;
11124 code
= BFD_RELOC_32_PCREL
;
11127 code
= BFD_RELOC_64_PCREL
;
11129 case BFD_RELOC_8_PCREL
:
11130 case BFD_RELOC_16_PCREL
:
11131 case BFD_RELOC_32_PCREL
:
11132 case BFD_RELOC_64_PCREL
:
11133 case BFD_RELOC_16_PCREL_S2
:
11134 case BFD_RELOC_PCREL_HI16_S
:
11135 case BFD_RELOC_PCREL_LO16
:
11138 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11139 _("Cannot make %s relocation PC relative"),
11140 bfd_get_reloc_code_name (code
));
11144 /* To support a PC relative reloc when generating embedded PIC code
11145 for ECOFF, we use a Cygnus extension. We check for that here to
11146 make sure that we don't let such a reloc escape normally. */
11147 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11148 && code
== BFD_RELOC_16_PCREL_S2
11149 && mips_pic
!= EMBEDDED_PIC
)
11150 reloc
->howto
= NULL
;
11152 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11154 if (reloc
->howto
== NULL
)
11156 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11157 _("Can not represent %s relocation in this object file format"),
11158 bfd_get_reloc_code_name (code
));
11165 /* Relax a machine dependent frag. This returns the amount by which
11166 the current size of the frag should change. */
11169 mips_relax_frag (fragp
, stretch
)
11173 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11176 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11178 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11180 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11185 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11187 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11194 /* Convert a machine dependent frag. */
11197 md_convert_frag (abfd
, asec
, fragp
)
11205 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11208 register const struct mips16_immed_operand
*op
;
11209 boolean small
, ext
;
11212 unsigned long insn
;
11213 boolean use_extend
;
11214 unsigned short extend
;
11216 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11217 op
= mips16_immed_operands
;
11218 while (op
->type
!= type
)
11221 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11232 resolve_symbol_value (fragp
->fr_symbol
, 1);
11233 val
= S_GET_VALUE (fragp
->fr_symbol
);
11238 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11240 /* The rules for the base address of a PC relative reloc are
11241 complicated; see mips16_extended_frag. */
11242 if (type
== 'p' || type
== 'q')
11247 /* Ignore the low bit in the target, since it will be
11248 set for a text label. */
11249 if ((val
& 1) != 0)
11252 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11254 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11257 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11260 /* Make sure the section winds up with the alignment we have
11263 record_alignment (asec
, op
->shift
);
11267 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11268 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11269 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11270 _("extended instruction in delay slot"));
11272 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11274 if (target_big_endian
)
11275 insn
= bfd_getb16 (buf
);
11277 insn
= bfd_getl16 (buf
);
11279 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11280 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11281 small
, ext
, &insn
, &use_extend
, &extend
);
11285 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11286 fragp
->fr_fix
+= 2;
11290 md_number_to_chars (buf
, insn
, 2);
11291 fragp
->fr_fix
+= 2;
11296 if (fragp
->fr_opcode
== NULL
)
11299 old
= RELAX_OLD (fragp
->fr_subtype
);
11300 new = RELAX_NEW (fragp
->fr_subtype
);
11301 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11304 memcpy (fixptr
- old
, fixptr
, new);
11306 fragp
->fr_fix
+= new - old
;
11312 /* This function is called after the relocs have been generated.
11313 We've been storing mips16 text labels as odd. Here we convert them
11314 back to even for the convenience of the debugger. */
11317 mips_frob_file_after_relocs ()
11320 unsigned int count
, i
;
11322 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11325 syms
= bfd_get_outsymbols (stdoutput
);
11326 count
= bfd_get_symcount (stdoutput
);
11327 for (i
= 0; i
< count
; i
++, syms
++)
11329 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11330 && ((*syms
)->value
& 1) != 0)
11332 (*syms
)->value
&= ~1;
11333 /* If the symbol has an odd size, it was probably computed
11334 incorrectly, so adjust that as well. */
11335 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11336 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11343 /* This function is called whenever a label is defined. It is used
11344 when handling branch delays; if a branch has a label, we assume we
11345 can not move it. */
11348 mips_define_label (sym
)
11351 struct insn_label_list
*l
;
11353 if (free_insn_labels
== NULL
)
11354 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11357 l
= free_insn_labels
;
11358 free_insn_labels
= l
->next
;
11362 l
->next
= insn_labels
;
11366 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11368 /* Some special processing for a MIPS ELF file. */
11371 mips_elf_final_processing ()
11373 /* Write out the register information. */
11378 s
.ri_gprmask
= mips_gprmask
;
11379 s
.ri_cprmask
[0] = mips_cprmask
[0];
11380 s
.ri_cprmask
[1] = mips_cprmask
[1];
11381 s
.ri_cprmask
[2] = mips_cprmask
[2];
11382 s
.ri_cprmask
[3] = mips_cprmask
[3];
11383 /* The gp_value field is set by the MIPS ELF backend. */
11385 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11386 ((Elf32_External_RegInfo
*)
11387 mips_regmask_frag
));
11391 Elf64_Internal_RegInfo s
;
11393 s
.ri_gprmask
= mips_gprmask
;
11395 s
.ri_cprmask
[0] = mips_cprmask
[0];
11396 s
.ri_cprmask
[1] = mips_cprmask
[1];
11397 s
.ri_cprmask
[2] = mips_cprmask
[2];
11398 s
.ri_cprmask
[3] = mips_cprmask
[3];
11399 /* The gp_value field is set by the MIPS ELF backend. */
11401 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11402 ((Elf64_External_RegInfo
*)
11403 mips_regmask_frag
));
11406 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11407 sort of BFD interface for this. */
11408 if (mips_any_noreorder
)
11409 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11410 if (mips_pic
!= NO_PIC
)
11411 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11413 /* Set the MIPS ELF ABI flags. */
11414 if (mips_abi_string
== 0)
11416 else if (strcmp (mips_abi_string
,"32") == 0)
11417 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11418 else if (strcmp (mips_abi_string
,"o64") == 0)
11419 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11420 else if (strcmp (mips_abi_string
,"eabi") == 0)
11423 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11425 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11428 if (mips_32bitmode
)
11429 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11432 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11434 typedef struct proc
11436 struct symbol
*isym
;
11437 unsigned long reg_mask
;
11438 unsigned long reg_offset
;
11439 unsigned long fpreg_mask
;
11440 unsigned long fpreg_offset
;
11441 unsigned long frame_offset
;
11442 unsigned long frame_reg
;
11443 unsigned long pc_reg
;
11447 static procS cur_proc
;
11448 static procS
*cur_proc_ptr
;
11449 static int numprocs
;
11459 /* check for premature end, nesting errors, etc */
11461 as_warn (_("missing `.end' at end of assembly"));
11470 if (*input_line_pointer
== '-')
11472 ++input_line_pointer
;
11475 if (!isdigit (*input_line_pointer
))
11476 as_bad (_("Expected simple number."));
11477 if (input_line_pointer
[0] == '0')
11479 if (input_line_pointer
[1] == 'x')
11481 input_line_pointer
+= 2;
11482 while (isxdigit (*input_line_pointer
))
11485 val
|= hex_value (*input_line_pointer
++);
11487 return negative
? -val
: val
;
11491 ++input_line_pointer
;
11492 while (isdigit (*input_line_pointer
))
11495 val
|= *input_line_pointer
++ - '0';
11497 return negative
? -val
: val
;
11500 if (!isdigit (*input_line_pointer
))
11502 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11503 *input_line_pointer
, *input_line_pointer
);
11504 as_warn (_("Invalid number"));
11507 while (isdigit (*input_line_pointer
))
11510 val
+= *input_line_pointer
++ - '0';
11512 return negative
? -val
: val
;
11515 /* The .file directive; just like the usual .file directive, but there
11516 is an initial number which is the ECOFF file index. */
11524 line
= get_number ();
11529 /* The .end directive. */
11538 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11541 demand_empty_rest_of_line ();
11546 #ifdef BFD_ASSEMBLER
11547 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11552 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11559 as_warn (_(".end not in text section"));
11563 as_warn (_(".end directive without a preceding .ent directive."));
11564 demand_empty_rest_of_line ();
11570 assert (S_GET_NAME (p
));
11571 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11572 as_warn (_(".end symbol does not match .ent symbol."));
11575 as_warn (_(".end directive missing or unknown symbol"));
11577 #ifdef MIPS_STABS_ELF
11579 segT saved_seg
= now_seg
;
11580 subsegT saved_subseg
= now_subseg
;
11581 fragS
*saved_frag
= frag_now
;
11587 dot
= frag_now_fix ();
11589 #ifdef md_flush_pending_output
11590 md_flush_pending_output ();
11594 subseg_set (pdr_seg
, 0);
11596 /* Write the symbol */
11597 exp
.X_op
= O_symbol
;
11598 exp
.X_add_symbol
= p
;
11599 exp
.X_add_number
= 0;
11600 emit_expr (&exp
, 4);
11602 fragp
= frag_more (7*4);
11604 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11605 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11606 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11607 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11608 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11609 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11610 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11612 subseg_set (saved_seg
, saved_subseg
);
11616 cur_proc_ptr
= NULL
;
11619 /* The .aent and .ent directives. */
11629 symbolP
= get_symbol ();
11630 if (*input_line_pointer
== ',')
11631 input_line_pointer
++;
11632 SKIP_WHITESPACE ();
11633 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
11634 number
= get_number ();
11636 #ifdef BFD_ASSEMBLER
11637 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11642 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11649 as_warn (_(".ent or .aent not in text section."));
11651 if (!aent
&& cur_proc_ptr
)
11652 as_warn (_("missing `.end'"));
11656 cur_proc_ptr
= &cur_proc
;
11657 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11659 cur_proc_ptr
->isym
= symbolP
;
11661 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
11666 demand_empty_rest_of_line ();
11669 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11670 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11671 s_mips_frame is used so that we can set the PDR information correctly.
11672 We can't use the ecoff routines because they make reference to the ecoff
11673 symbol table (in the mdebug section). */
11676 s_mips_frame (ignore
)
11679 #ifdef MIPS_STABS_ELF
11683 if (cur_proc_ptr
== (procS
*) NULL
)
11685 as_warn (_(".frame outside of .ent"));
11686 demand_empty_rest_of_line ();
11690 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11692 SKIP_WHITESPACE ();
11693 if (*input_line_pointer
++ != ','
11694 || get_absolute_expression_and_terminator (&val
) != ',')
11696 as_warn (_("Bad .frame directive"));
11697 --input_line_pointer
;
11698 demand_empty_rest_of_line ();
11702 cur_proc_ptr
->frame_offset
= val
;
11703 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11705 demand_empty_rest_of_line ();
11708 #endif /* MIPS_STABS_ELF */
11711 /* The .fmask and .mask directives. If the mdebug section is present
11712 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11713 embedded targets, s_mips_mask is used so that we can set the PDR
11714 information correctly. We can't use the ecoff routines because they
11715 make reference to the ecoff symbol table (in the mdebug section). */
11718 s_mips_mask (reg_type
)
11721 #ifdef MIPS_STABS_ELF
11724 if (cur_proc_ptr
== (procS
*) NULL
)
11726 as_warn (_(".mask/.fmask outside of .ent"));
11727 demand_empty_rest_of_line ();
11731 if (get_absolute_expression_and_terminator (&mask
) != ',')
11733 as_warn (_("Bad .mask/.fmask directive"));
11734 --input_line_pointer
;
11735 demand_empty_rest_of_line ();
11739 off
= get_absolute_expression ();
11741 if (reg_type
== 'F')
11743 cur_proc_ptr
->fpreg_mask
= mask
;
11744 cur_proc_ptr
->fpreg_offset
= off
;
11748 cur_proc_ptr
->reg_mask
= mask
;
11749 cur_proc_ptr
->reg_offset
= off
;
11752 demand_empty_rest_of_line ();
11754 s_ignore (reg_type
);
11755 #endif /* MIPS_STABS_ELF */
11758 /* The .loc directive. */
11769 assert (now_seg
== text_section
);
11771 lineno
= get_number ();
11772 addroff
= frag_now_fix ();
11774 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11775 S_SET_TYPE (symbolP
, N_SLINE
);
11776 S_SET_OTHER (symbolP
, 0);
11777 S_SET_DESC (symbolP
, lineno
);
11778 symbolP
->sy_segment
= now_seg
;