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Initial revision
[binutils.git] / gas / config / tc-m68k.c
blob856dd4ec264b9d9e9c67b6248aaf817ec861b935
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
36 #else
37 const char *m68k_comment_chars = "|";
38 #endif
39
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#*";
48
49 const char line_separator_chars[] = "";
50
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
53
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
56
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
58
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
62
63 const int md_reloc_size = 8; /* Size of relocation record */
64
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
69 int flag_want_pic;
70
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
73
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76 #else
77 int flag_reg_prefix_optional;
78 #endif
79
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
82
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
85
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
89
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
93
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97 static int m68k_rel32 = 1;
98
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
101
102 /* The default width to use for an index register when using a base
103 displacement. */
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110 struct label_line
111 {
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117 };
118
119 /* The list of labels. */
120
121 static struct label_line *labels;
122
123 /* The current label. */
124
125 static struct label_line *current_label;
126
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
130
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
133 #define BYTE 0
134 #define SHORT 1
135 #define LONG 2
136 #define SZ_UNDEF 3
137 #undef BRANCH
138 /* Case `g' except when BCC68000 is applicable. */
139 #define ABRANCH 1
140 /* Coprocessor branches. */
141 #define FBRANCH 2
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
144 #define PCREL 3
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
150 #define BCC68000 4
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
153 #define DBCC 5
154 /* Not currently used? */
155 #define PCLEA 6
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158 #define PCINDEX 7
159
160 struct m68k_incant
161 {
162 const char *m_operands;
163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
172
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
175 SFC, DFC, USP, VBR,
176 0
177 };
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181 };
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186 };
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191 };
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196 };
197 #define cpu32_control_regs m68010_control_regs
198
199 static const enum m68k_register *control_regs;
200
201 /* internal form of a 68020 instruction */
202 struct m68k_it
203 {
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
207
208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
210
211 struct m68k_op operands[6];
212
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
215
216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
221 offsetT foff;
222 int fragty;
223 }
224 fragb[4];
225
226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
241 #ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245 #endif
246 }
247 reloc[5]; /* Five is enough??? */
248 };
249
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
253
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
256
257 static struct m68k_it the_ins; /* the instruction being assembled */
258
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
263
264 /* Macros for adding things to the m68k_it struct */
265
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
267
268 /* Static functions. */
269
270 static void insop PARAMS ((int, const struct m68k_incant *));
271 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
272 static void add_frag PARAMS ((symbolS *, offsetT, int));
273
274 /* Like addword, but goes BEFORE general operands */
275 static void
276 insop (w, opcode)
277 int w;
278 const struct m68k_incant *opcode;
279 {
280 int z;
281 for(z=the_ins.numo;z>opcode->m_codenum;--z)
282 the_ins.opcode[z]=the_ins.opcode[z-1];
283 for(z=0;z<the_ins.nrel;z++)
284 the_ins.reloc[z].n+=2;
285 for (z = 0; z < the_ins.nfrag; z++)
286 the_ins.fragb[z].fragoff++;
287 the_ins.opcode[opcode->m_codenum]=w;
288 the_ins.numo++;
289 }
290
291 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
292 Blecch. */
293 static void
294 add_fix (width, exp, pc_rel, pc_fix)
295 int width;
296 struct m68k_exp *exp;
297 int pc_rel;
298 int pc_fix;
299 {
300 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
301 ? (the_ins.numo*2-1)
302 : (((width)=='b')
303 ? (the_ins.numo*2+1)
304 : (the_ins.numo*2)));
305 the_ins.reloc[the_ins.nrel].exp = exp->exp;
306 the_ins.reloc[the_ins.nrel].wid = width;
307 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
308 #ifdef OBJ_ELF
309 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
310 #endif
311 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
312 }
313
314 /* Cause an extra frag to be generated here, inserting up to 10 bytes
315 (that value is chosen in the frag_var call in md_assemble). TYPE
316 is the subtype of the frag to be generated; its primary type is
317 rs_machine_dependent.
318
319 The TYPE parameter is also used by md_convert_frag_1 and
320 md_estimate_size_before_relax. The appropriate type of fixup will
321 be emitted by md_convert_frag_1.
322
323 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
324 static void
325 add_frag (add, off, type)
326 symbolS *add;
327 offsetT off;
328 int type;
329 {
330 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
331 the_ins.fragb[the_ins.nfrag].fadd=add;
332 the_ins.fragb[the_ins.nfrag].foff=off;
333 the_ins.fragb[the_ins.nfrag++].fragty=type;
334 }
335
336 #define isvar(ex) \
337 (op (ex) != O_constant && op (ex) != O_big)
338
339 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
340 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
341 static void m68k_ip PARAMS ((char *));
342 static void insert_reg PARAMS ((const char *, int));
343 static void select_control_regs PARAMS ((void));
344 static void init_regtable PARAMS ((void));
345 static int reverse_16_bits PARAMS ((int in));
346 static int reverse_8_bits PARAMS ((int in));
347 static void install_gen_operand PARAMS ((int mode, int val));
348 static void install_operand PARAMS ((int mode, int val));
349 static void s_bss PARAMS ((int));
350 static void s_data1 PARAMS ((int));
351 static void s_data2 PARAMS ((int));
352 static void s_even PARAMS ((int));
353 static void s_proc PARAMS ((int));
354 static void mri_chip PARAMS ((void));
355 static void s_chip PARAMS ((int));
356 static void s_fopt PARAMS ((int));
357 static void s_opt PARAMS ((int));
358 static void s_reg PARAMS ((int));
359 static void s_restore PARAMS ((int));
360 static void s_save PARAMS ((int));
361 static void s_mri_if PARAMS ((int));
362 static void s_mri_else PARAMS ((int));
363 static void s_mri_endi PARAMS ((int));
364 static void s_mri_break PARAMS ((int));
365 static void s_mri_next PARAMS ((int));
366 static void s_mri_for PARAMS ((int));
367 static void s_mri_endf PARAMS ((int));
368 static void s_mri_repeat PARAMS ((int));
369 static void s_mri_until PARAMS ((int));
370 static void s_mri_while PARAMS ((int));
371 static void s_mri_endw PARAMS ((int));
372 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
373 static void md_convert_frag_1 PARAMS ((fragS *));
374
375 static int current_architecture;
376
377 struct m68k_cpu {
378 unsigned long arch;
379 const char *name;
380 int alias;
381 };
382
383 static const struct m68k_cpu archs[] = {
384 { m68000, "68000", 0 },
385 { m68010, "68010", 0 },
386 { m68020, "68020", 0 },
387 { m68030, "68030", 0 },
388 { m68040, "68040", 0 },
389 { m68060, "68060", 0 },
390 { cpu32, "cpu32", 0 },
391 { m68881, "68881", 0 },
392 { m68851, "68851", 0 },
393 { mcf5200, "5200", 0 },
394 /* Aliases (effectively, so far as gas is concerned) for the above
395 cpus. */
396 { m68020, "68k", 1 },
397 { m68000, "68008", 1 },
398 { m68000, "68302", 1 },
399 { m68000, "68306", 1 },
400 { m68000, "68307", 1 },
401 { m68000, "68322", 1 },
402 { m68000, "68356", 1 },
403 { m68000, "68ec000", 1 },
404 { m68000, "68hc000", 1 },
405 { m68000, "68hc001", 1 },
406 { m68020, "68ec020", 1 },
407 { m68030, "68ec030", 1 },
408 { m68040, "68ec040", 1 },
409 { m68060, "68ec060", 1 },
410 { cpu32, "68330", 1 },
411 { cpu32, "68331", 1 },
412 { cpu32, "68332", 1 },
413 { cpu32, "68333", 1 },
414 { cpu32, "68334", 1 },
415 { cpu32, "68336", 1 },
416 { cpu32, "68340", 1 },
417 { cpu32, "68341", 1 },
418 { cpu32, "68349", 1 },
419 { cpu32, "68360", 1 },
420 { m68881, "68882", 1 },
421 };
422
423 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
424
425 /* BCC68000 is for patching in an extra jmp instruction for long offsets
426 on the 68000. The 68000 doesn't support long branches with branchs */
427
428 /* This table desribes how you change sizes for the various types of variable
429 size expressions. This version only supports two kinds. */
430
431 /* Note that calls to frag_var need to specify the maximum expansion
432 needed; this is currently 10 bytes for DBCC. */
433
434 /* The fields are:
435 How far Forward this mode will reach:
436 How far Backward this mode will reach:
437 How many bytes this mode will add to the size of the frag
438 Which mode to go to if the offset won't fit in this one
439 */
440 relax_typeS md_relax_table[] =
441 {
442 {1, 1, 0, 0}, /* First entries aren't used */
443 {1, 1, 0, 0}, /* For no good reason except */
444 {1, 1, 0, 0}, /* that the VAX doesn't either */
445 {1, 1, 0, 0},
446
447 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
448 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
449 {0, 0, 4, 0},
450 {1, 1, 0, 0},
451
452 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
453 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
454 {0, 0, 4, 0},
455 {1, 1, 0, 0},
456
457 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
458 {(32767), (-32768), 2, TAB (PCREL, LONG)},
459 {0, 0, 4, 0},
460 {1, 1, 0, 0},
461
462 {(127), (-128), 0, TAB (BCC68000, SHORT)},
463 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
464 {0, 0, 6, 0}, /* jmp long space */
465 {1, 1, 0, 0},
466
467 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (DBCC, LONG)},
469 {0, 0, 10, 0}, /* bra/jmp long space */
470 {1, 1, 0, 0},
471
472 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
473 {32767, -32768, 2, TAB (PCLEA, LONG)},
474 {0, 0, 6, 0},
475 {1, 1, 0, 0},
476
477 /* For, e.g., jmp pcrel indexed. */
478 {125, -130, 0, TAB (PCINDEX, SHORT)},
479 {32765, -32770, 2, TAB (PCINDEX, LONG)},
480 {0, 0, 4, 0},
481 {1, 1, 0, 0},
482 };
483
484 /* These are the machine dependent pseudo-ops. These are included so
485 the assembler can work on the output from the SUN C compiler, which
486 generates these.
487 */
488
489 /* This table describes all the machine specific pseudo-ops the assembler
490 has to support. The fields are:
491 pseudo-op name without dot
492 function to call to execute this pseudo-op
493 Integer arg to pass to the function
494 */
495 const pseudo_typeS md_pseudo_table[] =
496 {
497 {"data1", s_data1, 0},
498 {"data2", s_data2, 0},
499 {"bss", s_bss, 0},
500 {"even", s_even, 0},
501 {"skip", s_space, 0},
502 {"proc", s_proc, 0},
503 #if defined (TE_SUN3) || defined (OBJ_ELF)
504 {"align", s_align_bytes, 0},
505 #endif
506 #ifdef OBJ_ELF
507 {"swbeg", s_ignore, 0},
508 #endif
509 {"extend", float_cons, 'x'},
510 {"ldouble", float_cons, 'x'},
511
512 /* The following pseudo-ops are supported for MRI compatibility. */
513 {"chip", s_chip, 0},
514 {"comline", s_space, 1},
515 {"fopt", s_fopt, 0},
516 {"mask2", s_ignore, 0},
517 {"opt", s_opt, 0},
518 {"reg", s_reg, 0},
519 {"restore", s_restore, 0},
520 {"save", s_save, 0},
521
522 {"if", s_mri_if, 0},
523 {"if.b", s_mri_if, 'b'},
524 {"if.w", s_mri_if, 'w'},
525 {"if.l", s_mri_if, 'l'},
526 {"else", s_mri_else, 0},
527 {"else.s", s_mri_else, 's'},
528 {"else.l", s_mri_else, 'l'},
529 {"endi", s_mri_endi, 0},
530 {"break", s_mri_break, 0},
531 {"break.s", s_mri_break, 's'},
532 {"break.l", s_mri_break, 'l'},
533 {"next", s_mri_next, 0},
534 {"next.s", s_mri_next, 's'},
535 {"next.l", s_mri_next, 'l'},
536 {"for", s_mri_for, 0},
537 {"for.b", s_mri_for, 'b'},
538 {"for.w", s_mri_for, 'w'},
539 {"for.l", s_mri_for, 'l'},
540 {"endf", s_mri_endf, 0},
541 {"repeat", s_mri_repeat, 0},
542 {"until", s_mri_until, 0},
543 {"until.b", s_mri_until, 'b'},
544 {"until.w", s_mri_until, 'w'},
545 {"until.l", s_mri_until, 'l'},
546 {"while", s_mri_while, 0},
547 {"while.b", s_mri_while, 'b'},
548 {"while.w", s_mri_while, 'w'},
549 {"while.l", s_mri_while, 'l'},
550 {"endw", s_mri_endw, 0},
551
552 {0, 0, 0}
553 };
554
555
556 /* The mote pseudo ops are put into the opcode table, since they
557 don't start with a . they look like opcodes to gas.
558 */
559
560 #ifdef M68KCOFF
561 extern void obj_coff_section PARAMS ((int));
562 #endif
563
564 CONST pseudo_typeS mote_pseudo_table[] =
565 {
566
567 {"dcl", cons, 4},
568 {"dc", cons, 2},
569 {"dcw", cons, 2},
570 {"dcb", cons, 1},
571
572 {"dsl", s_space, 4},
573 {"ds", s_space, 2},
574 {"dsw", s_space, 2},
575 {"dsb", s_space, 1},
576
577 {"xdef", s_globl, 0},
578 #ifdef OBJ_ELF
579 {"align", s_align_bytes, 0},
580 #else
581 {"align", s_align_ptwo, 0},
582 #endif
583 #ifdef M68KCOFF
584 {"sect", obj_coff_section, 0},
585 {"section", obj_coff_section, 0},
586 #endif
587 {0, 0, 0}
588 };
589
590 #define issbyte(x) ((x)>=-128 && (x)<=127)
591 #define isubyte(x) ((x)>=0 && (x)<=255)
592 #define issword(x) ((x)>=-32768 && (x)<=32767)
593 #define isuword(x) ((x)>=0 && (x)<=65535)
594
595 #define isbyte(x) ((x)>= -255 && (x)<=255)
596 #define isword(x) ((x)>=-65536 && (x)<=65535)
597 #define islong(x) (1)
598
599 extern char *input_line_pointer;
600
601 static char mklower_table[256];
602 #define mklower(c) (mklower_table[(unsigned char)(c)])
603 static char notend_table[256];
604 static char alt_notend_table[256];
605 #define notend(s) \
606 (! (notend_table[(unsigned char) *s] \
607 || (*s == ':' \
608 && alt_notend_table[(unsigned char) s[1]])))
609
610 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
611
612 #ifdef NO_PCREL_RELOCS
613
614 int
615 make_pcrel_absolute(fixP, add_number)
616 fixS *fixP;
617 long *add_number;
618 {
619 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
620
621 /* rewrite the PC relative instructions to absolute address ones.
622 * these are rumoured to be faster, and the apollo linker refuses
623 * to deal with the PC relative relocations.
624 */
625 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
626 {
627 opcode[0] = 0x4e;
628 opcode[1] = 0xf9;
629 }
630 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
631 {
632 opcode[0] = 0x4e;
633 opcode[1] = 0xb9;
634 }
635 else
636 as_fatal (_("Unknown PC relative instruction"));
637 *add_number -= 4;
638 return 0;
639 }
640
641 #endif /* NO_PCREL_RELOCS */
642
643 short
644 tc_coff_fix2rtype (fixP)
645 fixS *fixP;
646 {
647 if (fixP->fx_tcbit && fixP->fx_size == 4)
648 return R_RELLONG_NEG;
649 #ifdef NO_PCREL_RELOCS
650 know (fixP->fx_pcrel == 0);
651 return (fixP->fx_size == 1 ? R_RELBYTE
652 : fixP->fx_size == 2 ? R_DIR16
653 : R_DIR32);
654 #else
655 return (fixP->fx_pcrel ?
656 (fixP->fx_size == 1 ? R_PCRBYTE :
657 fixP->fx_size == 2 ? R_PCRWORD :
658 R_PCRLONG) :
659 (fixP->fx_size == 1 ? R_RELBYTE :
660 fixP->fx_size == 2 ? R_RELWORD :
661 R_RELLONG));
662 #endif
663 }
664
665 #endif
666
667 #ifdef OBJ_ELF
668
669 /* Compute the relocation code for a fixup of SIZE bytes, using pc
670 relative relocation if PCREL is non-zero. PIC says whether a special
671 pic relocation was requested. */
672
673 static bfd_reloc_code_real_type get_reloc_code
674 PARAMS ((int, int, enum pic_relocation));
675
676 static bfd_reloc_code_real_type
677 get_reloc_code (size, pcrel, pic)
678 int size;
679 int pcrel;
680 enum pic_relocation pic;
681 {
682 switch (pic)
683 {
684 case pic_got_pcrel:
685 switch (size)
686 {
687 case 1:
688 return BFD_RELOC_8_GOT_PCREL;
689 case 2:
690 return BFD_RELOC_16_GOT_PCREL;
691 case 4:
692 return BFD_RELOC_32_GOT_PCREL;
693 }
694 break;
695
696 case pic_got_off:
697 switch (size)
698 {
699 case 1:
700 return BFD_RELOC_8_GOTOFF;
701 case 2:
702 return BFD_RELOC_16_GOTOFF;
703 case 4:
704 return BFD_RELOC_32_GOTOFF;
705 }
706 break;
707
708 case pic_plt_pcrel:
709 switch (size)
710 {
711 case 1:
712 return BFD_RELOC_8_PLT_PCREL;
713 case 2:
714 return BFD_RELOC_16_PLT_PCREL;
715 case 4:
716 return BFD_RELOC_32_PLT_PCREL;
717 }
718 break;
719
720 case pic_plt_off:
721 switch (size)
722 {
723 case 1:
724 return BFD_RELOC_8_PLTOFF;
725 case 2:
726 return BFD_RELOC_16_PLTOFF;
727 case 4:
728 return BFD_RELOC_32_PLTOFF;
729 }
730 break;
731
732 case pic_none:
733 if (pcrel)
734 {
735 switch (size)
736 {
737 case 1:
738 return BFD_RELOC_8_PCREL;
739 case 2:
740 return BFD_RELOC_16_PCREL;
741 case 4:
742 return BFD_RELOC_32_PCREL;
743 }
744 }
745 else
746 {
747 switch (size)
748 {
749 case 1:
750 return BFD_RELOC_8;
751 case 2:
752 return BFD_RELOC_16;
753 case 4:
754 return BFD_RELOC_32;
755 }
756 }
757 }
758
759 if (pcrel)
760 {
761 if (pic == pic_none)
762 as_bad (_("Can not do %d byte pc-relative relocation"), size);
763 else
764 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
765 }
766 else
767 {
768 if (pic == pic_none)
769 as_bad (_("Can not do %d byte relocation"), size);
770 else
771 as_bad (_("Can not do %d byte pic relocation"), size);
772 }
773
774 return BFD_RELOC_NONE;
775 }
776
777 /* Here we decide which fixups can be adjusted to make them relative
778 to the beginning of the section instead of the symbol. Basically
779 we need to make sure that the dynamic relocations are done
780 correctly, so in some cases we force the original symbol to be
781 used. */
782 int
783 tc_m68k_fix_adjustable (fixP)
784 fixS *fixP;
785 {
786 /* Prevent all adjustments to global symbols. */
787 if (S_IS_EXTERNAL (fixP->fx_addsy)
788 || S_IS_WEAK (fixP->fx_addsy))
789 return 0;
790
791 /* adjust_reloc_syms doesn't know about the GOT */
792 switch (fixP->fx_r_type)
793 {
794 case BFD_RELOC_8_GOT_PCREL:
795 case BFD_RELOC_16_GOT_PCREL:
796 case BFD_RELOC_32_GOT_PCREL:
797 case BFD_RELOC_8_GOTOFF:
798 case BFD_RELOC_16_GOTOFF:
799 case BFD_RELOC_32_GOTOFF:
800 case BFD_RELOC_8_PLT_PCREL:
801 case BFD_RELOC_16_PLT_PCREL:
802 case BFD_RELOC_32_PLT_PCREL:
803 case BFD_RELOC_8_PLTOFF:
804 case BFD_RELOC_16_PLTOFF:
805 case BFD_RELOC_32_PLTOFF:
806 return 0;
807
808 case BFD_RELOC_VTABLE_INHERIT:
809 case BFD_RELOC_VTABLE_ENTRY:
810 return 0;
811
812 default:
813 return 1;
814 }
815 }
816
817 #else /* !OBJ_ELF */
818
819 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
820
821 #endif /* OBJ_ELF */
822
823 #ifdef BFD_ASSEMBLER
824
825 arelent *
826 tc_gen_reloc (section, fixp)
827 asection *section;
828 fixS *fixp;
829 {
830 arelent *reloc;
831 bfd_reloc_code_real_type code;
832
833 if (fixp->fx_tcbit)
834 abort ();
835
836 if (fixp->fx_r_type != BFD_RELOC_NONE)
837 {
838 code = fixp->fx_r_type;
839
840 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
841 that fixup_segment converted a non-PC relative reloc into a
842 PC relative reloc. In such a case, we need to convert the
843 reloc code. */
844 if (fixp->fx_pcrel)
845 {
846 switch (code)
847 {
848 case BFD_RELOC_8:
849 code = BFD_RELOC_8_PCREL;
850 break;
851 case BFD_RELOC_16:
852 code = BFD_RELOC_16_PCREL;
853 break;
854 case BFD_RELOC_32:
855 code = BFD_RELOC_32_PCREL;
856 break;
857 case BFD_RELOC_8_PCREL:
858 case BFD_RELOC_16_PCREL:
859 case BFD_RELOC_32_PCREL:
860 case BFD_RELOC_8_GOT_PCREL:
861 case BFD_RELOC_16_GOT_PCREL:
862 case BFD_RELOC_32_GOT_PCREL:
863 case BFD_RELOC_8_GOTOFF:
864 case BFD_RELOC_16_GOTOFF:
865 case BFD_RELOC_32_GOTOFF:
866 case BFD_RELOC_8_PLT_PCREL:
867 case BFD_RELOC_16_PLT_PCREL:
868 case BFD_RELOC_32_PLT_PCREL:
869 case BFD_RELOC_8_PLTOFF:
870 case BFD_RELOC_16_PLTOFF:
871 case BFD_RELOC_32_PLTOFF:
872 break;
873 default:
874 as_bad_where (fixp->fx_file, fixp->fx_line,
875 _("Cannot make %s relocation PC relative"),
876 bfd_get_reloc_code_name (code));
877 }
878 }
879 }
880 else
881 {
882 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
883 switch (F (fixp->fx_size, fixp->fx_pcrel))
884 {
885 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
886 MAP (1, 0, BFD_RELOC_8);
887 MAP (2, 0, BFD_RELOC_16);
888 MAP (4, 0, BFD_RELOC_32);
889 MAP (1, 1, BFD_RELOC_8_PCREL);
890 MAP (2, 1, BFD_RELOC_16_PCREL);
891 MAP (4, 1, BFD_RELOC_32_PCREL);
892 default:
893 abort ();
894 }
895 }
896 #undef F
897 #undef MAP
898
899 reloc = (arelent *) xmalloc (sizeof (arelent));
900 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
901 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
902 #ifndef OBJ_ELF
903 if (fixp->fx_pcrel)
904 reloc->addend = fixp->fx_addnumber;
905 else
906 reloc->addend = 0;
907 #else
908 if (!fixp->fx_pcrel)
909 reloc->addend = fixp->fx_addnumber;
910 else
911 reloc->addend = (section->vma
912 + (fixp->fx_pcrel_adjust == 64
913 ? -1 : fixp->fx_pcrel_adjust)
914 + fixp->fx_addnumber
915 + md_pcrel_from (fixp));
916 #endif
917
918 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
919 assert (reloc->howto != 0);
920
921 return reloc;
922 }
923
924 #endif /* BFD_ASSEMBLER */
925
926 /* Return zero if the reference to SYMBOL from within the same segment may
927 be relaxed. */
928 #ifdef OBJ_ELF
929
930 /* On an ELF system, we can't relax an externally visible symbol,
931 because it may be overridden by a shared library. However, if
932 TARGET_OS is "elf", then we presume that we are assembling for an
933 embedded system, in which case we don't have to worry about shared
934 libraries, and we can relax anything. */
935
936 #define relaxable_symbol(symbol) \
937 (strcmp (TARGET_OS, "elf") == 0 \
938 || (! S_IS_EXTERNAL (symbol) \
939 && ! S_IS_WEAK (symbol)))
940
941 #else
942
943 #define relaxable_symbol(symbol) 1
944
945 #endif
946
947 /* Handle of the OPCODE hash table. NULL means any use before
948 m68k_ip_begin() will crash. */
949 static struct hash_control *op_hash;
950 \f
951 /* Assemble an m68k instruction. */
952
953 static void
954 m68k_ip (instring)
955 char *instring;
956 {
957 register char *p;
958 register struct m68k_op *opP;
959 register const struct m68k_incant *opcode;
960 register const char *s;
961 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
962 char *pdot, *pdotmove;
963 enum m68k_size siz1, siz2;
964 char c;
965 int losing;
966 int opsfound;
967 LITTLENUM_TYPE words[6];
968 LITTLENUM_TYPE *wordp;
969 unsigned long ok_arch = 0;
970
971 if (*instring == ' ')
972 instring++; /* skip leading whitespace */
973
974 /* Scan up to end of operation-code, which MUST end in end-of-string
975 or exactly 1 space. */
976 pdot = 0;
977 for (p = instring; *p != '\0'; p++)
978 {
979 if (*p == ' ')
980 break;
981 if (*p == '.')
982 pdot = p;
983 }
984
985 if (p == instring)
986 {
987 the_ins.error = _("No operator");
988 return;
989 }
990
991 /* p now points to the end of the opcode name, probably whitespace.
992 Make sure the name is null terminated by clobbering the
993 whitespace, look it up in the hash table, then fix it back.
994 Remove a dot, first, since the opcode tables have none. */
995 if (pdot != NULL)
996 {
997 for (pdotmove = pdot; pdotmove < p; pdotmove++)
998 *pdotmove = pdotmove[1];
999 p--;
1000 }
1001
1002 c = *p;
1003 *p = '\0';
1004 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1005 *p = c;
1006
1007 if (pdot != NULL)
1008 {
1009 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1010 *pdotmove = pdotmove[-1];
1011 *pdot = '.';
1012 ++p;
1013 }
1014
1015 if (opcode == NULL)
1016 {
1017 the_ins.error = _("Unknown operator");
1018 return;
1019 }
1020
1021 /* found a legitimate opcode, start matching operands */
1022 while (*p == ' ')
1023 ++p;
1024
1025 if (opcode->m_operands == 0)
1026 {
1027 char *old = input_line_pointer;
1028 *old = '\n';
1029 input_line_pointer = p;
1030 /* Ahh - it's a motorola style psuedo op */
1031 mote_pseudo_table[opcode->m_opnum].poc_handler
1032 (mote_pseudo_table[opcode->m_opnum].poc_val);
1033 input_line_pointer = old;
1034 *old = 0;
1035
1036 return;
1037 }
1038
1039 if (flag_mri && opcode->m_opnum == 0)
1040 {
1041 /* In MRI mode, random garbage is allowed after an instruction
1042 which accepts no operands. */
1043 the_ins.args = opcode->m_operands;
1044 the_ins.numargs = opcode->m_opnum;
1045 the_ins.numo = opcode->m_codenum;
1046 the_ins.opcode[0] = getone (opcode);
1047 the_ins.opcode[1] = gettwo (opcode);
1048 return;
1049 }
1050
1051 for (opP = &the_ins.operands[0]; *p; opP++)
1052 {
1053 p = crack_operand (p, opP);
1054
1055 if (opP->error)
1056 {
1057 the_ins.error = opP->error;
1058 return;
1059 }
1060 }
1061
1062 opsfound = opP - &the_ins.operands[0];
1063
1064 /* This ugly hack is to support the floating pt opcodes in their
1065 standard form. Essentially, we fake a first enty of type COP#1 */
1066 if (opcode->m_operands[0] == 'I')
1067 {
1068 int n;
1069
1070 for (n = opsfound; n > 0; --n)
1071 the_ins.operands[n] = the_ins.operands[n - 1];
1072
1073 memset ((char *) (&the_ins.operands[0]), '\0',
1074 sizeof (the_ins.operands[0]));
1075 the_ins.operands[0].mode = CONTROL;
1076 the_ins.operands[0].reg = m68k_float_copnum;
1077 opsfound++;
1078 }
1079
1080 /* We've got the operands. Find an opcode that'll accept them */
1081 for (losing = 0;;)
1082 {
1083 /* If we didn't get the right number of ops, or we have no
1084 common model with this pattern then reject this pattern. */
1085
1086 ok_arch |= opcode->m_arch;
1087 if (opsfound != opcode->m_opnum
1088 || ((opcode->m_arch & current_architecture) == 0))
1089 ++losing;
1090 else
1091 {
1092 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1093 *s && !losing;
1094 s += 2, opP++)
1095 {
1096 /* Warning: this switch is huge! */
1097 /* I've tried to organize the cases into this order:
1098 non-alpha first, then alpha by letter. Lower-case
1099 goes directly before uppercase counterpart. */
1100 /* Code with multiple case ...: gets sorted by the lowest
1101 case ... it belongs to. I hope this makes sense. */
1102 switch (*s)
1103 {
1104 case '!':
1105 switch (opP->mode)
1106 {
1107 case IMMED:
1108 case DREG:
1109 case AREG:
1110 case FPREG:
1111 case CONTROL:
1112 case AINC:
1113 case ADEC:
1114 case REGLST:
1115 losing++;
1116 break;
1117 default:
1118 break;
1119 }
1120 break;
1121
1122 case '<':
1123 switch (opP->mode)
1124 {
1125 case DREG:
1126 case AREG:
1127 case FPREG:
1128 case CONTROL:
1129 case IMMED:
1130 case ADEC:
1131 case REGLST:
1132 losing++;
1133 break;
1134 default:
1135 break;
1136 }
1137 break;
1138
1139 case '>':
1140 switch (opP->mode)
1141 {
1142 case DREG:
1143 case AREG:
1144 case FPREG:
1145 case CONTROL:
1146 case IMMED:
1147 case AINC:
1148 case REGLST:
1149 losing++;
1150 break;
1151 case ABSL:
1152 break;
1153 default:
1154 if (opP->reg == PC
1155 || opP->reg == ZPC)
1156 losing++;
1157 break;
1158 }
1159 break;
1160
1161 case 'm':
1162 switch (opP->mode)
1163 {
1164 case DREG:
1165 case AREG:
1166 case AINDR:
1167 case AINC:
1168 case ADEC:
1169 break;
1170 default:
1171 losing++;
1172 }
1173 break;
1174
1175 case 'n':
1176 switch (opP->mode)
1177 {
1178 case DISP:
1179 break;
1180 default:
1181 losing++;
1182 }
1183 break;
1184
1185 case 'o':
1186 switch (opP->mode)
1187 {
1188 case BASE:
1189 case ABSL:
1190 case IMMED:
1191 break;
1192 default:
1193 losing++;
1194 }
1195 break;
1196
1197 case 'p':
1198 switch (opP->mode)
1199 {
1200 case DREG:
1201 case AREG:
1202 case AINDR:
1203 case AINC:
1204 case ADEC:
1205 break;
1206 case DISP:
1207 if (opP->reg == PC || opP->reg == ZPC)
1208 losing++;
1209 break;
1210 default:
1211 losing++;
1212 }
1213 break;
1214
1215 case 'q':
1216 switch (opP->mode)
1217 {
1218 case DREG:
1219 case AINDR:
1220 case AINC:
1221 case ADEC:
1222 break;
1223 case DISP:
1224 if (opP->reg == PC || opP->reg == ZPC)
1225 losing++;
1226 break;
1227 default:
1228 losing++;
1229 break;
1230 }
1231 break;
1232
1233 case 'v':
1234 switch (opP->mode)
1235 {
1236 case DREG:
1237 case AINDR:
1238 case AINC:
1239 case ADEC:
1240 case ABSL:
1241 break;
1242 case DISP:
1243 if (opP->reg == PC || opP->reg == ZPC)
1244 losing++;
1245 break;
1246 default:
1247 losing++;
1248 break;
1249 }
1250 break;
1251
1252 case '#':
1253 if (opP->mode != IMMED)
1254 losing++;
1255 else if (s[1] == 'b'
1256 && ! isvar (&opP->disp)
1257 && (opP->disp.exp.X_op != O_constant
1258 || ! isbyte (opP->disp.exp.X_add_number)))
1259 losing++;
1260 else if (s[1] == 'B'
1261 && ! isvar (&opP->disp)
1262 && (opP->disp.exp.X_op != O_constant
1263 || ! issbyte (opP->disp.exp.X_add_number)))
1264 losing++;
1265 else if (s[1] == 'w'
1266 && ! isvar (&opP->disp)
1267 && (opP->disp.exp.X_op != O_constant
1268 || ! isword (opP->disp.exp.X_add_number)))
1269 losing++;
1270 else if (s[1] == 'W'
1271 && ! isvar (&opP->disp)
1272 && (opP->disp.exp.X_op != O_constant
1273 || ! issword (opP->disp.exp.X_add_number)))
1274 losing++;
1275 break;
1276
1277 case '^':
1278 case 'T':
1279 if (opP->mode != IMMED)
1280 losing++;
1281 break;
1282
1283 case '$':
1284 if (opP->mode == AREG
1285 || opP->mode == CONTROL
1286 || opP->mode == FPREG
1287 || opP->mode == IMMED
1288 || opP->mode == REGLST
1289 || (opP->mode != ABSL
1290 && (opP->reg == PC
1291 || opP->reg == ZPC)))
1292 losing++;
1293 break;
1294
1295 case '%':
1296 if (opP->mode == CONTROL
1297 || opP->mode == FPREG
1298 || opP->mode == REGLST
1299 || opP->mode == IMMED
1300 || (opP->mode != ABSL
1301 && (opP->reg == PC
1302 || opP->reg == ZPC)))
1303 losing++;
1304 break;
1305
1306 case '&':
1307 switch (opP->mode)
1308 {
1309 case DREG:
1310 case AREG:
1311 case FPREG:
1312 case CONTROL:
1313 case IMMED:
1314 case AINC:
1315 case ADEC:
1316 case REGLST:
1317 losing++;
1318 break;
1319 case ABSL:
1320 break;
1321 default:
1322 if (opP->reg == PC
1323 || opP->reg == ZPC)
1324 losing++;
1325 break;
1326 }
1327 break;
1328
1329 case '*':
1330 if (opP->mode == CONTROL
1331 || opP->mode == FPREG
1332 || opP->mode == REGLST)
1333 losing++;
1334 break;
1335
1336 case '+':
1337 if (opP->mode != AINC)
1338 losing++;
1339 break;
1340
1341 case '-':
1342 if (opP->mode != ADEC)
1343 losing++;
1344 break;
1345
1346 case '/':
1347 switch (opP->mode)
1348 {
1349 case AREG:
1350 case CONTROL:
1351 case FPREG:
1352 case AINC:
1353 case ADEC:
1354 case IMMED:
1355 case REGLST:
1356 losing++;
1357 break;
1358 default:
1359 break;
1360 }
1361 break;
1362
1363 case ';':
1364 switch (opP->mode)
1365 {
1366 case AREG:
1367 case CONTROL:
1368 case FPREG:
1369 case REGLST:
1370 losing++;
1371 break;
1372 default:
1373 break;
1374 }
1375 break;
1376
1377 case '?':
1378 switch (opP->mode)
1379 {
1380 case AREG:
1381 case CONTROL:
1382 case FPREG:
1383 case AINC:
1384 case ADEC:
1385 case IMMED:
1386 case REGLST:
1387 losing++;
1388 break;
1389 case ABSL:
1390 break;
1391 default:
1392 if (opP->reg == PC || opP->reg == ZPC)
1393 losing++;
1394 break;
1395 }
1396 break;
1397
1398 case '@':
1399 switch (opP->mode)
1400 {
1401 case AREG:
1402 case CONTROL:
1403 case FPREG:
1404 case IMMED:
1405 case REGLST:
1406 losing++;
1407 break;
1408 default:
1409 break;
1410 }
1411 break;
1412
1413 case '~': /* For now! (JF FOO is this right?) */
1414 switch (opP->mode)
1415 {
1416 case DREG:
1417 case AREG:
1418 case CONTROL:
1419 case FPREG:
1420 case IMMED:
1421 case REGLST:
1422 losing++;
1423 break;
1424 case ABSL:
1425 break;
1426 default:
1427 if (opP->reg == PC
1428 || opP->reg == ZPC)
1429 losing++;
1430 break;
1431 }
1432 break;
1433
1434 case '3':
1435 if (opP->mode != CONTROL
1436 || (opP->reg != TT0 && opP->reg != TT1))
1437 losing++;
1438 break;
1439
1440 case 'A':
1441 if (opP->mode != AREG)
1442 losing++;
1443 break;
1444
1445 case 'a':
1446 if (opP->mode != AINDR)
1447 ++losing;
1448 break;
1449
1450 case 'B': /* FOO */
1451 if (opP->mode != ABSL
1452 || (flag_long_jumps
1453 && strncmp (instring, "jbsr", 4) == 0))
1454 losing++;
1455 break;
1456
1457 case 'C':
1458 if (opP->mode != CONTROL || opP->reg != CCR)
1459 losing++;
1460 break;
1461
1462 case 'd':
1463 if (opP->mode != DISP
1464 || opP->reg < ADDR0
1465 || opP->reg > ADDR7)
1466 losing++;
1467 break;
1468
1469 case 'D':
1470 if (opP->mode != DREG)
1471 losing++;
1472 break;
1473
1474 case 'F':
1475 if (opP->mode != FPREG)
1476 losing++;
1477 break;
1478
1479 case 'I':
1480 if (opP->mode != CONTROL
1481 || opP->reg < COP0
1482 || opP->reg > COP7)
1483 losing++;
1484 break;
1485
1486 case 'J':
1487 if (opP->mode != CONTROL
1488 || opP->reg < USP
1489 || opP->reg > last_movec_reg)
1490 losing++;
1491 else
1492 {
1493 const enum m68k_register *rp;
1494 for (rp = control_regs; *rp; rp++)
1495 if (*rp == opP->reg)
1496 break;
1497 if (*rp == 0)
1498 losing++;
1499 }
1500 break;
1501
1502 case 'k':
1503 if (opP->mode != IMMED)
1504 losing++;
1505 break;
1506
1507 case 'l':
1508 case 'L':
1509 if (opP->mode == DREG
1510 || opP->mode == AREG
1511 || opP->mode == FPREG)
1512 {
1513 if (s[1] == '8')
1514 losing++;
1515 else
1516 {
1517 switch (opP->mode)
1518 {
1519 case DREG:
1520 opP->mask = 1 << (opP->reg - DATA0);
1521 break;
1522 case AREG:
1523 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1524 break;
1525 case FPREG:
1526 opP->mask = 1 << (opP->reg - FP0 + 16);
1527 break;
1528 default:
1529 abort ();
1530 }
1531 opP->mode = REGLST;
1532 }
1533 }
1534 else if (opP->mode == CONTROL)
1535 {
1536 if (s[1] != '8')
1537 losing++;
1538 else
1539 {
1540 switch (opP->reg)
1541 {
1542 case FPI:
1543 opP->mask = 1 << 24;
1544 break;
1545 case FPS:
1546 opP->mask = 1 << 25;
1547 break;
1548 case FPC:
1549 opP->mask = 1 << 26;
1550 break;
1551 default:
1552 losing++;
1553 break;
1554 }
1555 opP->mode = REGLST;
1556 }
1557 }
1558 else if (opP->mode != REGLST)
1559 losing++;
1560 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1561 losing++;
1562 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1563 losing++;
1564 break;
1565
1566 case 'M':
1567 if (opP->mode != IMMED)
1568 losing++;
1569 else if (opP->disp.exp.X_op != O_constant
1570 || ! issbyte (opP->disp.exp.X_add_number))
1571 losing++;
1572 else if (! m68k_quick
1573 && instring[3] != 'q'
1574 && instring[4] != 'q')
1575 losing++;
1576 break;
1577
1578 case 'O':
1579 if (opP->mode != DREG
1580 && opP->mode != IMMED
1581 && opP->mode != ABSL)
1582 losing++;
1583 break;
1584
1585 case 'Q':
1586 if (opP->mode != IMMED)
1587 losing++;
1588 else if (opP->disp.exp.X_op != O_constant
1589 || opP->disp.exp.X_add_number < 1
1590 || opP->disp.exp.X_add_number > 8)
1591 losing++;
1592 else if (! m68k_quick
1593 && (strncmp (instring, "add", 3) == 0
1594 || strncmp (instring, "sub", 3) == 0)
1595 && instring[3] != 'q')
1596 losing++;
1597 break;
1598
1599 case 'R':
1600 if (opP->mode != DREG && opP->mode != AREG)
1601 losing++;
1602 break;
1603
1604 case 'r':
1605 if (opP->mode != AINDR
1606 && (opP->mode != BASE
1607 || (opP->reg != 0
1608 && opP->reg != ZADDR0)
1609 || opP->disp.exp.X_op != O_absent
1610 || ((opP->index.reg < DATA0
1611 || opP->index.reg > DATA7)
1612 && (opP->index.reg < ADDR0
1613 || opP->index.reg > ADDR7))
1614 || opP->index.size != SIZE_UNSPEC
1615 || opP->index.scale != 1))
1616 losing++;
1617 break;
1618
1619 case 's':
1620 if (opP->mode != CONTROL
1621 || ! (opP->reg == FPI
1622 || opP->reg == FPS
1623 || opP->reg == FPC))
1624 losing++;
1625 break;
1626
1627 case 'S':
1628 if (opP->mode != CONTROL || opP->reg != SR)
1629 losing++;
1630 break;
1631
1632 case 't':
1633 if (opP->mode != IMMED)
1634 losing++;
1635 else if (opP->disp.exp.X_op != O_constant
1636 || opP->disp.exp.X_add_number < 0
1637 || opP->disp.exp.X_add_number > 7)
1638 losing++;
1639 break;
1640
1641 case 'U':
1642 if (opP->mode != CONTROL || opP->reg != USP)
1643 losing++;
1644 break;
1645
1646 /* JF these are out of order. We could put them
1647 in order if we were willing to put up with
1648 bunches of #ifdef m68851s in the code.
1649
1650 Don't forget that you need these operands
1651 to use 68030 MMU instructions. */
1652 #ifndef NO_68851
1653 /* Memory addressing mode used by pflushr */
1654 case '|':
1655 if (opP->mode == CONTROL
1656 || opP->mode == FPREG
1657 || opP->mode == DREG
1658 || opP->mode == AREG
1659 || opP->mode == REGLST)
1660 losing++;
1661 /* We should accept immediate operands, but they
1662 supposedly have to be quad word, and we don't
1663 handle that. I would like to see what a Motorola
1664 assembler does before doing something here. */
1665 if (opP->mode == IMMED)
1666 losing++;
1667 break;
1668
1669 case 'f':
1670 if (opP->mode != CONTROL
1671 || (opP->reg != SFC && opP->reg != DFC))
1672 losing++;
1673 break;
1674
1675 case '0':
1676 if (opP->mode != CONTROL || opP->reg != TC)
1677 losing++;
1678 break;
1679
1680 case '1':
1681 if (opP->mode != CONTROL || opP->reg != AC)
1682 losing++;
1683 break;
1684
1685 case '2':
1686 if (opP->mode != CONTROL
1687 || (opP->reg != CAL
1688 && opP->reg != VAL
1689 && opP->reg != SCC))
1690 losing++;
1691 break;
1692
1693 case 'V':
1694 if (opP->mode != CONTROL
1695 || opP->reg != VAL)
1696 losing++;
1697 break;
1698
1699 case 'W':
1700 if (opP->mode != CONTROL
1701 || (opP->reg != DRP
1702 && opP->reg != SRP
1703 && opP->reg != CRP))
1704 losing++;
1705 break;
1706
1707 case 'X':
1708 if (opP->mode != CONTROL
1709 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1710 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1711 losing++;
1712 break;
1713
1714 case 'Y':
1715 if (opP->mode != CONTROL || opP->reg != PSR)
1716 losing++;
1717 break;
1718
1719 case 'Z':
1720 if (opP->mode != CONTROL || opP->reg != PCSR)
1721 losing++;
1722 break;
1723 #endif
1724 case 'c':
1725 if (opP->mode != CONTROL
1726 || (opP->reg != NC
1727 && opP->reg != IC
1728 && opP->reg != DC
1729 && opP->reg != BC))
1730 {
1731 losing++;
1732 } /* not a cache specifier. */
1733 break;
1734
1735 case '_':
1736 if (opP->mode != ABSL)
1737 ++losing;
1738 break;
1739
1740 default:
1741 abort ();
1742 } /* switch on type of operand */
1743
1744 if (losing)
1745 break;
1746 } /* for each operand */
1747 } /* if immediately wrong */
1748
1749 if (!losing)
1750 {
1751 break;
1752 } /* got it. */
1753
1754 opcode = opcode->m_next;
1755
1756 if (!opcode)
1757 {
1758 if (ok_arch
1759 && !(ok_arch & current_architecture))
1760 {
1761 char buf[200], *cp;
1762
1763 strcpy (buf,
1764 _("invalid instruction for this architecture; needs "));
1765 cp = buf + strlen (buf);
1766 switch (ok_arch)
1767 {
1768 case mfloat:
1769 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1770 break;
1771 case mmmu:
1772 strcpy (cp, _("mmu (68030 or 68851)"));
1773 break;
1774 case m68020up:
1775 strcpy (cp, _("68020 or higher"));
1776 break;
1777 case m68000up:
1778 strcpy (cp, _("68000 or higher"));
1779 break;
1780 case m68010up:
1781 strcpy (cp, _("68010 or higher"));
1782 break;
1783 default:
1784 {
1785 int got_one = 0, idx;
1786 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1787 idx++)
1788 {
1789 if ((archs[idx].arch & ok_arch)
1790 && ! archs[idx].alias)
1791 {
1792 if (got_one)
1793 {
1794 strcpy (cp, " or ");
1795 cp += strlen (cp);
1796 }
1797 got_one = 1;
1798 strcpy (cp, archs[idx].name);
1799 cp += strlen (cp);
1800 }
1801 }
1802 }
1803 }
1804 cp = xmalloc (strlen (buf) + 1);
1805 strcpy (cp, buf);
1806 the_ins.error = cp;
1807 }
1808 else
1809 the_ins.error = _("operands mismatch");
1810 return;
1811 } /* Fell off the end */
1812
1813 losing = 0;
1814 }
1815
1816 /* now assemble it */
1817
1818 the_ins.args = opcode->m_operands;
1819 the_ins.numargs = opcode->m_opnum;
1820 the_ins.numo = opcode->m_codenum;
1821 the_ins.opcode[0] = getone (opcode);
1822 the_ins.opcode[1] = gettwo (opcode);
1823
1824 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1825 {
1826 /* This switch is a doozy.
1827 Watch the first step; its a big one! */
1828 switch (s[0])
1829 {
1830
1831 case '*':
1832 case '~':
1833 case '%':
1834 case ';':
1835 case '@':
1836 case '!':
1837 case '&':
1838 case '$':
1839 case '?':
1840 case '/':
1841 case '<':
1842 case '>':
1843 case 'm':
1844 case 'n':
1845 case 'o':
1846 case 'p':
1847 case 'q':
1848 case 'v':
1849 #ifndef NO_68851
1850 case '|':
1851 #endif
1852 switch (opP->mode)
1853 {
1854 case IMMED:
1855 tmpreg = 0x3c; /* 7.4 */
1856 if (strchr ("bwl", s[1]))
1857 nextword = get_num (&opP->disp, 80);
1858 else
1859 nextword = get_num (&opP->disp, 0);
1860 if (isvar (&opP->disp))
1861 add_fix (s[1], &opP->disp, 0, 0);
1862 switch (s[1])
1863 {
1864 case 'b':
1865 if (!isbyte (nextword))
1866 opP->error = _("operand out of range");
1867 addword (nextword);
1868 baseo = 0;
1869 break;
1870 case 'w':
1871 if (!isword (nextword))
1872 opP->error = _("operand out of range");
1873 addword (nextword);
1874 baseo = 0;
1875 break;
1876 case 'W':
1877 if (!issword (nextword))
1878 opP->error = _("operand out of range");
1879 addword (nextword);
1880 baseo = 0;
1881 break;
1882 case 'l':
1883 addword (nextword >> 16);
1884 addword (nextword);
1885 baseo = 0;
1886 break;
1887
1888 case 'f':
1889 baseo = 2;
1890 outro = 8;
1891 break;
1892 case 'F':
1893 baseo = 4;
1894 outro = 11;
1895 break;
1896 case 'x':
1897 baseo = 6;
1898 outro = 15;
1899 break;
1900 case 'p':
1901 baseo = 6;
1902 outro = -1;
1903 break;
1904 default:
1905 abort ();
1906 }
1907 if (!baseo)
1908 break;
1909
1910 /* We gotta put out some float */
1911 if (op (&opP->disp) != O_big)
1912 {
1913 valueT val;
1914 int gencnt;
1915
1916 /* Can other cases happen here? */
1917 if (op (&opP->disp) != O_constant)
1918 abort ();
1919
1920 val = (valueT) offs (&opP->disp);
1921 gencnt = 0;
1922 do
1923 {
1924 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1925 val >>= LITTLENUM_NUMBER_OF_BITS;
1926 ++gencnt;
1927 }
1928 while (val != 0);
1929 offs (&opP->disp) = gencnt;
1930 }
1931 if (offs (&opP->disp) > 0)
1932 {
1933 if (offs (&opP->disp) > baseo)
1934 {
1935 as_warn (_("Bignum too big for %c format; truncated"),
1936 s[1]);
1937 offs (&opP->disp) = baseo;
1938 }
1939 baseo -= offs (&opP->disp);
1940 while (baseo--)
1941 addword (0);
1942 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1943 offs (&opP->disp)--;
1944 --wordp)
1945 addword (*wordp);
1946 break;
1947 }
1948 gen_to_words (words, baseo, (long) outro);
1949 for (wordp = words; baseo--; wordp++)
1950 addword (*wordp);
1951 break;
1952 case DREG:
1953 tmpreg = opP->reg - DATA; /* 0.dreg */
1954 break;
1955 case AREG:
1956 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1957 break;
1958 case AINDR:
1959 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1960 break;
1961 case ADEC:
1962 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1963 break;
1964 case AINC:
1965 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1966 break;
1967 case DISP:
1968
1969 nextword = get_num (&opP->disp, 80);
1970
1971 if (opP->reg == PC
1972 && ! isvar (&opP->disp)
1973 && m68k_abspcadd)
1974 {
1975 opP->disp.exp.X_op = O_symbol;
1976 #ifndef BFD_ASSEMBLER
1977 opP->disp.exp.X_add_symbol = &abs_symbol;
1978 #else
1979 opP->disp.exp.X_add_symbol =
1980 section_symbol (absolute_section);
1981 #endif
1982 }
1983
1984 /* Force into index mode. Hope this works */
1985
1986 /* We do the first bit for 32-bit displacements, and the
1987 second bit for 16 bit ones. It is possible that we
1988 should make the default be WORD instead of LONG, but
1989 I think that'd break GCC, so we put up with a little
1990 inefficiency for the sake of working output. */
1991
1992 if (!issword (nextword)
1993 || (isvar (&opP->disp)
1994 && ((opP->disp.size == SIZE_UNSPEC
1995 && flag_short_refs == 0
1996 && cpu_of_arch (current_architecture) >= m68020
1997 && cpu_of_arch (current_architecture) != mcf5200)
1998 || opP->disp.size == SIZE_LONG)))
1999 {
2000 if (cpu_of_arch (current_architecture) < m68020
2001 || cpu_of_arch (current_architecture) == mcf5200)
2002 opP->error =
2003 _("displacement too large for this architecture; needs 68020 or higher");
2004 if (opP->reg == PC)
2005 tmpreg = 0x3B; /* 7.3 */
2006 else
2007 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2008 if (isvar (&opP->disp))
2009 {
2010 if (opP->reg == PC)
2011 {
2012 if (opP->disp.size == SIZE_LONG
2013 #ifdef OBJ_ELF
2014 /* If the displacement needs pic
2015 relocation it cannot be relaxed. */
2016 || opP->disp.pic_reloc != pic_none
2017 #endif
2018 )
2019 {
2020 addword (0x0170);
2021 add_fix ('l', &opP->disp, 1, 2);
2022 }
2023 else
2024 {
2025 add_frag (adds (&opP->disp),
2026 offs (&opP->disp),
2027 TAB (PCLEA, SZ_UNDEF));
2028 break;
2029 }
2030 }
2031 else
2032 {
2033 addword (0x0170);
2034 add_fix ('l', &opP->disp, 0, 0);
2035 }
2036 }
2037 else
2038 addword (0x0170);
2039 addword (nextword >> 16);
2040 }
2041 else
2042 {
2043 if (opP->reg == PC)
2044 tmpreg = 0x3A; /* 7.2 */
2045 else
2046 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2047
2048 if (isvar (&opP->disp))
2049 {
2050 if (opP->reg == PC)
2051 {
2052 add_fix ('w', &opP->disp, 1, 0);
2053 }
2054 else
2055 add_fix ('w', &opP->disp, 0, 0);
2056 }
2057 }
2058 addword (nextword);
2059 break;
2060
2061 case POST:
2062 case PRE:
2063 case BASE:
2064 nextword = 0;
2065 baseo = get_num (&opP->disp, 80);
2066 if (opP->mode == POST || opP->mode == PRE)
2067 outro = get_num (&opP->odisp, 80);
2068 /* Figure out the `addressing mode'.
2069 Also turn on the BASE_DISABLE bit, if needed. */
2070 if (opP->reg == PC || opP->reg == ZPC)
2071 {
2072 tmpreg = 0x3b; /* 7.3 */
2073 if (opP->reg == ZPC)
2074 nextword |= 0x80;
2075 }
2076 else if (opP->reg == 0)
2077 {
2078 nextword |= 0x80;
2079 tmpreg = 0x30; /* 6.garbage */
2080 }
2081 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2082 {
2083 nextword |= 0x80;
2084 tmpreg = 0x30 + opP->reg - ZADDR0;
2085 }
2086 else
2087 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2088
2089 siz1 = opP->disp.size;
2090 if (opP->mode == POST || opP->mode == PRE)
2091 siz2 = opP->odisp.size;
2092 else
2093 siz2 = SIZE_UNSPEC;
2094
2095 /* Index register stuff */
2096 if (opP->index.reg != 0
2097 && opP->index.reg >= DATA
2098 && opP->index.reg <= ADDR7)
2099 {
2100 nextword |= (opP->index.reg - DATA) << 12;
2101
2102 if (opP->index.size == SIZE_LONG
2103 || (opP->index.size == SIZE_UNSPEC
2104 && m68k_index_width_default == SIZE_LONG))
2105 nextword |= 0x800;
2106
2107 if ((opP->index.scale != 1
2108 && cpu_of_arch (current_architecture) < m68020)
2109 || (opP->index.scale == 8
2110 && current_architecture == mcf5200))
2111 {
2112 opP->error =
2113 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2114 }
2115
2116 switch (opP->index.scale)
2117 {
2118 case 1:
2119 break;
2120 case 2:
2121 nextword |= 0x200;
2122 break;
2123 case 4:
2124 nextword |= 0x400;
2125 break;
2126 case 8:
2127 nextword |= 0x600;
2128 break;
2129 default:
2130 abort ();
2131 }
2132 /* IF its simple,
2133 GET US OUT OF HERE! */
2134
2135 /* Must be INDEX, with an index register. Address
2136 register cannot be ZERO-PC, and either :b was
2137 forced, or we know it will fit. For a 68000 or
2138 68010, force this mode anyways, because the
2139 larger modes aren't supported. */
2140 if (opP->mode == BASE
2141 && ((opP->reg >= ADDR0
2142 && opP->reg <= ADDR7)
2143 || opP->reg == PC))
2144 {
2145 if (siz1 == SIZE_BYTE
2146 || cpu_of_arch (current_architecture) < m68020
2147 || cpu_of_arch (current_architecture) == mcf5200
2148 || (siz1 == SIZE_UNSPEC
2149 && ! isvar (&opP->disp)
2150 && issbyte (baseo)))
2151 {
2152 nextword += baseo & 0xff;
2153 addword (nextword);
2154 if (isvar (&opP->disp))
2155 {
2156 /* Do a byte relocation. If it doesn't
2157 fit (possible on m68000) let the
2158 fixup processing complain later. */
2159 if (opP->reg == PC)
2160 add_fix ('B', &opP->disp, 1, 1);
2161 else
2162 add_fix ('B', &opP->disp, 0, 0);
2163 }
2164 else if (siz1 != SIZE_BYTE)
2165 {
2166 if (siz1 != SIZE_UNSPEC)
2167 as_warn (_("Forcing byte displacement"));
2168 if (! issbyte (baseo))
2169 opP->error = _("byte displacement out of range");
2170 }
2171
2172 break;
2173 }
2174 else if (siz1 == SIZE_UNSPEC
2175 && opP->reg == PC
2176 && isvar (&opP->disp)
2177 && subs (&opP->disp) == NULL
2178 #ifdef OBJ_ELF
2179 /* If the displacement needs pic
2180 relocation it cannot be relaxed. */
2181 && opP->disp.pic_reloc == pic_none
2182 #endif
2183 )
2184 {
2185 /* The code in md_convert_frag_1 needs to be
2186 able to adjust nextword. Call frag_grow
2187 to ensure that we have enough space in
2188 the frag obstack to make all the bytes
2189 contiguous. */
2190 frag_grow (14);
2191 nextword += baseo & 0xff;
2192 addword (nextword);
2193 add_frag (adds (&opP->disp), offs (&opP->disp),
2194 TAB (PCINDEX, SZ_UNDEF));
2195
2196 break;
2197 }
2198 }
2199 }
2200 else
2201 {
2202 nextword |= 0x40; /* No index reg */
2203 if (opP->index.reg >= ZDATA0
2204 && opP->index.reg <= ZDATA7)
2205 nextword |= (opP->index.reg - ZDATA0) << 12;
2206 else if (opP->index.reg >= ZADDR0
2207 || opP->index.reg <= ZADDR7)
2208 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2209 }
2210
2211 /* It isn't simple. */
2212
2213 if (cpu_of_arch (current_architecture) < m68020
2214 || cpu_of_arch (current_architecture) == mcf5200)
2215 opP->error =
2216 _("invalid operand mode for this architecture; needs 68020 or higher");
2217
2218 nextword |= 0x100;
2219 /* If the guy specified a width, we assume that it is
2220 wide enough. Maybe it isn't. If so, we lose. */
2221 switch (siz1)
2222 {
2223 case SIZE_UNSPEC:
2224 if (isvar (&opP->disp)
2225 ? m68k_rel32
2226 : ! issword (baseo))
2227 {
2228 siz1 = SIZE_LONG;
2229 nextword |= 0x30;
2230 }
2231 else if (! isvar (&opP->disp) && baseo == 0)
2232 nextword |= 0x10;
2233 else
2234 {
2235 nextword |= 0x20;
2236 siz1 = SIZE_WORD;
2237 }
2238 break;
2239 case SIZE_BYTE:
2240 as_warn (_(":b not permitted; defaulting to :w"));
2241 /* Fall through. */
2242 case SIZE_WORD:
2243 nextword |= 0x20;
2244 break;
2245 case SIZE_LONG:
2246 nextword |= 0x30;
2247 break;
2248 }
2249
2250 /* Figure out innner displacement stuff */
2251 if (opP->mode == POST || opP->mode == PRE)
2252 {
2253 if (cpu_of_arch (current_architecture) & cpu32)
2254 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2255 switch (siz2)
2256 {
2257 case SIZE_UNSPEC:
2258 if (isvar (&opP->odisp)
2259 ? m68k_rel32
2260 : ! issword (outro))
2261 {
2262 siz2 = SIZE_LONG;
2263 nextword |= 0x3;
2264 }
2265 else if (! isvar (&opP->odisp) && outro == 0)
2266 nextword |= 0x1;
2267 else
2268 {
2269 nextword |= 0x2;
2270 siz2 = SIZE_WORD;
2271 }
2272 break;
2273 case 1:
2274 as_warn (_(":b not permitted; defaulting to :w"));
2275 /* Fall through. */
2276 case 2:
2277 nextword |= 0x2;
2278 break;
2279 case 3:
2280 nextword |= 0x3;
2281 break;
2282 }
2283 if (opP->mode == POST
2284 && (nextword & 0x40) == 0)
2285 nextword |= 0x04;
2286 }
2287 addword (nextword);
2288
2289 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2290 {
2291 if (opP->reg == PC || opP->reg == ZPC)
2292 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2293 else
2294 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2295 }
2296 if (siz1 == SIZE_LONG)
2297 addword (baseo >> 16);
2298 if (siz1 != SIZE_UNSPEC)
2299 addword (baseo);
2300
2301 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2302 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2303 if (siz2 == SIZE_LONG)
2304 addword (outro >> 16);
2305 if (siz2 != SIZE_UNSPEC)
2306 addword (outro);
2307
2308 break;
2309
2310 case ABSL:
2311 nextword = get_num (&opP->disp, 80);
2312 switch (opP->disp.size)
2313 {
2314 default:
2315 abort ();
2316 case SIZE_UNSPEC:
2317 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2318 {
2319 tmpreg = 0x38; /* 7.0 */
2320 addword (nextword);
2321 break;
2322 }
2323 /* Don't generate pc relative code on 68010 and
2324 68000. */
2325 if (isvar (&opP->disp)
2326 && !subs (&opP->disp)
2327 && adds (&opP->disp)
2328 #ifdef OBJ_ELF
2329 /* If the displacement needs pic relocation it
2330 cannot be relaxed. */
2331 && opP->disp.pic_reloc == pic_none
2332 #endif
2333 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2334 && relaxable_symbol (adds (&opP->disp))
2335 && HAVE_LONG_BRANCH(current_architecture)
2336 && !flag_long_jumps
2337 && !strchr ("~%&$?", s[0]))
2338 {
2339 tmpreg = 0x3A; /* 7.2 */
2340 add_frag (adds (&opP->disp),
2341 offs (&opP->disp),
2342 TAB (PCREL, SZ_UNDEF));
2343 break;
2344 }
2345 /* Fall through into long */
2346 case SIZE_LONG:
2347 if (isvar (&opP->disp))
2348 add_fix ('l', &opP->disp, 0, 0);
2349
2350 tmpreg = 0x39;/* 7.1 mode */
2351 addword (nextword >> 16);
2352 addword (nextword);
2353 break;
2354
2355 case SIZE_BYTE:
2356 as_bad (_("unsupported byte value; use a different suffix"));
2357 /* Fall through. */
2358 case SIZE_WORD: /* Word */
2359 if (isvar (&opP->disp))
2360 add_fix ('w', &opP->disp, 0, 0);
2361
2362 tmpreg = 0x38;/* 7.0 mode */
2363 addword (nextword);
2364 break;
2365 }
2366 break;
2367 case CONTROL:
2368 case FPREG:
2369 default:
2370 as_bad (_("unknown/incorrect operand"));
2371 /* abort(); */
2372 }
2373 install_gen_operand (s[1], tmpreg);
2374 break;
2375
2376 case '#':
2377 case '^':
2378 switch (s[1])
2379 { /* JF: I hate floating point! */
2380 case 'j':
2381 tmpreg = 70;
2382 break;
2383 case '8':
2384 tmpreg = 20;
2385 break;
2386 case 'C':
2387 tmpreg = 50;
2388 break;
2389 case '3':
2390 default:
2391 tmpreg = 80;
2392 break;
2393 }
2394 tmpreg = get_num (&opP->disp, tmpreg);
2395 if (isvar (&opP->disp))
2396 add_fix (s[1], &opP->disp, 0, 0);
2397 switch (s[1])
2398 {
2399 case 'b': /* Danger: These do no check for
2400 certain types of overflow.
2401 user beware! */
2402 if (!isbyte (tmpreg))
2403 opP->error = _("out of range");
2404 insop (tmpreg, opcode);
2405 if (isvar (&opP->disp))
2406 the_ins.reloc[the_ins.nrel - 1].n =
2407 (opcode->m_codenum) * 2 + 1;
2408 break;
2409 case 'B':
2410 if (!issbyte (tmpreg))
2411 opP->error = _("out of range");
2412 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2413 if (isvar (&opP->disp))
2414 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2415 break;
2416 case 'w':
2417 if (!isword (tmpreg))
2418 opP->error = _("out of range");
2419 insop (tmpreg, opcode);
2420 if (isvar (&opP->disp))
2421 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2422 break;
2423 case 'W':
2424 if (!issword (tmpreg))
2425 opP->error = _("out of range");
2426 insop (tmpreg, opcode);
2427 if (isvar (&opP->disp))
2428 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2429 break;
2430 case 'l':
2431 /* Because of the way insop works, we put these two out
2432 backwards. */
2433 insop (tmpreg, opcode);
2434 insop (tmpreg >> 16, opcode);
2435 if (isvar (&opP->disp))
2436 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2437 break;
2438 case '3':
2439 tmpreg &= 0xFF;
2440 case '8':
2441 case 'C':
2442 case 'j':
2443 install_operand (s[1], tmpreg);
2444 break;
2445 default:
2446 abort ();
2447 }
2448 break;
2449
2450 case '+':
2451 case '-':
2452 case 'A':
2453 case 'a':
2454 install_operand (s[1], opP->reg - ADDR);
2455 break;
2456
2457 case 'B':
2458 tmpreg = get_num (&opP->disp, 80);
2459 switch (s[1])
2460 {
2461 case 'B':
2462 /* The pc_fix argument winds up in fx_pcrel_adjust,
2463 which is a char, and may therefore be unsigned. We
2464 want to pass -1, but we pass 64 instead, and convert
2465 back in md_pcrel_from. */
2466 add_fix ('B', &opP->disp, 1, 64);
2467 break;
2468 case 'W':
2469 add_fix ('w', &opP->disp, 1, 0);
2470 addword (0);
2471 break;
2472 case 'L':
2473 long_branch:
2474 if (!HAVE_LONG_BRANCH(current_architecture))
2475 as_warn (_("Can't use long branches on 68000/68010/5200"));
2476 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2477 add_fix ('l', &opP->disp, 1, 0);
2478 addword (0);
2479 addword (0);
2480 break;
2481 case 'g':
2482 if (subs (&opP->disp)) /* We can't relax it */
2483 goto long_branch;
2484
2485 #ifdef OBJ_ELF
2486 /* If the displacement needs pic relocation it cannot be
2487 relaxed. */
2488 if (opP->disp.pic_reloc != pic_none)
2489 goto long_branch;
2490 #endif
2491
2492 /* This could either be a symbol, or an absolute
2493 address. No matter, the frag hacking will finger it
2494 out. Not quite: it can't switch from BRANCH to
2495 BCC68000 for the case where opnd is absolute (it
2496 needs to use the 68000 hack since no conditional abs
2497 jumps). */
2498 if (( !HAVE_LONG_BRANCH(current_architecture)
2499 || (0 == adds (&opP->disp)))
2500 && (the_ins.opcode[0] >= 0x6200)
2501 && (the_ins.opcode[0] <= 0x6f00))
2502 add_frag (adds (&opP->disp), offs (&opP->disp),
2503 TAB (BCC68000, SZ_UNDEF));
2504 else
2505 add_frag (adds (&opP->disp), offs (&opP->disp),
2506 TAB (ABRANCH, SZ_UNDEF));
2507 break;
2508 case 'w':
2509 if (isvar (&opP->disp))
2510 {
2511 #if 1
2512 /* check for DBcc instruction */
2513 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2514 {
2515 /* size varies if patch */
2516 /* needed for long form */
2517 add_frag (adds (&opP->disp), offs (&opP->disp),
2518 TAB (DBCC, SZ_UNDEF));
2519 break;
2520 }
2521 #endif
2522 add_fix ('w', &opP->disp, 1, 0);
2523 }
2524 addword (0);
2525 break;
2526 case 'C': /* Fixed size LONG coproc branches */
2527 add_fix ('l', &opP->disp, 1, 0);
2528 addword (0);
2529 addword (0);
2530 break;
2531 case 'c': /* Var size Coprocesssor branches */
2532 if (subs (&opP->disp))
2533 {
2534 add_fix ('l', &opP->disp, 1, 0);
2535 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2536 }
2537 else if (adds (&opP->disp))
2538 add_frag (adds (&opP->disp), offs (&opP->disp),
2539 TAB (FBRANCH, SZ_UNDEF));
2540 else
2541 {
2542 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2543 TAB(FBRANCH,SHORT)); */
2544 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2545 add_fix ('l', &opP->disp, 1, 0);
2546 addword (0);
2547 addword (0);
2548 }
2549 break;
2550 default:
2551 abort ();
2552 }
2553 break;
2554
2555 case 'C': /* Ignore it */
2556 break;
2557
2558 case 'd': /* JF this is a kludge */
2559 install_operand ('s', opP->reg - ADDR);
2560 tmpreg = get_num (&opP->disp, 80);
2561 if (!issword (tmpreg))
2562 {
2563 as_warn (_("Expression out of range, using 0"));
2564 tmpreg = 0;
2565 }
2566 addword (tmpreg);
2567 break;
2568
2569 case 'D':
2570 install_operand (s[1], opP->reg - DATA);
2571 break;
2572
2573 case 'F':
2574 install_operand (s[1], opP->reg - FP0);
2575 break;
2576
2577 case 'I':
2578 tmpreg = opP->reg - COP0;
2579 install_operand (s[1], tmpreg);
2580 break;
2581
2582 case 'J': /* JF foo */
2583 switch (opP->reg)
2584 {
2585 case SFC:
2586 tmpreg = 0x000;
2587 break;
2588 case DFC:
2589 tmpreg = 0x001;
2590 break;
2591 case CACR:
2592 tmpreg = 0x002;
2593 break;
2594 case TC:
2595 tmpreg = 0x003;
2596 break;
2597 case ITT0:
2598 tmpreg = 0x004;
2599 break;
2600 case ITT1:
2601 tmpreg = 0x005;
2602 break;
2603 case DTT0:
2604 tmpreg = 0x006;
2605 break;
2606 case DTT1:
2607 tmpreg = 0x007;
2608 break;
2609 case BUSCR:
2610 tmpreg = 0x008;
2611 break;
2612
2613 case USP:
2614 tmpreg = 0x800;
2615 break;
2616 case VBR:
2617 tmpreg = 0x801;
2618 break;
2619 case CAAR:
2620 tmpreg = 0x802;
2621 break;
2622 case MSP:
2623 tmpreg = 0x803;
2624 break;
2625 case ISP:
2626 tmpreg = 0x804;
2627 break;
2628 case MMUSR:
2629 tmpreg = 0x805;
2630 break;
2631 case URP:
2632 tmpreg = 0x806;
2633 break;
2634 case SRP:
2635 tmpreg = 0x807;
2636 break;
2637 case PCR:
2638 tmpreg = 0x808;
2639 break;
2640 case ROMBAR:
2641 tmpreg = 0xC00;
2642 break;
2643 case RAMBAR0:
2644 tmpreg = 0xC04;
2645 break;
2646 case RAMBAR1:
2647 tmpreg = 0xC05;
2648 break;
2649 case MBAR:
2650 tmpreg = 0xC0F;
2651 break;
2652 default:
2653 abort ();
2654 }
2655 install_operand (s[1], tmpreg);
2656 break;
2657
2658 case 'k':
2659 tmpreg = get_num (&opP->disp, 55);
2660 install_operand (s[1], tmpreg & 0x7f);
2661 break;
2662
2663 case 'l':
2664 tmpreg = opP->mask;
2665 if (s[1] == 'w')
2666 {
2667 if (tmpreg & 0x7FF0000)
2668 as_bad (_("Floating point register in register list"));
2669 insop (reverse_16_bits (tmpreg), opcode);
2670 }
2671 else
2672 {
2673 if (tmpreg & 0x700FFFF)
2674 as_bad (_("Wrong register in floating-point reglist"));
2675 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2676 }
2677 break;
2678
2679 case 'L':
2680 tmpreg = opP->mask;
2681 if (s[1] == 'w')
2682 {
2683 if (tmpreg & 0x7FF0000)
2684 as_bad (_("Floating point register in register list"));
2685 insop (tmpreg, opcode);
2686 }
2687 else if (s[1] == '8')
2688 {
2689 if (tmpreg & 0x0FFFFFF)
2690 as_bad (_("incorrect register in reglist"));
2691 install_operand (s[1], tmpreg >> 24);
2692 }
2693 else
2694 {
2695 if (tmpreg & 0x700FFFF)
2696 as_bad (_("wrong register in floating-point reglist"));
2697 else
2698 install_operand (s[1], tmpreg >> 16);
2699 }
2700 break;
2701
2702 case 'M':
2703 install_operand (s[1], get_num (&opP->disp, 60));
2704 break;
2705
2706 case 'O':
2707 tmpreg = ((opP->mode == DREG)
2708 ? 0x20 + opP->reg - DATA
2709 : (get_num (&opP->disp, 40) & 0x1F));
2710 install_operand (s[1], tmpreg);
2711 break;
2712
2713 case 'Q':
2714 tmpreg = get_num (&opP->disp, 10);
2715 if (tmpreg == 8)
2716 tmpreg = 0;
2717 install_operand (s[1], tmpreg);
2718 break;
2719
2720 case 'R':
2721 /* This depends on the fact that ADDR registers are eight
2722 more than their corresponding DATA regs, so the result
2723 will have the ADDR_REG bit set */
2724 install_operand (s[1], opP->reg - DATA);
2725 break;
2726
2727 case 'r':
2728 if (opP->mode == AINDR)
2729 install_operand (s[1], opP->reg - DATA);
2730 else
2731 install_operand (s[1], opP->index.reg - DATA);
2732 break;
2733
2734 case 's':
2735 if (opP->reg == FPI)
2736 tmpreg = 0x1;
2737 else if (opP->reg == FPS)
2738 tmpreg = 0x2;
2739 else if (opP->reg == FPC)
2740 tmpreg = 0x4;
2741 else
2742 abort ();
2743 install_operand (s[1], tmpreg);
2744 break;
2745
2746 case 'S': /* Ignore it */
2747 break;
2748
2749 case 'T':
2750 install_operand (s[1], get_num (&opP->disp, 30));
2751 break;
2752
2753 case 'U': /* Ignore it */
2754 break;
2755
2756 case 'c':
2757 switch (opP->reg)
2758 {
2759 case NC:
2760 tmpreg = 0;
2761 break;
2762 case DC:
2763 tmpreg = 1;
2764 break;
2765 case IC:
2766 tmpreg = 2;
2767 break;
2768 case BC:
2769 tmpreg = 3;
2770 break;
2771 default:
2772 as_fatal (_("failed sanity check"));
2773 } /* switch on cache token */
2774 install_operand (s[1], tmpreg);
2775 break;
2776 #ifndef NO_68851
2777 /* JF: These are out of order, I fear. */
2778 case 'f':
2779 switch (opP->reg)
2780 {
2781 case SFC:
2782 tmpreg = 0;
2783 break;
2784 case DFC:
2785 tmpreg = 1;
2786 break;
2787 default:
2788 abort ();
2789 }
2790 install_operand (s[1], tmpreg);
2791 break;
2792
2793 case '0':
2794 case '1':
2795 case '2':
2796 switch (opP->reg)
2797 {
2798 case TC:
2799 tmpreg = 0;
2800 break;
2801 case CAL:
2802 tmpreg = 4;
2803 break;
2804 case VAL:
2805 tmpreg = 5;
2806 break;
2807 case SCC:
2808 tmpreg = 6;
2809 break;
2810 case AC:
2811 tmpreg = 7;
2812 break;
2813 default:
2814 abort ();
2815 }
2816 install_operand (s[1], tmpreg);
2817 break;
2818
2819 case 'V':
2820 if (opP->reg == VAL)
2821 break;
2822 abort ();
2823
2824 case 'W':
2825 switch (opP->reg)
2826 {
2827 case DRP:
2828 tmpreg = 1;
2829 break;
2830 case SRP:
2831 tmpreg = 2;
2832 break;
2833 case CRP:
2834 tmpreg = 3;
2835 break;
2836 default:
2837 abort ();
2838 }
2839 install_operand (s[1], tmpreg);
2840 break;
2841
2842 case 'X':
2843 switch (opP->reg)
2844 {
2845 case BAD:
2846 case BAD + 1:
2847 case BAD + 2:
2848 case BAD + 3:
2849 case BAD + 4:
2850 case BAD + 5:
2851 case BAD + 6:
2852 case BAD + 7:
2853 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2854 break;
2855
2856 case BAC:
2857 case BAC + 1:
2858 case BAC + 2:
2859 case BAC + 3:
2860 case BAC + 4:
2861 case BAC + 5:
2862 case BAC + 6:
2863 case BAC + 7:
2864 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2865 break;
2866
2867 default:
2868 abort ();
2869 }
2870 install_operand (s[1], tmpreg);
2871 break;
2872 case 'Y':
2873 know (opP->reg == PSR);
2874 break;
2875 case 'Z':
2876 know (opP->reg == PCSR);
2877 break;
2878 #endif /* m68851 */
2879 case '3':
2880 switch (opP->reg)
2881 {
2882 case TT0:
2883 tmpreg = 2;
2884 break;
2885 case TT1:
2886 tmpreg = 3;
2887 break;
2888 default:
2889 abort ();
2890 }
2891 install_operand (s[1], tmpreg);
2892 break;
2893 case 't':
2894 tmpreg = get_num (&opP->disp, 20);
2895 install_operand (s[1], tmpreg);
2896 break;
2897 case '_': /* used only for move16 absolute 32-bit address */
2898 if (isvar (&opP->disp))
2899 add_fix ('l', &opP->disp, 0, 0);
2900 tmpreg = get_num (&opP->disp, 80);
2901 addword (tmpreg >> 16);
2902 addword (tmpreg & 0xFFFF);
2903 break;
2904 default:
2905 abort ();
2906 }
2907 }
2908
2909 /* By the time whe get here (FINALLY) the_ins contains the complete
2910 instruction, ready to be emitted. . . */
2911 }
2912
2913 static int
2914 reverse_16_bits (in)
2915 int in;
2916 {
2917 int out = 0;
2918 int n;
2919
2920 static int mask[16] =
2921 {
2922 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2923 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2924 };
2925 for (n = 0; n < 16; n++)
2926 {
2927 if (in & mask[n])
2928 out |= mask[15 - n];
2929 }
2930 return out;
2931 } /* reverse_16_bits() */
2932
2933 static int
2934 reverse_8_bits (in)
2935 int in;
2936 {
2937 int out = 0;
2938 int n;
2939
2940 static int mask[8] =
2941 {
2942 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2943 };
2944
2945 for (n = 0; n < 8; n++)
2946 {
2947 if (in & mask[n])
2948 out |= mask[7 - n];
2949 }
2950 return out;
2951 } /* reverse_8_bits() */
2952
2953 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2954 (that value is chosen in the frag_var call in md_assemble). TYPE
2955 is the subtype of the frag to be generated; its primary type is
2956 rs_machine_dependent.
2957
2958 The TYPE parameter is also used by md_convert_frag_1 and
2959 md_estimate_size_before_relax. The appropriate type of fixup will
2960 be emitted by md_convert_frag_1.
2961
2962 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2963 static void
2964 install_operand (mode, val)
2965 int mode;
2966 int val;
2967 {
2968 switch (mode)
2969 {
2970 case 's':
2971 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2972 break;
2973 case 'd':
2974 the_ins.opcode[0] |= val << 9;
2975 break;
2976 case '1':
2977 the_ins.opcode[1] |= val << 12;
2978 break;
2979 case '2':
2980 the_ins.opcode[1] |= val << 6;
2981 break;
2982 case '3':
2983 the_ins.opcode[1] |= val;
2984 break;
2985 case '4':
2986 the_ins.opcode[2] |= val << 12;
2987 break;
2988 case '5':
2989 the_ins.opcode[2] |= val << 6;
2990 break;
2991 case '6':
2992 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2993 three words long! */
2994 the_ins.numo++;
2995 the_ins.opcode[2] |= val;
2996 break;
2997 case '7':
2998 the_ins.opcode[1] |= val << 7;
2999 break;
3000 case '8':
3001 the_ins.opcode[1] |= val << 10;
3002 break;
3003 #ifndef NO_68851
3004 case '9':
3005 the_ins.opcode[1] |= val << 5;
3006 break;
3007 #endif
3008
3009 case 't':
3010 the_ins.opcode[1] |= (val << 10) | (val << 7);
3011 break;
3012 case 'D':
3013 the_ins.opcode[1] |= (val << 12) | val;
3014 break;
3015 case 'g':
3016 the_ins.opcode[0] |= val = 0xff;
3017 break;
3018 case 'i':
3019 the_ins.opcode[0] |= val << 9;
3020 break;
3021 case 'C':
3022 the_ins.opcode[1] |= val;
3023 break;
3024 case 'j':
3025 the_ins.opcode[1] |= val;
3026 the_ins.numo++; /* What a hack */
3027 break;
3028 case 'k':
3029 the_ins.opcode[1] |= val << 4;
3030 break;
3031 case 'b':
3032 case 'w':
3033 case 'W':
3034 case 'l':
3035 break;
3036 case 'e':
3037 the_ins.opcode[0] |= (val << 6);
3038 break;
3039 case 'L':
3040 the_ins.opcode[1] = (val >> 16);
3041 the_ins.opcode[2] = val & 0xffff;
3042 break;
3043 case 'c':
3044 default:
3045 as_fatal (_("failed sanity check."));
3046 }
3047 } /* install_operand() */
3048
3049 static void
3050 install_gen_operand (mode, val)
3051 int mode;
3052 int val;
3053 {
3054 switch (mode)
3055 {
3056 case 's':
3057 the_ins.opcode[0] |= val;
3058 break;
3059 case 'd':
3060 /* This is a kludge!!! */
3061 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3062 break;
3063 case 'b':
3064 case 'w':
3065 case 'l':
3066 case 'f':
3067 case 'F':
3068 case 'x':
3069 case 'p':
3070 the_ins.opcode[0] |= val;
3071 break;
3072 /* more stuff goes here */
3073 default:
3074 as_fatal (_("failed sanity check."));
3075 }
3076 } /* install_gen_operand() */
3077
3078 /*
3079 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3080 * then deal with the bitfield hack.
3081 */
3082
3083 static char *
3084 crack_operand (str, opP)
3085 register char *str;
3086 register struct m68k_op *opP;
3087 {
3088 register int parens;
3089 register int c;
3090 register char *beg_str;
3091 int inquote = 0;
3092
3093 if (!str)
3094 {
3095 return str;
3096 }
3097 beg_str = str;
3098 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3099 {
3100 if (! inquote)
3101 {
3102 if (*str == '(')
3103 parens++;
3104 else if (*str == ')')
3105 {
3106 if (!parens)
3107 { /* ERROR */
3108 opP->error = _("Extra )");
3109 return str;
3110 }
3111 --parens;
3112 }
3113 }
3114 if (flag_mri && *str == '\'')
3115 inquote = ! inquote;
3116 }
3117 if (!*str && parens)
3118 { /* ERROR */
3119 opP->error = _("Missing )");
3120 return str;
3121 }
3122 c = *str;
3123 *str = '\0';
3124 if (m68k_ip_op (beg_str, opP) != 0)
3125 {
3126 *str = c;
3127 return str;
3128 }
3129 *str = c;
3130 if (c == '}')
3131 c = *++str; /* JF bitfield hack */
3132 if (c)
3133 {
3134 c = *++str;
3135 if (!c)
3136 as_bad (_("Missing operand"));
3137 }
3138
3139 /* Detect MRI REG symbols and convert them to REGLSTs. */
3140 if (opP->mode == CONTROL && (int)opP->reg < 0)
3141 {
3142 opP->mode = REGLST;
3143 opP->mask = ~(int)opP->reg;
3144 opP->reg = 0;
3145 }
3146
3147 return str;
3148 }
3149
3150 /* This is the guts of the machine-dependent assembler. STR points to a
3151 machine dependent instruction. This function is supposed to emit
3152 the frags/bytes it assembles to.
3153 */
3154
3155 static void
3156 insert_reg (regname, regnum)
3157 const char *regname;
3158 int regnum;
3159 {
3160 char buf[100];
3161 int i;
3162
3163 #ifdef REGISTER_PREFIX
3164 if (!flag_reg_prefix_optional)
3165 {
3166 buf[0] = REGISTER_PREFIX;
3167 strcpy (buf + 1, regname);
3168 regname = buf;
3169 }
3170 #endif
3171
3172 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3173 &zero_address_frag));
3174
3175 for (i = 0; regname[i]; i++)
3176 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3177 buf[i] = '\0';
3178
3179 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3180 &zero_address_frag));
3181 }
3182
3183 struct init_entry
3184 {
3185 const char *name;
3186 int number;
3187 };
3188
3189 static const struct init_entry init_table[] =
3190 {
3191 { "d0", DATA0 },
3192 { "d1", DATA1 },
3193 { "d2", DATA2 },
3194 { "d3", DATA3 },
3195 { "d4", DATA4 },
3196 { "d5", DATA5 },
3197 { "d6", DATA6 },
3198 { "d7", DATA7 },
3199 { "a0", ADDR0 },
3200 { "a1", ADDR1 },
3201 { "a2", ADDR2 },
3202 { "a3", ADDR3 },
3203 { "a4", ADDR4 },
3204 { "a5", ADDR5 },
3205 { "a6", ADDR6 },
3206 { "fp", ADDR6 },
3207 { "a7", ADDR7 },
3208 { "sp", ADDR7 },
3209 { "ssp", ADDR7 },
3210 { "fp0", FP0 },
3211 { "fp1", FP1 },
3212 { "fp2", FP2 },
3213 { "fp3", FP3 },
3214 { "fp4", FP4 },
3215 { "fp5", FP5 },
3216 { "fp6", FP6 },
3217 { "fp7", FP7 },
3218 { "fpi", FPI },
3219 { "fpiar", FPI },
3220 { "fpc", FPI },
3221 { "fps", FPS },
3222 { "fpsr", FPS },
3223 { "fpc", FPC },
3224 { "fpcr", FPC },
3225 { "control", FPC },
3226 { "status", FPS },
3227 { "iaddr", FPI },
3228
3229 { "cop0", COP0 },
3230 { "cop1", COP1 },
3231 { "cop2", COP2 },
3232 { "cop3", COP3 },
3233 { "cop4", COP4 },
3234 { "cop5", COP5 },
3235 { "cop6", COP6 },
3236 { "cop7", COP7 },
3237 { "pc", PC },
3238 { "zpc", ZPC },
3239 { "sr", SR },
3240
3241 { "ccr", CCR },
3242 { "cc", CCR },
3243
3244 /* control registers */
3245 { "sfc", SFC }, /* Source Function Code */
3246 { "sfcr", SFC },
3247 { "dfc", DFC }, /* Destination Function Code */
3248 { "dfcr", DFC },
3249 { "cacr", CACR }, /* Cache Control Register */
3250 { "caar", CAAR }, /* Cache Address Register */
3251
3252 { "usp", USP }, /* User Stack Pointer */
3253 { "vbr", VBR }, /* Vector Base Register */
3254 { "msp", MSP }, /* Master Stack Pointer */
3255 { "isp", ISP }, /* Interrupt Stack Pointer */
3256
3257 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3258 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3259 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3260 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3261
3262 /* 68ec040 versions of same */
3263 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3264 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3265 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3266 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3267
3268 /* mcf5200 versions of same. The ColdFire programmer's reference
3269 manual indicated that the order is 2,3,0,1, but Ken Rose
3270 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3271 { "acr0", ITT0 }, /* Access Control Unit 0 */
3272 { "acr1", ITT1 }, /* Access Control Unit 1 */
3273 { "acr2", DTT0 }, /* Access Control Unit 2 */
3274 { "acr3", DTT1 }, /* Access Control Unit 3 */
3275
3276 { "tc", TC }, /* MMU Translation Control Register */
3277 { "tcr", TC },
3278
3279 { "mmusr", MMUSR }, /* MMU Status Register */
3280 { "srp", SRP }, /* User Root Pointer */
3281 { "urp", URP }, /* Supervisor Root Pointer */
3282
3283 { "buscr", BUSCR },
3284 { "pcr", PCR },
3285
3286 { "rombar", ROMBAR }, /* ROM Base Address Register */
3287 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3288 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3289 { "mbar", MBAR }, /* Module Base Address Register */
3290 /* end of control registers */
3291
3292 { "ac", AC },
3293 { "bc", BC },
3294 { "cal", CAL },
3295 { "crp", CRP },
3296 { "drp", DRP },
3297 { "pcsr", PCSR },
3298 { "psr", PSR },
3299 { "scc", SCC },
3300 { "val", VAL },
3301 { "bad0", BAD0 },
3302 { "bad1", BAD1 },
3303 { "bad2", BAD2 },
3304 { "bad3", BAD3 },
3305 { "bad4", BAD4 },
3306 { "bad5", BAD5 },
3307 { "bad6", BAD6 },
3308 { "bad7", BAD7 },
3309 { "bac0", BAC0 },
3310 { "bac1", BAC1 },
3311 { "bac2", BAC2 },
3312 { "bac3", BAC3 },
3313 { "bac4", BAC4 },
3314 { "bac5", BAC5 },
3315 { "bac6", BAC6 },
3316 { "bac7", BAC7 },
3317
3318 { "ic", IC },
3319 { "dc", DC },
3320 { "nc", NC },
3321
3322 { "tt0", TT0 },
3323 { "tt1", TT1 },
3324 /* 68ec030 versions of same */
3325 { "ac0", TT0 },
3326 { "ac1", TT1 },
3327 /* 68ec030 access control unit, identical to 030 MMU status reg */
3328 { "acusr", PSR },
3329
3330 /* Suppressed data and address registers. */
3331 { "zd0", ZDATA0 },
3332 { "zd1", ZDATA1 },
3333 { "zd2", ZDATA2 },
3334 { "zd3", ZDATA3 },
3335 { "zd4", ZDATA4 },
3336 { "zd5", ZDATA5 },
3337 { "zd6", ZDATA6 },
3338 { "zd7", ZDATA7 },
3339 { "za0", ZADDR0 },
3340 { "za1", ZADDR1 },
3341 { "za2", ZADDR2 },
3342 { "za3", ZADDR3 },
3343 { "za4", ZADDR4 },
3344 { "za5", ZADDR5 },
3345 { "za6", ZADDR6 },
3346 { "za7", ZADDR7 },
3347
3348 { 0, 0 }
3349 };
3350
3351 static void
3352 init_regtable ()
3353 {
3354 int i;
3355 for (i = 0; init_table[i].name; i++)
3356 insert_reg (init_table[i].name, init_table[i].number);
3357 }
3358
3359 static int no_68851, no_68881;
3360
3361 #ifdef OBJ_AOUT
3362 /* a.out machine type. Default to 68020. */
3363 int m68k_aout_machtype = 2;
3364 #endif
3365
3366 void
3367 md_assemble (str)
3368 char *str;
3369 {
3370 const char *er;
3371 short *fromP;
3372 char *toP = NULL;
3373 int m, n = 0;
3374 char *to_beg_P;
3375 int shorts_this_frag;
3376 fixS *fixP;
3377
3378 /* In MRI mode, the instruction and operands are separated by a
3379 space. Anything following the operands is a comment. The label
3380 has already been removed. */
3381 if (flag_mri)
3382 {
3383 char *s;
3384 int fields = 0;
3385 int infield = 0;
3386 int inquote = 0;
3387
3388 for (s = str; *s != '\0'; s++)
3389 {
3390 if ((*s == ' ' || *s == '\t') && ! inquote)
3391 {
3392 if (infield)
3393 {
3394 ++fields;
3395 if (fields >= 2)
3396 {
3397 *s = '\0';
3398 break;
3399 }
3400 infield = 0;
3401 }
3402 }
3403 else
3404 {
3405 if (! infield)
3406 infield = 1;
3407 if (*s == '\'')
3408 inquote = ! inquote;
3409 }
3410 }
3411 }
3412
3413 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3414 m68k_ip (str);
3415 er = the_ins.error;
3416 if (!er)
3417 {
3418 for (n = 0; n < the_ins.numargs; n++)
3419 if (the_ins.operands[n].error)
3420 {
3421 er = the_ins.operands[n].error;
3422 break;
3423 }
3424 }
3425 if (er)
3426 {
3427 as_bad (_("%s -- statement `%s' ignored"), er, str);
3428 return;
3429 }
3430
3431 /* If there is a current label, record that it marks an instruction. */
3432 if (current_label != NULL)
3433 {
3434 current_label->text = 1;
3435 current_label = NULL;
3436 }
3437
3438 if (the_ins.nfrag == 0)
3439 {
3440 /* No frag hacking involved; just put it out */
3441 toP = frag_more (2 * the_ins.numo);
3442 fromP = &the_ins.opcode[0];
3443 for (m = the_ins.numo; m; --m)
3444 {
3445 md_number_to_chars (toP, (long) (*fromP), 2);
3446 toP += 2;
3447 fromP++;
3448 }
3449 /* put out symbol-dependent info */
3450 for (m = 0; m < the_ins.nrel; m++)
3451 {
3452 switch (the_ins.reloc[m].wid)
3453 {
3454 case 'B':
3455 n = 1;
3456 break;
3457 case 'b':
3458 n = 1;
3459 break;
3460 case '3':
3461 n = 1;
3462 break;
3463 case 'w':
3464 case 'W':
3465 n = 2;
3466 break;
3467 case 'l':
3468 n = 4;
3469 break;
3470 default:
3471 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3472 the_ins.reloc[m].wid);
3473 }
3474
3475 fixP = fix_new_exp (frag_now,
3476 ((toP - frag_now->fr_literal)
3477 - the_ins.numo * 2 + the_ins.reloc[m].n),
3478 n,
3479 &the_ins.reloc[m].exp,
3480 the_ins.reloc[m].pcrel,
3481 get_reloc_code (n, the_ins.reloc[m].pcrel,
3482 the_ins.reloc[m].pic_reloc));
3483 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3484 if (the_ins.reloc[m].wid == 'B')
3485 fixP->fx_signed = 1;
3486 }
3487 return;
3488 }
3489
3490 /* There's some frag hacking */
3491 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3492 {
3493 int wid;
3494
3495 if (n == 0)
3496 wid = 2 * the_ins.fragb[n].fragoff;
3497 else
3498 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3499 toP = frag_more (wid);
3500 to_beg_P = toP;
3501 shorts_this_frag = 0;
3502 for (m = wid / 2; m; --m)
3503 {
3504 md_number_to_chars (toP, (long) (*fromP), 2);
3505 toP += 2;
3506 fromP++;
3507 shorts_this_frag++;
3508 }
3509 for (m = 0; m < the_ins.nrel; m++)
3510 {
3511 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3512 {
3513 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3514 break;
3515 }
3516 wid = the_ins.reloc[m].wid;
3517 if (wid == 0)
3518 continue;
3519 the_ins.reloc[m].wid = 0;
3520 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3521
3522 fixP = fix_new_exp (frag_now,
3523 ((toP - frag_now->fr_literal)
3524 - the_ins.numo * 2 + the_ins.reloc[m].n),
3525 wid,
3526 &the_ins.reloc[m].exp,
3527 the_ins.reloc[m].pcrel,
3528 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3529 the_ins.reloc[m].pic_reloc));
3530 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3531 }
3532 (void) frag_var (rs_machine_dependent, 10, 0,
3533 (relax_substateT) (the_ins.fragb[n].fragty),
3534 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3535 }
3536 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3537 shorts_this_frag = 0;
3538 if (n)
3539 {
3540 toP = frag_more (n * sizeof (short));
3541 while (n--)
3542 {
3543 md_number_to_chars (toP, (long) (*fromP), 2);
3544 toP += 2;
3545 fromP++;
3546 shorts_this_frag++;
3547 }
3548 }
3549 for (m = 0; m < the_ins.nrel; m++)
3550 {
3551 int wid;
3552
3553 wid = the_ins.reloc[m].wid;
3554 if (wid == 0)
3555 continue;
3556 the_ins.reloc[m].wid = 0;
3557 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3558
3559 fixP = fix_new_exp (frag_now,
3560 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3561 - shorts_this_frag * 2),
3562 wid,
3563 &the_ins.reloc[m].exp,
3564 the_ins.reloc[m].pcrel,
3565 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3566 the_ins.reloc[m].pic_reloc));
3567 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3568 }
3569 }
3570
3571 void
3572 md_begin ()
3573 {
3574 /*
3575 * md_begin -- set up hash tables with 68000 instructions.
3576 * similar to what the vax assembler does. ---phr
3577 */
3578 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3579 a copy of it at runtime, adding in the information we want but isn't
3580 there. I think it'd be better to have an awk script hack the table
3581 at compile time. Or even just xstr the table and use it as-is. But
3582 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3583 names. */
3584
3585 register const struct m68k_opcode *ins;
3586 register struct m68k_incant *hack, *slak;
3587 register const char *retval = 0; /* empty string, or error msg text */
3588 register unsigned int i;
3589 register char c;
3590
3591 if (flag_mri)
3592 {
3593 flag_reg_prefix_optional = 1;
3594 m68k_abspcadd = 1;
3595 if (! m68k_rel32_from_cmdline)
3596 m68k_rel32 = 0;
3597 }
3598
3599 op_hash = hash_new ();
3600
3601 obstack_begin (&robyn, 4000);
3602 for (i = 0; i < m68k_numopcodes; i++)
3603 {
3604 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3605 do
3606 {
3607 ins = &m68k_opcodes[i];
3608 /* We *could* ignore insns that don't match our arch here
3609 but just leaving them out of the hash. */
3610 slak->m_operands = ins->args;
3611 slak->m_opnum = strlen (slak->m_operands) / 2;
3612 slak->m_arch = ins->arch;
3613 slak->m_opcode = ins->opcode;
3614 /* This is kludgey */
3615 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3616 if (i + 1 != m68k_numopcodes
3617 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3618 {
3619 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3620 i++;
3621 }
3622 else
3623 slak->m_next = 0;
3624 slak = slak->m_next;
3625 }
3626 while (slak);
3627
3628 retval = hash_insert (op_hash, ins->name, (char *) hack);
3629 if (retval)
3630 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3631 }
3632
3633 for (i = 0; i < m68k_numaliases; i++)
3634 {
3635 const char *name = m68k_opcode_aliases[i].primary;
3636 const char *alias = m68k_opcode_aliases[i].alias;
3637 PTR val = hash_find (op_hash, name);
3638 if (!val)
3639 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3640 retval = hash_insert (op_hash, alias, val);
3641 if (retval)
3642 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3643 }
3644
3645 /* In MRI mode, all unsized branches are variable sized. Normally,
3646 they are word sized. */
3647 if (flag_mri)
3648 {
3649 static struct m68k_opcode_alias mri_aliases[] =
3650 {
3651 { "bhi", "jhi", },
3652 { "bls", "jls", },
3653 { "bcc", "jcc", },
3654 { "bcs", "jcs", },
3655 { "bne", "jne", },
3656 { "beq", "jeq", },
3657 { "bvc", "jvc", },
3658 { "bvs", "jvs", },
3659 { "bpl", "jpl", },
3660 { "bmi", "jmi", },
3661 { "bge", "jge", },
3662 { "blt", "jlt", },
3663 { "bgt", "jgt", },
3664 { "ble", "jle", },
3665 { "bra", "jra", },
3666 { "bsr", "jbsr", },
3667 };
3668
3669 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3670 {
3671 const char *name = mri_aliases[i].primary;
3672 const char *alias = mri_aliases[i].alias;
3673 PTR val = hash_find (op_hash, name);
3674 if (!val)
3675 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3676 retval = hash_jam (op_hash, alias, val);
3677 if (retval)
3678 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3679 }
3680 }
3681
3682 for (i = 0; i < sizeof (mklower_table); i++)
3683 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3684
3685 for (i = 0; i < sizeof (notend_table); i++)
3686 {
3687 notend_table[i] = 0;
3688 alt_notend_table[i] = 0;
3689 }
3690 notend_table[','] = 1;
3691 notend_table['{'] = 1;
3692 notend_table['}'] = 1;
3693 alt_notend_table['a'] = 1;
3694 alt_notend_table['A'] = 1;
3695 alt_notend_table['d'] = 1;
3696 alt_notend_table['D'] = 1;
3697 alt_notend_table['#'] = 1;
3698 alt_notend_table['&'] = 1;
3699 alt_notend_table['f'] = 1;
3700 alt_notend_table['F'] = 1;
3701 #ifdef REGISTER_PREFIX
3702 alt_notend_table[REGISTER_PREFIX] = 1;
3703 #endif
3704
3705 /* We need to put '(' in alt_notend_table to handle
3706 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3707 */
3708 alt_notend_table['('] = 1;
3709
3710 /* We need to put '@' in alt_notend_table to handle
3711 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3712 */
3713 alt_notend_table['@'] = 1;
3714
3715 /* We need to put digits in alt_notend_table to handle
3716 bfextu %d0{24:1},%d0
3717 */
3718 alt_notend_table['0'] = 1;
3719 alt_notend_table['1'] = 1;
3720 alt_notend_table['2'] = 1;
3721 alt_notend_table['3'] = 1;
3722 alt_notend_table['4'] = 1;
3723 alt_notend_table['5'] = 1;
3724 alt_notend_table['6'] = 1;
3725 alt_notend_table['7'] = 1;
3726 alt_notend_table['8'] = 1;
3727 alt_notend_table['9'] = 1;
3728
3729 #ifndef MIT_SYNTAX_ONLY
3730 /* Insert pseudo ops, these have to go into the opcode table since
3731 gas expects pseudo ops to start with a dot */
3732 {
3733 int n = 0;
3734 while (mote_pseudo_table[n].poc_name)
3735 {
3736 hack = (struct m68k_incant *)
3737 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3738 hash_insert (op_hash,
3739 mote_pseudo_table[n].poc_name, (char *) hack);
3740 hack->m_operands = 0;
3741 hack->m_opnum = n;
3742 n++;
3743 }
3744 }
3745 #endif
3746
3747 init_regtable ();
3748
3749 #ifdef OBJ_ELF
3750 record_alignment (text_section, 2);
3751 record_alignment (data_section, 2);
3752 record_alignment (bss_section, 2);
3753 #endif
3754 }
3755
3756 static void
3757 select_control_regs ()
3758 {
3759 /* Note which set of "movec" control registers is available. */
3760 switch (cpu_of_arch (current_architecture))
3761 {
3762 case m68000:
3763 control_regs = m68000_control_regs;
3764 break;
3765 case m68010:
3766 control_regs = m68010_control_regs;
3767 break;
3768 case m68020:
3769 case m68030:
3770 control_regs = m68020_control_regs;
3771 break;
3772 case m68040:
3773 control_regs = m68040_control_regs;
3774 break;
3775 case m68060:
3776 control_regs = m68060_control_regs;
3777 break;
3778 case cpu32:
3779 control_regs = cpu32_control_regs;
3780 break;
3781 case mcf5200:
3782 control_regs = mcf5200_control_regs;
3783 break;
3784 default:
3785 abort ();
3786 }
3787 }
3788
3789 void
3790 m68k_init_after_args ()
3791 {
3792 if (cpu_of_arch (current_architecture) == 0)
3793 {
3794 int i;
3795 const char *default_cpu = TARGET_CPU;
3796
3797 if (*default_cpu == 'm')
3798 default_cpu++;
3799 for (i = 0; i < n_archs; i++)
3800 if (strcasecmp (default_cpu, archs[i].name) == 0)
3801 break;
3802 if (i == n_archs)
3803 {
3804 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3805 current_architecture |= m68020;
3806 }
3807 else
3808 current_architecture |= archs[i].arch;
3809 }
3810 /* Permit m68881 specification with all cpus; those that can't work
3811 with a coprocessor could be doing emulation. */
3812 if (current_architecture & m68851)
3813 {
3814 if (current_architecture & m68040)
3815 {
3816 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3817 }
3818 }
3819 /* What other incompatibilities could we check for? */
3820
3821 /* Toss in some default assumptions about coprocessors. */
3822 if (!no_68881
3823 && (cpu_of_arch (current_architecture)
3824 /* Can CPU32 have a 68881 coprocessor?? */
3825 & (m68020 | m68030 | cpu32)))
3826 {
3827 current_architecture |= m68881;
3828 }
3829 if (!no_68851
3830 && (cpu_of_arch (current_architecture) & m68020up) != 0
3831 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3832 {
3833 current_architecture |= m68851;
3834 }
3835 if (no_68881 && (current_architecture & m68881))
3836 as_bad (_("options for 68881 and no-68881 both given"));
3837 if (no_68851 && (current_architecture & m68851))
3838 as_bad (_("options for 68851 and no-68851 both given"));
3839
3840 #ifdef OBJ_AOUT
3841 /* Work out the magic number. This isn't very general. */
3842 if (current_architecture & m68000)
3843 m68k_aout_machtype = 0;
3844 else if (current_architecture & m68010)
3845 m68k_aout_machtype = 1;
3846 else if (current_architecture & m68020)
3847 m68k_aout_machtype = 2;
3848 else
3849 m68k_aout_machtype = 2;
3850 #endif
3851
3852 /* Note which set of "movec" control registers is available. */
3853 select_control_regs ();
3854
3855 if (cpu_of_arch (current_architecture) < m68020
3856 || cpu_of_arch (current_architecture) == mcf5200)
3857 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3858 }
3859 \f
3860 /* This is called when a label is defined. */
3861
3862 void
3863 m68k_frob_label (sym)
3864 symbolS *sym;
3865 {
3866 struct label_line *n;
3867
3868 n = (struct label_line *) xmalloc (sizeof *n);
3869 n->next = labels;
3870 n->label = sym;
3871 as_where (&n->file, &n->line);
3872 n->text = 0;
3873 labels = n;
3874 current_label = n;
3875 }
3876
3877 /* This is called when a value that is not an instruction is emitted. */
3878
3879 void
3880 m68k_flush_pending_output ()
3881 {
3882 current_label = NULL;
3883 }
3884
3885 /* This is called at the end of the assembly, when the final value of
3886 the label is known. We warn if this is a text symbol aligned at an
3887 odd location. */
3888
3889 void
3890 m68k_frob_symbol (sym)
3891 symbolS *sym;
3892 {
3893 if (S_GET_SEGMENT (sym) == reg_section
3894 && (int) S_GET_VALUE (sym) < 0)
3895 {
3896 S_SET_SEGMENT (sym, absolute_section);
3897 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
3898 }
3899 else if ((S_GET_VALUE (sym) & 1) != 0)
3900 {
3901 struct label_line *l;
3902
3903 for (l = labels; l != NULL; l = l->next)
3904 {
3905 if (l->label == sym)
3906 {
3907 if (l->text)
3908 as_warn_where (l->file, l->line,
3909 _("text label `%s' aligned to odd boundary"),
3910 S_GET_NAME (sym));
3911 break;
3912 }
3913 }
3914 }
3915 }
3916 \f
3917 /* This is called if we go in or out of MRI mode because of the .mri
3918 pseudo-op. */
3919
3920 void
3921 m68k_mri_mode_change (on)
3922 int on;
3923 {
3924 if (on)
3925 {
3926 if (! flag_reg_prefix_optional)
3927 {
3928 flag_reg_prefix_optional = 1;
3929 #ifdef REGISTER_PREFIX
3930 init_regtable ();
3931 #endif
3932 }
3933 m68k_abspcadd = 1;
3934 if (! m68k_rel32_from_cmdline)
3935 m68k_rel32 = 0;
3936 }
3937 else
3938 {
3939 if (! reg_prefix_optional_seen)
3940 {
3941 #ifdef REGISTER_PREFIX_OPTIONAL
3942 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3943 #else
3944 flag_reg_prefix_optional = 0;
3945 #endif
3946 #ifdef REGISTER_PREFIX
3947 init_regtable ();
3948 #endif
3949 }
3950 m68k_abspcadd = 0;
3951 if (! m68k_rel32_from_cmdline)
3952 m68k_rel32 = 1;
3953 }
3954 }
3955
3956 /* Equal to MAX_PRECISION in atof-ieee.c */
3957 #define MAX_LITTLENUMS 6
3958
3959 /* Turn a string in input_line_pointer into a floating point constant
3960 of type type, and store the appropriate bytes in *litP. The number
3961 of LITTLENUMS emitted is stored in *sizeP . An error message is
3962 returned, or NULL on OK. */
3963
3964 char *
3965 md_atof (type, litP, sizeP)
3966 char type;
3967 char *litP;
3968 int *sizeP;
3969 {
3970 int prec;
3971 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3972 LITTLENUM_TYPE *wordP;
3973 char *t;
3974
3975 switch (type)
3976 {
3977 case 'f':
3978 case 'F':
3979 case 's':
3980 case 'S':
3981 prec = 2;
3982 break;
3983
3984 case 'd':
3985 case 'D':
3986 case 'r':
3987 case 'R':
3988 prec = 4;
3989 break;
3990
3991 case 'x':
3992 case 'X':
3993 prec = 6;
3994 break;
3995
3996 case 'p':
3997 case 'P':
3998 prec = 6;
3999 break;
4000
4001 default:
4002 *sizeP = 0;
4003 return _("Bad call to MD_ATOF()");
4004 }
4005 t = atof_ieee (input_line_pointer, type, words);
4006 if (t)
4007 input_line_pointer = t;
4008
4009 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4010 for (wordP = words; prec--;)
4011 {
4012 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4013 litP += sizeof (LITTLENUM_TYPE);
4014 }
4015 return 0;
4016 }
4017
4018 void
4019 md_number_to_chars (buf, val, n)
4020 char *buf;
4021 valueT val;
4022 int n;
4023 {
4024 number_to_chars_bigendian (buf, val, n);
4025 }
4026
4027 static void
4028 md_apply_fix_2 (fixP, val)
4029 fixS *fixP;
4030 offsetT val;
4031 {
4032 addressT upper_limit;
4033 offsetT lower_limit;
4034
4035 /* This is unnecessary but it convinces the native rs6000 compiler
4036 to generate the code we want. */
4037 char *buf = fixP->fx_frag->fr_literal;
4038 buf += fixP->fx_where;
4039 /* end ibm compiler workaround */
4040
4041 if (val & 0x80000000)
4042 val |= ~(addressT)0x7fffffff;
4043 else
4044 val &= 0x7fffffff;
4045
4046 #ifdef OBJ_ELF
4047 if (fixP->fx_addsy)
4048 {
4049 memset (buf, 0, fixP->fx_size);
4050 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4051
4052 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4053 && !S_IS_DEFINED (fixP->fx_addsy)
4054 && !S_IS_WEAK (fixP->fx_addsy))
4055 S_SET_WEAK (fixP->fx_addsy);
4056 return;
4057 }
4058 #endif
4059
4060 #ifdef BFD_ASSEMBLER
4061 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4062 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4063 return;
4064 #endif
4065
4066 switch (fixP->fx_size)
4067 {
4068 /* The cast to offsetT below are necessary to make code correct for
4069 machines where ints are smaller than offsetT */
4070 case 1:
4071 *buf++ = val;
4072 upper_limit = 0x7f;
4073 lower_limit = - (offsetT) 0x80;
4074 break;
4075 case 2:
4076 *buf++ = (val >> 8);
4077 *buf++ = val;
4078 upper_limit = 0x7fff;
4079 lower_limit = - (offsetT) 0x8000;
4080 break;
4081 case 4:
4082 *buf++ = (val >> 24);
4083 *buf++ = (val >> 16);
4084 *buf++ = (val >> 8);
4085 *buf++ = val;
4086 upper_limit = 0x7fffffff;
4087 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4088 break;
4089 default:
4090 BAD_CASE (fixP->fx_size);
4091 }
4092
4093 /* Fix up a negative reloc. */
4094 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4095 {
4096 fixP->fx_addsy = fixP->fx_subsy;
4097 fixP->fx_subsy = NULL;
4098 fixP->fx_tcbit = 1;
4099 }
4100
4101 /* For non-pc-relative values, it's conceivable we might get something
4102 like "0xff" for a byte field. So extend the upper part of the range
4103 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4104 so that we can do any range checking at all. */
4105 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4106 upper_limit = upper_limit * 2 + 1;
4107
4108 if ((addressT) val > upper_limit
4109 && (val > 0 || val < lower_limit))
4110 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4111
4112 /* A one byte PC-relative reloc means a short branch. We can't use
4113 a short branch with a value of 0 or -1, because those indicate
4114 different opcodes (branches with longer offsets). fixup_segment
4115 in write.c may have clobbered fx_pcrel, so we need to examine the
4116 reloc type. */
4117 if ((fixP->fx_pcrel
4118 #ifdef BFD_ASSEMBLER
4119 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4120 #endif
4121 )
4122 && fixP->fx_size == 1
4123 && (fixP->fx_addsy == NULL
4124 || S_IS_DEFINED (fixP->fx_addsy))
4125 && (val == 0 || val == -1))
4126 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4127 }
4128
4129 #ifdef BFD_ASSEMBLER
4130 int
4131 md_apply_fix (fixP, valp)
4132 fixS *fixP;
4133 valueT *valp;
4134 {
4135 md_apply_fix_2 (fixP, (addressT) *valp);
4136 return 1;
4137 }
4138 #else
4139 void md_apply_fix (fixP, val)
4140 fixS *fixP;
4141 long val;
4142 {
4143 md_apply_fix_2 (fixP, (addressT) val);
4144 }
4145 #endif
4146
4147 /* *fragP has been relaxed to its final size, and now needs to have
4148 the bytes inside it modified to conform to the new size There is UGLY
4149 MAGIC here. ..
4150 */
4151 static void
4152 md_convert_frag_1 (fragP)
4153 register fragS *fragP;
4154 {
4155 long disp;
4156 long ext = 0;
4157 fixS *fixP;
4158
4159 /* Address in object code of the displacement. */
4160 register int object_address = fragP->fr_fix + fragP->fr_address;
4161
4162 /* Address in gas core of the place to store the displacement. */
4163 /* This convinces the native rs6000 compiler to generate the code we
4164 want. */
4165 register char *buffer_address = fragP->fr_literal;
4166 buffer_address += fragP->fr_fix;
4167 /* end ibm compiler workaround */
4168
4169 /* The displacement of the address, from current location. */
4170 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4171 disp = (disp + fragP->fr_offset) - object_address;
4172
4173 #ifdef BFD_ASSEMBLER
4174 disp += fragP->fr_symbol->sy_frag->fr_address;
4175 #endif
4176
4177 switch (fragP->fr_subtype)
4178 {
4179 case TAB (BCC68000, BYTE):
4180 case TAB (ABRANCH, BYTE):
4181 know (issbyte (disp));
4182 if (disp == 0)
4183 as_bad (_("short branch with zero offset: use :w"));
4184 fragP->fr_opcode[1] = disp;
4185 ext = 0;
4186 break;
4187 case TAB (DBCC, SHORT):
4188 know (issword (disp));
4189 ext = 2;
4190 break;
4191 case TAB (BCC68000, SHORT):
4192 case TAB (ABRANCH, SHORT):
4193 know (issword (disp));
4194 fragP->fr_opcode[1] = 0x00;
4195 ext = 2;
4196 break;
4197 case TAB (ABRANCH, LONG):
4198 if (!HAVE_LONG_BRANCH(current_architecture))
4199 {
4200 if (fragP->fr_opcode[0] == 0x61)
4201 /* BSR */
4202 {
4203 fragP->fr_opcode[0] = 0x4E;
4204 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4205
4206 fix_new (fragP,
4207 fragP->fr_fix,
4208 4,
4209 fragP->fr_symbol,
4210 fragP->fr_offset,
4211 0,
4212 NO_RELOC);
4213
4214 fragP->fr_fix += 4;
4215 ext = 0;
4216 }
4217 /* BRA */
4218 else if (fragP->fr_opcode[0] == 0x60)
4219 {
4220 fragP->fr_opcode[0] = 0x4E;
4221 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4222 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4223 fragP->fr_offset, 0, NO_RELOC);
4224 fragP->fr_fix += 4;
4225 ext = 0;
4226 }
4227 else
4228 {
4229 as_bad (_("Long branch offset not supported."));
4230 }
4231 }
4232 else
4233 {
4234 fragP->fr_opcode[1] = (char) 0xff;
4235 ext = 4;
4236 }
4237 break;
4238 case TAB (BCC68000, LONG):
4239 /* only Bcc 68000 instructions can come here */
4240 /* change bcc into b!cc/jmp absl long */
4241 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4242 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4243
4244 /* JF: these used to be fr_opcode[2,3], but they may be in a
4245 different frag, in which case refering to them is a no-no.
4246 Only fr_opcode[0,1] are guaranteed to work. */
4247 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4248 *buffer_address++ = (char) 0xf9;
4249 fragP->fr_fix += 2; /* account for jmp instruction */
4250 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4251 fragP->fr_offset, 0, NO_RELOC);
4252 fragP->fr_fix += 4;
4253 ext = 0;
4254 break;
4255 case TAB (DBCC, LONG):
4256 /* only DBcc 68000 instructions can come here */
4257 /* change dbcc into dbcc/jmp absl long */
4258 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4259 *buffer_address++ = 0x00; /* branch offset = 4 */
4260 *buffer_address++ = 0x04;
4261 *buffer_address++ = 0x60; /* put in bra pc+6 */
4262 *buffer_address++ = 0x06;
4263 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4264 *buffer_address++ = (char) 0xf9;
4265
4266 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4267 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4268 fragP->fr_offset, 0, NO_RELOC);
4269 fragP->fr_fix += 4;
4270 ext = 0;
4271 break;
4272 case TAB (FBRANCH, SHORT):
4273 know ((fragP->fr_opcode[1] & 0x40) == 0);
4274 ext = 2;
4275 break;
4276 case TAB (FBRANCH, LONG):
4277 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4278 ext = 4;
4279 break;
4280 case TAB (PCREL, SHORT):
4281 ext = 2;
4282 break;
4283 case TAB (PCREL, LONG):
4284 /* The thing to do here is force it to ABSOLUTE LONG, since
4285 PCREL is really trying to shorten an ABSOLUTE address anyway */
4286 /* JF FOO This code has not been tested */
4287 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4288 0, NO_RELOC);
4289 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4290 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4291 (unsigned) fragP->fr_opcode[0],
4292 (unsigned long) fragP->fr_address);
4293 fragP->fr_opcode[1] &= ~0x3F;
4294 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4295 fragP->fr_fix += 4;
4296 ext = 0;
4297 break;
4298 case TAB (PCLEA, SHORT):
4299 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4300 fragP->fr_offset, 1, NO_RELOC);
4301 fragP->fr_opcode[1] &= ~0x3F;
4302 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4303 ext = 2;
4304 break;
4305 case TAB (PCLEA, LONG):
4306 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4307 fragP->fr_offset, 1, NO_RELOC);
4308 fixP->fx_pcrel_adjust = 2;
4309 /* Already set to mode 7.3; this indicates: PC indirect with
4310 suppressed index, 32-bit displacement. */
4311 *buffer_address++ = 0x01;
4312 *buffer_address++ = 0x70;
4313 fragP->fr_fix += 2;
4314 ext = 4;
4315 break;
4316
4317 case TAB (PCINDEX, BYTE):
4318 disp += 2;
4319 if (!issbyte (disp))
4320 {
4321 as_bad (_("displacement doesn't fit in one byte"));
4322 disp = 0;
4323 }
4324 assert (fragP->fr_fix >= 2);
4325 buffer_address[-2] &= ~1;
4326 buffer_address[-1] = disp;
4327 ext = 0;
4328 break;
4329 case TAB (PCINDEX, SHORT):
4330 disp += 2;
4331 assert (issword (disp));
4332 assert (fragP->fr_fix >= 2);
4333 buffer_address[-2] |= 0x1;
4334 buffer_address[-1] = 0x20;
4335 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4336 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4337 NO_RELOC);
4338 fixP->fx_pcrel_adjust = 2;
4339 ext = 2;
4340 break;
4341 case TAB (PCINDEX, LONG):
4342 disp += 2;
4343 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4344 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4345 NO_RELOC);
4346 fixP->fx_pcrel_adjust = 2;
4347 assert (fragP->fr_fix >= 2);
4348 buffer_address[-2] |= 0x1;
4349 buffer_address[-1] = 0x30;
4350 ext = 4;
4351 break;
4352 }
4353
4354 if (ext)
4355 {
4356 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4357 fragP->fr_fix += ext;
4358 }
4359 }
4360
4361 #ifndef BFD_ASSEMBLER
4362
4363 void
4364 md_convert_frag (headers, sec, fragP)
4365 object_headers *headers;
4366 segT sec;
4367 fragS *fragP;
4368 {
4369 md_convert_frag_1 (fragP);
4370 }
4371
4372 #else
4373
4374 void
4375 md_convert_frag (abfd, sec, fragP)
4376 bfd *abfd;
4377 segT sec;
4378 fragS *fragP;
4379 {
4380 md_convert_frag_1 (fragP);
4381 }
4382 #endif
4383
4384 /* Force truly undefined symbols to their maximum size, and generally set up
4385 the frag list to be relaxed
4386 */
4387 int
4388 md_estimate_size_before_relax (fragP, segment)
4389 register fragS *fragP;
4390 segT segment;
4391 {
4392 int old_fix;
4393 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4394
4395 old_fix = fragP->fr_fix;
4396
4397 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4398 switch (fragP->fr_subtype)
4399 {
4400
4401 case TAB (ABRANCH, SZ_UNDEF):
4402 {
4403 if ((fragP->fr_symbol != NULL) /* Not absolute */
4404 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4405 && relaxable_symbol (fragP->fr_symbol))
4406 {
4407 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4408 break;
4409 }
4410 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4411 {
4412 /* On 68000, or for absolute value, switch to abs long */
4413 /* FIXME, we should check abs val, pick short or long */
4414 if (fragP->fr_opcode[0] == 0x61)
4415 {
4416 fragP->fr_opcode[0] = 0x4E;
4417 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4418 fix_new (fragP, fragP->fr_fix, 4,
4419 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4420 fragP->fr_fix += 4;
4421 frag_wane (fragP);
4422 }
4423 else if (fragP->fr_opcode[0] == 0x60)
4424 {
4425 fragP->fr_opcode[0] = 0x4E;
4426 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4427 fix_new (fragP, fragP->fr_fix, 4,
4428 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4429 fragP->fr_fix += 4;
4430 frag_wane (fragP);
4431 }
4432 else
4433 {
4434 as_warn (_("Long branch offset to extern symbol not supported."));
4435 }
4436 }
4437 else
4438 { /* Symbol is still undefined. Make it simple */
4439 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4440 fragP->fr_offset, 1, NO_RELOC);
4441 fragP->fr_fix += 4;
4442 fragP->fr_opcode[1] = (char) 0xff;
4443 frag_wane (fragP);
4444 break;
4445 }
4446
4447 break;
4448 } /* case TAB(ABRANCH,SZ_UNDEF) */
4449
4450 case TAB (FBRANCH, SZ_UNDEF):
4451 {
4452 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4453 && relaxable_symbol (fragP->fr_symbol))
4454 || flag_short_refs)
4455 {
4456 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4457 fragP->fr_var += 2;
4458 }
4459 else
4460 {
4461 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4462 fragP->fr_offset, 1, NO_RELOC);
4463 fragP->fr_fix += 4;
4464 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4465 frag_wane (fragP);
4466 }
4467 break;
4468 } /* TAB(FBRANCH,SZ_UNDEF) */
4469
4470 case TAB (PCREL, SZ_UNDEF):
4471 {
4472 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4473 && relaxable_symbol (fragP->fr_symbol))
4474 || flag_short_refs
4475 || cpu_of_arch (current_architecture) < m68020
4476 || cpu_of_arch (current_architecture) == mcf5200)
4477 {
4478 fragP->fr_subtype = TAB (PCREL, SHORT);
4479 fragP->fr_var += 2;
4480 }
4481 else
4482 {
4483 fragP->fr_subtype = TAB (PCREL, LONG);
4484 fragP->fr_var += 4;
4485 }
4486 break;
4487 } /* TAB(PCREL,SZ_UNDEF) */
4488
4489 case TAB (BCC68000, SZ_UNDEF):
4490 {
4491 if ((fragP->fr_symbol != NULL)
4492 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4493 && relaxable_symbol (fragP->fr_symbol))
4494 {
4495 fragP->fr_subtype = TAB (BCC68000, BYTE);
4496 break;
4497 }
4498 /* only Bcc 68000 instructions can come here */
4499 /* change bcc into b!cc/jmp absl long */
4500 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4501 if (flag_short_refs)
4502 {
4503 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4504 /* JF: these were fr_opcode[2,3] */
4505 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4506 buffer_address[1] = (char) 0xf8;
4507 fragP->fr_fix += 2; /* account for jmp instruction */
4508 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4509 fragP->fr_offset, 0, NO_RELOC);
4510 fragP->fr_fix += 2;
4511 }
4512 else
4513 {
4514 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4515 /* JF: these were fr_opcode[2,3] */
4516 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4517 buffer_address[1] = (char) 0xf9;
4518 fragP->fr_fix += 2; /* account for jmp instruction */
4519 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4520 fragP->fr_offset, 0, NO_RELOC);
4521 fragP->fr_fix += 4;
4522 }
4523 frag_wane (fragP);
4524 break;
4525 } /* case TAB(BCC68000,SZ_UNDEF) */
4526
4527 case TAB (DBCC, SZ_UNDEF):
4528 {
4529 if (fragP->fr_symbol != NULL
4530 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4531 && relaxable_symbol (fragP->fr_symbol))
4532 {
4533 fragP->fr_subtype = TAB (DBCC, SHORT);
4534 fragP->fr_var += 2;
4535 break;
4536 }
4537 /* only DBcc 68000 instructions can come here */
4538 /* change dbcc into dbcc/jmp absl long */
4539 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4540 buffer_address[0] = 0x00; /* branch offset = 4 */
4541 buffer_address[1] = 0x04;
4542 buffer_address[2] = 0x60; /* put in bra pc + ... */
4543
4544 if (flag_short_refs)
4545 {
4546 /* JF: these were fr_opcode[5-7] */
4547 buffer_address[3] = 0x04; /* plus 4 */
4548 buffer_address[4] = 0x4e; /* Put in Jump Word */
4549 buffer_address[5] = (char) 0xf8;
4550 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4551 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4552 fragP->fr_offset, 0, NO_RELOC);
4553 fragP->fr_fix += 2;
4554 }
4555 else
4556 {
4557 /* JF: these were fr_opcode[5-7] */
4558 buffer_address[3] = 0x06; /* Plus 6 */
4559 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4560 buffer_address[5] = (char) 0xf9;
4561 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4562 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4563 fragP->fr_offset, 0, NO_RELOC);
4564 fragP->fr_fix += 4;
4565 }
4566
4567 frag_wane (fragP);
4568 break;
4569 } /* case TAB(DBCC,SZ_UNDEF) */
4570
4571 case TAB (PCLEA, SZ_UNDEF):
4572 {
4573 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4574 && relaxable_symbol (fragP->fr_symbol))
4575 || flag_short_refs
4576 || cpu_of_arch (current_architecture) < m68020
4577 || cpu_of_arch (current_architecture) == mcf5200)
4578 {
4579 fragP->fr_subtype = TAB (PCLEA, SHORT);
4580 fragP->fr_var += 2;
4581 }
4582 else
4583 {
4584 fragP->fr_subtype = TAB (PCLEA, LONG);
4585 fragP->fr_var += 6;
4586 }
4587 break;
4588 } /* TAB(PCLEA,SZ_UNDEF) */
4589
4590 case TAB (PCINDEX, SZ_UNDEF):
4591 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4592 && relaxable_symbol (fragP->fr_symbol))
4593 || cpu_of_arch (current_architecture) < m68020
4594 || cpu_of_arch (current_architecture) == mcf5200)
4595 {
4596 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4597 }
4598 else
4599 {
4600 fragP->fr_subtype = TAB (PCINDEX, LONG);
4601 fragP->fr_var += 4;
4602 }
4603 break;
4604
4605 default:
4606 break;
4607 }
4608
4609 /* now that SZ_UNDEF are taken care of, check others */
4610 switch (fragP->fr_subtype)
4611 {
4612 case TAB (BCC68000, BYTE):
4613 case TAB (ABRANCH, BYTE):
4614 /* We can't do a short jump to the next instruction, so in that
4615 case we force word mode. At this point S_GET_VALUE should
4616 return the offset of the symbol within its frag. If the
4617 symbol is at the start of a frag, and it is the next frag
4618 with any data in it (usually this is just the next frag, but
4619 assembler listings may introduce empty frags), we must use
4620 word mode. */
4621 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4622 {
4623 fragS *l;
4624
4625 for (l = fragP->fr_next;
4626 l != fragP->fr_symbol->sy_frag;
4627 l = l->fr_next)
4628 if (l->fr_fix + l->fr_var != 0)
4629 break;
4630 if (l == fragP->fr_symbol->sy_frag)
4631 {
4632 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4633 fragP->fr_var += 2;
4634 }
4635 }
4636 break;
4637 default:
4638 break;
4639 }
4640 return fragP->fr_var + fragP->fr_fix - old_fix;
4641 }
4642
4643 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4644 /* the bit-field entries in the relocation_info struct plays hell
4645 with the byte-order problems of cross-assembly. So as a hack,
4646 I added this mach. dependent ri twiddler. Ugly, but it gets
4647 you there. -KWK */
4648 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4649 are symbolnum, most sig. byte first. Last byte is broken up with
4650 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4651 nibble as nuthin. (on Sun 3 at least) */
4652 /* Translate the internal relocation information into target-specific
4653 format. */
4654 #ifdef comment
4655 void
4656 md_ri_to_chars (the_bytes, ri)
4657 char *the_bytes;
4658 struct reloc_info_generic *ri;
4659 {
4660 /* this is easy */
4661 md_number_to_chars (the_bytes, ri->r_address, 4);
4662 /* now the fun stuff */
4663 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4664 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4665 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4666 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4667 ((ri->r_extern << 4) & 0x10));
4668 }
4669
4670 #endif /* comment */
4671
4672 #ifndef BFD_ASSEMBLER
4673 void
4674 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4675 char *where;
4676 fixS *fixP;
4677 relax_addressT segment_address_in_file;
4678 {
4679 /*
4680 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4681 * Out: GNU LD relocation length code: 0, 1, or 2.
4682 */
4683
4684 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4685 long r_symbolnum;
4686
4687 know (fixP->fx_addsy != NULL);
4688
4689 md_number_to_chars (where,
4690 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4691 4);
4692
4693 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4694 ? S_GET_TYPE (fixP->fx_addsy)
4695 : fixP->fx_addsy->sy_number);
4696
4697 where[4] = (r_symbolnum >> 16) & 0x0ff;
4698 where[5] = (r_symbolnum >> 8) & 0x0ff;
4699 where[6] = r_symbolnum & 0x0ff;
4700 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4701 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4702 }
4703 #endif
4704
4705 #endif /* OBJ_AOUT or OBJ_BOUT */
4706
4707 #ifndef WORKING_DOT_WORD
4708 CONST int md_short_jump_size = 4;
4709 CONST int md_long_jump_size = 6;
4710
4711 void
4712 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4713 char *ptr;
4714 addressT from_addr, to_addr;
4715 fragS *frag;
4716 symbolS *to_symbol;
4717 {
4718 valueT offset;
4719
4720 offset = to_addr - (from_addr + 2);
4721
4722 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4723 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4724 }
4725
4726 void
4727 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4728 char *ptr;
4729 addressT from_addr, to_addr;
4730 fragS *frag;
4731 symbolS *to_symbol;
4732 {
4733 valueT offset;
4734
4735 if (!HAVE_LONG_BRANCH(current_architecture))
4736 {
4737 offset = to_addr - S_GET_VALUE (to_symbol);
4738 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4739 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4740 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4741 0, NO_RELOC);
4742 }
4743 else
4744 {
4745 offset = to_addr - (from_addr + 2);
4746 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4747 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4748 }
4749 }
4750
4751 #endif
4752
4753 /* Different values of OK tell what its OK to return. Things that
4754 aren't OK are an error (what a shock, no?)
4755
4756 0: Everything is OK
4757 10: Absolute 1:8 only
4758 20: Absolute 0:7 only
4759 30: absolute 0:15 only
4760 40: Absolute 0:31 only
4761 50: absolute 0:127 only
4762 55: absolute -64:63 only
4763 60: absolute -128:127 only
4764 70: absolute 0:4095 only
4765 80: No bignums
4766
4767 */
4768
4769 static int
4770 get_num (exp, ok)
4771 struct m68k_exp *exp;
4772 int ok;
4773 {
4774 if (exp->exp.X_op == O_absent)
4775 {
4776 /* Do the same thing the VAX asm does */
4777 op (exp) = O_constant;
4778 adds (exp) = 0;
4779 subs (exp) = 0;
4780 offs (exp) = 0;
4781 if (ok == 10)
4782 {
4783 as_warn (_("expression out of range: defaulting to 1"));
4784 offs (exp) = 1;
4785 }
4786 }
4787 else if (exp->exp.X_op == O_constant)
4788 {
4789 switch (ok)
4790 {
4791 case 10:
4792 if (offs (exp) < 1 || offs (exp) > 8)
4793 {
4794 as_warn (_("expression out of range: defaulting to 1"));
4795 offs (exp) = 1;
4796 }
4797 break;
4798 case 20:
4799 if (offs (exp) < 0 || offs (exp) > 7)
4800 goto outrange;
4801 break;
4802 case 30:
4803 if (offs (exp) < 0 || offs (exp) > 15)
4804 goto outrange;
4805 break;
4806 case 40:
4807 if (offs (exp) < 0 || offs (exp) > 32)
4808 goto outrange;
4809 break;
4810 case 50:
4811 if (offs (exp) < 0 || offs (exp) > 127)
4812 goto outrange;
4813 break;
4814 case 55:
4815 if (offs (exp) < -64 || offs (exp) > 63)
4816 goto outrange;
4817 break;
4818 case 60:
4819 if (offs (exp) < -128 || offs (exp) > 127)
4820 goto outrange;
4821 break;
4822 case 70:
4823 if (offs (exp) < 0 || offs (exp) > 4095)
4824 {
4825 outrange:
4826 as_warn (_("expression out of range: defaulting to 0"));
4827 offs (exp) = 0;
4828 }
4829 break;
4830 default:
4831 break;
4832 }
4833 }
4834 else if (exp->exp.X_op == O_big)
4835 {
4836 if (offs (exp) <= 0 /* flonum */
4837 && (ok == 80 /* no bignums */
4838 || (ok > 10 /* small-int ranges including 0 ok */
4839 /* If we have a flonum zero, a zero integer should
4840 do as well (e.g., in moveq). */
4841 && generic_floating_point_number.exponent == 0
4842 && generic_floating_point_number.low[0] == 0)))
4843 {
4844 /* HACK! Turn it into a long */
4845 LITTLENUM_TYPE words[6];
4846
4847 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4848 op (exp) = O_constant;
4849 adds (exp) = 0;
4850 subs (exp) = 0;
4851 offs (exp) = words[1] | (words[0] << 16);
4852 }
4853 else if (ok != 0)
4854 {
4855 op (exp) = O_constant;
4856 adds (exp) = 0;
4857 subs (exp) = 0;
4858 offs (exp) = (ok == 10) ? 1 : 0;
4859 as_warn (_("Can't deal with expression; defaulting to %ld"),
4860 offs (exp));
4861 }
4862 }
4863 else
4864 {
4865 if (ok >= 10 && ok <= 70)
4866 {
4867 op (exp) = O_constant;
4868 adds (exp) = 0;
4869 subs (exp) = 0;
4870 offs (exp) = (ok == 10) ? 1 : 0;
4871 as_warn (_("Can't deal with expression; defaulting to %ld"),
4872 offs (exp));
4873 }
4874 }
4875
4876 if (exp->size != SIZE_UNSPEC)
4877 {
4878 switch (exp->size)
4879 {
4880 case SIZE_UNSPEC:
4881 case SIZE_LONG:
4882 break;
4883 case SIZE_BYTE:
4884 if (!isbyte (offs (exp)))
4885 as_warn (_("expression doesn't fit in BYTE"));
4886 break;
4887 case SIZE_WORD:
4888 if (!isword (offs (exp)))
4889 as_warn (_("expression doesn't fit in WORD"));
4890 break;
4891 }
4892 }
4893
4894 return offs (exp);
4895 }
4896
4897 /* These are the back-ends for the various machine dependent pseudo-ops. */
4898
4899 static void
4900 s_data1 (ignore)
4901 int ignore;
4902 {
4903 subseg_set (data_section, 1);
4904 demand_empty_rest_of_line ();
4905 }
4906
4907 static void
4908 s_data2 (ignore)
4909 int ignore;
4910 {
4911 subseg_set (data_section, 2);
4912 demand_empty_rest_of_line ();
4913 }
4914
4915 static void
4916 s_bss (ignore)
4917 int ignore;
4918 {
4919 /* We don't support putting frags in the BSS segment, we fake it
4920 by marking in_bss, then looking at s_skip for clues. */
4921
4922 subseg_set (bss_section, 0);
4923 demand_empty_rest_of_line ();
4924 }
4925
4926 static void
4927 s_even (ignore)
4928 int ignore;
4929 {
4930 register int temp;
4931 register long temp_fill;
4932
4933 temp = 1; /* JF should be 2? */
4934 temp_fill = get_absolute_expression ();
4935 if (!need_pass_2) /* Never make frag if expect extra pass. */
4936 frag_align (temp, (int) temp_fill, 0);
4937 demand_empty_rest_of_line ();
4938 record_alignment (now_seg, temp);
4939 }
4940
4941 static void
4942 s_proc (ignore)
4943 int ignore;
4944 {
4945 demand_empty_rest_of_line ();
4946 }
4947 \f
4948 /* Pseudo-ops handled for MRI compatibility. */
4949
4950 /* This function returns non-zero if the argument is a conditional
4951 pseudo-op. This is called when checking whether a pending
4952 alignment is needed. */
4953
4954 int
4955 m68k_conditional_pseudoop (pop)
4956 pseudo_typeS *pop;
4957 {
4958 return (pop->poc_handler == s_mri_if
4959 || pop->poc_handler == s_mri_else);
4960 }
4961
4962 /* Handle an MRI style chip specification. */
4963
4964 static void
4965 mri_chip ()
4966 {
4967 char *s;
4968 char c;
4969 int i;
4970
4971 s = input_line_pointer;
4972 /* We can't use get_symbol_end since the processor names are not proper
4973 symbols. */
4974 while (is_part_of_name (c = *input_line_pointer++))
4975 ;
4976 *--input_line_pointer = 0;
4977 for (i = 0; i < n_archs; i++)
4978 if (strcasecmp (s, archs[i].name) == 0)
4979 break;
4980 if (i >= n_archs)
4981 {
4982 as_bad (_("%s: unrecognized processor name"), s);
4983 *input_line_pointer = c;
4984 ignore_rest_of_line ();
4985 return;
4986 }
4987 *input_line_pointer = c;
4988
4989 if (*input_line_pointer == '/')
4990 current_architecture = 0;
4991 else
4992 current_architecture &= m68881 | m68851;
4993 current_architecture |= archs[i].arch;
4994
4995 while (*input_line_pointer == '/')
4996 {
4997 ++input_line_pointer;
4998 s = input_line_pointer;
4999 /* We can't use get_symbol_end since the processor names are not
5000 proper symbols. */
5001 while (is_part_of_name (c = *input_line_pointer++))
5002 ;
5003 *--input_line_pointer = 0;
5004 if (strcmp (s, "68881") == 0)
5005 current_architecture |= m68881;
5006 else if (strcmp (s, "68851") == 0)
5007 current_architecture |= m68851;
5008 *input_line_pointer = c;
5009 }
5010
5011 /* Update info about available control registers. */
5012 select_control_regs ();
5013 }
5014
5015 /* The MRI CHIP pseudo-op. */
5016
5017 static void
5018 s_chip (ignore)
5019 int ignore;
5020 {
5021 char *stop = NULL;
5022 char stopc;
5023
5024 if (flag_mri)
5025 stop = mri_comment_field (&stopc);
5026 mri_chip ();
5027 if (flag_mri)
5028 mri_comment_end (stop, stopc);
5029 demand_empty_rest_of_line ();
5030 }
5031
5032 /* The MRI FOPT pseudo-op. */
5033
5034 static void
5035 s_fopt (ignore)
5036 int ignore;
5037 {
5038 SKIP_WHITESPACE ();
5039
5040 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5041 {
5042 int temp;
5043
5044 input_line_pointer += 3;
5045 temp = get_absolute_expression ();
5046 if (temp < 0 || temp > 7)
5047 as_bad (_("bad coprocessor id"));
5048 else
5049 m68k_float_copnum = COP0 + temp;
5050 }
5051 else
5052 {
5053 as_bad (_("unrecognized fopt option"));
5054 ignore_rest_of_line ();
5055 return;
5056 }
5057
5058 demand_empty_rest_of_line ();
5059 }
5060
5061 /* The structure used to handle the MRI OPT pseudo-op. */
5062
5063 struct opt_action
5064 {
5065 /* The name of the option. */
5066 const char *name;
5067
5068 /* If this is not NULL, just call this function. The first argument
5069 is the ARG field of this structure, the second argument is
5070 whether the option was negated. */
5071 void (*pfn) PARAMS ((int arg, int on));
5072
5073 /* If this is not NULL, and the PFN field is NULL, set the variable
5074 this points to. Set it to the ARG field if the option was not
5075 negated, and the NOTARG field otherwise. */
5076 int *pvar;
5077
5078 /* The value to pass to PFN or to assign to *PVAR. */
5079 int arg;
5080
5081 /* The value to assign to *PVAR if the option is negated. If PFN is
5082 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5083 the option may not be negated. */
5084 int notarg;
5085 };
5086
5087 /* The table used to handle the MRI OPT pseudo-op. */
5088
5089 static void skip_to_comma PARAMS ((int, int));
5090 static void opt_nest PARAMS ((int, int));
5091 static void opt_chip PARAMS ((int, int));
5092 static void opt_list PARAMS ((int, int));
5093 static void opt_list_symbols PARAMS ((int, int));
5094
5095 static const struct opt_action opt_table[] =
5096 {
5097 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5098
5099 /* We do relaxing, so there is little use for these options. */
5100 { "b", 0, 0, 0, 0 },
5101 { "brs", 0, 0, 0, 0 },
5102 { "brb", 0, 0, 0, 0 },
5103 { "brl", 0, 0, 0, 0 },
5104 { "brw", 0, 0, 0, 0 },
5105
5106 { "c", 0, 0, 0, 0 },
5107 { "cex", 0, 0, 0, 0 },
5108 { "case", 0, &symbols_case_sensitive, 1, 0 },
5109 { "cl", 0, 0, 0, 0 },
5110 { "cre", 0, 0, 0, 0 },
5111 { "d", 0, &flag_keep_locals, 1, 0 },
5112 { "e", 0, 0, 0, 0 },
5113 { "f", 0, &flag_short_refs, 1, 0 },
5114 { "frs", 0, &flag_short_refs, 1, 0 },
5115 { "frl", 0, &flag_short_refs, 0, 1 },
5116 { "g", 0, 0, 0, 0 },
5117 { "i", 0, 0, 0, 0 },
5118 { "m", 0, 0, 0, 0 },
5119 { "mex", 0, 0, 0, 0 },
5120 { "mc", 0, 0, 0, 0 },
5121 { "md", 0, 0, 0, 0 },
5122 { "nest", opt_nest, 0, 0, 0 },
5123 { "next", skip_to_comma, 0, 0, 0 },
5124 { "o", 0, 0, 0, 0 },
5125 { "old", 0, 0, 0, 0 },
5126 { "op", skip_to_comma, 0, 0, 0 },
5127 { "pco", 0, 0, 0, 0 },
5128 { "p", opt_chip, 0, 0, 0 },
5129 { "pcr", 0, 0, 0, 0 },
5130 { "pcs", 0, 0, 0, 0 },
5131 { "r", 0, 0, 0, 0 },
5132 { "quick", 0, &m68k_quick, 1, 0 },
5133 { "rel32", 0, &m68k_rel32, 1, 0 },
5134 { "s", opt_list, 0, 0, 0 },
5135 { "t", opt_list_symbols, 0, 0, 0 },
5136 { "w", 0, &flag_no_warnings, 0, 1 },
5137 { "x", 0, 0, 0, 0 }
5138 };
5139
5140 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5141
5142 /* The MRI OPT pseudo-op. */
5143
5144 static void
5145 s_opt (ignore)
5146 int ignore;
5147 {
5148 do
5149 {
5150 int t;
5151 char *s;
5152 char c;
5153 int i;
5154 const struct opt_action *o;
5155
5156 SKIP_WHITESPACE ();
5157
5158 t = 1;
5159 if (*input_line_pointer == '-')
5160 {
5161 ++input_line_pointer;
5162 t = 0;
5163 }
5164 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5165 {
5166 input_line_pointer += 2;
5167 t = 0;
5168 }
5169
5170 s = input_line_pointer;
5171 c = get_symbol_end ();
5172
5173 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5174 {
5175 if (strcasecmp (s, o->name) == 0)
5176 {
5177 if (o->pfn)
5178 {
5179 /* Restore input_line_pointer now in case the option
5180 takes arguments. */
5181 *input_line_pointer = c;
5182 (*o->pfn) (o->arg, t);
5183 }
5184 else if (o->pvar != NULL)
5185 {
5186 if (! t && o->arg == o->notarg)
5187 as_bad (_("option `%s' may not be negated"), s);
5188 *input_line_pointer = c;
5189 *o->pvar = t ? o->arg : o->notarg;
5190 }
5191 else
5192 *input_line_pointer = c;
5193 break;
5194 }
5195 }
5196 if (i >= OPTCOUNT)
5197 {
5198 as_bad (_("option `%s' not recognized"), s);
5199 *input_line_pointer = c;
5200 }
5201 }
5202 while (*input_line_pointer++ == ',');
5203
5204 /* Move back to terminating character. */
5205 --input_line_pointer;
5206 demand_empty_rest_of_line ();
5207 }
5208
5209 /* Skip ahead to a comma. This is used for OPT options which we do
5210 not suppor tand which take arguments. */
5211
5212 static void
5213 skip_to_comma (arg, on)
5214 int arg;
5215 int on;
5216 {
5217 while (*input_line_pointer != ','
5218 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5219 ++input_line_pointer;
5220 }
5221
5222 /* Handle the OPT NEST=depth option. */
5223
5224 static void
5225 opt_nest (arg, on)
5226 int arg;
5227 int on;
5228 {
5229 if (*input_line_pointer != '=')
5230 {
5231 as_bad (_("bad format of OPT NEST=depth"));
5232 return;
5233 }
5234
5235 ++input_line_pointer;
5236 max_macro_nest = get_absolute_expression ();
5237 }
5238
5239 /* Handle the OPT P=chip option. */
5240
5241 static void
5242 opt_chip (arg, on)
5243 int arg;
5244 int on;
5245 {
5246 if (*input_line_pointer != '=')
5247 {
5248 /* This is just OPT P, which we do not support. */
5249 return;
5250 }
5251
5252 ++input_line_pointer;
5253 mri_chip ();
5254 }
5255
5256 /* Handle the OPT S option. */
5257
5258 static void
5259 opt_list (arg, on)
5260 int arg;
5261 int on;
5262 {
5263 listing_list (on);
5264 }
5265
5266 /* Handle the OPT T option. */
5267
5268 static void
5269 opt_list_symbols (arg, on)
5270 int arg;
5271 int on;
5272 {
5273 if (on)
5274 listing |= LISTING_SYMBOLS;
5275 else
5276 listing &=~ LISTING_SYMBOLS;
5277 }
5278
5279 /* Handle the MRI REG pseudo-op. */
5280
5281 static void
5282 s_reg (ignore)
5283 int ignore;
5284 {
5285 char *s;
5286 int c;
5287 struct m68k_op rop;
5288 int mask;
5289 char *stop = NULL;
5290 char stopc;
5291
5292 if (line_label == NULL)
5293 {
5294 as_bad (_("missing label"));
5295 ignore_rest_of_line ();
5296 return;
5297 }
5298
5299 if (flag_mri)
5300 stop = mri_comment_field (&stopc);
5301
5302 SKIP_WHITESPACE ();
5303
5304 s = input_line_pointer;
5305 while (isalnum ((unsigned char) *input_line_pointer)
5306 #ifdef REGISTER_PREFIX
5307 || *input_line_pointer == REGISTER_PREFIX
5308 #endif
5309 || *input_line_pointer == '/'
5310 || *input_line_pointer == '-')
5311 ++input_line_pointer;
5312 c = *input_line_pointer;
5313 *input_line_pointer = '\0';
5314
5315 if (m68k_ip_op (s, &rop) != 0)
5316 {
5317 if (rop.error == NULL)
5318 as_bad (_("bad register list"));
5319 else
5320 as_bad (_("bad register list: %s"), rop.error);
5321 *input_line_pointer = c;
5322 ignore_rest_of_line ();
5323 return;
5324 }
5325
5326 *input_line_pointer = c;
5327
5328 if (rop.mode == REGLST)
5329 mask = rop.mask;
5330 else if (rop.mode == DREG)
5331 mask = 1 << (rop.reg - DATA0);
5332 else if (rop.mode == AREG)
5333 mask = 1 << (rop.reg - ADDR0 + 8);
5334 else if (rop.mode == FPREG)
5335 mask = 1 << (rop.reg - FP0 + 16);
5336 else if (rop.mode == CONTROL
5337 && rop.reg == FPI)
5338 mask = 1 << 24;
5339 else if (rop.mode == CONTROL
5340 && rop.reg == FPS)
5341 mask = 1 << 25;
5342 else if (rop.mode == CONTROL
5343 && rop.reg == FPC)
5344 mask = 1 << 26;
5345 else
5346 {
5347 as_bad (_("bad register list"));
5348 ignore_rest_of_line ();
5349 return;
5350 }
5351
5352 S_SET_SEGMENT (line_label, reg_section);
5353 S_SET_VALUE (line_label, ~mask);
5354 line_label->sy_frag = &zero_address_frag;
5355
5356 if (flag_mri)
5357 mri_comment_end (stop, stopc);
5358
5359 demand_empty_rest_of_line ();
5360 }
5361
5362 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5363
5364 struct save_opts
5365 {
5366 struct save_opts *next;
5367 int abspcadd;
5368 int symbols_case_sensitive;
5369 int keep_locals;
5370 int short_refs;
5371 int architecture;
5372 int quick;
5373 int rel32;
5374 int listing;
5375 int no_warnings;
5376 /* FIXME: We don't save OPT S. */
5377 };
5378
5379 /* This variable holds the stack of saved options. */
5380
5381 static struct save_opts *save_stack;
5382
5383 /* The MRI SAVE pseudo-op. */
5384
5385 static void
5386 s_save (ignore)
5387 int ignore;
5388 {
5389 struct save_opts *s;
5390
5391 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5392 s->abspcadd = m68k_abspcadd;
5393 s->symbols_case_sensitive = symbols_case_sensitive;
5394 s->keep_locals = flag_keep_locals;
5395 s->short_refs = flag_short_refs;
5396 s->architecture = current_architecture;
5397 s->quick = m68k_quick;
5398 s->rel32 = m68k_rel32;
5399 s->listing = listing;
5400 s->no_warnings = flag_no_warnings;
5401
5402 s->next = save_stack;
5403 save_stack = s;
5404
5405 demand_empty_rest_of_line ();
5406 }
5407
5408 /* The MRI RESTORE pseudo-op. */
5409
5410 static void
5411 s_restore (ignore)
5412 int ignore;
5413 {
5414 struct save_opts *s;
5415
5416 if (save_stack == NULL)
5417 {
5418 as_bad (_("restore without save"));
5419 ignore_rest_of_line ();
5420 return;
5421 }
5422
5423 s = save_stack;
5424 save_stack = s->next;
5425
5426 m68k_abspcadd = s->abspcadd;
5427 symbols_case_sensitive = s->symbols_case_sensitive;
5428 flag_keep_locals = s->keep_locals;
5429 flag_short_refs = s->short_refs;
5430 current_architecture = s->architecture;
5431 m68k_quick = s->quick;
5432 m68k_rel32 = s->rel32;
5433 listing = s->listing;
5434 flag_no_warnings = s->no_warnings;
5435
5436 free (s);
5437
5438 demand_empty_rest_of_line ();
5439 }
5440
5441 /* Types of MRI structured control directives. */
5442
5443 enum mri_control_type
5444 {
5445 mri_for,
5446 mri_if,
5447 mri_repeat,
5448 mri_while
5449 };
5450
5451 /* This structure is used to stack the MRI structured control
5452 directives. */
5453
5454 struct mri_control_info
5455 {
5456 /* The directive within which this one is enclosed. */
5457 struct mri_control_info *outer;
5458
5459 /* The type of directive. */
5460 enum mri_control_type type;
5461
5462 /* Whether an ELSE has been in an IF. */
5463 int else_seen;
5464
5465 /* The add or sub statement at the end of a FOR. */
5466 char *incr;
5467
5468 /* The label of the top of a FOR or REPEAT loop. */
5469 char *top;
5470
5471 /* The label to jump to for the next iteration, or the else
5472 expression of a conditional. */
5473 char *next;
5474
5475 /* The label to jump to to break out of the loop, or the label past
5476 the end of a conditional. */
5477 char *bottom;
5478 };
5479
5480 /* The stack of MRI structured control directives. */
5481
5482 static struct mri_control_info *mri_control_stack;
5483
5484 /* The current MRI structured control directive index number, used to
5485 generate label names. */
5486
5487 static int mri_control_index;
5488
5489 /* Some function prototypes. */
5490
5491 static void mri_assemble PARAMS ((char *));
5492 static char *mri_control_label PARAMS ((void));
5493 static struct mri_control_info *push_mri_control
5494 PARAMS ((enum mri_control_type));
5495 static void pop_mri_control PARAMS ((void));
5496 static int parse_mri_condition PARAMS ((int *));
5497 static int parse_mri_control_operand
5498 PARAMS ((int *, char **, char **, char **, char **));
5499 static int swap_mri_condition PARAMS ((int));
5500 static int reverse_mri_condition PARAMS ((int));
5501 static void build_mri_control_operand
5502 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5503 const char *, int));
5504 static void parse_mri_control_expression
5505 PARAMS ((char *, int, const char *, const char *, int));
5506
5507 /* Assemble an instruction for an MRI structured control directive. */
5508
5509 static void
5510 mri_assemble (str)
5511 char *str;
5512 {
5513 char *s;
5514
5515 /* md_assemble expects the opcode to be in lower case. */
5516 for (s = str; *s != ' ' && *s != '\0'; s++)
5517 {
5518 if (isupper ((unsigned char) *s))
5519 *s = tolower ((unsigned char) *s);
5520 }
5521
5522 md_assemble (str);
5523 }
5524
5525 /* Generate a new MRI label structured control directive label name. */
5526
5527 static char *
5528 mri_control_label ()
5529 {
5530 char *n;
5531
5532 n = (char *) xmalloc (20);
5533 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5534 ++mri_control_index;
5535 return n;
5536 }
5537
5538 /* Create a new MRI structured control directive. */
5539
5540 static struct mri_control_info *
5541 push_mri_control (type)
5542 enum mri_control_type type;
5543 {
5544 struct mri_control_info *n;
5545
5546 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5547
5548 n->type = type;
5549 n->else_seen = 0;
5550 if (type == mri_if || type == mri_while)
5551 n->top = NULL;
5552 else
5553 n->top = mri_control_label ();
5554 n->next = mri_control_label ();
5555 n->bottom = mri_control_label ();
5556
5557 n->outer = mri_control_stack;
5558 mri_control_stack = n;
5559
5560 return n;
5561 }
5562
5563 /* Pop off the stack of MRI structured control directives. */
5564
5565 static void
5566 pop_mri_control ()
5567 {
5568 struct mri_control_info *n;
5569
5570 n = mri_control_stack;
5571 mri_control_stack = n->outer;
5572 if (n->top != NULL)
5573 free (n->top);
5574 free (n->next);
5575 free (n->bottom);
5576 free (n);
5577 }
5578
5579 /* Recognize a condition code in an MRI structured control expression. */
5580
5581 static int
5582 parse_mri_condition (pcc)
5583 int *pcc;
5584 {
5585 char c1, c2;
5586
5587 know (*input_line_pointer == '<');
5588
5589 ++input_line_pointer;
5590 c1 = *input_line_pointer++;
5591 c2 = *input_line_pointer++;
5592
5593 if (*input_line_pointer != '>')
5594 {
5595 as_bad (_("syntax error in structured control directive"));
5596 return 0;
5597 }
5598
5599 ++input_line_pointer;
5600 SKIP_WHITESPACE ();
5601
5602 if (isupper (c1))
5603 c1 = tolower (c1);
5604 if (isupper (c2))
5605 c2 = tolower (c2);
5606
5607 *pcc = (c1 << 8) | c2;
5608
5609 return 1;
5610 }
5611
5612 /* Parse a single operand in an MRI structured control expression. */
5613
5614 static int
5615 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5616 int *pcc;
5617 char **leftstart;
5618 char **leftstop;
5619 char **rightstart;
5620 char **rightstop;
5621 {
5622 char *s;
5623
5624 SKIP_WHITESPACE ();
5625
5626 *pcc = -1;
5627 *leftstart = NULL;
5628 *leftstop = NULL;
5629 *rightstart = NULL;
5630 *rightstop = NULL;
5631
5632 if (*input_line_pointer == '<')
5633 {
5634 /* It's just a condition code. */
5635 return parse_mri_condition (pcc);
5636 }
5637
5638 /* Look ahead for the condition code. */
5639 for (s = input_line_pointer; *s != '\0'; ++s)
5640 {
5641 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5642 break;
5643 }
5644 if (*s == '\0')
5645 {
5646 as_bad (_("missing condition code in structured control directive"));
5647 return 0;
5648 }
5649
5650 *leftstart = input_line_pointer;
5651 *leftstop = s;
5652 if (*leftstop > *leftstart
5653 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5654 --*leftstop;
5655
5656 input_line_pointer = s;
5657 if (! parse_mri_condition (pcc))
5658 return 0;
5659
5660 /* Look ahead for AND or OR or end of line. */
5661 for (s = input_line_pointer; *s != '\0'; ++s)
5662 {
5663 if ((strncasecmp (s, "AND", 3) == 0
5664 && (s[3] == '.' || ! is_part_of_name (s[3])))
5665 || (strncasecmp (s, "OR", 2) == 0
5666 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5667 break;
5668 }
5669
5670 *rightstart = input_line_pointer;
5671 *rightstop = s;
5672 if (*rightstop > *rightstart
5673 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5674 --*rightstop;
5675
5676 input_line_pointer = s;
5677
5678 return 1;
5679 }
5680
5681 #define MCC(b1, b2) (((b1) << 8) | (b2))
5682
5683 /* Swap the sense of a condition. This changes the condition so that
5684 it generates the same result when the operands are swapped. */
5685
5686 static int
5687 swap_mri_condition (cc)
5688 int cc;
5689 {
5690 switch (cc)
5691 {
5692 case MCC ('h', 'i'): return MCC ('c', 's');
5693 case MCC ('l', 's'): return MCC ('c', 'c');
5694 case MCC ('c', 'c'): return MCC ('l', 's');
5695 case MCC ('c', 's'): return MCC ('h', 'i');
5696 case MCC ('p', 'l'): return MCC ('m', 'i');
5697 case MCC ('m', 'i'): return MCC ('p', 'l');
5698 case MCC ('g', 'e'): return MCC ('l', 'e');
5699 case MCC ('l', 't'): return MCC ('g', 't');
5700 case MCC ('g', 't'): return MCC ('l', 't');
5701 case MCC ('l', 'e'): return MCC ('g', 'e');
5702 }
5703 return cc;
5704 }
5705
5706 /* Reverse the sense of a condition. */
5707
5708 static int
5709 reverse_mri_condition (cc)
5710 int cc;
5711 {
5712 switch (cc)
5713 {
5714 case MCC ('h', 'i'): return MCC ('l', 's');
5715 case MCC ('l', 's'): return MCC ('h', 'i');
5716 case MCC ('c', 'c'): return MCC ('c', 's');
5717 case MCC ('c', 's'): return MCC ('c', 'c');
5718 case MCC ('n', 'e'): return MCC ('e', 'q');
5719 case MCC ('e', 'q'): return MCC ('n', 'e');
5720 case MCC ('v', 'c'): return MCC ('v', 's');
5721 case MCC ('v', 's'): return MCC ('v', 'c');
5722 case MCC ('p', 'l'): return MCC ('m', 'i');
5723 case MCC ('m', 'i'): return MCC ('p', 'l');
5724 case MCC ('g', 'e'): return MCC ('l', 't');
5725 case MCC ('l', 't'): return MCC ('g', 'e');
5726 case MCC ('g', 't'): return MCC ('l', 'e');
5727 case MCC ('l', 'e'): return MCC ('g', 't');
5728 }
5729 return cc;
5730 }
5731
5732 /* Build an MRI structured control expression. This generates test
5733 and branch instructions. It goes to TRUELAB if the condition is
5734 true, and to FALSELAB if the condition is false. Exactly one of
5735 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5736 is the size qualifier for the expression. EXTENT is the size to
5737 use for the branch. */
5738
5739 static void
5740 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5741 rightstop, truelab, falselab, extent)
5742 int qual;
5743 int cc;
5744 char *leftstart;
5745 char *leftstop;
5746 char *rightstart;
5747 char *rightstop;
5748 const char *truelab;
5749 const char *falselab;
5750 int extent;
5751 {
5752 char *buf;
5753 char *s;
5754
5755 if (leftstart != NULL)
5756 {
5757 struct m68k_op leftop, rightop;
5758 char c;
5759
5760 /* Swap the compare operands, if necessary, to produce a legal
5761 m68k compare instruction. Comparing a register operand with
5762 a non-register operand requires the register to be on the
5763 right (cmp, cmpa). Comparing an immediate value with
5764 anything requires the immediate value to be on the left
5765 (cmpi). */
5766
5767 c = *leftstop;
5768 *leftstop = '\0';
5769 (void) m68k_ip_op (leftstart, &leftop);
5770 *leftstop = c;
5771
5772 c = *rightstop;
5773 *rightstop = '\0';
5774 (void) m68k_ip_op (rightstart, &rightop);
5775 *rightstop = c;
5776
5777 if (rightop.mode == IMMED
5778 || ((leftop.mode == DREG || leftop.mode == AREG)
5779 && (rightop.mode != DREG && rightop.mode != AREG)))
5780 {
5781 char *temp;
5782
5783 cc = swap_mri_condition (cc);
5784 temp = leftstart;
5785 leftstart = rightstart;
5786 rightstart = temp;
5787 temp = leftstop;
5788 leftstop = rightstop;
5789 rightstop = temp;
5790 }
5791 }
5792
5793 if (truelab == NULL)
5794 {
5795 cc = reverse_mri_condition (cc);
5796 truelab = falselab;
5797 }
5798
5799 if (leftstart != NULL)
5800 {
5801 buf = (char *) xmalloc (20
5802 + (leftstop - leftstart)
5803 + (rightstop - rightstart));
5804 s = buf;
5805 *s++ = 'c';
5806 *s++ = 'm';
5807 *s++ = 'p';
5808 if (qual != '\0')
5809 *s++ = qual;
5810 *s++ = ' ';
5811 memcpy (s, leftstart, leftstop - leftstart);
5812 s += leftstop - leftstart;
5813 *s++ = ',';
5814 memcpy (s, rightstart, rightstop - rightstart);
5815 s += rightstop - rightstart;
5816 *s = '\0';
5817 mri_assemble (buf);
5818 free (buf);
5819 }
5820
5821 buf = (char *) xmalloc (20 + strlen (truelab));
5822 s = buf;
5823 *s++ = 'b';
5824 *s++ = cc >> 8;
5825 *s++ = cc & 0xff;
5826 if (extent != '\0')
5827 *s++ = extent;
5828 *s++ = ' ';
5829 strcpy (s, truelab);
5830 mri_assemble (buf);
5831 free (buf);
5832 }
5833
5834 /* Parse an MRI structured control expression. This generates test
5835 and branch instructions. STOP is where the expression ends. It
5836 goes to TRUELAB if the condition is true, and to FALSELAB if the
5837 condition is false. Exactly one of TRUELAB and FALSELAB will be
5838 NULL, meaning to fall through. QUAL is the size qualifier for the
5839 expression. EXTENT is the size to use for the branch. */
5840
5841 static void
5842 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5843 char *stop;
5844 int qual;
5845 const char *truelab;
5846 const char *falselab;
5847 int extent;
5848 {
5849 int c;
5850 int cc;
5851 char *leftstart;
5852 char *leftstop;
5853 char *rightstart;
5854 char *rightstop;
5855
5856 c = *stop;
5857 *stop = '\0';
5858
5859 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5860 &rightstart, &rightstop))
5861 {
5862 *stop = c;
5863 return;
5864 }
5865
5866 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5867 {
5868 const char *flab;
5869
5870 if (falselab != NULL)
5871 flab = falselab;
5872 else
5873 flab = mri_control_label ();
5874
5875 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5876 rightstop, (const char *) NULL, flab, extent);
5877
5878 input_line_pointer += 3;
5879 if (*input_line_pointer != '.'
5880 || input_line_pointer[1] == '\0')
5881 qual = '\0';
5882 else
5883 {
5884 qual = input_line_pointer[1];
5885 input_line_pointer += 2;
5886 }
5887
5888 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5889 &rightstart, &rightstop))
5890 {
5891 *stop = c;
5892 return;
5893 }
5894
5895 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5896 rightstop, truelab, falselab, extent);
5897
5898 if (falselab == NULL)
5899 colon (flab);
5900 }
5901 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5902 {
5903 const char *tlab;
5904
5905 if (truelab != NULL)
5906 tlab = truelab;
5907 else
5908 tlab = mri_control_label ();
5909
5910 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5911 rightstop, tlab, (const char *) NULL, extent);
5912
5913 input_line_pointer += 2;
5914 if (*input_line_pointer != '.'
5915 || input_line_pointer[1] == '\0')
5916 qual = '\0';
5917 else
5918 {
5919 qual = input_line_pointer[1];
5920 input_line_pointer += 2;
5921 }
5922
5923 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5924 &rightstart, &rightstop))
5925 {
5926 *stop = c;
5927 return;
5928 }
5929
5930 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5931 rightstop, truelab, falselab, extent);
5932
5933 if (truelab == NULL)
5934 colon (tlab);
5935 }
5936 else
5937 {
5938 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5939 rightstop, truelab, falselab, extent);
5940 }
5941
5942 *stop = c;
5943 if (input_line_pointer != stop)
5944 as_bad (_("syntax error in structured control directive"));
5945 }
5946
5947 /* Handle the MRI IF pseudo-op. This may be a structured control
5948 directive, or it may be a regular assembler conditional, depending
5949 on its operands. */
5950
5951 static void
5952 s_mri_if (qual)
5953 int qual;
5954 {
5955 char *s;
5956 int c;
5957 struct mri_control_info *n;
5958
5959 /* A structured control directive must end with THEN with an
5960 optional qualifier. */
5961 s = input_line_pointer;
5962 while (! is_end_of_line[(unsigned char) *s]
5963 && (! flag_mri || *s != '*'))
5964 ++s;
5965 --s;
5966 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5967 --s;
5968
5969 if (s - input_line_pointer > 1
5970 && s[-1] == '.')
5971 s -= 2;
5972
5973 if (s - input_line_pointer < 3
5974 || strncasecmp (s - 3, "THEN", 4) != 0)
5975 {
5976 if (qual != '\0')
5977 {
5978 as_bad (_("missing then"));
5979 ignore_rest_of_line ();
5980 return;
5981 }
5982
5983 /* It's a conditional. */
5984 s_if (O_ne);
5985 return;
5986 }
5987
5988 /* Since this might be a conditional if, this pseudo-op will be
5989 called even if we are supported to be ignoring input. Double
5990 check now. Clobber *input_line_pointer so that ignore_input
5991 thinks that this is not a special pseudo-op. */
5992 c = *input_line_pointer;
5993 *input_line_pointer = 0;
5994 if (ignore_input ())
5995 {
5996 *input_line_pointer = c;
5997 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5998 ++input_line_pointer;
5999 demand_empty_rest_of_line ();
6000 return;
6001 }
6002 *input_line_pointer = c;
6003
6004 n = push_mri_control (mri_if);
6005
6006 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6007 n->next, s[1] == '.' ? s[2] : '\0');
6008
6009 if (s[1] == '.')
6010 input_line_pointer = s + 3;
6011 else
6012 input_line_pointer = s + 1;
6013
6014 if (flag_mri)
6015 {
6016 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6017 ++input_line_pointer;
6018 }
6019
6020 demand_empty_rest_of_line ();
6021 }
6022
6023 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6024 structured IF, associate the ELSE with the IF. Otherwise, assume
6025 it is a conditional else. */
6026
6027 static void
6028 s_mri_else (qual)
6029 int qual;
6030 {
6031 int c;
6032 char *buf;
6033 char q[2];
6034
6035 if (qual == '\0'
6036 && (mri_control_stack == NULL
6037 || mri_control_stack->type != mri_if
6038 || mri_control_stack->else_seen))
6039 {
6040 s_else (0);
6041 return;
6042 }
6043
6044 c = *input_line_pointer;
6045 *input_line_pointer = 0;
6046 if (ignore_input ())
6047 {
6048 *input_line_pointer = c;
6049 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6050 ++input_line_pointer;
6051 demand_empty_rest_of_line ();
6052 return;
6053 }
6054 *input_line_pointer = c;
6055
6056 if (mri_control_stack == NULL
6057 || mri_control_stack->type != mri_if
6058 || mri_control_stack->else_seen)
6059 {
6060 as_bad (_("else without matching if"));
6061 ignore_rest_of_line ();
6062 return;
6063 }
6064
6065 mri_control_stack->else_seen = 1;
6066
6067 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6068 q[0] = qual;
6069 q[1] = '\0';
6070 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6071 mri_assemble (buf);
6072 free (buf);
6073
6074 colon (mri_control_stack->next);
6075
6076 if (flag_mri)
6077 {
6078 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6079 ++input_line_pointer;
6080 }
6081
6082 demand_empty_rest_of_line ();
6083 }
6084
6085 /* Handle the MRI ENDI pseudo-op. */
6086
6087 static void
6088 s_mri_endi (ignore)
6089 int ignore;
6090 {
6091 if (mri_control_stack == NULL
6092 || mri_control_stack->type != mri_if)
6093 {
6094 as_bad (_("endi without matching if"));
6095 ignore_rest_of_line ();
6096 return;
6097 }
6098
6099 /* ignore_input will not return true for ENDI, so we don't need to
6100 worry about checking it again here. */
6101
6102 if (! mri_control_stack->else_seen)
6103 colon (mri_control_stack->next);
6104 colon (mri_control_stack->bottom);
6105
6106 pop_mri_control ();
6107
6108 if (flag_mri)
6109 {
6110 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6111 ++input_line_pointer;
6112 }
6113
6114 demand_empty_rest_of_line ();
6115 }
6116
6117 /* Handle the MRI BREAK pseudo-op. */
6118
6119 static void
6120 s_mri_break (extent)
6121 int extent;
6122 {
6123 struct mri_control_info *n;
6124 char *buf;
6125 char ex[2];
6126
6127 n = mri_control_stack;
6128 while (n != NULL
6129 && n->type != mri_for
6130 && n->type != mri_repeat
6131 && n->type != mri_while)
6132 n = n->outer;
6133 if (n == NULL)
6134 {
6135 as_bad (_("break outside of structured loop"));
6136 ignore_rest_of_line ();
6137 return;
6138 }
6139
6140 buf = (char *) xmalloc (20 + strlen (n->bottom));
6141 ex[0] = extent;
6142 ex[1] = '\0';
6143 sprintf (buf, "bra%s %s", ex, n->bottom);
6144 mri_assemble (buf);
6145 free (buf);
6146
6147 if (flag_mri)
6148 {
6149 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6150 ++input_line_pointer;
6151 }
6152
6153 demand_empty_rest_of_line ();
6154 }
6155
6156 /* Handle the MRI NEXT pseudo-op. */
6157
6158 static void
6159 s_mri_next (extent)
6160 int extent;
6161 {
6162 struct mri_control_info *n;
6163 char *buf;
6164 char ex[2];
6165
6166 n = mri_control_stack;
6167 while (n != NULL
6168 && n->type != mri_for
6169 && n->type != mri_repeat
6170 && n->type != mri_while)
6171 n = n->outer;
6172 if (n == NULL)
6173 {
6174 as_bad (_("next outside of structured loop"));
6175 ignore_rest_of_line ();
6176 return;
6177 }
6178
6179 buf = (char *) xmalloc (20 + strlen (n->next));
6180 ex[0] = extent;
6181 ex[1] = '\0';
6182 sprintf (buf, "bra%s %s", ex, n->next);
6183 mri_assemble (buf);
6184 free (buf);
6185
6186 if (flag_mri)
6187 {
6188 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6189 ++input_line_pointer;
6190 }
6191
6192 demand_empty_rest_of_line ();
6193 }
6194
6195 /* Handle the MRI FOR pseudo-op. */
6196
6197 static void
6198 s_mri_for (qual)
6199 int qual;
6200 {
6201 const char *varstart, *varstop;
6202 const char *initstart, *initstop;
6203 const char *endstart, *endstop;
6204 const char *bystart, *bystop;
6205 int up;
6206 int by;
6207 int extent;
6208 struct mri_control_info *n;
6209 char *buf;
6210 char *s;
6211 char ex[2];
6212
6213 /* The syntax is
6214 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6215 */
6216
6217 SKIP_WHITESPACE ();
6218 varstart = input_line_pointer;
6219
6220 /* Look for the '='. */
6221 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6222 && *input_line_pointer != '=')
6223 ++input_line_pointer;
6224 if (*input_line_pointer != '=')
6225 {
6226 as_bad (_("missing ="));
6227 ignore_rest_of_line ();
6228 return;
6229 }
6230
6231 varstop = input_line_pointer;
6232 if (varstop > varstart
6233 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6234 --varstop;
6235
6236 ++input_line_pointer;
6237
6238 initstart = input_line_pointer;
6239
6240 /* Look for TO or DOWNTO. */
6241 up = 1;
6242 initstop = NULL;
6243 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6244 {
6245 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6246 && ! is_part_of_name (input_line_pointer[2]))
6247 {
6248 initstop = input_line_pointer;
6249 input_line_pointer += 2;
6250 break;
6251 }
6252 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6253 && ! is_part_of_name (input_line_pointer[6]))
6254 {
6255 initstop = input_line_pointer;
6256 up = 0;
6257 input_line_pointer += 6;
6258 break;
6259 }
6260 ++input_line_pointer;
6261 }
6262 if (initstop == NULL)
6263 {
6264 as_bad (_("missing to or downto"));
6265 ignore_rest_of_line ();
6266 return;
6267 }
6268 if (initstop > initstart
6269 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6270 --initstop;
6271
6272 SKIP_WHITESPACE ();
6273 endstart = input_line_pointer;
6274
6275 /* Look for BY or DO. */
6276 by = 0;
6277 endstop = NULL;
6278 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6279 {
6280 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6281 && ! is_part_of_name (input_line_pointer[2]))
6282 {
6283 endstop = input_line_pointer;
6284 by = 1;
6285 input_line_pointer += 2;
6286 break;
6287 }
6288 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6289 && (input_line_pointer[2] == '.'
6290 || ! is_part_of_name (input_line_pointer[2])))
6291 {
6292 endstop = input_line_pointer;
6293 input_line_pointer += 2;
6294 break;
6295 }
6296 ++input_line_pointer;
6297 }
6298 if (endstop == NULL)
6299 {
6300 as_bad (_("missing do"));
6301 ignore_rest_of_line ();
6302 return;
6303 }
6304 if (endstop > endstart
6305 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6306 --endstop;
6307
6308 if (! by)
6309 {
6310 bystart = "#1";
6311 bystop = bystart + 2;
6312 }
6313 else
6314 {
6315 SKIP_WHITESPACE ();
6316 bystart = input_line_pointer;
6317
6318 /* Look for DO. */
6319 bystop = NULL;
6320 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6321 {
6322 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6323 && (input_line_pointer[2] == '.'
6324 || ! is_part_of_name (input_line_pointer[2])))
6325 {
6326 bystop = input_line_pointer;
6327 input_line_pointer += 2;
6328 break;
6329 }
6330 ++input_line_pointer;
6331 }
6332 if (bystop == NULL)
6333 {
6334 as_bad (_("missing do"));
6335 ignore_rest_of_line ();
6336 return;
6337 }
6338 if (bystop > bystart
6339 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6340 --bystop;
6341 }
6342
6343 if (*input_line_pointer != '.')
6344 extent = '\0';
6345 else
6346 {
6347 extent = input_line_pointer[1];
6348 input_line_pointer += 2;
6349 }
6350
6351 /* We have fully parsed the FOR operands. Now build the loop. */
6352
6353 n = push_mri_control (mri_for);
6354
6355 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6356
6357 /* move init,var */
6358 s = buf;
6359 *s++ = 'm';
6360 *s++ = 'o';
6361 *s++ = 'v';
6362 *s++ = 'e';
6363 if (qual != '\0')
6364 *s++ = qual;
6365 *s++ = ' ';
6366 memcpy (s, initstart, initstop - initstart);
6367 s += initstop - initstart;
6368 *s++ = ',';
6369 memcpy (s, varstart, varstop - varstart);
6370 s += varstop - varstart;
6371 *s = '\0';
6372 mri_assemble (buf);
6373
6374 colon (n->top);
6375
6376 /* cmp end,var */
6377 s = buf;
6378 *s++ = 'c';
6379 *s++ = 'm';
6380 *s++ = 'p';
6381 if (qual != '\0')
6382 *s++ = qual;
6383 *s++ = ' ';
6384 memcpy (s, endstart, endstop - endstart);
6385 s += endstop - endstart;
6386 *s++ = ',';
6387 memcpy (s, varstart, varstop - varstart);
6388 s += varstop - varstart;
6389 *s = '\0';
6390 mri_assemble (buf);
6391
6392 /* bcc bottom */
6393 ex[0] = extent;
6394 ex[1] = '\0';
6395 if (up)
6396 sprintf (buf, "blt%s %s", ex, n->bottom);
6397 else
6398 sprintf (buf, "bgt%s %s", ex, n->bottom);
6399 mri_assemble (buf);
6400
6401 /* Put together the add or sub instruction used by ENDF. */
6402 s = buf;
6403 if (up)
6404 strcpy (s, "add");
6405 else
6406 strcpy (s, "sub");
6407 s += 3;
6408 if (qual != '\0')
6409 *s++ = qual;
6410 *s++ = ' ';
6411 memcpy (s, bystart, bystop - bystart);
6412 s += bystop - bystart;
6413 *s++ = ',';
6414 memcpy (s, varstart, varstop - varstart);
6415 s += varstop - varstart;
6416 *s = '\0';
6417 n->incr = buf;
6418
6419 if (flag_mri)
6420 {
6421 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6422 ++input_line_pointer;
6423 }
6424
6425 demand_empty_rest_of_line ();
6426 }
6427
6428 /* Handle the MRI ENDF pseudo-op. */
6429
6430 static void
6431 s_mri_endf (ignore)
6432 int ignore;
6433 {
6434 if (mri_control_stack == NULL
6435 || mri_control_stack->type != mri_for)
6436 {
6437 as_bad (_("endf without for"));
6438 ignore_rest_of_line ();
6439 return;
6440 }
6441
6442 colon (mri_control_stack->next);
6443
6444 mri_assemble (mri_control_stack->incr);
6445
6446 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6447 mri_assemble (mri_control_stack->incr);
6448
6449 free (mri_control_stack->incr);
6450
6451 colon (mri_control_stack->bottom);
6452
6453 pop_mri_control ();
6454
6455 if (flag_mri)
6456 {
6457 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6458 ++input_line_pointer;
6459 }
6460
6461 demand_empty_rest_of_line ();
6462 }
6463
6464 /* Handle the MRI REPEAT pseudo-op. */
6465
6466 static void
6467 s_mri_repeat (ignore)
6468 int ignore;
6469 {
6470 struct mri_control_info *n;
6471
6472 n = push_mri_control (mri_repeat);
6473 colon (n->top);
6474 if (flag_mri)
6475 {
6476 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6477 ++input_line_pointer;
6478 }
6479 demand_empty_rest_of_line ();
6480 }
6481
6482 /* Handle the MRI UNTIL pseudo-op. */
6483
6484 static void
6485 s_mri_until (qual)
6486 int qual;
6487 {
6488 char *s;
6489
6490 if (mri_control_stack == NULL
6491 || mri_control_stack->type != mri_repeat)
6492 {
6493 as_bad (_("until without repeat"));
6494 ignore_rest_of_line ();
6495 return;
6496 }
6497
6498 colon (mri_control_stack->next);
6499
6500 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6501 ;
6502
6503 parse_mri_control_expression (s, qual, (const char *) NULL,
6504 mri_control_stack->top, '\0');
6505
6506 colon (mri_control_stack->bottom);
6507
6508 input_line_pointer = s;
6509
6510 pop_mri_control ();
6511
6512 if (flag_mri)
6513 {
6514 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6515 ++input_line_pointer;
6516 }
6517
6518 demand_empty_rest_of_line ();
6519 }
6520
6521 /* Handle the MRI WHILE pseudo-op. */
6522
6523 static void
6524 s_mri_while (qual)
6525 int qual;
6526 {
6527 char *s;
6528
6529 struct mri_control_info *n;
6530
6531 s = input_line_pointer;
6532 while (! is_end_of_line[(unsigned char) *s]
6533 && (! flag_mri || *s != '*'))
6534 s++;
6535 --s;
6536 while (*s == ' ' || *s == '\t')
6537 --s;
6538 if (s - input_line_pointer > 1
6539 && s[-1] == '.')
6540 s -= 2;
6541 if (s - input_line_pointer < 2
6542 || strncasecmp (s - 1, "DO", 2) != 0)
6543 {
6544 as_bad (_("missing do"));
6545 ignore_rest_of_line ();
6546 return;
6547 }
6548
6549 n = push_mri_control (mri_while);
6550
6551 colon (n->next);
6552
6553 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6554 s[1] == '.' ? s[2] : '\0');
6555
6556 input_line_pointer = s + 1;
6557 if (*input_line_pointer == '.')
6558 input_line_pointer += 2;
6559
6560 if (flag_mri)
6561 {
6562 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6563 ++input_line_pointer;
6564 }
6565
6566 demand_empty_rest_of_line ();
6567 }
6568
6569 /* Handle the MRI ENDW pseudo-op. */
6570
6571 static void
6572 s_mri_endw (ignore)
6573 int ignore;
6574 {
6575 char *buf;
6576
6577 if (mri_control_stack == NULL
6578 || mri_control_stack->type != mri_while)
6579 {
6580 as_bad (_("endw without while"));
6581 ignore_rest_of_line ();
6582 return;
6583 }
6584
6585 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6586 sprintf (buf, "bra %s", mri_control_stack->next);
6587 mri_assemble (buf);
6588 free (buf);
6589
6590 colon (mri_control_stack->bottom);
6591
6592 pop_mri_control ();
6593
6594 if (flag_mri)
6595 {
6596 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6597 ++input_line_pointer;
6598 }
6599
6600 demand_empty_rest_of_line ();
6601 }
6602 \f
6603 /*
6604 * md_parse_option
6605 * Invocation line includes a switch not recognized by the base assembler.
6606 * See if it's a processor-specific option. These are:
6607 *
6608 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6609 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6610 * Select the architecture. Instructions or features not
6611 * supported by the selected architecture cause fatal
6612 * errors. More than one may be specified. The default is
6613 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6614 * for -m68000, and -m68882 is a synonym for -m68881.
6615 * -[A]m[c]no-68851, -[A]m[c]no-68881
6616 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6617 * so don't use or document it, but that's the way the parsing
6618 * works).
6619 *
6620 * -pic Indicates PIC.
6621 * -k Indicates PIC. (Sun 3 only.)
6622 *
6623 * --bitwise-or
6624 * Permit `|' to be used in expressions.
6625 *
6626 */
6627
6628 #ifdef OBJ_ELF
6629 CONST char *md_shortopts = "lSA:m:kQ:V";
6630 #else
6631 CONST char *md_shortopts = "lSA:m:k";
6632 #endif
6633
6634 struct option md_longopts[] = {
6635 #define OPTION_PIC (OPTION_MD_BASE)
6636 {"pic", no_argument, NULL, OPTION_PIC},
6637 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6638 {"register-prefix-optional", no_argument, NULL,
6639 OPTION_REGISTER_PREFIX_OPTIONAL},
6640 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6641 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6642 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6643 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6644 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6645 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6646 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6647 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6648 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6649 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6650 {NULL, no_argument, NULL, 0}
6651 };
6652 size_t md_longopts_size = sizeof(md_longopts);
6653
6654 int
6655 md_parse_option (c, arg)
6656 int c;
6657 char *arg;
6658 {
6659 switch (c)
6660 {
6661 case 'l': /* -l means keep external to 2 bit offset
6662 rather than 16 bit one */
6663 flag_short_refs = 1;
6664 break;
6665
6666 case 'S': /* -S means that jbsr's always turn into
6667 jsr's. */
6668 flag_long_jumps = 1;
6669 break;
6670
6671 case 'A':
6672 if (*arg == 'm')
6673 arg++;
6674 /* intentional fall-through */
6675 case 'm':
6676
6677 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6678 {
6679 int i;
6680 unsigned long arch;
6681 const char *oarg = arg;
6682
6683 arg += 3;
6684 if (*arg == 'm')
6685 {
6686 arg++;
6687 if (arg[0] == 'c' && arg[1] == '6')
6688 arg++;
6689 }
6690 for (i = 0; i < n_archs; i++)
6691 if (!strcmp (arg, archs[i].name))
6692 break;
6693 if (i == n_archs)
6694 {
6695 unknown:
6696 as_bad (_("unrecognized option `%s'"), oarg);
6697 return 0;
6698 }
6699 arch = archs[i].arch;
6700 if (arch == m68881)
6701 no_68881 = 1;
6702 else if (arch == m68851)
6703 no_68851 = 1;
6704 else
6705 goto unknown;
6706 }
6707 else
6708 {
6709 int i;
6710
6711 if (arg[0] == 'c' && arg[1] == '6')
6712 arg++;
6713
6714 for (i = 0; i < n_archs; i++)
6715 if (!strcmp (arg, archs[i].name))
6716 {
6717 unsigned long arch = archs[i].arch;
6718 if (cpu_of_arch (arch))
6719 /* It's a cpu spec. */
6720 {
6721 current_architecture &= ~m68000up;
6722 current_architecture |= arch;
6723 }
6724 else if (arch == m68881)
6725 {
6726 current_architecture |= m68881;
6727 no_68881 = 0;
6728 }
6729 else if (arch == m68851)
6730 {
6731 current_architecture |= m68851;
6732 no_68851 = 0;
6733 }
6734 else
6735 /* ??? */
6736 abort ();
6737 break;
6738 }
6739 if (i == n_archs)
6740 {
6741 as_bad (_("unrecognized architecture specification `%s'"), arg);
6742 return 0;
6743 }
6744 }
6745 break;
6746
6747 case OPTION_PIC:
6748 case 'k':
6749 flag_want_pic = 1;
6750 break; /* -pic, Position Independent Code */
6751
6752 case OPTION_REGISTER_PREFIX_OPTIONAL:
6753 flag_reg_prefix_optional = 1;
6754 reg_prefix_optional_seen = 1;
6755 break;
6756
6757 /* -V: SVR4 argument to print version ID. */
6758 case 'V':
6759 print_version_id ();
6760 break;
6761
6762 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6763 should be emitted or not. FIXME: Not implemented. */
6764 case 'Q':
6765 break;
6766
6767 case OPTION_BITWISE_OR:
6768 {
6769 char *n, *t;
6770 const char *s;
6771
6772 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6773 t = n;
6774 for (s = m68k_comment_chars; *s != '\0'; s++)
6775 if (*s != '|')
6776 *t++ = *s;
6777 *t = '\0';
6778 m68k_comment_chars = n;
6779 }
6780 break;
6781
6782 case OPTION_BASE_SIZE_DEFAULT_16:
6783 m68k_index_width_default = SIZE_WORD;
6784 break;
6785
6786 case OPTION_BASE_SIZE_DEFAULT_32:
6787 m68k_index_width_default = SIZE_LONG;
6788 break;
6789
6790 case OPTION_DISP_SIZE_DEFAULT_16:
6791 m68k_rel32 = 0;
6792 m68k_rel32_from_cmdline = 1;
6793 break;
6794
6795 case OPTION_DISP_SIZE_DEFAULT_32:
6796 m68k_rel32 = 1;
6797 m68k_rel32_from_cmdline = 1;
6798 break;
6799
6800 default:
6801 return 0;
6802 }
6803
6804 return 1;
6805 }
6806
6807 void
6808 md_show_usage (stream)
6809 FILE *stream;
6810 {
6811 fprintf(stream, _("\
6812 680X0 options:\n\
6813 -l use 1 word for refs to undefined symbols [default 2]\n\
6814 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6815 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6816 | -mcpu32 | -m5200\n\
6817 specify variant of 680X0 architecture [default 68020]\n\
6818 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6819 target has/lacks floating-point coprocessor\n\
6820 [default yes for 68020, 68030, and cpu32]\n"));
6821 fprintf(stream, _("\
6822 -m68851 | -mno-68851\n\
6823 target has/lacks memory-management unit coprocessor\n\
6824 [default yes for 68020 and up]\n\
6825 -pic, -k generate position independent code\n\
6826 -S turn jbsr into jsr\n\
6827 --register-prefix-optional\n\
6828 recognize register names without prefix character\n\
6829 --bitwise-or do not treat `|' as a comment character\n"));
6830 fprintf (stream, _("\
6831 --base-size-default-16 base reg without size is 16 bits\n\
6832 --base-size-default-32 base reg without size is 32 bits (default)\n\
6833 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6834 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6835 }
6836 \f
6837 #ifdef TEST2
6838
6839 /* TEST2: Test md_assemble() */
6840 /* Warning, this routine probably doesn't work anymore */
6841
6842 main ()
6843 {
6844 struct m68k_it the_ins;
6845 char buf[120];
6846 char *cp;
6847 int n;
6848
6849 m68k_ip_begin ();
6850 for (;;)
6851 {
6852 if (!gets (buf) || !*buf)
6853 break;
6854 if (buf[0] == '|' || buf[1] == '.')
6855 continue;
6856 for (cp = buf; *cp; cp++)
6857 if (*cp == '\t')
6858 *cp = ' ';
6859 if (is_label (buf))
6860 continue;
6861 memset (&the_ins, '\0', sizeof (the_ins));
6862 m68k_ip (&the_ins, buf);
6863 if (the_ins.error)
6864 {
6865 printf (_("Error %s in %s\n"), the_ins.error, buf);
6866 }
6867 else
6868 {
6869 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6870 for (n = 0; n < the_ins.numo; n++)
6871 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6872 printf (" ");
6873 print_the_insn (&the_ins.opcode[0], stdout);
6874 (void) putchar ('\n');
6875 }
6876 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6877 {
6878 if (the_ins.operands[n].error)
6879 {
6880 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6881 continue;
6882 }
6883 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6884 if (the_ins.operands[n].b_const)
6885 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6886 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6887 if (the_ins.operands[n].b_iadd)
6888 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6889 (void) putchar ('\n');
6890 }
6891 }
6892 m68k_ip_end ();
6893 return 0;
6894 }
6895
6896 is_label (str)
6897 char *str;
6898 {
6899 while (*str == ' ')
6900 str++;
6901 while (*str && *str != ' ')
6902 str++;
6903 if (str[-1] == ':' || str[1] == '=')
6904 return 1;
6905 return 0;
6906 }
6907
6908 #endif
6909
6910 /* Possible states for relaxation:
6911
6912 0 0 branch offset byte (bra, etc)
6913 0 1 word
6914 0 2 long
6915
6916 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6917 1 1 word
6918 1 2 long
6919
6920 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6921 2 1 word-long
6922 2 2 long-word
6923 2 3 long-long
6924
6925 */
6926
6927 /* We have no need to default values of symbols. */
6928
6929 /* ARGSUSED */
6930 symbolS *
6931 md_undefined_symbol (name)
6932 char *name;
6933 {
6934 return 0;
6935 }
6936
6937 /* Round up a section size to the appropriate boundary. */
6938 valueT
6939 md_section_align (segment, size)
6940 segT segment;
6941 valueT size;
6942 {
6943 #ifdef OBJ_AOUT
6944 #ifdef BFD_ASSEMBLER
6945 /* For a.out, force the section size to be aligned. If we don't do
6946 this, BFD will align it for us, but it will not write out the
6947 final bytes of the section. This may be a bug in BFD, but it is
6948 easier to fix it here since that is how the other a.out targets
6949 work. */
6950 int align;
6951
6952 align = bfd_get_section_alignment (stdoutput, segment);
6953 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6954 #endif
6955 #endif
6956
6957 return size;
6958 }
6959
6960 /* Exactly what point is a PC-relative offset relative TO?
6961 On the 68k, it is relative to the address of the first extension
6962 word. The difference between the addresses of the offset and the
6963 first extension word is stored in fx_pcrel_adjust. */
6964 long
6965 md_pcrel_from (fixP)
6966 fixS *fixP;
6967 {
6968 int adjust;
6969
6970 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6971 -1 as 64. */
6972 adjust = fixP->fx_pcrel_adjust;
6973 if (adjust == 64)
6974 adjust = -1;
6975 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6976 }
6977
6978 #ifndef BFD_ASSEMBLER
6979 #ifdef OBJ_COFF
6980
6981 /*ARGSUSED*/
6982 void
6983 tc_coff_symbol_emit_hook (ignore)
6984 symbolS *ignore;
6985 {
6986 }
6987
6988 int
6989 tc_coff_sizemachdep (frag)
6990 fragS *frag;
6991 {
6992 switch (frag->fr_subtype & 0x3)
6993 {
6994 case BYTE:
6995 return 1;
6996 case SHORT:
6997 return 2;
6998 case LONG:
6999 return 4;
7000 default:
7001 abort ();
7002 return 0;
7003 }
7004 }
7005
7006 #endif
7007 #endif
7008
7009 /* end of tc-m68k.c */
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