gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
   3
   4    This file is part of GAS, the GNU Assembler.
   5
   6    GAS is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2, or (at your option)
   9    any later version.
  10
  11    GAS is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  19    02111-1307, USA.  */
  20
  21 #ifndef TC_I386
  22 #define TC_I386 1
  23
  24 #ifdef ANSI_PROTOTYPES
  25 struct fix;
  26 #endif
  27
  28 #define TARGET_BYTES_BIG_ENDIAN 0
  29
  30 #ifdef TE_LYNX
  31 #define TARGET_FORMAT           "coff-i386-lynx"
  32 #endif
  33
  34 #ifdef BFD_ASSEMBLER
  35 /* This is used to determine relocation types in tc-i386.c.  The first
  36    parameter is the current relocation type, the second one is the desired
  37    type.  The idea is that if the original type is already some kind of PIC
  38    relocation, we leave it alone, otherwise we give it the desired type */
  39
  40 #define TC_RELOC(X,Y) (((X) != BFD_RELOC_386_PLT32 && \
  41            (X) != BFD_RELOC_386_GOTOFF && \
  42            (X) != BFD_RELOC_386_GOT32 && \
  43            (X) != BFD_RELOC_386_GOTPC) ? Y : X)
  44
  45 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
  46 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
  47
  48 /* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
  49  * It comes up in complicated expressions such as
  50  * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
  51  * the regular expressions.  The fixup specified here when used at runtime
  52  * implies that we should add the address of the GOT to the specified location,
  53  * and as a result we have simplified the expression into something we can use.
  54  */
  55 #define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC
  56
  57 /* This expression evaluates to false if the relocation is for a local object
  58    for which we still want to do the relocation at runtime.  True if we
  59    are willing to perform this relocation while building the .o file.
  60    This is only used for pcrel relocations, so GOTOFF does not need to be
  61    checked here.  I am not sure if some of the others are ever used with
  62    pcrel, but it is easier to be safe than sorry. */
  63
  64 #define TC_RELOC_RTSYM_LOC_FIXUP(FIX)                           \
  65   ((FIX)->fx_r_type != BFD_RELOC_386_PLT32                      \
  66    && (FIX)->fx_r_type != BFD_RELOC_386_GOT32                   \
  67    && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC                   \
  68    && ((FIX)->fx_addsy == NULL                                  \
  69        || (! S_IS_EXTERNAL ((FIX)->fx_addsy)                    \
  70            && ! S_IS_WEAK ((FIX)->fx_addsy)                     \
  71            && S_IS_DEFINED ((FIX)->fx_addsy)                    \
  72            && ! S_IS_COMMON ((FIX)->fx_addsy))))
  73
  74 #define TARGET_ARCH             bfd_arch_i386
  75
  76 #ifdef OBJ_AOUT
  77 #ifdef TE_NetBSD
  78 #define TARGET_FORMAT           "a.out-i386-netbsd"
  79 #endif
  80 #ifdef TE_386BSD
  81 #define TARGET_FORMAT           "a.out-i386-bsd"
  82 #endif
  83 #ifdef TE_LINUX
  84 #define TARGET_FORMAT           "a.out-i386-linux"
  85 #endif
  86 #ifdef TE_Mach
  87 #define TARGET_FORMAT           "a.out-mach3"
  88 #endif
  89 #ifdef TE_DYNIX
  90 #define TARGET_FORMAT           "a.out-i386-dynix"
  91 #endif
  92 #ifndef TARGET_FORMAT
  93 #define TARGET_FORMAT           "a.out-i386"
  94 #endif
  95 #endif /* OBJ_AOUT */
  96
  97 #ifdef OBJ_ELF
  98 #define TARGET_FORMAT           "elf32-i386"
  99 #endif
 100
 101 #ifdef OBJ_MAYBE_ELF
 102 #ifdef OBJ_MAYBE_COFF
 103 extern const char *i386_target_format PARAMS ((void));
 104 #define TARGET_FORMAT i386_target_format ()
 105 #endif
 106 #endif
 107
 108 #else /* ! BFD_ASSEMBLER */
 109
 110 /* COFF STUFF */
 111
 112 #define COFF_MAGIC I386MAGIC
 113 #define BFD_ARCH bfd_arch_i386
 114 #define COFF_FLAGS F_AR32WR
 115 #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
 116 #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
 117 extern short tc_coff_fix2rtype PARAMS ((struct fix *));
 118 #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
 119 extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
 120 #define SUB_SEGMENT_ALIGN(SEG) 2
 121 #define TC_RVA_RELOC 7
 122 /* Need this for PIC relocations */
 123 #define NEED_FX_R_TYPE
 124
 125
 126 #ifdef TE_386BSD
 127 /* The BSDI linker apparently rejects objects with a machine type of
 128    M_386 (100).  */
 129 #define AOUT_MACHTYPE 0
 130 #else
 131 #define AOUT_MACHTYPE 100
 132 #endif
 133
 134 #undef REVERSE_SORT_RELOCS
 135
 136 #endif /* ! BFD_ASSEMBLER */
 137
 138 #define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
 139 extern int tc_i386_force_relocation PARAMS ((struct fix *));
 140
 141 #ifdef BFD_ASSEMBLER
 142 #define NO_RELOC BFD_RELOC_NONE
 143 #else
 144 #define NO_RELOC 0
 145 #endif
 146 #define tc_coff_symbol_emit_hook(a)     ;       /* not used */
 147
 148 #ifndef BFD_ASSEMBLER
 149 #ifndef OBJ_AOUT
 150 #ifndef TE_PE
 151 #ifndef TE_GO32
 152 /* Local labels starts with .L */
 153 #define LOCAL_LABEL(name) (name[0] == '.' \
 154                  && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
 155 #endif
 156 #endif
 157 #endif
 158 #endif
 159
 160 #define LOCAL_LABELS_FB 1
 161
 162 #define tc_aout_pre_write_hook(x)       {;}     /* not used */
 163 #define tc_crawl_symbol_chain(a)        {;}     /* not used */
 164 #define tc_headers_hook(a)              {;}     /* not used */
 165
 166 extern const char extra_symbol_chars[];
 167 #define tc_symbol_chars extra_symbol_chars
 168
 169 #define MAX_OPERANDS 3          /* max operands per insn */
 170 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
 171 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
 172
 173 /* Prefixes will be emitted in the order defined below.
 174    WAIT_PREFIX must be the first prefix since FWAIT is really is an
 175    instruction, and so must come before any prefixes. */
 176 #define WAIT_PREFIX     0
 177 #define LOCKREP_PREFIX  1
 178 #define ADDR_PREFIX     2
 179 #define DATA_PREFIX     3
 180 #define SEG_PREFIX      4
 181 #define MAX_PREFIXES    5       /* max prefixes per opcode */
 182
 183 /* we define the syntax here (modulo base,index,scale syntax) */
 184 #define REGISTER_PREFIX '%'
 185 #define IMMEDIATE_PREFIX '$'
 186 #define ABSOLUTE_PREFIX '*'
 187
 188 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 189 #define NOP_OPCODE (char) 0x90
 190
 191 /* register numbers */
 192 #define EBP_REG_NUM 5
 193 #define ESP_REG_NUM 4
 194
 195 /* modrm_byte.regmem for twobyte escape */
 196 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 197 /* index_base_byte.index for no index register addressing */
 198 #define NO_INDEX_REGISTER ESP_REG_NUM
 199 /* index_base_byte.base for no base register addressing */
 200 #define NO_BASE_REGISTER EBP_REG_NUM
 201 #define NO_BASE_REGISTER_16 6
 202
 203 /* these are the instruction mnemonic suffixes.  */
 204 #define DWORD_MNEM_SUFFIX 'l'
 205 #define WORD_MNEM_SUFFIX  'w'
 206 #define BYTE_MNEM_SUFFIX  'b'
 207 #define SHORT_MNEM_SUFFIX 's'
 208 #define LONG_MNEM_SUFFIX  'l'
 209 /* Intel Syntax */
 210 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 211 /* Intel Syntax */
 212 #define INTEL_DWORD_MNEM_SUFFIX 'd'
 213
 214 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 215 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 216 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 217
 218 #define END_OF_INSN '\0'
 219
 220 /* Intel Syntax */
 221 /* Values 0-4 map onto scale factor */
 222 #define BYTE_PTR     0
 223 #define WORD_PTR     1
 224 #define DWORD_PTR    2
 225 #define QWORD_PTR    3
 226 #define XWORD_PTR    4
 227 #define SHORT        5
 228 #define OFFSET_FLAT  6
 229 #define FLAT         7
 230 #define NONE_FOUND   8
 231 /*
 232   When an operand is read in it is classified by its type.  This type includes
 233   all the possible ways an operand can be used.  Thus, '%eax' is both 'register
 234   # 0' and 'The Accumulator'.  In our language this is expressed by OR'ing
 235   'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
 236   Operands are classified so that we can match given operand types with
 237   the opcode table in opcode/i386.h.
 238   */
 239 /* register */
 240 #define Reg8               0x1  /* 8 bit reg */
 241 #define Reg16              0x2  /* 16 bit reg */
 242 #define Reg32              0x4  /* 32 bit reg */
 243 /* immediate */
 244 #define Imm8               0x8  /* 8 bit immediate */
 245 #define Imm8S             0x10  /* 8 bit immediate sign extended */
 246 #define Imm16             0x20  /* 16 bit immediate */
 247 #define Imm32             0x40  /* 32 bit immediate */
 248 #define Imm1              0x80  /* 1 bit immediate */
 249 /* memory */
 250 #define BaseIndex        0x100
 251 /* Disp8,16,32 are used in different ways, depending on the
 252    instruction.  For jumps, they specify the size of the PC relative
 253    displacement, for baseindex type instructions, they specify the
 254    size of the offset relative to the base register, and for memory
 255    offset instructions such as `mov 1234,%al' they specify the size of
 256    the offset relative to the segment base.  */
 257 #define Disp8            0x200  /* 8 bit displacement */
 258 #define Disp16           0x400  /* 16 bit displacement */
 259 #define Disp32           0x800  /* 32 bit displacement */
 260 /* specials */
 261 #define InOutPortReg    0x1000  /* register to hold in/out port addr = dx */
 262 #define ShiftCount      0x2000  /* register to hold shift cound = cl */
 263 #define Control         0x4000  /* Control register */
 264 #define Debug           0x8000  /* Debug register */
 265 #define Test           0x10000  /* Test register */
 266 #define FloatReg       0x20000  /* Float register */
 267 #define FloatAcc       0x40000  /* Float stack top %st(0) */
 268 #define SReg2          0x80000  /* 2 bit segment register */
 269 #define SReg3         0x100000  /* 3 bit segment register */
 270 #define Acc           0x200000  /* Accumulator %al or %ax or %eax */
 271 #define JumpAbsolute  0x400000
 272 #define RegMMX        0x800000  /* MMX register */
 273 #define EsSeg        0x1000000  /* String insn operand with fixed es segment */
 274
 275 #define Reg     (Reg8|Reg16|Reg32)      /* gen'l register */
 276 #define WordReg (Reg16|Reg32)
 277 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 278 #define Imm     (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
 279 #define Disp    (Disp8|Disp16|Disp32)   /* General displacement */
 280 #define AnyMem  (Disp|BaseIndex)        /* General memory */
 281 /* The following aliases are defined because the opcode table
 282    carefully specifies the allowed memory types for each instruction.
 283    At the moment we can only tell a memory reference size by the
 284    instruction suffix, so there's not much point in defining Mem8,
 285    Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 286    the suffix directly to check memory operands.  */
 287 #define LLongMem AnyMem         /* 64 bits (or more) */
 288 #define LongMem AnyMem          /* 32 bit memory ref */
 289 #define ShortMem AnyMem         /* 16 bit memory ref */
 290 #define WordMem AnyMem          /* 16 or 32 bit memory ref */
 291 #define ByteMem AnyMem          /* 8 bit memory ref */
 292
 293 #define SMALLEST_DISP_TYPE(num) \
 294     (fits_in_signed_byte(num) ? (Disp8|Disp32) : Disp32)
 295
 296 typedef struct
 297 {
 298   /* instruction name sans width suffix ("mov" for movl insns) */
 299   char *name;
 300
 301   /* how many operands */
 302   unsigned int operands;
 303
 304   /* base_opcode is the fundamental opcode byte without optional
 305      prefix(es).  */
 306   unsigned int base_opcode;
 307
 308   /* extension_opcode is the 3 bit extension for group <n> insns.
 309      This field is also used to store the 8-bit opcode suffix for the
 310      AMD 3DNow! instructions.
 311      If this template has no extension opcode (the usual case) use None */
 312   unsigned int extension_opcode;
 313 #define None 0xffff             /* If no extension_opcode is possible. */
 314
 315   /* the bits in opcode_modifier are used to generate the final opcode from
 316      the base_opcode.  These bits also are used to detect alternate forms of
 317      the same instruction */
 318   unsigned int opcode_modifier;
 319
 320   /* opcode_modifier bits: */
 321 #define W                  0x1  /* set if operands can be words or dwords
 322                                    encoded the canonical way */
 323 #define D                  0x2  /* D = 0 if Reg --> Regmem;
 324                                    D = 1 if Regmem --> Reg:    MUST BE 0x2 */
 325 #define Modrm              0x4
 326 #define ReverseRegRegmem   0x8  /* swap reg,regmem fields for 2 reg case */
 327 #define FloatR             0x8  /* src/dest swap for floats:   MUST BE 0x8 */
 328 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 329 #define FloatMF           0x20  /* FP insn memory format bit, sized by 0x4 */
 330 #define Jump              0x40  /* special case for jump insns. */
 331 #define JumpDword         0x80  /* call and jump */
 332 #define JumpByte         0x100  /* loop and jecxz */
 333 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 334 #define FloatD           0x400  /* direction for float insns:  MUST BE 0x400 */
 335 #define Seg2ShortForm    0x800  /* encoding of load segment reg insns */
 336 #define Seg3ShortForm   0x1000  /* fs/gs segment register insns. */
 337 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 338 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 339 #define IgnoreSize      0x8000  /* instruction ignores operand size prefix */
 340 #define No_bSuf        0x10000  /* b suffix on instruction illegal */
 341 #define No_wSuf        0x20000  /* w suffix on instruction illegal */
 342 #define No_lSuf        0x40000  /* l suffix on instruction illegal */
 343 #define No_sSuf        0x80000  /* s suffix on instruction illegal */
 344 #define FWait         0x100000  /* instruction needs FWAIT */
 345 #define IsString      0x200000  /* quick test for string instructions */
 346 #define regKludge     0x400000  /* fake an extra reg operand for clr, imul */
 347 #define IsPrefix      0x800000  /* opcode is a prefix */
 348 #define No_dSuf      0x1000000  /* d suffix on instruction illegal */
 349 #define No_xSuf      0x2000000  /* x suffix on instruction illegal */
 350 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 351
 352   /* operand_types[i] describes the type of operand i.  This is made
 353      by OR'ing together all of the possible type masks.  (e.g.
 354      'operand_types[i] = Reg|Imm' specifies that operand i can be
 355      either a register or an immediate operand */
 356   unsigned int operand_types[3];
 357 }
 358 template;
 359
 360 /*
 361   'templates' is for grouping together 'template' structures for opcodes
 362   of the same name.  This is only used for storing the insns in the grand
 363   ole hash table of insns.
 364   The templates themselves start at START and range up to (but not including)
 365   END.
 366   */
 367 typedef struct
 368   {
 369     const template *start;
 370     const template *end;
 371   } templates;
 372
 373 /* these are for register name --> number & type hash lookup */
 374 typedef struct
 375   {
 376     char *reg_name;
 377     unsigned int reg_type;
 378     unsigned int reg_num;
 379   }
 380 reg_entry;
 381
 382 typedef struct
 383   {
 384     char *seg_name;
 385     unsigned int seg_prefix;
 386   }
 387 seg_entry;
 388
 389 /* 386 operand encoding bytes:  see 386 book for details of this. */
 390 typedef struct
 391   {
 392     unsigned int regmem;        /* codes register or memory operand */
 393     unsigned int reg;           /* codes register operand (or extended opcode) */
 394     unsigned int mode;          /* how to interpret regmem & reg */
 395   }
 396 modrm_byte;
 397
 398 /* 386 opcode byte to code indirect addressing. */
 399 typedef struct
 400   {
 401     unsigned base;
 402     unsigned index;
 403     unsigned scale;
 404   }
 405 sib_byte;
 406
 407 /* The name of the global offset table generated by the compiler. Allow
 408    this to be overridden if need be. */
 409 #ifndef GLOBAL_OFFSET_TABLE_NAME
 410 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 411 #endif
 412
 413 #ifdef BFD_ASSEMBLER
 414 void i386_validate_fix PARAMS ((struct fix *));
 415 #define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
 416 #endif
 417
 418 #endif /* TC_I386 */
 419
 420 #define md_operand(x)
 421
 422 extern const struct relax_type md_relax_table[];
 423 #define TC_GENERIC_RELAX_TABLE md_relax_table
 424
 425
 426 extern int flag_16bit_code;
 427
 428 #ifdef BFD_ASSEMBLER
 429 #define md_maybe_text() \
 430   ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
 431 #else
 432 #define md_maybe_text() \
 433   (now_seg != data_section && now_seg != bss_section)
 434 #endif
 435
 436 #define md_do_align(n, fill, len, max, around)                          \
 437 if ((n) && !need_pass_2                                                 \
 438     && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1))         \
 439     && md_maybe_text ())                                                \
 440   {                                                                     \
 441     char *p;                                                            \
 442     p = frag_var (rs_align_code, 15, 1, (relax_substateT) max,          \
 443                   (symbolS *) 0, (offsetT) (n), (char *) 0);            \
 444     *p = 0x90;                                                          \
 445     goto around;                                                        \
 446   }
 447
 448 extern void i386_align_code PARAMS ((fragS *, int));
 449
 450 #define HANDLE_ALIGN(fragP)                                             \
 451 if (fragP->fr_type == rs_align_code)                                    \
 452   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 453                            - fragP->fr_address                          \
 454                            - fragP->fr_fix));
 455
 456 /* call md_apply_fix3 with segment instead of md_apply_fix */
 457 #define MD_APPLY_FIX3
 458
 459 void i386_print_statistics PARAMS ((FILE *));
 460 #define tc_print_statistics i386_print_statistics
 461
 462 #define md_number_to_chars number_to_chars_littleendian
 463
 464 #ifdef SCO_ELF
 465 #define tc_init_after_args() sco_id ()
 466 extern void sco_id PARAMS ((void));
 467 #endif
 468
 469 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 470
 471 /* end of tc-i386.h */