opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int, int);
  59 static void OP_E_extended (int, int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_VEX_FMA (int, int);
  97 static void OP_EX_Vex (int, int);
  98 static void OP_EX_VexW (int, int);
  99 static void OP_EX_VexImmW (int, int);
 100 static void OP_XMM_Vex (int, int);
 101 static void OP_XMM_VexW (int, int);
 102 static void OP_REG_VexI4 (int, int);
 103 static void PCLMUL_Fixup (int, int);
 104 static void VEXI4_Fixup (int, int);
 105 static void VZERO_Fixup (int, int);
 106 static void VCMP_Fixup (int, int);
 107 static void VPERMIL2_Fixup (int, int);
 108 static void OP_0f07 (int, int);
 109 static void OP_Monitor (int, int);
 110 static void OP_Mwait (int, int);
 111 static void NOP_Fixup1 (int, int);
 112 static void NOP_Fixup2 (int, int);
 113 static void OP_3DNowSuffix (int, int);
 114 static void CMP_Fixup (int, int);
 115 static void BadOp (void);
 116 static void REP_Fixup (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void print_drex_arg (unsigned int, int, int);
 121 static void OP_DREX4 (int, int);
 122 static void OP_DREX3 (int, int);
 123 static void OP_DREX_ICMP (int, int);
 124 static void OP_DREX_FCMP (int, int);
 125 static void MOVBE_Fixup (int, int);
 126
 127 struct dis_private {
 128   /* Points to first byte not fetched.  */
 129   bfd_byte *max_fetched;
 130   bfd_byte the_buffer[MAX_MNEM_SIZE];
 131   bfd_vma insn_start;
 132   int orig_sizeflag;
 133   jmp_buf bailout;
 134 };
 135
 136 enum address_mode
 137 {
 138   mode_16bit,
 139   mode_32bit,
 140   mode_64bit
 141 };
 142
 143 enum address_mode address_mode;
 144
 145 /* Flags for the prefixes for the current instruction.  See below.  */
 146 static int prefixes;
 147
 148 /* REX prefix the current instruction.  See below.  */
 149 static int rex;
 150 /* Bits of REX we've already used.  */
 151 static int rex_used;
 152 /* Original REX prefix.  */
 153 static int rex_original;
 154 /* REX bits in original REX prefix ignored.  It may not be the same
 155    as rex_original since some bits may not be ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Special 'registers' for DREX handling */
 173 #define DREX_REG_UNKNOWN        1000    /* not initialized */
 174 #define DREX_REG_MEMORY         1001    /* use MODRM/SIB/OFFSET memory */
 175
 176 /* The DREX byte has the following fields:
 177    Bits 7-4 -- DREX.Dest, xmm destination register
 178    Bit 3    -- DREX.OC0, operand config bit defines operand order
 179    Bit 2    -- DREX.R, equivalent to REX_R bit, to extend ModRM register
 180    Bit 1    -- DREX.X, equivalent to REX_X bit, to extend SIB index field
 181    Bit 0    -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
 182                SIB base field, or opcode reg field.  */
 183 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
 184 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
 185
 186 /* Flags for prefixes which we somehow handled when printing the
 187    current instruction.  */
 188 static int used_prefixes;
 189
 190 /* Flags stored in PREFIXES.  */
 191 #define PREFIX_REPZ 1
 192 #define PREFIX_REPNZ 2
 193 #define PREFIX_LOCK 4
 194 #define PREFIX_CS 8
 195 #define PREFIX_SS 0x10
 196 #define PREFIX_DS 0x20
 197 #define PREFIX_ES 0x40
 198 #define PREFIX_FS 0x80
 199 #define PREFIX_GS 0x100
 200 #define PREFIX_DATA 0x200
 201 #define PREFIX_ADDR 0x400
 202 #define PREFIX_FWAIT 0x800
 203
 204 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 205    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 206    on error.  */
 207 #define FETCH_DATA(info, addr) \
 208   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 209    ? 1 : fetch_data ((info), (addr)))
 210
 211 static int
 212 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 213 {
 214   int status;
 215   struct dis_private *priv = (struct dis_private *) info->private_data;
 216   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 217
 218   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 219     status = (*info->read_memory_func) (start,
 220                                         priv->max_fetched,
 221                                         addr - priv->max_fetched,
 222                                         info);
 223   else
 224     status = -1;
 225   if (status != 0)
 226     {
 227       /* If we did manage to read at least one byte, then
 228          print_insn_i386 will do something sensible.  Otherwise, print
 229          an error.  We do that here because this is where we know
 230          STATUS.  */
 231       if (priv->max_fetched == priv->the_buffer)
 232         (*info->memory_error_func) (status, start, info);
 233       longjmp (priv->bailout, 1);
 234     }
 235   else
 236     priv->max_fetched = addr;
 237   return 1;
 238 }
 239
 240 #define XX { NULL, 0 }
 241
 242 #define Eb { OP_E, b_mode }
 243 #define Ev { OP_E, v_mode }
 244 #define Ed { OP_E, d_mode }
 245 #define Edq { OP_E, dq_mode }
 246 #define Edqw { OP_E, dqw_mode }
 247 #define Edqb { OP_E, dqb_mode }
 248 #define Edqd { OP_E, dqd_mode }
 249 #define Eq { OP_E, q_mode }
 250 #define indirEv { OP_indirE, stack_v_mode }
 251 #define indirEp { OP_indirE, f_mode }
 252 #define stackEv { OP_E, stack_v_mode }
 253 #define Em { OP_E, m_mode }
 254 #define Ew { OP_E, w_mode }
 255 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 256 #define Ma { OP_M, a_mode }
 257 #define Mb { OP_M, b_mode }
 258 #define Md { OP_M, d_mode }
 259 #define Mo { OP_M, o_mode }
 260 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 261 #define Mq { OP_M, q_mode }
 262 #define Mx { OP_M, x_mode }
 263 #define Mxmm { OP_M, xmm_mode }
 264 #define Gb { OP_G, b_mode }
 265 #define Gv { OP_G, v_mode }
 266 #define Gd { OP_G, d_mode }
 267 #define Gdq { OP_G, dq_mode }
 268 #define Gm { OP_G, m_mode }
 269 #define Gw { OP_G, w_mode }
 270 #define Rd { OP_R, d_mode }
 271 #define Rm { OP_R, m_mode }
 272 #define Ib { OP_I, b_mode }
 273 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 274 #define Iv { OP_I, v_mode }
 275 #define Iq { OP_I, q_mode }
 276 #define Iv64 { OP_I64, v_mode }
 277 #define Iw { OP_I, w_mode }
 278 #define I1 { OP_I, const_1_mode }
 279 #define Jb { OP_J, b_mode }
 280 #define Jv { OP_J, v_mode }
 281 #define Cm { OP_C, m_mode }
 282 #define Dm { OP_D, m_mode }
 283 #define Td { OP_T, d_mode }
 284 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 285
 286 #define RMeAX { OP_REG, eAX_reg }
 287 #define RMeBX { OP_REG, eBX_reg }
 288 #define RMeCX { OP_REG, eCX_reg }
 289 #define RMeDX { OP_REG, eDX_reg }
 290 #define RMeSP { OP_REG, eSP_reg }
 291 #define RMeBP { OP_REG, eBP_reg }
 292 #define RMeSI { OP_REG, eSI_reg }
 293 #define RMeDI { OP_REG, eDI_reg }
 294 #define RMrAX { OP_REG, rAX_reg }
 295 #define RMrBX { OP_REG, rBX_reg }
 296 #define RMrCX { OP_REG, rCX_reg }
 297 #define RMrDX { OP_REG, rDX_reg }
 298 #define RMrSP { OP_REG, rSP_reg }
 299 #define RMrBP { OP_REG, rBP_reg }
 300 #define RMrSI { OP_REG, rSI_reg }
 301 #define RMrDI { OP_REG, rDI_reg }
 302 #define RMAL { OP_REG, al_reg }
 303 #define RMAL { OP_REG, al_reg }
 304 #define RMCL { OP_REG, cl_reg }
 305 #define RMDL { OP_REG, dl_reg }
 306 #define RMBL { OP_REG, bl_reg }
 307 #define RMAH { OP_REG, ah_reg }
 308 #define RMCH { OP_REG, ch_reg }
 309 #define RMDH { OP_REG, dh_reg }
 310 #define RMBH { OP_REG, bh_reg }
 311 #define RMAX { OP_REG, ax_reg }
 312 #define RMDX { OP_REG, dx_reg }
 313
 314 #define eAX { OP_IMREG, eAX_reg }
 315 #define eBX { OP_IMREG, eBX_reg }
 316 #define eCX { OP_IMREG, eCX_reg }
 317 #define eDX { OP_IMREG, eDX_reg }
 318 #define eSP { OP_IMREG, eSP_reg }
 319 #define eBP { OP_IMREG, eBP_reg }
 320 #define eSI { OP_IMREG, eSI_reg }
 321 #define eDI { OP_IMREG, eDI_reg }
 322 #define AL { OP_IMREG, al_reg }
 323 #define CL { OP_IMREG, cl_reg }
 324 #define DL { OP_IMREG, dl_reg }
 325 #define BL { OP_IMREG, bl_reg }
 326 #define AH { OP_IMREG, ah_reg }
 327 #define CH { OP_IMREG, ch_reg }
 328 #define DH { OP_IMREG, dh_reg }
 329 #define BH { OP_IMREG, bh_reg }
 330 #define AX { OP_IMREG, ax_reg }
 331 #define DX { OP_IMREG, dx_reg }
 332 #define zAX { OP_IMREG, z_mode_ax_reg }
 333 #define indirDX { OP_IMREG, indir_dx_reg }
 334
 335 #define Sw { OP_SEG, w_mode }
 336 #define Sv { OP_SEG, v_mode }
 337 #define Ap { OP_DIR, 0 }
 338 #define Ob { OP_OFF64, b_mode }
 339 #define Ov { OP_OFF64, v_mode }
 340 #define Xb { OP_DSreg, eSI_reg }
 341 #define Xv { OP_DSreg, eSI_reg }
 342 #define Xz { OP_DSreg, eSI_reg }
 343 #define Yb { OP_ESreg, eDI_reg }
 344 #define Yv { OP_ESreg, eDI_reg }
 345 #define DSBX { OP_DSreg, eBX_reg }
 346
 347 #define es { OP_REG, es_reg }
 348 #define ss { OP_REG, ss_reg }
 349 #define cs { OP_REG, cs_reg }
 350 #define ds { OP_REG, ds_reg }
 351 #define fs { OP_REG, fs_reg }
 352 #define gs { OP_REG, gs_reg }
 353
 354 #define MX { OP_MMX, 0 }
 355 #define XM { OP_XMM, 0 }
 356 #define XMM { OP_XMM, xmm_mode }
 357 #define EM { OP_EM, v_mode }
 358 #define EMd { OP_EM, d_mode }
 359 #define EMx { OP_EM, x_mode }
 360 #define EXw { OP_EX, w_mode }
 361 #define EXd { OP_EX, d_mode }
 362 #define EXq { OP_EX, q_mode }
 363 #define EXx { OP_EX, x_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXxmmq { OP_EX, xmmq_mode }
 366 #define EXymmq { OP_EX, ymmq_mode }
 367 #define MS { OP_MS, v_mode }
 368 #define XS { OP_XS, v_mode }
 369 #define EMCq { OP_EMC, q_mode }
 370 #define MXC { OP_MXC, 0 }
 371 #define OPSUF { OP_3DNowSuffix, 0 }
 372 #define CMP { CMP_Fixup, 0 }
 373 #define XMM0 { XMM_Fixup, 0 }
 374
 375 #define Vex { OP_VEX, vex_mode }
 376 #define Vex128 { OP_VEX, vex128_mode }
 377 #define Vex256 { OP_VEX, vex256_mode }
 378 #define VexI4 { VEXI4_Fixup, 0}
 379 #define VexFMA { OP_VEX_FMA, vex_mode }
 380 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
 381 #define EXdVex { OP_EX_Vex, d_mode }
 382 #define EXqVex { OP_EX_Vex, q_mode }
 383 #define EXVexW { OP_EX_VexW, x_mode }
 384 #define EXdVexW { OP_EX_VexW, d_mode }
 385 #define EXqVexW { OP_EX_VexW, q_mode }
 386 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 387 #define XMVex { OP_XMM_Vex, 0 }
 388 #define XMVexW { OP_XMM_VexW, 0 }
 389 #define XMVexI4 { OP_REG_VexI4, x_mode }
 390 #define PCLMUL { PCLMUL_Fixup, 0 }
 391 #define VZERO { VZERO_Fixup, 0 }
 392 #define VCMP { VCMP_Fixup, 0 }
 393 #define VPERMIL2 { VPERMIL2_Fixup, 0 }
 394
 395 /* Used handle "rep" prefix for string instructions.  */
 396 #define Xbr { REP_Fixup, eSI_reg }
 397 #define Xvr { REP_Fixup, eSI_reg }
 398 #define Ybr { REP_Fixup, eDI_reg }
 399 #define Yvr { REP_Fixup, eDI_reg }
 400 #define Yzr { REP_Fixup, eDI_reg }
 401 #define indirDXr { REP_Fixup, indir_dx_reg }
 402 #define ALr { REP_Fixup, al_reg }
 403 #define eAXr { REP_Fixup, eAX_reg }
 404
 405 #define cond_jump_flag { NULL, cond_jump_mode }
 406 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 407
 408 /* bits in sizeflag */
 409 #define SUFFIX_ALWAYS 4
 410 #define AFLAG 2
 411 #define DFLAG 1
 412
 413 /* byte operand */
 414 #define b_mode                  1
 415 /* operand size depends on prefixes */
 416 #define v_mode                  (b_mode + 1)
 417 /* word operand */
 418 #define w_mode                  (v_mode + 1)
 419 /* double word operand  */
 420 #define d_mode                  (w_mode + 1)
 421 /* quad word operand */
 422 #define q_mode                  (d_mode + 1)
 423 /* ten-byte operand */
 424 #define t_mode                  (q_mode + 1)
 425 /* 16-byte XMM or 32-byte YMM operand */
 426 #define x_mode                  (t_mode + 1)
 427 /* 16-byte XMM operand */
 428 #define xmm_mode                (x_mode + 1)
 429 /* 16-byte XMM or quad word operand */
 430 #define xmmq_mode               (xmm_mode + 1)
 431 /* 32-byte YMM or quad word operand */
 432 #define ymmq_mode               (xmmq_mode + 1)
 433 /* d_mode in 32bit, q_mode in 64bit mode.  */
 434 #define m_mode                  (ymmq_mode + 1)
 435 /* pair of v_mode operands */
 436 #define a_mode                  (m_mode + 1)
 437 #define cond_jump_mode          (a_mode + 1)
 438 #define loop_jcxz_mode          (cond_jump_mode + 1)
 439 /* operand size depends on REX prefixes.  */
 440 #define dq_mode                 (loop_jcxz_mode + 1)
 441 /* registers like dq_mode, memory like w_mode.  */
 442 #define dqw_mode                (dq_mode + 1)
 443 /* 4- or 6-byte pointer operand */
 444 #define f_mode                  (dqw_mode + 1)
 445 #define const_1_mode            (f_mode + 1)
 446 /* v_mode for stack-related opcodes.  */
 447 #define stack_v_mode            (const_1_mode + 1)
 448 /* non-quad operand size depends on prefixes */
 449 #define z_mode                  (stack_v_mode + 1)
 450 /* 16-byte operand */
 451 #define o_mode                  (z_mode + 1)
 452 /* registers like dq_mode, memory like b_mode.  */
 453 #define dqb_mode                (o_mode + 1)
 454 /* registers like dq_mode, memory like d_mode.  */
 455 #define dqd_mode                (dqb_mode + 1)
 456 /* normal vex mode */
 457 #define vex_mode                (dqd_mode + 1)
 458 /* 128bit vex mode */
 459 #define vex128_mode             (vex_mode + 1)
 460 /* 256bit vex mode */
 461 #define vex256_mode             (vex128_mode + 1)
 462
 463 #define es_reg                  (vex256_mode + 1)
 464 #define cs_reg                  (es_reg + 1)
 465 #define ss_reg                  (cs_reg + 1)
 466 #define ds_reg                  (ss_reg + 1)
 467 #define fs_reg                  (ds_reg + 1)
 468 #define gs_reg                  (fs_reg + 1)
 469
 470 #define eAX_reg                 (gs_reg + 1)
 471 #define eCX_reg                 (eAX_reg + 1)
 472 #define eDX_reg                 (eCX_reg + 1)
 473 #define eBX_reg                 (eDX_reg + 1)
 474 #define eSP_reg                 (eBX_reg + 1)
 475 #define eBP_reg                 (eSP_reg + 1)
 476 #define eSI_reg                 (eBP_reg + 1)
 477 #define eDI_reg                 (eSI_reg + 1)
 478
 479 #define al_reg                  (eDI_reg + 1)
 480 #define cl_reg                  (al_reg + 1)
 481 #define dl_reg                  (cl_reg + 1)
 482 #define bl_reg                  (dl_reg + 1)
 483 #define ah_reg                  (bl_reg + 1)
 484 #define ch_reg                  (ah_reg + 1)
 485 #define dh_reg                  (ch_reg + 1)
 486 #define bh_reg                  (dh_reg + 1)
 487
 488 #define ax_reg                  (bh_reg + 1)
 489 #define cx_reg                  (ax_reg + 1)
 490 #define dx_reg                  (cx_reg + 1)
 491 #define bx_reg                  (dx_reg + 1)
 492 #define sp_reg                  (bx_reg + 1)
 493 #define bp_reg                  (sp_reg + 1)
 494 #define si_reg                  (bp_reg + 1)
 495 #define di_reg                  (si_reg + 1)
 496
 497 #define rAX_reg                 (di_reg + 1)
 498 #define rCX_reg                 (rAX_reg + 1)
 499 #define rDX_reg                 (rCX_reg + 1)
 500 #define rBX_reg                 (rDX_reg + 1)
 501 #define rSP_reg                 (rBX_reg + 1)
 502 #define rBP_reg                 (rSP_reg + 1)
 503 #define rSI_reg                 (rBP_reg + 1)
 504 #define rDI_reg                 (rSI_reg + 1)
 505
 506 #define z_mode_ax_reg           (rDI_reg + 1)
 507 #define indir_dx_reg            (z_mode_ax_reg + 1)
 508
 509 #define MAX_BYTEMODE    indir_dx_reg
 510
 511 /* Flags that are OR'ed into the bytemode field to pass extra
 512    information.  */
 513 #define DREX_OC1                0x10000 /* OC1 bit set */
 514 #define DREX_NO_OC0             0x20000 /* OC0 bit not used */
 515 #define DREX_MASK               0x40000 /* mask to delete */
 516
 517 #if MAX_BYTEMODE >= DREX_OC1
 518 #error MAX_BYTEMODE must be less than DREX_OC1
 519 #endif
 520
 521 #define FLOATCODE               1
 522 #define USE_REG_TABLE           (FLOATCODE + 1)
 523 #define USE_MOD_TABLE           (USE_REG_TABLE + 1)
 524 #define USE_RM_TABLE            (USE_MOD_TABLE + 1)
 525 #define USE_PREFIX_TABLE        (USE_RM_TABLE + 1)
 526 #define USE_X86_64_TABLE        (USE_PREFIX_TABLE + 1)
 527 #define USE_3BYTE_TABLE         (USE_X86_64_TABLE + 1)
 528 #define USE_VEX_C4_TABLE        (USE_3BYTE_TABLE + 1)
 529 #define USE_VEX_C5_TABLE        (USE_VEX_C4_TABLE + 1)
 530 #define USE_VEX_LEN_TABLE       (USE_VEX_C5_TABLE + 1)
 531
 532 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 533
 534 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 535 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 536 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 537 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 538 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 539 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 540 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 541 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 542 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 543 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 544
 545 #define REG_80                  0
 546 #define REG_81                  (REG_80 + 1)
 547 #define REG_82                  (REG_81 + 1)
 548 #define REG_8F                  (REG_82 + 1)
 549 #define REG_C0                  (REG_8F + 1)
 550 #define REG_C1                  (REG_C0 + 1)
 551 #define REG_C6                  (REG_C1 + 1)
 552 #define REG_C7                  (REG_C6 + 1)
 553 #define REG_D0                  (REG_C7 + 1)
 554 #define REG_D1                  (REG_D0 + 1)
 555 #define REG_D2                  (REG_D1 + 1)
 556 #define REG_D3                  (REG_D2 + 1)
 557 #define REG_F6                  (REG_D3 + 1)
 558 #define REG_F7                  (REG_F6 + 1)
 559 #define REG_FE                  (REG_F7 + 1)
 560 #define REG_FF                  (REG_FE + 1)
 561 #define REG_0F00                (REG_FF + 1)
 562 #define REG_0F01                (REG_0F00 + 1)
 563 #define REG_0F0D                (REG_0F01 + 1)
 564 #define REG_0F18                (REG_0F0D + 1)
 565 #define REG_0F71                (REG_0F18 + 1)
 566 #define REG_0F72                (REG_0F71 + 1)
 567 #define REG_0F73                (REG_0F72 + 1)
 568 #define REG_0FA6                (REG_0F73 + 1)
 569 #define REG_0FA7                (REG_0FA6 + 1)
 570 #define REG_0FAE                (REG_0FA7 + 1)
 571 #define REG_0FBA                (REG_0FAE + 1)
 572 #define REG_0FC7                (REG_0FBA + 1)
 573 #define REG_VEX_71              (REG_0FC7 + 1)
 574 #define REG_VEX_72              (REG_VEX_71 + 1)
 575 #define REG_VEX_73              (REG_VEX_72 + 1)
 576 #define REG_VEX_AE              (REG_VEX_73 + 1)
 577
 578 #define MOD_8D                  0
 579 #define MOD_0F01_REG_0          (MOD_8D + 1)
 580 #define MOD_0F01_REG_1          (MOD_0F01_REG_0 + 1)
 581 #define MOD_0F01_REG_2          (MOD_0F01_REG_1 + 1)
 582 #define MOD_0F01_REG_3          (MOD_0F01_REG_2 + 1)
 583 #define MOD_0F01_REG_7          (MOD_0F01_REG_3 + 1)
 584 #define MOD_0F12_PREFIX_0       (MOD_0F01_REG_7 + 1)
 585 #define MOD_0F13                (MOD_0F12_PREFIX_0 + 1)
 586 #define MOD_0F16_PREFIX_0       (MOD_0F13 + 1)
 587 #define MOD_0F17                (MOD_0F16_PREFIX_0 + 1)
 588 #define MOD_0F18_REG_0          (MOD_0F17 + 1)
 589 #define MOD_0F18_REG_1          (MOD_0F18_REG_0 + 1)
 590 #define MOD_0F18_REG_2          (MOD_0F18_REG_1 + 1)
 591 #define MOD_0F18_REG_3          (MOD_0F18_REG_2 + 1)
 592 #define MOD_0F20                (MOD_0F18_REG_3 + 1)
 593 #define MOD_0F21                (MOD_0F20 + 1)
 594 #define MOD_0F22                (MOD_0F21 + 1)
 595 #define MOD_0F23                (MOD_0F22 + 1)
 596 #define MOD_0F24                (MOD_0F23 + 1)
 597 #define MOD_0F26                (MOD_0F24 + 1)
 598 #define MOD_0F2B_PREFIX_0       (MOD_0F26 + 1)
 599 #define MOD_0F2B_PREFIX_1       (MOD_0F2B_PREFIX_0 + 1)
 600 #define MOD_0F2B_PREFIX_2       (MOD_0F2B_PREFIX_1 + 1)
 601 #define MOD_0F2B_PREFIX_3       (MOD_0F2B_PREFIX_2 + 1)
 602 #define MOD_0F51                (MOD_0F2B_PREFIX_3 + 1)
 603 #define MOD_0F71_REG_2          (MOD_0F51 + 1)
 604 #define MOD_0F71_REG_4          (MOD_0F71_REG_2 + 1)
 605 #define MOD_0F71_REG_6          (MOD_0F71_REG_4 + 1)
 606 #define MOD_0F72_REG_2          (MOD_0F71_REG_6 + 1)
 607 #define MOD_0F72_REG_4          (MOD_0F72_REG_2 + 1)
 608 #define MOD_0F72_REG_6          (MOD_0F72_REG_4 + 1)
 609 #define MOD_0F73_REG_2          (MOD_0F72_REG_6 + 1)
 610 #define MOD_0F73_REG_3          (MOD_0F73_REG_2 + 1)
 611 #define MOD_0F73_REG_6          (MOD_0F73_REG_3 + 1)
 612 #define MOD_0F73_REG_7          (MOD_0F73_REG_6 + 1)
 613 #define MOD_0FAE_REG_0          (MOD_0F73_REG_7 + 1)
 614 #define MOD_0FAE_REG_1          (MOD_0FAE_REG_0 + 1)
 615 #define MOD_0FAE_REG_2          (MOD_0FAE_REG_1 + 1)
 616 #define MOD_0FAE_REG_3          (MOD_0FAE_REG_2 + 1)
 617 #define MOD_0FAE_REG_4          (MOD_0FAE_REG_3 + 1)
 618 #define MOD_0FAE_REG_5          (MOD_0FAE_REG_4 + 1)
 619 #define MOD_0FAE_REG_6          (MOD_0FAE_REG_5 + 1)
 620 #define MOD_0FAE_REG_7          (MOD_0FAE_REG_6 + 1)
 621 #define MOD_0FB2                (MOD_0FAE_REG_7 + 1)
 622 #define MOD_0FB4                (MOD_0FB2 + 1)
 623 #define MOD_0FB5                (MOD_0FB4 + 1)
 624 #define MOD_0FC7_REG_6          (MOD_0FB5 + 1)
 625 #define MOD_0FC7_REG_7          (MOD_0FC7_REG_6 + 1)
 626 #define MOD_0FD7                (MOD_0FC7_REG_7 + 1)
 627 #define MOD_0FE7_PREFIX_2       (MOD_0FD7 + 1)
 628 #define MOD_0FF0_PREFIX_3       (MOD_0FE7_PREFIX_2 + 1)
 629 #define MOD_0F382A_PREFIX_2     (MOD_0FF0_PREFIX_3 + 1)
 630 #define MOD_62_32BIT            (MOD_0F382A_PREFIX_2 + 1)
 631 #define MOD_C4_32BIT            (MOD_62_32BIT + 1)
 632 #define MOD_C5_32BIT            (MOD_C4_32BIT + 1)
 633 #define MOD_VEX_12_PREFIX_0     (MOD_C5_32BIT + 1)
 634 #define MOD_VEX_13              (MOD_VEX_12_PREFIX_0 + 1)
 635 #define MOD_VEX_16_PREFIX_0     (MOD_VEX_13 + 1)
 636 #define MOD_VEX_17              (MOD_VEX_16_PREFIX_0 + 1)
 637 #define MOD_VEX_2B              (MOD_VEX_17 + 1)
 638 #define MOD_VEX_51              (MOD_VEX_2B + 1)
 639 #define MOD_VEX_71_REG_2        (MOD_VEX_51 + 1)
 640 #define MOD_VEX_71_REG_4        (MOD_VEX_71_REG_2 + 1)
 641 #define MOD_VEX_71_REG_6        (MOD_VEX_71_REG_4 + 1)
 642 #define MOD_VEX_72_REG_2        (MOD_VEX_71_REG_6 + 1)
 643 #define MOD_VEX_72_REG_4        (MOD_VEX_72_REG_2 + 1)
 644 #define MOD_VEX_72_REG_6        (MOD_VEX_72_REG_4 + 1)
 645 #define MOD_VEX_73_REG_2        (MOD_VEX_72_REG_6 + 1)
 646 #define MOD_VEX_73_REG_3        (MOD_VEX_73_REG_2 + 1)
 647 #define MOD_VEX_73_REG_6        (MOD_VEX_73_REG_3 + 1)
 648 #define MOD_VEX_73_REG_7        (MOD_VEX_73_REG_6 + 1)
 649 #define MOD_VEX_AE_REG_2        (MOD_VEX_73_REG_7 + 1)
 650 #define MOD_VEX_AE_REG_3        (MOD_VEX_AE_REG_2 + 1)
 651 #define MOD_VEX_D7_PREFIX_2     (MOD_VEX_AE_REG_3 + 1)
 652 #define MOD_VEX_E7_PREFIX_2     (MOD_VEX_D7_PREFIX_2 + 1)
 653 #define MOD_VEX_F0_PREFIX_3     (MOD_VEX_E7_PREFIX_2 + 1)
 654 #define MOD_VEX_3818_PREFIX_2   (MOD_VEX_F0_PREFIX_3 + 1)
 655 #define MOD_VEX_3819_PREFIX_2   (MOD_VEX_3818_PREFIX_2 + 1)
 656 #define MOD_VEX_381A_PREFIX_2   (MOD_VEX_3819_PREFIX_2 + 1)
 657 #define MOD_VEX_382A_PREFIX_2   (MOD_VEX_381A_PREFIX_2 + 1)
 658 #define MOD_VEX_382C_PREFIX_2   (MOD_VEX_382A_PREFIX_2 + 1)
 659 #define MOD_VEX_382D_PREFIX_2   (MOD_VEX_382C_PREFIX_2 + 1)
 660 #define MOD_VEX_382E_PREFIX_2   (MOD_VEX_382D_PREFIX_2 + 1)
 661 #define MOD_VEX_382F_PREFIX_2   (MOD_VEX_382E_PREFIX_2 + 1)
 662
 663 #define RM_0F01_REG_0           0
 664 #define RM_0F01_REG_1           (RM_0F01_REG_0 + 1)
 665 #define RM_0F01_REG_2           (RM_0F01_REG_1 + 1)
 666 #define RM_0F01_REG_3           (RM_0F01_REG_2 + 1)
 667 #define RM_0F01_REG_7           (RM_0F01_REG_3 + 1)
 668 #define RM_0FAE_REG_5           (RM_0F01_REG_7 + 1)
 669 #define RM_0FAE_REG_6           (RM_0FAE_REG_5 + 1)
 670 #define RM_0FAE_REG_7           (RM_0FAE_REG_6 + 1)
 671
 672 #define PREFIX_90               0
 673 #define PREFIX_0F10             (PREFIX_90 + 1)
 674 #define PREFIX_0F11             (PREFIX_0F10 + 1)
 675 #define PREFIX_0F12             (PREFIX_0F11 + 1)
 676 #define PREFIX_0F16             (PREFIX_0F12 + 1)
 677 #define PREFIX_0F2A             (PREFIX_0F16 + 1)
 678 #define PREFIX_0F2B             (PREFIX_0F2A + 1)
 679 #define PREFIX_0F2C             (PREFIX_0F2B + 1)
 680 #define PREFIX_0F2D             (PREFIX_0F2C + 1)
 681 #define PREFIX_0F2E             (PREFIX_0F2D + 1)
 682 #define PREFIX_0F2F             (PREFIX_0F2E + 1)
 683 #define PREFIX_0F51             (PREFIX_0F2F + 1)
 684 #define PREFIX_0F52             (PREFIX_0F51 + 1)
 685 #define PREFIX_0F53             (PREFIX_0F52 + 1)
 686 #define PREFIX_0F58             (PREFIX_0F53 + 1)
 687 #define PREFIX_0F59             (PREFIX_0F58 + 1)
 688 #define PREFIX_0F5A             (PREFIX_0F59 + 1)
 689 #define PREFIX_0F5B             (PREFIX_0F5A + 1)
 690 #define PREFIX_0F5C             (PREFIX_0F5B + 1)
 691 #define PREFIX_0F5D             (PREFIX_0F5C + 1)
 692 #define PREFIX_0F5E             (PREFIX_0F5D + 1)
 693 #define PREFIX_0F5F             (PREFIX_0F5E + 1)
 694 #define PREFIX_0F60             (PREFIX_0F5F + 1)
 695 #define PREFIX_0F61             (PREFIX_0F60 + 1)
 696 #define PREFIX_0F62             (PREFIX_0F61 + 1)
 697 #define PREFIX_0F6C             (PREFIX_0F62 + 1)
 698 #define PREFIX_0F6D             (PREFIX_0F6C + 1)
 699 #define PREFIX_0F6F             (PREFIX_0F6D + 1)
 700 #define PREFIX_0F70             (PREFIX_0F6F + 1)
 701 #define PREFIX_0F73_REG_3       (PREFIX_0F70 + 1)
 702 #define PREFIX_0F73_REG_7       (PREFIX_0F73_REG_3 + 1)
 703 #define PREFIX_0F78             (PREFIX_0F73_REG_7 + 1)
 704 #define PREFIX_0F79             (PREFIX_0F78 + 1)
 705 #define PREFIX_0F7C             (PREFIX_0F79 + 1)
 706 #define PREFIX_0F7D             (PREFIX_0F7C + 1)
 707 #define PREFIX_0F7E             (PREFIX_0F7D + 1)
 708 #define PREFIX_0F7F             (PREFIX_0F7E + 1)
 709 #define PREFIX_0FB8             (PREFIX_0F7F + 1)
 710 #define PREFIX_0FBD             (PREFIX_0FB8 + 1)
 711 #define PREFIX_0FC2             (PREFIX_0FBD + 1)
 712 #define PREFIX_0FC3             (PREFIX_0FC2 + 1)
 713 #define PREFIX_0FC7_REG_6       (PREFIX_0FC3 + 1)
 714 #define PREFIX_0FD0             (PREFIX_0FC7_REG_6 + 1)
 715 #define PREFIX_0FD6             (PREFIX_0FD0 + 1)
 716 #define PREFIX_0FE6             (PREFIX_0FD6 + 1)
 717 #define PREFIX_0FE7             (PREFIX_0FE6 + 1)
 718 #define PREFIX_0FF0             (PREFIX_0FE7 + 1)
 719 #define PREFIX_0FF7             (PREFIX_0FF0 + 1)
 720 #define PREFIX_0F3810           (PREFIX_0FF7 + 1)
 721 #define PREFIX_0F3814           (PREFIX_0F3810 + 1)
 722 #define PREFIX_0F3815           (PREFIX_0F3814 + 1)
 723 #define PREFIX_0F3817           (PREFIX_0F3815 + 1)
 724 #define PREFIX_0F3820           (PREFIX_0F3817 + 1)
 725 #define PREFIX_0F3821           (PREFIX_0F3820 + 1)
 726 #define PREFIX_0F3822           (PREFIX_0F3821 + 1)
 727 #define PREFIX_0F3823           (PREFIX_0F3822 + 1)
 728 #define PREFIX_0F3824           (PREFIX_0F3823 + 1)
 729 #define PREFIX_0F3825           (PREFIX_0F3824 + 1)
 730 #define PREFIX_0F3828           (PREFIX_0F3825 + 1)
 731 #define PREFIX_0F3829           (PREFIX_0F3828 + 1)
 732 #define PREFIX_0F382A           (PREFIX_0F3829 + 1)
 733 #define PREFIX_0F382B           (PREFIX_0F382A + 1)
 734 #define PREFIX_0F3830           (PREFIX_0F382B + 1)
 735 #define PREFIX_0F3831           (PREFIX_0F3830 + 1)
 736 #define PREFIX_0F3832           (PREFIX_0F3831 + 1)
 737 #define PREFIX_0F3833           (PREFIX_0F3832 + 1)
 738 #define PREFIX_0F3834           (PREFIX_0F3833 + 1)
 739 #define PREFIX_0F3835           (PREFIX_0F3834 + 1)
 740 #define PREFIX_0F3837           (PREFIX_0F3835 + 1)
 741 #define PREFIX_0F3838           (PREFIX_0F3837 + 1)
 742 #define PREFIX_0F3839           (PREFIX_0F3838 + 1)
 743 #define PREFIX_0F383A           (PREFIX_0F3839 + 1)
 744 #define PREFIX_0F383B           (PREFIX_0F383A + 1)
 745 #define PREFIX_0F383C           (PREFIX_0F383B + 1)
 746 #define PREFIX_0F383D           (PREFIX_0F383C + 1)
 747 #define PREFIX_0F383E           (PREFIX_0F383D + 1)
 748 #define PREFIX_0F383F           (PREFIX_0F383E + 1)
 749 #define PREFIX_0F3840           (PREFIX_0F383F + 1)
 750 #define PREFIX_0F3841           (PREFIX_0F3840 + 1)
 751 #define PREFIX_0F3880           (PREFIX_0F3841 + 1)
 752 #define PREFIX_0F3881           (PREFIX_0F3880 + 1)
 753 #define PREFIX_0F38DB           (PREFIX_0F3881 + 1)
 754 #define PREFIX_0F38DC           (PREFIX_0F38DB + 1)
 755 #define PREFIX_0F38DD           (PREFIX_0F38DC + 1)
 756 #define PREFIX_0F38DE           (PREFIX_0F38DD + 1)
 757 #define PREFIX_0F38DF           (PREFIX_0F38DE + 1)
 758 #define PREFIX_0F38F0           (PREFIX_0F38DF + 1)
 759 #define PREFIX_0F38F1           (PREFIX_0F38F0 + 1)
 760 #define PREFIX_0F3A08           (PREFIX_0F38F1 + 1)
 761 #define PREFIX_0F3A09           (PREFIX_0F3A08 + 1)
 762 #define PREFIX_0F3A0A           (PREFIX_0F3A09 + 1)
 763 #define PREFIX_0F3A0B           (PREFIX_0F3A0A + 1)
 764 #define PREFIX_0F3A0C           (PREFIX_0F3A0B + 1)
 765 #define PREFIX_0F3A0D           (PREFIX_0F3A0C + 1)
 766 #define PREFIX_0F3A0E           (PREFIX_0F3A0D + 1)
 767 #define PREFIX_0F3A14           (PREFIX_0F3A0E + 1)
 768 #define PREFIX_0F3A15           (PREFIX_0F3A14 + 1)
 769 #define PREFIX_0F3A16           (PREFIX_0F3A15 + 1)
 770 #define PREFIX_0F3A17           (PREFIX_0F3A16 + 1)
 771 #define PREFIX_0F3A20           (PREFIX_0F3A17 + 1)
 772 #define PREFIX_0F3A21           (PREFIX_0F3A20 + 1)
 773 #define PREFIX_0F3A22           (PREFIX_0F3A21 + 1)
 774 #define PREFIX_0F3A40           (PREFIX_0F3A22 + 1)
 775 #define PREFIX_0F3A41           (PREFIX_0F3A40 + 1)
 776 #define PREFIX_0F3A42           (PREFIX_0F3A41 + 1)
 777 #define PREFIX_0F3A44           (PREFIX_0F3A42 + 1)
 778 #define PREFIX_0F3A60           (PREFIX_0F3A44 + 1)
 779 #define PREFIX_0F3A61           (PREFIX_0F3A60 + 1)
 780 #define PREFIX_0F3A62           (PREFIX_0F3A61 + 1)
 781 #define PREFIX_0F3A63           (PREFIX_0F3A62 + 1)
 782 #define PREFIX_0F3ADF           (PREFIX_0F3A63 + 1)
 783 #define PREFIX_VEX_10           (PREFIX_0F3ADF + 1)
 784 #define PREFIX_VEX_11           (PREFIX_VEX_10 + 1)
 785 #define PREFIX_VEX_12           (PREFIX_VEX_11 + 1)
 786 #define PREFIX_VEX_16           (PREFIX_VEX_12 + 1)
 787 #define PREFIX_VEX_2A           (PREFIX_VEX_16 + 1)
 788 #define PREFIX_VEX_2C           (PREFIX_VEX_2A + 1)
 789 #define PREFIX_VEX_2D           (PREFIX_VEX_2C + 1)
 790 #define PREFIX_VEX_2E           (PREFIX_VEX_2D + 1)
 791 #define PREFIX_VEX_2F           (PREFIX_VEX_2E + 1)
 792 #define PREFIX_VEX_51           (PREFIX_VEX_2F + 1)
 793 #define PREFIX_VEX_52           (PREFIX_VEX_51 + 1)
 794 #define PREFIX_VEX_53           (PREFIX_VEX_52 + 1)
 795 #define PREFIX_VEX_58           (PREFIX_VEX_53 + 1)
 796 #define PREFIX_VEX_59           (PREFIX_VEX_58 + 1)
 797 #define PREFIX_VEX_5A           (PREFIX_VEX_59 + 1)
 798 #define PREFIX_VEX_5B           (PREFIX_VEX_5A + 1)
 799 #define PREFIX_VEX_5C           (PREFIX_VEX_5B + 1)
 800 #define PREFIX_VEX_5D           (PREFIX_VEX_5C + 1)
 801 #define PREFIX_VEX_5E           (PREFIX_VEX_5D + 1)
 802 #define PREFIX_VEX_5F           (PREFIX_VEX_5E + 1)
 803 #define PREFIX_VEX_60           (PREFIX_VEX_5F + 1)
 804 #define PREFIX_VEX_61           (PREFIX_VEX_60 + 1)
 805 #define PREFIX_VEX_62           (PREFIX_VEX_61 + 1)
 806 #define PREFIX_VEX_63           (PREFIX_VEX_62 + 1)
 807 #define PREFIX_VEX_64           (PREFIX_VEX_63 + 1)
 808 #define PREFIX_VEX_65           (PREFIX_VEX_64 + 1)
 809 #define PREFIX_VEX_66           (PREFIX_VEX_65 + 1)
 810 #define PREFIX_VEX_67           (PREFIX_VEX_66 + 1)
 811 #define PREFIX_VEX_68           (PREFIX_VEX_67 + 1)
 812 #define PREFIX_VEX_69           (PREFIX_VEX_68 + 1)
 813 #define PREFIX_VEX_6A           (PREFIX_VEX_69 + 1)
 814 #define PREFIX_VEX_6B           (PREFIX_VEX_6A + 1)
 815 #define PREFIX_VEX_6C           (PREFIX_VEX_6B + 1)
 816 #define PREFIX_VEX_6D           (PREFIX_VEX_6C + 1)
 817 #define PREFIX_VEX_6E           (PREFIX_VEX_6D + 1)
 818 #define PREFIX_VEX_6F           (PREFIX_VEX_6E + 1)
 819 #define PREFIX_VEX_70           (PREFIX_VEX_6F + 1)
 820 #define PREFIX_VEX_71_REG_2     (PREFIX_VEX_70 + 1)
 821 #define PREFIX_VEX_71_REG_4     (PREFIX_VEX_71_REG_2 + 1)
 822 #define PREFIX_VEX_71_REG_6     (PREFIX_VEX_71_REG_4 + 1)
 823 #define PREFIX_VEX_72_REG_2     (PREFIX_VEX_71_REG_6 + 1)
 824 #define PREFIX_VEX_72_REG_4     (PREFIX_VEX_72_REG_2 + 1)
 825 #define PREFIX_VEX_72_REG_6     (PREFIX_VEX_72_REG_4 + 1)
 826 #define PREFIX_VEX_73_REG_2     (PREFIX_VEX_72_REG_6 + 1)
 827 #define PREFIX_VEX_73_REG_3     (PREFIX_VEX_73_REG_2 + 1)
 828 #define PREFIX_VEX_73_REG_6     (PREFIX_VEX_73_REG_3 + 1)
 829 #define PREFIX_VEX_73_REG_7     (PREFIX_VEX_73_REG_6 + 1)
 830 #define PREFIX_VEX_74           (PREFIX_VEX_73_REG_7 + 1)
 831 #define PREFIX_VEX_75           (PREFIX_VEX_74 + 1)
 832 #define PREFIX_VEX_76           (PREFIX_VEX_75 + 1)
 833 #define PREFIX_VEX_77           (PREFIX_VEX_76 + 1)
 834 #define PREFIX_VEX_7C           (PREFIX_VEX_77 + 1)
 835 #define PREFIX_VEX_7D           (PREFIX_VEX_7C + 1)
 836 #define PREFIX_VEX_7E           (PREFIX_VEX_7D + 1)
 837 #define PREFIX_VEX_7F           (PREFIX_VEX_7E + 1)
 838 #define PREFIX_VEX_C2           (PREFIX_VEX_7F + 1)
 839 #define PREFIX_VEX_C4           (PREFIX_VEX_C2 + 1)
 840 #define PREFIX_VEX_C5           (PREFIX_VEX_C4 + 1)
 841 #define PREFIX_VEX_D0           (PREFIX_VEX_C5 + 1)
 842 #define PREFIX_VEX_D1           (PREFIX_VEX_D0 + 1)
 843 #define PREFIX_VEX_D2           (PREFIX_VEX_D1 + 1)
 844 #define PREFIX_VEX_D3           (PREFIX_VEX_D2 + 1)
 845 #define PREFIX_VEX_D4           (PREFIX_VEX_D3 + 1)
 846 #define PREFIX_VEX_D5           (PREFIX_VEX_D4 + 1)
 847 #define PREFIX_VEX_D6           (PREFIX_VEX_D5 + 1)
 848 #define PREFIX_VEX_D7           (PREFIX_VEX_D6 + 1)
 849 #define PREFIX_VEX_D8           (PREFIX_VEX_D7 + 1)
 850 #define PREFIX_VEX_D9           (PREFIX_VEX_D8 + 1)
 851 #define PREFIX_VEX_DA           (PREFIX_VEX_D9 + 1)
 852 #define PREFIX_VEX_DB           (PREFIX_VEX_DA + 1)
 853 #define PREFIX_VEX_DC           (PREFIX_VEX_DB + 1)
 854 #define PREFIX_VEX_DD           (PREFIX_VEX_DC + 1)
 855 #define PREFIX_VEX_DE           (PREFIX_VEX_DD + 1)
 856 #define PREFIX_VEX_DF           (PREFIX_VEX_DE + 1)
 857 #define PREFIX_VEX_E0           (PREFIX_VEX_DF + 1)
 858 #define PREFIX_VEX_E1           (PREFIX_VEX_E0 + 1)
 859 #define PREFIX_VEX_E2           (PREFIX_VEX_E1 + 1)
 860 #define PREFIX_VEX_E3           (PREFIX_VEX_E2 + 1)
 861 #define PREFIX_VEX_E4           (PREFIX_VEX_E3 + 1)
 862 #define PREFIX_VEX_E5           (PREFIX_VEX_E4 + 1)
 863 #define PREFIX_VEX_E6           (PREFIX_VEX_E5 + 1)
 864 #define PREFIX_VEX_E7           (PREFIX_VEX_E6 + 1)
 865 #define PREFIX_VEX_E8           (PREFIX_VEX_E7 + 1)
 866 #define PREFIX_VEX_E9           (PREFIX_VEX_E8 + 1)
 867 #define PREFIX_VEX_EA           (PREFIX_VEX_E9 + 1)
 868 #define PREFIX_VEX_EB           (PREFIX_VEX_EA + 1)
 869 #define PREFIX_VEX_EC           (PREFIX_VEX_EB + 1)
 870 #define PREFIX_VEX_ED           (PREFIX_VEX_EC + 1)
 871 #define PREFIX_VEX_EE           (PREFIX_VEX_ED + 1)
 872 #define PREFIX_VEX_EF           (PREFIX_VEX_EE + 1)
 873 #define PREFIX_VEX_F0           (PREFIX_VEX_EF + 1)
 874 #define PREFIX_VEX_F1           (PREFIX_VEX_F0 + 1)
 875 #define PREFIX_VEX_F2           (PREFIX_VEX_F1 + 1)
 876 #define PREFIX_VEX_F3           (PREFIX_VEX_F2 + 1)
 877 #define PREFIX_VEX_F4           (PREFIX_VEX_F3 + 1)
 878 #define PREFIX_VEX_F5           (PREFIX_VEX_F4 + 1)
 879 #define PREFIX_VEX_F6           (PREFIX_VEX_F5 + 1)
 880 #define PREFIX_VEX_F7           (PREFIX_VEX_F6 + 1)
 881 #define PREFIX_VEX_F8           (PREFIX_VEX_F7 + 1)
 882 #define PREFIX_VEX_F9           (PREFIX_VEX_F8 + 1)
 883 #define PREFIX_VEX_FA           (PREFIX_VEX_F9 + 1)
 884 #define PREFIX_VEX_FB           (PREFIX_VEX_FA + 1)
 885 #define PREFIX_VEX_FC           (PREFIX_VEX_FB + 1)
 886 #define PREFIX_VEX_FD           (PREFIX_VEX_FC + 1)
 887 #define PREFIX_VEX_FE           (PREFIX_VEX_FD + 1)
 888 #define PREFIX_VEX_3800         (PREFIX_VEX_FE + 1)
 889 #define PREFIX_VEX_3801         (PREFIX_VEX_3800 + 1)
 890 #define PREFIX_VEX_3802         (PREFIX_VEX_3801 + 1)
 891 #define PREFIX_VEX_3803         (PREFIX_VEX_3802 + 1)
 892 #define PREFIX_VEX_3804         (PREFIX_VEX_3803 + 1)
 893 #define PREFIX_VEX_3805         (PREFIX_VEX_3804 + 1)
 894 #define PREFIX_VEX_3806         (PREFIX_VEX_3805 + 1)
 895 #define PREFIX_VEX_3807         (PREFIX_VEX_3806 + 1)
 896 #define PREFIX_VEX_3808         (PREFIX_VEX_3807 + 1)
 897 #define PREFIX_VEX_3809         (PREFIX_VEX_3808 + 1)
 898 #define PREFIX_VEX_380A         (PREFIX_VEX_3809 + 1)
 899 #define PREFIX_VEX_380B         (PREFIX_VEX_380A + 1)
 900 #define PREFIX_VEX_380C         (PREFIX_VEX_380B + 1)
 901 #define PREFIX_VEX_380D         (PREFIX_VEX_380C + 1)
 902 #define PREFIX_VEX_380E         (PREFIX_VEX_380D + 1)
 903 #define PREFIX_VEX_380F         (PREFIX_VEX_380E + 1)
 904 #define PREFIX_VEX_3817         (PREFIX_VEX_380F + 1)
 905 #define PREFIX_VEX_3818         (PREFIX_VEX_3817 + 1)
 906 #define PREFIX_VEX_3819         (PREFIX_VEX_3818 + 1)
 907 #define PREFIX_VEX_381A         (PREFIX_VEX_3819 + 1)
 908 #define PREFIX_VEX_381C         (PREFIX_VEX_381A + 1)
 909 #define PREFIX_VEX_381D         (PREFIX_VEX_381C + 1)
 910 #define PREFIX_VEX_381E         (PREFIX_VEX_381D + 1)
 911 #define PREFIX_VEX_3820         (PREFIX_VEX_381E + 1)
 912 #define PREFIX_VEX_3821         (PREFIX_VEX_3820 + 1)
 913 #define PREFIX_VEX_3822         (PREFIX_VEX_3821 + 1)
 914 #define PREFIX_VEX_3823         (PREFIX_VEX_3822 + 1)
 915 #define PREFIX_VEX_3824         (PREFIX_VEX_3823 + 1)
 916 #define PREFIX_VEX_3825         (PREFIX_VEX_3824 + 1)
 917 #define PREFIX_VEX_3828         (PREFIX_VEX_3825 + 1)
 918 #define PREFIX_VEX_3829         (PREFIX_VEX_3828 + 1)
 919 #define PREFIX_VEX_382A         (PREFIX_VEX_3829 + 1)
 920 #define PREFIX_VEX_382B         (PREFIX_VEX_382A + 1)
 921 #define PREFIX_VEX_382C         (PREFIX_VEX_382B + 1)
 922 #define PREFIX_VEX_382D         (PREFIX_VEX_382C + 1)
 923 #define PREFIX_VEX_382E         (PREFIX_VEX_382D + 1)
 924 #define PREFIX_VEX_382F         (PREFIX_VEX_382E + 1)
 925 #define PREFIX_VEX_3830         (PREFIX_VEX_382F + 1)
 926 #define PREFIX_VEX_3831         (PREFIX_VEX_3830 + 1)
 927 #define PREFIX_VEX_3832         (PREFIX_VEX_3831 + 1)
 928 #define PREFIX_VEX_3833         (PREFIX_VEX_3832 + 1)
 929 #define PREFIX_VEX_3834         (PREFIX_VEX_3833 + 1)
 930 #define PREFIX_VEX_3835         (PREFIX_VEX_3834 + 1)
 931 #define PREFIX_VEX_3837         (PREFIX_VEX_3835 + 1)
 932 #define PREFIX_VEX_3838         (PREFIX_VEX_3837 + 1)
 933 #define PREFIX_VEX_3839         (PREFIX_VEX_3838 + 1)
 934 #define PREFIX_VEX_383A         (PREFIX_VEX_3839 + 1)
 935 #define PREFIX_VEX_383B         (PREFIX_VEX_383A + 1)
 936 #define PREFIX_VEX_383C         (PREFIX_VEX_383B + 1)
 937 #define PREFIX_VEX_383D         (PREFIX_VEX_383C + 1)
 938 #define PREFIX_VEX_383E         (PREFIX_VEX_383D + 1)
 939 #define PREFIX_VEX_383F         (PREFIX_VEX_383E + 1)
 940 #define PREFIX_VEX_3840         (PREFIX_VEX_383F + 1)
 941 #define PREFIX_VEX_3841         (PREFIX_VEX_3840 + 1)
 942 #define PREFIX_VEX_38DB         (PREFIX_VEX_3841 + 1)
 943 #define PREFIX_VEX_38DC         (PREFIX_VEX_38DB + 1)
 944 #define PREFIX_VEX_38DD         (PREFIX_VEX_38DC + 1)
 945 #define PREFIX_VEX_38DE         (PREFIX_VEX_38DD + 1)
 946 #define PREFIX_VEX_38DF         (PREFIX_VEX_38DE + 1)
 947 #define PREFIX_VEX_3A04         (PREFIX_VEX_38DF + 1)
 948 #define PREFIX_VEX_3A05         (PREFIX_VEX_3A04 + 1)
 949 #define PREFIX_VEX_3A06         (PREFIX_VEX_3A05 + 1)
 950 #define PREFIX_VEX_3A08         (PREFIX_VEX_3A06 + 1)
 951 #define PREFIX_VEX_3A09         (PREFIX_VEX_3A08 + 1)
 952 #define PREFIX_VEX_3A0A         (PREFIX_VEX_3A09 + 1)
 953 #define PREFIX_VEX_3A0B         (PREFIX_VEX_3A0A + 1)
 954 #define PREFIX_VEX_3A0C         (PREFIX_VEX_3A0B + 1)
 955 #define PREFIX_VEX_3A0D         (PREFIX_VEX_3A0C + 1)
 956 #define PREFIX_VEX_3A0E         (PREFIX_VEX_3A0D + 1)
 957 #define PREFIX_VEX_3A0F         (PREFIX_VEX_3A0E + 1)
 958 #define PREFIX_VEX_3A14         (PREFIX_VEX_3A0F + 1)
 959 #define PREFIX_VEX_3A15         (PREFIX_VEX_3A14 + 1)
 960 #define PREFIX_VEX_3A16         (PREFIX_VEX_3A15 + 1)
 961 #define PREFIX_VEX_3A17         (PREFIX_VEX_3A16 + 1)
 962 #define PREFIX_VEX_3A18         (PREFIX_VEX_3A17 + 1)
 963 #define PREFIX_VEX_3A19         (PREFIX_VEX_3A18 + 1)
 964 #define PREFIX_VEX_3A20         (PREFIX_VEX_3A19 + 1)
 965 #define PREFIX_VEX_3A21         (PREFIX_VEX_3A20 + 1)
 966 #define PREFIX_VEX_3A22         (PREFIX_VEX_3A21 + 1)
 967 #define PREFIX_VEX_3A40         (PREFIX_VEX_3A22 + 1)
 968 #define PREFIX_VEX_3A41         (PREFIX_VEX_3A40 + 1)
 969 #define PREFIX_VEX_3A42         (PREFIX_VEX_3A41 + 1)
 970 #define PREFIX_VEX_3A48         (PREFIX_VEX_3A42 + 1)
 971 #define PREFIX_VEX_3A49         (PREFIX_VEX_3A48 + 1)
 972 #define PREFIX_VEX_3A4A         (PREFIX_VEX_3A49 + 1)
 973 #define PREFIX_VEX_3A4B         (PREFIX_VEX_3A4A + 1)
 974 #define PREFIX_VEX_3A4C         (PREFIX_VEX_3A4B + 1)
 975 #define PREFIX_VEX_3A5C         (PREFIX_VEX_3A4C + 1)
 976 #define PREFIX_VEX_3A5D         (PREFIX_VEX_3A5C + 1)
 977 #define PREFIX_VEX_3A5E         (PREFIX_VEX_3A5D + 1)
 978 #define PREFIX_VEX_3A5F         (PREFIX_VEX_3A5E + 1)
 979 #define PREFIX_VEX_3A60         (PREFIX_VEX_3A5F + 1)
 980 #define PREFIX_VEX_3A61         (PREFIX_VEX_3A60 + 1)
 981 #define PREFIX_VEX_3A62         (PREFIX_VEX_3A61 + 1)
 982 #define PREFIX_VEX_3A63         (PREFIX_VEX_3A62 + 1)
 983 #define PREFIX_VEX_3A68         (PREFIX_VEX_3A63 + 1)
 984 #define PREFIX_VEX_3A69         (PREFIX_VEX_3A68 + 1)
 985 #define PREFIX_VEX_3A6A         (PREFIX_VEX_3A69 + 1)
 986 #define PREFIX_VEX_3A6B         (PREFIX_VEX_3A6A + 1)
 987 #define PREFIX_VEX_3A6C         (PREFIX_VEX_3A6B + 1)
 988 #define PREFIX_VEX_3A6D         (PREFIX_VEX_3A6C + 1)
 989 #define PREFIX_VEX_3A6E         (PREFIX_VEX_3A6D + 1)
 990 #define PREFIX_VEX_3A6F         (PREFIX_VEX_3A6E + 1)
 991 #define PREFIX_VEX_3A78         (PREFIX_VEX_3A6F + 1)
 992 #define PREFIX_VEX_3A79         (PREFIX_VEX_3A78 + 1)
 993 #define PREFIX_VEX_3A7A         (PREFIX_VEX_3A79 + 1)
 994 #define PREFIX_VEX_3A7B         (PREFIX_VEX_3A7A + 1)
 995 #define PREFIX_VEX_3A7C         (PREFIX_VEX_3A7B + 1)
 996 #define PREFIX_VEX_3A7D         (PREFIX_VEX_3A7C + 1)
 997 #define PREFIX_VEX_3A7E         (PREFIX_VEX_3A7D + 1)
 998 #define PREFIX_VEX_3A7F         (PREFIX_VEX_3A7E + 1)
 999 #define PREFIX_VEX_3ADF         (PREFIX_VEX_3A7F + 1)
1000
1001 #define X86_64_06               0
1002 #define X86_64_07               (X86_64_06 + 1)
1003 #define X86_64_0D               (X86_64_07 + 1)
1004 #define X86_64_16               (X86_64_0D + 1)
1005 #define X86_64_17               (X86_64_16 + 1)
1006 #define X86_64_1E               (X86_64_17 + 1)
1007 #define X86_64_1F               (X86_64_1E + 1)
1008 #define X86_64_27               (X86_64_1F + 1)
1009 #define X86_64_2F               (X86_64_27 + 1)
1010 #define X86_64_37               (X86_64_2F + 1)
1011 #define X86_64_3F               (X86_64_37 + 1)
1012 #define X86_64_60               (X86_64_3F + 1)
1013 #define X86_64_61               (X86_64_60 + 1)
1014 #define X86_64_62               (X86_64_61 + 1)
1015 #define X86_64_63               (X86_64_62 + 1)
1016 #define X86_64_6D               (X86_64_63 + 1)
1017 #define X86_64_6F               (X86_64_6D + 1)
1018 #define X86_64_9A               (X86_64_6F + 1)
1019 #define X86_64_C4               (X86_64_9A + 1)
1020 #define X86_64_C5               (X86_64_C4 + 1)
1021 #define X86_64_CE               (X86_64_C5 + 1)
1022 #define X86_64_D4               (X86_64_CE + 1)
1023 #define X86_64_D5               (X86_64_D4 + 1)
1024 #define X86_64_EA               (X86_64_D5 + 1)
1025 #define X86_64_0F01_REG_0       (X86_64_EA + 1)
1026 #define X86_64_0F01_REG_1       (X86_64_0F01_REG_0 + 1)
1027 #define X86_64_0F01_REG_2       (X86_64_0F01_REG_1 + 1)
1028 #define X86_64_0F01_REG_3       (X86_64_0F01_REG_2 + 1)
1029
1030 #define THREE_BYTE_0F24         0
1031 #define THREE_BYTE_0F25         (THREE_BYTE_0F24 + 1)
1032 #define THREE_BYTE_0F38         (THREE_BYTE_0F25 + 1)
1033 #define THREE_BYTE_0F3A         (THREE_BYTE_0F38 + 1)
1034 #define THREE_BYTE_0F7A         (THREE_BYTE_0F3A + 1)
1035 #define THREE_BYTE_0F7B         (THREE_BYTE_0F7A + 1)
1036
1037 #define VEX_0F                  0
1038 #define VEX_0F38                (VEX_0F + 1)
1039 #define VEX_0F3A                (VEX_0F38 + 1)
1040
1041 #define VEX_LEN_10_P_1  0
1042 #define VEX_LEN_10_P_3  (VEX_LEN_10_P_1 + 1)
1043 #define VEX_LEN_11_P_1  (VEX_LEN_10_P_3 + 1)
1044 #define VEX_LEN_11_P_3  (VEX_LEN_11_P_1 + 1)
1045 #define VEX_LEN_12_P_0_M_0      (VEX_LEN_11_P_3 + 1)
1046 #define VEX_LEN_12_P_0_M_1      (VEX_LEN_12_P_0_M_0 + 1)
1047 #define VEX_LEN_12_P_2  (VEX_LEN_12_P_0_M_1 + 1)
1048 #define VEX_LEN_13_M_0  (VEX_LEN_12_P_2 + 1)
1049 #define VEX_LEN_16_P_0_M_0      (VEX_LEN_13_M_0 + 1)
1050 #define VEX_LEN_16_P_0_M_1      (VEX_LEN_16_P_0_M_0 + 1)
1051 #define VEX_LEN_16_P_2  (VEX_LEN_16_P_0_M_1 + 1)
1052 #define VEX_LEN_17_M_0  (VEX_LEN_16_P_2 + 1)
1053 #define VEX_LEN_2A_P_1  (VEX_LEN_17_M_0 + 1)
1054 #define VEX_LEN_2A_P_3  (VEX_LEN_2A_P_1 + 1)
1055 #define VEX_LEN_2B_M_0  (VEX_LEN_2A_P_3 + 1)
1056 #define VEX_LEN_2C_P_1  (VEX_LEN_2B_M_0 + 1)
1057 #define VEX_LEN_2C_P_3  (VEX_LEN_2C_P_1 + 1)
1058 #define VEX_LEN_2D_P_1  (VEX_LEN_2C_P_3 + 1)
1059 #define VEX_LEN_2D_P_3  (VEX_LEN_2D_P_1 + 1)
1060 #define VEX_LEN_2E_P_0  (VEX_LEN_2D_P_3 + 1)
1061 #define VEX_LEN_2E_P_2  (VEX_LEN_2E_P_0 + 1)
1062 #define VEX_LEN_2F_P_0  (VEX_LEN_2E_P_2 + 1)
1063 #define VEX_LEN_2F_P_2  (VEX_LEN_2F_P_0 + 1)
1064 #define VEX_LEN_51_P_1  (VEX_LEN_2F_P_2 + 1)
1065 #define VEX_LEN_51_P_3  (VEX_LEN_51_P_1 + 1)
1066 #define VEX_LEN_52_P_1  (VEX_LEN_51_P_3 + 1)
1067 #define VEX_LEN_53_P_1  (VEX_LEN_52_P_1 + 1)
1068 #define VEX_LEN_58_P_1  (VEX_LEN_53_P_1 + 1)
1069 #define VEX_LEN_58_P_3  (VEX_LEN_58_P_1 + 1)
1070 #define VEX_LEN_59_P_1  (VEX_LEN_58_P_3 + 1)
1071 #define VEX_LEN_59_P_3  (VEX_LEN_59_P_1 + 1)
1072 #define VEX_LEN_5A_P_1  (VEX_LEN_59_P_3 + 1)
1073 #define VEX_LEN_5A_P_3  (VEX_LEN_5A_P_1 + 1)
1074 #define VEX_LEN_5C_P_1  (VEX_LEN_5A_P_3 + 1)
1075 #define VEX_LEN_5C_P_3  (VEX_LEN_5C_P_1 + 1)
1076 #define VEX_LEN_5D_P_1  (VEX_LEN_5C_P_3 + 1)
1077 #define VEX_LEN_5D_P_3  (VEX_LEN_5D_P_1 + 1)
1078 #define VEX_LEN_5E_P_1  (VEX_LEN_5D_P_3 + 1)
1079 #define VEX_LEN_5E_P_3  (VEX_LEN_5E_P_1 + 1)
1080 #define VEX_LEN_5F_P_1  (VEX_LEN_5E_P_3 + 1)
1081 #define VEX_LEN_5F_P_3  (VEX_LEN_5F_P_1 + 1)
1082 #define VEX_LEN_60_P_2  (VEX_LEN_5F_P_3 + 1)
1083 #define VEX_LEN_61_P_2  (VEX_LEN_60_P_2 + 1)
1084 #define VEX_LEN_62_P_2  (VEX_LEN_61_P_2 + 1)
1085 #define VEX_LEN_63_P_2  (VEX_LEN_62_P_2 + 1)
1086 #define VEX_LEN_64_P_2  (VEX_LEN_63_P_2 + 1)
1087 #define VEX_LEN_65_P_2  (VEX_LEN_64_P_2 + 1)
1088 #define VEX_LEN_66_P_2  (VEX_LEN_65_P_2 + 1)
1089 #define VEX_LEN_67_P_2  (VEX_LEN_66_P_2 + 1)
1090 #define VEX_LEN_68_P_2  (VEX_LEN_67_P_2 + 1)
1091 #define VEX_LEN_69_P_2  (VEX_LEN_68_P_2 + 1)
1092 #define VEX_LEN_6A_P_2  (VEX_LEN_69_P_2 + 1)
1093 #define VEX_LEN_6B_P_2  (VEX_LEN_6A_P_2 + 1)
1094 #define VEX_LEN_6C_P_2  (VEX_LEN_6B_P_2 + 1)
1095 #define VEX_LEN_6D_P_2  (VEX_LEN_6C_P_2 + 1)
1096 #define VEX_LEN_6E_P_2  (VEX_LEN_6D_P_2 + 1)
1097 #define VEX_LEN_70_P_1  (VEX_LEN_6E_P_2 + 1)
1098 #define VEX_LEN_70_P_2  (VEX_LEN_70_P_1 + 1)
1099 #define VEX_LEN_70_P_3  (VEX_LEN_70_P_2 + 1)
1100 #define VEX_LEN_71_R_2_P_2      (VEX_LEN_70_P_3 + 1)
1101 #define VEX_LEN_71_R_4_P_2      (VEX_LEN_71_R_2_P_2 + 1)
1102 #define VEX_LEN_71_R_6_P_2      (VEX_LEN_71_R_4_P_2 + 1)
1103 #define VEX_LEN_72_R_2_P_2      (VEX_LEN_71_R_6_P_2 + 1)
1104 #define VEX_LEN_72_R_4_P_2      (VEX_LEN_72_R_2_P_2 + 1)
1105 #define VEX_LEN_72_R_6_P_2      (VEX_LEN_72_R_4_P_2 + 1)
1106 #define VEX_LEN_73_R_2_P_2      (VEX_LEN_72_R_6_P_2 + 1)
1107 #define VEX_LEN_73_R_3_P_2      (VEX_LEN_73_R_2_P_2 + 1)
1108 #define VEX_LEN_73_R_6_P_2      (VEX_LEN_73_R_3_P_2 + 1)
1109 #define VEX_LEN_73_R_7_P_2      (VEX_LEN_73_R_6_P_2 + 1)
1110 #define VEX_LEN_74_P_2  (VEX_LEN_73_R_7_P_2 + 1)
1111 #define VEX_LEN_75_P_2  (VEX_LEN_74_P_2 + 1)
1112 #define VEX_LEN_76_P_2  (VEX_LEN_75_P_2 + 1)
1113 #define VEX_LEN_7E_P_1  (VEX_LEN_76_P_2 + 1)
1114 #define VEX_LEN_7E_P_2  (VEX_LEN_7E_P_1 + 1)
1115 #define VEX_LEN_AE_R_2_M_0      (VEX_LEN_7E_P_2 + 1)
1116 #define VEX_LEN_AE_R_3_M_0      (VEX_LEN_AE_R_2_M_0 + 1)
1117 #define VEX_LEN_C2_P_1  (VEX_LEN_AE_R_3_M_0 + 1)
1118 #define VEX_LEN_C2_P_3  (VEX_LEN_C2_P_1 + 1)
1119 #define VEX_LEN_C4_P_2  (VEX_LEN_C2_P_3 + 1)
1120 #define VEX_LEN_C5_P_2  (VEX_LEN_C4_P_2 + 1)
1121 #define VEX_LEN_D1_P_2  (VEX_LEN_C5_P_2 + 1)
1122 #define VEX_LEN_D2_P_2  (VEX_LEN_D1_P_2 + 1)
1123 #define VEX_LEN_D3_P_2  (VEX_LEN_D2_P_2 + 1)
1124 #define VEX_LEN_D4_P_2  (VEX_LEN_D3_P_2 + 1)
1125 #define VEX_LEN_D5_P_2  (VEX_LEN_D4_P_2 + 1)
1126 #define VEX_LEN_D6_P_2  (VEX_LEN_D5_P_2 + 1)
1127 #define VEX_LEN_D7_P_2_M_1      (VEX_LEN_D6_P_2 + 1)
1128 #define VEX_LEN_D8_P_2  (VEX_LEN_D7_P_2_M_1 + 1)
1129 #define VEX_LEN_D9_P_2  (VEX_LEN_D8_P_2 + 1)
1130 #define VEX_LEN_DA_P_2  (VEX_LEN_D9_P_2 + 1)
1131 #define VEX_LEN_DB_P_2  (VEX_LEN_DA_P_2 + 1)
1132 #define VEX_LEN_DC_P_2  (VEX_LEN_DB_P_2 + 1)
1133 #define VEX_LEN_DD_P_2  (VEX_LEN_DC_P_2 + 1)
1134 #define VEX_LEN_DE_P_2  (VEX_LEN_DD_P_2 + 1)
1135 #define VEX_LEN_DF_P_2  (VEX_LEN_DE_P_2 + 1)
1136 #define VEX_LEN_E0_P_2  (VEX_LEN_DF_P_2 + 1)
1137 #define VEX_LEN_E1_P_2  (VEX_LEN_E0_P_2 + 1)
1138 #define VEX_LEN_E2_P_2  (VEX_LEN_E1_P_2 + 1)
1139 #define VEX_LEN_E3_P_2  (VEX_LEN_E2_P_2 + 1)
1140 #define VEX_LEN_E4_P_2  (VEX_LEN_E3_P_2 + 1)
1141 #define VEX_LEN_E5_P_2  (VEX_LEN_E4_P_2 + 1)
1142 #define VEX_LEN_E7_P_2_M_0      (VEX_LEN_E5_P_2 + 1)
1143 #define VEX_LEN_E8_P_2  (VEX_LEN_E7_P_2_M_0 + 1)
1144 #define VEX_LEN_E9_P_2  (VEX_LEN_E8_P_2 + 1)
1145 #define VEX_LEN_EA_P_2  (VEX_LEN_E9_P_2 + 1)
1146 #define VEX_LEN_EB_P_2  (VEX_LEN_EA_P_2 + 1)
1147 #define VEX_LEN_EC_P_2  (VEX_LEN_EB_P_2 + 1)
1148 #define VEX_LEN_ED_P_2  (VEX_LEN_EC_P_2 + 1)
1149 #define VEX_LEN_EE_P_2  (VEX_LEN_ED_P_2 + 1)
1150 #define VEX_LEN_EF_P_2  (VEX_LEN_EE_P_2 + 1)
1151 #define VEX_LEN_F1_P_2  (VEX_LEN_EF_P_2 + 1)
1152 #define VEX_LEN_F2_P_2  (VEX_LEN_F1_P_2 + 1)
1153 #define VEX_LEN_F3_P_2  (VEX_LEN_F2_P_2 + 1)
1154 #define VEX_LEN_F4_P_2  (VEX_LEN_F3_P_2 + 1)
1155 #define VEX_LEN_F5_P_2  (VEX_LEN_F4_P_2 + 1)
1156 #define VEX_LEN_F6_P_2  (VEX_LEN_F5_P_2 + 1)
1157 #define VEX_LEN_F7_P_2  (VEX_LEN_F6_P_2 + 1)
1158 #define VEX_LEN_F8_P_2  (VEX_LEN_F7_P_2 + 1)
1159 #define VEX_LEN_F9_P_2  (VEX_LEN_F8_P_2 + 1)
1160 #define VEX_LEN_FA_P_2  (VEX_LEN_F9_P_2 + 1)
1161 #define VEX_LEN_FB_P_2  (VEX_LEN_FA_P_2 + 1)
1162 #define VEX_LEN_FC_P_2  (VEX_LEN_FB_P_2 + 1)
1163 #define VEX_LEN_FD_P_2  (VEX_LEN_FC_P_2 + 1)
1164 #define VEX_LEN_FE_P_2  (VEX_LEN_FD_P_2 + 1)
1165 #define VEX_LEN_3800_P_2        (VEX_LEN_FE_P_2 + 1)
1166 #define VEX_LEN_3801_P_2        (VEX_LEN_3800_P_2 + 1)
1167 #define VEX_LEN_3802_P_2        (VEX_LEN_3801_P_2 + 1)
1168 #define VEX_LEN_3803_P_2        (VEX_LEN_3802_P_2 + 1)
1169 #define VEX_LEN_3804_P_2        (VEX_LEN_3803_P_2 + 1)
1170 #define VEX_LEN_3805_P_2        (VEX_LEN_3804_P_2 + 1)
1171 #define VEX_LEN_3806_P_2        (VEX_LEN_3805_P_2 + 1)
1172 #define VEX_LEN_3807_P_2        (VEX_LEN_3806_P_2 + 1)
1173 #define VEX_LEN_3808_P_2        (VEX_LEN_3807_P_2 + 1)
1174 #define VEX_LEN_3809_P_2        (VEX_LEN_3808_P_2 + 1)
1175 #define VEX_LEN_380A_P_2        (VEX_LEN_3809_P_2 + 1)
1176 #define VEX_LEN_380B_P_2        (VEX_LEN_380A_P_2 + 1)
1177 #define VEX_LEN_3819_P_2_M_0    (VEX_LEN_380B_P_2 + 1)
1178 #define VEX_LEN_381A_P_2_M_0    (VEX_LEN_3819_P_2_M_0 + 1)
1179 #define VEX_LEN_381C_P_2        (VEX_LEN_381A_P_2_M_0 + 1)
1180 #define VEX_LEN_381D_P_2        (VEX_LEN_381C_P_2 + 1)
1181 #define VEX_LEN_381E_P_2        (VEX_LEN_381D_P_2 + 1)
1182 #define VEX_LEN_3820_P_2        (VEX_LEN_381E_P_2 + 1)
1183 #define VEX_LEN_3821_P_2        (VEX_LEN_3820_P_2 + 1)
1184 #define VEX_LEN_3822_P_2        (VEX_LEN_3821_P_2 + 1)
1185 #define VEX_LEN_3823_P_2        (VEX_LEN_3822_P_2 + 1)
1186 #define VEX_LEN_3824_P_2        (VEX_LEN_3823_P_2 + 1)
1187 #define VEX_LEN_3825_P_2        (VEX_LEN_3824_P_2 + 1)
1188 #define VEX_LEN_3828_P_2        (VEX_LEN_3825_P_2 + 1)
1189 #define VEX_LEN_3829_P_2        (VEX_LEN_3828_P_2 + 1)
1190 #define VEX_LEN_382A_P_2_M_0    (VEX_LEN_3829_P_2 + 1)
1191 #define VEX_LEN_382B_P_2        (VEX_LEN_382A_P_2_M_0 + 1)
1192 #define VEX_LEN_3830_P_2        (VEX_LEN_382B_P_2 + 1)
1193 #define VEX_LEN_3831_P_2        (VEX_LEN_3830_P_2 + 1)
1194 #define VEX_LEN_3832_P_2        (VEX_LEN_3831_P_2 + 1)
1195 #define VEX_LEN_3833_P_2        (VEX_LEN_3832_P_2 + 1)
1196 #define VEX_LEN_3834_P_2        (VEX_LEN_3833_P_2 + 1)
1197 #define VEX_LEN_3835_P_2        (VEX_LEN_3834_P_2 + 1)
1198 #define VEX_LEN_3837_P_2        (VEX_LEN_3835_P_2 + 1)
1199 #define VEX_LEN_3838_P_2        (VEX_LEN_3837_P_2 + 1)
1200 #define VEX_LEN_3839_P_2        (VEX_LEN_3838_P_2 + 1)
1201 #define VEX_LEN_383A_P_2        (VEX_LEN_3839_P_2 + 1)
1202 #define VEX_LEN_383B_P_2        (VEX_LEN_383A_P_2 + 1)
1203 #define VEX_LEN_383C_P_2        (VEX_LEN_383B_P_2 + 1)
1204 #define VEX_LEN_383D_P_2        (VEX_LEN_383C_P_2 + 1)
1205 #define VEX_LEN_383E_P_2        (VEX_LEN_383D_P_2 + 1)
1206 #define VEX_LEN_383F_P_2        (VEX_LEN_383E_P_2 + 1)
1207 #define VEX_LEN_3840_P_2        (VEX_LEN_383F_P_2 + 1)
1208 #define VEX_LEN_3841_P_2        (VEX_LEN_3840_P_2 + 1)
1209 #define VEX_LEN_38DB_P_2        (VEX_LEN_3841_P_2 + 1)
1210 #define VEX_LEN_38DC_P_2        (VEX_LEN_38DB_P_2 + 1)
1211 #define VEX_LEN_38DD_P_2        (VEX_LEN_38DC_P_2 + 1)
1212 #define VEX_LEN_38DE_P_2        (VEX_LEN_38DD_P_2 + 1)
1213 #define VEX_LEN_38DF_P_2        (VEX_LEN_38DE_P_2 + 1)
1214 #define VEX_LEN_3A06_P_2        (VEX_LEN_38DF_P_2 + 1)
1215 #define VEX_LEN_3A0A_P_2        (VEX_LEN_3A06_P_2 + 1)
1216 #define VEX_LEN_3A0B_P_2        (VEX_LEN_3A0A_P_2 + 1)
1217 #define VEX_LEN_3A0E_P_2        (VEX_LEN_3A0B_P_2 + 1)
1218 #define VEX_LEN_3A0F_P_2        (VEX_LEN_3A0E_P_2 + 1)
1219 #define VEX_LEN_3A14_P_2        (VEX_LEN_3A0F_P_2 + 1)
1220 #define VEX_LEN_3A15_P_2        (VEX_LEN_3A14_P_2 + 1)
1221 #define VEX_LEN_3A16_P_2        (VEX_LEN_3A15_P_2 + 1)
1222 #define VEX_LEN_3A17_P_2        (VEX_LEN_3A16_P_2 + 1)
1223 #define VEX_LEN_3A18_P_2        (VEX_LEN_3A17_P_2 + 1)
1224 #define VEX_LEN_3A19_P_2        (VEX_LEN_3A18_P_2 + 1)
1225 #define VEX_LEN_3A20_P_2        (VEX_LEN_3A19_P_2 + 1)
1226 #define VEX_LEN_3A21_P_2        (VEX_LEN_3A20_P_2 + 1)
1227 #define VEX_LEN_3A22_P_2        (VEX_LEN_3A21_P_2 + 1)
1228 #define VEX_LEN_3A41_P_2        (VEX_LEN_3A22_P_2 + 1)
1229 #define VEX_LEN_3A42_P_2        (VEX_LEN_3A41_P_2 + 1)
1230 #define VEX_LEN_3A4C_P_2        (VEX_LEN_3A42_P_2 + 1)
1231 #define VEX_LEN_3A60_P_2        (VEX_LEN_3A4C_P_2 + 1)
1232 #define VEX_LEN_3A61_P_2        (VEX_LEN_3A60_P_2 + 1)
1233 #define VEX_LEN_3A62_P_2        (VEX_LEN_3A61_P_2 + 1)
1234 #define VEX_LEN_3A63_P_2        (VEX_LEN_3A62_P_2 + 1)
1235 #define VEX_LEN_3A6A_P_2        (VEX_LEN_3A63_P_2 + 1)
1236 #define VEX_LEN_3A6B_P_2        (VEX_LEN_3A6A_P_2 + 1)
1237 #define VEX_LEN_3A6E_P_2        (VEX_LEN_3A6B_P_2 + 1)
1238 #define VEX_LEN_3A6F_P_2        (VEX_LEN_3A6E_P_2 + 1)
1239 #define VEX_LEN_3A7A_P_2        (VEX_LEN_3A6F_P_2 + 1)
1240 #define VEX_LEN_3A7B_P_2        (VEX_LEN_3A7A_P_2 + 1)
1241 #define VEX_LEN_3A7E_P_2        (VEX_LEN_3A7B_P_2 + 1)
1242 #define VEX_LEN_3A7F_P_2        (VEX_LEN_3A7E_P_2 + 1)
1243 #define VEX_LEN_3ADF_P_2        (VEX_LEN_3A7F_P_2 + 1)
1244
1245 typedef void (*op_rtn) (int bytemode, int sizeflag);
1246
1247 struct dis386 {
1248   const char *name;
1249   struct
1250     {
1251       op_rtn rtn;
1252       int bytemode;
1253     } op[MAX_OPERANDS];
1254 };
1255
1256 /* Upper case letters in the instruction names here are macros.
1257    'A' => print 'b' if no register operands or suffix_always is true
1258    'B' => print 'b' if suffix_always is true
1259    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1260           size prefix
1261    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1262           suffix_always is true
1263    'E' => print 'e' if 32-bit form of jcxz
1264    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1265    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1266    'H' => print ",pt" or ",pn" branch hint
1267    'I' => honor following macro letter even in Intel mode (implemented only
1268           for some of the macro letters)
1269    'J' => print 'l'
1270    'K' => print 'd' or 'q' if rex prefix is present.
1271    'L' => print 'l' if suffix_always is true
1272    'M' => print 'r' if intel_mnemonic is false.
1273    'N' => print 'n' if instruction has no wait "prefix"
1274    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1275    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1276           or suffix_always is true.  print 'q' if rex prefix is present.
1277    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1278           is true
1279    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1280    'S' => print 'w', 'l' or 'q' if suffix_always is true
1281    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1282    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1283    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1284    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1285    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1286    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1287           suffix_always is true.
1288    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1289    '!' => change condition from true to false or from false to true.
1290    '%' => add 1 upper case letter to the macro.
1291
1292    2 upper case letter macros:
1293    "XY" => print 'x' or 'y' if no register operands or suffix_always
1294            is true.
1295    'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1296            or suffix_always is true
1297
1298    Many of the above letters print nothing in Intel mode.  See "putop"
1299    for the details.
1300
1301    Braces '{' and '}', and vertical bars '|', indicate alternative
1302    mnemonic strings for AT&T and Intel.  */
1303
1304 static const struct dis386 dis386[] = {
1305   /* 00 */
1306   { "addB",             { Eb, Gb } },
1307   { "addS",             { Ev, Gv } },
1308   { "addB",             { Gb, Eb } },
1309   { "addS",             { Gv, Ev } },
1310   { "addB",             { AL, Ib } },
1311   { "addS",             { eAX, Iv } },
1312   { X86_64_TABLE (X86_64_06) },
1313   { X86_64_TABLE (X86_64_07) },
1314   /* 08 */
1315   { "orB",              { Eb, Gb } },
1316   { "orS",              { Ev, Gv } },
1317   { "orB",              { Gb, Eb } },
1318   { "orS",              { Gv, Ev } },
1319   { "orB",              { AL, Ib } },
1320   { "orS",              { eAX, Iv } },
1321   { X86_64_TABLE (X86_64_0D) },
1322   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1323   /* 10 */
1324   { "adcB",             { Eb, Gb } },
1325   { "adcS",             { Ev, Gv } },
1326   { "adcB",             { Gb, Eb } },
1327   { "adcS",             { Gv, Ev } },
1328   { "adcB",             { AL, Ib } },
1329   { "adcS",             { eAX, Iv } },
1330   { X86_64_TABLE (X86_64_16) },
1331   { X86_64_TABLE (X86_64_17) },
1332   /* 18 */
1333   { "sbbB",             { Eb, Gb } },
1334   { "sbbS",             { Ev, Gv } },
1335   { "sbbB",             { Gb, Eb } },
1336   { "sbbS",             { Gv, Ev } },
1337   { "sbbB",             { AL, Ib } },
1338   { "sbbS",             { eAX, Iv } },
1339   { X86_64_TABLE (X86_64_1E) },
1340   { X86_64_TABLE (X86_64_1F) },
1341   /* 20 */
1342   { "andB",             { Eb, Gb } },
1343   { "andS",             { Ev, Gv } },
1344   { "andB",             { Gb, Eb } },
1345   { "andS",             { Gv, Ev } },
1346   { "andB",             { AL, Ib } },
1347   { "andS",             { eAX, Iv } },
1348   { "(bad)",            { XX } },       /* SEG ES prefix */
1349   { X86_64_TABLE (X86_64_27) },
1350   /* 28 */
1351   { "subB",             { Eb, Gb } },
1352   { "subS",             { Ev, Gv } },
1353   { "subB",             { Gb, Eb } },
1354   { "subS",             { Gv, Ev } },
1355   { "subB",             { AL, Ib } },
1356   { "subS",             { eAX, Iv } },
1357   { "(bad)",            { XX } },       /* SEG CS prefix */
1358   { X86_64_TABLE (X86_64_2F) },
1359   /* 30 */
1360   { "xorB",             { Eb, Gb } },
1361   { "xorS",             { Ev, Gv } },
1362   { "xorB",             { Gb, Eb } },
1363   { "xorS",             { Gv, Ev } },
1364   { "xorB",             { AL, Ib } },
1365   { "xorS",             { eAX, Iv } },
1366   { "(bad)",            { XX } },       /* SEG SS prefix */
1367   { X86_64_TABLE (X86_64_37) },
1368   /* 38 */
1369   { "cmpB",             { Eb, Gb } },
1370   { "cmpS",             { Ev, Gv } },
1371   { "cmpB",             { Gb, Eb } },
1372   { "cmpS",             { Gv, Ev } },
1373   { "cmpB",             { AL, Ib } },
1374   { "cmpS",             { eAX, Iv } },
1375   { "(bad)",            { XX } },       /* SEG DS prefix */
1376   { X86_64_TABLE (X86_64_3F) },
1377   /* 40 */
1378   { "inc{S|}",          { RMeAX } },
1379   { "inc{S|}",          { RMeCX } },
1380   { "inc{S|}",          { RMeDX } },
1381   { "inc{S|}",          { RMeBX } },
1382   { "inc{S|}",          { RMeSP } },
1383   { "inc{S|}",          { RMeBP } },
1384   { "inc{S|}",          { RMeSI } },
1385   { "inc{S|}",          { RMeDI } },
1386   /* 48 */
1387   { "dec{S|}",          { RMeAX } },
1388   { "dec{S|}",          { RMeCX } },
1389   { "dec{S|}",          { RMeDX } },
1390   { "dec{S|}",          { RMeBX } },
1391   { "dec{S|}",          { RMeSP } },
1392   { "dec{S|}",          { RMeBP } },
1393   { "dec{S|}",          { RMeSI } },
1394   { "dec{S|}",          { RMeDI } },
1395   /* 50 */
1396   { "pushV",            { RMrAX } },
1397   { "pushV",            { RMrCX } },
1398   { "pushV",            { RMrDX } },
1399   { "pushV",            { RMrBX } },
1400   { "pushV",            { RMrSP } },
1401   { "pushV",            { RMrBP } },
1402   { "pushV",            { RMrSI } },
1403   { "pushV",            { RMrDI } },
1404   /* 58 */
1405   { "popV",             { RMrAX } },
1406   { "popV",             { RMrCX } },
1407   { "popV",             { RMrDX } },
1408   { "popV",             { RMrBX } },
1409   { "popV",             { RMrSP } },
1410   { "popV",             { RMrBP } },
1411   { "popV",             { RMrSI } },
1412   { "popV",             { RMrDI } },
1413   /* 60 */
1414   { X86_64_TABLE (X86_64_60) },
1415   { X86_64_TABLE (X86_64_61) },
1416   { X86_64_TABLE (X86_64_62) },
1417   { X86_64_TABLE (X86_64_63) },
1418   { "(bad)",            { XX } },       /* seg fs */
1419   { "(bad)",            { XX } },       /* seg gs */
1420   { "(bad)",            { XX } },       /* op size prefix */
1421   { "(bad)",            { XX } },       /* adr size prefix */
1422   /* 68 */
1423   { "pushT",            { Iq } },
1424   { "imulS",            { Gv, Ev, Iv } },
1425   { "pushT",            { sIb } },
1426   { "imulS",            { Gv, Ev, sIb } },
1427   { "ins{b|}",          { Ybr, indirDX } },
1428   { X86_64_TABLE (X86_64_6D) },
1429   { "outs{b|}",         { indirDXr, Xb } },
1430   { X86_64_TABLE (X86_64_6F) },
1431   /* 70 */
1432   { "joH",              { Jb, XX, cond_jump_flag } },
1433   { "jnoH",             { Jb, XX, cond_jump_flag } },
1434   { "jbH",              { Jb, XX, cond_jump_flag } },
1435   { "jaeH",             { Jb, XX, cond_jump_flag } },
1436   { "jeH",              { Jb, XX, cond_jump_flag } },
1437   { "jneH",             { Jb, XX, cond_jump_flag } },
1438   { "jbeH",             { Jb, XX, cond_jump_flag } },
1439   { "jaH",              { Jb, XX, cond_jump_flag } },
1440   /* 78 */
1441   { "jsH",              { Jb, XX, cond_jump_flag } },
1442   { "jnsH",             { Jb, XX, cond_jump_flag } },
1443   { "jpH",              { Jb, XX, cond_jump_flag } },
1444   { "jnpH",             { Jb, XX, cond_jump_flag } },
1445   { "jlH",              { Jb, XX, cond_jump_flag } },
1446   { "jgeH",             { Jb, XX, cond_jump_flag } },
1447   { "jleH",             { Jb, XX, cond_jump_flag } },
1448   { "jgH",              { Jb, XX, cond_jump_flag } },
1449   /* 80 */
1450   { REG_TABLE (REG_80) },
1451   { REG_TABLE (REG_81) },
1452   { "(bad)",            { XX } },
1453   { REG_TABLE (REG_82) },
1454   { "testB",            { Eb, Gb } },
1455   { "testS",            { Ev, Gv } },
1456   { "xchgB",            { Eb, Gb } },
1457   { "xchgS",            { Ev, Gv } },
1458   /* 88 */
1459   { "movB",             { Eb, Gb } },
1460   { "movS",             { Ev, Gv } },
1461   { "movB",             { Gb, Eb } },
1462   { "movS",             { Gv, Ev } },
1463   { "movD",             { Sv, Sw } },
1464   { MOD_TABLE (MOD_8D) },
1465   { "movD",             { Sw, Sv } },
1466   { REG_TABLE (REG_8F) },
1467   /* 90 */
1468   { PREFIX_TABLE (PREFIX_90) },
1469   { "xchgS",            { RMeCX, eAX } },
1470   { "xchgS",            { RMeDX, eAX } },
1471   { "xchgS",            { RMeBX, eAX } },
1472   { "xchgS",            { RMeSP, eAX } },
1473   { "xchgS",            { RMeBP, eAX } },
1474   { "xchgS",            { RMeSI, eAX } },
1475   { "xchgS",            { RMeDI, eAX } },
1476   /* 98 */
1477   { "cW{t|}R",          { XX } },
1478   { "cR{t|}O",          { XX } },
1479   { X86_64_TABLE (X86_64_9A) },
1480   { "(bad)",            { XX } },       /* fwait */
1481   { "pushfT",           { XX } },
1482   { "popfT",            { XX } },
1483   { "sahf",             { XX } },
1484   { "lahf",             { XX } },
1485   /* a0 */
1486   { "movB",             { AL, Ob } },
1487   { "movS",             { eAX, Ov } },
1488   { "movB",             { Ob, AL } },
1489   { "movS",             { Ov, eAX } },
1490   { "movs{b|}",         { Ybr, Xb } },
1491   { "movs{R|}",         { Yvr, Xv } },
1492   { "cmps{b|}",         { Xb, Yb } },
1493   { "cmps{R|}",         { Xv, Yv } },
1494   /* a8 */
1495   { "testB",            { AL, Ib } },
1496   { "testS",            { eAX, Iv } },
1497   { "stosB",            { Ybr, AL } },
1498   { "stosS",            { Yvr, eAX } },
1499   { "lodsB",            { ALr, Xb } },
1500   { "lodsS",            { eAXr, Xv } },
1501   { "scasB",            { AL, Yb } },
1502   { "scasS",            { eAX, Yv } },
1503   /* b0 */
1504   { "movB",             { RMAL, Ib } },
1505   { "movB",             { RMCL, Ib } },
1506   { "movB",             { RMDL, Ib } },
1507   { "movB",             { RMBL, Ib } },
1508   { "movB",             { RMAH, Ib } },
1509   { "movB",             { RMCH, Ib } },
1510   { "movB",             { RMDH, Ib } },
1511   { "movB",             { RMBH, Ib } },
1512   /* b8 */
1513   { "movS",             { RMeAX, Iv64 } },
1514   { "movS",             { RMeCX, Iv64 } },
1515   { "movS",             { RMeDX, Iv64 } },
1516   { "movS",             { RMeBX, Iv64 } },
1517   { "movS",             { RMeSP, Iv64 } },
1518   { "movS",             { RMeBP, Iv64 } },
1519   { "movS",             { RMeSI, Iv64 } },
1520   { "movS",             { RMeDI, Iv64 } },
1521   /* c0 */
1522   { REG_TABLE (REG_C0) },
1523   { REG_TABLE (REG_C1) },
1524   { "retT",             { Iw } },
1525   { "retT",             { XX } },
1526   { X86_64_TABLE (X86_64_C4) },
1527   { X86_64_TABLE (X86_64_C5) },
1528   { REG_TABLE (REG_C6) },
1529   { REG_TABLE (REG_C7) },
1530   /* c8 */
1531   { "enterT",           { Iw, Ib } },
1532   { "leaveT",           { XX } },
1533   { "lretP",            { Iw } },
1534   { "lretP",            { XX } },
1535   { "int3",             { XX } },
1536   { "int",              { Ib } },
1537   { X86_64_TABLE (X86_64_CE) },
1538   { "iretP",            { XX } },
1539   /* d0 */
1540   { REG_TABLE (REG_D0) },
1541   { REG_TABLE (REG_D1) },
1542   { REG_TABLE (REG_D2) },
1543   { REG_TABLE (REG_D3) },
1544   { X86_64_TABLE (X86_64_D4) },
1545   { X86_64_TABLE (X86_64_D5) },
1546   { "(bad)",            { XX } },
1547   { "xlat",             { DSBX } },
1548   /* d8 */
1549   { FLOAT },
1550   { FLOAT },
1551   { FLOAT },
1552   { FLOAT },
1553   { FLOAT },
1554   { FLOAT },
1555   { FLOAT },
1556   { FLOAT },
1557   /* e0 */
1558   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1559   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1560   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1561   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1562   { "inB",              { AL, Ib } },
1563   { "inG",              { zAX, Ib } },
1564   { "outB",             { Ib, AL } },
1565   { "outG",             { Ib, zAX } },
1566   /* e8 */
1567   { "callT",            { Jv } },
1568   { "jmpT",             { Jv } },
1569   { X86_64_TABLE (X86_64_EA) },
1570   { "jmp",              { Jb } },
1571   { "inB",              { AL, indirDX } },
1572   { "inG",              { zAX, indirDX } },
1573   { "outB",             { indirDX, AL } },
1574   { "outG",             { indirDX, zAX } },
1575   /* f0 */
1576   { "(bad)",            { XX } },       /* lock prefix */
1577   { "icebp",            { XX } },
1578   { "(bad)",            { XX } },       /* repne */
1579   { "(bad)",            { XX } },       /* repz */
1580   { "hlt",              { XX } },
1581   { "cmc",              { XX } },
1582   { REG_TABLE (REG_F6) },
1583   { REG_TABLE (REG_F7) },
1584   /* f8 */
1585   { "clc",              { XX } },
1586   { "stc",              { XX } },
1587   { "cli",              { XX } },
1588   { "sti",              { XX } },
1589   { "cld",              { XX } },
1590   { "std",              { XX } },
1591   { REG_TABLE (REG_FE) },
1592   { REG_TABLE (REG_FF) },
1593 };
1594
1595 static const struct dis386 dis386_twobyte[] = {
1596   /* 00 */
1597   { REG_TABLE (REG_0F00 ) },
1598   { REG_TABLE (REG_0F01 ) },
1599   { "larS",             { Gv, Ew } },
1600   { "lslS",             { Gv, Ew } },
1601   { "(bad)",            { XX } },
1602   { "syscall",          { XX } },
1603   { "clts",             { XX } },
1604   { "sysretP",          { XX } },
1605   /* 08 */
1606   { "invd",             { XX } },
1607   { "wbinvd",           { XX } },
1608   { "(bad)",            { XX } },
1609   { "ud2a",             { XX } },
1610   { "(bad)",            { XX } },
1611   { REG_TABLE (REG_0F0D) },
1612   { "femms",            { XX } },
1613   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1614   /* 10 */
1615   { PREFIX_TABLE (PREFIX_0F10) },
1616   { PREFIX_TABLE (PREFIX_0F11) },
1617   { PREFIX_TABLE (PREFIX_0F12) },
1618   { MOD_TABLE (MOD_0F13) },
1619   { "unpcklpX",         { XM, EXx } },
1620   { "unpckhpX",         { XM, EXx } },
1621   { PREFIX_TABLE (PREFIX_0F16) },
1622   { MOD_TABLE (MOD_0F17) },
1623   /* 18 */
1624   { REG_TABLE (REG_0F18) },
1625   { "nopQ",             { Ev } },
1626   { "nopQ",             { Ev } },
1627   { "nopQ",             { Ev } },
1628   { "nopQ",             { Ev } },
1629   { "nopQ",             { Ev } },
1630   { "nopQ",             { Ev } },
1631   { "nopQ",             { Ev } },
1632   /* 20 */
1633   { MOD_TABLE (MOD_0F20) },
1634   { MOD_TABLE (MOD_0F21) },
1635   { MOD_TABLE (MOD_0F22) },
1636   { MOD_TABLE (MOD_0F23) },
1637   { MOD_TABLE (MOD_0F24) },
1638   { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1639   { MOD_TABLE (MOD_0F26) },
1640   { "(bad)",            { XX } },
1641   /* 28 */
1642   { "movapX",           { XM, EXx } },
1643   { "movapX",           { EXx, XM } },
1644   { PREFIX_TABLE (PREFIX_0F2A) },
1645   { PREFIX_TABLE (PREFIX_0F2B) },
1646   { PREFIX_TABLE (PREFIX_0F2C) },
1647   { PREFIX_TABLE (PREFIX_0F2D) },
1648   { PREFIX_TABLE (PREFIX_0F2E) },
1649   { PREFIX_TABLE (PREFIX_0F2F) },
1650   /* 30 */
1651   { "wrmsr",            { XX } },
1652   { "rdtsc",            { XX } },
1653   { "rdmsr",            { XX } },
1654   { "rdpmc",            { XX } },
1655   { "sysenter",         { XX } },
1656   { "sysexit",          { XX } },
1657   { "(bad)",            { XX } },
1658   { "getsec",           { XX } },
1659   /* 38 */
1660   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1661   { "(bad)",            { XX } },
1662   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1663   { "(bad)",            { XX } },
1664   { "(bad)",            { XX } },
1665   { "(bad)",            { XX } },
1666   { "(bad)",            { XX } },
1667   { "(bad)",            { XX } },
1668   /* 40 */
1669   { "cmovo",            { Gv, Ev } },
1670   { "cmovno",           { Gv, Ev } },
1671   { "cmovb",            { Gv, Ev } },
1672   { "cmovae",           { Gv, Ev } },
1673   { "cmove",            { Gv, Ev } },
1674   { "cmovne",           { Gv, Ev } },
1675   { "cmovbe",           { Gv, Ev } },
1676   { "cmova",            { Gv, Ev } },
1677   /* 48 */
1678   { "cmovs",            { Gv, Ev } },
1679   { "cmovns",           { Gv, Ev } },
1680   { "cmovp",            { Gv, Ev } },
1681   { "cmovnp",           { Gv, Ev } },
1682   { "cmovl",            { Gv, Ev } },
1683   { "cmovge",           { Gv, Ev } },
1684   { "cmovle",           { Gv, Ev } },
1685   { "cmovg",            { Gv, Ev } },
1686   /* 50 */
1687   { MOD_TABLE (MOD_0F51) },
1688   { PREFIX_TABLE (PREFIX_0F51) },
1689   { PREFIX_TABLE (PREFIX_0F52) },
1690   { PREFIX_TABLE (PREFIX_0F53) },
1691   { "andpX",            { XM, EXx } },
1692   { "andnpX",           { XM, EXx } },
1693   { "orpX",             { XM, EXx } },
1694   { "xorpX",            { XM, EXx } },
1695   /* 58 */
1696   { PREFIX_TABLE (PREFIX_0F58) },
1697   { PREFIX_TABLE (PREFIX_0F59) },
1698   { PREFIX_TABLE (PREFIX_0F5A) },
1699   { PREFIX_TABLE (PREFIX_0F5B) },
1700   { PREFIX_TABLE (PREFIX_0F5C) },
1701   { PREFIX_TABLE (PREFIX_0F5D) },
1702   { PREFIX_TABLE (PREFIX_0F5E) },
1703   { PREFIX_TABLE (PREFIX_0F5F) },
1704   /* 60 */
1705   { PREFIX_TABLE (PREFIX_0F60) },
1706   { PREFIX_TABLE (PREFIX_0F61) },
1707   { PREFIX_TABLE (PREFIX_0F62) },
1708   { "packsswb",         { MX, EM } },
1709   { "pcmpgtb",          { MX, EM } },
1710   { "pcmpgtw",          { MX, EM } },
1711   { "pcmpgtd",          { MX, EM } },
1712   { "packuswb",         { MX, EM } },
1713   /* 68 */
1714   { "punpckhbw",        { MX, EM } },
1715   { "punpckhwd",        { MX, EM } },
1716   { "punpckhdq",        { MX, EM } },
1717   { "packssdw",         { MX, EM } },
1718   { PREFIX_TABLE (PREFIX_0F6C) },
1719   { PREFIX_TABLE (PREFIX_0F6D) },
1720   { "movK",             { MX, Edq } },
1721   { PREFIX_TABLE (PREFIX_0F6F) },
1722   /* 70 */
1723   { PREFIX_TABLE (PREFIX_0F70) },
1724   { REG_TABLE (REG_0F71) },
1725   { REG_TABLE (REG_0F72) },
1726   { REG_TABLE (REG_0F73) },
1727   { "pcmpeqb",          { MX, EM } },
1728   { "pcmpeqw",          { MX, EM } },
1729   { "pcmpeqd",          { MX, EM } },
1730   { "emms",             { XX } },
1731   /* 78 */
1732   { PREFIX_TABLE (PREFIX_0F78) },
1733   { PREFIX_TABLE (PREFIX_0F79) },
1734   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1735   { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1736   { PREFIX_TABLE (PREFIX_0F7C) },
1737   { PREFIX_TABLE (PREFIX_0F7D) },
1738   { PREFIX_TABLE (PREFIX_0F7E) },
1739   { PREFIX_TABLE (PREFIX_0F7F) },
1740   /* 80 */
1741   { "joH",              { Jv, XX, cond_jump_flag } },
1742   { "jnoH",             { Jv, XX, cond_jump_flag } },
1743   { "jbH",              { Jv, XX, cond_jump_flag } },
1744   { "jaeH",             { Jv, XX, cond_jump_flag } },
1745   { "jeH",              { Jv, XX, cond_jump_flag } },
1746   { "jneH",             { Jv, XX, cond_jump_flag } },
1747   { "jbeH",             { Jv, XX, cond_jump_flag } },
1748   { "jaH",              { Jv, XX, cond_jump_flag } },
1749   /* 88 */
1750   { "jsH",              { Jv, XX, cond_jump_flag } },
1751   { "jnsH",             { Jv, XX, cond_jump_flag } },
1752   { "jpH",              { Jv, XX, cond_jump_flag } },
1753   { "jnpH",             { Jv, XX, cond_jump_flag } },
1754   { "jlH",              { Jv, XX, cond_jump_flag } },
1755   { "jgeH",             { Jv, XX, cond_jump_flag } },
1756   { "jleH",             { Jv, XX, cond_jump_flag } },
1757   { "jgH",              { Jv, XX, cond_jump_flag } },
1758   /* 90 */
1759   { "seto",             { Eb } },
1760   { "setno",            { Eb } },
1761   { "setb",             { Eb } },
1762   { "setae",            { Eb } },
1763   { "sete",             { Eb } },
1764   { "setne",            { Eb } },
1765   { "setbe",            { Eb } },
1766   { "seta",             { Eb } },
1767   /* 98 */
1768   { "sets",             { Eb } },
1769   { "setns",            { Eb } },
1770   { "setp",             { Eb } },
1771   { "setnp",            { Eb } },
1772   { "setl",             { Eb } },
1773   { "setge",            { Eb } },
1774   { "setle",            { Eb } },
1775   { "setg",             { Eb } },
1776   /* a0 */
1777   { "pushT",            { fs } },
1778   { "popT",             { fs } },
1779   { "cpuid",            { XX } },
1780   { "btS",              { Ev, Gv } },
1781   { "shldS",            { Ev, Gv, Ib } },
1782   { "shldS",            { Ev, Gv, CL } },
1783   { REG_TABLE (REG_0FA6) },
1784   { REG_TABLE (REG_0FA7) },
1785   /* a8 */
1786   { "pushT",            { gs } },
1787   { "popT",             { gs } },
1788   { "rsm",              { XX } },
1789   { "btsS",             { Ev, Gv } },
1790   { "shrdS",            { Ev, Gv, Ib } },
1791   { "shrdS",            { Ev, Gv, CL } },
1792   { REG_TABLE (REG_0FAE) },
1793   { "imulS",            { Gv, Ev } },
1794   /* b0 */
1795   { "cmpxchgB",         { Eb, Gb } },
1796   { "cmpxchgS",         { Ev, Gv } },
1797   { MOD_TABLE (MOD_0FB2) },
1798   { "btrS",             { Ev, Gv } },
1799   { MOD_TABLE (MOD_0FB4) },
1800   { MOD_TABLE (MOD_0FB5) },
1801   { "movz{bR|x}",       { Gv, Eb } },
1802   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1803   /* b8 */
1804   { PREFIX_TABLE (PREFIX_0FB8) },
1805   { "ud2b",             { XX } },
1806   { REG_TABLE (REG_0FBA) },
1807   { "btcS",             { Ev, Gv } },
1808   { "bsfS",             { Gv, Ev } },
1809   { PREFIX_TABLE (PREFIX_0FBD) },
1810   { "movs{bR|x}",       { Gv, Eb } },
1811   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1812   /* c0 */
1813   { "xaddB",            { Eb, Gb } },
1814   { "xaddS",            { Ev, Gv } },
1815   { PREFIX_TABLE (PREFIX_0FC2) },
1816   { PREFIX_TABLE (PREFIX_0FC3) },
1817   { "pinsrw",           { MX, Edqw, Ib } },
1818   { "pextrw",           { Gdq, MS, Ib } },
1819   { "shufpX",           { XM, EXx, Ib } },
1820   { REG_TABLE (REG_0FC7) },
1821   /* c8 */
1822   { "bswap",            { RMeAX } },
1823   { "bswap",            { RMeCX } },
1824   { "bswap",            { RMeDX } },
1825   { "bswap",            { RMeBX } },
1826   { "bswap",            { RMeSP } },
1827   { "bswap",            { RMeBP } },
1828   { "bswap",            { RMeSI } },
1829   { "bswap",            { RMeDI } },
1830   /* d0 */
1831   { PREFIX_TABLE (PREFIX_0FD0) },
1832   { "psrlw",            { MX, EM } },
1833   { "psrld",            { MX, EM } },
1834   { "psrlq",            { MX, EM } },
1835   { "paddq",            { MX, EM } },
1836   { "pmullw",           { MX, EM } },
1837   { PREFIX_TABLE (PREFIX_0FD6) },
1838   { MOD_TABLE (MOD_0FD7) },
1839   /* d8 */
1840   { "psubusb",          { MX, EM } },
1841   { "psubusw",          { MX, EM } },
1842   { "pminub",           { MX, EM } },
1843   { "pand",             { MX, EM } },
1844   { "paddusb",          { MX, EM } },
1845   { "paddusw",          { MX, EM } },
1846   { "pmaxub",           { MX, EM } },
1847   { "pandn",            { MX, EM } },
1848   /* e0 */
1849   { "pavgb",            { MX, EM } },
1850   { "psraw",            { MX, EM } },
1851   { "psrad",            { MX, EM } },
1852   { "pavgw",            { MX, EM } },
1853   { "pmulhuw",          { MX, EM } },
1854   { "pmulhw",           { MX, EM } },
1855   { PREFIX_TABLE (PREFIX_0FE6) },
1856   { PREFIX_TABLE (PREFIX_0FE7) },
1857   /* e8 */
1858   { "psubsb",           { MX, EM } },
1859   { "psubsw",           { MX, EM } },
1860   { "pminsw",           { MX, EM } },
1861   { "por",              { MX, EM } },
1862   { "paddsb",           { MX, EM } },
1863   { "paddsw",           { MX, EM } },
1864   { "pmaxsw",           { MX, EM } },
1865   { "pxor",             { MX, EM } },
1866   /* f0 */
1867   { PREFIX_TABLE (PREFIX_0FF0) },
1868   { "psllw",            { MX, EM } },
1869   { "pslld",            { MX, EM } },
1870   { "psllq",            { MX, EM } },
1871   { "pmuludq",          { MX, EM } },
1872   { "pmaddwd",          { MX, EM } },
1873   { "psadbw",           { MX, EM } },
1874   { PREFIX_TABLE (PREFIX_0FF7) },
1875   /* f8 */
1876   { "psubb",            { MX, EM } },
1877   { "psubw",            { MX, EM } },
1878   { "psubd",            { MX, EM } },
1879   { "psubq",            { MX, EM } },
1880   { "paddb",            { MX, EM } },
1881   { "paddw",            { MX, EM } },
1882   { "paddd",            { MX, EM } },
1883   { "(bad)",            { XX } },
1884 };
1885
1886 static const unsigned char onebyte_has_modrm[256] = {
1887   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1888   /*       -------------------------------        */
1889   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1890   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1891   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1892   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1893   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1894   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1895   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1896   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1897   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1898   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1899   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1900   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1901   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1902   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1903   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1904   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1905   /*       -------------------------------        */
1906   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1907 };
1908
1909 static const unsigned char twobyte_has_modrm[256] = {
1910   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1911   /*       -------------------------------        */
1912   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1913   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1914   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1915   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1916   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1917   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1918   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1919   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1920   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1921   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1922   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1923   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1924   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1925   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1926   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1927   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1928   /*       -------------------------------        */
1929   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1930 };
1931
1932 static char obuf[100];
1933 static char *obufp;
1934 static char scratchbuf[100];
1935 static unsigned char *start_codep;
1936 static unsigned char *insn_codep;
1937 static unsigned char *codep;
1938 static const char *lock_prefix;
1939 static const char *data_prefix;
1940 static const char *addr_prefix;
1941 static const char *repz_prefix;
1942 static const char *repnz_prefix;
1943 static disassemble_info *the_info;
1944 static struct
1945   {
1946     int mod;
1947     int reg;
1948     int rm;
1949   }
1950 modrm;
1951 static unsigned char need_modrm;
1952 static struct
1953   {
1954     int register_specifier;
1955     int length;
1956     int prefix;
1957     int w;
1958   }
1959 vex;
1960 static unsigned char need_vex;
1961 static unsigned char need_vex_reg;
1962 static unsigned char vex_w_done;
1963
1964 /* If we are accessing mod/rm/reg without need_modrm set, then the
1965    values are stale.  Hitting this abort likely indicates that you
1966    need to update onebyte_has_modrm or twobyte_has_modrm.  */
1967 #define MODRM_CHECK  if (!need_modrm) abort ()
1968
1969 static const char **names64;
1970 static const char **names32;
1971 static const char **names16;
1972 static const char **names8;
1973 static const char **names8rex;
1974 static const char **names_seg;
1975 static const char *index64;
1976 static const char *index32;
1977 static const char **index16;
1978
1979 static const char *intel_names64[] = {
1980   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1981   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1982 };
1983 static const char *intel_names32[] = {
1984   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1985   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1986 };
1987 static const char *intel_names16[] = {
1988   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1989   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1990 };
1991 static const char *intel_names8[] = {
1992   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1993 };
1994 static const char *intel_names8rex[] = {
1995   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1996   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1997 };
1998 static const char *intel_names_seg[] = {
1999   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2000 };
2001 static const char *intel_index64 = "riz";
2002 static const char *intel_index32 = "eiz";
2003 static const char *intel_index16[] = {
2004   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2005 };
2006
2007 static const char *att_names64[] = {
2008   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2009   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2010 };
2011 static const char *att_names32[] = {
2012   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2013   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2014 };
2015 static const char *att_names16[] = {
2016   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2017   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2018 };
2019 static const char *att_names8[] = {
2020   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2021 };
2022 static const char *att_names8rex[] = {
2023   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2024   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2025 };
2026 static const char *att_names_seg[] = {
2027   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2028 };
2029 static const char *att_index64 = "%riz";
2030 static const char *att_index32 = "%eiz";
2031 static const char *att_index16[] = {
2032   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2033 };
2034
2035 static const struct dis386 reg_table[][8] = {
2036   /* REG_80 */
2037   {
2038     { "addA",   { Eb, Ib } },
2039     { "orA",    { Eb, Ib } },
2040     { "adcA",   { Eb, Ib } },
2041     { "sbbA",   { Eb, Ib } },
2042     { "andA",   { Eb, Ib } },
2043     { "subA",   { Eb, Ib } },
2044     { "xorA",   { Eb, Ib } },
2045     { "cmpA",   { Eb, Ib } },
2046   },
2047   /* REG_81 */
2048   {
2049     { "addQ",   { Ev, Iv } },
2050     { "orQ",    { Ev, Iv } },
2051     { "adcQ",   { Ev, Iv } },
2052     { "sbbQ",   { Ev, Iv } },
2053     { "andQ",   { Ev, Iv } },
2054     { "subQ",   { Ev, Iv } },
2055     { "xorQ",   { Ev, Iv } },
2056     { "cmpQ",   { Ev, Iv } },
2057   },
2058   /* REG_82 */
2059   {
2060     { "addQ",   { Ev, sIb } },
2061     { "orQ",    { Ev, sIb } },
2062     { "adcQ",   { Ev, sIb } },
2063     { "sbbQ",   { Ev, sIb } },
2064     { "andQ",   { Ev, sIb } },
2065     { "subQ",   { Ev, sIb } },
2066     { "xorQ",   { Ev, sIb } },
2067     { "cmpQ",   { Ev, sIb } },
2068   },
2069   /* REG_8F */
2070   {
2071     { "popU",   { stackEv } },
2072     { "(bad)",  { XX } },
2073     { "(bad)",  { XX } },
2074     { "(bad)",  { XX } },
2075     { "(bad)",  { XX } },
2076     { "(bad)",  { XX } },
2077     { "(bad)",  { XX } },
2078     { "(bad)",  { XX } },
2079   },
2080   /* REG_C0 */
2081   {
2082     { "rolA",   { Eb, Ib } },
2083     { "rorA",   { Eb, Ib } },
2084     { "rclA",   { Eb, Ib } },
2085     { "rcrA",   { Eb, Ib } },
2086     { "shlA",   { Eb, Ib } },
2087     { "shrA",   { Eb, Ib } },
2088     { "(bad)",  { XX } },
2089     { "sarA",   { Eb, Ib } },
2090   },
2091   /* REG_C1 */
2092   {
2093     { "rolQ",   { Ev, Ib } },
2094     { "rorQ",   { Ev, Ib } },
2095     { "rclQ",   { Ev, Ib } },
2096     { "rcrQ",   { Ev, Ib } },
2097     { "shlQ",   { Ev, Ib } },
2098     { "shrQ",   { Ev, Ib } },
2099     { "(bad)",  { XX } },
2100     { "sarQ",   { Ev, Ib } },
2101   },
2102   /* REG_C6 */
2103   {
2104     { "movA",   { Eb, Ib } },
2105     { "(bad)",  { XX } },
2106     { "(bad)",  { XX } },
2107     { "(bad)",  { XX } },
2108     { "(bad)",  { XX } },
2109     { "(bad)",  { XX } },
2110     { "(bad)",  { XX } },
2111     { "(bad)",  { XX } },
2112   },
2113   /* REG_C7 */
2114   {
2115     { "movQ",   { Ev, Iv } },
2116     { "(bad)",  { XX } },
2117     { "(bad)",  { XX } },
2118     { "(bad)",  { XX } },
2119     { "(bad)",  { XX } },
2120     { "(bad)",  { XX } },
2121     { "(bad)",  { XX } },
2122     { "(bad)",  { XX } },
2123   },
2124   /* REG_D0 */
2125   {
2126     { "rolA",   { Eb, I1 } },
2127     { "rorA",   { Eb, I1 } },
2128     { "rclA",   { Eb, I1 } },
2129     { "rcrA",   { Eb, I1 } },
2130     { "shlA",   { Eb, I1 } },
2131     { "shrA",   { Eb, I1 } },
2132     { "(bad)",  { XX } },
2133     { "sarA",   { Eb, I1 } },
2134   },
2135   /* REG_D1 */
2136   {
2137     { "rolQ",   { Ev, I1 } },
2138     { "rorQ",   { Ev, I1 } },
2139     { "rclQ",   { Ev, I1 } },
2140     { "rcrQ",   { Ev, I1 } },
2141     { "shlQ",   { Ev, I1 } },
2142     { "shrQ",   { Ev, I1 } },
2143     { "(bad)",  { XX } },
2144     { "sarQ",   { Ev, I1 } },
2145   },
2146   /* REG_D2 */
2147   {
2148     { "rolA",   { Eb, CL } },
2149     { "rorA",   { Eb, CL } },
2150     { "rclA",   { Eb, CL } },
2151     { "rcrA",   { Eb, CL } },
2152     { "shlA",   { Eb, CL } },
2153     { "shrA",   { Eb, CL } },
2154     { "(bad)",  { XX } },
2155     { "sarA",   { Eb, CL } },
2156   },
2157   /* REG_D3 */
2158   {
2159     { "rolQ",   { Ev, CL } },
2160     { "rorQ",   { Ev, CL } },
2161     { "rclQ",   { Ev, CL } },
2162     { "rcrQ",   { Ev, CL } },
2163     { "shlQ",   { Ev, CL } },
2164     { "shrQ",   { Ev, CL } },
2165     { "(bad)",  { XX } },
2166     { "sarQ",   { Ev, CL } },
2167   },
2168   /* REG_F6 */
2169   {
2170     { "testA",  { Eb, Ib } },
2171     { "(bad)",  { XX } },
2172     { "notA",   { Eb } },
2173     { "negA",   { Eb } },
2174     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2175     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2176     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2177     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2178   },
2179   /* REG_F7 */
2180   {
2181     { "testQ",  { Ev, Iv } },
2182     { "(bad)",  { XX } },
2183     { "notQ",   { Ev } },
2184     { "negQ",   { Ev } },
2185     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2186     { "imulQ",  { Ev } },
2187     { "divQ",   { Ev } },
2188     { "idivQ",  { Ev } },
2189   },
2190   /* REG_FE */
2191   {
2192     { "incA",   { Eb } },
2193     { "decA",   { Eb } },
2194     { "(bad)",  { XX } },
2195     { "(bad)",  { XX } },
2196     { "(bad)",  { XX } },
2197     { "(bad)",  { XX } },
2198     { "(bad)",  { XX } },
2199     { "(bad)",  { XX } },
2200   },
2201   /* REG_FF */
2202   {
2203     { "incQ",   { Ev } },
2204     { "decQ",   { Ev } },
2205     { "callT",  { indirEv } },
2206     { "JcallT", { indirEp } },
2207     { "jmpT",   { indirEv } },
2208     { "JjmpT",  { indirEp } },
2209     { "pushU",  { stackEv } },
2210     { "(bad)",  { XX } },
2211   },
2212   /* REG_0F00 */
2213   {
2214     { "sldtD",  { Sv } },
2215     { "strD",   { Sv } },
2216     { "lldt",   { Ew } },
2217     { "ltr",    { Ew } },
2218     { "verr",   { Ew } },
2219     { "verw",   { Ew } },
2220     { "(bad)",  { XX } },
2221     { "(bad)",  { XX } },
2222   },
2223   /* REG_0F01 */
2224   {
2225     { MOD_TABLE (MOD_0F01_REG_0) },
2226     { MOD_TABLE (MOD_0F01_REG_1) },
2227     { MOD_TABLE (MOD_0F01_REG_2) },
2228     { MOD_TABLE (MOD_0F01_REG_3) },
2229     { "smswD",  { Sv } },
2230     { "(bad)",  { XX } },
2231     { "lmsw",   { Ew } },
2232     { MOD_TABLE (MOD_0F01_REG_7) },
2233   },
2234   /* REG_0F0D */
2235   {
2236     { "prefetch",       { Eb } },
2237     { "prefetchw",      { Eb } },
2238     { "(bad)",          { XX } },
2239     { "(bad)",          { XX } },
2240     { "(bad)",          { XX } },
2241     { "(bad)",          { XX } },
2242     { "(bad)",          { XX } },
2243     { "(bad)",          { XX } },
2244   },
2245   /* REG_0F18 */
2246   {
2247     { MOD_TABLE (MOD_0F18_REG_0) },
2248     { MOD_TABLE (MOD_0F18_REG_1) },
2249     { MOD_TABLE (MOD_0F18_REG_2) },
2250     { MOD_TABLE (MOD_0F18_REG_3) },
2251     { "(bad)",  { XX } },
2252     { "(bad)",  { XX } },
2253     { "(bad)",  { XX } },
2254     { "(bad)",  { XX } },
2255   },
2256   /* REG_0F71 */
2257   {
2258     { "(bad)",  { XX } },
2259     { "(bad)",  { XX } },
2260     { MOD_TABLE (MOD_0F71_REG_2) },
2261     { "(bad)",  { XX } },
2262     { MOD_TABLE (MOD_0F71_REG_4) },
2263     { "(bad)",  { XX } },
2264     { MOD_TABLE (MOD_0F71_REG_6) },
2265     { "(bad)",  { XX } },
2266   },
2267   /* REG_0F72 */
2268   {
2269     { "(bad)",  { XX } },
2270     { "(bad)",  { XX } },
2271     { MOD_TABLE (MOD_0F72_REG_2) },
2272     { "(bad)",  { XX } },
2273     { MOD_TABLE (MOD_0F72_REG_4) },
2274     { "(bad)",  { XX } },
2275     { MOD_TABLE (MOD_0F72_REG_6) },
2276     { "(bad)",  { XX } },
2277   },
2278   /* REG_0F73 */
2279   {
2280     { "(bad)",  { XX } },
2281     { "(bad)",  { XX } },
2282     { MOD_TABLE (MOD_0F73_REG_2) },
2283     { MOD_TABLE (MOD_0F73_REG_3) },
2284     { "(bad)",  { XX } },
2285     { "(bad)",  { XX } },
2286     { MOD_TABLE (MOD_0F73_REG_6) },
2287     { MOD_TABLE (MOD_0F73_REG_7) },
2288   },
2289   /* REG_0FA6 */
2290   {
2291     { "montmul",        { { OP_0f07, 0 } } },
2292     { "xsha1",          { { OP_0f07, 0 } } },
2293     { "xsha256",        { { OP_0f07, 0 } } },
2294     { "(bad)",          { { OP_0f07, 0 } } },
2295     { "(bad)",          { { OP_0f07, 0 } } },
2296     { "(bad)",          { { OP_0f07, 0 } } },
2297     { "(bad)",          { { OP_0f07, 0 } } },
2298     { "(bad)",          { { OP_0f07, 0 } } },
2299   },
2300   /* REG_0FA7 */
2301   {
2302     { "xstore-rng",     { { OP_0f07, 0 } } },
2303     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2304     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2305     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2306     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2307     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2308     { "(bad)",          { { OP_0f07, 0 } } },
2309     { "(bad)",          { { OP_0f07, 0 } } },
2310   },
2311   /* REG_0FAE */
2312   {
2313     { MOD_TABLE (MOD_0FAE_REG_0) },
2314     { MOD_TABLE (MOD_0FAE_REG_1) },
2315     { MOD_TABLE (MOD_0FAE_REG_2) },
2316     { MOD_TABLE (MOD_0FAE_REG_3) },
2317     { MOD_TABLE (MOD_0FAE_REG_4) },
2318     { MOD_TABLE (MOD_0FAE_REG_5) },
2319     { MOD_TABLE (MOD_0FAE_REG_6) },
2320     { MOD_TABLE (MOD_0FAE_REG_7) },
2321   },
2322   /* REG_0FBA */
2323   {
2324     { "(bad)",  { XX } },
2325     { "(bad)",  { XX } },
2326     { "(bad)",  { XX } },
2327     { "(bad)",  { XX } },
2328     { "btQ",    { Ev, Ib } },
2329     { "btsQ",   { Ev, Ib } },
2330     { "btrQ",   { Ev, Ib } },
2331     { "btcQ",   { Ev, Ib } },
2332   },
2333   /* REG_0FC7 */
2334   {
2335     { "(bad)",  { XX } },
2336     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2337     { "(bad)",  { XX } },
2338     { "(bad)",  { XX } },
2339     { "(bad)",  { XX } },
2340     { "(bad)",  { XX } },
2341     { MOD_TABLE (MOD_0FC7_REG_6) },
2342     { MOD_TABLE (MOD_0FC7_REG_7) },
2343   },
2344   /* REG_VEX_71 */
2345   {
2346     { "(bad)",  { XX } },
2347     { "(bad)",  { XX } },
2348     { MOD_TABLE (MOD_VEX_71_REG_2) },
2349     { "(bad)",  { XX } },
2350     { MOD_TABLE (MOD_VEX_71_REG_4) },
2351     { "(bad)",  { XX } },
2352     { MOD_TABLE (MOD_VEX_71_REG_6) },
2353     { "(bad)",  { XX } },
2354   },
2355   /* REG_VEX_72 */
2356   {
2357     { "(bad)",  { XX } },
2358     { "(bad)",  { XX } },
2359     { MOD_TABLE (MOD_VEX_72_REG_2) },
2360     { "(bad)",  { XX } },
2361     { MOD_TABLE (MOD_VEX_72_REG_4) },
2362     { "(bad)",  { XX } },
2363     { MOD_TABLE (MOD_VEX_72_REG_6) },
2364     { "(bad)",  { XX } },
2365   },
2366   /* REG_VEX_73 */
2367   {
2368     { "(bad)",  { XX } },
2369     { "(bad)",  { XX } },
2370     { MOD_TABLE (MOD_VEX_73_REG_2) },
2371     { MOD_TABLE (MOD_VEX_73_REG_3) },
2372     { "(bad)",  { XX } },
2373     { "(bad)",  { XX } },
2374     { MOD_TABLE (MOD_VEX_73_REG_6) },
2375     { MOD_TABLE (MOD_VEX_73_REG_7) },
2376   },
2377   /* REG_VEX_AE */
2378   {
2379     { "(bad)",  { XX } },
2380     { "(bad)",  { XX } },
2381     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2382     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2383     { "(bad)",  { XX } },
2384     { "(bad)",  { XX } },
2385     { "(bad)",  { XX } },
2386     { "(bad)",  { XX } },
2387   },
2388 };
2389
2390 static const struct dis386 prefix_table[][4] = {
2391   /* PREFIX_90 */
2392   {
2393     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2394     { "pause", { XX } },
2395     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2396     { "(bad)", { XX } },
2397   },
2398
2399   /* PREFIX_0F10 */
2400   {
2401     { "movups", { XM, EXx } },
2402     { "movss",  { XM, EXd } },
2403     { "movupd", { XM, EXx } },
2404     { "movsd",  { XM, EXq } },
2405   },
2406
2407   /* PREFIX_0F11 */
2408   {
2409     { "movups", { EXx, XM } },
2410     { "movss",  { EXd, XM } },
2411     { "movupd", { EXx, XM } },
2412     { "movsd",  { EXq, XM } },
2413   },
2414
2415   /* PREFIX_0F12 */
2416   {
2417     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2418     { "movsldup", { XM, EXx } },
2419     { "movlpd", { XM, EXq } },
2420     { "movddup", { XM, EXq } },
2421   },
2422
2423   /* PREFIX_0F16 */
2424   {
2425     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2426     { "movshdup", { XM, EXx } },
2427     { "movhpd", { XM, EXq } },
2428     { "(bad)",  { XX } },
2429   },
2430
2431   /* PREFIX_0F2A */
2432   {
2433     { "cvtpi2ps", { XM, EMCq } },
2434     { "cvtsi2ss%LQ", { XM, Ev } },
2435     { "cvtpi2pd", { XM, EMCq } },
2436     { "cvtsi2sd%LQ", { XM, Ev } },
2437   },
2438
2439   /* PREFIX_0F2B */
2440   {
2441     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2442     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2443     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2444     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2445   },
2446
2447   /* PREFIX_0F2C */
2448   {
2449     { "cvttps2pi", { MXC, EXq } },
2450     { "cvttss2siY", { Gv, EXd } },
2451     { "cvttpd2pi", { MXC, EXx } },
2452     { "cvttsd2siY", { Gv, EXq } },
2453   },
2454
2455   /* PREFIX_0F2D */
2456   {
2457     { "cvtps2pi", { MXC, EXq } },
2458     { "cvtss2siY", { Gv, EXd } },
2459     { "cvtpd2pi", { MXC, EXx } },
2460     { "cvtsd2siY", { Gv, EXq } },
2461   },
2462
2463   /* PREFIX_0F2E */
2464   {
2465     { "ucomiss",{ XM, EXd } },
2466     { "(bad)",  { XX } },
2467     { "ucomisd",{ XM, EXq } },
2468     { "(bad)",  { XX } },
2469   },
2470
2471   /* PREFIX_0F2F */
2472   {
2473     { "comiss", { XM, EXd } },
2474     { "(bad)",  { XX } },
2475     { "comisd", { XM, EXq } },
2476     { "(bad)",  { XX } },
2477   },
2478
2479   /* PREFIX_0F51 */
2480   {
2481     { "sqrtps", { XM, EXx } },
2482     { "sqrtss", { XM, EXd } },
2483     { "sqrtpd", { XM, EXx } },
2484     { "sqrtsd", { XM, EXq } },
2485   },
2486
2487   /* PREFIX_0F52 */
2488   {
2489     { "rsqrtps",{ XM, EXx } },
2490     { "rsqrtss",{ XM, EXd } },
2491     { "(bad)",  { XX } },
2492     { "(bad)",  { XX } },
2493   },
2494
2495   /* PREFIX_0F53 */
2496   {
2497     { "rcpps",  { XM, EXx } },
2498     { "rcpss",  { XM, EXd } },
2499     { "(bad)",  { XX } },
2500     { "(bad)",  { XX } },
2501   },
2502
2503   /* PREFIX_0F58 */
2504   {
2505     { "addps", { XM, EXx } },
2506     { "addss", { XM, EXd } },
2507     { "addpd", { XM, EXx } },
2508     { "addsd", { XM, EXq } },
2509   },
2510
2511   /* PREFIX_0F59 */
2512   {
2513     { "mulps",  { XM, EXx } },
2514     { "mulss",  { XM, EXd } },
2515     { "mulpd",  { XM, EXx } },
2516     { "mulsd",  { XM, EXq } },
2517   },
2518
2519   /* PREFIX_0F5A */
2520   {
2521     { "cvtps2pd", { XM, EXq } },
2522     { "cvtss2sd", { XM, EXd } },
2523     { "cvtpd2ps", { XM, EXx } },
2524     { "cvtsd2ss", { XM, EXq } },
2525   },
2526
2527   /* PREFIX_0F5B */
2528   {
2529     { "cvtdq2ps", { XM, EXx } },
2530     { "cvttps2dq", { XM, EXx } },
2531     { "cvtps2dq", { XM, EXx } },
2532     { "(bad)",  { XX } },
2533   },
2534
2535   /* PREFIX_0F5C */
2536   {
2537     { "subps",  { XM, EXx } },
2538     { "subss",  { XM, EXd } },
2539     { "subpd",  { XM, EXx } },
2540     { "subsd",  { XM, EXq } },
2541   },
2542
2543   /* PREFIX_0F5D */
2544   {
2545     { "minps",  { XM, EXx } },
2546     { "minss",  { XM, EXd } },
2547     { "minpd",  { XM, EXx } },
2548     { "minsd",  { XM, EXq } },
2549   },
2550
2551   /* PREFIX_0F5E */
2552   {
2553     { "divps",  { XM, EXx } },
2554     { "divss",  { XM, EXd } },
2555     { "divpd",  { XM, EXx } },
2556     { "divsd",  { XM, EXq } },
2557   },
2558
2559   /* PREFIX_0F5F */
2560   {
2561     { "maxps",  { XM, EXx } },
2562     { "maxss",  { XM, EXd } },
2563     { "maxpd",  { XM, EXx } },
2564     { "maxsd",  { XM, EXq } },
2565   },
2566
2567   /* PREFIX_0F60 */
2568   {
2569     { "punpcklbw",{ MX, EMd } },
2570     { "(bad)",  { XX } },
2571     { "punpcklbw",{ MX, EMx } },
2572     { "(bad)",  { XX } },
2573   },
2574
2575   /* PREFIX_0F61 */
2576   {
2577     { "punpcklwd",{ MX, EMd } },
2578     { "(bad)",  { XX } },
2579     { "punpcklwd",{ MX, EMx } },
2580     { "(bad)",  { XX } },
2581   },
2582
2583   /* PREFIX_0F62 */
2584   {
2585     { "punpckldq",{ MX, EMd } },
2586     { "(bad)",  { XX } },
2587     { "punpckldq",{ MX, EMx } },
2588     { "(bad)",  { XX } },
2589   },
2590
2591   /* PREFIX_0F6C */
2592   {
2593     { "(bad)",  { XX } },
2594     { "(bad)",  { XX } },
2595     { "punpcklqdq", { XM, EXx } },
2596     { "(bad)",  { XX } },
2597   },
2598
2599   /* PREFIX_0F6D */
2600   {
2601     { "(bad)",  { XX } },
2602     { "(bad)",  { XX } },
2603     { "punpckhqdq", { XM, EXx } },
2604     { "(bad)",  { XX } },
2605   },
2606
2607   /* PREFIX_0F6F */
2608   {
2609     { "movq",   { MX, EM } },
2610     { "movdqu", { XM, EXx } },
2611     { "movdqa", { XM, EXx } },
2612     { "(bad)",  { XX } },
2613   },
2614
2615   /* PREFIX_0F70 */
2616   {
2617     { "pshufw", { MX, EM, Ib } },
2618     { "pshufhw",{ XM, EXx, Ib } },
2619     { "pshufd", { XM, EXx, Ib } },
2620     { "pshuflw",{ XM, EXx, Ib } },
2621   },
2622
2623   /* PREFIX_0F73_REG_3 */
2624   {
2625     { "(bad)",  { XX } },
2626     { "(bad)",  { XX } },
2627     { "psrldq", { XS, Ib } },
2628     { "(bad)",  { XX } },
2629   },
2630
2631   /* PREFIX_0F73_REG_7 */
2632   {
2633     { "(bad)",  { XX } },
2634     { "(bad)",  { XX } },
2635     { "pslldq", { XS, Ib } },
2636     { "(bad)",  { XX } },
2637   },
2638
2639   /* PREFIX_0F78 */
2640   {
2641     {"vmread",  { Em, Gm } },
2642     {"(bad)",   { XX } },
2643     {"extrq",   { XS, Ib, Ib } },
2644     {"insertq", { XM, XS, Ib, Ib } },
2645   },
2646
2647   /* PREFIX_0F79 */
2648   {
2649     {"vmwrite", { Gm, Em } },
2650     {"(bad)",   { XX } },
2651     {"extrq",   { XM, XS } },
2652     {"insertq", { XM, XS } },
2653   },
2654
2655   /* PREFIX_0F7C */
2656   {
2657     { "(bad)",  { XX } },
2658     { "(bad)",  { XX } },
2659     { "haddpd", { XM, EXx } },
2660     { "haddps", { XM, EXx } },
2661   },
2662
2663   /* PREFIX_0F7D */
2664   {
2665     { "(bad)",  { XX } },
2666     { "(bad)",  { XX } },
2667     { "hsubpd", { XM, EXx } },
2668     { "hsubps", { XM, EXx } },
2669   },
2670
2671   /* PREFIX_0F7E */
2672   {
2673     { "movK",   { Edq, MX } },
2674     { "movq",   { XM, EXq } },
2675     { "movK",   { Edq, XM } },
2676     { "(bad)",  { XX } },
2677   },
2678
2679   /* PREFIX_0F7F */
2680   {
2681     { "movq",   { EM, MX } },
2682     { "movdqu", { EXx, XM } },
2683     { "movdqa", { EXx, XM } },
2684     { "(bad)",  { XX } },
2685   },
2686
2687   /* PREFIX_0FB8 */
2688   {
2689     { "(bad)", { XX } },
2690     { "popcntS", { Gv, Ev } },
2691     { "(bad)", { XX } },
2692     { "(bad)", { XX } },
2693   },
2694
2695   /* PREFIX_0FBD */
2696   {
2697     { "bsrS",   { Gv, Ev } },
2698     { "lzcntS", { Gv, Ev } },
2699     { "bsrS",   { Gv, Ev } },
2700     { "(bad)",  { XX } },
2701   },
2702
2703   /* PREFIX_0FC2 */
2704   {
2705     { "cmpps",  { XM, EXx, CMP } },
2706     { "cmpss",  { XM, EXd, CMP } },
2707     { "cmppd",  { XM, EXx, CMP } },
2708     { "cmpsd",  { XM, EXq, CMP } },
2709   },
2710
2711   /* PREFIX_0FC3 */
2712   {
2713     { "movntiS", { Ma, Gv } },
2714     { "(bad)",  { XX } },
2715     { "(bad)",  { XX } },
2716     { "(bad)",  { XX } },
2717   },
2718
2719   /* PREFIX_0FC7_REG_6 */
2720   {
2721     { "vmptrld",{ Mq } },
2722     { "vmxon",  { Mq } },
2723     { "vmclear",{ Mq } },
2724     { "(bad)",  { XX } },
2725   },
2726
2727   /* PREFIX_0FD0 */
2728   {
2729     { "(bad)",  { XX } },
2730     { "(bad)",  { XX } },
2731     { "addsubpd", { XM, EXx } },
2732     { "addsubps", { XM, EXx } },
2733   },
2734
2735   /* PREFIX_0FD6 */
2736   {
2737     { "(bad)",  { XX } },
2738     { "movq2dq",{ XM, MS } },
2739     { "movq",   { EXq, XM } },
2740     { "movdq2q",{ MX, XS } },
2741   },
2742
2743   /* PREFIX_0FE6 */
2744   {
2745     { "(bad)",  { XX } },
2746     { "cvtdq2pd", { XM, EXq } },
2747     { "cvttpd2dq", { XM, EXx } },
2748     { "cvtpd2dq", { XM, EXx } },
2749   },
2750
2751   /* PREFIX_0FE7 */
2752   {
2753     { "movntq", { Mq, MX } },
2754     { "(bad)",  { XX } },
2755     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2756     { "(bad)",  { XX } },
2757   },
2758
2759   /* PREFIX_0FF0 */
2760   {
2761     { "(bad)",  { XX } },
2762     { "(bad)",  { XX } },
2763     { "(bad)",  { XX } },
2764     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2765   },
2766
2767   /* PREFIX_0FF7 */
2768   {
2769     { "maskmovq", { MX, MS } },
2770     { "(bad)",  { XX } },
2771     { "maskmovdqu", { XM, XS } },
2772     { "(bad)",  { XX } },
2773   },
2774
2775   /* PREFIX_0F3810 */
2776   {
2777     { "(bad)",  { XX } },
2778     { "(bad)",  { XX } },
2779     { "pblendvb", { XM, EXx, XMM0 } },
2780     { "(bad)",  { XX } },
2781   },
2782
2783   /* PREFIX_0F3814 */
2784   {
2785     { "(bad)",  { XX } },
2786     { "(bad)",  { XX } },
2787     { "blendvps", { XM, EXx, XMM0 } },
2788     { "(bad)",  { XX } },
2789   },
2790
2791   /* PREFIX_0F3815 */
2792   {
2793     { "(bad)",  { XX } },
2794     { "(bad)",  { XX } },
2795     { "blendvpd", { XM, EXx, XMM0 } },
2796     { "(bad)",  { XX } },
2797   },
2798
2799   /* PREFIX_0F3817 */
2800   {
2801     { "(bad)",  { XX } },
2802     { "(bad)",  { XX } },
2803     { "ptest",  { XM, EXx } },
2804     { "(bad)",  { XX } },
2805   },
2806
2807   /* PREFIX_0F3820 */
2808   {
2809     { "(bad)",  { XX } },
2810     { "(bad)",  { XX } },
2811     { "pmovsxbw", { XM, EXq } },
2812     { "(bad)",  { XX } },
2813   },
2814
2815   /* PREFIX_0F3821 */
2816   {
2817     { "(bad)",  { XX } },
2818     { "(bad)",  { XX } },
2819     { "pmovsxbd", { XM, EXd } },
2820     { "(bad)",  { XX } },
2821   },
2822
2823   /* PREFIX_0F3822 */
2824   {
2825     { "(bad)",  { XX } },
2826     { "(bad)",  { XX } },
2827     { "pmovsxbq", { XM, EXw } },
2828     { "(bad)",  { XX } },
2829   },
2830
2831   /* PREFIX_0F3823 */
2832   {
2833     { "(bad)",  { XX } },
2834     { "(bad)",  { XX } },
2835     { "pmovsxwd", { XM, EXq } },
2836     { "(bad)",  { XX } },
2837   },
2838
2839   /* PREFIX_0F3824 */
2840   {
2841     { "(bad)",  { XX } },
2842     { "(bad)",  { XX } },
2843     { "pmovsxwq", { XM, EXd } },
2844     { "(bad)",  { XX } },
2845   },
2846
2847   /* PREFIX_0F3825 */
2848   {
2849     { "(bad)",  { XX } },
2850     { "(bad)",  { XX } },
2851     { "pmovsxdq", { XM, EXq } },
2852     { "(bad)",  { XX } },
2853   },
2854
2855   /* PREFIX_0F3828 */
2856   {
2857     { "(bad)",  { XX } },
2858     { "(bad)",  { XX } },
2859     { "pmuldq", { XM, EXx } },
2860     { "(bad)",  { XX } },
2861   },
2862
2863   /* PREFIX_0F3829 */
2864   {
2865     { "(bad)",  { XX } },
2866     { "(bad)",  { XX } },
2867     { "pcmpeqq", { XM, EXx } },
2868     { "(bad)",  { XX } },
2869   },
2870
2871   /* PREFIX_0F382A */
2872   {
2873     { "(bad)",  { XX } },
2874     { "(bad)",  { XX } },
2875     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2876     { "(bad)",  { XX } },
2877   },
2878
2879   /* PREFIX_0F382B */
2880   {
2881     { "(bad)",  { XX } },
2882     { "(bad)",  { XX } },
2883     { "packusdw", { XM, EXx } },
2884     { "(bad)",  { XX } },
2885   },
2886
2887   /* PREFIX_0F3830 */
2888   {
2889     { "(bad)",  { XX } },
2890     { "(bad)",  { XX } },
2891     { "pmovzxbw", { XM, EXq } },
2892     { "(bad)",  { XX } },
2893   },
2894
2895   /* PREFIX_0F3831 */
2896   {
2897     { "(bad)",  { XX } },
2898     { "(bad)",  { XX } },
2899     { "pmovzxbd", { XM, EXd } },
2900     { "(bad)",  { XX } },
2901   },
2902
2903   /* PREFIX_0F3832 */
2904   {
2905     { "(bad)",  { XX } },
2906     { "(bad)",  { XX } },
2907     { "pmovzxbq", { XM, EXw } },
2908     { "(bad)",  { XX } },
2909   },
2910
2911   /* PREFIX_0F3833 */
2912   {
2913     { "(bad)",  { XX } },
2914     { "(bad)",  { XX } },
2915     { "pmovzxwd", { XM, EXq } },
2916     { "(bad)",  { XX } },
2917   },
2918
2919   /* PREFIX_0F3834 */
2920   {
2921     { "(bad)",  { XX } },
2922     { "(bad)",  { XX } },
2923     { "pmovzxwq", { XM, EXd } },
2924     { "(bad)",  { XX } },
2925   },
2926
2927   /* PREFIX_0F3835 */
2928   {
2929     { "(bad)",  { XX } },
2930     { "(bad)",  { XX } },
2931     { "pmovzxdq", { XM, EXq } },
2932     { "(bad)",  { XX } },
2933   },
2934
2935   /* PREFIX_0F3837 */
2936   {
2937     { "(bad)",  { XX } },
2938     { "(bad)",  { XX } },
2939     { "pcmpgtq", { XM, EXx } },
2940     { "(bad)",  { XX } },
2941   },
2942
2943   /* PREFIX_0F3838 */
2944   {
2945     { "(bad)",  { XX } },
2946     { "(bad)",  { XX } },
2947     { "pminsb", { XM, EXx } },
2948     { "(bad)",  { XX } },
2949   },
2950
2951   /* PREFIX_0F3839 */
2952   {
2953     { "(bad)",  { XX } },
2954     { "(bad)",  { XX } },
2955     { "pminsd", { XM, EXx } },
2956     { "(bad)",  { XX } },
2957   },
2958
2959   /* PREFIX_0F383A */
2960   {
2961     { "(bad)",  { XX } },
2962     { "(bad)",  { XX } },
2963     { "pminuw", { XM, EXx } },
2964     { "(bad)",  { XX } },
2965   },
2966
2967   /* PREFIX_0F383B */
2968   {
2969     { "(bad)",  { XX } },
2970     { "(bad)",  { XX } },
2971     { "pminud", { XM, EXx } },
2972     { "(bad)",  { XX } },
2973   },
2974
2975   /* PREFIX_0F383C */
2976   {
2977     { "(bad)",  { XX } },
2978     { "(bad)",  { XX } },
2979     { "pmaxsb", { XM, EXx } },
2980     { "(bad)",  { XX } },
2981   },
2982
2983   /* PREFIX_0F383D */
2984   {
2985     { "(bad)",  { XX } },
2986     { "(bad)",  { XX } },
2987     { "pmaxsd", { XM, EXx } },
2988     { "(bad)",  { XX } },
2989   },
2990
2991   /* PREFIX_0F383E */
2992   {
2993     { "(bad)",  { XX } },
2994     { "(bad)",  { XX } },
2995     { "pmaxuw", { XM, EXx } },
2996     { "(bad)",  { XX } },
2997   },
2998
2999   /* PREFIX_0F383F */
3000   {
3001     { "(bad)",  { XX } },
3002     { "(bad)",  { XX } },
3003     { "pmaxud", { XM, EXx } },
3004     { "(bad)",  { XX } },
3005   },
3006
3007   /* PREFIX_0F3840 */
3008   {
3009     { "(bad)",  { XX } },
3010     { "(bad)",  { XX } },
3011     { "pmulld", { XM, EXx } },
3012     { "(bad)",  { XX } },
3013   },
3014
3015   /* PREFIX_0F3841 */
3016   {
3017     { "(bad)",  { XX } },
3018     { "(bad)",  { XX } },
3019     { "phminposuw", { XM, EXx } },
3020     { "(bad)",  { XX } },
3021   },
3022
3023   /* PREFIX_0F3880 */
3024   {
3025     { "(bad)",  { XX } },
3026     { "(bad)",  { XX } },
3027     { "invept", { Gm, Mo } },
3028     { "(bad)",  { XX } },
3029   },
3030
3031   /* PREFIX_0F3881 */
3032   {
3033     { "(bad)",  { XX } },
3034     { "(bad)",  { XX } },
3035     { "invvpid", { Gm, Mo } },
3036     { "(bad)",  { XX } },
3037   },
3038
3039   /* PREFIX_0F38DB */
3040   {
3041     { "(bad)",  { XX } },
3042     { "(bad)",  { XX } },
3043     { "aesimc", { XM, EXx } },
3044     { "(bad)",  { XX } },
3045   },
3046
3047   /* PREFIX_0F38DC */
3048   {
3049     { "(bad)",  { XX } },
3050     { "(bad)",  { XX } },
3051     { "aesenc", { XM, EXx } },
3052     { "(bad)",  { XX } },
3053   },
3054
3055   /* PREFIX_0F38DD */
3056   {
3057     { "(bad)",  { XX } },
3058     { "(bad)",  { XX } },
3059     { "aesenclast", { XM, EXx } },
3060     { "(bad)",  { XX } },
3061   },
3062
3063   /* PREFIX_0F38DE */
3064   {
3065     { "(bad)",  { XX } },
3066     { "(bad)",  { XX } },
3067     { "aesdec", { XM, EXx } },
3068     { "(bad)",  { XX } },
3069   },
3070
3071   /* PREFIX_0F38DF */
3072   {
3073     { "(bad)",  { XX } },
3074     { "(bad)",  { XX } },
3075     { "aesdeclast", { XM, EXx } },
3076     { "(bad)",  { XX } },
3077   },
3078
3079   /* PREFIX_0F38F0 */
3080   {
3081     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3082     { "(bad)",  { XX } },
3083     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3084     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3085   },
3086
3087   /* PREFIX_0F38F1 */
3088   {
3089     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3090     { "(bad)",  { XX } },
3091     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3092     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3093   },
3094
3095   /* PREFIX_0F3A08 */
3096   {
3097     { "(bad)",  { XX } },
3098     { "(bad)",  { XX } },
3099     { "roundps", { XM, EXx, Ib } },
3100     { "(bad)",  { XX } },
3101   },
3102
3103   /* PREFIX_0F3A09 */
3104   {
3105     { "(bad)",  { XX } },
3106     { "(bad)",  { XX } },
3107     { "roundpd", { XM, EXx, Ib } },
3108     { "(bad)",  { XX } },
3109   },
3110
3111   /* PREFIX_0F3A0A */
3112   {
3113     { "(bad)",  { XX } },
3114     { "(bad)",  { XX } },
3115     { "roundss", { XM, EXd, Ib } },
3116     { "(bad)",  { XX } },
3117   },
3118
3119   /* PREFIX_0F3A0B */
3120   {
3121     { "(bad)",  { XX } },
3122     { "(bad)",  { XX } },
3123     { "roundsd", { XM, EXq, Ib } },
3124     { "(bad)",  { XX } },
3125   },
3126
3127   /* PREFIX_0F3A0C */
3128   {
3129     { "(bad)",  { XX } },
3130     { "(bad)",  { XX } },
3131     { "blendps", { XM, EXx, Ib } },
3132     { "(bad)",  { XX } },
3133   },
3134
3135   /* PREFIX_0F3A0D */
3136   {
3137     { "(bad)",  { XX } },
3138     { "(bad)",  { XX } },
3139     { "blendpd", { XM, EXx, Ib } },
3140     { "(bad)",  { XX } },
3141   },
3142
3143   /* PREFIX_0F3A0E */
3144   {
3145     { "(bad)",  { XX } },
3146     { "(bad)",  { XX } },
3147     { "pblendw", { XM, EXx, Ib } },
3148     { "(bad)",  { XX } },
3149   },
3150
3151   /* PREFIX_0F3A14 */
3152   {
3153     { "(bad)",  { XX } },
3154     { "(bad)",  { XX } },
3155     { "pextrb", { Edqb, XM, Ib } },
3156     { "(bad)",  { XX } },
3157   },
3158
3159   /* PREFIX_0F3A15 */
3160   {
3161     { "(bad)",  { XX } },
3162     { "(bad)",  { XX } },
3163     { "pextrw", { Edqw, XM, Ib } },
3164     { "(bad)",  { XX } },
3165   },
3166
3167   /* PREFIX_0F3A16 */
3168   {
3169     { "(bad)",  { XX } },
3170     { "(bad)",  { XX } },
3171     { "pextrK", { Edq, XM, Ib } },
3172     { "(bad)",  { XX } },
3173   },
3174
3175   /* PREFIX_0F3A17 */
3176   {
3177     { "(bad)",  { XX } },
3178     { "(bad)",  { XX } },
3179     { "extractps", { Edqd, XM, Ib } },
3180     { "(bad)",  { XX } },
3181   },
3182
3183   /* PREFIX_0F3A20 */
3184   {
3185     { "(bad)",  { XX } },
3186     { "(bad)",  { XX } },
3187     { "pinsrb", { XM, Edqb, Ib } },
3188     { "(bad)",  { XX } },
3189   },
3190
3191   /* PREFIX_0F3A21 */
3192   {
3193     { "(bad)",  { XX } },
3194     { "(bad)",  { XX } },
3195     { "insertps", { XM, EXd, Ib } },
3196     { "(bad)",  { XX } },
3197   },
3198
3199   /* PREFIX_0F3A22 */
3200   {
3201     { "(bad)",  { XX } },
3202     { "(bad)",  { XX } },
3203     { "pinsrK", { XM, Edq, Ib } },
3204     { "(bad)",  { XX } },
3205   },
3206
3207   /* PREFIX_0F3A40 */
3208   {
3209     { "(bad)",  { XX } },
3210     { "(bad)",  { XX } },
3211     { "dpps",   { XM, EXx, Ib } },
3212     { "(bad)",  { XX } },
3213   },
3214
3215   /* PREFIX_0F3A41 */
3216   {
3217     { "(bad)",  { XX } },
3218     { "(bad)",  { XX } },
3219     { "dppd",   { XM, EXx, Ib } },
3220     { "(bad)",  { XX } },
3221   },
3222
3223   /* PREFIX_0F3A42 */
3224   {
3225     { "(bad)",  { XX } },
3226     { "(bad)",  { XX } },
3227     { "mpsadbw", { XM, EXx, Ib } },
3228     { "(bad)",  { XX } },
3229   },
3230
3231   /* PREFIX_0F3A44 */
3232   {
3233     { "(bad)",  { XX } },
3234     { "(bad)",  { XX } },
3235     { "pclmulqdq", { XM, EXx, PCLMUL } },
3236     { "(bad)",  { XX } },
3237   },
3238
3239   /* PREFIX_0F3A60 */
3240   {
3241     { "(bad)",  { XX } },
3242     { "(bad)",  { XX } },
3243     { "pcmpestrm", { XM, EXx, Ib } },
3244     { "(bad)",  { XX } },
3245   },
3246
3247   /* PREFIX_0F3A61 */
3248   {
3249     { "(bad)",  { XX } },
3250     { "(bad)",  { XX } },
3251     { "pcmpestri", { XM, EXx, Ib } },
3252     { "(bad)",  { XX } },
3253   },
3254
3255   /* PREFIX_0F3A62 */
3256   {
3257     { "(bad)",  { XX } },
3258     { "(bad)",  { XX } },
3259     { "pcmpistrm", { XM, EXx, Ib } },
3260     { "(bad)",  { XX } },
3261   },
3262
3263   /* PREFIX_0F3A63 */
3264   {
3265     { "(bad)",  { XX } },
3266     { "(bad)",  { XX } },
3267     { "pcmpistri", { XM, EXx, Ib } },
3268     { "(bad)",  { XX } },
3269   },
3270
3271   /* PREFIX_0F3ADF */
3272   {
3273     { "(bad)",  { XX } },
3274     { "(bad)",  { XX } },
3275     { "aeskeygenassist", { XM, EXx, Ib } },
3276     { "(bad)",  { XX } },
3277   },
3278
3279   /* PREFIX_VEX_10 */
3280   {
3281     { "vmovups", { XM, EXx } },
3282     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3283     { "vmovupd", { XM, EXx } },
3284     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3285   },
3286
3287   /* PREFIX_VEX_11 */
3288   {
3289     { "vmovups", { EXx, XM } },
3290     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3291     { "vmovupd", { EXx, XM } },
3292     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3293   },
3294
3295   /* PREFIX_VEX_12 */
3296   {
3297     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3298     { "vmovsldup", { XM, EXx } },
3299     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3300     { "vmovddup", { XM, EXymmq } },
3301   },
3302
3303   /* PREFIX_VEX_16 */
3304   {
3305     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3306     { "vmovshdup", { XM, EXx } },
3307     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3308     { "(bad)",  { XX } },
3309   },
3310
3311   /* PREFIX_VEX_2A */
3312   {
3313     { "(bad)",  { XX } },
3314     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3315     { "(bad)",  { XX } },
3316     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3317   },
3318
3319   /* PREFIX_VEX_2C */
3320   {
3321     { "(bad)",  { XX } },
3322     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3323     { "(bad)",  { XX } },
3324     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3325   },
3326
3327   /* PREFIX_VEX_2D */
3328   {
3329     { "(bad)",  { XX } },
3330     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3331     { "(bad)",  { XX } },
3332     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3333   },
3334
3335   /* PREFIX_VEX_2E */
3336   {
3337     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3338     { "(bad)",  { XX } },
3339     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3340     { "(bad)",  { XX } },
3341   },
3342
3343   /* PREFIX_VEX_2F */
3344   {
3345     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3346     { "(bad)",  { XX } },
3347     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3348     { "(bad)",  { XX } },
3349   },
3350
3351   /* PREFIX_VEX_51 */
3352   {
3353     { "vsqrtps", { XM, EXx } },
3354     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3355     { "vsqrtpd", { XM, EXx } },
3356     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3357   },
3358
3359   /* PREFIX_VEX_52 */
3360   {
3361     { "vrsqrtps", { XM, EXx } },
3362     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3363     { "(bad)",  { XX } },
3364     { "(bad)",  { XX } },
3365   },
3366
3367   /* PREFIX_VEX_53 */
3368   {
3369     { "vrcpps", { XM, EXx } },
3370     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3371     { "(bad)",  { XX } },
3372     { "(bad)",  { XX } },
3373   },
3374
3375   /* PREFIX_VEX_58 */
3376   {
3377     { "vaddps", { XM, Vex, EXx } },
3378     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3379     { "vaddpd", { XM, Vex, EXx } },
3380     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3381   },
3382
3383   /* PREFIX_VEX_59 */
3384   {
3385     { "vmulps", { XM, Vex, EXx } },
3386     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3387     { "vmulpd", { XM, Vex, EXx } },
3388     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3389   },
3390
3391   /* PREFIX_VEX_5A */
3392   {
3393     { "vcvtps2pd", { XM, EXxmmq } },
3394     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3395     { "vcvtpd2ps%XY", { XMM, EXx } },
3396     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3397   },
3398
3399   /* PREFIX_VEX_5B */
3400   {
3401     { "vcvtdq2ps", { XM, EXx } },
3402     { "vcvttps2dq", { XM, EXx } },
3403     { "vcvtps2dq", { XM, EXx } },
3404     { "(bad)",  { XX } },
3405   },
3406
3407   /* PREFIX_VEX_5C */
3408   {
3409     { "vsubps", { XM, Vex, EXx } },
3410     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3411     { "vsubpd", { XM, Vex, EXx } },
3412     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3413   },
3414
3415   /* PREFIX_VEX_5D */
3416   {
3417     { "vminps", { XM, Vex, EXx } },
3418     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3419     { "vminpd", { XM, Vex, EXx } },
3420     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3421   },
3422
3423   /* PREFIX_VEX_5E */
3424   {
3425     { "vdivps", { XM, Vex, EXx } },
3426     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3427     { "vdivpd", { XM, Vex, EXx } },
3428     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3429   },
3430
3431   /* PREFIX_VEX_5F */
3432   {
3433     { "vmaxps", { XM, Vex, EXx } },
3434     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3435     { "vmaxpd", { XM, Vex, EXx } },
3436     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3437   },
3438
3439   /* PREFIX_VEX_60 */
3440   {
3441     { "(bad)",  { XX } },
3442     { "(bad)",  { XX } },
3443     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3444     { "(bad)",  { XX } },
3445   },
3446
3447   /* PREFIX_VEX_61 */
3448   {
3449     { "(bad)",  { XX } },
3450     { "(bad)",  { XX } },
3451     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3452     { "(bad)",  { XX } },
3453   },
3454
3455   /* PREFIX_VEX_62 */
3456   {
3457     { "(bad)",  { XX } },
3458     { "(bad)",  { XX } },
3459     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3460     { "(bad)",  { XX } },
3461   },
3462
3463   /* PREFIX_VEX_63 */
3464   {
3465     { "(bad)",  { XX } },
3466     { "(bad)",  { XX } },
3467     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3468     { "(bad)",  { XX } },
3469   },
3470
3471   /* PREFIX_VEX_64 */
3472   {
3473     { "(bad)",  { XX } },
3474     { "(bad)",  { XX } },
3475     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3476     { "(bad)",  { XX } },
3477   },
3478
3479   /* PREFIX_VEX_65 */
3480   {
3481     { "(bad)",  { XX } },
3482     { "(bad)",  { XX } },
3483     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3484     { "(bad)",  { XX } },
3485   },
3486
3487   /* PREFIX_VEX_66 */
3488   {
3489     { "(bad)",  { XX } },
3490     { "(bad)",  { XX } },
3491     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3492     { "(bad)",  { XX } },
3493   },
3494
3495   /* PREFIX_VEX_67 */
3496   {
3497     { "(bad)",  { XX } },
3498     { "(bad)",  { XX } },
3499     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3500     { "(bad)",  { XX } },
3501   },
3502
3503   /* PREFIX_VEX_68 */
3504   {
3505     { "(bad)",  { XX } },
3506     { "(bad)",  { XX } },
3507     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3508     { "(bad)",  { XX } },
3509   },
3510
3511   /* PREFIX_VEX_69 */
3512   {
3513     { "(bad)",  { XX } },
3514     { "(bad)",  { XX } },
3515     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3516     { "(bad)",  { XX } },
3517   },
3518
3519   /* PREFIX_VEX_6A */
3520   {
3521     { "(bad)",  { XX } },
3522     { "(bad)",  { XX } },
3523     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3524     { "(bad)",  { XX } },
3525   },
3526
3527   /* PREFIX_VEX_6B */
3528   {
3529     { "(bad)",  { XX } },
3530     { "(bad)",  { XX } },
3531     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3532     { "(bad)",  { XX } },
3533   },
3534
3535   /* PREFIX_VEX_6C */
3536   {
3537     { "(bad)",  { XX } },
3538     { "(bad)",  { XX } },
3539     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3540     { "(bad)",  { XX } },
3541   },
3542
3543   /* PREFIX_VEX_6D */
3544   {
3545     { "(bad)",  { XX } },
3546     { "(bad)",  { XX } },
3547     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3548     { "(bad)",  { XX } },
3549   },
3550
3551   /* PREFIX_VEX_6E */
3552   {
3553     { "(bad)",  { XX } },
3554     { "(bad)",  { XX } },
3555     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3556     { "(bad)",  { XX } },
3557   },
3558
3559   /* PREFIX_VEX_6F */
3560   {
3561     { "(bad)",  { XX } },
3562     { "vmovdqu", { XM, EXx } },
3563     { "vmovdqa", { XM, EXx } },
3564     { "(bad)",  { XX } },
3565   },
3566
3567   /* PREFIX_VEX_70 */
3568   {
3569     { "(bad)",  { XX } },
3570     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3571     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3572     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3573   },
3574
3575   /* PREFIX_VEX_71_REG_2 */
3576   {
3577     { "(bad)",  { XX } },
3578     { "(bad)",  { XX } },
3579     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3580     { "(bad)",  { XX } },
3581   },
3582
3583   /* PREFIX_VEX_71_REG_4 */
3584   {
3585     { "(bad)",  { XX } },
3586     { "(bad)",  { XX } },
3587     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3588     { "(bad)",  { XX } },
3589   },
3590
3591   /* PREFIX_VEX_71_REG_6 */
3592   {
3593     { "(bad)",  { XX } },
3594     { "(bad)",  { XX } },
3595     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3596     { "(bad)",  { XX } },
3597   },
3598
3599   /* PREFIX_VEX_72_REG_2 */
3600   {
3601     { "(bad)",  { XX } },
3602     { "(bad)",  { XX } },
3603     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3604     { "(bad)",  { XX } },
3605   },
3606
3607   /* PREFIX_VEX_72_REG_4 */
3608   {
3609     { "(bad)",  { XX } },
3610     { "(bad)",  { XX } },
3611     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3612     { "(bad)",  { XX } },
3613   },
3614
3615   /* PREFIX_VEX_72_REG_6 */
3616   {
3617     { "(bad)",  { XX } },
3618     { "(bad)",  { XX } },
3619     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3620     { "(bad)",  { XX } },
3621   },
3622
3623   /* PREFIX_VEX_73_REG_2 */
3624   {
3625     { "(bad)",  { XX } },
3626     { "(bad)",  { XX } },
3627     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3628     { "(bad)",  { XX } },
3629   },
3630
3631   /* PREFIX_VEX_73_REG_3 */
3632   {
3633     { "(bad)",  { XX } },
3634     { "(bad)",  { XX } },
3635     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3636     { "(bad)",  { XX } },
3637   },
3638
3639   /* PREFIX_VEX_73_REG_6 */
3640   {
3641     { "(bad)",  { XX } },
3642     { "(bad)",  { XX } },
3643     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3644     { "(bad)",  { XX } },
3645   },
3646
3647   /* PREFIX_VEX_73_REG_7 */
3648   {
3649     { "(bad)",  { XX } },
3650     { "(bad)",  { XX } },
3651     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3652     { "(bad)",  { XX } },
3653   },
3654
3655   /* PREFIX_VEX_74 */
3656   {
3657     { "(bad)",  { XX } },
3658     { "(bad)",  { XX } },
3659     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3660     { "(bad)",  { XX } },
3661   },
3662
3663   /* PREFIX_VEX_75 */
3664   {
3665     { "(bad)",  { XX } },
3666     { "(bad)",  { XX } },
3667     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3668     { "(bad)",  { XX } },
3669   },
3670
3671   /* PREFIX_VEX_76 */
3672   {
3673     { "(bad)",  { XX } },
3674     { "(bad)",  { XX } },
3675     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3676     { "(bad)",  { XX } },
3677   },
3678
3679   /* PREFIX_VEX_77 */
3680   {
3681     { "",       { VZERO } },
3682     { "(bad)",  { XX } },
3683     { "(bad)",  { XX } },
3684     { "(bad)",  { XX } },
3685   },
3686
3687   /* PREFIX_VEX_7C */
3688   {
3689     { "(bad)",  { XX } },
3690     { "(bad)",  { XX } },
3691     { "vhaddpd", { XM, Vex, EXx } },
3692     { "vhaddps", { XM, Vex, EXx } },
3693   },
3694
3695   /* PREFIX_VEX_7D */
3696   {
3697     { "(bad)",  { XX } },
3698     { "(bad)",  { XX } },
3699     { "vhsubpd", { XM, Vex, EXx } },
3700     { "vhsubps", { XM, Vex, EXx } },
3701   },
3702
3703   /* PREFIX_VEX_7E */
3704   {
3705     { "(bad)",  { XX } },
3706     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3707     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3708     { "(bad)",  { XX } },
3709   },
3710
3711   /* PREFIX_VEX_7F */
3712   {
3713     { "(bad)",  { XX } },
3714     { "vmovdqu", { EXx, XM } },
3715     { "vmovdqa", { EXx, XM } },
3716     { "(bad)",  { XX } },
3717   },
3718
3719   /* PREFIX_VEX_C2 */
3720   {
3721     { "vcmpps", { XM, Vex, EXx, VCMP } },
3722     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3723     { "vcmppd", { XM, Vex, EXx, VCMP } },
3724     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3725   },
3726
3727   /* PREFIX_VEX_C4 */
3728   {
3729     { "(bad)",  { XX } },
3730     { "(bad)",  { XX } },
3731     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3732     { "(bad)",  { XX } },
3733   },
3734
3735   /* PREFIX_VEX_C5 */
3736   {
3737     { "(bad)",  { XX } },
3738     { "(bad)",  { XX } },
3739     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3740     { "(bad)",  { XX } },
3741   },
3742
3743   /* PREFIX_VEX_D0 */
3744   {
3745     { "(bad)",  { XX } },
3746     { "(bad)",  { XX } },
3747     { "vaddsubpd", { XM, Vex, EXx } },
3748     { "vaddsubps", { XM, Vex, EXx } },
3749   },
3750
3751   /* PREFIX_VEX_D1 */
3752   {
3753     { "(bad)",  { XX } },
3754     { "(bad)",  { XX } },
3755     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3756     { "(bad)",  { XX } },
3757   },
3758
3759   /* PREFIX_VEX_D2 */
3760   {
3761     { "(bad)",  { XX } },
3762     { "(bad)",  { XX } },
3763     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3764     { "(bad)",  { XX } },
3765   },
3766
3767   /* PREFIX_VEX_D3 */
3768   {
3769     { "(bad)",  { XX } },
3770     { "(bad)",  { XX } },
3771     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3772     { "(bad)",  { XX } },
3773   },
3774
3775   /* PREFIX_VEX_D4 */
3776   {
3777     { "(bad)",  { XX } },
3778     { "(bad)",  { XX } },
3779     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3780     { "(bad)",  { XX } },
3781   },
3782
3783   /* PREFIX_VEX_D5 */
3784   {
3785     { "(bad)",  { XX } },
3786     { "(bad)",  { XX } },
3787     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3788     { "(bad)",  { XX } },
3789   },
3790
3791   /* PREFIX_VEX_D6 */
3792   {
3793     { "(bad)",  { XX } },
3794     { "(bad)",  { XX } },
3795     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3796     { "(bad)",  { XX } },
3797   },
3798
3799   /* PREFIX_VEX_D7 */
3800   {
3801     { "(bad)",  { XX } },
3802     { "(bad)",  { XX } },
3803     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3804     { "(bad)",  { XX } },
3805   },
3806
3807   /* PREFIX_VEX_D8 */
3808   {
3809     { "(bad)",  { XX } },
3810     { "(bad)",  { XX } },
3811     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3812     { "(bad)",  { XX } },
3813   },
3814
3815   /* PREFIX_VEX_D9 */
3816   {
3817     { "(bad)",  { XX } },
3818     { "(bad)",  { XX } },
3819     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3820     { "(bad)",  { XX } },
3821   },
3822
3823   /* PREFIX_VEX_DA */
3824   {
3825     { "(bad)",  { XX } },
3826     { "(bad)",  { XX } },
3827     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3828     { "(bad)",  { XX } },
3829   },
3830
3831   /* PREFIX_VEX_DB */
3832   {
3833     { "(bad)",  { XX } },
3834     { "(bad)",  { XX } },
3835     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3836     { "(bad)",  { XX } },
3837   },
3838
3839   /* PREFIX_VEX_DC */
3840   {
3841     { "(bad)",  { XX } },
3842     { "(bad)",  { XX } },
3843     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3844     { "(bad)",  { XX } },
3845   },
3846
3847   /* PREFIX_VEX_DD */
3848   {
3849     { "(bad)",  { XX } },
3850     { "(bad)",  { XX } },
3851     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3852     { "(bad)",  { XX } },
3853   },
3854
3855   /* PREFIX_VEX_DE */
3856   {
3857     { "(bad)",  { XX } },
3858     { "(bad)",  { XX } },
3859     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3860     { "(bad)",  { XX } },
3861   },
3862
3863   /* PREFIX_VEX_DF */
3864   {
3865     { "(bad)",  { XX } },
3866     { "(bad)",  { XX } },
3867     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3868     { "(bad)",  { XX } },
3869   },
3870
3871   /* PREFIX_VEX_E0 */
3872   {
3873     { "(bad)",  { XX } },
3874     { "(bad)",  { XX } },
3875     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3876     { "(bad)",  { XX } },
3877   },
3878
3879   /* PREFIX_VEX_E1 */
3880   {
3881     { "(bad)",  { XX } },
3882     { "(bad)",  { XX } },
3883     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3884     { "(bad)",  { XX } },
3885   },
3886
3887   /* PREFIX_VEX_E2 */
3888   {
3889     { "(bad)",  { XX } },
3890     { "(bad)",  { XX } },
3891     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3892     { "(bad)",  { XX } },
3893   },
3894
3895   /* PREFIX_VEX_E3 */
3896   {
3897     { "(bad)",  { XX } },
3898     { "(bad)",  { XX } },
3899     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3900     { "(bad)",  { XX } },
3901   },
3902
3903   /* PREFIX_VEX_E4 */
3904   {
3905     { "(bad)",  { XX } },
3906     { "(bad)",  { XX } },
3907     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3908     { "(bad)",  { XX } },
3909   },
3910
3911   /* PREFIX_VEX_E5 */
3912   {
3913     { "(bad)",  { XX } },
3914     { "(bad)",  { XX } },
3915     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3916     { "(bad)",  { XX } },
3917   },
3918
3919   /* PREFIX_VEX_E6 */
3920   {
3921     { "(bad)",  { XX } },
3922     { "vcvtdq2pd", { XM, EXxmmq } },
3923     { "vcvttpd2dq%XY", { XMM, EXx } },
3924     { "vcvtpd2dq%XY", { XMM, EXx } },
3925   },
3926
3927   /* PREFIX_VEX_E7 */
3928   {
3929     { "(bad)",  { XX } },
3930     { "(bad)",  { XX } },
3931     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3932     { "(bad)",  { XX } },
3933   },
3934
3935   /* PREFIX_VEX_E8 */
3936   {
3937     { "(bad)",  { XX } },
3938     { "(bad)",  { XX } },
3939     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3940     { "(bad)",  { XX } },
3941   },
3942
3943   /* PREFIX_VEX_E9 */
3944   {
3945     { "(bad)",  { XX } },
3946     { "(bad)",  { XX } },
3947     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3948     { "(bad)",  { XX } },
3949   },
3950
3951   /* PREFIX_VEX_EA */
3952   {
3953     { "(bad)",  { XX } },
3954     { "(bad)",  { XX } },
3955     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3956     { "(bad)",  { XX } },
3957   },
3958
3959   /* PREFIX_VEX_EB */
3960   {
3961     { "(bad)",  { XX } },
3962     { "(bad)",  { XX } },
3963     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3964     { "(bad)",  { XX } },
3965   },
3966
3967   /* PREFIX_VEX_EC */
3968   {
3969     { "(bad)",  { XX } },
3970     { "(bad)",  { XX } },
3971     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3972     { "(bad)",  { XX } },
3973   },
3974
3975   /* PREFIX_VEX_ED */
3976   {
3977     { "(bad)",  { XX } },
3978     { "(bad)",  { XX } },
3979     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
3980     { "(bad)",  { XX } },
3981   },
3982
3983   /* PREFIX_VEX_EE */
3984   {
3985     { "(bad)",  { XX } },
3986     { "(bad)",  { XX } },
3987     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
3988     { "(bad)",  { XX } },
3989   },
3990
3991   /* PREFIX_VEX_EF */
3992   {
3993     { "(bad)",  { XX } },
3994     { "(bad)",  { XX } },
3995     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
3996     { "(bad)",  { XX } },
3997   },
3998
3999   /* PREFIX_VEX_F0 */
4000   {
4001     { "(bad)",  { XX } },
4002     { "(bad)",  { XX } },
4003     { "(bad)",  { XX } },
4004     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4005   },
4006
4007   /* PREFIX_VEX_F1 */
4008   {
4009     { "(bad)",  { XX } },
4010     { "(bad)",  { XX } },
4011     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4012     { "(bad)",  { XX } },
4013   },
4014
4015   /* PREFIX_VEX_F2 */
4016   {
4017     { "(bad)",  { XX } },
4018     { "(bad)",  { XX } },
4019     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4020     { "(bad)",  { XX } },
4021   },
4022
4023   /* PREFIX_VEX_F3 */
4024   {
4025     { "(bad)",  { XX } },
4026     { "(bad)",  { XX } },
4027     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4028     { "(bad)",  { XX } },
4029   },
4030
4031   /* PREFIX_VEX_F4 */
4032   {
4033     { "(bad)",  { XX } },
4034     { "(bad)",  { XX } },
4035     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4036     { "(bad)",  { XX } },
4037   },
4038
4039   /* PREFIX_VEX_F5 */
4040   {
4041     { "(bad)",  { XX } },
4042     { "(bad)",  { XX } },
4043     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4044     { "(bad)",  { XX } },
4045   },
4046
4047   /* PREFIX_VEX_F6 */
4048   {
4049     { "(bad)",  { XX } },
4050     { "(bad)",  { XX } },
4051     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4052     { "(bad)",  { XX } },
4053   },
4054
4055   /* PREFIX_VEX_F7 */
4056   {
4057     { "(bad)",  { XX } },
4058     { "(bad)",  { XX } },
4059     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4060     { "(bad)",  { XX } },
4061   },
4062
4063   /* PREFIX_VEX_F8 */
4064   {
4065     { "(bad)",  { XX } },
4066     { "(bad)",  { XX } },
4067     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4068     { "(bad)",  { XX } },
4069   },
4070
4071   /* PREFIX_VEX_F9 */
4072   {
4073     { "(bad)",  { XX } },
4074     { "(bad)",  { XX } },
4075     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4076     { "(bad)",  { XX } },
4077   },
4078
4079   /* PREFIX_VEX_FA */
4080   {
4081     { "(bad)",  { XX } },
4082     { "(bad)",  { XX } },
4083     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4084     { "(bad)",  { XX } },
4085   },
4086
4087   /* PREFIX_VEX_FB */
4088   {
4089     { "(bad)",  { XX } },
4090     { "(bad)",  { XX } },
4091     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4092     { "(bad)",  { XX } },
4093   },
4094
4095   /* PREFIX_VEX_FC */
4096   {
4097     { "(bad)",  { XX } },
4098     { "(bad)",  { XX } },
4099     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4100     { "(bad)",  { XX } },
4101   },
4102
4103   /* PREFIX_VEX_FD */
4104   {
4105     { "(bad)",  { XX } },
4106     { "(bad)",  { XX } },
4107     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4108     { "(bad)",  { XX } },
4109   },
4110
4111   /* PREFIX_VEX_FE */
4112   {
4113     { "(bad)",  { XX } },
4114     { "(bad)",  { XX } },
4115     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4116     { "(bad)",  { XX } },
4117   },
4118
4119   /* PREFIX_VEX_3800 */
4120   {
4121     { "(bad)",  { XX } },
4122     { "(bad)",  { XX } },
4123     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4124     { "(bad)",  { XX } },
4125   },
4126
4127   /* PREFIX_VEX_3801 */
4128   {
4129     { "(bad)",  { XX } },
4130     { "(bad)",  { XX } },
4131     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4132     { "(bad)",  { XX } },
4133   },
4134
4135   /* PREFIX_VEX_3802 */
4136   {
4137     { "(bad)",  { XX } },
4138     { "(bad)",  { XX } },
4139     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4140     { "(bad)",  { XX } },
4141   },
4142
4143   /* PREFIX_VEX_3803 */
4144   {
4145     { "(bad)",  { XX } },
4146     { "(bad)",  { XX } },
4147     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4148     { "(bad)",  { XX } },
4149   },
4150
4151   /* PREFIX_VEX_3804 */
4152   {
4153     { "(bad)",  { XX } },
4154     { "(bad)",  { XX } },
4155     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4156     { "(bad)",  { XX } },
4157   },
4158
4159   /* PREFIX_VEX_3805 */
4160   {
4161     { "(bad)",  { XX } },
4162     { "(bad)",  { XX } },
4163     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4164     { "(bad)",  { XX } },
4165   },
4166
4167   /* PREFIX_VEX_3806 */
4168   {
4169     { "(bad)",  { XX } },
4170     { "(bad)",  { XX } },
4171     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4172     { "(bad)",  { XX } },
4173   },
4174
4175   /* PREFIX_VEX_3807 */
4176   {
4177     { "(bad)",  { XX } },
4178     { "(bad)",  { XX } },
4179     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4180     { "(bad)",  { XX } },
4181   },
4182
4183   /* PREFIX_VEX_3808 */
4184   {
4185     { "(bad)",  { XX } },
4186     { "(bad)",  { XX } },
4187     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4188     { "(bad)",  { XX } },
4189   },
4190
4191   /* PREFIX_VEX_3809 */
4192   {
4193     { "(bad)",  { XX } },
4194     { "(bad)",  { XX } },
4195     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4196     { "(bad)",  { XX } },
4197   },
4198
4199   /* PREFIX_VEX_380A */
4200   {
4201     { "(bad)",  { XX } },
4202     { "(bad)",  { XX } },
4203     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4204     { "(bad)",  { XX } },
4205   },
4206
4207   /* PREFIX_VEX_380B */
4208   {
4209     { "(bad)",  { XX } },
4210     { "(bad)",  { XX } },
4211     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4212     { "(bad)",  { XX } },
4213   },
4214
4215   /* PREFIX_VEX_380C */
4216   {
4217     { "(bad)",  { XX } },
4218     { "(bad)",  { XX } },
4219     { "vpermilps", { XM, Vex, EXx } },
4220     { "(bad)",  { XX } },
4221   },
4222
4223   /* PREFIX_VEX_380D */
4224   {
4225     { "(bad)",  { XX } },
4226     { "(bad)",  { XX } },
4227     { "vpermilpd", { XM, Vex, EXx } },
4228     { "(bad)",  { XX } },
4229   },
4230
4231   /* PREFIX_VEX_380E */
4232   {
4233     { "(bad)",  { XX } },
4234     { "(bad)",  { XX } },
4235     { "vtestps", { XM, EXx } },
4236     { "(bad)",  { XX } },
4237   },
4238
4239   /* PREFIX_VEX_380F */
4240   {
4241     { "(bad)",  { XX } },
4242     { "(bad)",  { XX } },
4243     { "vtestpd", { XM, EXx } },
4244     { "(bad)",  { XX } },
4245   },
4246
4247   /* PREFIX_VEX_3817 */
4248   {
4249     { "(bad)",  { XX } },
4250     { "(bad)",  { XX } },
4251     { "vptest", { XM, EXx } },
4252     { "(bad)",  { XX } },
4253   },
4254
4255   /* PREFIX_VEX_3818 */
4256   {
4257     { "(bad)",  { XX } },
4258     { "(bad)",  { XX } },
4259     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4260     { "(bad)",  { XX } },
4261   },
4262
4263   /* PREFIX_VEX_3819 */
4264   {
4265     { "(bad)",  { XX } },
4266     { "(bad)",  { XX } },
4267     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4268     { "(bad)",  { XX } },
4269   },
4270
4271   /* PREFIX_VEX_381A */
4272   {
4273     { "(bad)",  { XX } },
4274     { "(bad)",  { XX } },
4275     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4276     { "(bad)",  { XX } },
4277   },
4278
4279   /* PREFIX_VEX_381C */
4280   {
4281     { "(bad)",  { XX } },
4282     { "(bad)",  { XX } },
4283     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4284     { "(bad)",  { XX } },
4285   },
4286
4287   /* PREFIX_VEX_381D */
4288   {
4289     { "(bad)",  { XX } },
4290     { "(bad)",  { XX } },
4291     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4292     { "(bad)",  { XX } },
4293   },
4294
4295   /* PREFIX_VEX_381E */
4296   {
4297     { "(bad)",  { XX } },
4298     { "(bad)",  { XX } },
4299     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4300     { "(bad)",  { XX } },
4301   },
4302
4303   /* PREFIX_VEX_3820 */
4304   {
4305     { "(bad)",  { XX } },
4306     { "(bad)",  { XX } },
4307     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4308     { "(bad)",  { XX } },
4309   },
4310
4311   /* PREFIX_VEX_3821 */
4312   {
4313     { "(bad)",  { XX } },
4314     { "(bad)",  { XX } },
4315     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4316     { "(bad)",  { XX } },
4317   },
4318
4319   /* PREFIX_VEX_3822 */
4320   {
4321     { "(bad)",  { XX } },
4322     { "(bad)",  { XX } },
4323     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4324     { "(bad)",  { XX } },
4325   },
4326
4327   /* PREFIX_VEX_3823 */
4328   {
4329     { "(bad)",  { XX } },
4330     { "(bad)",  { XX } },
4331     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4332     { "(bad)",  { XX } },
4333   },
4334
4335   /* PREFIX_VEX_3824 */
4336   {
4337     { "(bad)",  { XX } },
4338     { "(bad)",  { XX } },
4339     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4340     { "(bad)",  { XX } },
4341   },
4342
4343   /* PREFIX_VEX_3825 */
4344   {
4345     { "(bad)",  { XX } },
4346     { "(bad)",  { XX } },
4347     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4348     { "(bad)",  { XX } },
4349   },
4350
4351   /* PREFIX_VEX_3828 */
4352   {
4353     { "(bad)",  { XX } },
4354     { "(bad)",  { XX } },
4355     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4356     { "(bad)",  { XX } },
4357   },
4358
4359   /* PREFIX_VEX_3829 */
4360   {
4361     { "(bad)",  { XX } },
4362     { "(bad)",  { XX } },
4363     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4364     { "(bad)",  { XX } },
4365   },
4366
4367   /* PREFIX_VEX_382A */
4368   {
4369     { "(bad)",  { XX } },
4370     { "(bad)",  { XX } },
4371     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4372     { "(bad)",  { XX } },
4373   },
4374
4375   /* PREFIX_VEX_382B */
4376   {
4377     { "(bad)",  { XX } },
4378     { "(bad)",  { XX } },
4379     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4380     { "(bad)",  { XX } },
4381   },
4382
4383   /* PREFIX_VEX_382C */
4384   {
4385     { "(bad)",  { XX } },
4386     { "(bad)",  { XX } },
4387      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4388     { "(bad)",  { XX } },
4389   },
4390
4391   /* PREFIX_VEX_382D */
4392   {
4393     { "(bad)",  { XX } },
4394     { "(bad)",  { XX } },
4395      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4396     { "(bad)",  { XX } },
4397   },
4398
4399   /* PREFIX_VEX_382E */
4400   {
4401     { "(bad)",  { XX } },
4402     { "(bad)",  { XX } },
4403      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4404     { "(bad)",  { XX } },
4405   },
4406
4407   /* PREFIX_VEX_382F */
4408   {
4409     { "(bad)",  { XX } },
4410     { "(bad)",  { XX } },
4411      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4412     { "(bad)",  { XX } },
4413   },
4414
4415   /* PREFIX_VEX_3830 */
4416   {
4417     { "(bad)",  { XX } },
4418     { "(bad)",  { XX } },
4419     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4420     { "(bad)",  { XX } },
4421   },
4422
4423   /* PREFIX_VEX_3831 */
4424   {
4425     { "(bad)",  { XX } },
4426     { "(bad)",  { XX } },
4427     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4428     { "(bad)",  { XX } },
4429   },
4430
4431   /* PREFIX_VEX_3832 */
4432   {
4433     { "(bad)",  { XX } },
4434     { "(bad)",  { XX } },
4435     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4436     { "(bad)",  { XX } },
4437   },
4438
4439   /* PREFIX_VEX_3833 */
4440   {
4441     { "(bad)",  { XX } },
4442     { "(bad)",  { XX } },
4443     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4444     { "(bad)",  { XX } },
4445   },
4446
4447   /* PREFIX_VEX_3834 */
4448   {
4449     { "(bad)",  { XX } },
4450     { "(bad)",  { XX } },
4451     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4452     { "(bad)",  { XX } },
4453   },
4454
4455   /* PREFIX_VEX_3835 */
4456   {
4457     { "(bad)",  { XX } },
4458     { "(bad)",  { XX } },
4459     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4460     { "(bad)",  { XX } },
4461   },
4462
4463   /* PREFIX_VEX_3837 */
4464   {
4465     { "(bad)",  { XX } },
4466     { "(bad)",  { XX } },
4467     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4468     { "(bad)",  { XX } },
4469   },
4470
4471   /* PREFIX_VEX_3838 */
4472   {
4473     { "(bad)",  { XX } },
4474     { "(bad)",  { XX } },
4475     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4476     { "(bad)",  { XX } },
4477   },
4478
4479   /* PREFIX_VEX_3839 */
4480   {
4481     { "(bad)",  { XX } },
4482     { "(bad)",  { XX } },
4483     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4484     { "(bad)",  { XX } },
4485   },
4486
4487   /* PREFIX_VEX_383A */
4488   {
4489     { "(bad)",  { XX } },
4490     { "(bad)",  { XX } },
4491     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4492     { "(bad)",  { XX } },
4493   },
4494
4495   /* PREFIX_VEX_383B */
4496   {
4497     { "(bad)",  { XX } },
4498     { "(bad)",  { XX } },
4499     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4500     { "(bad)",  { XX } },
4501   },
4502
4503   /* PREFIX_VEX_383C */
4504   {
4505     { "(bad)",  { XX } },
4506     { "(bad)",  { XX } },
4507     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4508     { "(bad)",  { XX } },
4509   },
4510
4511   /* PREFIX_VEX_383D */
4512   {
4513     { "(bad)",  { XX } },
4514     { "(bad)",  { XX } },
4515     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4516     { "(bad)",  { XX } },
4517   },
4518
4519   /* PREFIX_VEX_383E */
4520   {
4521     { "(bad)",  { XX } },
4522     { "(bad)",  { XX } },
4523     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4524     { "(bad)",  { XX } },
4525   },
4526
4527   /* PREFIX_VEX_383F */
4528   {
4529     { "(bad)",  { XX } },
4530     { "(bad)",  { XX } },
4531     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4532     { "(bad)",  { XX } },
4533   },
4534
4535   /* PREFIX_VEX_3840 */
4536   {
4537     { "(bad)",  { XX } },
4538     { "(bad)",  { XX } },
4539     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4540     { "(bad)",  { XX } },
4541   },
4542
4543   /* PREFIX_VEX_3841 */
4544   {
4545     { "(bad)",  { XX } },
4546     { "(bad)",  { XX } },
4547     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4548     { "(bad)",  { XX } },
4549   },
4550
4551   /* PREFIX_VEX_38DB */
4552   {
4553     { "(bad)",  { XX } },
4554     { "(bad)",  { XX } },
4555     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4556     { "(bad)",  { XX } },
4557   },
4558
4559   /* PREFIX_VEX_38DC */
4560   {
4561     { "(bad)",  { XX } },
4562     { "(bad)",  { XX } },
4563     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4564     { "(bad)",  { XX } },
4565   },
4566
4567   /* PREFIX_VEX_38DD */
4568   {
4569     { "(bad)",  { XX } },
4570     { "(bad)",  { XX } },
4571     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4572     { "(bad)",  { XX } },
4573   },
4574
4575   /* PREFIX_VEX_38DE */
4576   {
4577     { "(bad)",  { XX } },
4578     { "(bad)",  { XX } },
4579     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4580     { "(bad)",  { XX } },
4581   },
4582
4583   /* PREFIX_VEX_38DF */
4584   {
4585     { "(bad)",  { XX } },
4586     { "(bad)",  { XX } },
4587     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4588     { "(bad)",  { XX } },
4589   },
4590
4591   /* PREFIX_VEX_3A04 */
4592   {
4593     { "(bad)",  { XX } },
4594     { "(bad)",  { XX } },
4595     { "vpermilps", { XM, EXx, Ib } },
4596     { "(bad)",  { XX } },
4597   },
4598
4599   /* PREFIX_VEX_3A05 */
4600   {
4601     { "(bad)",  { XX } },
4602     { "(bad)",  { XX } },
4603     { "vpermilpd", { XM, EXx, Ib } },
4604     { "(bad)",  { XX } },
4605   },
4606
4607   /* PREFIX_VEX_3A06 */
4608   {
4609     { "(bad)",  { XX } },
4610     { "(bad)",  { XX } },
4611     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4612     { "(bad)",  { XX } },
4613   },
4614
4615   /* PREFIX_VEX_3A08 */
4616   {
4617     { "(bad)",  { XX } },
4618     { "(bad)",  { XX } },
4619     { "vroundps", { XM, EXx, Ib } },
4620     { "(bad)",  { XX } },
4621   },
4622
4623   /* PREFIX_VEX_3A09 */
4624   {
4625     { "(bad)",  { XX } },
4626     { "(bad)",  { XX } },
4627     { "vroundpd", { XM, EXx, Ib } },
4628     { "(bad)",  { XX } },
4629   },
4630
4631   /* PREFIX_VEX_3A0A */
4632   {
4633     { "(bad)",  { XX } },
4634     { "(bad)",  { XX } },
4635     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4636     { "(bad)",  { XX } },
4637   },
4638
4639   /* PREFIX_VEX_3A0B */
4640   {
4641     { "(bad)",  { XX } },
4642     { "(bad)",  { XX } },
4643     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4644     { "(bad)",  { XX } },
4645   },
4646
4647   /* PREFIX_VEX_3A0C */
4648   {
4649     { "(bad)",  { XX } },
4650     { "(bad)",  { XX } },
4651     { "vblendps", { XM, Vex, EXx, Ib } },
4652     { "(bad)",  { XX } },
4653   },
4654
4655   /* PREFIX_VEX_3A0D */
4656   {
4657     { "(bad)",  { XX } },
4658     { "(bad)",  { XX } },
4659     { "vblendpd", { XM, Vex, EXx, Ib } },
4660     { "(bad)",  { XX } },
4661   },
4662
4663   /* PREFIX_VEX_3A0E */
4664   {
4665     { "(bad)",  { XX } },
4666     { "(bad)",  { XX } },
4667     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4668     { "(bad)",  { XX } },
4669   },
4670
4671   /* PREFIX_VEX_3A0F */
4672   {
4673     { "(bad)",  { XX } },
4674     { "(bad)",  { XX } },
4675     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4676     { "(bad)",  { XX } },
4677   },
4678
4679   /* PREFIX_VEX_3A14 */
4680   {
4681     { "(bad)",  { XX } },
4682     { "(bad)",  { XX } },
4683     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4684     { "(bad)",  { XX } },
4685   },
4686
4687   /* PREFIX_VEX_3A15 */
4688   {
4689     { "(bad)",  { XX } },
4690     { "(bad)",  { XX } },
4691     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4692     { "(bad)",  { XX } },
4693   },
4694
4695   /* PREFIX_VEX_3A16 */
4696   {
4697     { "(bad)",  { XX } },
4698     { "(bad)",  { XX } },
4699     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4700     { "(bad)",  { XX } },
4701   },
4702
4703   /* PREFIX_VEX_3A17 */
4704   {
4705     { "(bad)",  { XX } },
4706     { "(bad)",  { XX } },
4707     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4708     { "(bad)",  { XX } },
4709   },
4710
4711   /* PREFIX_VEX_3A18 */
4712   {
4713     { "(bad)",  { XX } },
4714     { "(bad)",  { XX } },
4715     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4716     { "(bad)",  { XX } },
4717   },
4718
4719   /* PREFIX_VEX_3A19 */
4720   {
4721     { "(bad)",  { XX } },
4722     { "(bad)",  { XX } },
4723     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4724     { "(bad)",  { XX } },
4725   },
4726
4727   /* PREFIX_VEX_3A20 */
4728   {
4729     { "(bad)",  { XX } },
4730     { "(bad)",  { XX } },
4731     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4732     { "(bad)",  { XX } },
4733   },
4734
4735   /* PREFIX_VEX_3A21 */
4736   {
4737     { "(bad)",  { XX } },
4738     { "(bad)",  { XX } },
4739     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4740     { "(bad)",  { XX } },
4741   },
4742
4743   /* PREFIX_VEX_3A22 */
4744   {
4745     { "(bad)",  { XX } },
4746     { "(bad)",  { XX } },
4747     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
4748     { "(bad)",  { XX } },
4749   },
4750
4751   /* PREFIX_VEX_3A40 */
4752   {
4753     { "(bad)",  { XX } },
4754     { "(bad)",  { XX } },
4755     { "vdpps",  { XM, Vex, EXx, Ib } },
4756     { "(bad)",  { XX } },
4757   },
4758
4759   /* PREFIX_VEX_3A41 */
4760   {
4761     { "(bad)",  { XX } },
4762     { "(bad)",  { XX } },
4763     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
4764     { "(bad)",  { XX } },
4765   },
4766
4767   /* PREFIX_VEX_3A42 */
4768   {
4769     { "(bad)",  { XX } },
4770     { "(bad)",  { XX } },
4771     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
4772     { "(bad)",  { XX } },
4773   },
4774
4775   /* PREFIX_VEX_3A48 */
4776   {
4777     { "(bad)",  { XX } },
4778     { "(bad)",  { XX } },
4779     { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4780     { "(bad)",  { XX } },
4781   },
4782
4783   /* PREFIX_VEX_3A49 */
4784   {
4785     { "(bad)",  { XX } },
4786     { "(bad)",  { XX } },
4787     { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4788     { "(bad)",  { XX } },
4789   },
4790
4791   /* PREFIX_VEX_3A4A */
4792   {
4793     { "(bad)",  { XX } },
4794     { "(bad)",  { XX } },
4795     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
4796     { "(bad)",  { XX } },
4797   },
4798
4799   /* PREFIX_VEX_3A4B */
4800   {
4801     { "(bad)",  { XX } },
4802     { "(bad)",  { XX } },
4803     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
4804     { "(bad)",  { XX } },
4805   },
4806
4807   /* PREFIX_VEX_3A4C */
4808   {
4809     { "(bad)",  { XX } },
4810     { "(bad)",  { XX } },
4811     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
4812     { "(bad)",  { XX } },
4813   },
4814
4815   /* PREFIX_VEX_3A5C */
4816   {
4817     { "(bad)",  { XX } },
4818     { "(bad)",  { XX } },
4819     { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4820     { "(bad)",  { XX } },
4821   },
4822
4823   /* PREFIX_VEX_3A5D */
4824   {
4825     { "(bad)",  { XX } },
4826     { "(bad)",  { XX } },
4827     { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4828     { "(bad)",  { XX } },
4829   },
4830
4831   /* PREFIX_VEX_3A5E */
4832   {
4833     { "(bad)",  { XX } },
4834     { "(bad)",  { XX } },
4835     { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4836     { "(bad)",  { XX } },
4837   },
4838
4839   /* PREFIX_VEX_3A5F */
4840   {
4841     { "(bad)",  { XX } },
4842     { "(bad)",  { XX } },
4843     { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4844     { "(bad)",  { XX } },
4845   },
4846
4847   /* PREFIX_VEX_3A60 */
4848   {
4849     { "(bad)",  { XX } },
4850     { "(bad)",  { XX } },
4851     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
4852     { "(bad)",  { XX } },
4853   },
4854
4855   /* PREFIX_VEX_3A61 */
4856   {
4857     { "(bad)",  { XX } },
4858     { "(bad)",  { XX } },
4859     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
4860     { "(bad)",  { XX } },
4861   },
4862
4863   /* PREFIX_VEX_3A62 */
4864   {
4865     { "(bad)",  { XX } },
4866     { "(bad)",  { XX } },
4867     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
4868     { "(bad)",  { XX } },
4869   },
4870
4871   /* PREFIX_VEX_3A63 */
4872   {
4873     { "(bad)",  { XX } },
4874     { "(bad)",  { XX } },
4875     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
4876     { "(bad)",  { XX } },
4877   },
4878
4879   /* PREFIX_VEX_3A68 */
4880   {
4881     { "(bad)",  { XX } },
4882     { "(bad)",  { XX } },
4883     { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4884     { "(bad)",  { XX } },
4885   },
4886
4887   /* PREFIX_VEX_3A69 */
4888   {
4889     { "(bad)",  { XX } },
4890     { "(bad)",  { XX } },
4891     { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4892     { "(bad)",  { XX } },
4893   },
4894
4895   /* PREFIX_VEX_3A6A */
4896   {
4897     { "(bad)",  { XX } },
4898     { "(bad)",  { XX } },
4899     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
4900     { "(bad)",  { XX } },
4901   },
4902
4903   /* PREFIX_VEX_3A6B */
4904   {
4905     { "(bad)",  { XX } },
4906     { "(bad)",  { XX } },
4907     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
4908     { "(bad)",  { XX } },
4909   },
4910
4911   /* PREFIX_VEX_3A6C */
4912   {
4913     { "(bad)",  { XX } },
4914     { "(bad)",  { XX } },
4915     { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4916     { "(bad)",  { XX } },
4917   },
4918
4919   /* PREFIX_VEX_3A6D */
4920   {
4921     { "(bad)",  { XX } },
4922     { "(bad)",  { XX } },
4923     { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4924     { "(bad)",  { XX } },
4925   },
4926
4927   /* PREFIX_VEX_3A6E */
4928   {
4929     { "(bad)",  { XX } },
4930     { "(bad)",  { XX } },
4931     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
4932     { "(bad)",  { XX } },
4933   },
4934
4935   /* PREFIX_VEX_3A6F */
4936   {
4937     { "(bad)",  { XX } },
4938     { "(bad)",  { XX } },
4939     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
4940     { "(bad)",  { XX } },
4941   },
4942
4943   /* PREFIX_VEX_3A78 */
4944   {
4945     { "(bad)",  { XX } },
4946     { "(bad)",  { XX } },
4947     { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4948     { "(bad)",  { XX } },
4949   },
4950
4951   /* PREFIX_VEX_3A79 */
4952   {
4953     { "(bad)",  { XX } },
4954     { "(bad)",  { XX } },
4955     { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4956     { "(bad)",  { XX } },
4957   },
4958
4959   /* PREFIX_VEX_3A7A */
4960   {
4961     { "(bad)",  { XX } },
4962     { "(bad)",  { XX } },
4963     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
4964     { "(bad)",  { XX } },
4965   },
4966
4967   /* PREFIX_VEX_3A7B */
4968   {
4969     { "(bad)",  { XX } },
4970     { "(bad)",  { XX } },
4971     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
4972     { "(bad)",  { XX } },
4973   },
4974
4975   /* PREFIX_VEX_3A7C */
4976   {
4977     { "(bad)",  { XX } },
4978     { "(bad)",  { XX } },
4979     { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4980     { "(bad)",  { XX } },
4981   },
4982
4983   /* PREFIX_VEX_3A7D */
4984   {
4985     { "(bad)",  { XX } },
4986     { "(bad)",  { XX } },
4987     { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4988     { "(bad)",  { XX } },
4989   },
4990
4991   /* PREFIX_VEX_3A7E */
4992   {
4993     { "(bad)",  { XX } },
4994     { "(bad)",  { XX } },
4995     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
4996     { "(bad)",  { XX } },
4997   },
4998
4999   /* PREFIX_VEX_3A7F */
5000   {
5001     { "(bad)",  { XX } },
5002     { "(bad)",  { XX } },
5003     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5004     { "(bad)",  { XX } },
5005   },
5006
5007   /* PREFIX_VEX_3ADF */
5008   {
5009     { "(bad)",  { XX } },
5010     { "(bad)",  { XX } },
5011     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5012     { "(bad)",  { XX } },
5013   },
5014 };
5015
5016 static const struct dis386 x86_64_table[][2] = {
5017   /* X86_64_06 */
5018   {
5019     { "push{T|}", { es } },
5020     { "(bad)", { XX } },
5021   },
5022
5023   /* X86_64_07 */
5024   {
5025     { "pop{T|}", { es } },
5026     { "(bad)", { XX } },
5027   },
5028
5029   /* X86_64_0D */
5030   {
5031     { "push{T|}", { cs } },
5032     { "(bad)", { XX } },
5033   },
5034
5035   /* X86_64_16 */
5036   {
5037     { "push{T|}", { ss } },
5038     { "(bad)", { XX } },
5039   },
5040
5041   /* X86_64_17 */
5042   {
5043     { "pop{T|}", { ss } },
5044     { "(bad)", { XX } },
5045   },
5046
5047   /* X86_64_1E */
5048   {
5049     { "push{T|}", { ds } },
5050     { "(bad)", { XX } },
5051   },
5052
5053   /* X86_64_1F */
5054   {
5055     { "pop{T|}", { ds } },
5056     { "(bad)", { XX } },
5057   },
5058
5059   /* X86_64_27 */
5060   {
5061     { "daa", { XX } },
5062     { "(bad)", { XX } },
5063   },
5064
5065   /* X86_64_2F */
5066   {
5067     { "das", { XX } },
5068     { "(bad)", { XX } },
5069   },
5070
5071   /* X86_64_37 */
5072   {
5073     { "aaa", { XX } },
5074     { "(bad)", { XX } },
5075   },
5076
5077   /* X86_64_3F */
5078   {
5079     { "aas", { XX } },
5080     { "(bad)", { XX } },
5081   },
5082
5083   /* X86_64_60 */
5084   {
5085     { "pusha{P|}", { XX } },
5086     { "(bad)", { XX } },
5087   },
5088
5089   /* X86_64_61 */
5090   {
5091     { "popa{P|}", { XX } },
5092     { "(bad)", { XX } },
5093   },
5094
5095   /* X86_64_62 */
5096   {
5097     { MOD_TABLE (MOD_62_32BIT) },
5098     { "(bad)", { XX } },
5099   },
5100
5101   /* X86_64_63 */
5102   {
5103     { "arpl", { Ew, Gw } },
5104     { "movs{lq|xd}", { Gv, Ed } },
5105   },
5106
5107   /* X86_64_6D */
5108   {
5109     { "ins{R|}", { Yzr, indirDX } },
5110     { "ins{G|}", { Yzr, indirDX } },
5111   },
5112
5113   /* X86_64_6F */
5114   {
5115     { "outs{R|}", { indirDXr, Xz } },
5116     { "outs{G|}", { indirDXr, Xz } },
5117   },
5118
5119   /* X86_64_9A */
5120   {
5121     { "Jcall{T|}", { Ap } },
5122     { "(bad)", { XX } },
5123   },
5124
5125   /* X86_64_C4 */
5126   {
5127     { MOD_TABLE (MOD_C4_32BIT) },
5128     { VEX_C4_TABLE (VEX_0F) },
5129   },
5130
5131   /* X86_64_C5 */
5132   {
5133     { MOD_TABLE (MOD_C5_32BIT) },
5134     { VEX_C5_TABLE (VEX_0F) },
5135   },
5136
5137   /* X86_64_CE */
5138   {
5139     { "into", { XX } },
5140     { "(bad)", { XX } },
5141   },
5142
5143   /* X86_64_D4 */
5144   {
5145     { "aam", { sIb } },
5146     { "(bad)", { XX } },
5147   },
5148
5149   /* X86_64_D5 */
5150   {
5151     { "aad", { sIb } },
5152     { "(bad)", { XX } },
5153   },
5154
5155   /* X86_64_EA */
5156   {
5157     { "Jjmp{T|}", { Ap } },
5158     { "(bad)", { XX } },
5159   },
5160
5161   /* X86_64_0F01_REG_0 */
5162   {
5163     { "sgdt{Q|IQ}", { M } },
5164     { "sgdt", { M } },
5165   },
5166
5167   /* X86_64_0F01_REG_1 */
5168   {
5169     { "sidt{Q|IQ}", { M } },
5170     { "sidt", { M } },
5171   },
5172
5173   /* X86_64_0F01_REG_2 */
5174   {
5175     { "lgdt{Q|Q}", { M } },
5176     { "lgdt", { M } },
5177   },
5178
5179   /* X86_64_0F01_REG_3 */
5180   {
5181     { "lidt{Q|Q}", { M } },
5182     { "lidt", { M } },
5183   },
5184 };
5185
5186 static const struct dis386 three_byte_table[][256] = {
5187   /* THREE_BYTE_0F24 */
5188   {
5189     /* 00 */
5190     { "fmaddps",        { { OP_DREX4, q_mode } } },
5191     { "fmaddpd",        { { OP_DREX4, q_mode } } },
5192     { "fmaddss",        { { OP_DREX4, w_mode } } },
5193     { "fmaddsd",        { { OP_DREX4, d_mode } } },
5194     { "fmaddps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5195     { "fmaddpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5196     { "fmaddss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5197     { "fmaddsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5198     /* 08 */
5199     { "fmsubps",        { { OP_DREX4, q_mode } } },
5200     { "fmsubpd",        { { OP_DREX4, q_mode } } },
5201     { "fmsubss",        { { OP_DREX4, w_mode } } },
5202     { "fmsubsd",        { { OP_DREX4, d_mode } } },
5203     { "fmsubps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5204     { "fmsubpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5205     { "fmsubss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5206     { "fmsubsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5207     /* 10 */
5208     { "fnmaddps",       { { OP_DREX4, q_mode } } },
5209     { "fnmaddpd",       { { OP_DREX4, q_mode } } },
5210     { "fnmaddss",       { { OP_DREX4, w_mode } } },
5211     { "fnmaddsd",       { { OP_DREX4, d_mode } } },
5212     { "fnmaddps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5213     { "fnmaddpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5214     { "fnmaddss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5215     { "fnmaddsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5216     /* 18 */
5217     { "fnmsubps",       { { OP_DREX4, q_mode } } },
5218     { "fnmsubpd",       { { OP_DREX4, q_mode } } },
5219     { "fnmsubss",       { { OP_DREX4, w_mode } } },
5220     { "fnmsubsd",       { { OP_DREX4, d_mode } } },
5221     { "fnmsubps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5222     { "fnmsubpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5223     { "fnmsubss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5224     { "fnmsubsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5225     /* 20 */
5226     { "permps",         { { OP_DREX4, q_mode } } },
5227     { "permpd",         { { OP_DREX4, q_mode } } },
5228     { "pcmov",          { { OP_DREX4, q_mode } } },
5229     { "pperm",          { { OP_DREX4, q_mode } } },
5230     { "permps",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5231     { "permpd",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5232     { "pcmov",          { { OP_DREX4, DREX_OC1 + w_mode } } },
5233     { "pperm",          { { OP_DREX4, DREX_OC1 + d_mode } } },
5234     /* 28 */
5235     { "(bad)",          { XX } },
5236     { "(bad)",          { XX } },
5237     { "(bad)",          { XX } },
5238     { "(bad)",          { XX } },
5239     { "(bad)",          { XX } },
5240     { "(bad)",          { XX } },
5241     { "(bad)",          { XX } },
5242     { "(bad)",          { XX } },
5243     /* 30 */
5244     { "(bad)",          { XX } },
5245     { "(bad)",          { XX } },
5246     { "(bad)",          { XX } },
5247     { "(bad)",          { XX } },
5248     { "(bad)",          { XX } },
5249     { "(bad)",          { XX } },
5250     { "(bad)",          { XX } },
5251     { "(bad)",          { XX } },
5252     /* 38 */
5253     { "(bad)",          { XX } },
5254     { "(bad)",          { XX } },
5255     { "(bad)",          { XX } },
5256     { "(bad)",          { XX } },
5257     { "(bad)",          { XX } },
5258     { "(bad)",          { XX } },
5259     { "(bad)",          { XX } },
5260     { "(bad)",          { XX } },
5261     /* 40 */
5262     { "protb",          { { OP_DREX3, q_mode } } },
5263     { "protw",          { { OP_DREX3, q_mode } } },
5264     { "protd",          { { OP_DREX3, q_mode } } },
5265     { "protq",          { { OP_DREX3, q_mode } } },
5266     { "pshlb",          { { OP_DREX3, q_mode } } },
5267     { "pshlw",          { { OP_DREX3, q_mode } } },
5268     { "pshld",          { { OP_DREX3, q_mode } } },
5269     { "pshlq",          { { OP_DREX3, q_mode } } },
5270     /* 48 */
5271     { "pshab",          { { OP_DREX3, q_mode } } },
5272     { "pshaw",          { { OP_DREX3, q_mode } } },
5273     { "pshad",          { { OP_DREX3, q_mode } } },
5274     { "pshaq",          { { OP_DREX3, q_mode } } },
5275     { "(bad)",          { XX } },
5276     { "(bad)",          { XX } },
5277     { "(bad)",          { XX } },
5278     { "(bad)",          { XX } },
5279     /* 50 */
5280     { "(bad)",          { XX } },
5281     { "(bad)",          { XX } },
5282     { "(bad)",          { XX } },
5283     { "(bad)",          { XX } },
5284     { "(bad)",          { XX } },
5285     { "(bad)",          { XX } },
5286     { "(bad)",          { XX } },
5287     { "(bad)",          { XX } },
5288     /* 58 */
5289     { "(bad)",          { XX } },
5290     { "(bad)",          { XX } },
5291     { "(bad)",          { XX } },
5292     { "(bad)",          { XX } },
5293     { "(bad)",          { XX } },
5294     { "(bad)",          { XX } },
5295     { "(bad)",          { XX } },
5296     { "(bad)",          { XX } },
5297     /* 60 */
5298     { "(bad)",          { XX } },
5299     { "(bad)",          { XX } },
5300     { "(bad)",          { XX } },
5301     { "(bad)",          { XX } },
5302     { "(bad)",          { XX } },
5303     { "(bad)",          { XX } },
5304     { "(bad)",          { XX } },
5305     { "(bad)",          { XX } },
5306     /* 68 */
5307     { "(bad)",          { XX } },
5308     { "(bad)",          { XX } },
5309     { "(bad)",          { XX } },
5310     { "(bad)",          { XX } },
5311     { "(bad)",          { XX } },
5312     { "(bad)",          { XX } },
5313     { "(bad)",          { XX } },
5314     { "(bad)",          { XX } },
5315     /* 70 */
5316     { "(bad)",          { XX } },
5317     { "(bad)",          { XX } },
5318     { "(bad)",          { XX } },
5319     { "(bad)",          { XX } },
5320     { "(bad)",          { XX } },
5321     { "(bad)",          { XX } },
5322     { "(bad)",          { XX } },
5323     { "(bad)",          { XX } },
5324     /* 78 */
5325     { "(bad)",          { XX } },
5326     { "(bad)",          { XX } },
5327     { "(bad)",          { XX } },
5328     { "(bad)",          { XX } },
5329     { "(bad)",          { XX } },
5330     { "(bad)",          { XX } },
5331     { "(bad)",          { XX } },
5332     { "(bad)",          { XX } },
5333     /* 80 */
5334     { "(bad)",          { XX } },
5335     { "(bad)",          { XX } },
5336     { "(bad)",          { XX } },
5337     { "(bad)",          { XX } },
5338     { "(bad)",          { XX } },
5339     { "pmacssww",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5340     { "pmacsswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5341     { "pmacssdql",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5342     /* 88 */
5343     { "(bad)",          { XX } },
5344     { "(bad)",          { XX } },
5345     { "(bad)",          { XX } },
5346     { "(bad)",          { XX } },
5347     { "(bad)",          { XX } },
5348     { "(bad)",          { XX } },
5349     { "pmacssdd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5350     { "pmacssdqh",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5351     /* 90 */
5352     { "(bad)",          { XX } },
5353     { "(bad)",          { XX } },
5354     { "(bad)",          { XX } },
5355     { "(bad)",          { XX } },
5356     { "(bad)",          { XX } },
5357     { "pmacsww",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5358     { "pmacswd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5359     { "pmacsdql",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5360     /* 98 */
5361     { "(bad)",          { XX } },
5362     { "(bad)",          { XX } },
5363     { "(bad)",          { XX } },
5364     { "(bad)",          { XX } },
5365     { "(bad)",          { XX } },
5366     { "(bad)",          { XX } },
5367     { "pmacsdd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5368     { "pmacsdqh",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5369     /* a0 */
5370     { "(bad)",          { XX } },
5371     { "(bad)",          { XX } },
5372     { "(bad)",          { XX } },
5373     { "(bad)",          { XX } },
5374     { "(bad)",          { XX } },
5375     { "(bad)",          { XX } },
5376     { "pmadcsswd",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5377     { "(bad)",          { XX } },
5378     /* a8 */
5379     { "(bad)",          { XX } },
5380     { "(bad)",          { XX } },
5381     { "(bad)",          { XX } },
5382     { "(bad)",          { XX } },
5383     { "(bad)",          { XX } },
5384     { "(bad)",          { XX } },
5385     { "(bad)",          { XX } },
5386     { "(bad)",          { XX } },
5387     /* b0 */
5388     { "(bad)",          { XX } },
5389     { "(bad)",          { XX } },
5390     { "(bad)",          { XX } },
5391     { "(bad)",          { XX } },
5392     { "(bad)",          { XX } },
5393     { "(bad)",          { XX } },
5394     { "pmadcswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5395     { "(bad)",          { XX } },
5396     /* b8 */
5397     { "(bad)",          { XX } },
5398     { "(bad)",          { XX } },
5399     { "(bad)",          { XX } },
5400     { "(bad)",          { XX } },
5401     { "(bad)",          { XX } },
5402     { "(bad)",          { XX } },
5403     { "(bad)",          { XX } },
5404     { "(bad)",          { XX } },
5405     /* c0 */
5406     { "(bad)",          { XX } },
5407     { "(bad)",          { XX } },
5408     { "(bad)",          { XX } },
5409     { "(bad)",          { XX } },
5410     { "(bad)",          { XX } },
5411     { "(bad)",          { XX } },
5412     { "(bad)",          { XX } },
5413     { "(bad)",          { XX } },
5414     /* c8 */
5415     { "(bad)",          { XX } },
5416     { "(bad)",          { XX } },
5417     { "(bad)",          { XX } },
5418     { "(bad)",          { XX } },
5419     { "(bad)",          { XX } },
5420     { "(bad)",          { XX } },
5421     { "(bad)",          { XX } },
5422     { "(bad)",          { XX } },
5423     /* d0 */
5424     { "(bad)",          { XX } },
5425     { "(bad)",          { XX } },
5426     { "(bad)",          { XX } },
5427     { "(bad)",          { XX } },
5428     { "(bad)",          { XX } },
5429     { "(bad)",          { XX } },
5430     { "(bad)",          { XX } },
5431     { "(bad)",          { XX } },
5432     /* d8 */
5433     { "(bad)",          { XX } },
5434     { "(bad)",          { XX } },
5435     { "(bad)",          { XX } },
5436     { "(bad)",          { XX } },
5437     { "(bad)",          { XX } },
5438     { "(bad)",          { XX } },
5439     { "(bad)",          { XX } },
5440     { "(bad)",          { XX } },
5441     /* e0 */
5442     { "(bad)",          { XX } },
5443     { "(bad)",          { XX } },
5444     { "(bad)",          { XX } },
5445     { "(bad)",          { XX } },
5446     { "(bad)",          { XX } },
5447     { "(bad)",          { XX } },
5448     { "(bad)",          { XX } },
5449     { "(bad)",          { XX } },
5450     /* e8 */
5451     { "(bad)",          { XX } },
5452     { "(bad)",          { XX } },
5453     { "(bad)",          { XX } },
5454     { "(bad)",          { XX } },
5455     { "(bad)",          { XX } },
5456     { "(bad)",          { XX } },
5457     { "(bad)",          { XX } },
5458     { "(bad)",          { XX } },
5459     /* f0 */
5460     { "(bad)",          { XX } },
5461     { "(bad)",          { XX } },
5462     { "(bad)",          { XX } },
5463     { "(bad)",          { XX } },
5464     { "(bad)",          { XX } },
5465     { "(bad)",          { XX } },
5466     { "(bad)",          { XX } },
5467     { "(bad)",          { XX } },
5468     /* f8 */
5469     { "(bad)",          { XX } },
5470     { "(bad)",          { XX } },
5471     { "(bad)",          { XX } },
5472     { "(bad)",          { XX } },
5473     { "(bad)",          { XX } },
5474     { "(bad)",          { XX } },
5475     { "(bad)",          { XX } },
5476     { "(bad)",          { XX } },
5477   },
5478   /* THREE_BYTE_0F25 */
5479   {
5480     /* 00 */
5481     { "(bad)",          { XX } },
5482     { "(bad)",          { XX } },
5483     { "(bad)",          { XX } },
5484     { "(bad)",          { XX } },
5485     { "(bad)",          { XX } },
5486     { "(bad)",          { XX } },
5487     { "(bad)",          { XX } },
5488     { "(bad)",          { XX } },
5489     /* 08 */
5490     { "(bad)",          { XX } },
5491     { "(bad)",          { XX } },
5492     { "(bad)",          { XX } },
5493     { "(bad)",          { XX } },
5494     { "(bad)",          { XX } },
5495     { "(bad)",          { XX } },
5496     { "(bad)",          { XX } },
5497     { "(bad)",          { XX } },
5498     /* 10 */
5499     { "(bad)",          { XX } },
5500     { "(bad)",          { XX } },
5501     { "(bad)",          { XX } },
5502     { "(bad)",          { XX } },
5503     { "(bad)",          { XX } },
5504     { "(bad)",          { XX } },
5505     { "(bad)",          { XX } },
5506     { "(bad)",          { XX } },
5507     /* 18 */
5508     { "(bad)",          { XX } },
5509     { "(bad)",          { XX } },
5510     { "(bad)",          { XX } },
5511     { "(bad)",          { XX } },
5512     { "(bad)",          { XX } },
5513     { "(bad)",          { XX } },
5514     { "(bad)",          { XX } },
5515     { "(bad)",          { XX } },
5516     /* 20 */
5517     { "(bad)",          { XX } },
5518     { "(bad)",          { XX } },
5519     { "(bad)",          { XX } },
5520     { "(bad)",          { XX } },
5521     { "(bad)",          { XX } },
5522     { "(bad)",          { XX } },
5523     { "(bad)",          { XX } },
5524     { "(bad)",          { XX } },
5525     /* 28 */
5526     { "(bad)",          { XX } },
5527     { "(bad)",          { XX } },
5528     { "(bad)",          { XX } },
5529     { "(bad)",          { XX } },
5530     { "comps",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5531     { "compd",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5532     { "comss",          { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5533     { "comsd",          { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5534     /* 30 */
5535     { "(bad)",          { XX } },
5536     { "(bad)",          { XX } },
5537     { "(bad)",          { XX } },
5538     { "(bad)",          { XX } },
5539     { "(bad)",          { XX } },
5540     { "(bad)",          { XX } },
5541     { "(bad)",          { XX } },
5542     { "(bad)",          { XX } },
5543     /* 38 */
5544     { "(bad)",          { XX } },
5545     { "(bad)",          { XX } },
5546     { "(bad)",          { XX } },
5547     { "(bad)",          { XX } },
5548     { "(bad)",          { XX } },
5549     { "(bad)",          { XX } },
5550     { "(bad)",          { XX } },
5551     { "(bad)",          { XX } },
5552     /* 40 */
5553     { "(bad)",          { XX } },
5554     { "(bad)",          { XX } },
5555     { "(bad)",          { XX } },
5556     { "(bad)",          { XX } },
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     /* 48 */
5562     { "(bad)",          { XX } },
5563     { "(bad)",          { XX } },
5564     { "(bad)",          { XX } },
5565     { "(bad)",          { XX } },
5566     { "pcomb",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5567     { "pcomw",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5568     { "pcomd",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5569     { "pcomq",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5570     /* 50 */
5571     { "(bad)",          { XX } },
5572     { "(bad)",          { XX } },
5573     { "(bad)",          { XX } },
5574     { "(bad)",          { XX } },
5575     { "(bad)",          { XX } },
5576     { "(bad)",          { XX } },
5577     { "(bad)",          { XX } },
5578     { "(bad)",          { XX } },
5579     /* 58 */
5580     { "(bad)",          { XX } },
5581     { "(bad)",          { XX } },
5582     { "(bad)",          { XX } },
5583     { "(bad)",          { XX } },
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     { "(bad)",          { XX } },
5587     { "(bad)",          { XX } },
5588     /* 60 */
5589     { "(bad)",          { XX } },
5590     { "(bad)",          { XX } },
5591     { "(bad)",          { XX } },
5592     { "(bad)",          { XX } },
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     /* 68 */
5598     { "(bad)",          { XX } },
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     { "(bad)",          { XX } },
5602     { "pcomub",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5603     { "pcomuw",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5604     { "pcomud",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5605     { "pcomuq",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5606     /* 70 */
5607     { "(bad)",          { XX } },
5608     { "(bad)",          { XX } },
5609     { "(bad)",          { XX } },
5610     { "(bad)",          { XX } },
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     /* 78 */
5616     { "(bad)",          { XX } },
5617     { "(bad)",          { XX } },
5618     { "(bad)",          { XX } },
5619     { "(bad)",          { XX } },
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     /* 80 */
5625     { "(bad)",          { XX } },
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     { "(bad)",          { XX } },
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     /* 88 */
5634     { "(bad)",          { XX } },
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     { "(bad)",          { XX } },
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     /* 90 */
5643     { "(bad)",          { XX } },
5644     { "(bad)",          { XX } },
5645     { "(bad)",          { XX } },
5646     { "(bad)",          { XX } },
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     /* 98 */
5652     { "(bad)",          { XX } },
5653     { "(bad)",          { XX } },
5654     { "(bad)",          { XX } },
5655     { "(bad)",          { XX } },
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     /* a0 */
5661     { "(bad)",          { XX } },
5662     { "(bad)",          { XX } },
5663     { "(bad)",          { XX } },
5664     { "(bad)",          { XX } },
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     /* a8 */
5670     { "(bad)",          { XX } },
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     { "(bad)",          { XX } },
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     /* b0 */
5679     { "(bad)",          { XX } },
5680     { "(bad)",          { XX } },
5681     { "(bad)",          { XX } },
5682     { "(bad)",          { XX } },
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     /* b8 */
5688     { "(bad)",          { XX } },
5689     { "(bad)",          { XX } },
5690     { "(bad)",          { XX } },
5691     { "(bad)",          { XX } },
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     /* c0 */
5697     { "(bad)",          { XX } },
5698     { "(bad)",          { XX } },
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     /* c8 */
5706     { "(bad)",          { XX } },
5707     { "(bad)",          { XX } },
5708     { "(bad)",          { XX } },
5709     { "(bad)",          { XX } },
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     /* d0 */
5715     { "(bad)",          { XX } },
5716     { "(bad)",          { XX } },
5717     { "(bad)",          { XX } },
5718     { "(bad)",          { XX } },
5719     { "(bad)",          { XX } },
5720     { "(bad)",          { XX } },
5721     { "(bad)",          { XX } },
5722     { "(bad)",          { XX } },
5723     /* d8 */
5724     { "(bad)",          { XX } },
5725     { "(bad)",          { XX } },
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     /* e0 */
5733     { "(bad)",          { XX } },
5734     { "(bad)",          { XX } },
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     /* e8 */
5742     { "(bad)",          { XX } },
5743     { "(bad)",          { XX } },
5744     { "(bad)",          { XX } },
5745     { "(bad)",          { XX } },
5746     { "(bad)",          { XX } },
5747     { "(bad)",          { XX } },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     /* f0 */
5751     { "(bad)",          { XX } },
5752     { "(bad)",          { XX } },
5753     { "(bad)",          { XX } },
5754     { "(bad)",          { XX } },
5755     { "(bad)",          { XX } },
5756     { "(bad)",          { XX } },
5757     { "(bad)",          { XX } },
5758     { "(bad)",          { XX } },
5759     /* f8 */
5760     { "(bad)",          { XX } },
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763     { "(bad)",          { XX } },
5764     { "(bad)",          { XX } },
5765     { "(bad)",          { XX } },
5766     { "(bad)",          { XX } },
5767     { "(bad)",          { XX } },
5768   },
5769   /* THREE_BYTE_0F38 */
5770   {
5771     /* 00 */
5772     { "pshufb",         { MX, EM } },
5773     { "phaddw",         { MX, EM } },
5774     { "phaddd",         { MX, EM } },
5775     { "phaddsw",        { MX, EM } },
5776     { "pmaddubsw",      { MX, EM } },
5777     { "phsubw",         { MX, EM } },
5778     { "phsubd",         { MX, EM } },
5779     { "phsubsw",        { MX, EM } },
5780     /* 08 */
5781     { "psignb",         { MX, EM } },
5782     { "psignw",         { MX, EM } },
5783     { "psignd",         { MX, EM } },
5784     { "pmulhrsw",       { MX, EM } },
5785     { "(bad)",          { XX } },
5786     { "(bad)",          { XX } },
5787     { "(bad)",          { XX } },
5788     { "(bad)",          { XX } },
5789     /* 10 */
5790     { PREFIX_TABLE (PREFIX_0F3810) },
5791     { "(bad)",          { XX } },
5792     { "(bad)",          { XX } },
5793     { "(bad)",          { XX } },
5794     { PREFIX_TABLE (PREFIX_0F3814) },
5795     { PREFIX_TABLE (PREFIX_0F3815) },
5796     { "(bad)",          { XX } },
5797     { PREFIX_TABLE (PREFIX_0F3817) },
5798     /* 18 */
5799     { "(bad)",          { XX } },
5800     { "(bad)",          { XX } },
5801     { "(bad)",          { XX } },
5802     { "(bad)",          { XX } },
5803     { "pabsb",          { MX, EM } },
5804     { "pabsw",          { MX, EM } },
5805     { "pabsd",          { MX, EM } },
5806     { "(bad)",          { XX } },
5807     /* 20 */
5808     { PREFIX_TABLE (PREFIX_0F3820) },
5809     { PREFIX_TABLE (PREFIX_0F3821) },
5810     { PREFIX_TABLE (PREFIX_0F3822) },
5811     { PREFIX_TABLE (PREFIX_0F3823) },
5812     { PREFIX_TABLE (PREFIX_0F3824) },
5813     { PREFIX_TABLE (PREFIX_0F3825) },
5814     { "(bad)",          { XX } },
5815     { "(bad)",          { XX } },
5816     /* 28 */
5817     { PREFIX_TABLE (PREFIX_0F3828) },
5818     { PREFIX_TABLE (PREFIX_0F3829) },
5819     { PREFIX_TABLE (PREFIX_0F382A) },
5820     { PREFIX_TABLE (PREFIX_0F382B) },
5821     { "(bad)",          { XX } },
5822     { "(bad)",          { XX } },
5823     { "(bad)",          { XX } },
5824     { "(bad)",          { XX } },
5825     /* 30 */
5826     { PREFIX_TABLE (PREFIX_0F3830) },
5827     { PREFIX_TABLE (PREFIX_0F3831) },
5828     { PREFIX_TABLE (PREFIX_0F3832) },
5829     { PREFIX_TABLE (PREFIX_0F3833) },
5830     { PREFIX_TABLE (PREFIX_0F3834) },
5831     { PREFIX_TABLE (PREFIX_0F3835) },
5832     { "(bad)",          { XX } },
5833     { PREFIX_TABLE (PREFIX_0F3837) },
5834     /* 38 */
5835     { PREFIX_TABLE (PREFIX_0F3838) },
5836     { PREFIX_TABLE (PREFIX_0F3839) },
5837     { PREFIX_TABLE (PREFIX_0F383A) },
5838     { PREFIX_TABLE (PREFIX_0F383B) },
5839     { PREFIX_TABLE (PREFIX_0F383C) },
5840     { PREFIX_TABLE (PREFIX_0F383D) },
5841     { PREFIX_TABLE (PREFIX_0F383E) },
5842     { PREFIX_TABLE (PREFIX_0F383F) },
5843     /* 40 */
5844     { PREFIX_TABLE (PREFIX_0F3840) },
5845     { PREFIX_TABLE (PREFIX_0F3841) },
5846     { "(bad)",          { XX } },
5847     { "(bad)",          { XX } },
5848     { "(bad)",          { XX } },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     /* 48 */
5853     { "(bad)",          { XX } },
5854     { "(bad)",          { XX } },
5855     { "(bad)",          { XX } },
5856     { "(bad)",          { XX } },
5857     { "(bad)",          { XX } },
5858     { "(bad)",          { XX } },
5859     { "(bad)",          { XX } },
5860     { "(bad)",          { XX } },
5861     /* 50 */
5862     { "(bad)",          { XX } },
5863     { "(bad)",          { XX } },
5864     { "(bad)",          { XX } },
5865     { "(bad)",          { XX } },
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     /* 58 */
5871     { "(bad)",          { XX } },
5872     { "(bad)",          { XX } },
5873     { "(bad)",          { XX } },
5874     { "(bad)",          { XX } },
5875     { "(bad)",          { XX } },
5876     { "(bad)",          { XX } },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     /* 60 */
5880     { "(bad)",          { XX } },
5881     { "(bad)",          { XX } },
5882     { "(bad)",          { XX } },
5883     { "(bad)",          { XX } },
5884     { "(bad)",          { XX } },
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     /* 68 */
5889     { "(bad)",          { XX } },
5890     { "(bad)",          { XX } },
5891     { "(bad)",          { XX } },
5892     { "(bad)",          { XX } },
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     /* 70 */
5898     { "(bad)",          { XX } },
5899     { "(bad)",          { XX } },
5900     { "(bad)",          { XX } },
5901     { "(bad)",          { XX } },
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     /* 78 */
5907     { "(bad)",          { XX } },
5908     { "(bad)",          { XX } },
5909     { "(bad)",          { XX } },
5910     { "(bad)",          { XX } },
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     /* 80 */
5916     { PREFIX_TABLE (PREFIX_0F3880) },
5917     { PREFIX_TABLE (PREFIX_0F3881) },
5918     { "(bad)",          { XX } },
5919     { "(bad)",          { XX } },
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     /* 88 */
5925     { "(bad)",          { XX } },
5926     { "(bad)",          { XX } },
5927     { "(bad)",          { XX } },
5928     { "(bad)",          { XX } },
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     /* 90 */
5934     { "(bad)",          { XX } },
5935     { "(bad)",          { XX } },
5936     { "(bad)",          { XX } },
5937     { "(bad)",          { XX } },
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     /* 98 */
5943     { "(bad)",          { XX } },
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     { "(bad)",          { XX } },
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     /* a0 */
5952     { "(bad)",          { XX } },
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     { "(bad)",          { XX } },
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     /* a8 */
5961     { "(bad)",          { XX } },
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     { "(bad)",          { XX } },
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     /* b0 */
5970     { "(bad)",          { XX } },
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973     { "(bad)",          { XX } },
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     /* b8 */
5979     { "(bad)",          { XX } },
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     /* c0 */
5988     { "(bad)",          { XX } },
5989     { "(bad)",          { XX } },
5990     { "(bad)",          { XX } },
5991     { "(bad)",          { XX } },
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     /* c8 */
5997     { "(bad)",          { XX } },
5998     { "(bad)",          { XX } },
5999     { "(bad)",          { XX } },
6000     { "(bad)",          { XX } },
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     /* d0 */
6006     { "(bad)",          { XX } },
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     /* d8 */
6015     { "(bad)",          { XX } },
6016     { "(bad)",          { XX } },
6017     { "(bad)",          { XX } },
6018     { PREFIX_TABLE (PREFIX_0F38DB) },
6019     { PREFIX_TABLE (PREFIX_0F38DC) },
6020     { PREFIX_TABLE (PREFIX_0F38DD) },
6021     { PREFIX_TABLE (PREFIX_0F38DE) },
6022     { PREFIX_TABLE (PREFIX_0F38DF) },
6023     /* e0 */
6024     { "(bad)",          { XX } },
6025     { "(bad)",          { XX } },
6026     { "(bad)",          { XX } },
6027     { "(bad)",          { XX } },
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     /* e8 */
6033     { "(bad)",          { XX } },
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     { "(bad)",          { XX } },
6040     { "(bad)",          { XX } },
6041     /* f0 */
6042     { PREFIX_TABLE (PREFIX_0F38F0) },
6043     { PREFIX_TABLE (PREFIX_0F38F1) },
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     /* f8 */
6051     { "(bad)",          { XX } },
6052     { "(bad)",          { XX } },
6053     { "(bad)",          { XX } },
6054     { "(bad)",          { XX } },
6055     { "(bad)",          { XX } },
6056     { "(bad)",          { XX } },
6057     { "(bad)",          { XX } },
6058     { "(bad)",          { XX } },
6059   },
6060   /* THREE_BYTE_0F3A */
6061   {
6062     /* 00 */
6063     { "(bad)",          { XX } },
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     { "(bad)",          { XX } },
6069     { "(bad)",          { XX } },
6070     { "(bad)",          { XX } },
6071     /* 08 */
6072     { PREFIX_TABLE (PREFIX_0F3A08) },
6073     { PREFIX_TABLE (PREFIX_0F3A09) },
6074     { PREFIX_TABLE (PREFIX_0F3A0A) },
6075     { PREFIX_TABLE (PREFIX_0F3A0B) },
6076     { PREFIX_TABLE (PREFIX_0F3A0C) },
6077     { PREFIX_TABLE (PREFIX_0F3A0D) },
6078     { PREFIX_TABLE (PREFIX_0F3A0E) },
6079     { "palignr",        { MX, EM, Ib } },
6080     /* 10 */
6081     { "(bad)",          { XX } },
6082     { "(bad)",          { XX } },
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     { PREFIX_TABLE (PREFIX_0F3A14) },
6086     { PREFIX_TABLE (PREFIX_0F3A15) },
6087     { PREFIX_TABLE (PREFIX_0F3A16) },
6088     { PREFIX_TABLE (PREFIX_0F3A17) },
6089     /* 18 */
6090     { "(bad)",          { XX } },
6091     { "(bad)",          { XX } },
6092     { "(bad)",          { XX } },
6093     { "(bad)",          { XX } },
6094     { "(bad)",          { XX } },
6095     { "(bad)",          { XX } },
6096     { "(bad)",          { XX } },
6097     { "(bad)",          { XX } },
6098     /* 20 */
6099     { PREFIX_TABLE (PREFIX_0F3A20) },
6100     { PREFIX_TABLE (PREFIX_0F3A21) },
6101     { PREFIX_TABLE (PREFIX_0F3A22) },
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     /* 28 */
6108     { "(bad)",          { XX } },
6109     { "(bad)",          { XX } },
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     /* 30 */
6117     { "(bad)",          { XX } },
6118     { "(bad)",          { XX } },
6119     { "(bad)",          { XX } },
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     /* 38 */
6126     { "(bad)",          { XX } },
6127     { "(bad)",          { XX } },
6128     { "(bad)",          { XX } },
6129     { "(bad)",          { XX } },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     /* 40 */
6135     { PREFIX_TABLE (PREFIX_0F3A40) },
6136     { PREFIX_TABLE (PREFIX_0F3A41) },
6137     { PREFIX_TABLE (PREFIX_0F3A42) },
6138     { "(bad)",          { XX } },
6139     { PREFIX_TABLE (PREFIX_0F3A44) },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     /* 48 */
6144     { "(bad)",          { XX } },
6145     { "(bad)",          { XX } },
6146     { "(bad)",          { XX } },
6147     { "(bad)",          { XX } },
6148     { "(bad)",          { XX } },
6149     { "(bad)",          { XX } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     /* 50 */
6153     { "(bad)",          { XX } },
6154     { "(bad)",          { XX } },
6155     { "(bad)",          { XX } },
6156     { "(bad)",          { XX } },
6157     { "(bad)",          { XX } },
6158     { "(bad)",          { XX } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     /* 58 */
6162     { "(bad)",          { XX } },
6163     { "(bad)",          { XX } },
6164     { "(bad)",          { XX } },
6165     { "(bad)",          { XX } },
6166     { "(bad)",          { XX } },
6167     { "(bad)",          { XX } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     /* 60 */
6171     { PREFIX_TABLE (PREFIX_0F3A60) },
6172     { PREFIX_TABLE (PREFIX_0F3A61) },
6173     { PREFIX_TABLE (PREFIX_0F3A62) },
6174     { PREFIX_TABLE (PREFIX_0F3A63) },
6175     { "(bad)",          { XX } },
6176     { "(bad)",          { XX } },
6177     { "(bad)",          { XX } },
6178     { "(bad)",          { XX } },
6179     /* 68 */
6180     { "(bad)",          { XX } },
6181     { "(bad)",          { XX } },
6182     { "(bad)",          { XX } },
6183     { "(bad)",          { XX } },
6184     { "(bad)",          { XX } },
6185     { "(bad)",          { XX } },
6186     { "(bad)",          { XX } },
6187     { "(bad)",          { XX } },
6188     /* 70 */
6189     { "(bad)",          { XX } },
6190     { "(bad)",          { XX } },
6191     { "(bad)",          { XX } },
6192     { "(bad)",          { XX } },
6193     { "(bad)",          { XX } },
6194     { "(bad)",          { XX } },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     /* 78 */
6198     { "(bad)",          { XX } },
6199     { "(bad)",          { XX } },
6200     { "(bad)",          { XX } },
6201     { "(bad)",          { XX } },
6202     { "(bad)",          { XX } },
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     /* 80 */
6207     { "(bad)",          { XX } },
6208     { "(bad)",          { XX } },
6209     { "(bad)",          { XX } },
6210     { "(bad)",          { XX } },
6211     { "(bad)",          { XX } },
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     /* 88 */
6216     { "(bad)",          { XX } },
6217     { "(bad)",          { XX } },
6218     { "(bad)",          { XX } },
6219     { "(bad)",          { XX } },
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     /* 90 */
6225     { "(bad)",          { XX } },
6226     { "(bad)",          { XX } },
6227     { "(bad)",          { XX } },
6228     { "(bad)",          { XX } },
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     /* 98 */
6234     { "(bad)",          { XX } },
6235     { "(bad)",          { XX } },
6236     { "(bad)",          { XX } },
6237     { "(bad)",          { XX } },
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     /* a0 */
6243     { "(bad)",          { XX } },
6244     { "(bad)",          { XX } },
6245     { "(bad)",          { XX } },
6246     { "(bad)",          { XX } },
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     /* a8 */
6252     { "(bad)",          { XX } },
6253     { "(bad)",          { XX } },
6254     { "(bad)",          { XX } },
6255     { "(bad)",          { XX } },
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     /* b0 */
6261     { "(bad)",          { XX } },
6262     { "(bad)",          { XX } },
6263     { "(bad)",          { XX } },
6264     { "(bad)",          { XX } },
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     /* b8 */
6270     { "(bad)",          { XX } },
6271     { "(bad)",          { XX } },
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     /* c0 */
6279     { "(bad)",          { XX } },
6280     { "(bad)",          { XX } },
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     /* c8 */
6288     { "(bad)",          { XX } },
6289     { "(bad)",          { XX } },
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     /* d0 */
6297     { "(bad)",          { XX } },
6298     { "(bad)",          { XX } },
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     /* d8 */
6306     { "(bad)",          { XX } },
6307     { "(bad)",          { XX } },
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { PREFIX_TABLE (PREFIX_0F3ADF) },
6314     /* e0 */
6315     { "(bad)",          { XX } },
6316     { "(bad)",          { XX } },
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     /* e8 */
6324     { "(bad)",          { XX } },
6325     { "(bad)",          { XX } },
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     /* f0 */
6333     { "(bad)",          { XX } },
6334     { "(bad)",          { XX } },
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     /* f8 */
6342     { "(bad)",          { XX } },
6343     { "(bad)",          { XX } },
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346     { "(bad)",          { XX } },
6347     { "(bad)",          { XX } },
6348     { "(bad)",          { XX } },
6349     { "(bad)",          { XX } },
6350   },
6351   /* THREE_BYTE_0F7A */
6352   {
6353     /* 00 */
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     { "(bad)",          { XX } },
6361     { "(bad)",          { XX } },
6362     /* 08 */
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     { "(bad)",          { XX } },
6370     { "(bad)",          { XX } },
6371     /* 10 */
6372     { "frczps",         { XM, EXq } },
6373     { "frczpd",         { XM, EXq } },
6374     { "frczss",         { XM, EXq } },
6375     { "frczsd",         { XM, EXq } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378     { "(bad)",          { XX } },
6379     { "(bad)",          { XX } },
6380     /* 18 */
6381     { "(bad)",          { XX } },
6382     { "(bad)",          { XX } },
6383     { "(bad)",          { XX } },
6384     { "(bad)",          { XX } },
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389     /* 20 */
6390     { "ptest",          { XX } },
6391     { "(bad)",          { XX } },
6392     { "(bad)",          { XX } },
6393     { "(bad)",          { XX } },
6394     { "(bad)",          { XX } },
6395     { "(bad)",          { XX } },
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     /* 28 */
6399     { "(bad)",          { XX } },
6400     { "(bad)",          { XX } },
6401     { "(bad)",          { XX } },
6402     { "(bad)",          { XX } },
6403     { "(bad)",          { XX } },
6404     { "(bad)",          { XX } },
6405     { "(bad)",          { XX } },
6406     { "(bad)",          { XX } },
6407     /* 30 */
6408     { "cvtph2ps",       { XM, EXd } },
6409     { "cvtps2ph",       { EXd, XM } },
6410     { "(bad)",          { XX } },
6411     { "(bad)",          { XX } },
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     /* 38 */
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     { "(bad)",          { XX } },
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     /* 40 */
6426     { "(bad)",          { XX } },
6427     { "phaddbw",        { XM, EXq } },
6428     { "phaddbd",        { XM, EXq } },
6429     { "phaddbq",        { XM, EXq } },
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     { "phaddwd",        { XM, EXq } },
6433     { "phaddwq",        { XM, EXq } },
6434     /* 48 */
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     { "(bad)",          { XX } },
6438     { "phadddq",        { XM, EXq } },
6439     { "(bad)",          { XX } },
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     /* 50 */
6444     { "(bad)",          { XX } },
6445     { "phaddubw",       { XM, EXq } },
6446     { "phaddubd",       { XM, EXq } },
6447     { "phaddubq",       { XM, EXq } },
6448     { "(bad)",          { XX } },
6449     { "(bad)",          { XX } },
6450     { "phadduwd",       { XM, EXq } },
6451     { "phadduwq",       { XM, EXq } },
6452     /* 58 */
6453     { "(bad)",          { XX } },
6454     { "(bad)",          { XX } },
6455     { "(bad)",          { XX } },
6456     { "phaddudq",       { XM, EXq } },
6457     { "(bad)",          { XX } },
6458     { "(bad)",          { XX } },
6459     { "(bad)",          { XX } },
6460     { "(bad)",          { XX } },
6461     /* 60 */
6462     { "(bad)",          { XX } },
6463     { "phsubbw",        { XM, EXq } },
6464     { "phsubbd",        { XM, EXq } },
6465     { "phsubbq",        { XM, EXq } },
6466     { "(bad)",          { XX } },
6467     { "(bad)",          { XX } },
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     /* 68 */
6471     { "(bad)",          { XX } },
6472     { "(bad)",          { XX } },
6473     { "(bad)",          { XX } },
6474     { "(bad)",          { XX } },
6475     { "(bad)",          { XX } },
6476     { "(bad)",          { XX } },
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     /* 70 */
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     { "(bad)",          { XX } },
6483     { "(bad)",          { XX } },
6484     { "(bad)",          { XX } },
6485     { "(bad)",          { XX } },
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     /* 78 */
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     { "(bad)",          { XX } },
6493     { "(bad)",          { XX } },
6494     { "(bad)",          { XX } },
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     /* 80 */
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     { "(bad)",          { XX } },
6502     { "(bad)",          { XX } },
6503     { "(bad)",          { XX } },
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     /* 88 */
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     { "(bad)",          { XX } },
6511     { "(bad)",          { XX } },
6512     { "(bad)",          { XX } },
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     /* 90 */
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     { "(bad)",          { XX } },
6520     { "(bad)",          { XX } },
6521     { "(bad)",          { XX } },
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     /* 98 */
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     { "(bad)",          { XX } },
6529     { "(bad)",          { XX } },
6530     { "(bad)",          { XX } },
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     /* a0 */
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     { "(bad)",          { XX } },
6538     { "(bad)",          { XX } },
6539     { "(bad)",          { XX } },
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     /* a8 */
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "(bad)",          { XX } },
6546     { "(bad)",          { XX } },
6547     { "(bad)",          { XX } },
6548     { "(bad)",          { XX } },
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     /* b0 */
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555     { "(bad)",          { XX } },
6556     { "(bad)",          { XX } },
6557     { "(bad)",          { XX } },
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     /* b8 */
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "(bad)",          { XX } },
6564     { "(bad)",          { XX } },
6565     { "(bad)",          { XX } },
6566     { "(bad)",          { XX } },
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     /* c0 */
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     { "(bad)",          { XX } },
6573     { "(bad)",          { XX } },
6574     { "(bad)",          { XX } },
6575     { "(bad)",          { XX } },
6576     { "(bad)",          { XX } },
6577     { "(bad)",          { XX } },
6578     /* c8 */
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     { "(bad)",          { XX } },
6583     { "(bad)",          { XX } },
6584     { "(bad)",          { XX } },
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     /* d0 */
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     { "(bad)",          { XX } },
6592     { "(bad)",          { XX } },
6593     { "(bad)",          { XX } },
6594     { "(bad)",          { XX } },
6595     { "(bad)",          { XX } },
6596     /* d8 */
6597     { "(bad)",          { XX } },
6598     { "(bad)",          { XX } },
6599     { "(bad)",          { XX } },
6600     { "(bad)",          { XX } },
6601     { "(bad)",          { XX } },
6602     { "(bad)",          { XX } },
6603     { "(bad)",          { XX } },
6604     { "(bad)",          { XX } },
6605     /* e0 */
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     { "(bad)",          { XX } },
6610     { "(bad)",          { XX } },
6611     { "(bad)",          { XX } },
6612     { "(bad)",          { XX } },
6613     { "(bad)",          { XX } },
6614     /* e8 */
6615     { "(bad)",          { XX } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     { "(bad)",          { XX } },
6619     { "(bad)",          { XX } },
6620     { "(bad)",          { XX } },
6621     { "(bad)",          { XX } },
6622     { "(bad)",          { XX } },
6623     /* f0 */
6624     { "(bad)",          { XX } },
6625     { "(bad)",          { XX } },
6626     { "(bad)",          { XX } },
6627     { "(bad)",          { XX } },
6628     { "(bad)",          { XX } },
6629     { "(bad)",          { XX } },
6630     { "(bad)",          { XX } },
6631     { "(bad)",          { XX } },
6632     /* f8 */
6633     { "(bad)",          { XX } },
6634     { "(bad)",          { XX } },
6635     { "(bad)",          { XX } },
6636     { "(bad)",          { XX } },
6637     { "(bad)",          { XX } },
6638     { "(bad)",          { XX } },
6639     { "(bad)",          { XX } },
6640     { "(bad)",          { XX } },
6641   },
6642   /* THREE_BYTE_0F7B */
6643   {
6644     /* 00 */
6645     { "(bad)",          { XX } },
6646     { "(bad)",          { XX } },
6647     { "(bad)",          { XX } },
6648     { "(bad)",          { XX } },
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     { "(bad)",          { XX } },
6653     /* 08 */
6654     { "(bad)",          { XX } },
6655     { "(bad)",          { XX } },
6656     { "(bad)",          { XX } },
6657     { "(bad)",          { XX } },
6658     { "(bad)",          { XX } },
6659     { "(bad)",          { XX } },
6660     { "(bad)",          { XX } },
6661     { "(bad)",          { XX } },
6662     /* 10 */
6663     { "(bad)",          { XX } },
6664     { "(bad)",          { XX } },
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { "(bad)",          { XX } },
6671     /* 18 */
6672     { "(bad)",          { XX } },
6673     { "(bad)",          { XX } },
6674     { "(bad)",          { XX } },
6675     { "(bad)",          { XX } },
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     /* 20 */
6681     { "(bad)",          { XX } },
6682     { "(bad)",          { XX } },
6683     { "(bad)",          { XX } },
6684     { "(bad)",          { XX } },
6685     { "(bad)",          { XX } },
6686     { "(bad)",          { XX } },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     /* 28 */
6690     { "(bad)",          { XX } },
6691     { "(bad)",          { XX } },
6692     { "(bad)",          { XX } },
6693     { "(bad)",          { XX } },
6694     { "(bad)",          { XX } },
6695     { "(bad)",          { XX } },
6696     { "(bad)",          { XX } },
6697     { "(bad)",          { XX } },
6698     /* 30 */
6699     { "(bad)",          { XX } },
6700     { "(bad)",          { XX } },
6701     { "(bad)",          { XX } },
6702     { "(bad)",          { XX } },
6703     { "(bad)",          { XX } },
6704     { "(bad)",          { XX } },
6705     { "(bad)",          { XX } },
6706     { "(bad)",          { XX } },
6707     /* 38 */
6708     { "(bad)",          { XX } },
6709     { "(bad)",          { XX } },
6710     { "(bad)",          { XX } },
6711     { "(bad)",          { XX } },
6712     { "(bad)",          { XX } },
6713     { "(bad)",          { XX } },
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     /* 40 */
6717     { "protb",          { XM, EXq, Ib } },
6718     { "protw",          { XM, EXq, Ib } },
6719     { "protd",          { XM, EXq, Ib } },
6720     { "protq",          { XM, EXq, Ib } },
6721     { "pshlb",          { XM, EXq, Ib } },
6722     { "pshlw",          { XM, EXq, Ib } },
6723     { "pshld",          { XM, EXq, Ib } },
6724     { "pshlq",          { XM, EXq, Ib } },
6725     /* 48 */
6726     { "pshab",          { XM, EXq, Ib } },
6727     { "pshaw",          { XM, EXq, Ib } },
6728     { "pshad",          { XM, EXq, Ib } },
6729     { "pshaq",          { XM, EXq, Ib } },
6730     { "(bad)",          { XX } },
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     /* 50 */
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     { "(bad)",          { XX } },
6739     { "(bad)",          { XX } },
6740     { "(bad)",          { XX } },
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     /* 58 */
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     { "(bad)",          { XX } },
6748     { "(bad)",          { XX } },
6749     { "(bad)",          { XX } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     /* 60 */
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     { "(bad)",          { XX } },
6757     { "(bad)",          { XX } },
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     /* 68 */
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     { "(bad)",          { XX } },
6766     { "(bad)",          { XX } },
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     /* 70 */
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     { "(bad)",          { XX } },
6775     { "(bad)",          { XX } },
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     /* 78 */
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     { "(bad)",          { XX } },
6784     { "(bad)",          { XX } },
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     /* 80 */
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     { "(bad)",          { XX } },
6793     { "(bad)",          { XX } },
6794     { "(bad)",          { XX } },
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     /* 88 */
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     { "(bad)",          { XX } },
6802     { "(bad)",          { XX } },
6803     { "(bad)",          { XX } },
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     /* 90 */
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     { "(bad)",          { XX } },
6811     { "(bad)",          { XX } },
6812     { "(bad)",          { XX } },
6813     { "(bad)",          { XX } },
6814     { "(bad)",          { XX } },
6815     /* 98 */
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     { "(bad)",          { XX } },
6819     { "(bad)",          { XX } },
6820     { "(bad)",          { XX } },
6821     { "(bad)",          { XX } },
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     /* a0 */
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     { "(bad)",          { XX } },
6829     { "(bad)",          { XX } },
6830     { "(bad)",          { XX } },
6831     { "(bad)",          { XX } },
6832     { "(bad)",          { XX } },
6833     /* a8 */
6834     { "(bad)",          { XX } },
6835     { "(bad)",          { XX } },
6836     { "(bad)",          { XX } },
6837     { "(bad)",          { XX } },
6838     { "(bad)",          { XX } },
6839     { "(bad)",          { XX } },
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     /* b0 */
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     { "(bad)",          { XX } },
6847     { "(bad)",          { XX } },
6848     { "(bad)",          { XX } },
6849     { "(bad)",          { XX } },
6850     { "(bad)",          { XX } },
6851     /* b8 */
6852     { "(bad)",          { XX } },
6853     { "(bad)",          { XX } },
6854     { "(bad)",          { XX } },
6855     { "(bad)",          { XX } },
6856     { "(bad)",          { XX } },
6857     { "(bad)",          { XX } },
6858     { "(bad)",          { XX } },
6859     { "(bad)",          { XX } },
6860     /* c0 */
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     { "(bad)",          { XX } },
6865     { "(bad)",          { XX } },
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     /* c8 */
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     { "(bad)",          { XX } },
6874     { "(bad)",          { XX } },
6875     { "(bad)",          { XX } },
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     /* d0 */
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     { "(bad)",          { XX } },
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     /* d8 */
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     { "(bad)",          { XX } },
6892     { "(bad)",          { XX } },
6893     { "(bad)",          { XX } },
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     /* e0 */
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     { "(bad)",          { XX } },
6901     { "(bad)",          { XX } },
6902     { "(bad)",          { XX } },
6903     { "(bad)",          { XX } },
6904     { "(bad)",          { XX } },
6905     /* e8 */
6906     { "(bad)",          { XX } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     { "(bad)",          { XX } },
6910     { "(bad)",          { XX } },
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     /* f0 */
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     { "(bad)",          { XX } },
6920     { "(bad)",          { XX } },
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     /* f8 */
6924     { "(bad)",          { XX } },
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     { "(bad)",          { XX } },
6928     { "(bad)",          { XX } },
6929     { "(bad)",          { XX } },
6930     { "(bad)",          { XX } },
6931     { "(bad)",          { XX } },
6932   },
6933 };
6934
6935 static const struct dis386 vex_table[][256] = {
6936   /* VEX_0F */
6937   {
6938     /* 00 */
6939     { "(bad)",          { XX } },
6940     { "(bad)",          { XX } },
6941     { "(bad)",          { XX } },
6942     { "(bad)",          { XX } },
6943     { "(bad)",          { XX } },
6944     { "(bad)",          { XX } },
6945     { "(bad)",          { XX } },
6946     { "(bad)",          { XX } },
6947     /* 08 */
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     { "(bad)",          { XX } },
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     { "(bad)",          { XX } },
6955     { "(bad)",          { XX } },
6956     /* 10 */
6957     { PREFIX_TABLE (PREFIX_VEX_10) },
6958     { PREFIX_TABLE (PREFIX_VEX_11) },
6959     { PREFIX_TABLE (PREFIX_VEX_12) },
6960     { MOD_TABLE (MOD_VEX_13) },
6961     { "vunpcklpX",      { XM, Vex, EXx } },
6962     { "vunpckhpX",      { XM, Vex, EXx } },
6963     { PREFIX_TABLE (PREFIX_VEX_16) },
6964     { MOD_TABLE (MOD_VEX_17) },
6965     /* 18 */
6966     { "(bad)",          { XX } },
6967     { "(bad)",          { XX } },
6968     { "(bad)",          { XX } },
6969     { "(bad)",          { XX } },
6970     { "(bad)",          { XX } },
6971     { "(bad)",          { XX } },
6972     { "(bad)",          { XX } },
6973     { "(bad)",          { XX } },
6974     /* 20 */
6975     { "(bad)",          { XX } },
6976     { "(bad)",          { XX } },
6977     { "(bad)",          { XX } },
6978     { "(bad)",          { XX } },
6979     { "(bad)",          { XX } },
6980     { "(bad)",          { XX } },
6981     { "(bad)",          { XX } },
6982     { "(bad)",          { XX } },
6983     /* 28 */
6984     { "vmovapX",        { XM, EXx } },
6985     { "vmovapX",        { EXx, XM } },
6986     { PREFIX_TABLE (PREFIX_VEX_2A) },
6987     { MOD_TABLE (MOD_VEX_2B) },
6988     { PREFIX_TABLE (PREFIX_VEX_2C) },
6989     { PREFIX_TABLE (PREFIX_VEX_2D) },
6990     { PREFIX_TABLE (PREFIX_VEX_2E) },
6991     { PREFIX_TABLE (PREFIX_VEX_2F) },
6992     /* 30 */
6993     { "(bad)",          { XX } },
6994     { "(bad)",          { XX } },
6995     { "(bad)",          { XX } },
6996     { "(bad)",          { XX } },
6997     { "(bad)",          { XX } },
6998     { "(bad)",          { XX } },
6999     { "(bad)",          { XX } },
7000     { "(bad)",          { XX } },
7001     /* 38 */
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     { "(bad)",          { XX } },
7005     { "(bad)",          { XX } },
7006     { "(bad)",          { XX } },
7007     { "(bad)",          { XX } },
7008     { "(bad)",          { XX } },
7009     { "(bad)",          { XX } },
7010     /* 40 */
7011     { "(bad)",          { XX } },
7012     { "(bad)",          { XX } },
7013     { "(bad)",          { XX } },
7014     { "(bad)",          { XX } },
7015     { "(bad)",          { XX } },
7016     { "(bad)",          { XX } },
7017     { "(bad)",          { XX } },
7018     { "(bad)",          { XX } },
7019     /* 48 */
7020     { "(bad)",          { XX } },
7021     { "(bad)",          { XX } },
7022     { "(bad)",          { XX } },
7023     { "(bad)",          { XX } },
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     /* 50 */
7029     { MOD_TABLE (MOD_VEX_51) },
7030     { PREFIX_TABLE (PREFIX_VEX_51) },
7031     { PREFIX_TABLE (PREFIX_VEX_52) },
7032     { PREFIX_TABLE (PREFIX_VEX_53) },
7033     { "vandpX",         { XM, Vex, EXx } },
7034     { "vandnpX",        { XM, Vex, EXx } },
7035     { "vorpX",          { XM, Vex, EXx } },
7036     { "vxorpX",         { XM, Vex, EXx } },
7037     /* 58 */
7038     { PREFIX_TABLE (PREFIX_VEX_58) },
7039     { PREFIX_TABLE (PREFIX_VEX_59) },
7040     { PREFIX_TABLE (PREFIX_VEX_5A) },
7041     { PREFIX_TABLE (PREFIX_VEX_5B) },
7042     { PREFIX_TABLE (PREFIX_VEX_5C) },
7043     { PREFIX_TABLE (PREFIX_VEX_5D) },
7044     { PREFIX_TABLE (PREFIX_VEX_5E) },
7045     { PREFIX_TABLE (PREFIX_VEX_5F) },
7046     /* 60 */
7047     { PREFIX_TABLE (PREFIX_VEX_60) },
7048     { PREFIX_TABLE (PREFIX_VEX_61) },
7049     { PREFIX_TABLE (PREFIX_VEX_62) },
7050     { PREFIX_TABLE (PREFIX_VEX_63) },
7051     { PREFIX_TABLE (PREFIX_VEX_64) },
7052     { PREFIX_TABLE (PREFIX_VEX_65) },
7053     { PREFIX_TABLE (PREFIX_VEX_66) },
7054     { PREFIX_TABLE (PREFIX_VEX_67) },
7055     /* 68 */
7056     { PREFIX_TABLE (PREFIX_VEX_68) },
7057     { PREFIX_TABLE (PREFIX_VEX_69) },
7058     { PREFIX_TABLE (PREFIX_VEX_6A) },
7059     { PREFIX_TABLE (PREFIX_VEX_6B) },
7060     { PREFIX_TABLE (PREFIX_VEX_6C) },
7061     { PREFIX_TABLE (PREFIX_VEX_6D) },
7062     { PREFIX_TABLE (PREFIX_VEX_6E) },
7063     { PREFIX_TABLE (PREFIX_VEX_6F) },
7064     /* 70 */
7065     { PREFIX_TABLE (PREFIX_VEX_70) },
7066     { REG_TABLE (REG_VEX_71) },
7067     { REG_TABLE (REG_VEX_72) },
7068     { REG_TABLE (REG_VEX_73) },
7069     { PREFIX_TABLE (PREFIX_VEX_74) },
7070     { PREFIX_TABLE (PREFIX_VEX_75) },
7071     { PREFIX_TABLE (PREFIX_VEX_76) },
7072     { PREFIX_TABLE (PREFIX_VEX_77) },
7073     /* 78 */
7074     { "(bad)",          { XX } },
7075     { "(bad)",          { XX } },
7076     { "(bad)",          { XX } },
7077     { "(bad)",          { XX } },
7078     { PREFIX_TABLE (PREFIX_VEX_7C) },
7079     { PREFIX_TABLE (PREFIX_VEX_7D) },
7080     { PREFIX_TABLE (PREFIX_VEX_7E) },
7081     { PREFIX_TABLE (PREFIX_VEX_7F) },
7082     /* 80 */
7083     { "(bad)",          { XX } },
7084     { "(bad)",          { XX } },
7085     { "(bad)",          { XX } },
7086     { "(bad)",          { XX } },
7087     { "(bad)",          { XX } },
7088     { "(bad)",          { XX } },
7089     { "(bad)",          { XX } },
7090     { "(bad)",          { XX } },
7091     /* 88 */
7092     { "(bad)",          { XX } },
7093     { "(bad)",          { XX } },
7094     { "(bad)",          { XX } },
7095     { "(bad)",          { XX } },
7096     { "(bad)",          { XX } },
7097     { "(bad)",          { XX } },
7098     { "(bad)",          { XX } },
7099     { "(bad)",          { XX } },
7100     /* 90 */
7101     { "(bad)",          { XX } },
7102     { "(bad)",          { XX } },
7103     { "(bad)",          { XX } },
7104     { "(bad)",          { XX } },
7105     { "(bad)",          { XX } },
7106     { "(bad)",          { XX } },
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     /* 98 */
7110     { "(bad)",          { XX } },
7111     { "(bad)",          { XX } },
7112     { "(bad)",          { XX } },
7113     { "(bad)",          { XX } },
7114     { "(bad)",          { XX } },
7115     { "(bad)",          { XX } },
7116     { "(bad)",          { XX } },
7117     { "(bad)",          { XX } },
7118     /* a0 */
7119     { "(bad)",          { XX } },
7120     { "(bad)",          { XX } },
7121     { "(bad)",          { XX } },
7122     { "(bad)",          { XX } },
7123     { "(bad)",          { XX } },
7124     { "(bad)",          { XX } },
7125     { "(bad)",          { XX } },
7126     { "(bad)",          { XX } },
7127     /* a8 */
7128     { "(bad)",          { XX } },
7129     { "(bad)",          { XX } },
7130     { "(bad)",          { XX } },
7131     { "(bad)",          { XX } },
7132     { "(bad)",          { XX } },
7133     { "(bad)",          { XX } },
7134     { REG_TABLE (REG_VEX_AE) },
7135     { "(bad)",          { XX } },
7136     /* b0 */
7137     { "(bad)",          { XX } },
7138     { "(bad)",          { XX } },
7139     { "(bad)",          { XX } },
7140     { "(bad)",          { XX } },
7141     { "(bad)",          { XX } },
7142     { "(bad)",          { XX } },
7143     { "(bad)",          { XX } },
7144     { "(bad)",          { XX } },
7145     /* b8 */
7146     { "(bad)",          { XX } },
7147     { "(bad)",          { XX } },
7148     { "(bad)",          { XX } },
7149     { "(bad)",          { XX } },
7150     { "(bad)",          { XX } },
7151     { "(bad)",          { XX } },
7152     { "(bad)",          { XX } },
7153     { "(bad)",          { XX } },
7154     /* c0 */
7155     { "(bad)",          { XX } },
7156     { "(bad)",          { XX } },
7157     { PREFIX_TABLE (PREFIX_VEX_C2) },
7158     { "(bad)",          { XX } },
7159     { PREFIX_TABLE (PREFIX_VEX_C4) },
7160     { PREFIX_TABLE (PREFIX_VEX_C5) },
7161     { "vshufpX",        { XM, Vex, EXx, Ib } },
7162     { "(bad)",          { XX } },
7163     /* c8 */
7164     { "(bad)",          { XX } },
7165     { "(bad)",          { XX } },
7166     { "(bad)",          { XX } },
7167     { "(bad)",          { XX } },
7168     { "(bad)",          { XX } },
7169     { "(bad)",          { XX } },
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     /* d0 */
7173     { PREFIX_TABLE (PREFIX_VEX_D0) },
7174     { PREFIX_TABLE (PREFIX_VEX_D1) },
7175     { PREFIX_TABLE (PREFIX_VEX_D2) },
7176     { PREFIX_TABLE (PREFIX_VEX_D3) },
7177     { PREFIX_TABLE (PREFIX_VEX_D4) },
7178     { PREFIX_TABLE (PREFIX_VEX_D5) },
7179     { PREFIX_TABLE (PREFIX_VEX_D6) },
7180     { PREFIX_TABLE (PREFIX_VEX_D7) },
7181     /* d8 */
7182     { PREFIX_TABLE (PREFIX_VEX_D8) },
7183     { PREFIX_TABLE (PREFIX_VEX_D9) },
7184     { PREFIX_TABLE (PREFIX_VEX_DA) },
7185     { PREFIX_TABLE (PREFIX_VEX_DB) },
7186     { PREFIX_TABLE (PREFIX_VEX_DC) },
7187     { PREFIX_TABLE (PREFIX_VEX_DD) },
7188     { PREFIX_TABLE (PREFIX_VEX_DE) },
7189     { PREFIX_TABLE (PREFIX_VEX_DF) },
7190     /* e0 */
7191     { PREFIX_TABLE (PREFIX_VEX_E0) },
7192     { PREFIX_TABLE (PREFIX_VEX_E1) },
7193     { PREFIX_TABLE (PREFIX_VEX_E2) },
7194     { PREFIX_TABLE (PREFIX_VEX_E3) },
7195     { PREFIX_TABLE (PREFIX_VEX_E4) },
7196     { PREFIX_TABLE (PREFIX_VEX_E5) },
7197     { PREFIX_TABLE (PREFIX_VEX_E6) },
7198     { PREFIX_TABLE (PREFIX_VEX_E7) },
7199     /* e8 */
7200     { PREFIX_TABLE (PREFIX_VEX_E8) },
7201     { PREFIX_TABLE (PREFIX_VEX_E9) },
7202     { PREFIX_TABLE (PREFIX_VEX_EA) },
7203     { PREFIX_TABLE (PREFIX_VEX_EB) },
7204     { PREFIX_TABLE (PREFIX_VEX_EC) },
7205     { PREFIX_TABLE (PREFIX_VEX_ED) },
7206     { PREFIX_TABLE (PREFIX_VEX_EE) },
7207     { PREFIX_TABLE (PREFIX_VEX_EF) },
7208     /* f0 */
7209     { PREFIX_TABLE (PREFIX_VEX_F0) },
7210     { PREFIX_TABLE (PREFIX_VEX_F1) },
7211     { PREFIX_TABLE (PREFIX_VEX_F2) },
7212     { PREFIX_TABLE (PREFIX_VEX_F3) },
7213     { PREFIX_TABLE (PREFIX_VEX_F4) },
7214     { PREFIX_TABLE (PREFIX_VEX_F5) },
7215     { PREFIX_TABLE (PREFIX_VEX_F6) },
7216     { PREFIX_TABLE (PREFIX_VEX_F7) },
7217     /* f8 */
7218     { PREFIX_TABLE (PREFIX_VEX_F8) },
7219     { PREFIX_TABLE (PREFIX_VEX_F9) },
7220     { PREFIX_TABLE (PREFIX_VEX_FA) },
7221     { PREFIX_TABLE (PREFIX_VEX_FB) },
7222     { PREFIX_TABLE (PREFIX_VEX_FC) },
7223     { PREFIX_TABLE (PREFIX_VEX_FD) },
7224     { PREFIX_TABLE (PREFIX_VEX_FE) },
7225     { "(bad)",          { XX } },
7226   },
7227   /* VEX_0F38 */
7228   {
7229     /* 00 */
7230     { PREFIX_TABLE (PREFIX_VEX_3800) },
7231     { PREFIX_TABLE (PREFIX_VEX_3801) },
7232     { PREFIX_TABLE (PREFIX_VEX_3802) },
7233     { PREFIX_TABLE (PREFIX_VEX_3803) },
7234     { PREFIX_TABLE (PREFIX_VEX_3804) },
7235     { PREFIX_TABLE (PREFIX_VEX_3805) },
7236     { PREFIX_TABLE (PREFIX_VEX_3806) },
7237     { PREFIX_TABLE (PREFIX_VEX_3807) },
7238     /* 08 */
7239     { PREFIX_TABLE (PREFIX_VEX_3808) },
7240     { PREFIX_TABLE (PREFIX_VEX_3809) },
7241     { PREFIX_TABLE (PREFIX_VEX_380A) },
7242     { PREFIX_TABLE (PREFIX_VEX_380B) },
7243     { PREFIX_TABLE (PREFIX_VEX_380C) },
7244     { PREFIX_TABLE (PREFIX_VEX_380D) },
7245     { PREFIX_TABLE (PREFIX_VEX_380E) },
7246     { PREFIX_TABLE (PREFIX_VEX_380F) },
7247     /* 10 */
7248     { "(bad)",          { XX } },
7249     { "(bad)",          { XX } },
7250     { "(bad)",          { XX } },
7251     { "(bad)",          { XX } },
7252     { "(bad)",          { XX } },
7253     { "(bad)",          { XX } },
7254     { "(bad)",          { XX } },
7255     { PREFIX_TABLE (PREFIX_VEX_3817) },
7256     /* 18 */
7257     { PREFIX_TABLE (PREFIX_VEX_3818) },
7258     { PREFIX_TABLE (PREFIX_VEX_3819) },
7259     { PREFIX_TABLE (PREFIX_VEX_381A) },
7260     { "(bad)",          { XX } },
7261     { PREFIX_TABLE (PREFIX_VEX_381C) },
7262     { PREFIX_TABLE (PREFIX_VEX_381D) },
7263     { PREFIX_TABLE (PREFIX_VEX_381E) },
7264     { "(bad)",          { XX } },
7265     /* 20 */
7266     { PREFIX_TABLE (PREFIX_VEX_3820) },
7267     { PREFIX_TABLE (PREFIX_VEX_3821) },
7268     { PREFIX_TABLE (PREFIX_VEX_3822) },
7269     { PREFIX_TABLE (PREFIX_VEX_3823) },
7270     { PREFIX_TABLE (PREFIX_VEX_3824) },
7271     { PREFIX_TABLE (PREFIX_VEX_3825) },
7272     { "(bad)",          { XX } },
7273     { "(bad)",          { XX } },
7274     /* 28 */
7275     { PREFIX_TABLE (PREFIX_VEX_3828) },
7276     { PREFIX_TABLE (PREFIX_VEX_3829) },
7277     { PREFIX_TABLE (PREFIX_VEX_382A) },
7278     { PREFIX_TABLE (PREFIX_VEX_382B) },
7279     { PREFIX_TABLE (PREFIX_VEX_382C) },
7280     { PREFIX_TABLE (PREFIX_VEX_382D) },
7281     { PREFIX_TABLE (PREFIX_VEX_382E) },
7282     { PREFIX_TABLE (PREFIX_VEX_382F) },
7283     /* 30 */
7284     { PREFIX_TABLE (PREFIX_VEX_3830) },
7285     { PREFIX_TABLE (PREFIX_VEX_3831) },
7286     { PREFIX_TABLE (PREFIX_VEX_3832) },
7287     { PREFIX_TABLE (PREFIX_VEX_3833) },
7288     { PREFIX_TABLE (PREFIX_VEX_3834) },
7289     { PREFIX_TABLE (PREFIX_VEX_3835) },
7290     { "(bad)",          { XX } },
7291     { PREFIX_TABLE (PREFIX_VEX_3837) },
7292     /* 38 */
7293     { PREFIX_TABLE (PREFIX_VEX_3838) },
7294     { PREFIX_TABLE (PREFIX_VEX_3839) },
7295     { PREFIX_TABLE (PREFIX_VEX_383A) },
7296     { PREFIX_TABLE (PREFIX_VEX_383B) },
7297     { PREFIX_TABLE (PREFIX_VEX_383C) },
7298     { PREFIX_TABLE (PREFIX_VEX_383D) },
7299     { PREFIX_TABLE (PREFIX_VEX_383E) },
7300     { PREFIX_TABLE (PREFIX_VEX_383F) },
7301     /* 40 */
7302     { PREFIX_TABLE (PREFIX_VEX_3840) },
7303     { PREFIX_TABLE (PREFIX_VEX_3841) },
7304     { "(bad)",          { XX } },
7305     { "(bad)",          { XX } },
7306     { "(bad)",          { XX } },
7307     { "(bad)",          { XX } },
7308     { "(bad)",          { XX } },
7309     { "(bad)",          { XX } },
7310     /* 48 */
7311     { "(bad)",          { XX } },
7312     { "(bad)",          { XX } },
7313     { "(bad)",          { XX } },
7314     { "(bad)",          { XX } },
7315     { "(bad)",          { XX } },
7316     { "(bad)",          { XX } },
7317     { "(bad)",          { XX } },
7318     { "(bad)",          { XX } },
7319     /* 50 */
7320     { "(bad)",          { XX } },
7321     { "(bad)",          { XX } },
7322     { "(bad)",          { XX } },
7323     { "(bad)",          { XX } },
7324     { "(bad)",          { XX } },
7325     { "(bad)",          { XX } },
7326     { "(bad)",          { XX } },
7327     { "(bad)",          { XX } },
7328     /* 58 */
7329     { "(bad)",          { XX } },
7330     { "(bad)",          { XX } },
7331     { "(bad)",          { XX } },
7332     { "(bad)",          { XX } },
7333     { "(bad)",          { XX } },
7334     { "(bad)",          { XX } },
7335     { "(bad)",          { XX } },
7336     { "(bad)",          { XX } },
7337     /* 60 */
7338     { "(bad)",          { XX } },
7339     { "(bad)",          { XX } },
7340     { "(bad)",          { XX } },
7341     { "(bad)",          { XX } },
7342     { "(bad)",          { XX } },
7343     { "(bad)",          { XX } },
7344     { "(bad)",          { XX } },
7345     { "(bad)",          { XX } },
7346     /* 68 */
7347     { "(bad)",          { XX } },
7348     { "(bad)",          { XX } },
7349     { "(bad)",          { XX } },
7350     { "(bad)",          { XX } },
7351     { "(bad)",          { XX } },
7352     { "(bad)",          { XX } },
7353     { "(bad)",          { XX } },
7354     { "(bad)",          { XX } },
7355     /* 70 */
7356     { "(bad)",          { XX } },
7357     { "(bad)",          { XX } },
7358     { "(bad)",          { XX } },
7359     { "(bad)",          { XX } },
7360     { "(bad)",          { XX } },
7361     { "(bad)",          { XX } },
7362     { "(bad)",          { XX } },
7363     { "(bad)",          { XX } },
7364     /* 78 */
7365     { "(bad)",          { XX } },
7366     { "(bad)",          { XX } },
7367     { "(bad)",          { XX } },
7368     { "(bad)",          { XX } },
7369     { "(bad)",          { XX } },
7370     { "(bad)",          { XX } },
7371     { "(bad)",          { XX } },
7372     { "(bad)",          { XX } },
7373     /* 80 */
7374     { "(bad)",          { XX } },
7375     { "(bad)",          { XX } },
7376     { "(bad)",          { XX } },
7377     { "(bad)",          { XX } },
7378     { "(bad)",          { XX } },
7379     { "(bad)",          { XX } },
7380     { "(bad)",          { XX } },
7381     { "(bad)",          { XX } },
7382     /* 88 */
7383     { "(bad)",          { XX } },
7384     { "(bad)",          { XX } },
7385     { "(bad)",          { XX } },
7386     { "(bad)",          { XX } },
7387     { "(bad)",          { XX } },
7388     { "(bad)",          { XX } },
7389     { "(bad)",          { XX } },
7390     { "(bad)",          { XX } },
7391     /* 90 */
7392     { "(bad)",          { XX } },
7393     { "(bad)",          { XX } },
7394     { "(bad)",          { XX } },
7395     { "(bad)",          { XX } },
7396     { "(bad)",          { XX } },
7397     { "(bad)",          { XX } },
7398     { "(bad)",          { XX } },
7399     { "(bad)",          { XX } },
7400     /* 98 */
7401     { "(bad)",          { XX } },
7402     { "(bad)",          { XX } },
7403     { "(bad)",          { XX } },
7404     { "(bad)",          { XX } },
7405     { "(bad)",          { XX } },
7406     { "(bad)",          { XX } },
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     /* a0 */
7410     { "(bad)",          { XX } },
7411     { "(bad)",          { XX } },
7412     { "(bad)",          { XX } },
7413     { "(bad)",          { XX } },
7414     { "(bad)",          { XX } },
7415     { "(bad)",          { XX } },
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     /* a8 */
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     { "(bad)",          { XX } },
7422     { "(bad)",          { XX } },
7423     { "(bad)",          { XX } },
7424     { "(bad)",          { XX } },
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     /* b0 */
7428     { "(bad)",          { XX } },
7429     { "(bad)",          { XX } },
7430     { "(bad)",          { XX } },
7431     { "(bad)",          { XX } },
7432     { "(bad)",          { XX } },
7433     { "(bad)",          { XX } },
7434     { "(bad)",          { XX } },
7435     { "(bad)",          { XX } },
7436     /* b8 */
7437     { "(bad)",          { XX } },
7438     { "(bad)",          { XX } },
7439     { "(bad)",          { XX } },
7440     { "(bad)",          { XX } },
7441     { "(bad)",          { XX } },
7442     { "(bad)",          { XX } },
7443     { "(bad)",          { XX } },
7444     { "(bad)",          { XX } },
7445     /* c0 */
7446     { "(bad)",          { XX } },
7447     { "(bad)",          { XX } },
7448     { "(bad)",          { XX } },
7449     { "(bad)",          { XX } },
7450     { "(bad)",          { XX } },
7451     { "(bad)",          { XX } },
7452     { "(bad)",          { XX } },
7453     { "(bad)",          { XX } },
7454     /* c8 */
7455     { "(bad)",          { XX } },
7456     { "(bad)",          { XX } },
7457     { "(bad)",          { XX } },
7458     { "(bad)",          { XX } },
7459     { "(bad)",          { XX } },
7460     { "(bad)",          { XX } },
7461     { "(bad)",          { XX } },
7462     { "(bad)",          { XX } },
7463     /* d0 */
7464     { "(bad)",          { XX } },
7465     { "(bad)",          { XX } },
7466     { "(bad)",          { XX } },
7467     { "(bad)",          { XX } },
7468     { "(bad)",          { XX } },
7469     { "(bad)",          { XX } },
7470     { "(bad)",          { XX } },
7471     { "(bad)",          { XX } },
7472     /* d8 */
7473     { "(bad)",          { XX } },
7474     { "(bad)",          { XX } },
7475     { "(bad)",          { XX } },
7476     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7477     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7478     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7479     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7480     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7481     /* e0 */
7482     { "(bad)",          { XX } },
7483     { "(bad)",          { XX } },
7484     { "(bad)",          { XX } },
7485     { "(bad)",          { XX } },
7486     { "(bad)",          { XX } },
7487     { "(bad)",          { XX } },
7488     { "(bad)",          { XX } },
7489     { "(bad)",          { XX } },
7490     /* e8 */
7491     { "(bad)",          { XX } },
7492     { "(bad)",          { XX } },
7493     { "(bad)",          { XX } },
7494     { "(bad)",          { XX } },
7495     { "(bad)",          { XX } },
7496     { "(bad)",          { XX } },
7497     { "(bad)",          { XX } },
7498     { "(bad)",          { XX } },
7499     /* f0 */
7500     { "(bad)",          { XX } },
7501     { "(bad)",          { XX } },
7502     { "(bad)",          { XX } },
7503     { "(bad)",          { XX } },
7504     { "(bad)",          { XX } },
7505     { "(bad)",          { XX } },
7506     { "(bad)",          { XX } },
7507     { "(bad)",          { XX } },
7508     /* f8 */
7509     { "(bad)",          { XX } },
7510     { "(bad)",          { XX } },
7511     { "(bad)",          { XX } },
7512     { "(bad)",          { XX } },
7513     { "(bad)",          { XX } },
7514     { "(bad)",          { XX } },
7515     { "(bad)",          { XX } },
7516     { "(bad)",          { XX } },
7517   },
7518   /* VEX_0F3A */
7519   {
7520     /* 00 */
7521     { "(bad)",          { XX } },
7522     { "(bad)",          { XX } },
7523     { "(bad)",          { XX } },
7524     { "(bad)",          { XX } },
7525     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7526     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7527     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7528     { "(bad)",          { XX } },
7529     /* 08 */
7530     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7531     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7532     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7533     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7534     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7535     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7536     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7537     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7538     /* 10 */
7539     { "(bad)",          { XX } },
7540     { "(bad)",          { XX } },
7541     { "(bad)",          { XX } },
7542     { "(bad)",          { XX } },
7543     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7544     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7545     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7546     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7547     /* 18 */
7548     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7549     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7550     { "(bad)",          { XX } },
7551     { "(bad)",          { XX } },
7552     { "(bad)",          { XX } },
7553     { "(bad)",          { XX } },
7554     { "(bad)",          { XX } },
7555     { "(bad)",          { XX } },
7556     /* 20 */
7557     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7558     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7559     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7560     { "(bad)",          { XX } },
7561     { "(bad)",          { XX } },
7562     { "(bad)",          { XX } },
7563     { "(bad)",          { XX } },
7564     { "(bad)",          { XX } },
7565     /* 28 */
7566     { "(bad)",          { XX } },
7567     { "(bad)",          { XX } },
7568     { "(bad)",          { XX } },
7569     { "(bad)",          { XX } },
7570     { "(bad)",          { XX } },
7571     { "(bad)",          { XX } },
7572     { "(bad)",          { XX } },
7573     { "(bad)",          { XX } },
7574     /* 30 */
7575     { "(bad)",          { XX } },
7576     { "(bad)",          { XX } },
7577     { "(bad)",          { XX } },
7578     { "(bad)",          { XX } },
7579     { "(bad)",          { XX } },
7580     { "(bad)",          { XX } },
7581     { "(bad)",          { XX } },
7582     { "(bad)",          { XX } },
7583     /* 38 */
7584     { "(bad)",          { XX } },
7585     { "(bad)",          { XX } },
7586     { "(bad)",          { XX } },
7587     { "(bad)",          { XX } },
7588     { "(bad)",          { XX } },
7589     { "(bad)",          { XX } },
7590     { "(bad)",          { XX } },
7591     { "(bad)",          { XX } },
7592     /* 40 */
7593     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7594     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7595     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7596     { "(bad)",          { XX } },
7597     { "(bad)",          { XX } },
7598     { "(bad)",          { XX } },
7599     { "(bad)",          { XX } },
7600     { "(bad)",          { XX } },
7601     /* 48 */
7602     { PREFIX_TABLE (PREFIX_VEX_3A48) },
7603     { PREFIX_TABLE (PREFIX_VEX_3A49) },
7604     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7605     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7606     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7607     { "(bad)",          { XX } },
7608     { "(bad)",          { XX } },
7609     { "(bad)",          { XX } },
7610     /* 50 */
7611     { "(bad)",          { XX } },
7612     { "(bad)",          { XX } },
7613     { "(bad)",          { XX } },
7614     { "(bad)",          { XX } },
7615     { "(bad)",          { XX } },
7616     { "(bad)",          { XX } },
7617     { "(bad)",          { XX } },
7618     { "(bad)",          { XX } },
7619     /* 58 */
7620     { "(bad)",          { XX } },
7621     { "(bad)",          { XX } },
7622     { "(bad)",          { XX } },
7623     { "(bad)",          { XX } },
7624     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7625     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7626     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7627     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7628     /* 60 */
7629     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7630     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7631     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7632     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7633     { "(bad)",          { XX } },
7634     { "(bad)",          { XX } },
7635     { "(bad)",          { XX } },
7636     { "(bad)",          { XX } },
7637     /* 68 */
7638     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7639     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7640     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7641     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7642     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7643     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7644     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7645     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7646     /* 70 */
7647     { "(bad)",          { XX } },
7648     { "(bad)",          { XX } },
7649     { "(bad)",          { XX } },
7650     { "(bad)",          { XX } },
7651     { "(bad)",          { XX } },
7652     { "(bad)",          { XX } },
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     /* 78 */
7656     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7657     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7658     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7659     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7660     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7661     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7662     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7663     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7664     /* 80 */
7665     { "(bad)",          { XX } },
7666     { "(bad)",          { XX } },
7667     { "(bad)",          { XX } },
7668     { "(bad)",          { XX } },
7669     { "(bad)",          { XX } },
7670     { "(bad)",          { XX } },
7671     { "(bad)",          { XX } },
7672     { "(bad)",          { XX } },
7673     /* 88 */
7674     { "(bad)",          { XX } },
7675     { "(bad)",          { XX } },
7676     { "(bad)",          { XX } },
7677     { "(bad)",          { XX } },
7678     { "(bad)",          { XX } },
7679     { "(bad)",          { XX } },
7680     { "(bad)",          { XX } },
7681     { "(bad)",          { XX } },
7682     /* 90 */
7683     { "(bad)",          { XX } },
7684     { "(bad)",          { XX } },
7685     { "(bad)",          { XX } },
7686     { "(bad)",          { XX } },
7687     { "(bad)",          { XX } },
7688     { "(bad)",          { XX } },
7689     { "(bad)",          { XX } },
7690     { "(bad)",          { XX } },
7691     /* 98 */
7692     { "(bad)",          { XX } },
7693     { "(bad)",          { XX } },
7694     { "(bad)",          { XX } },
7695     { "(bad)",          { XX } },
7696     { "(bad)",          { XX } },
7697     { "(bad)",          { XX } },
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     /* a0 */
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     { "(bad)",          { XX } },
7704     { "(bad)",          { XX } },
7705     { "(bad)",          { XX } },
7706     { "(bad)",          { XX } },
7707     { "(bad)",          { XX } },
7708     { "(bad)",          { XX } },
7709     /* a8 */
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     { "(bad)",          { XX } },
7713     { "(bad)",          { XX } },
7714     { "(bad)",          { XX } },
7715     { "(bad)",          { XX } },
7716     { "(bad)",          { XX } },
7717     { "(bad)",          { XX } },
7718     /* b0 */
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     { "(bad)",          { XX } },
7722     { "(bad)",          { XX } },
7723     { "(bad)",          { XX } },
7724     { "(bad)",          { XX } },
7725     { "(bad)",          { XX } },
7726     { "(bad)",          { XX } },
7727     /* b8 */
7728     { "(bad)",          { XX } },
7729     { "(bad)",          { XX } },
7730     { "(bad)",          { XX } },
7731     { "(bad)",          { XX } },
7732     { "(bad)",          { XX } },
7733     { "(bad)",          { XX } },
7734     { "(bad)",          { XX } },
7735     { "(bad)",          { XX } },
7736     /* c0 */
7737     { "(bad)",          { XX } },
7738     { "(bad)",          { XX } },
7739     { "(bad)",          { XX } },
7740     { "(bad)",          { XX } },
7741     { "(bad)",          { XX } },
7742     { "(bad)",          { XX } },
7743     { "(bad)",          { XX } },
7744     { "(bad)",          { XX } },
7745     /* c8 */
7746     { "(bad)",          { XX } },
7747     { "(bad)",          { XX } },
7748     { "(bad)",          { XX } },
7749     { "(bad)",          { XX } },
7750     { "(bad)",          { XX } },
7751     { "(bad)",          { XX } },
7752     { "(bad)",          { XX } },
7753     { "(bad)",          { XX } },
7754     /* d0 */
7755     { "(bad)",          { XX } },
7756     { "(bad)",          { XX } },
7757     { "(bad)",          { XX } },
7758     { "(bad)",          { XX } },
7759     { "(bad)",          { XX } },
7760     { "(bad)",          { XX } },
7761     { "(bad)",          { XX } },
7762     { "(bad)",          { XX } },
7763     /* d8 */
7764     { "(bad)",          { XX } },
7765     { "(bad)",          { XX } },
7766     { "(bad)",          { XX } },
7767     { "(bad)",          { XX } },
7768     { "(bad)",          { XX } },
7769     { "(bad)",          { XX } },
7770     { "(bad)",          { XX } },
7771     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7772     /* e0 */
7773     { "(bad)",          { XX } },
7774     { "(bad)",          { XX } },
7775     { "(bad)",          { XX } },
7776     { "(bad)",          { XX } },
7777     { "(bad)",          { XX } },
7778     { "(bad)",          { XX } },
7779     { "(bad)",          { XX } },
7780     { "(bad)",          { XX } },
7781     /* e8 */
7782     { "(bad)",          { XX } },
7783     { "(bad)",          { XX } },
7784     { "(bad)",          { XX } },
7785     { "(bad)",          { XX } },
7786     { "(bad)",          { XX } },
7787     { "(bad)",          { XX } },
7788     { "(bad)",          { XX } },
7789     { "(bad)",          { XX } },
7790     /* f0 */
7791     { "(bad)",          { XX } },
7792     { "(bad)",          { XX } },
7793     { "(bad)",          { XX } },
7794     { "(bad)",          { XX } },
7795     { "(bad)",          { XX } },
7796     { "(bad)",          { XX } },
7797     { "(bad)",          { XX } },
7798     { "(bad)",          { XX } },
7799     /* f8 */
7800     { "(bad)",          { XX } },
7801     { "(bad)",          { XX } },
7802     { "(bad)",          { XX } },
7803     { "(bad)",          { XX } },
7804     { "(bad)",          { XX } },
7805     { "(bad)",          { XX } },
7806     { "(bad)",          { XX } },
7807     { "(bad)",          { XX } },
7808   },
7809 };
7810
7811 static const struct dis386 vex_len_table[][2] = {
7812   /* VEX_LEN_10_P_1 */
7813   {
7814     { "vmovss",         { XMVex, Vex128, EXd } },
7815     { "(bad)",          { XX } },
7816   },
7817
7818   /* VEX_LEN_10_P_3 */
7819   {
7820     { "vmovsd",         { XMVex, Vex128, EXq } },
7821     { "(bad)",          { XX } },
7822   },
7823
7824   /* VEX_LEN_11_P_1 */
7825   {
7826     { "vmovss",         { EXdVex, Vex128, XM } },
7827     { "(bad)",          { XX } },
7828   },
7829
7830   /* VEX_LEN_11_P_3 */
7831   {
7832     { "vmovsd",         { EXqVex, Vex128, XM } },
7833     { "(bad)",          { XX } },
7834   },
7835
7836   /* VEX_LEN_12_P_0_M_0 */
7837   {
7838     { "vmovlps",        { XM, Vex128, EXq } },
7839     { "(bad)",          { XX } },
7840   },
7841
7842   /* VEX_LEN_12_P_0_M_1 */
7843   {
7844     { "vmovhlps",       { XM, Vex128, EXq } },
7845     { "(bad)",          { XX } },
7846   },
7847
7848   /* VEX_LEN_12_P_2 */
7849   {
7850     { "vmovlpd",        { XM, Vex128, EXq } },
7851     { "(bad)",          { XX } },
7852   },
7853
7854   /* VEX_LEN_13_M_0 */
7855   {
7856     { "vmovlpX",        { EXq, XM } },
7857     { "(bad)",          { XX } },
7858   },
7859
7860   /* VEX_LEN_16_P_0_M_0 */
7861   {
7862     { "vmovhps",        { XM, Vex128, EXq } },
7863     { "(bad)",          { XX } },
7864   },
7865
7866   /* VEX_LEN_16_P_0_M_1 */
7867   {
7868     { "vmovlhps",       { XM, Vex128, EXq } },
7869     { "(bad)",          { XX } },
7870   },
7871
7872   /* VEX_LEN_16_P_2 */
7873   {
7874     { "vmovhpd",        { XM, Vex128, EXq } },
7875     { "(bad)",          { XX } },
7876   },
7877
7878   /* VEX_LEN_17_M_0 */
7879   {
7880     { "vmovhpX",        { EXq, XM } },
7881     { "(bad)",          { XX } },
7882   },
7883
7884   /* VEX_LEN_2A_P_1 */
7885   {
7886     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7887     { "(bad)",          { XX } },
7888   },
7889
7890   /* VEX_LEN_2A_P_3 */
7891   {
7892     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7893     { "(bad)",          { XX } },
7894   },
7895
7896   /* VEX_LEN_2B_M_0 */
7897   {
7898     { "vmovntpX",       { Mx, XM } },
7899     { "(bad)",          { XX } },
7900   },
7901
7902   /* VEX_LEN_2C_P_1 */
7903   {
7904     { "vcvttss2siY",    { Gv, EXd } },
7905     { "(bad)",          { XX } },
7906   },
7907
7908   /* VEX_LEN_2C_P_3 */
7909   {
7910     { "vcvttsd2siY",    { Gv, EXq } },
7911     { "(bad)",          { XX } },
7912   },
7913
7914   /* VEX_LEN_2D_P_1 */
7915   {
7916     { "vcvtss2siY",     { Gv, EXd } },
7917     { "(bad)",          { XX } },
7918   },
7919
7920   /* VEX_LEN_2D_P_3 */
7921   {
7922     { "vcvtsd2siY",     { Gv, EXq } },
7923     { "(bad)",          { XX } },
7924   },
7925
7926   /* VEX_LEN_2E_P_0 */
7927   {
7928     { "vucomiss",       { XM, EXd } },
7929     { "(bad)",          { XX } },
7930   },
7931
7932   /* VEX_LEN_2E_P_2 */
7933   {
7934     { "vucomisd",       { XM, EXq } },
7935     { "(bad)",          { XX } },
7936   },
7937
7938   /* VEX_LEN_2F_P_0 */
7939   {
7940     { "vcomiss",        { XM, EXd } },
7941     { "(bad)",          { XX } },
7942   },
7943
7944   /* VEX_LEN_2F_P_2 */
7945   {
7946     { "vcomisd",        { XM, EXq } },
7947     { "(bad)",          { XX } },
7948   },
7949
7950   /* VEX_LEN_51_P_1 */
7951   {
7952     { "vsqrtss",        { XM, Vex128, EXd } },
7953     { "(bad)",          { XX } },
7954   },
7955
7956   /* VEX_LEN_51_P_3 */
7957   {
7958     { "vsqrtsd",        { XM, Vex128, EXq } },
7959     { "(bad)",          { XX } },
7960   },
7961
7962   /* VEX_LEN_52_P_1 */
7963   {
7964     { "vrsqrtss",       { XM, Vex128, EXd } },
7965     { "(bad)",          { XX } },
7966   },
7967
7968   /* VEX_LEN_53_P_1 */
7969   {
7970     { "vrcpss",         { XM, Vex128, EXd } },
7971     { "(bad)",          { XX } },
7972   },
7973
7974   /* VEX_LEN_58_P_1 */
7975   {
7976     { "vaddss",         { XM, Vex128, EXd } },
7977     { "(bad)",          { XX } },
7978   },
7979
7980   /* VEX_LEN_58_P_3 */
7981   {
7982     { "vaddsd",         { XM, Vex128, EXq } },
7983     { "(bad)",          { XX } },
7984   },
7985
7986   /* VEX_LEN_59_P_1 */
7987   {
7988     { "vmulss",         { XM, Vex128, EXd } },
7989     { "(bad)",          { XX } },
7990   },
7991
7992   /* VEX_LEN_59_P_3 */
7993   {
7994     { "vmulsd",         { XM, Vex128, EXq } },
7995     { "(bad)",          { XX } },
7996   },
7997
7998   /* VEX_LEN_5A_P_1 */
7999   {
8000     { "vcvtss2sd",      { XM, Vex128, EXd } },
8001     { "(bad)",          { XX } },
8002   },
8003
8004   /* VEX_LEN_5A_P_3 */
8005   {
8006     { "vcvtsd2ss",      { XM, Vex128, EXq } },
8007     { "(bad)",          { XX } },
8008   },
8009
8010   /* VEX_LEN_5C_P_1 */
8011   {
8012     { "vsubss",         { XM, Vex128, EXd } },
8013     { "(bad)",          { XX } },
8014   },
8015
8016   /* VEX_LEN_5C_P_3 */
8017   {
8018     { "vsubsd",         { XM, Vex128, EXq } },
8019     { "(bad)",          { XX } },
8020   },
8021
8022   /* VEX_LEN_5D_P_1 */
8023   {
8024     { "vminss",         { XM, Vex128, EXd } },
8025     { "(bad)",          { XX } },
8026   },
8027
8028   /* VEX_LEN_5D_P_3 */
8029   {
8030     { "vminsd",         { XM, Vex128, EXq } },
8031     { "(bad)",          { XX } },
8032   },
8033
8034   /* VEX_LEN_5E_P_1 */
8035   {
8036     { "vdivss",         { XM, Vex128, EXd } },
8037     { "(bad)",          { XX } },
8038   },
8039
8040   /* VEX_LEN_5E_P_3 */
8041   {
8042     { "vdivsd",         { XM, Vex128, EXq } },
8043     { "(bad)",          { XX } },
8044   },
8045
8046   /* VEX_LEN_5F_P_1 */
8047   {
8048     { "vmaxss",         { XM, Vex128, EXd } },
8049     { "(bad)",          { XX } },
8050   },
8051
8052   /* VEX_LEN_5F_P_3 */
8053   {
8054     { "vmaxsd",         { XM, Vex128, EXq } },
8055     { "(bad)",          { XX } },
8056   },
8057
8058   /* VEX_LEN_60_P_2 */
8059   {
8060     { "vpunpcklbw",     { XM, Vex128, EXx } },
8061     { "(bad)",          { XX } },
8062   },
8063
8064   /* VEX_LEN_61_P_2 */
8065   {
8066     { "vpunpcklwd",     { XM, Vex128, EXx } },
8067     { "(bad)",          { XX } },
8068   },
8069
8070   /* VEX_LEN_62_P_2 */
8071   {
8072     { "vpunpckldq",     { XM, Vex128, EXx } },
8073     { "(bad)",          { XX } },
8074   },
8075
8076   /* VEX_LEN_63_P_2 */
8077   {
8078     { "vpacksswb",      { XM, Vex128, EXx } },
8079     { "(bad)",          { XX } },
8080   },
8081
8082   /* VEX_LEN_64_P_2 */
8083   {
8084     { "vpcmpgtb",       { XM, Vex128, EXx } },
8085     { "(bad)",          { XX } },
8086   },
8087
8088   /* VEX_LEN_65_P_2 */
8089   {
8090     { "vpcmpgtw",       { XM, Vex128, EXx } },
8091     { "(bad)",          { XX } },
8092   },
8093
8094   /* VEX_LEN_66_P_2 */
8095   {
8096     { "vpcmpgtd",       { XM, Vex128, EXx } },
8097     { "(bad)",          { XX } },
8098   },
8099
8100   /* VEX_LEN_67_P_2 */
8101   {
8102     { "vpackuswb",      { XM, Vex128, EXx } },
8103     { "(bad)",          { XX } },
8104   },
8105
8106   /* VEX_LEN_68_P_2 */
8107   {
8108     { "vpunpckhbw",     { XM, Vex128, EXx } },
8109     { "(bad)",          { XX } },
8110   },
8111
8112   /* VEX_LEN_69_P_2 */
8113   {
8114     { "vpunpckhwd",     { XM, Vex128, EXx } },
8115     { "(bad)",          { XX } },
8116   },
8117
8118   /* VEX_LEN_6A_P_2 */
8119   {
8120     { "vpunpckhdq",     { XM, Vex128, EXx } },
8121     { "(bad)",          { XX } },
8122   },
8123
8124   /* VEX_LEN_6B_P_2 */
8125   {
8126     { "vpackssdw",      { XM, Vex128, EXx } },
8127     { "(bad)",          { XX } },
8128   },
8129
8130   /* VEX_LEN_6C_P_2 */
8131   {
8132     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8133     { "(bad)",          { XX } },
8134   },
8135
8136   /* VEX_LEN_6D_P_2 */
8137   {
8138     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8139     { "(bad)",          { XX } },
8140   },
8141
8142   /* VEX_LEN_6E_P_2 */
8143   {
8144     { "vmovK",          { XM, Edq } },
8145     { "(bad)",          { XX } },
8146   },
8147
8148   /* VEX_LEN_70_P_1 */
8149   {
8150     { "vpshufhw",       { XM, EXx, Ib } },
8151     { "(bad)",          { XX } },
8152   },
8153
8154   /* VEX_LEN_70_P_2 */
8155   {
8156     { "vpshufd",        { XM, EXx, Ib } },
8157     { "(bad)",          { XX } },
8158   },
8159
8160   /* VEX_LEN_70_P_3 */
8161   {
8162     { "vpshuflw",       { XM, EXx, Ib } },
8163     { "(bad)",          { XX } },
8164   },
8165
8166   /* VEX_LEN_71_R_2_P_2 */
8167   {
8168     { "vpsrlw",         { Vex128, XS, Ib } },
8169     { "(bad)",          { XX } },
8170   },
8171
8172   /* VEX_LEN_71_R_4_P_2 */
8173   {
8174     { "vpsraw",         { Vex128, XS, Ib } },
8175     { "(bad)",          { XX } },
8176   },
8177
8178   /* VEX_LEN_71_R_6_P_2 */
8179   {
8180     { "vpsllw",         { Vex128, XS, Ib } },
8181     { "(bad)",          { XX } },
8182   },
8183
8184   /* VEX_LEN_72_R_2_P_2 */
8185   {
8186     { "vpsrld",         { Vex128, XS, Ib } },
8187     { "(bad)",          { XX } },
8188   },
8189
8190   /* VEX_LEN_72_R_4_P_2 */
8191   {
8192     { "vpsrad",         { Vex128, XS, Ib } },
8193     { "(bad)",          { XX } },
8194   },
8195
8196   /* VEX_LEN_72_R_6_P_2 */
8197   {
8198     { "vpslld",         { Vex128, XS, Ib } },
8199     { "(bad)",          { XX } },
8200   },
8201
8202   /* VEX_LEN_73_R_2_P_2 */
8203   {
8204     { "vpsrlq",         { Vex128, XS, Ib } },
8205     { "(bad)",          { XX } },
8206   },
8207
8208   /* VEX_LEN_73_R_3_P_2 */
8209   {
8210     { "vpsrldq",        { Vex128, XS, Ib } },
8211     { "(bad)",          { XX } },
8212   },
8213
8214   /* VEX_LEN_73_R_6_P_2 */
8215   {
8216     { "vpsllq",         { Vex128, XS, Ib } },
8217     { "(bad)",          { XX } },
8218   },
8219
8220   /* VEX_LEN_73_R_7_P_2 */
8221   {
8222     { "vpslldq",        { Vex128, XS, Ib } },
8223     { "(bad)",          { XX } },
8224   },
8225
8226   /* VEX_LEN_74_P_2 */
8227   {
8228     { "vpcmpeqb",       { XM, Vex128, EXx } },
8229     { "(bad)",          { XX } },
8230   },
8231
8232   /* VEX_LEN_75_P_2 */
8233   {
8234     { "vpcmpeqw",       { XM, Vex128, EXx } },
8235     { "(bad)",          { XX } },
8236   },
8237
8238   /* VEX_LEN_76_P_2 */
8239   {
8240     { "vpcmpeqd",       { XM, Vex128, EXx } },
8241     { "(bad)",          { XX } },
8242   },
8243
8244   /* VEX_LEN_7E_P_1 */
8245   {
8246     { "vmovq",          { XM, EXq } },
8247     { "(bad)",          { XX } },
8248   },
8249
8250   /* VEX_LEN_7E_P_2 */
8251   {
8252     { "vmovK",          { Edq, XM } },
8253     { "(bad)",          { XX } },
8254   },
8255
8256   /* VEX_LEN_AE_R_2_M0 */
8257   {
8258     { "vldmxcsr",       { Md } },
8259     { "(bad)",          { XX } },
8260   },
8261
8262   /* VEX_LEN_AE_R_3_M0 */
8263   {
8264     { "vstmxcsr",       { Md } },
8265     { "(bad)",          { XX } },
8266   },
8267
8268   /* VEX_LEN_C2_P_1 */
8269   {
8270     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8271     { "(bad)",          { XX } },
8272   },
8273
8274   /* VEX_LEN_C2_P_3 */
8275   {
8276     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8277     { "(bad)",          { XX } },
8278   },
8279
8280   /* VEX_LEN_C4_P_2 */
8281   {
8282     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8283     { "(bad)",          { XX } },
8284   },
8285
8286   /* VEX_LEN_C5_P_2 */
8287   {
8288     { "vpextrw",        { Gdq, XS, Ib } },
8289     { "(bad)",          { XX } },
8290   },
8291
8292   /* VEX_LEN_D1_P_2 */
8293   {
8294     { "vpsrlw",         { XM, Vex128, EXx } },
8295     { "(bad)",          { XX } },
8296   },
8297
8298   /* VEX_LEN_D2_P_2 */
8299   {
8300     { "vpsrld",         { XM, Vex128, EXx } },
8301     { "(bad)",          { XX } },
8302   },
8303
8304   /* VEX_LEN_D3_P_2 */
8305   {
8306     { "vpsrlq",         { XM, Vex128, EXx } },
8307     { "(bad)",          { XX } },
8308   },
8309
8310   /* VEX_LEN_D4_P_2 */
8311   {
8312     { "vpaddq",         { XM, Vex128, EXx } },
8313     { "(bad)",          { XX } },
8314   },
8315
8316   /* VEX_LEN_D5_P_2 */
8317   {
8318     { "vpmullw",        { XM, Vex128, EXx } },
8319     { "(bad)",          { XX } },
8320   },
8321
8322   /* VEX_LEN_D6_P_2 */
8323   {
8324     { "vmovq",          { EXq, XM } },
8325     { "(bad)",          { XX } },
8326   },
8327
8328   /* VEX_LEN_D7_P_2_M_1 */
8329   {
8330     { "vpmovmskb",      { Gdq, XS } },
8331     { "(bad)",          { XX } },
8332   },
8333
8334   /* VEX_LEN_D8_P_2 */
8335   {
8336     { "vpsubusb",       { XM, Vex128, EXx } },
8337     { "(bad)",          { XX } },
8338   },
8339
8340   /* VEX_LEN_D9_P_2 */
8341   {
8342     { "vpsubusw",       { XM, Vex128, EXx } },
8343     { "(bad)",          { XX } },
8344   },
8345
8346   /* VEX_LEN_DA_P_2 */
8347   {
8348     { "vpminub",        { XM, Vex128, EXx } },
8349     { "(bad)",          { XX } },
8350   },
8351
8352   /* VEX_LEN_DB_P_2 */
8353   {
8354     { "vpand",          { XM, Vex128, EXx } },
8355     { "(bad)",          { XX } },
8356   },
8357
8358   /* VEX_LEN_DC_P_2 */
8359   {
8360     { "vpaddusb",       { XM, Vex128, EXx } },
8361     { "(bad)",          { XX } },
8362   },
8363
8364   /* VEX_LEN_DD_P_2 */
8365   {
8366     { "vpaddusw",       { XM, Vex128, EXx } },
8367     { "(bad)",          { XX } },
8368   },
8369
8370   /* VEX_LEN_DE_P_2 */
8371   {
8372     { "vpmaxub",        { XM, Vex128, EXx } },
8373     { "(bad)",          { XX } },
8374   },
8375
8376   /* VEX_LEN_DF_P_2 */
8377   {
8378     { "vpandn",         { XM, Vex128, EXx } },
8379     { "(bad)",          { XX } },
8380   },
8381
8382   /* VEX_LEN_E0_P_2 */
8383   {
8384     { "vpavgb",         { XM, Vex128, EXx } },
8385     { "(bad)",          { XX } },
8386   },
8387
8388   /* VEX_LEN_E1_P_2 */
8389   {
8390     { "vpsraw",         { XM, Vex128, EXx } },
8391     { "(bad)",          { XX } },
8392   },
8393
8394   /* VEX_LEN_E2_P_2 */
8395   {
8396     { "vpsrad",         { XM, Vex128, EXx } },
8397     { "(bad)",          { XX } },
8398   },
8399
8400   /* VEX_LEN_E3_P_2 */
8401   {
8402     { "vpavgw",         { XM, Vex128, EXx } },
8403     { "(bad)",          { XX } },
8404   },
8405
8406   /* VEX_LEN_E4_P_2 */
8407   {
8408     { "vpmulhuw",       { XM, Vex128, EXx } },
8409     { "(bad)",          { XX } },
8410   },
8411
8412   /* VEX_LEN_E5_P_2 */
8413   {
8414     { "vpmulhw",        { XM, Vex128, EXx } },
8415     { "(bad)",          { XX } },
8416   },
8417
8418   /* VEX_LEN_E7_P_2_M_0 */
8419   {
8420     { "vmovntdq",       { Mx, XM } },
8421     { "(bad)",          { XX } },
8422   },
8423
8424   /* VEX_LEN_E8_P_2 */
8425   {
8426     { "vpsubsb",        { XM, Vex128, EXx } },
8427     { "(bad)",          { XX } },
8428   },
8429
8430   /* VEX_LEN_E9_P_2 */
8431   {
8432     { "vpsubsw",        { XM, Vex128, EXx } },
8433     { "(bad)",          { XX } },
8434   },
8435
8436   /* VEX_LEN_EA_P_2 */
8437   {
8438     { "vpminsw",        { XM, Vex128, EXx } },
8439     { "(bad)",          { XX } },
8440   },
8441
8442   /* VEX_LEN_EB_P_2 */
8443   {
8444     { "vpor",           { XM, Vex128, EXx } },
8445     { "(bad)",          { XX } },
8446   },
8447
8448   /* VEX_LEN_EC_P_2 */
8449   {
8450     { "vpaddsb",        { XM, Vex128, EXx } },
8451     { "(bad)",          { XX } },
8452   },
8453
8454   /* VEX_LEN_ED_P_2 */
8455   {
8456     { "vpaddsw",        { XM, Vex128, EXx } },
8457     { "(bad)",          { XX } },
8458   },
8459
8460   /* VEX_LEN_EE_P_2 */
8461   {
8462     { "vpmaxsw",        { XM, Vex128, EXx } },
8463     { "(bad)",          { XX } },
8464   },
8465
8466   /* VEX_LEN_EF_P_2 */
8467   {
8468     { "vpxor",          { XM, Vex128, EXx } },
8469     { "(bad)",          { XX } },
8470   },
8471
8472   /* VEX_LEN_F1_P_2 */
8473   {
8474     { "vpsllw",         { XM, Vex128, EXx } },
8475     { "(bad)",          { XX } },
8476   },
8477
8478   /* VEX_LEN_F2_P_2 */
8479   {
8480     { "vpslld",         { XM, Vex128, EXx } },
8481     { "(bad)",          { XX } },
8482   },
8483
8484   /* VEX_LEN_F3_P_2 */
8485   {
8486     { "vpsllq",         { XM, Vex128, EXx } },
8487     { "(bad)",          { XX } },
8488   },
8489
8490   /* VEX_LEN_F4_P_2 */
8491   {
8492     { "vpmuludq",       { XM, Vex128, EXx } },
8493     { "(bad)",          { XX } },
8494   },
8495
8496   /* VEX_LEN_F5_P_2 */
8497   {
8498     { "vpmaddwd",       { XM, Vex128, EXx } },
8499     { "(bad)",          { XX } },
8500   },
8501
8502   /* VEX_LEN_F6_P_2 */
8503   {
8504     { "vpsadbw",        { XM, Vex128, EXx } },
8505     { "(bad)",          { XX } },
8506   },
8507
8508   /* VEX_LEN_F7_P_2 */
8509   {
8510     { "vmaskmovdqu",    { XM, XS } },
8511     { "(bad)",          { XX } },
8512   },
8513
8514   /* VEX_LEN_F8_P_2 */
8515   {
8516     { "vpsubb",         { XM, Vex128, EXx } },
8517     { "(bad)",          { XX } },
8518   },
8519
8520   /* VEX_LEN_F9_P_2 */
8521   {
8522     { "vpsubw",         { XM, Vex128, EXx } },
8523     { "(bad)",          { XX } },
8524   },
8525
8526   /* VEX_LEN_FA_P_2 */
8527   {
8528     { "vpsubd",         { XM, Vex128, EXx } },
8529     { "(bad)",          { XX } },
8530   },
8531
8532   /* VEX_LEN_FB_P_2 */
8533   {
8534     { "vpsubq",         { XM, Vex128, EXx } },
8535     { "(bad)",          { XX } },
8536   },
8537
8538   /* VEX_LEN_FC_P_2 */
8539   {
8540     { "vpaddb",         { XM, Vex128, EXx } },
8541     { "(bad)",          { XX } },
8542   },
8543
8544   /* VEX_LEN_FD_P_2 */
8545   {
8546     { "vpaddw",         { XM, Vex128, EXx } },
8547     { "(bad)",          { XX } },
8548   },
8549
8550   /* VEX_LEN_FE_P_2 */
8551   {
8552     { "vpaddd",         { XM, Vex128, EXx } },
8553     { "(bad)",          { XX } },
8554   },
8555
8556   /* VEX_LEN_3800_P_2 */
8557   {
8558     { "vpshufb",        { XM, Vex128, EXx } },
8559     { "(bad)",          { XX } },
8560   },
8561
8562   /* VEX_LEN_3801_P_2 */
8563   {
8564     { "vphaddw",        { XM, Vex128, EXx } },
8565     { "(bad)",          { XX } },
8566   },
8567
8568   /* VEX_LEN_3802_P_2 */
8569   {
8570     { "vphaddd",        { XM, Vex128, EXx } },
8571     { "(bad)",          { XX } },
8572   },
8573
8574   /* VEX_LEN_3803_P_2 */
8575   {
8576     { "vphaddsw",       { XM, Vex128, EXx } },
8577     { "(bad)",          { XX } },
8578   },
8579
8580   /* VEX_LEN_3804_P_2 */
8581   {
8582     { "vpmaddubsw",     { XM, Vex128, EXx } },
8583     { "(bad)",          { XX } },
8584   },
8585
8586   /* VEX_LEN_3805_P_2 */
8587   {
8588     { "vphsubw",        { XM, Vex128, EXx } },
8589     { "(bad)",          { XX } },
8590   },
8591
8592   /* VEX_LEN_3806_P_2 */
8593   {
8594     { "vphsubd",        { XM, Vex128, EXx } },
8595     { "(bad)",          { XX } },
8596   },
8597
8598   /* VEX_LEN_3807_P_2 */
8599   {
8600     { "vphsubsw",       { XM, Vex128, EXx } },
8601     { "(bad)",          { XX } },
8602   },
8603
8604   /* VEX_LEN_3808_P_2 */
8605   {
8606     { "vpsignb",        { XM, Vex128, EXx } },
8607     { "(bad)",          { XX } },
8608   },
8609
8610   /* VEX_LEN_3809_P_2 */
8611   {
8612     { "vpsignw",        { XM, Vex128, EXx } },
8613     { "(bad)",          { XX } },
8614   },
8615
8616   /* VEX_LEN_380A_P_2 */
8617   {
8618     { "vpsignd",        { XM, Vex128, EXx } },
8619     { "(bad)",          { XX } },
8620   },
8621
8622   /* VEX_LEN_380B_P_2 */
8623   {
8624     { "vpmulhrsw",      { XM, Vex128, EXx } },
8625     { "(bad)",          { XX } },
8626   },
8627
8628   /* VEX_LEN_3819_P_2_M_0 */
8629   {
8630     { "(bad)",          { XX } },
8631     { "vbroadcastsd",   { XM, Mq } },
8632   },
8633
8634   /* VEX_LEN_381A_P_2_M_0 */
8635   {
8636     { "(bad)",          { XX } },
8637     { "vbroadcastf128", { XM, Mxmm } },
8638   },
8639
8640   /* VEX_LEN_381C_P_2 */
8641   {
8642     { "vpabsb",         { XM, EXx } },
8643     { "(bad)",          { XX } },
8644   },
8645
8646   /* VEX_LEN_381D_P_2 */
8647   {
8648     { "vpabsw",         { XM, EXx } },
8649     { "(bad)",          { XX } },
8650   },
8651
8652   /* VEX_LEN_381E_P_2 */
8653   {
8654     { "vpabsd",         { XM, EXx } },
8655     { "(bad)",          { XX } },
8656   },
8657
8658   /* VEX_LEN_3820_P_2 */
8659   {
8660     { "vpmovsxbw",      { XM, EXq } },
8661     { "(bad)",          { XX } },
8662   },
8663
8664   /* VEX_LEN_3821_P_2 */
8665   {
8666     { "vpmovsxbd",      { XM, EXd } },
8667     { "(bad)",          { XX } },
8668   },
8669
8670   /* VEX_LEN_3822_P_2 */
8671   {
8672     { "vpmovsxbq",      { XM, EXw } },
8673     { "(bad)",          { XX } },
8674   },
8675
8676   /* VEX_LEN_3823_P_2 */
8677   {
8678     { "vpmovsxwd",      { XM, EXq } },
8679     { "(bad)",          { XX } },
8680   },
8681
8682   /* VEX_LEN_3824_P_2 */
8683   {
8684     { "vpmovsxwq",      { XM, EXd } },
8685     { "(bad)",          { XX } },
8686   },
8687
8688   /* VEX_LEN_3825_P_2 */
8689   {
8690     { "vpmovsxdq",      { XM, EXq } },
8691     { "(bad)",          { XX } },
8692   },
8693
8694   /* VEX_LEN_3828_P_2 */
8695   {
8696     { "vpmuldq",        { XM, Vex128, EXx } },
8697     { "(bad)",          { XX } },
8698   },
8699
8700   /* VEX_LEN_3829_P_2 */
8701   {
8702     { "vpcmpeqq",       { XM, Vex128, EXx } },
8703     { "(bad)",          { XX } },
8704   },
8705
8706   /* VEX_LEN_382A_P_2_M_0 */
8707   {
8708     { "vmovntdqa",      { XM, Mx } },
8709     { "(bad)",          { XX } },
8710   },
8711
8712   /* VEX_LEN_382B_P_2 */
8713   {
8714     { "vpackusdw",      { XM, Vex128, EXx } },
8715     { "(bad)",          { XX } },
8716   },
8717
8718   /* VEX_LEN_3830_P_2 */
8719   {
8720     { "vpmovzxbw",      { XM, EXq } },
8721     { "(bad)",          { XX } },
8722   },
8723
8724   /* VEX_LEN_3831_P_2 */
8725   {
8726     { "vpmovzxbd",      { XM, EXd } },
8727     { "(bad)",          { XX } },
8728   },
8729
8730   /* VEX_LEN_3832_P_2 */
8731   {
8732     { "vpmovzxbq",      { XM, EXw } },
8733     { "(bad)",          { XX } },
8734   },
8735
8736   /* VEX_LEN_3833_P_2 */
8737   {
8738     { "vpmovzxwd",      { XM, EXq } },
8739     { "(bad)",          { XX } },
8740   },
8741
8742   /* VEX_LEN_3834_P_2 */
8743   {
8744     { "vpmovzxwq",      { XM, EXd } },
8745     { "(bad)",          { XX } },
8746   },
8747
8748   /* VEX_LEN_3835_P_2 */
8749   {
8750     { "vpmovzxdq",      { XM, EXq } },
8751     { "(bad)",          { XX } },
8752   },
8753
8754   /* VEX_LEN_3837_P_2 */
8755   {
8756     { "vpcmpgtq",       { XM, Vex128, EXx } },
8757     { "(bad)",          { XX } },
8758   },
8759
8760   /* VEX_LEN_3838_P_2 */
8761   {
8762     { "vpminsb",        { XM, Vex128, EXx } },
8763     { "(bad)",          { XX } },
8764   },
8765
8766   /* VEX_LEN_3839_P_2 */
8767   {
8768     { "vpminsd",        { XM, Vex128, EXx } },
8769     { "(bad)",          { XX } },
8770   },
8771
8772   /* VEX_LEN_383A_P_2 */
8773   {
8774     { "vpminuw",        { XM, Vex128, EXx } },
8775     { "(bad)",          { XX } },
8776   },
8777
8778   /* VEX_LEN_383B_P_2 */
8779   {
8780     { "vpminud",        { XM, Vex128, EXx } },
8781     { "(bad)",          { XX } },
8782   },
8783
8784   /* VEX_LEN_383C_P_2 */
8785   {
8786     { "vpmaxsb",        { XM, Vex128, EXx } },
8787     { "(bad)",          { XX } },
8788   },
8789
8790   /* VEX_LEN_383D_P_2 */
8791   {
8792     { "vpmaxsd",        { XM, Vex128, EXx } },
8793     { "(bad)",          { XX } },
8794   },
8795
8796   /* VEX_LEN_383E_P_2 */
8797   {
8798     { "vpmaxuw",        { XM, Vex128, EXx } },
8799     { "(bad)",          { XX } },
8800   },
8801
8802   /* VEX_LEN_383F_P_2 */
8803   {
8804     { "vpmaxud",        { XM, Vex128, EXx } },
8805     { "(bad)",          { XX } },
8806   },
8807
8808   /* VEX_LEN_3840_P_2 */
8809   {
8810     { "vpmulld",        { XM, Vex128, EXx } },
8811     { "(bad)",          { XX } },
8812   },
8813
8814   /* VEX_LEN_3841_P_2 */
8815   {
8816     { "vphminposuw",    { XM, EXx } },
8817     { "(bad)",          { XX } },
8818   },
8819
8820   /* VEX_LEN_38DB_P_2 */
8821   {
8822     { "vaesimc",        { XM, EXx } },
8823     { "(bad)",          { XX } },
8824   },
8825
8826   /* VEX_LEN_38DC_P_2 */
8827   {
8828     { "vaesenc",        { XM, Vex128, EXx } },
8829     { "(bad)",          { XX } },
8830   },
8831
8832   /* VEX_LEN_38DD_P_2 */
8833   {
8834     { "vaesenclast",    { XM, Vex128, EXx } },
8835     { "(bad)",          { XX } },
8836   },
8837
8838   /* VEX_LEN_38DE_P_2 */
8839   {
8840     { "vaesdec",        { XM, Vex128, EXx } },
8841     { "(bad)",          { XX } },
8842   },
8843
8844   /* VEX_LEN_38DF_P_2 */
8845   {
8846     { "vaesdeclast",    { XM, Vex128, EXx } },
8847     { "(bad)",          { XX } },
8848   },
8849
8850   /* VEX_LEN_3A06_P_2 */
8851   {
8852     { "(bad)",          { XX } },
8853     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8854   },
8855
8856   /* VEX_LEN_3A0A_P_2 */
8857   {
8858     { "vroundss",       { XM, Vex128, EXd, Ib } },
8859     { "(bad)",          { XX } },
8860   },
8861
8862   /* VEX_LEN_3A0B_P_2 */
8863   {
8864     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8865     { "(bad)",          { XX } },
8866   },
8867
8868   /* VEX_LEN_3A0E_P_2 */
8869   {
8870     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8871     { "(bad)",          { XX } },
8872   },
8873
8874   /* VEX_LEN_3A0F_P_2 */
8875   {
8876     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8877     { "(bad)",          { XX } },
8878   },
8879
8880   /* VEX_LEN_3A14_P_2 */
8881   {
8882     { "vpextrb",        { Edqb, XM, Ib } },
8883     { "(bad)",          { XX } },
8884   },
8885
8886   /* VEX_LEN_3A15_P_2 */
8887   {
8888     { "vpextrw",        { Edqw, XM, Ib } },
8889     { "(bad)",          { XX } },
8890   },
8891
8892   /* VEX_LEN_3A16_P_2  */
8893   {
8894     { "vpextrK",        { Edq, XM, Ib } },
8895     { "(bad)",          { XX } },
8896   },
8897
8898   /* VEX_LEN_3A17_P_2 */
8899   {
8900     { "vextractps",     { Edqd, XM, Ib } },
8901     { "(bad)",          { XX } },
8902   },
8903
8904   /* VEX_LEN_3A18_P_2 */
8905   {
8906     { "(bad)",          { XX } },
8907     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8908   },
8909
8910   /* VEX_LEN_3A19_P_2 */
8911   {
8912     { "(bad)",          { XX } },
8913     { "vextractf128",   { EXxmm, XM, Ib } },
8914   },
8915
8916   /* VEX_LEN_3A20_P_2 */
8917   {
8918     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8919     { "(bad)",          { XX } },
8920   },
8921
8922   /* VEX_LEN_3A21_P_2 */
8923   {
8924     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8925     { "(bad)",          { XX } },
8926   },
8927
8928   /* VEX_LEN_3A22_P_2 */
8929   {
8930     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8931     { "(bad)",          { XX } },
8932   },
8933
8934   /* VEX_LEN_3A41_P_2 */
8935   {
8936     { "vdppd",          { XM, Vex128, EXx, Ib } },
8937     { "(bad)",          { XX } },
8938   },
8939
8940   /* VEX_LEN_3A42_P_2 */
8941   {
8942     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
8943     { "(bad)",          { XX } },
8944   },
8945
8946   /* VEX_LEN_3A4C_P_2 */
8947   {
8948     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
8949     { "(bad)",          { XX } },
8950   },
8951
8952   /* VEX_LEN_3A60_P_2 */
8953   {
8954     { "vpcmpestrm",     { XM, EXx, Ib } },
8955     { "(bad)",          { XX } },
8956   },
8957
8958   /* VEX_LEN_3A61_P_2 */
8959   {
8960     { "vpcmpestri",     { XM, EXx, Ib } },
8961     { "(bad)",          { XX } },
8962   },
8963
8964   /* VEX_LEN_3A62_P_2 */
8965   {
8966     { "vpcmpistrm",     { XM, EXx, Ib } },
8967     { "(bad)",          { XX } },
8968   },
8969
8970   /* VEX_LEN_3A63_P_2 */
8971   {
8972     { "vpcmpistri",     { XM, EXx, Ib } },
8973     { "(bad)",          { XX } },
8974   },
8975
8976   /* VEX_LEN_3A6A_P_2 */
8977   {
8978     { "vfmaddss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8979     { "(bad)",          { XX } },
8980   },
8981
8982   /* VEX_LEN_3A6B_P_2 */
8983   {
8984     { "vfmaddsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8985     { "(bad)",          { XX } },
8986   },
8987
8988   /* VEX_LEN_3A6E_P_2 */
8989   {
8990     { "vfmsubss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8991     { "(bad)",          { XX } },
8992   },
8993
8994   /* VEX_LEN_3A6F_P_2 */
8995   {
8996     { "vfmsubsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8997     { "(bad)",          { XX } },
8998   },
8999
9000   /* VEX_LEN_3A7A_P_2 */
9001   {
9002     { "vfnmaddss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9003     { "(bad)",          { XX } },
9004   },
9005
9006   /* VEX_LEN_3A7B_P_2 */
9007   {
9008     { "vfnmaddsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9009     { "(bad)",          { XX } },
9010   },
9011
9012   /* VEX_LEN_3A7E_P_2 */
9013   {
9014     { "vfnmsubss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9015     { "(bad)",          { XX } },
9016   },
9017
9018   /* VEX_LEN_3A7F_P_2 */
9019   {
9020     { "vfnmsubsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9021     { "(bad)",          { XX } },
9022   },
9023
9024   /* VEX_LEN_3ADF_P_2 */
9025   {
9026     { "vaeskeygenassist", { XM, EXx, Ib } },
9027     { "(bad)",          { XX } },
9028   },
9029 };
9030
9031 static const struct dis386 mod_table[][2] = {
9032   {
9033     /* MOD_8D */
9034     { "leaS",           { Gv, M } },
9035     { "(bad)",          { XX } },
9036   },
9037   {
9038     /* MOD_0F01_REG_0 */
9039     { X86_64_TABLE (X86_64_0F01_REG_0) },
9040     { RM_TABLE (RM_0F01_REG_0) },
9041   },
9042   {
9043     /* MOD_0F01_REG_1 */
9044     { X86_64_TABLE (X86_64_0F01_REG_1) },
9045     { RM_TABLE (RM_0F01_REG_1) },
9046   },
9047   {
9048     /* MOD_0F01_REG_2 */
9049     { X86_64_TABLE (X86_64_0F01_REG_2) },
9050     { RM_TABLE (RM_0F01_REG_2) },
9051   },
9052   {
9053     /* MOD_0F01_REG_3 */
9054     { X86_64_TABLE (X86_64_0F01_REG_3) },
9055     { RM_TABLE (RM_0F01_REG_3) },
9056   },
9057   {
9058     /* MOD_0F01_REG_7 */
9059     { "invlpg",         { Mb } },
9060     { RM_TABLE (RM_0F01_REG_7) },
9061   },
9062   {
9063     /* MOD_0F12_PREFIX_0 */
9064     { "movlps",         { XM, EXq } },
9065     { "movhlps",        { XM, EXq } },
9066   },
9067   {
9068     /* MOD_0F13 */
9069     { "movlpX",         { EXq, XM } },
9070     { "(bad)",          { XX } },
9071   },
9072   {
9073     /* MOD_0F16_PREFIX_0 */
9074     { "movhps",         { XM, EXq } },
9075     { "movlhps",        { XM, EXq } },
9076   },
9077   {
9078     /* MOD_0F17 */
9079     { "movhpX",         { EXq, XM } },
9080     { "(bad)",          { XX } },
9081   },
9082   {
9083     /* MOD_0F18_REG_0 */
9084     { "prefetchnta",    { Mb } },
9085     { "(bad)",          { XX } },
9086   },
9087   {
9088     /* MOD_0F18_REG_1 */
9089     { "prefetcht0",     { Mb } },
9090     { "(bad)",          { XX } },
9091   },
9092   {
9093     /* MOD_0F18_REG_2 */
9094     { "prefetcht1",     { Mb } },
9095     { "(bad)",          { XX } },
9096   },
9097   {
9098     /* MOD_0F18_REG_3 */
9099     { "prefetcht2",     { Mb } },
9100     { "(bad)",          { XX } },
9101   },
9102   {
9103     /* MOD_0F20 */
9104     { "(bad)",          { XX } },
9105     { "movZ",           { Rm, Cm } },
9106   },
9107   {
9108     /* MOD_0F21 */
9109     { "(bad)",          { XX } },
9110     { "movZ",           { Rm, Dm } },
9111   },
9112   {
9113     /* MOD_0F22 */
9114     { "(bad)",          { XX } },
9115     { "movZ",           { Cm, Rm } },
9116   },
9117   {
9118     /* MOD_0F23 */
9119     { "(bad)",          { XX } },
9120     { "movZ",           { Dm, Rm } },
9121   },
9122   {
9123     /* MOD_0F24 */
9124     { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9125     { "movL",           { Rd, Td } },
9126   },
9127   {
9128     /* MOD_0F26 */
9129     { "(bad)",          { XX } },
9130     { "movL",           { Td, Rd } },
9131   },
9132   {
9133     /* MOD_0F2B_PREFIX_0 */
9134     {"movntps",         { Mx, XM } },
9135     { "(bad)",          { XX } },
9136   },
9137   {
9138     /* MOD_0F2B_PREFIX_1 */
9139     {"movntss",         { Md, XM } },
9140     { "(bad)",          { XX } },
9141   },
9142   {
9143     /* MOD_0F2B_PREFIX_2 */
9144     {"movntpd",         { Mx, XM } },
9145     { "(bad)",          { XX } },
9146   },
9147   {
9148     /* MOD_0F2B_PREFIX_3 */
9149     {"movntsd",         { Mq, XM } },
9150     { "(bad)",          { XX } },
9151   },
9152   {
9153     /* MOD_0F51 */
9154     { "(bad)",          { XX } },
9155     { "movmskpX",       { Gdq, XS } },
9156   },
9157   {
9158     /* MOD_0F71_REG_2 */
9159     { "(bad)",          { XX } },
9160     { "psrlw",          { MS, Ib } },
9161   },
9162   {
9163     /* MOD_0F71_REG_4 */
9164     { "(bad)",          { XX } },
9165     { "psraw",          { MS, Ib } },
9166   },
9167   {
9168     /* MOD_0F71_REG_6 */
9169     { "(bad)",          { XX } },
9170     { "psllw",          { MS, Ib } },
9171   },
9172   {
9173     /* MOD_0F72_REG_2 */
9174     { "(bad)",          { XX } },
9175     { "psrld",          { MS, Ib } },
9176   },
9177   {
9178     /* MOD_0F72_REG_4 */
9179     { "(bad)",          { XX } },
9180     { "psrad",          { MS, Ib } },
9181   },
9182   {
9183     /* MOD_0F72_REG_6 */
9184     { "(bad)",          { XX } },
9185     { "pslld",          { MS, Ib } },
9186   },
9187   {
9188     /* MOD_0F73_REG_2 */
9189     { "(bad)",          { XX } },
9190     { "psrlq",          { MS, Ib } },
9191   },
9192   {
9193     /* MOD_0F73_REG_3 */
9194     { "(bad)",          { XX } },
9195     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9196   },
9197   {
9198     /* MOD_0F73_REG_6 */
9199     { "(bad)",          { XX } },
9200     { "psllq",          { MS, Ib } },
9201   },
9202   {
9203     /* MOD_0F73_REG_7 */
9204     { "(bad)",          { XX } },
9205     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9206   },
9207   {
9208     /* MOD_0FAE_REG_0 */
9209     { "fxsave",         { M } },
9210     { "(bad)",          { XX } },
9211   },
9212   {
9213     /* MOD_0FAE_REG_1 */
9214     { "fxrstor",        { M } },
9215     { "(bad)",          { XX } },
9216   },
9217   {
9218     /* MOD_0FAE_REG_2 */
9219     { "ldmxcsr",        { Md } },
9220     { "(bad)",          { XX } },
9221   },
9222   {
9223     /* MOD_0FAE_REG_3 */
9224     { "stmxcsr",        { Md } },
9225     { "(bad)",          { XX } },
9226   },
9227   {
9228     /* MOD_0FAE_REG_4 */
9229     { "xsave",          { M } },
9230     { "(bad)",          { XX } },
9231   },
9232   {
9233     /* MOD_0FAE_REG_5 */
9234     { "xrstor",         { M } },
9235     { RM_TABLE (RM_0FAE_REG_5) },
9236   },
9237   {
9238     /* MOD_0FAE_REG_6 */
9239     { "xsaveopt",       { M } },
9240     { RM_TABLE (RM_0FAE_REG_6) },
9241   },
9242   {
9243     /* MOD_0FAE_REG_7 */
9244     { "clflush",        { Mb } },
9245     { RM_TABLE (RM_0FAE_REG_7) },
9246   },
9247   {
9248     /* MOD_0FB2 */
9249     { "lssS",           { Gv, Mp } },
9250     { "(bad)",          { XX } },
9251   },
9252   {
9253     /* MOD_0FB4 */
9254     { "lfsS",           { Gv, Mp } },
9255     { "(bad)",          { XX } },
9256   },
9257   {
9258     /* MOD_0FB5 */
9259     { "lgsS",           { Gv, Mp } },
9260     { "(bad)",          { XX } },
9261   },
9262   {
9263     /* MOD_0FC7_REG_6 */
9264     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9265     { "(bad)",          { XX } },
9266   },
9267   {
9268     /* MOD_0FC7_REG_7 */
9269     { "vmptrst",        { Mq } },
9270     { "(bad)",          { XX } },
9271   },
9272   {
9273     /* MOD_0FD7 */
9274     { "(bad)",          { XX } },
9275     { "pmovmskb",       { Gdq, MS } },
9276   },
9277   {
9278     /* MOD_0FE7_PREFIX_2 */
9279     { "movntdq",        { Mx, XM } },
9280     { "(bad)",          { XX } },
9281   },
9282   {
9283     /* MOD_0FF0_PREFIX_3 */
9284     { "lddqu",          { XM, M } },
9285     { "(bad)",          { XX } },
9286   },
9287   {
9288     /* MOD_0F382A_PREFIX_2 */
9289     { "movntdqa",       { XM, Mx } },
9290     { "(bad)",          { XX } },
9291   },
9292   {
9293     /* MOD_62_32BIT */
9294     { "bound{S|}",      { Gv, Ma } },
9295     { "(bad)",          { XX } },
9296   },
9297   {
9298     /* MOD_C4_32BIT */
9299     { "lesS",           { Gv, Mp } },
9300     { VEX_C4_TABLE (VEX_0F) },
9301   },
9302   {
9303     /* MOD_C5_32BIT */
9304     { "ldsS",           { Gv, Mp } },
9305     { VEX_C5_TABLE (VEX_0F) },
9306   },
9307   {
9308     /* MOD_VEX_12_PREFIX_0 */
9309     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9310     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9311   },
9312   {
9313     /* MOD_VEX_13 */
9314     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9315     { "(bad)",          { XX } },
9316   },
9317   {
9318     /* MOD_VEX_16_PREFIX_0 */
9319     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9320     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9321   },
9322   {
9323     /* MOD_VEX_17 */
9324     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9325     { "(bad)",          { XX } },
9326   },
9327   {
9328     /* MOD_VEX_2B */
9329     { VEX_LEN_TABLE (VEX_LEN_2B_M_0) },
9330     { "(bad)",          { XX } },
9331   },
9332   {
9333     /* MOD_VEX_51 */
9334     { "(bad)",          { XX } },
9335     { "vmovmskpX",      { Gdq, XS } },
9336   },
9337   {
9338     /* MOD_VEX_71_REG_2 */
9339     { "(bad)",          { XX } },
9340     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9341   },
9342   {
9343     /* MOD_VEX_71_REG_4 */
9344     { "(bad)",          { XX } },
9345     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9346   },
9347   {
9348     /* MOD_VEX_71_REG_6 */
9349     { "(bad)",          { XX } },
9350     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9351   },
9352   {
9353     /* MOD_VEX_72_REG_2 */
9354     { "(bad)",          { XX } },
9355     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9356   },
9357   {
9358     /* MOD_VEX_72_REG_4 */
9359     { "(bad)",          { XX } },
9360     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9361   },
9362   {
9363     /* MOD_VEX_72_REG_6 */
9364     { "(bad)",          { XX } },
9365     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9366   },
9367   {
9368     /* MOD_VEX_73_REG_2 */
9369     { "(bad)",          { XX } },
9370     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9371   },
9372   {
9373     /* MOD_VEX_73_REG_3 */
9374     { "(bad)",          { XX } },
9375     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9376   },
9377   {
9378     /* MOD_VEX_73_REG_6 */
9379     { "(bad)",          { XX } },
9380     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9381   },
9382   {
9383     /* MOD_VEX_73_REG_7 */
9384     { "(bad)",          { XX } },
9385     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9386   },
9387   {
9388     /* MOD_VEX_AE_REG_2 */
9389     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9390     { "(bad)",          { XX } },
9391   },
9392   {
9393     /* MOD_VEX_AE_REG_3 */
9394     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9395     { "(bad)",          { XX } },
9396   },
9397   {
9398     /* MOD_VEX_D7_PREFIX_2 */
9399     { "(bad)",          { XX } },
9400     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9401   },
9402   {
9403     /* MOD_VEX_E7_PREFIX_2 */
9404     { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) },
9405     { "(bad)",          { XX } },
9406   },
9407   {
9408     /* MOD_VEX_F0_PREFIX_3 */
9409     { "vlddqu",         { XM, M } },
9410     { "(bad)",          { XX } },
9411   },
9412   {
9413     /* MOD_VEX_3818_PREFIX_2 */
9414     { "vbroadcastss",   { XM, Md } },
9415     { "(bad)",          { XX } },
9416   },
9417   {
9418     /* MOD_VEX_3819_PREFIX_2 */
9419     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9420     { "(bad)",          { XX } },
9421   },
9422   {
9423     /* MOD_VEX_381A_PREFIX_2 */
9424     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9425     { "(bad)",          { XX } },
9426   },
9427   {
9428     /* MOD_VEX_382A_PREFIX_2 */
9429     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9430     { "(bad)",          { XX } },
9431   },
9432   {
9433     /* MOD_VEX_382C_PREFIX_2 */
9434     { "vmaskmovps",     { XM, Vex, Mx } },
9435     { "(bad)",          { XX } },
9436   },
9437   {
9438     /* MOD_VEX_382D_PREFIX_2 */
9439     { "vmaskmovpd",     { XM, Vex, Mx } },
9440     { "(bad)",          { XX } },
9441   },
9442   {
9443     /* MOD_VEX_382E_PREFIX_2 */
9444     { "vmaskmovps",     { Mx, Vex, XM } },
9445     { "(bad)",          { XX } },
9446   },
9447   {
9448     /* MOD_VEX_382F_PREFIX_2 */
9449     { "vmaskmovpd",     { Mx, Vex, XM } },
9450     { "(bad)",          { XX } },
9451   },
9452 };
9453
9454 static const struct dis386 rm_table[][8] = {
9455   {
9456     /* RM_0F01_REG_0 */
9457     { "(bad)",          { XX } },
9458     { "vmcall",         { Skip_MODRM } },
9459     { "vmlaunch",       { Skip_MODRM } },
9460     { "vmresume",       { Skip_MODRM } },
9461     { "vmxoff",         { Skip_MODRM } },
9462     { "(bad)",          { XX } },
9463     { "(bad)",          { XX } },
9464     { "(bad)",          { XX } },
9465   },
9466   {
9467     /* RM_0F01_REG_1 */
9468     { "monitor",        { { OP_Monitor, 0 } } },
9469     { "mwait",          { { OP_Mwait, 0 } } },
9470     { "(bad)",          { XX } },
9471     { "(bad)",          { XX } },
9472     { "(bad)",          { XX } },
9473     { "(bad)",          { XX } },
9474     { "(bad)",          { XX } },
9475     { "(bad)",          { XX } },
9476   },
9477   {
9478     /* RM_0F01_REG_2 */
9479     { "xgetbv",         { Skip_MODRM } },
9480     { "xsetbv",         { Skip_MODRM } },
9481     { "(bad)",          { XX } },
9482     { "(bad)",          { XX } },
9483     { "(bad)",          { XX } },
9484     { "(bad)",          { XX } },
9485     { "(bad)",          { XX } },
9486     { "(bad)",          { XX } },
9487   },
9488   {
9489     /* RM_0F01_REG_3 */
9490     { "vmrun",          { Skip_MODRM } },
9491     { "vmmcall",        { Skip_MODRM } },
9492     { "vmload",         { Skip_MODRM } },
9493     { "vmsave",         { Skip_MODRM } },
9494     { "stgi",           { Skip_MODRM } },
9495     { "clgi",           { Skip_MODRM } },
9496     { "skinit",         { Skip_MODRM } },
9497     { "invlpga",        { Skip_MODRM } },
9498   },
9499   {
9500     /* RM_0F01_REG_7 */
9501     { "swapgs",         { Skip_MODRM } },
9502     { "rdtscp",         { Skip_MODRM } },
9503     { "(bad)",          { XX } },
9504     { "(bad)",          { XX } },
9505     { "(bad)",          { XX } },
9506     { "(bad)",          { XX } },
9507     { "(bad)",          { XX } },
9508     { "(bad)",          { XX } },
9509   },
9510   {
9511     /* RM_0FAE_REG_5 */
9512     { "lfence",         { Skip_MODRM } },
9513     { "(bad)",          { XX } },
9514     { "(bad)",          { XX } },
9515     { "(bad)",          { XX } },
9516     { "(bad)",          { XX } },
9517     { "(bad)",          { XX } },
9518     { "(bad)",          { XX } },
9519     { "(bad)",          { XX } },
9520   },
9521   {
9522     /* RM_0FAE_REG_6 */
9523     { "mfence",         { Skip_MODRM } },
9524     { "(bad)",          { XX } },
9525     { "(bad)",          { XX } },
9526     { "(bad)",          { XX } },
9527     { "(bad)",          { XX } },
9528     { "(bad)",          { XX } },
9529     { "(bad)",          { XX } },
9530     { "(bad)",          { XX } },
9531   },
9532   {
9533     /* RM_0FAE_REG_7 */
9534     { "sfence",         { Skip_MODRM } },
9535     { "(bad)",          { XX } },
9536     { "(bad)",          { XX } },
9537     { "(bad)",          { XX } },
9538     { "(bad)",          { XX } },
9539     { "(bad)",          { XX } },
9540     { "(bad)",          { XX } },
9541     { "(bad)",          { XX } },
9542   },
9543 };
9544
9545 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9546
9547 static void
9548 ckprefix (void)
9549 {
9550   int newrex;
9551   rex = 0;
9552   rex_original = 0;
9553   rex_ignored = 0;
9554   prefixes = 0;
9555   used_prefixes = 0;
9556   rex_used = 0;
9557   while (1)
9558     {
9559       FETCH_DATA (the_info, codep + 1);
9560       newrex = 0;
9561       switch (*codep)
9562         {
9563         /* REX prefixes family.  */
9564         case 0x40:
9565         case 0x41:
9566         case 0x42:
9567         case 0x43:
9568         case 0x44:
9569         case 0x45:
9570         case 0x46:
9571         case 0x47:
9572         case 0x48:
9573         case 0x49:
9574         case 0x4a:
9575         case 0x4b:
9576         case 0x4c:
9577         case 0x4d:
9578         case 0x4e:
9579         case 0x4f:
9580             if (address_mode == mode_64bit)
9581               newrex = *codep;
9582             else
9583               return;
9584           break;
9585         case 0xf3:
9586           prefixes |= PREFIX_REPZ;
9587           break;
9588         case 0xf2:
9589           prefixes |= PREFIX_REPNZ;
9590           break;
9591         case 0xf0:
9592           prefixes |= PREFIX_LOCK;
9593           break;
9594         case 0x2e:
9595           prefixes |= PREFIX_CS;
9596           break;
9597         case 0x36:
9598           prefixes |= PREFIX_SS;
9599           break;
9600         case 0x3e:
9601           prefixes |= PREFIX_DS;
9602           break;
9603         case 0x26:
9604           prefixes |= PREFIX_ES;
9605           break;
9606         case 0x64:
9607           prefixes |= PREFIX_FS;
9608           break;
9609         case 0x65:
9610           prefixes |= PREFIX_GS;
9611           break;
9612         case 0x66:
9613           prefixes |= PREFIX_DATA;
9614           break;
9615         case 0x67:
9616           prefixes |= PREFIX_ADDR;
9617           break;
9618         case FWAIT_OPCODE:
9619           /* fwait is really an instruction.  If there are prefixes
9620              before the fwait, they belong to the fwait, *not* to the
9621              following instruction.  */
9622           if (prefixes || rex)
9623             {
9624               prefixes |= PREFIX_FWAIT;
9625               codep++;
9626               return;
9627             }
9628           prefixes = PREFIX_FWAIT;
9629           break;
9630         default:
9631           return;
9632         }
9633       /* Rex is ignored when followed by another prefix.  */
9634       if (rex)
9635         {
9636           rex_used = rex;
9637           return;
9638         }
9639       rex = newrex;
9640       rex_original = rex;
9641       codep++;
9642     }
9643 }
9644
9645 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9646    prefix byte.  */
9647
9648 static const char *
9649 prefix_name (int pref, int sizeflag)
9650 {
9651   static const char *rexes [16] =
9652     {
9653       "rex",            /* 0x40 */
9654       "rex.B",          /* 0x41 */
9655       "rex.X",          /* 0x42 */
9656       "rex.XB",         /* 0x43 */
9657       "rex.R",          /* 0x44 */
9658       "rex.RB",         /* 0x45 */
9659       "rex.RX",         /* 0x46 */
9660       "rex.RXB",        /* 0x47 */
9661       "rex.W",          /* 0x48 */
9662       "rex.WB",         /* 0x49 */
9663       "rex.WX",         /* 0x4a */
9664       "rex.WXB",        /* 0x4b */
9665       "rex.WR",         /* 0x4c */
9666       "rex.WRB",        /* 0x4d */
9667       "rex.WRX",        /* 0x4e */
9668       "rex.WRXB",       /* 0x4f */
9669     };
9670
9671   switch (pref)
9672     {
9673     /* REX prefixes family.  */
9674     case 0x40:
9675     case 0x41:
9676     case 0x42:
9677     case 0x43:
9678     case 0x44:
9679     case 0x45:
9680     case 0x46:
9681     case 0x47:
9682     case 0x48:
9683     case 0x49:
9684     case 0x4a:
9685     case 0x4b:
9686     case 0x4c:
9687     case 0x4d:
9688     case 0x4e:
9689     case 0x4f:
9690       return rexes [pref - 0x40];
9691     case 0xf3:
9692       return "repz";
9693     case 0xf2:
9694       return "repnz";
9695     case 0xf0:
9696       return "lock";
9697     case 0x2e:
9698       return "cs";
9699     case 0x36:
9700       return "ss";
9701     case 0x3e:
9702       return "ds";
9703     case 0x26:
9704       return "es";
9705     case 0x64:
9706       return "fs";
9707     case 0x65:
9708       return "gs";
9709     case 0x66:
9710       return (sizeflag & DFLAG) ? "data16" : "data32";
9711     case 0x67:
9712       if (address_mode == mode_64bit)
9713         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9714       else
9715         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9716     case FWAIT_OPCODE:
9717       return "fwait";
9718     default:
9719       return NULL;
9720     }
9721 }
9722
9723 static char op_out[MAX_OPERANDS][100];
9724 static int op_ad, op_index[MAX_OPERANDS];
9725 static int two_source_ops;
9726 static bfd_vma op_address[MAX_OPERANDS];
9727 static bfd_vma op_riprel[MAX_OPERANDS];
9728 static bfd_vma start_pc;
9729
9730 /*
9731  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9732  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9733  *   section of the "Virtual 8086 Mode" chapter.)
9734  * 'pc' should be the address of this instruction, it will
9735  *   be used to print the target address if this is a relative jump or call
9736  * The function returns the length of this instruction in bytes.
9737  */
9738
9739 static char intel_syntax;
9740 static char intel_mnemonic = !SYSV386_COMPAT;
9741 static char open_char;
9742 static char close_char;
9743 static char separator_char;
9744 static char scale_char;
9745
9746 /* Here for backwards compatibility.  When gdb stops using
9747    print_insn_i386_att and print_insn_i386_intel these functions can
9748    disappear, and print_insn_i386 be merged into print_insn.  */
9749 int
9750 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9751 {
9752   intel_syntax = 0;
9753
9754   return print_insn (pc, info);
9755 }
9756
9757 int
9758 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9759 {
9760   intel_syntax = 1;
9761
9762   return print_insn (pc, info);
9763 }
9764
9765 int
9766 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9767 {
9768   intel_syntax = -1;
9769
9770   return print_insn (pc, info);
9771 }
9772
9773 void
9774 print_i386_disassembler_options (FILE *stream)
9775 {
9776   fprintf (stream, _("\n\
9777 The following i386/x86-64 specific disassembler options are supported for use\n\
9778 with the -M switch (multiple options should be separated by commas):\n"));
9779
9780   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9781   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9782   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9783   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9784   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9785   fprintf (stream, _("  att-mnemonic\n"
9786                      "              Display instruction in AT&T mnemonic\n"));
9787   fprintf (stream, _("  intel-mnemonic\n"
9788                      "              Display instruction in Intel mnemonic\n"));
9789   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9790   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9791   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9792   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9793   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9794   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9795 }
9796
9797 /* Get a pointer to struct dis386 with a valid name.  */
9798
9799 static const struct dis386 *
9800 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9801 {
9802   int index, vex_table_index;
9803
9804   if (dp->name != NULL)
9805     return dp;
9806
9807   switch (dp->op[0].bytemode)
9808     {
9809     case USE_REG_TABLE:
9810       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9811       break;
9812
9813     case USE_MOD_TABLE:
9814       index = modrm.mod == 0x3 ? 1 : 0;
9815       dp = &mod_table[dp->op[1].bytemode][index];
9816       break;
9817
9818     case USE_RM_TABLE:
9819       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9820       break;
9821
9822     case USE_PREFIX_TABLE:
9823       if (need_vex)
9824         {
9825           /* The prefix in VEX is implicit.  */
9826           switch (vex.prefix)
9827             {
9828             case 0:
9829               index = 0;
9830               break;
9831             case REPE_PREFIX_OPCODE:
9832               index = 1;
9833               break;
9834             case DATA_PREFIX_OPCODE:
9835               index = 2;
9836               break;
9837             case REPNE_PREFIX_OPCODE:
9838               index = 3;
9839               break;
9840             default:
9841               abort ();
9842               break;
9843             }
9844         }
9845       else
9846         {
9847           index = 0;
9848           used_prefixes |= (prefixes & PREFIX_REPZ);
9849           if (prefixes & PREFIX_REPZ)
9850             {
9851               index = 1;
9852               repz_prefix = NULL;
9853             }
9854           else
9855             {
9856               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9857                  PREFIX_DATA.  */
9858               used_prefixes |= (prefixes & PREFIX_REPNZ);
9859               if (prefixes & PREFIX_REPNZ)
9860                 {
9861                   index = 3;
9862                   repnz_prefix = NULL;
9863                 }
9864               else
9865                 {
9866                   used_prefixes |= (prefixes & PREFIX_DATA);
9867                   if (prefixes & PREFIX_DATA)
9868                     {
9869                       index = 2;
9870                       data_prefix = NULL;
9871                     }
9872                 }
9873             }
9874         }
9875       dp = &prefix_table[dp->op[1].bytemode][index];
9876       break;
9877
9878     case USE_X86_64_TABLE:
9879       index = address_mode == mode_64bit ? 1 : 0;
9880       dp = &x86_64_table[dp->op[1].bytemode][index];
9881       break;
9882
9883     case USE_3BYTE_TABLE:
9884       FETCH_DATA (info, codep + 2);
9885       index = *codep++;
9886       dp = &three_byte_table[dp->op[1].bytemode][index];
9887       modrm.mod = (*codep >> 6) & 3;
9888       modrm.reg = (*codep >> 3) & 7;
9889       modrm.rm = *codep & 7;
9890       break;
9891
9892     case USE_VEX_LEN_TABLE:
9893       if (!need_vex)
9894         abort ();
9895
9896       switch (vex.length)
9897         {
9898         case 128:
9899           index = 0;
9900           break;
9901         case 256:
9902           index = 1;
9903           break;
9904         default:
9905           abort ();
9906           break;
9907         }
9908
9909       dp = &vex_len_table[dp->op[1].bytemode][index];
9910       break;
9911
9912     case USE_VEX_C4_TABLE:
9913       FETCH_DATA (info, codep + 3);
9914       /* All bits in the REX prefix are ignored.  */
9915       rex_ignored = rex;
9916       rex = ~(*codep >> 5) & 0x7;
9917       switch ((*codep & 0x1f))
9918         {
9919         default:
9920           BadOp ();
9921         case 0x1:
9922           vex_table_index = 0;
9923           break;
9924         case 0x2:
9925           vex_table_index = 1;
9926           break;
9927         case 0x3:
9928           vex_table_index = 2;
9929           break;
9930         }
9931       codep++;
9932       vex.w = *codep & 0x80;
9933       if (vex.w && address_mode == mode_64bit)
9934         rex |= REX_W;
9935
9936       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9937       if (address_mode != mode_64bit
9938           && vex.register_specifier > 0x7)
9939         BadOp ();
9940
9941       vex.length = (*codep & 0x4) ? 256 : 128;
9942       switch ((*codep & 0x3))
9943         {
9944         case 0:
9945           vex.prefix = 0;
9946           break;
9947         case 1:
9948           vex.prefix = DATA_PREFIX_OPCODE;
9949           break;
9950         case 2:
9951           vex.prefix = REPE_PREFIX_OPCODE;
9952           break;
9953         case 3:
9954           vex.prefix = REPNE_PREFIX_OPCODE;
9955           break;
9956         }
9957       need_vex = 1;
9958       need_vex_reg = 1;
9959       codep++;
9960       index = *codep++;
9961       dp = &vex_table[vex_table_index][index];
9962       /* There is no MODRM byte for VEX [82|77].  */
9963       if (index != 0x77 && index != 0x82)
9964         {
9965           FETCH_DATA (info, codep + 1);
9966           modrm.mod = (*codep >> 6) & 3;
9967           modrm.reg = (*codep >> 3) & 7;
9968           modrm.rm = *codep & 7;
9969         }
9970       break;
9971
9972     case USE_VEX_C5_TABLE:
9973       FETCH_DATA (info, codep + 2);
9974       /* All bits in the REX prefix are ignored.  */
9975       rex_ignored = rex;
9976       rex = (*codep & 0x80) ? 0 : REX_R;
9977
9978       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9979       if (address_mode != mode_64bit
9980           && vex.register_specifier > 0x7)
9981         BadOp ();
9982
9983       vex.length = (*codep & 0x4) ? 256 : 128;
9984       switch ((*codep & 0x3))
9985         {
9986         case 0:
9987           vex.prefix = 0;
9988           break;
9989         case 1:
9990           vex.prefix = DATA_PREFIX_OPCODE;
9991           break;
9992         case 2:
9993           vex.prefix = REPE_PREFIX_OPCODE;
9994           break;
9995         case 3:
9996           vex.prefix = REPNE_PREFIX_OPCODE;
9997           break;
9998         }
9999       need_vex = 1;
10000       need_vex_reg = 1;
10001       codep++;
10002       index = *codep++;
10003       dp = &vex_table[dp->op[1].bytemode][index];
10004       /* There is no MODRM byte for VEX [82|77].  */
10005       if (index != 0x77 && index != 0x82)
10006         {
10007           FETCH_DATA (info, codep + 1);
10008           modrm.mod = (*codep >> 6) & 3;
10009           modrm.reg = (*codep >> 3) & 7;
10010           modrm.rm = *codep & 7;
10011         }
10012       break;
10013
10014     default:
10015       oappend (INTERNAL_DISASSEMBLER_ERROR);
10016       return NULL;
10017     }
10018
10019   if (dp->name != NULL)
10020     return dp;
10021   else
10022     return get_valid_dis386 (dp, info);
10023 }
10024
10025 static int
10026 print_insn (bfd_vma pc, disassemble_info *info)
10027 {
10028   const struct dis386 *dp;
10029   int i;
10030   char *op_txt[MAX_OPERANDS];
10031   int needcomma;
10032   int sizeflag;
10033   const char *p;
10034   struct dis_private priv;
10035   unsigned char op;
10036   char prefix_obuf[32];
10037   char *prefix_obufp;
10038
10039   if (info->mach == bfd_mach_x86_64_intel_syntax
10040       || info->mach == bfd_mach_x86_64)
10041     address_mode = mode_64bit;
10042   else
10043     address_mode = mode_32bit;
10044
10045   if (intel_syntax == (char) -1)
10046     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10047                     || info->mach == bfd_mach_x86_64_intel_syntax);
10048
10049   if (info->mach == bfd_mach_i386_i386
10050       || info->mach == bfd_mach_x86_64
10051       || info->mach == bfd_mach_i386_i386_intel_syntax
10052       || info->mach == bfd_mach_x86_64_intel_syntax)
10053     priv.orig_sizeflag = AFLAG | DFLAG;
10054   else if (info->mach == bfd_mach_i386_i8086)
10055     priv.orig_sizeflag = 0;
10056   else
10057     abort ();
10058
10059   for (p = info->disassembler_options; p != NULL; )
10060     {
10061       if (CONST_STRNEQ (p, "x86-64"))
10062         {
10063           address_mode = mode_64bit;
10064           priv.orig_sizeflag = AFLAG | DFLAG;
10065         }
10066       else if (CONST_STRNEQ (p, "i386"))
10067         {
10068           address_mode = mode_32bit;
10069           priv.orig_sizeflag = AFLAG | DFLAG;
10070         }
10071       else if (CONST_STRNEQ (p, "i8086"))
10072         {
10073           address_mode = mode_16bit;
10074           priv.orig_sizeflag = 0;
10075         }
10076       else if (CONST_STRNEQ (p, "intel"))
10077         {
10078           intel_syntax = 1;
10079           if (CONST_STRNEQ (p + 5, "-mnemonic"))
10080             intel_mnemonic = 1;
10081         }
10082       else if (CONST_STRNEQ (p, "att"))
10083         {
10084           intel_syntax = 0;
10085           if (CONST_STRNEQ (p + 3, "-mnemonic"))
10086             intel_mnemonic = 0;
10087         }
10088       else if (CONST_STRNEQ (p, "addr"))
10089         {
10090           if (address_mode == mode_64bit)
10091             {
10092               if (p[4] == '3' && p[5] == '2')
10093                 priv.orig_sizeflag &= ~AFLAG;
10094               else if (p[4] == '6' && p[5] == '4')
10095                 priv.orig_sizeflag |= AFLAG;
10096             }
10097           else
10098             {
10099               if (p[4] == '1' && p[5] == '6')
10100                 priv.orig_sizeflag &= ~AFLAG;
10101               else if (p[4] == '3' && p[5] == '2')
10102                 priv.orig_sizeflag |= AFLAG;
10103             }
10104         }
10105       else if (CONST_STRNEQ (p, "data"))
10106         {
10107           if (p[4] == '1' && p[5] == '6')
10108             priv.orig_sizeflag &= ~DFLAG;
10109           else if (p[4] == '3' && p[5] == '2')
10110             priv.orig_sizeflag |= DFLAG;
10111         }
10112       else if (CONST_STRNEQ (p, "suffix"))
10113         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10114
10115       p = strchr (p, ',');
10116       if (p != NULL)
10117         p++;
10118     }
10119
10120   if (intel_syntax)
10121     {
10122       names64 = intel_names64;
10123       names32 = intel_names32;
10124       names16 = intel_names16;
10125       names8 = intel_names8;
10126       names8rex = intel_names8rex;
10127       names_seg = intel_names_seg;
10128       index64 = intel_index64;
10129       index32 = intel_index32;
10130       index16 = intel_index16;
10131       open_char = '[';
10132       close_char = ']';
10133       separator_char = '+';
10134       scale_char = '*';
10135     }
10136   else
10137     {
10138       names64 = att_names64;
10139       names32 = att_names32;
10140       names16 = att_names16;
10141       names8 = att_names8;
10142       names8rex = att_names8rex;
10143       names_seg = att_names_seg;
10144       index64 = att_index64;
10145       index32 = att_index32;
10146       index16 = att_index16;
10147       open_char = '(';
10148       close_char =  ')';
10149       separator_char = ',';
10150       scale_char = ',';
10151     }
10152
10153   /* The output looks better if we put 7 bytes on a line, since that
10154      puts most long word instructions on a single line.  */
10155   info->bytes_per_line = 7;
10156
10157   info->private_data = &priv;
10158   priv.max_fetched = priv.the_buffer;
10159   priv.insn_start = pc;
10160
10161   obuf[0] = 0;
10162   for (i = 0; i < MAX_OPERANDS; ++i)
10163     {
10164       op_out[i][0] = 0;
10165       op_index[i] = -1;
10166     }
10167
10168   the_info = info;
10169   start_pc = pc;
10170   start_codep = priv.the_buffer;
10171   codep = priv.the_buffer;
10172
10173   if (setjmp (priv.bailout) != 0)
10174     {
10175       const char *name;
10176
10177       /* Getting here means we tried for data but didn't get it.  That
10178          means we have an incomplete instruction of some sort.  Just
10179          print the first byte as a prefix or a .byte pseudo-op.  */
10180       if (codep > priv.the_buffer)
10181         {
10182           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10183           if (name != NULL)
10184             (*info->fprintf_func) (info->stream, "%s", name);
10185           else
10186             {
10187               /* Just print the first byte as a .byte instruction.  */
10188               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10189                                      (unsigned int) priv.the_buffer[0]);
10190             }
10191
10192           return 1;
10193         }
10194
10195       return -1;
10196     }
10197
10198   obufp = obuf;
10199   ckprefix ();
10200
10201   insn_codep = codep;
10202   sizeflag = priv.orig_sizeflag;
10203
10204   FETCH_DATA (info, codep + 1);
10205   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10206
10207   if (((prefixes & PREFIX_FWAIT)
10208        && ((*codep < 0xd8) || (*codep > 0xdf)))
10209       || (rex && rex_used))
10210     {
10211       const char *name;
10212
10213       /* fwait not followed by floating point instruction, or rex followed
10214          by other prefixes.  Print the first prefix.  */
10215       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10216       if (name == NULL)
10217         name = INTERNAL_DISASSEMBLER_ERROR;
10218       (*info->fprintf_func) (info->stream, "%s", name);
10219       return 1;
10220     }
10221
10222   op = 0;
10223   if (*codep == 0x0f)
10224     {
10225       unsigned char threebyte;
10226       FETCH_DATA (info, codep + 2);
10227       threebyte = *++codep;
10228       dp = &dis386_twobyte[threebyte];
10229       need_modrm = twobyte_has_modrm[*codep];
10230       codep++;
10231     }
10232   else
10233     {
10234       dp = &dis386[*codep];
10235       need_modrm = onebyte_has_modrm[*codep];
10236       codep++;
10237     }
10238
10239   if ((prefixes & PREFIX_REPZ))
10240     {
10241       repz_prefix = "repz ";
10242       used_prefixes |= PREFIX_REPZ;
10243     }
10244   else
10245     repz_prefix = NULL;
10246
10247   if ((prefixes & PREFIX_REPNZ))
10248     {
10249       repnz_prefix = "repnz ";
10250       used_prefixes |= PREFIX_REPNZ;
10251     }
10252   else
10253     repnz_prefix = NULL;
10254
10255   if ((prefixes & PREFIX_LOCK))
10256     {
10257       lock_prefix = "lock ";
10258       used_prefixes |= PREFIX_LOCK;
10259     }
10260   else
10261     lock_prefix = NULL;
10262
10263   addr_prefix = NULL;
10264   if (prefixes & PREFIX_ADDR)
10265     {
10266       sizeflag ^= AFLAG;
10267       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10268         {
10269           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10270             addr_prefix = "addr32 ";
10271           else
10272             addr_prefix = "addr16 ";
10273           used_prefixes |= PREFIX_ADDR;
10274         }
10275     }
10276
10277   data_prefix = NULL;
10278   if ((prefixes & PREFIX_DATA))
10279     {
10280       sizeflag ^= DFLAG;
10281       if (dp->op[2].bytemode == cond_jump_mode
10282           && dp->op[0].bytemode == v_mode
10283           && !intel_syntax)
10284         {
10285           if (sizeflag & DFLAG)
10286             data_prefix = "data32 ";
10287           else
10288             data_prefix = "data16 ";
10289           used_prefixes |= PREFIX_DATA;
10290         }
10291     }
10292
10293   if (need_modrm)
10294     {
10295       FETCH_DATA (info, codep + 1);
10296       modrm.mod = (*codep >> 6) & 3;
10297       modrm.reg = (*codep >> 3) & 7;
10298       modrm.rm = *codep & 7;
10299     }
10300
10301   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10302     {
10303       dofloat (sizeflag);
10304     }
10305   else
10306     {
10307       need_vex = 0;
10308       need_vex_reg = 0;
10309       vex_w_done = 0;
10310       dp = get_valid_dis386 (dp, info);
10311       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10312         {
10313           for (i = 0; i < MAX_OPERANDS; ++i)
10314             {
10315               obufp = op_out[i];
10316               op_ad = MAX_OPERANDS - 1 - i;
10317               if (dp->op[i].rtn)
10318                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10319             }
10320         }
10321     }
10322
10323   /* See if any prefixes were not used.  If so, print the first one
10324      separately.  If we don't do this, we'll wind up printing an
10325      instruction stream which does not precisely correspond to the
10326      bytes we are disassembling.  */
10327   if ((prefixes & ~used_prefixes) != 0)
10328     {
10329       const char *name;
10330
10331       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10332       if (name == NULL)
10333         name = INTERNAL_DISASSEMBLER_ERROR;
10334       (*info->fprintf_func) (info->stream, "%s", name);
10335       return 1;
10336     }
10337   if ((rex_original & ~rex_used) || rex_ignored)
10338     {
10339       const char *name;
10340       name = prefix_name (rex_original, priv.orig_sizeflag);
10341       if (name == NULL)
10342         name = INTERNAL_DISASSEMBLER_ERROR;
10343       (*info->fprintf_func) (info->stream, "%s ", name);
10344     }
10345
10346   prefix_obuf[0] = 0;
10347   prefix_obufp = prefix_obuf;
10348   if (lock_prefix)
10349     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10350   if (repz_prefix)
10351     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10352   if (repnz_prefix)
10353     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10354   if (addr_prefix)
10355     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10356   if (data_prefix)
10357     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10358
10359   if (prefix_obuf[0] != 0)
10360     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10361
10362   obufp = obuf + strlen (obuf);
10363   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10364     oappend (" ");
10365   oappend (" ");
10366   (*info->fprintf_func) (info->stream, "%s", obuf);
10367
10368   /* The enter and bound instructions are printed with operands in the same
10369      order as the intel book; everything else is printed in reverse order.  */
10370   if (intel_syntax || two_source_ops)
10371     {
10372       bfd_vma riprel;
10373
10374       for (i = 0; i < MAX_OPERANDS; ++i)
10375         op_txt[i] = op_out[i];
10376
10377       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10378         {
10379           op_ad = op_index[i];
10380           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10381           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10382           riprel = op_riprel[i];
10383           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10384           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10385         }
10386     }
10387   else
10388     {
10389       for (i = 0; i < MAX_OPERANDS; ++i)
10390         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10391     }
10392
10393   needcomma = 0;
10394   for (i = 0; i < MAX_OPERANDS; ++i)
10395     if (*op_txt[i])
10396       {
10397         if (needcomma)
10398           (*info->fprintf_func) (info->stream, ",");
10399         if (op_index[i] != -1 && !op_riprel[i])
10400           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10401         else
10402           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10403         needcomma = 1;
10404       }
10405
10406   for (i = 0; i < MAX_OPERANDS; i++)
10407     if (op_index[i] != -1 && op_riprel[i])
10408       {
10409         (*info->fprintf_func) (info->stream, "        # ");
10410         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10411                                                 + op_address[op_index[i]]), info);
10412         break;
10413       }
10414   return codep - priv.the_buffer;
10415 }
10416
10417 static const char *float_mem[] = {
10418   /* d8 */
10419   "fadd{s|}",
10420   "fmul{s|}",
10421   "fcom{s|}",
10422   "fcomp{s|}",
10423   "fsub{s|}",
10424   "fsubr{s|}",
10425   "fdiv{s|}",
10426   "fdivr{s|}",
10427   /* d9 */
10428   "fld{s|}",
10429   "(bad)",
10430   "fst{s|}",
10431   "fstp{s|}",
10432   "fldenvIC",
10433   "fldcw",
10434   "fNstenvIC",
10435   "fNstcw",
10436   /* da */
10437   "fiadd{l|}",
10438   "fimul{l|}",
10439   "ficom{l|}",
10440   "ficomp{l|}",
10441   "fisub{l|}",
10442   "fisubr{l|}",
10443   "fidiv{l|}",
10444   "fidivr{l|}",
10445   /* db */
10446   "fild{l|}",
10447   "fisttp{l|}",
10448   "fist{l|}",
10449   "fistp{l|}",
10450   "(bad)",
10451   "fld{t||t|}",
10452   "(bad)",
10453   "fstp{t||t|}",
10454   /* dc */
10455   "fadd{l|}",
10456   "fmul{l|}",
10457   "fcom{l|}",
10458   "fcomp{l|}",
10459   "fsub{l|}",
10460   "fsubr{l|}",
10461   "fdiv{l|}",
10462   "fdivr{l|}",
10463   /* dd */
10464   "fld{l|}",
10465   "fisttp{ll|}",
10466   "fst{l||}",
10467   "fstp{l|}",
10468   "frstorIC",
10469   "(bad)",
10470   "fNsaveIC",
10471   "fNstsw",
10472   /* de */
10473   "fiadd",
10474   "fimul",
10475   "ficom",
10476   "ficomp",
10477   "fisub",
10478   "fisubr",
10479   "fidiv",
10480   "fidivr",
10481   /* df */
10482   "fild",
10483   "fisttp",
10484   "fist",
10485   "fistp",
10486   "fbld",
10487   "fild{ll|}",
10488   "fbstp",
10489   "fistp{ll|}",
10490 };
10491
10492 static const unsigned char float_mem_mode[] = {
10493   /* d8 */
10494   d_mode,
10495   d_mode,
10496   d_mode,
10497   d_mode,
10498   d_mode,
10499   d_mode,
10500   d_mode,
10501   d_mode,
10502   /* d9 */
10503   d_mode,
10504   0,
10505   d_mode,
10506   d_mode,
10507   0,
10508   w_mode,
10509   0,
10510   w_mode,
10511   /* da */
10512   d_mode,
10513   d_mode,
10514   d_mode,
10515   d_mode,
10516   d_mode,
10517   d_mode,
10518   d_mode,
10519   d_mode,
10520   /* db */
10521   d_mode,
10522   d_mode,
10523   d_mode,
10524   d_mode,
10525   0,
10526   t_mode,
10527   0,
10528   t_mode,
10529   /* dc */
10530   q_mode,
10531   q_mode,
10532   q_mode,
10533   q_mode,
10534   q_mode,
10535   q_mode,
10536   q_mode,
10537   q_mode,
10538   /* dd */
10539   q_mode,
10540   q_mode,
10541   q_mode,
10542   q_mode,
10543   0,
10544   0,
10545   0,
10546   w_mode,
10547   /* de */
10548   w_mode,
10549   w_mode,
10550   w_mode,
10551   w_mode,
10552   w_mode,
10553   w_mode,
10554   w_mode,
10555   w_mode,
10556   /* df */
10557   w_mode,
10558   w_mode,
10559   w_mode,
10560   w_mode,
10561   t_mode,
10562   q_mode,
10563   t_mode,
10564   q_mode
10565 };
10566
10567 #define ST { OP_ST, 0 }
10568 #define STi { OP_STi, 0 }
10569
10570 #define FGRPd9_2 NULL, { { NULL, 0 } }
10571 #define FGRPd9_4 NULL, { { NULL, 1 } }
10572 #define FGRPd9_5 NULL, { { NULL, 2 } }
10573 #define FGRPd9_6 NULL, { { NULL, 3 } }
10574 #define FGRPd9_7 NULL, { { NULL, 4 } }
10575 #define FGRPda_5 NULL, { { NULL, 5 } }
10576 #define FGRPdb_4 NULL, { { NULL, 6 } }
10577 #define FGRPde_3 NULL, { { NULL, 7 } }
10578 #define FGRPdf_4 NULL, { { NULL, 8 } }
10579
10580 static const struct dis386 float_reg[][8] = {
10581   /* d8 */
10582   {
10583     { "fadd",   { ST, STi } },
10584     { "fmul",   { ST, STi } },
10585     { "fcom",   { STi } },
10586     { "fcomp",  { STi } },
10587     { "fsub",   { ST, STi } },
10588     { "fsubr",  { ST, STi } },
10589     { "fdiv",   { ST, STi } },
10590     { "fdivr",  { ST, STi } },
10591   },
10592   /* d9 */
10593   {
10594     { "fld",    { STi } },
10595     { "fxch",   { STi } },
10596     { FGRPd9_2 },
10597     { "(bad)",  { XX } },
10598     { FGRPd9_4 },
10599     { FGRPd9_5 },
10600     { FGRPd9_6 },
10601     { FGRPd9_7 },
10602   },
10603   /* da */
10604   {
10605     { "fcmovb", { ST, STi } },
10606     { "fcmove", { ST, STi } },
10607     { "fcmovbe",{ ST, STi } },
10608     { "fcmovu", { ST, STi } },
10609     { "(bad)",  { XX } },
10610     { FGRPda_5 },
10611     { "(bad)",  { XX } },
10612     { "(bad)",  { XX } },
10613   },
10614   /* db */
10615   {
10616     { "fcmovnb",{ ST, STi } },
10617     { "fcmovne",{ ST, STi } },
10618     { "fcmovnbe",{ ST, STi } },
10619     { "fcmovnu",{ ST, STi } },
10620     { FGRPdb_4 },
10621     { "fucomi", { ST, STi } },
10622     { "fcomi",  { ST, STi } },
10623     { "(bad)",  { XX } },
10624   },
10625   /* dc */
10626   {
10627     { "fadd",   { STi, ST } },
10628     { "fmul",   { STi, ST } },
10629     { "(bad)",  { XX } },
10630     { "(bad)",  { XX } },
10631     { "fsub!M", { STi, ST } },
10632     { "fsubM",  { STi, ST } },
10633     { "fdiv!M", { STi, ST } },
10634     { "fdivM",  { STi, ST } },
10635   },
10636   /* dd */
10637   {
10638     { "ffree",  { STi } },
10639     { "(bad)",  { XX } },
10640     { "fst",    { STi } },
10641     { "fstp",   { STi } },
10642     { "fucom",  { STi } },
10643     { "fucomp", { STi } },
10644     { "(bad)",  { XX } },
10645     { "(bad)",  { XX } },
10646   },
10647   /* de */
10648   {
10649     { "faddp",  { STi, ST } },
10650     { "fmulp",  { STi, ST } },
10651     { "(bad)",  { XX } },
10652     { FGRPde_3 },
10653     { "fsub!Mp", { STi, ST } },
10654     { "fsubMp", { STi, ST } },
10655     { "fdiv!Mp", { STi, ST } },
10656     { "fdivMp", { STi, ST } },
10657   },
10658   /* df */
10659   {
10660     { "ffreep", { STi } },
10661     { "(bad)",  { XX } },
10662     { "(bad)",  { XX } },
10663     { "(bad)",  { XX } },
10664     { FGRPdf_4 },
10665     { "fucomip", { ST, STi } },
10666     { "fcomip", { ST, STi } },
10667     { "(bad)",  { XX } },
10668   },
10669 };
10670
10671 static char *fgrps[][8] = {
10672   /* d9_2  0 */
10673   {
10674     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10675   },
10676
10677   /* d9_4  1 */
10678   {
10679     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10680   },
10681
10682   /* d9_5  2 */
10683   {
10684     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10685   },
10686
10687   /* d9_6  3 */
10688   {
10689     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10690   },
10691
10692   /* d9_7  4 */
10693   {
10694     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10695   },
10696
10697   /* da_5  5 */
10698   {
10699     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10700   },
10701
10702   /* db_4  6 */
10703   {
10704     "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10705     "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10706   },
10707
10708   /* de_3  7 */
10709   {
10710     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10711   },
10712
10713   /* df_4  8 */
10714   {
10715     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10716   },
10717 };
10718
10719 static void
10720 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10721                int sizeflag ATTRIBUTE_UNUSED)
10722 {
10723   /* Skip mod/rm byte.  */
10724   MODRM_CHECK;
10725   codep++;
10726 }
10727
10728 static void
10729 dofloat (int sizeflag)
10730 {
10731   const struct dis386 *dp;
10732   unsigned char floatop;
10733
10734   floatop = codep[-1];
10735
10736   if (modrm.mod != 3)
10737     {
10738       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10739
10740       putop (float_mem[fp_indx], sizeflag);
10741       obufp = op_out[0];
10742       op_ad = 2;
10743       OP_E (float_mem_mode[fp_indx], sizeflag);
10744       return;
10745     }
10746   /* Skip mod/rm byte.  */
10747   MODRM_CHECK;
10748   codep++;
10749
10750   dp = &float_reg[floatop - 0xd8][modrm.reg];
10751   if (dp->name == NULL)
10752     {
10753       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10754
10755       /* Instruction fnstsw is only one with strange arg.  */
10756       if (floatop == 0xdf && codep[-1] == 0xe0)
10757         strcpy (op_out[0], names16[0]);
10758     }
10759   else
10760     {
10761       putop (dp->name, sizeflag);
10762
10763       obufp = op_out[0];
10764       op_ad = 2;
10765       if (dp->op[0].rtn)
10766         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10767
10768       obufp = op_out[1];
10769       op_ad = 1;
10770       if (dp->op[1].rtn)
10771         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10772     }
10773 }
10774
10775 static void
10776 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10777 {
10778   oappend ("%st" + intel_syntax);
10779 }
10780
10781 static void
10782 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10783 {
10784   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10785   oappend (scratchbuf + intel_syntax);
10786 }
10787
10788 /* Capital letters in template are macros.  */
10789 static int
10790 putop (const char *template, int sizeflag)
10791 {
10792   const char *p;
10793   int alt = 0;
10794   int cond = 1;
10795   unsigned int l = 0, len = 1;
10796   char last[4];
10797
10798 #define SAVE_LAST(c)                    \
10799   if (l < len && l < sizeof (last))     \
10800     last[l++] = c;                      \
10801   else                                  \
10802     abort ();
10803
10804   for (p = template; *p; p++)
10805     {
10806       switch (*p)
10807         {
10808         default:
10809           *obufp++ = *p;
10810           break;
10811         case '%':
10812           len++;
10813           break;
10814         case '!':
10815           cond = 0;
10816           break;
10817         case '{':
10818           alt = 0;
10819           if (intel_syntax)
10820             {
10821               while (*++p != '|')
10822                 if (*p == '}' || *p == '\0')
10823                   abort ();
10824             }
10825           /* Fall through.  */
10826         case 'I':
10827           alt = 1;
10828           continue;
10829         case '|':
10830           while (*++p != '}')
10831             {
10832               if (*p == '\0')
10833                 abort ();
10834             }
10835           break;
10836         case '}':
10837           break;
10838         case 'A':
10839           if (intel_syntax)
10840             break;
10841           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10842             *obufp++ = 'b';
10843           break;
10844         case 'B':
10845           if (intel_syntax)
10846             break;
10847           if (sizeflag & SUFFIX_ALWAYS)
10848             *obufp++ = 'b';
10849           break;
10850         case 'C':
10851           if (intel_syntax && !alt)
10852             break;
10853           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10854             {
10855               if (sizeflag & DFLAG)
10856                 *obufp++ = intel_syntax ? 'd' : 'l';
10857               else
10858                 *obufp++ = intel_syntax ? 'w' : 's';
10859               used_prefixes |= (prefixes & PREFIX_DATA);
10860             }
10861           break;
10862         case 'D':
10863           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10864             break;
10865           USED_REX (REX_W);
10866           if (modrm.mod == 3)
10867             {
10868               if (rex & REX_W)
10869                 *obufp++ = 'q';
10870               else if (sizeflag & DFLAG)
10871                 *obufp++ = intel_syntax ? 'd' : 'l';
10872               else
10873                 *obufp++ = 'w';
10874               used_prefixes |= (prefixes & PREFIX_DATA);
10875             }
10876           else
10877             *obufp++ = 'w';
10878           break;
10879         case 'E':               /* For jcxz/jecxz */
10880           if (address_mode == mode_64bit)
10881             {
10882               if (sizeflag & AFLAG)
10883                 *obufp++ = 'r';
10884               else
10885                 *obufp++ = 'e';
10886             }
10887           else
10888             if (sizeflag & AFLAG)
10889               *obufp++ = 'e';
10890           used_prefixes |= (prefixes & PREFIX_ADDR);
10891           break;
10892         case 'F':
10893           if (intel_syntax)
10894             break;
10895           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10896             {
10897               if (sizeflag & AFLAG)
10898                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10899               else
10900                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10901               used_prefixes |= (prefixes & PREFIX_ADDR);
10902             }
10903           break;
10904         case 'G':
10905           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10906             break;
10907           if ((rex & REX_W) || (sizeflag & DFLAG))
10908             *obufp++ = 'l';
10909           else
10910             *obufp++ = 'w';
10911           if (!(rex & REX_W))
10912             used_prefixes |= (prefixes & PREFIX_DATA);
10913           break;
10914         case 'H':
10915           if (intel_syntax)
10916             break;
10917           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10918               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10919             {
10920               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10921               *obufp++ = ',';
10922               *obufp++ = 'p';
10923               if (prefixes & PREFIX_DS)
10924                 *obufp++ = 't';
10925               else
10926                 *obufp++ = 'n';
10927             }
10928           break;
10929         case 'J':
10930           if (intel_syntax)
10931             break;
10932           *obufp++ = 'l';
10933           break;
10934         case 'K':
10935           USED_REX (REX_W);
10936           if (rex & REX_W)
10937             *obufp++ = 'q';
10938           else
10939             *obufp++ = 'd';
10940           break;
10941         case 'Z':
10942           if (intel_syntax)
10943             break;
10944           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10945             {
10946               *obufp++ = 'q';
10947               break;
10948             }
10949           /* Fall through.  */
10950           goto case_L;
10951         case 'L':
10952           if (l != 0 || len != 1)
10953             {
10954               SAVE_LAST (*p);
10955               break;
10956             }
10957 case_L:
10958           if (intel_syntax)
10959             break;
10960           if (sizeflag & SUFFIX_ALWAYS)
10961             *obufp++ = 'l';
10962           break;
10963         case 'M':
10964           if (intel_mnemonic != cond)
10965             *obufp++ = 'r';
10966           break;
10967         case 'N':
10968           if ((prefixes & PREFIX_FWAIT) == 0)
10969             *obufp++ = 'n';
10970           else
10971             used_prefixes |= PREFIX_FWAIT;
10972           break;
10973         case 'O':
10974           USED_REX (REX_W);
10975           if (rex & REX_W)
10976             *obufp++ = 'o';
10977           else if (intel_syntax && (sizeflag & DFLAG))
10978             *obufp++ = 'q';
10979           else
10980             *obufp++ = 'd';
10981           if (!(rex & REX_W))
10982             used_prefixes |= (prefixes & PREFIX_DATA);
10983           break;
10984         case 'T':
10985           if (intel_syntax)
10986             break;
10987           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10988             {
10989               *obufp++ = 'q';
10990               break;
10991             }
10992           /* Fall through.  */
10993         case 'P':
10994           if (intel_syntax)
10995             break;
10996           if ((prefixes & PREFIX_DATA)
10997               || (rex & REX_W)
10998               || (sizeflag & SUFFIX_ALWAYS))
10999             {
11000               USED_REX (REX_W);
11001               if (rex & REX_W)
11002                 *obufp++ = 'q';
11003               else
11004                 {
11005                    if (sizeflag & DFLAG)
11006                       *obufp++ = 'l';
11007                    else
11008                      *obufp++ = 'w';
11009                 }
11010               used_prefixes |= (prefixes & PREFIX_DATA);
11011             }
11012           break;
11013         case 'U':
11014           if (intel_syntax)
11015             break;
11016           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11017             {
11018               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11019                 *obufp++ = 'q';
11020               break;
11021             }
11022           /* Fall through.  */
11023           goto case_Q;
11024         case 'Q':
11025           if (l == 0 && len == 1)
11026             {
11027 case_Q:
11028               if (intel_syntax && !alt)
11029                 break;
11030               USED_REX (REX_W);
11031               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11032                 {
11033                   if (rex & REX_W)
11034                     *obufp++ = 'q';
11035                   else
11036                     {
11037                       if (sizeflag & DFLAG)
11038                         *obufp++ = intel_syntax ? 'd' : 'l';
11039                       else
11040                         *obufp++ = 'w';
11041                     }
11042                   used_prefixes |= (prefixes & PREFIX_DATA);
11043                 }
11044             }
11045           else
11046             {
11047               if (l != 1 || len != 2 || last[0] != 'L')
11048                 {
11049                   SAVE_LAST (*p);
11050                   break;
11051                 }
11052               if (intel_syntax
11053                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11054                 break;
11055               if ((rex & REX_W))
11056                 {
11057                   USED_REX (REX_W);
11058                   *obufp++ = 'q';
11059                 }
11060               else
11061                 *obufp++ = 'l';
11062             }
11063           break;
11064         case 'R':
11065           USED_REX (REX_W);
11066           if (rex & REX_W)
11067             *obufp++ = 'q';
11068           else if (sizeflag & DFLAG)
11069             {
11070               if (intel_syntax)
11071                   *obufp++ = 'd';
11072               else
11073                   *obufp++ = 'l';
11074             }
11075           else
11076             *obufp++ = 'w';
11077           if (intel_syntax && !p[1]
11078               && ((rex & REX_W) || (sizeflag & DFLAG)))
11079             *obufp++ = 'e';
11080           if (!(rex & REX_W))
11081             used_prefixes |= (prefixes & PREFIX_DATA);
11082           break;
11083         case 'V':
11084           if (intel_syntax)
11085             break;
11086           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11087             {
11088               if (sizeflag & SUFFIX_ALWAYS)
11089                 *obufp++ = 'q';
11090               break;
11091             }
11092           /* Fall through.  */
11093         case 'S':
11094           if (intel_syntax)
11095             break;
11096           if (sizeflag & SUFFIX_ALWAYS)
11097             {
11098               if (rex & REX_W)
11099                 *obufp++ = 'q';
11100               else
11101                 {
11102                   if (sizeflag & DFLAG)
11103                     *obufp++ = 'l';
11104                   else
11105                     *obufp++ = 'w';
11106                   used_prefixes |= (prefixes & PREFIX_DATA);
11107                 }
11108             }
11109           break;
11110         case 'X':
11111           if (l != 0 || len != 1)
11112             {
11113               SAVE_LAST (*p);
11114               break;
11115             }
11116           if (need_vex && vex.prefix)
11117             {
11118               if (vex.prefix == DATA_PREFIX_OPCODE)
11119                 *obufp++ = 'd';
11120               else
11121                 *obufp++ = 's';
11122             }
11123           else if (prefixes & PREFIX_DATA)
11124             *obufp++ = 'd';
11125           else
11126             *obufp++ = 's';
11127           used_prefixes |= (prefixes & PREFIX_DATA);
11128           break;
11129         case 'Y':
11130           if (l == 0 && len == 1)
11131             {
11132               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11133                 break;
11134               if (rex & REX_W)
11135                 {
11136                   USED_REX (REX_W);
11137                   *obufp++ = 'q';
11138                 }
11139               break;
11140             }
11141           else
11142             {
11143               if (l != 1 || len != 2 || last[0] != 'X')
11144                 {
11145                   SAVE_LAST (*p);
11146                   break;
11147                 }
11148               if (!need_vex)
11149                 abort ();
11150               if (intel_syntax
11151                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11152                 break;
11153               switch (vex.length)
11154                 {
11155                 case 128:
11156                   *obufp++ = 'x';
11157                   break;
11158                 case 256:
11159                   *obufp++ = 'y';
11160                   break;
11161                 default:
11162                   abort ();
11163                 }
11164             }
11165           break;
11166           /* implicit operand size 'l' for i386 or 'q' for x86-64 */
11167         case 'W':
11168           /* operand size flag for cwtl, cbtw */
11169           USED_REX (REX_W);
11170           if (rex & REX_W)
11171             {
11172               if (intel_syntax)
11173                 *obufp++ = 'd';
11174               else
11175                 *obufp++ = 'l';
11176             }
11177           else if (sizeflag & DFLAG)
11178             *obufp++ = 'w';
11179           else
11180             *obufp++ = 'b';
11181           if (!(rex & REX_W))
11182             used_prefixes |= (prefixes & PREFIX_DATA);
11183           break;
11184         }
11185       alt = 0;
11186     }
11187   *obufp = 0;
11188   return 0;
11189 }
11190
11191 static void
11192 oappend (const char *s)
11193 {
11194   strcpy (obufp, s);
11195   obufp += strlen (s);
11196 }
11197
11198 static void
11199 append_seg (void)
11200 {
11201   if (prefixes & PREFIX_CS)
11202     {
11203       used_prefixes |= PREFIX_CS;
11204       oappend ("%cs:" + intel_syntax);
11205     }
11206   if (prefixes & PREFIX_DS)
11207     {
11208       used_prefixes |= PREFIX_DS;
11209       oappend ("%ds:" + intel_syntax);
11210     }
11211   if (prefixes & PREFIX_SS)
11212     {
11213       used_prefixes |= PREFIX_SS;
11214       oappend ("%ss:" + intel_syntax);
11215     }
11216   if (prefixes & PREFIX_ES)
11217     {
11218       used_prefixes |= PREFIX_ES;
11219       oappend ("%es:" + intel_syntax);
11220     }
11221   if (prefixes & PREFIX_FS)
11222     {
11223       used_prefixes |= PREFIX_FS;
11224       oappend ("%fs:" + intel_syntax);
11225     }
11226   if (prefixes & PREFIX_GS)
11227     {
11228       used_prefixes |= PREFIX_GS;
11229       oappend ("%gs:" + intel_syntax);
11230     }
11231 }
11232
11233 static void
11234 OP_indirE (int bytemode, int sizeflag)
11235 {
11236   if (!intel_syntax)
11237     oappend ("*");
11238   OP_E (bytemode, sizeflag);
11239 }
11240
11241 static void
11242 print_operand_value (char *buf, int hex, bfd_vma disp)
11243 {
11244   if (address_mode == mode_64bit)
11245     {
11246       if (hex)
11247         {
11248           char tmp[30];
11249           int i;
11250           buf[0] = '0';
11251           buf[1] = 'x';
11252           sprintf_vma (tmp, disp);
11253           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11254           strcpy (buf + 2, tmp + i);
11255         }
11256       else
11257         {
11258           bfd_signed_vma v = disp;
11259           char tmp[30];
11260           int i;
11261           if (v < 0)
11262             {
11263               *(buf++) = '-';
11264               v = -disp;
11265               /* Check for possible overflow on 0x8000000000000000.  */
11266               if (v < 0)
11267                 {
11268                   strcpy (buf, "9223372036854775808");
11269                   return;
11270                 }
11271             }
11272           if (!v)
11273             {
11274               strcpy (buf, "0");
11275               return;
11276             }
11277
11278           i = 0;
11279           tmp[29] = 0;
11280           while (v)
11281             {
11282               tmp[28 - i] = (v % 10) + '0';
11283               v /= 10;
11284               i++;
11285             }
11286           strcpy (buf, tmp + 29 - i);
11287         }
11288     }
11289   else
11290     {
11291       if (hex)
11292         sprintf (buf, "0x%x", (unsigned int) disp);
11293       else
11294         sprintf (buf, "%d", (int) disp);
11295     }
11296 }
11297
11298 /* Put DISP in BUF as signed hex number.  */
11299
11300 static void
11301 print_displacement (char *buf, bfd_vma disp)
11302 {
11303   bfd_signed_vma val = disp;
11304   char tmp[30];
11305   int i, j = 0;
11306
11307   if (val < 0)
11308     {
11309       buf[j++] = '-';
11310       val = -disp;
11311
11312       /* Check for possible overflow.  */
11313       if (val < 0)
11314         {
11315           switch (address_mode)
11316             {
11317             case mode_64bit:
11318               strcpy (buf + j, "0x8000000000000000");
11319               break;
11320             case mode_32bit:
11321               strcpy (buf + j, "0x80000000");
11322               break;
11323             case mode_16bit:
11324               strcpy (buf + j, "0x8000");
11325               break;
11326             }
11327           return;
11328         }
11329     }
11330
11331   buf[j++] = '0';
11332   buf[j++] = 'x';
11333
11334   sprintf_vma (tmp, (bfd_vma) val);
11335   for (i = 0; tmp[i] == '0'; i++)
11336     continue;
11337   if (tmp[i] == '\0')
11338     i--;
11339   strcpy (buf + j, tmp + i);
11340 }
11341
11342 static void
11343 intel_operand_size (int bytemode, int sizeflag)
11344 {
11345   switch (bytemode)
11346     {
11347     case b_mode:
11348     case dqb_mode:
11349       oappend ("BYTE PTR ");
11350       break;
11351     case w_mode:
11352     case dqw_mode:
11353       oappend ("WORD PTR ");
11354       break;
11355     case stack_v_mode:
11356       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11357         {
11358           oappend ("QWORD PTR ");
11359           used_prefixes |= (prefixes & PREFIX_DATA);
11360           break;
11361         }
11362       /* FALLTHRU */
11363     case v_mode:
11364     case dq_mode:
11365       USED_REX (REX_W);
11366       if (rex & REX_W)
11367         oappend ("QWORD PTR ");
11368       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11369         oappend ("DWORD PTR ");
11370       else
11371         oappend ("WORD PTR ");
11372       used_prefixes |= (prefixes & PREFIX_DATA);
11373       break;
11374     case z_mode:
11375       if ((rex & REX_W) || (sizeflag & DFLAG))
11376         *obufp++ = 'D';
11377       oappend ("WORD PTR ");
11378       if (!(rex & REX_W))
11379         used_prefixes |= (prefixes & PREFIX_DATA);
11380       break;
11381     case a_mode:
11382       if (sizeflag & DFLAG)
11383         oappend ("QWORD PTR ");
11384       else
11385         oappend ("DWORD PTR ");
11386       used_prefixes |= (prefixes & PREFIX_DATA);
11387       break;
11388     case d_mode:
11389     case dqd_mode:
11390       oappend ("DWORD PTR ");
11391       break;
11392     case q_mode:
11393       oappend ("QWORD PTR ");
11394       break;
11395     case m_mode:
11396       if (address_mode == mode_64bit)
11397         oappend ("QWORD PTR ");
11398       else
11399         oappend ("DWORD PTR ");
11400       break;
11401     case f_mode:
11402       if (sizeflag & DFLAG)
11403         oappend ("FWORD PTR ");
11404       else
11405         oappend ("DWORD PTR ");
11406       used_prefixes |= (prefixes & PREFIX_DATA);
11407       break;
11408     case t_mode:
11409       oappend ("TBYTE PTR ");
11410       break;
11411     case x_mode:
11412       if (need_vex)
11413         {
11414           switch (vex.length)
11415             {
11416             case 128:
11417               oappend ("XMMWORD PTR ");
11418               break;
11419             case 256:
11420               oappend ("YMMWORD PTR ");
11421               break;
11422             default:
11423               abort ();
11424             }
11425         }
11426       else
11427         oappend ("XMMWORD PTR ");
11428       break;
11429     case xmm_mode:
11430       oappend ("XMMWORD PTR ");
11431       break;
11432     case xmmq_mode:
11433       if (!need_vex)
11434         abort ();
11435
11436       switch (vex.length)
11437         {
11438         case 128:
11439           oappend ("QWORD PTR ");
11440           break;
11441         case 256:
11442           oappend ("XMMWORD PTR ");
11443           break;
11444         default:
11445           abort ();
11446         }
11447       break;
11448     case ymmq_mode:
11449       if (!need_vex)
11450         abort ();
11451
11452       switch (vex.length)
11453         {
11454         case 128:
11455           oappend ("QWORD PTR ");
11456           break;
11457         case 256:
11458           oappend ("YMMWORD PTR ");
11459           break;
11460         default:
11461           abort ();
11462         }
11463       break;
11464     case o_mode:
11465       oappend ("OWORD PTR ");
11466       break;
11467     default:
11468       break;
11469     }
11470 }
11471
11472 static void
11473 OP_E_register (int bytemode, int sizeflag)
11474 {
11475   int reg = modrm.rm;
11476   const char **names;
11477
11478   USED_REX (REX_B);
11479   if ((rex & REX_B))
11480     reg += 8;
11481
11482   switch (bytemode)
11483     {
11484     case b_mode:
11485       USED_REX (0);
11486       if (rex)
11487         names = names8rex;
11488       else
11489         names = names8;
11490       break;
11491     case w_mode:
11492       names = names16;
11493       break;
11494     case d_mode:
11495       names = names32;
11496       break;
11497     case q_mode:
11498       names = names64;
11499       break;
11500     case m_mode:
11501       names = address_mode == mode_64bit ? names64 : names32;
11502       break;
11503     case stack_v_mode:
11504       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11505         {
11506           names = names64;
11507           used_prefixes |= (prefixes & PREFIX_DATA);
11508           break;
11509         }
11510       bytemode = v_mode;
11511       /* FALLTHRU */
11512     case v_mode:
11513     case dq_mode:
11514     case dqb_mode:
11515     case dqd_mode:
11516     case dqw_mode:
11517       USED_REX (REX_W);
11518       if (rex & REX_W)
11519         names = names64;
11520       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11521         names = names32;
11522       else
11523         names = names16;
11524       used_prefixes |= (prefixes & PREFIX_DATA);
11525       break;
11526     case 0:
11527       return;
11528     default:
11529       oappend (INTERNAL_DISASSEMBLER_ERROR);
11530       return;
11531     }
11532   oappend (names[reg]);
11533 }
11534
11535 static void
11536 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11537 {
11538   bfd_vma disp = 0;
11539   int add = (rex & REX_B) ? 8 : 0;
11540   int riprel = 0;
11541
11542   USED_REX (REX_B);
11543   if (intel_syntax)
11544     intel_operand_size (bytemode, sizeflag);
11545   append_seg ();
11546
11547   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11548     {
11549       /* 32/64 bit address mode */
11550       int havedisp;
11551       int havesib;
11552       int havebase;
11553       int haveindex;
11554       int needindex;
11555       int base, rbase;
11556       int index = 0;
11557       int scale = 0;
11558
11559       havesib = 0;
11560       havebase = 1;
11561       haveindex = 0;
11562       base = modrm.rm;
11563
11564       if (base == 4)
11565         {
11566           havesib = 1;
11567           FETCH_DATA (the_info, codep + 1);
11568           index = (*codep >> 3) & 7;
11569           scale = (*codep >> 6) & 3;
11570           base = *codep & 7;
11571           USED_REX (REX_X);
11572           if (rex & REX_X)
11573             index += 8;
11574           haveindex = index != 4;
11575           codep++;
11576         }
11577       rbase = base + add;
11578
11579       /* If we have a DREX byte, skip it now
11580          (it has already been handled) */
11581       if (has_drex)
11582         {
11583           FETCH_DATA (the_info, codep + 1);
11584           codep++;
11585         }
11586
11587       switch (modrm.mod)
11588         {
11589         case 0:
11590           if (base == 5)
11591             {
11592               havebase = 0;
11593               if (address_mode == mode_64bit && !havesib)
11594                 riprel = 1;
11595               disp = get32s ();
11596             }
11597           break;
11598         case 1:
11599           FETCH_DATA (the_info, codep + 1);
11600           disp = *codep++;
11601           if ((disp & 0x80) != 0)
11602             disp -= 0x100;
11603           break;
11604         case 2:
11605           disp = get32s ();
11606           break;
11607         }
11608
11609       /* In 32bit mode, we need index register to tell [offset] from
11610          [eiz*1 + offset].  */
11611       needindex = (havesib
11612                    && !havebase
11613                    && !haveindex
11614                    && address_mode == mode_32bit);
11615       havedisp = (havebase
11616                   || needindex
11617                   || (havesib && (haveindex || scale != 0)));
11618
11619       if (!intel_syntax)
11620         if (modrm.mod != 0 || base == 5)
11621           {
11622             if (havedisp || riprel)
11623               print_displacement (scratchbuf, disp);
11624             else
11625               print_operand_value (scratchbuf, 1, disp);
11626             oappend (scratchbuf);
11627             if (riprel)
11628               {
11629                 set_op (disp, 1);
11630                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11631               }
11632           }
11633
11634       if (havebase || haveindex || riprel)
11635         used_prefixes |= PREFIX_ADDR;
11636
11637       if (havedisp || (intel_syntax && riprel))
11638         {
11639           *obufp++ = open_char;
11640           if (intel_syntax && riprel)
11641             {
11642               set_op (disp, 1);
11643               oappend (sizeflag & AFLAG ? "rip" : "eip");
11644             }
11645           *obufp = '\0';
11646           if (havebase)
11647             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11648                      ? names64[rbase] : names32[rbase]);
11649           if (havesib)
11650             {
11651               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11652                  print index to tell base + index from base.  */
11653               if (scale != 0
11654                   || needindex
11655                   || haveindex
11656                   || (havebase && base != ESP_REG_NUM))
11657                 {
11658                   if (!intel_syntax || havebase)
11659                     {
11660                       *obufp++ = separator_char;
11661                       *obufp = '\0';
11662                     }
11663                   if (haveindex)
11664                     oappend (address_mode == mode_64bit
11665                              && (sizeflag & AFLAG)
11666                              ? names64[index] : names32[index]);
11667                   else
11668                     oappend (address_mode == mode_64bit
11669                              && (sizeflag & AFLAG)
11670                              ? index64 : index32);
11671
11672                   *obufp++ = scale_char;
11673                   *obufp = '\0';
11674                   sprintf (scratchbuf, "%d", 1 << scale);
11675                   oappend (scratchbuf);
11676                 }
11677             }
11678           if (intel_syntax
11679               && (disp || modrm.mod != 0 || base == 5))
11680             {
11681               if (!havedisp || (bfd_signed_vma) disp >= 0)
11682                 {
11683                   *obufp++ = '+';
11684                   *obufp = '\0';
11685                 }
11686               else if (modrm.mod != 1)
11687                 {
11688                   *obufp++ = '-';
11689                   *obufp = '\0';
11690                   disp = - (bfd_signed_vma) disp;
11691                 }
11692
11693               if (havedisp)
11694                 print_displacement (scratchbuf, disp);
11695               else
11696                 print_operand_value (scratchbuf, 1, disp);
11697               oappend (scratchbuf);
11698             }
11699
11700           *obufp++ = close_char;
11701           *obufp = '\0';
11702         }
11703       else if (intel_syntax)
11704         {
11705           if (modrm.mod != 0 || base == 5)
11706             {
11707               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11708                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11709                 ;
11710               else
11711                 {
11712                   oappend (names_seg[ds_reg - es_reg]);
11713                   oappend (":");
11714                 }
11715               print_operand_value (scratchbuf, 1, disp);
11716               oappend (scratchbuf);
11717             }
11718         }
11719     }
11720   else
11721     { /* 16 bit address mode */
11722       switch (modrm.mod)
11723         {
11724         case 0:
11725           if (modrm.rm == 6)
11726             {
11727               disp = get16 ();
11728               if ((disp & 0x8000) != 0)
11729                 disp -= 0x10000;
11730             }
11731           break;
11732         case 1:
11733           FETCH_DATA (the_info, codep + 1);
11734           disp = *codep++;
11735           if ((disp & 0x80) != 0)
11736             disp -= 0x100;
11737           break;
11738         case 2:
11739           disp = get16 ();
11740           if ((disp & 0x8000) != 0)
11741             disp -= 0x10000;
11742           break;
11743         }
11744
11745       if (!intel_syntax)
11746         if (modrm.mod != 0 || modrm.rm == 6)
11747           {
11748             print_displacement (scratchbuf, disp);
11749             oappend (scratchbuf);
11750           }
11751
11752       if (modrm.mod != 0 || modrm.rm != 6)
11753         {
11754           *obufp++ = open_char;
11755           *obufp = '\0';
11756           oappend (index16[modrm.rm]);
11757           if (intel_syntax
11758               && (disp || modrm.mod != 0 || modrm.rm == 6))
11759             {
11760               if ((bfd_signed_vma) disp >= 0)
11761                 {
11762                   *obufp++ = '+';
11763                   *obufp = '\0';
11764                 }
11765               else if (modrm.mod != 1)
11766                 {
11767                   *obufp++ = '-';
11768                   *obufp = '\0';
11769                   disp = - (bfd_signed_vma) disp;
11770                 }
11771
11772               print_displacement (scratchbuf, disp);
11773               oappend (scratchbuf);
11774             }
11775
11776           *obufp++ = close_char;
11777           *obufp = '\0';
11778         }
11779       else if (intel_syntax)
11780         {
11781           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11782                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11783             ;
11784           else
11785             {
11786               oappend (names_seg[ds_reg - es_reg]);
11787               oappend (":");
11788             }
11789           print_operand_value (scratchbuf, 1, disp & 0xffff);
11790           oappend (scratchbuf);
11791         }
11792     }
11793 }
11794
11795 static void
11796 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11797 {
11798   /* Skip mod/rm byte.  */
11799   MODRM_CHECK;
11800   codep++;
11801
11802   if (modrm.mod == 3)
11803     OP_E_register (bytemode, sizeflag);
11804   else
11805     OP_E_memory (bytemode, sizeflag, has_drex);
11806 }
11807
11808 static void
11809 OP_E (int bytemode, int sizeflag)
11810 {
11811   OP_E_extended (bytemode, sizeflag, 0);
11812 }
11813
11814
11815 static void
11816 OP_G (int bytemode, int sizeflag)
11817 {
11818   int add = 0;
11819   USED_REX (REX_R);
11820   if (rex & REX_R)
11821     add += 8;
11822   switch (bytemode)
11823     {
11824     case b_mode:
11825       USED_REX (0);
11826       if (rex)
11827         oappend (names8rex[modrm.reg + add]);
11828       else
11829         oappend (names8[modrm.reg + add]);
11830       break;
11831     case w_mode:
11832       oappend (names16[modrm.reg + add]);
11833       break;
11834     case d_mode:
11835       oappend (names32[modrm.reg + add]);
11836       break;
11837     case q_mode:
11838       oappend (names64[modrm.reg + add]);
11839       break;
11840     case v_mode:
11841     case dq_mode:
11842     case dqb_mode:
11843     case dqd_mode:
11844     case dqw_mode:
11845       USED_REX (REX_W);
11846       if (rex & REX_W)
11847         oappend (names64[modrm.reg + add]);
11848       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11849         oappend (names32[modrm.reg + add]);
11850       else
11851         oappend (names16[modrm.reg + add]);
11852       used_prefixes |= (prefixes & PREFIX_DATA);
11853       break;
11854     case m_mode:
11855       if (address_mode == mode_64bit)
11856         oappend (names64[modrm.reg + add]);
11857       else
11858         oappend (names32[modrm.reg + add]);
11859       break;
11860     default:
11861       oappend (INTERNAL_DISASSEMBLER_ERROR);
11862       break;
11863     }
11864 }
11865
11866 static bfd_vma
11867 get64 (void)
11868 {
11869   bfd_vma x;
11870 #ifdef BFD64
11871   unsigned int a;
11872   unsigned int b;
11873
11874   FETCH_DATA (the_info, codep + 8);
11875   a = *codep++ & 0xff;
11876   a |= (*codep++ & 0xff) << 8;
11877   a |= (*codep++ & 0xff) << 16;
11878   a |= (*codep++ & 0xff) << 24;
11879   b = *codep++ & 0xff;
11880   b |= (*codep++ & 0xff) << 8;
11881   b |= (*codep++ & 0xff) << 16;
11882   b |= (*codep++ & 0xff) << 24;
11883   x = a + ((bfd_vma) b << 32);
11884 #else
11885   abort ();
11886   x = 0;
11887 #endif
11888   return x;
11889 }
11890
11891 static bfd_signed_vma
11892 get32 (void)
11893 {
11894   bfd_signed_vma x = 0;
11895
11896   FETCH_DATA (the_info, codep + 4);
11897   x = *codep++ & (bfd_signed_vma) 0xff;
11898   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11899   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11900   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11901   return x;
11902 }
11903
11904 static bfd_signed_vma
11905 get32s (void)
11906 {
11907   bfd_signed_vma x = 0;
11908
11909   FETCH_DATA (the_info, codep + 4);
11910   x = *codep++ & (bfd_signed_vma) 0xff;
11911   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11912   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11913   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11914
11915   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11916
11917   return x;
11918 }
11919
11920 static int
11921 get16 (void)
11922 {
11923   int x = 0;
11924
11925   FETCH_DATA (the_info, codep + 2);
11926   x = *codep++ & 0xff;
11927   x |= (*codep++ & 0xff) << 8;
11928   return x;
11929 }
11930
11931 static void
11932 set_op (bfd_vma op, int riprel)
11933 {
11934   op_index[op_ad] = op_ad;
11935   if (address_mode == mode_64bit)
11936     {
11937       op_address[op_ad] = op;
11938       op_riprel[op_ad] = riprel;
11939     }
11940   else
11941     {
11942       /* Mask to get a 32-bit address.  */
11943       op_address[op_ad] = op & 0xffffffff;
11944       op_riprel[op_ad] = riprel & 0xffffffff;
11945     }
11946 }
11947
11948 static void
11949 OP_REG (int code, int sizeflag)
11950 {
11951   const char *s;
11952   int add;
11953   USED_REX (REX_B);
11954   if (rex & REX_B)
11955     add = 8;
11956   else
11957     add = 0;
11958
11959   switch (code)
11960     {
11961     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11962     case sp_reg: case bp_reg: case si_reg: case di_reg:
11963       s = names16[code - ax_reg + add];
11964       break;
11965     case es_reg: case ss_reg: case cs_reg:
11966     case ds_reg: case fs_reg: case gs_reg:
11967       s = names_seg[code - es_reg + add];
11968       break;
11969     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11970     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11971       USED_REX (0);
11972       if (rex)
11973         s = names8rex[code - al_reg + add];
11974       else
11975         s = names8[code - al_reg];
11976       break;
11977     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11978     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11979       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11980         {
11981           s = names64[code - rAX_reg + add];
11982           break;
11983         }
11984       code += eAX_reg - rAX_reg;
11985       /* Fall through.  */
11986     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11987     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11988       USED_REX (REX_W);
11989       if (rex & REX_W)
11990         s = names64[code - eAX_reg + add];
11991       else if (sizeflag & DFLAG)
11992         s = names32[code - eAX_reg + add];
11993       else
11994         s = names16[code - eAX_reg + add];
11995       used_prefixes |= (prefixes & PREFIX_DATA);
11996       break;
11997     default:
11998       s = INTERNAL_DISASSEMBLER_ERROR;
11999       break;
12000     }
12001   oappend (s);
12002 }
12003
12004 static void
12005 OP_IMREG (int code, int sizeflag)
12006 {
12007   const char *s;
12008
12009   switch (code)
12010     {
12011     case indir_dx_reg:
12012       if (intel_syntax)
12013         s = "dx";
12014       else
12015         s = "(%dx)";
12016       break;
12017     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12018     case sp_reg: case bp_reg: case si_reg: case di_reg:
12019       s = names16[code - ax_reg];
12020       break;
12021     case es_reg: case ss_reg: case cs_reg:
12022     case ds_reg: case fs_reg: case gs_reg:
12023       s = names_seg[code - es_reg];
12024       break;
12025     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12026     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12027       USED_REX (0);
12028       if (rex)
12029         s = names8rex[code - al_reg];
12030       else
12031         s = names8[code - al_reg];
12032       break;
12033     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12034     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12035       USED_REX (REX_W);
12036       if (rex & REX_W)
12037         s = names64[code - eAX_reg];
12038       else if (sizeflag & DFLAG)
12039         s = names32[code - eAX_reg];
12040       else
12041         s = names16[code - eAX_reg];
12042       used_prefixes |= (prefixes & PREFIX_DATA);
12043       break;
12044     case z_mode_ax_reg:
12045       if ((rex & REX_W) || (sizeflag & DFLAG))
12046         s = *names32;
12047       else
12048         s = *names16;
12049       if (!(rex & REX_W))
12050         used_prefixes |= (prefixes & PREFIX_DATA);
12051       break;
12052     default:
12053       s = INTERNAL_DISASSEMBLER_ERROR;
12054       break;
12055     }
12056   oappend (s);
12057 }
12058
12059 static void
12060 OP_I (int bytemode, int sizeflag)
12061 {
12062   bfd_signed_vma op;
12063   bfd_signed_vma mask = -1;
12064
12065   switch (bytemode)
12066     {
12067     case b_mode:
12068       FETCH_DATA (the_info, codep + 1);
12069       op = *codep++;
12070       mask = 0xff;
12071       break;
12072     case q_mode:
12073       if (address_mode == mode_64bit)
12074         {
12075           op = get32s ();
12076           break;
12077         }
12078       /* Fall through.  */
12079     case v_mode:
12080       USED_REX (REX_W);
12081       if (rex & REX_W)
12082         op = get32s ();
12083       else if (sizeflag & DFLAG)
12084         {
12085           op = get32 ();
12086           mask = 0xffffffff;
12087         }
12088       else
12089         {
12090           op = get16 ();
12091           mask = 0xfffff;
12092         }
12093       used_prefixes |= (prefixes & PREFIX_DATA);
12094       break;
12095     case w_mode:
12096       mask = 0xfffff;
12097       op = get16 ();
12098       break;
12099     case const_1_mode:
12100       if (intel_syntax)
12101         oappend ("1");
12102       return;
12103     default:
12104       oappend (INTERNAL_DISASSEMBLER_ERROR);
12105       return;
12106     }
12107
12108   op &= mask;
12109   scratchbuf[0] = '$';
12110   print_operand_value (scratchbuf + 1, 1, op);
12111   oappend (scratchbuf + intel_syntax);
12112   scratchbuf[0] = '\0';
12113 }
12114
12115 static void
12116 OP_I64 (int bytemode, int sizeflag)
12117 {
12118   bfd_signed_vma op;
12119   bfd_signed_vma mask = -1;
12120
12121   if (address_mode != mode_64bit)
12122     {
12123       OP_I (bytemode, sizeflag);
12124       return;
12125     }
12126
12127   switch (bytemode)
12128     {
12129     case b_mode:
12130       FETCH_DATA (the_info, codep + 1);
12131       op = *codep++;
12132       mask = 0xff;
12133       break;
12134     case v_mode:
12135       USED_REX (REX_W);
12136       if (rex & REX_W)
12137         op = get64 ();
12138       else if (sizeflag & DFLAG)
12139         {
12140           op = get32 ();
12141           mask = 0xffffffff;
12142         }
12143       else
12144         {
12145           op = get16 ();
12146           mask = 0xfffff;
12147         }
12148       used_prefixes |= (prefixes & PREFIX_DATA);
12149       break;
12150     case w_mode:
12151       mask = 0xfffff;
12152       op = get16 ();
12153       break;
12154     default:
12155       oappend (INTERNAL_DISASSEMBLER_ERROR);
12156       return;
12157     }
12158
12159   op &= mask;
12160   scratchbuf[0] = '$';
12161   print_operand_value (scratchbuf + 1, 1, op);
12162   oappend (scratchbuf + intel_syntax);
12163   scratchbuf[0] = '\0';
12164 }
12165
12166 static void
12167 OP_sI (int bytemode, int sizeflag)
12168 {
12169   bfd_signed_vma op;
12170   bfd_signed_vma mask = -1;
12171
12172   switch (bytemode)
12173     {
12174     case b_mode:
12175       FETCH_DATA (the_info, codep + 1);
12176       op = *codep++;
12177       if ((op & 0x80) != 0)
12178         op -= 0x100;
12179       mask = 0xffffffff;
12180       break;
12181     case v_mode:
12182       USED_REX (REX_W);
12183       if (rex & REX_W)
12184         op = get32s ();
12185       else if (sizeflag & DFLAG)
12186         {
12187           op = get32s ();
12188           mask = 0xffffffff;
12189         }
12190       else
12191         {
12192           mask = 0xffffffff;
12193           op = get16 ();
12194           if ((op & 0x8000) != 0)
12195             op -= 0x10000;
12196         }
12197       used_prefixes |= (prefixes & PREFIX_DATA);
12198       break;
12199     case w_mode:
12200       op = get16 ();
12201       mask = 0xffffffff;
12202       if ((op & 0x8000) != 0)
12203         op -= 0x10000;
12204       break;
12205     default:
12206       oappend (INTERNAL_DISASSEMBLER_ERROR);
12207       return;
12208     }
12209
12210   scratchbuf[0] = '$';
12211   print_operand_value (scratchbuf + 1, 1, op);
12212   oappend (scratchbuf + intel_syntax);
12213 }
12214
12215 static void
12216 OP_J (int bytemode, int sizeflag)
12217 {
12218   bfd_vma disp;
12219   bfd_vma mask = -1;
12220   bfd_vma segment = 0;
12221
12222   switch (bytemode)
12223     {
12224     case b_mode:
12225       FETCH_DATA (the_info, codep + 1);
12226       disp = *codep++;
12227       if ((disp & 0x80) != 0)
12228         disp -= 0x100;
12229       break;
12230     case v_mode:
12231       if ((sizeflag & DFLAG) || (rex & REX_W))
12232         disp = get32s ();
12233       else
12234         {
12235           disp = get16 ();
12236           if ((disp & 0x8000) != 0)
12237             disp -= 0x10000;
12238           /* In 16bit mode, address is wrapped around at 64k within
12239              the same segment.  Otherwise, a data16 prefix on a jump
12240              instruction means that the pc is masked to 16 bits after
12241              the displacement is added!  */
12242           mask = 0xffff;
12243           if ((prefixes & PREFIX_DATA) == 0)
12244             segment = ((start_pc + codep - start_codep)
12245                        & ~((bfd_vma) 0xffff));
12246         }
12247       used_prefixes |= (prefixes & PREFIX_DATA);
12248       break;
12249     default:
12250       oappend (INTERNAL_DISASSEMBLER_ERROR);
12251       return;
12252     }
12253   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12254   set_op (disp, 0);
12255   print_operand_value (scratchbuf, 1, disp);
12256   oappend (scratchbuf);
12257 }
12258
12259 static void
12260 OP_SEG (int bytemode, int sizeflag)
12261 {
12262   if (bytemode == w_mode)
12263     oappend (names_seg[modrm.reg]);
12264   else
12265     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12266 }
12267
12268 static void
12269 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12270 {
12271   int seg, offset;
12272
12273   if (sizeflag & DFLAG)
12274     {
12275       offset = get32 ();
12276       seg = get16 ();
12277     }
12278   else
12279     {
12280       offset = get16 ();
12281       seg = get16 ();
12282     }
12283   used_prefixes |= (prefixes & PREFIX_DATA);
12284   if (intel_syntax)
12285     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12286   else
12287     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12288   oappend (scratchbuf);
12289 }
12290
12291 static void
12292 OP_OFF (int bytemode, int sizeflag)
12293 {
12294   bfd_vma off;
12295
12296   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12297     intel_operand_size (bytemode, sizeflag);
12298   append_seg ();
12299
12300   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12301     off = get32 ();
12302   else
12303     off = get16 ();
12304
12305   if (intel_syntax)
12306     {
12307       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12308                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12309         {
12310           oappend (names_seg[ds_reg - es_reg]);
12311           oappend (":");
12312         }
12313     }
12314   print_operand_value (scratchbuf, 1, off);
12315   oappend (scratchbuf);
12316 }
12317
12318 static void
12319 OP_OFF64 (int bytemode, int sizeflag)
12320 {
12321   bfd_vma off;
12322
12323   if (address_mode != mode_64bit
12324       || (prefixes & PREFIX_ADDR))
12325     {
12326       OP_OFF (bytemode, sizeflag);
12327       return;
12328     }
12329
12330   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12331     intel_operand_size (bytemode, sizeflag);
12332   append_seg ();
12333
12334   off = get64 ();
12335
12336   if (intel_syntax)
12337     {
12338       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12339                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12340         {
12341           oappend (names_seg[ds_reg - es_reg]);
12342           oappend (":");
12343         }
12344     }
12345   print_operand_value (scratchbuf, 1, off);
12346   oappend (scratchbuf);
12347 }
12348
12349 static void
12350 ptr_reg (int code, int sizeflag)
12351 {
12352   const char *s;
12353
12354   *obufp++ = open_char;
12355   used_prefixes |= (prefixes & PREFIX_ADDR);
12356   if (address_mode == mode_64bit)
12357     {
12358       if (!(sizeflag & AFLAG))
12359         s = names32[code - eAX_reg];
12360       else
12361         s = names64[code - eAX_reg];
12362     }
12363   else if (sizeflag & AFLAG)
12364     s = names32[code - eAX_reg];
12365   else
12366     s = names16[code - eAX_reg];
12367   oappend (s);
12368   *obufp++ = close_char;
12369   *obufp = 0;
12370 }
12371
12372 static void
12373 OP_ESreg (int code, int sizeflag)
12374 {
12375   if (intel_syntax)
12376     {
12377       switch (codep[-1])
12378         {
12379         case 0x6d:      /* insw/insl */
12380           intel_operand_size (z_mode, sizeflag);
12381           break;
12382         case 0xa5:      /* movsw/movsl/movsq */
12383         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12384         case 0xab:      /* stosw/stosl */
12385         case 0xaf:      /* scasw/scasl */
12386           intel_operand_size (v_mode, sizeflag);
12387           break;
12388         default:
12389           intel_operand_size (b_mode, sizeflag);
12390         }
12391     }
12392   oappend ("%es:" + intel_syntax);
12393   ptr_reg (code, sizeflag);
12394 }
12395
12396 static void
12397 OP_DSreg (int code, int sizeflag)
12398 {
12399   if (intel_syntax)
12400     {
12401       switch (codep[-1])
12402         {
12403         case 0x6f:      /* outsw/outsl */
12404           intel_operand_size (z_mode, sizeflag);
12405           break;
12406         case 0xa5:      /* movsw/movsl/movsq */
12407         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12408         case 0xad:      /* lodsw/lodsl/lodsq */
12409           intel_operand_size (v_mode, sizeflag);
12410           break;
12411         default:
12412           intel_operand_size (b_mode, sizeflag);
12413         }
12414     }
12415   if ((prefixes
12416        & (PREFIX_CS
12417           | PREFIX_DS
12418           | PREFIX_SS
12419           | PREFIX_ES
12420           | PREFIX_FS
12421           | PREFIX_GS)) == 0)
12422     prefixes |= PREFIX_DS;
12423   append_seg ();
12424   ptr_reg (code, sizeflag);
12425 }
12426
12427 static void
12428 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12429 {
12430   int add;
12431   if (rex & REX_R)
12432     {
12433       USED_REX (REX_R);
12434       add = 8;
12435     }
12436   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12437     {
12438       lock_prefix = NULL;
12439       used_prefixes |= PREFIX_LOCK;
12440       add = 8;
12441     }
12442   else
12443     add = 0;
12444   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12445   oappend (scratchbuf + intel_syntax);
12446 }
12447
12448 static void
12449 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12450 {
12451   int add;
12452   USED_REX (REX_R);
12453   if (rex & REX_R)
12454     add = 8;
12455   else
12456     add = 0;
12457   if (intel_syntax)
12458     sprintf (scratchbuf, "db%d", modrm.reg + add);
12459   else
12460     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12461   oappend (scratchbuf);
12462 }
12463
12464 static void
12465 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12466 {
12467   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12468   oappend (scratchbuf + intel_syntax);
12469 }
12470
12471 static void
12472 OP_R (int bytemode, int sizeflag)
12473 {
12474   if (modrm.mod == 3)
12475     OP_E (bytemode, sizeflag);
12476   else
12477     BadOp ();
12478 }
12479
12480 static void
12481 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12482 {
12483   used_prefixes |= (prefixes & PREFIX_DATA);
12484   if (prefixes & PREFIX_DATA)
12485     {
12486       int add;
12487       USED_REX (REX_R);
12488       if (rex & REX_R)
12489         add = 8;
12490       else
12491         add = 0;
12492       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12493     }
12494   else
12495     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12496   oappend (scratchbuf + intel_syntax);
12497 }
12498
12499 static void
12500 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12501 {
12502   int add;
12503   USED_REX (REX_R);
12504   if (rex & REX_R)
12505     add = 8;
12506   else
12507     add = 0;
12508   if (need_vex && bytemode != xmm_mode)
12509     {
12510       switch (vex.length)
12511         {
12512         case 128:
12513           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12514           break;
12515         case 256:
12516           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12517           break;
12518         default:
12519           abort ();
12520         }
12521     }
12522   else
12523     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12524   oappend (scratchbuf + intel_syntax);
12525 }
12526
12527 static void
12528 OP_EM (int bytemode, int sizeflag)
12529 {
12530   if (modrm.mod != 3)
12531     {
12532       if (intel_syntax && bytemode == v_mode)
12533         {
12534           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12535           used_prefixes |= (prefixes & PREFIX_DATA);
12536         }
12537       OP_E (bytemode, sizeflag);
12538       return;
12539     }
12540
12541   /* Skip mod/rm byte.  */
12542   MODRM_CHECK;
12543   codep++;
12544   used_prefixes |= (prefixes & PREFIX_DATA);
12545   if (prefixes & PREFIX_DATA)
12546     {
12547       int add;
12548
12549       USED_REX (REX_B);
12550       if (rex & REX_B)
12551         add = 8;
12552       else
12553         add = 0;
12554       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12555     }
12556   else
12557     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12558   oappend (scratchbuf + intel_syntax);
12559 }
12560
12561 /* cvt* are the only instructions in sse2 which have
12562    both SSE and MMX operands and also have 0x66 prefix
12563    in their opcode. 0x66 was originally used to differentiate
12564    between SSE and MMX instruction(operands). So we have to handle the
12565    cvt* separately using OP_EMC and OP_MXC */
12566 static void
12567 OP_EMC (int bytemode, int sizeflag)
12568 {
12569   if (modrm.mod != 3)
12570     {
12571       if (intel_syntax && bytemode == v_mode)
12572         {
12573           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12574           used_prefixes |= (prefixes & PREFIX_DATA);
12575         }
12576       OP_E (bytemode, sizeflag);
12577       return;
12578     }
12579
12580   /* Skip mod/rm byte.  */
12581   MODRM_CHECK;
12582   codep++;
12583   used_prefixes |= (prefixes & PREFIX_DATA);
12584   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12585   oappend (scratchbuf + intel_syntax);
12586 }
12587
12588 static void
12589 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12590 {
12591   used_prefixes |= (prefixes & PREFIX_DATA);
12592   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12593   oappend (scratchbuf + intel_syntax);
12594 }
12595
12596 static void
12597 OP_EX (int bytemode, int sizeflag)
12598 {
12599   int add;
12600   if (modrm.mod != 3)
12601     {
12602       OP_E (bytemode, sizeflag);
12603       return;
12604     }
12605   USED_REX (REX_B);
12606   if (rex & REX_B)
12607     add = 8;
12608   else
12609     add = 0;
12610
12611   /* Skip mod/rm byte.  */
12612   MODRM_CHECK;
12613   codep++;
12614   if (need_vex
12615       && bytemode != xmm_mode
12616       && bytemode != xmmq_mode)
12617     {
12618       switch (vex.length)
12619         {
12620         case 128:
12621           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12622           break;
12623         case 256:
12624           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12625           break;
12626         default:
12627           abort ();
12628         }
12629     }
12630   else
12631     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12632   oappend (scratchbuf + intel_syntax);
12633 }
12634
12635 static void
12636 OP_MS (int bytemode, int sizeflag)
12637 {
12638   if (modrm.mod == 3)
12639     OP_EM (bytemode, sizeflag);
12640   else
12641     BadOp ();
12642 }
12643
12644 static void
12645 OP_XS (int bytemode, int sizeflag)
12646 {
12647   if (modrm.mod == 3)
12648     OP_EX (bytemode, sizeflag);
12649   else
12650     BadOp ();
12651 }
12652
12653 static void
12654 OP_M (int bytemode, int sizeflag)
12655 {
12656   if (modrm.mod == 3)
12657     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12658     BadOp ();
12659   else
12660     OP_E (bytemode, sizeflag);
12661 }
12662
12663 static void
12664 OP_0f07 (int bytemode, int sizeflag)
12665 {
12666   if (modrm.mod != 3 || modrm.rm != 0)
12667     BadOp ();
12668   else
12669     OP_E (bytemode, sizeflag);
12670 }
12671
12672 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12673    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12674
12675 static void
12676 NOP_Fixup1 (int bytemode, int sizeflag)
12677 {
12678   if ((prefixes & PREFIX_DATA) != 0
12679       || (rex != 0
12680           && rex != 0x48
12681           && address_mode == mode_64bit))
12682     OP_REG (bytemode, sizeflag);
12683   else
12684     strcpy (obuf, "nop");
12685 }
12686
12687 static void
12688 NOP_Fixup2 (int bytemode, int sizeflag)
12689 {
12690   if ((prefixes & PREFIX_DATA) != 0
12691       || (rex != 0
12692           && rex != 0x48
12693           && address_mode == mode_64bit))
12694     OP_IMREG (bytemode, sizeflag);
12695 }
12696
12697 static const char *const Suffix3DNow[] = {
12698 /* 00 */        NULL,           NULL,           NULL,           NULL,
12699 /* 04 */        NULL,           NULL,           NULL,           NULL,
12700 /* 08 */        NULL,           NULL,           NULL,           NULL,
12701 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12702 /* 10 */        NULL,           NULL,           NULL,           NULL,
12703 /* 14 */        NULL,           NULL,           NULL,           NULL,
12704 /* 18 */        NULL,           NULL,           NULL,           NULL,
12705 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12706 /* 20 */        NULL,           NULL,           NULL,           NULL,
12707 /* 24 */        NULL,           NULL,           NULL,           NULL,
12708 /* 28 */        NULL,           NULL,           NULL,           NULL,
12709 /* 2C */        NULL,           NULL,           NULL,           NULL,
12710 /* 30 */        NULL,           NULL,           NULL,           NULL,
12711 /* 34 */        NULL,           NULL,           NULL,           NULL,
12712 /* 38 */        NULL,           NULL,           NULL,           NULL,
12713 /* 3C */        NULL,           NULL,           NULL,           NULL,
12714 /* 40 */        NULL,           NULL,           NULL,           NULL,
12715 /* 44 */        NULL,           NULL,           NULL,           NULL,
12716 /* 48 */        NULL,           NULL,           NULL,           NULL,
12717 /* 4C */        NULL,           NULL,           NULL,           NULL,
12718 /* 50 */        NULL,           NULL,           NULL,           NULL,
12719 /* 54 */        NULL,           NULL,           NULL,           NULL,
12720 /* 58 */        NULL,           NULL,           NULL,           NULL,
12721 /* 5C */        NULL,           NULL,           NULL,           NULL,
12722 /* 60 */        NULL,           NULL,           NULL,           NULL,
12723 /* 64 */        NULL,           NULL,           NULL,           NULL,
12724 /* 68 */        NULL,           NULL,           NULL,           NULL,
12725 /* 6C */        NULL,           NULL,           NULL,           NULL,
12726 /* 70 */        NULL,           NULL,           NULL,           NULL,
12727 /* 74 */        NULL,           NULL,           NULL,           NULL,
12728 /* 78 */        NULL,           NULL,           NULL,           NULL,
12729 /* 7C */        NULL,           NULL,           NULL,           NULL,
12730 /* 80 */        NULL,           NULL,           NULL,           NULL,
12731 /* 84 */        NULL,           NULL,           NULL,           NULL,
12732 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12733 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12734 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12735 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12736 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12737 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12738 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12739 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12740 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12741 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12742 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12743 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12744 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12745 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12746 /* C0 */        NULL,           NULL,           NULL,           NULL,
12747 /* C4 */        NULL,           NULL,           NULL,           NULL,
12748 /* C8 */        NULL,           NULL,           NULL,           NULL,
12749 /* CC */        NULL,           NULL,           NULL,           NULL,
12750 /* D0 */        NULL,           NULL,           NULL,           NULL,
12751 /* D4 */        NULL,           NULL,           NULL,           NULL,
12752 /* D8 */        NULL,           NULL,           NULL,           NULL,
12753 /* DC */        NULL,           NULL,           NULL,           NULL,
12754 /* E0 */        NULL,           NULL,           NULL,           NULL,
12755 /* E4 */        NULL,           NULL,           NULL,           NULL,
12756 /* E8 */        NULL,           NULL,           NULL,           NULL,
12757 /* EC */        NULL,           NULL,           NULL,           NULL,
12758 /* F0 */        NULL,           NULL,           NULL,           NULL,
12759 /* F4 */        NULL,           NULL,           NULL,           NULL,
12760 /* F8 */        NULL,           NULL,           NULL,           NULL,
12761 /* FC */        NULL,           NULL,           NULL,           NULL,
12762 };
12763
12764 static void
12765 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12766 {
12767   const char *mnemonic;
12768
12769   FETCH_DATA (the_info, codep + 1);
12770   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12771      place where an 8-bit immediate would normally go.  ie. the last
12772      byte of the instruction.  */
12773   obufp = obuf + strlen (obuf);
12774   mnemonic = Suffix3DNow[*codep++ & 0xff];
12775   if (mnemonic)
12776     oappend (mnemonic);
12777   else
12778     {
12779       /* Since a variable sized modrm/sib chunk is between the start
12780          of the opcode (0x0f0f) and the opcode suffix, we need to do
12781          all the modrm processing first, and don't know until now that
12782          we have a bad opcode.  This necessitates some cleaning up.  */
12783       op_out[0][0] = '\0';
12784       op_out[1][0] = '\0';
12785       BadOp ();
12786     }
12787 }
12788
12789 static const char *simd_cmp_op[] = {
12790   "eq",
12791   "lt",
12792   "le",
12793   "unord",
12794   "neq",
12795   "nlt",
12796   "nle",
12797   "ord"
12798 };
12799
12800 static void
12801 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12802 {
12803   unsigned int cmp_type;
12804
12805   FETCH_DATA (the_info, codep + 1);
12806   cmp_type = *codep++ & 0xff;
12807   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12808     {
12809       char suffix [3];
12810       char *p = obuf + strlen (obuf) - 2;
12811       suffix[0] = p[0];
12812       suffix[1] = p[1];
12813       suffix[2] = '\0';
12814       sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix);
12815     }
12816   else
12817     {
12818       /* We have a reserved extension byte.  Output it directly.  */
12819       scratchbuf[0] = '$';
12820       print_operand_value (scratchbuf + 1, 1, cmp_type);
12821       oappend (scratchbuf + intel_syntax);
12822       scratchbuf[0] = '\0';
12823     }
12824 }
12825
12826 static void
12827 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12828           int sizeflag ATTRIBUTE_UNUSED)
12829 {
12830   /* mwait %eax,%ecx  */
12831   if (!intel_syntax)
12832     {
12833       const char **names = (address_mode == mode_64bit
12834                             ? names64 : names32);
12835       strcpy (op_out[0], names[0]);
12836       strcpy (op_out[1], names[1]);
12837       two_source_ops = 1;
12838     }
12839   /* Skip mod/rm byte.  */
12840   MODRM_CHECK;
12841   codep++;
12842 }
12843
12844 static void
12845 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12846             int sizeflag ATTRIBUTE_UNUSED)
12847 {
12848   /* monitor %eax,%ecx,%edx"  */
12849   if (!intel_syntax)
12850     {
12851       const char **op1_names;
12852       const char **names = (address_mode == mode_64bit
12853                             ? names64 : names32);
12854
12855       if (!(prefixes & PREFIX_ADDR))
12856         op1_names = (address_mode == mode_16bit
12857                      ? names16 : names);
12858       else
12859         {
12860           /* Remove "addr16/addr32".  */
12861           addr_prefix = NULL;
12862           op1_names = (address_mode != mode_32bit
12863                        ? names32 : names16);
12864           used_prefixes |= PREFIX_ADDR;
12865         }
12866       strcpy (op_out[0], op1_names[0]);
12867       strcpy (op_out[1], names[1]);
12868       strcpy (op_out[2], names[2]);
12869       two_source_ops = 1;
12870     }
12871   /* Skip mod/rm byte.  */
12872   MODRM_CHECK;
12873   codep++;
12874 }
12875
12876 static void
12877 BadOp (void)
12878 {
12879   /* Throw away prefixes and 1st. opcode byte.  */
12880   codep = insn_codep + 1;
12881   oappend ("(bad)");
12882 }
12883
12884 static void
12885 REP_Fixup (int bytemode, int sizeflag)
12886 {
12887   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12888      lods and stos.  */
12889   if (prefixes & PREFIX_REPZ)
12890     repz_prefix = "rep ";
12891
12892   switch (bytemode)
12893     {
12894     case al_reg:
12895     case eAX_reg:
12896     case indir_dx_reg:
12897       OP_IMREG (bytemode, sizeflag);
12898       break;
12899     case eDI_reg:
12900       OP_ESreg (bytemode, sizeflag);
12901       break;
12902     case eSI_reg:
12903       OP_DSreg (bytemode, sizeflag);
12904       break;
12905     default:
12906       abort ();
12907       break;
12908     }
12909 }
12910
12911 static void
12912 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12913 {
12914   USED_REX (REX_W);
12915   if (rex & REX_W)
12916     {
12917       /* Change cmpxchg8b to cmpxchg16b.  */
12918       char *p = obuf + strlen (obuf) - 2;
12919       strcpy (p, "16b");
12920       bytemode = o_mode;
12921     }
12922   OP_M (bytemode, sizeflag);
12923 }
12924
12925 static void
12926 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12927 {
12928   if (need_vex)
12929     {
12930       switch (vex.length)
12931         {
12932         case 128:
12933           sprintf (scratchbuf, "%%xmm%d", reg);
12934           break;
12935         case 256:
12936           sprintf (scratchbuf, "%%ymm%d", reg);
12937           break;
12938         default:
12939           abort ();
12940         }
12941     }
12942   else
12943     sprintf (scratchbuf, "%%xmm%d", reg);
12944   oappend (scratchbuf + intel_syntax);
12945 }
12946
12947 static void
12948 CRC32_Fixup (int bytemode, int sizeflag)
12949 {
12950   /* Add proper suffix to "crc32".  */
12951   char *p = obuf + strlen (obuf);
12952
12953   switch (bytemode)
12954     {
12955     case b_mode:
12956       if (intel_syntax)
12957         break;
12958
12959       *p++ = 'b';
12960       break;
12961     case v_mode:
12962       if (intel_syntax)
12963         break;
12964
12965       USED_REX (REX_W);
12966       if (rex & REX_W)
12967         *p++ = 'q';
12968       else if (sizeflag & DFLAG)
12969         *p++ = 'l';
12970       else
12971         *p++ = 'w';
12972       used_prefixes |= (prefixes & PREFIX_DATA);
12973       break;
12974     default:
12975       oappend (INTERNAL_DISASSEMBLER_ERROR);
12976       break;
12977     }
12978   *p = '\0';
12979
12980   if (modrm.mod == 3)
12981     {
12982       int add;
12983
12984       /* Skip mod/rm byte.  */
12985       MODRM_CHECK;
12986       codep++;
12987
12988       USED_REX (REX_B);
12989       add = (rex & REX_B) ? 8 : 0;
12990       if (bytemode == b_mode)
12991         {
12992           USED_REX (0);
12993           if (rex)
12994             oappend (names8rex[modrm.rm + add]);
12995           else
12996             oappend (names8[modrm.rm + add]);
12997         }
12998       else
12999         {
13000           USED_REX (REX_W);
13001           if (rex & REX_W)
13002             oappend (names64[modrm.rm + add]);
13003           else if ((prefixes & PREFIX_DATA))
13004             oappend (names16[modrm.rm + add]);
13005           else
13006             oappend (names32[modrm.rm + add]);
13007         }
13008     }
13009   else
13010     OP_E (bytemode, sizeflag);
13011 }
13012
13013 /* Print a DREX argument as either a register or memory operation.  */
13014 static void
13015 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
13016 {
13017   if (reg == DREX_REG_UNKNOWN)
13018     BadOp ();
13019
13020   else if (reg != DREX_REG_MEMORY)
13021     {
13022       sprintf (scratchbuf, "%%xmm%d", reg);
13023       oappend (scratchbuf + intel_syntax);
13024     }
13025
13026   else
13027     OP_E_extended (bytemode, sizeflag, 1);
13028 }
13029
13030 /* SSE5 instructions that have 4 arguments are encoded as:
13031    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
13032
13033    The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
13034    the DREX field (0x8) to determine how the arguments are laid out.
13035    The destination register must be the same register as one of the
13036    inputs, and it is encoded in the DREX byte.  No REX prefix is used
13037    for these instructions, since the DREX field contains the 3 extension
13038    bits provided by the REX prefix.
13039
13040    The bytemode argument adds 2 extra bits for passing extra information:
13041         DREX_OC1        -- Set the OC1 bit to indicate dest == 1st arg
13042         DREX_NO_OC0     -- OC0 in DREX is invalid
13043         (but pretend it is set).  */
13044
13045 static void
13046 OP_DREX4 (int flag_bytemode, int sizeflag)
13047 {
13048   unsigned int drex_byte;
13049   unsigned int regs[4];
13050   unsigned int modrm_regmem;
13051   unsigned int modrm_reg;
13052   unsigned int drex_reg;
13053   int bytemode;
13054   int rex_save = rex;
13055   int rex_used_save = rex_used;
13056   int has_sib = 0;
13057   int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
13058   int oc0;
13059   int i;
13060
13061   bytemode = flag_bytemode & ~ DREX_MASK;
13062
13063   for (i = 0; i < 4; i++)
13064     regs[i] = DREX_REG_UNKNOWN;
13065
13066   /* Determine if we have a SIB byte in addition to MODRM before the
13067      DREX byte.  */
13068   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13069       && (modrm.mod != 3)
13070       && (modrm.rm == 4))
13071     has_sib = 1;
13072
13073   /* Get the DREX byte.  */
13074   FETCH_DATA (the_info, codep + 2 + has_sib);
13075   drex_byte = codep[has_sib+1];
13076   drex_reg = DREX_XMM (drex_byte);
13077   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13078
13079   /* Is OC0 legal?  If not, hardwire oc0 == 1.  */
13080   if (flag_bytemode & DREX_NO_OC0)
13081     {
13082       oc0 = 1;
13083       if (DREX_OC0 (drex_byte))
13084         BadOp ();
13085     }
13086   else
13087     oc0 = DREX_OC0 (drex_byte);
13088
13089   if (modrm.mod == 3)
13090     {
13091       /* regmem == register  */
13092       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13093       rex = rex_used = 0;
13094       /* skip modrm/drex since we don't call OP_E_extended  */
13095       codep += 2;
13096     }
13097   else
13098     {
13099       /* regmem == memory, fill in appropriate REX bits  */
13100       modrm_regmem = DREX_REG_MEMORY;
13101       rex = drex_byte & (REX_B | REX_X | REX_R);
13102       if (rex)
13103         rex |= REX_OPCODE;
13104       rex_used = rex;
13105     }
13106
13107   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13108      order.  */
13109   switch (oc0 + oc1)
13110     {
13111     default:
13112       BadOp ();
13113       return;
13114
13115     case 0:
13116       regs[0] = modrm_regmem;
13117       regs[1] = modrm_reg;
13118       regs[2] = drex_reg;
13119       regs[3] = drex_reg;
13120       break;
13121
13122     case 1:
13123       regs[0] = modrm_reg;
13124       regs[1] = modrm_regmem;
13125       regs[2] = drex_reg;
13126       regs[3] = drex_reg;
13127       break;
13128
13129     case 2:
13130       regs[0] = drex_reg;
13131       regs[1] = modrm_regmem;
13132       regs[2] = modrm_reg;
13133       regs[3] = drex_reg;
13134       break;
13135
13136     case 3:
13137       regs[0] = drex_reg;
13138       regs[1] = modrm_reg;
13139       regs[2] = modrm_regmem;
13140       regs[3] = drex_reg;
13141       break;
13142     }
13143
13144   /* Print out the arguments.  */
13145   for (i = 0; i < 4; i++)
13146     {
13147       int j = (intel_syntax) ? 3 - i : i;
13148       if (i > 0)
13149         {
13150           *obufp++ = ',';
13151           *obufp = '\0';
13152         }
13153
13154       print_drex_arg (regs[j], bytemode, sizeflag);
13155     }
13156
13157   rex = rex_save;
13158   rex_used = rex_used_save;
13159 }
13160
13161 /* SSE5 instructions that have 3 arguments, and are encoded as:
13162    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>    (or)
13163    0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13164
13165    The DREX field has 1 bit (0x8) to determine how the arguments are
13166    laid out. The destination register is encoded in the DREX byte.
13167    No REX prefix is used for these instructions, since the DREX field
13168    contains the 3 extension bits provided by the REX prefix.  */
13169
13170 static void
13171 OP_DREX3 (int flag_bytemode, int sizeflag)
13172 {
13173   unsigned int drex_byte;
13174   unsigned int regs[3];
13175   unsigned int modrm_regmem;
13176   unsigned int modrm_reg;
13177   unsigned int drex_reg;
13178   int bytemode;
13179   int rex_save = rex;
13180   int rex_used_save = rex_used;
13181   int has_sib = 0;
13182   int oc0;
13183   int i;
13184
13185   bytemode = flag_bytemode & ~ DREX_MASK;
13186
13187   for (i = 0; i < 3; i++)
13188     regs[i] = DREX_REG_UNKNOWN;
13189
13190   /* Determine if we have a SIB byte in addition to MODRM before the
13191      DREX byte.  */
13192   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13193       && (modrm.mod != 3)
13194       && (modrm.rm == 4))
13195     has_sib = 1;
13196
13197   /* Get the DREX byte.  */
13198   FETCH_DATA (the_info, codep + 2 + has_sib);
13199   drex_byte = codep[has_sib+1];
13200   drex_reg = DREX_XMM (drex_byte);
13201   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13202
13203   /* Is OC0 legal?  If not, hardwire oc0 == 0 */
13204   oc0 = DREX_OC0 (drex_byte);
13205   if ((flag_bytemode & DREX_NO_OC0) && oc0)
13206     BadOp ();
13207
13208   if (modrm.mod == 3)
13209     {
13210       /* regmem == register */
13211       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13212       rex = rex_used = 0;
13213       /* skip modrm/drex since we don't call OP_E_extended.  */
13214       codep += 2;
13215     }
13216   else
13217     {
13218       /* regmem == memory, fill in appropriate REX bits.  */
13219       modrm_regmem = DREX_REG_MEMORY;
13220       rex = drex_byte & (REX_B | REX_X | REX_R);
13221       if (rex)
13222         rex |= REX_OPCODE;
13223       rex_used = rex;
13224     }
13225
13226   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13227      order.  */
13228   switch (oc0)
13229     {
13230     default:
13231       BadOp ();
13232       return;
13233
13234     case 0:
13235       regs[0] = modrm_regmem;
13236       regs[1] = modrm_reg;
13237       regs[2] = drex_reg;
13238       break;
13239
13240     case 1:
13241       regs[0] = modrm_reg;
13242       regs[1] = modrm_regmem;
13243       regs[2] = drex_reg;
13244       break;
13245     }
13246
13247   /* Print out the arguments.  */
13248   for (i = 0; i < 3; i++)
13249     {
13250       int j = (intel_syntax) ? 2 - i : i;
13251       if (i > 0)
13252         {
13253           *obufp++ = ',';
13254           *obufp = '\0';
13255         }
13256
13257       print_drex_arg (regs[j], bytemode, sizeflag);
13258     }
13259
13260   rex = rex_save;
13261   rex_used = rex_used_save;
13262 }
13263
13264 /* Emit a floating point comparison for comp<xx> instructions.  */
13265
13266 static void
13267 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13268               int sizeflag ATTRIBUTE_UNUSED)
13269 {
13270   unsigned char byte;
13271
13272   static const char *const cmp_test[] = {
13273     "eq",
13274     "lt",
13275     "le",
13276     "unord",
13277     "ne",
13278     "nlt",
13279     "nle",
13280     "ord",
13281     "ueq",
13282     "ult",
13283     "ule",
13284     "false",
13285     "une",
13286     "unlt",
13287     "unle",
13288     "true"
13289   };
13290
13291   FETCH_DATA (the_info, codep + 1);
13292   byte = *codep & 0xff;
13293
13294   if (byte >= ARRAY_SIZE (cmp_test)
13295       || obuf[0] != 'c'
13296       || obuf[1] != 'o'
13297       || obuf[2] != 'm')
13298     {
13299       /* The instruction isn't one we know about, so just append the
13300          extension byte as a numeric value.  */
13301       OP_I (b_mode, 0);
13302     }
13303
13304   else
13305     {
13306       sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13307       strcpy (obuf, scratchbuf);
13308       codep++;
13309     }
13310 }
13311
13312 /* Emit an integer point comparison for pcom<xx> instructions,
13313    rewriting the instruction to have the test inside of it.  */
13314
13315 static void
13316 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13317               int sizeflag ATTRIBUTE_UNUSED)
13318 {
13319   unsigned char byte;
13320
13321   static const char *const cmp_test[] = {
13322     "lt",
13323     "le",
13324     "gt",
13325     "ge",
13326     "eq",
13327     "ne",
13328     "false",
13329     "true"
13330   };
13331
13332   FETCH_DATA (the_info, codep + 1);
13333   byte = *codep & 0xff;
13334
13335   if (byte >= ARRAY_SIZE (cmp_test)
13336       || obuf[0] != 'p'
13337       || obuf[1] != 'c'
13338       || obuf[2] != 'o'
13339       || obuf[3] != 'm')
13340     {
13341       /* The instruction isn't one we know about, so just print the
13342          comparison test byte as a numeric value.  */
13343       OP_I (b_mode, 0);
13344     }
13345
13346   else
13347     {
13348       sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13349       strcpy (obuf, scratchbuf);
13350       codep++;
13351     }
13352 }
13353
13354 /* Display the destination register operand for instructions with
13355    VEX. */
13356
13357 static void
13358 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13359 {
13360   if (!need_vex)
13361     abort ();
13362
13363   if (!need_vex_reg)
13364     return;
13365
13366   switch (vex.length)
13367     {
13368     case 128:
13369       switch (bytemode)
13370         {
13371         case vex_mode:
13372         case vex128_mode:
13373           break;
13374         default:
13375           abort ();
13376           return;
13377         }
13378
13379       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13380       break;
13381     case 256:
13382       switch (bytemode)
13383         {
13384         case vex_mode:
13385         case vex256_mode:
13386           break;
13387         default:
13388           abort ();
13389           return;
13390         }
13391
13392       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13393       break;
13394     default:
13395       abort ();
13396       break;
13397     }
13398   oappend (scratchbuf + intel_syntax);
13399 }
13400
13401 /* Get the VEX immediate byte without moving codep.  */
13402
13403 static unsigned char
13404 get_vex_imm8 (int sizeflag)
13405 {
13406   int bytes_before_imm = 0;
13407
13408   /* Skip mod/rm byte.   */
13409   MODRM_CHECK;
13410   codep++;
13411
13412   if (modrm.mod != 3)
13413     {
13414       /* There are SIB/displacement bytes.  */
13415       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13416         {
13417           /* 32/64 bit address mode */
13418           int base = modrm.rm;
13419
13420           /* Check SIB byte.  */
13421           if (base == 4)
13422             {
13423               FETCH_DATA (the_info, codep + 1);
13424               base = *codep & 7;
13425               bytes_before_imm++;
13426             }
13427
13428           switch (modrm.mod)
13429             {
13430             case 0:
13431               /* When modrm.rm == 5 or modrm.rm == 4 and base in
13432                  SIB == 5, there is a 4 byte displacement.  */
13433               if (base != 5)
13434                 /* No displacement. */
13435                 break;
13436             case 2:
13437               /* 4 byte displacement.  */
13438               bytes_before_imm += 4;
13439               break;
13440             case 1:
13441               /* 1 byte displacement.  */
13442               bytes_before_imm++;
13443               break;
13444             }
13445         }
13446       else
13447         { /* 16 bit address mode */
13448           switch (modrm.mod)
13449             {
13450             case 0:
13451               /* When modrm.rm == 6, there is a 2 byte displacement.  */
13452               if (modrm.rm != 6)
13453                 /* No displacement. */
13454                 break;
13455             case 2:
13456               /* 2 byte displacement.  */
13457               bytes_before_imm += 2;
13458               break;
13459             case 1:
13460               /* 1 byte displacement.  */
13461               bytes_before_imm++;
13462               break;
13463             }
13464         }
13465     }
13466
13467   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13468   return codep [bytes_before_imm];
13469 }
13470
13471 static void
13472 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13473 {
13474   if (reg == -1 && modrm.mod != 3)
13475     {
13476       OP_E_memory (bytemode, sizeflag, 0);
13477       return;
13478     }
13479   else
13480     {
13481       if (reg == -1)
13482         {
13483           reg = modrm.rm;
13484           USED_REX (REX_B);
13485           if (rex & REX_B)
13486             reg += 8;
13487         }
13488       else if (reg > 7 && address_mode != mode_64bit)
13489         BadOp ();
13490     }
13491
13492   switch (vex.length)
13493     {
13494     case 128:
13495       sprintf (scratchbuf, "%%xmm%d", reg);
13496       break;
13497     case 256:
13498       sprintf (scratchbuf, "%%ymm%d", reg);
13499       break;
13500     default:
13501       abort ();
13502     }
13503   oappend (scratchbuf + intel_syntax);
13504 }
13505
13506 static void
13507 OP_EX_VexImmW (int bytemode, int sizeflag)
13508 {
13509   int reg = -1;
13510   static unsigned char vex_imm8;
13511
13512   if (!vex_w_done)
13513     {
13514       vex_imm8 = get_vex_imm8 (sizeflag);
13515       if (vex.w)
13516         reg = vex_imm8 >> 4;
13517       vex_w_done = 1;
13518     }
13519   else
13520     {
13521       if (!vex.w)
13522         reg = vex_imm8 >> 4;
13523     }
13524
13525   OP_EX_VexReg (bytemode, sizeflag, reg);
13526 }
13527
13528 static void
13529 OP_EX_VexW (int bytemode, int sizeflag)
13530 {
13531   int reg = -1;
13532
13533   if (!vex_w_done)
13534     {
13535       vex_w_done = 1;
13536       if (vex.w)
13537         reg = vex.register_specifier;
13538     }
13539   else
13540     {
13541       if (!vex.w)
13542         reg = vex.register_specifier;
13543     }
13544
13545   OP_EX_VexReg (bytemode, sizeflag, reg);
13546 }
13547
13548 static void
13549 OP_VEX_FMA (int bytemode, int sizeflag)
13550 {
13551   int reg = get_vex_imm8 (sizeflag) >> 4;
13552
13553   if (reg > 7 && address_mode != mode_64bit)
13554     BadOp ();
13555
13556   switch (vex.length)
13557     {
13558     case 128:
13559       switch (bytemode)
13560         {
13561         case vex_mode:
13562         case vex128_mode:
13563           break;
13564         default:
13565           abort ();
13566           return;
13567         }
13568
13569       sprintf (scratchbuf, "%%xmm%d", reg);
13570       break;
13571     case 256:
13572       switch (bytemode)
13573         {
13574         case vex_mode:
13575           break;
13576         default:
13577           abort ();
13578           return;
13579         }
13580
13581       sprintf (scratchbuf, "%%ymm%d", reg);
13582       break;
13583     default:
13584       abort ();
13585     }
13586   oappend (scratchbuf + intel_syntax);
13587 }
13588
13589 static void
13590 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13591              int sizeflag ATTRIBUTE_UNUSED)
13592 {
13593   /* Skip the immediate byte and check for invalid bits.  */
13594   FETCH_DATA (the_info, codep + 1);
13595   if (*codep++ & 0xf)
13596     BadOp ();
13597 }
13598
13599 static void
13600 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13601 {
13602   int reg;
13603   FETCH_DATA (the_info, codep + 1);
13604   reg = *codep++;
13605
13606   if (bytemode != x_mode)
13607     abort ();
13608
13609   if (reg & 0xf)
13610       BadOp ();
13611
13612   reg >>= 4;
13613   if (reg > 7 && address_mode != mode_64bit)
13614     BadOp ();
13615
13616   switch (vex.length)
13617     {
13618     case 128:
13619       sprintf (scratchbuf, "%%xmm%d", reg);
13620       break;
13621     case 256:
13622       sprintf (scratchbuf, "%%ymm%d", reg);
13623       break;
13624     default:
13625       abort ();
13626     }
13627   oappend (scratchbuf + intel_syntax);
13628 }
13629
13630 static void
13631 OP_XMM_VexW (int bytemode, int sizeflag)
13632 {
13633   /* Turn off the REX.W bit since it is used for swapping operands
13634      now.  */
13635   rex &= ~REX_W;
13636   OP_XMM (bytemode, sizeflag);
13637 }
13638
13639 static void
13640 OP_EX_Vex (int bytemode, int sizeflag)
13641 {
13642   if (modrm.mod != 3)
13643     {
13644       if (vex.register_specifier != 0)
13645         BadOp ();
13646       need_vex_reg = 0;
13647     }
13648   OP_EX (bytemode, sizeflag);
13649 }
13650
13651 static void
13652 OP_XMM_Vex (int bytemode, int sizeflag)
13653 {
13654   if (modrm.mod != 3)
13655     {
13656       if (vex.register_specifier != 0)
13657         BadOp ();
13658       need_vex_reg = 0;
13659     }
13660   OP_XMM (bytemode, sizeflag);
13661 }
13662
13663 static void
13664 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13665 {
13666   switch (vex.length)
13667     {
13668     case 128:
13669       strcpy (obuf, "vzeroupper");
13670       break;
13671     case 256:
13672       strcpy (obuf, "vzeroall");
13673       break;
13674     default:
13675       abort ();
13676     }
13677 }
13678
13679 static const char *vex_cmp_op[] = {
13680   "eq",
13681   "lt",
13682   "le",
13683   "unord",
13684   "neq",
13685   "nlt",
13686   "nle",
13687   "ord",
13688   "eq_uq",
13689   "nge",
13690   "ngt",
13691   "false",
13692   "neq_oq",
13693   "ge",
13694   "gt",
13695   "true",
13696   "eq_os",
13697   "lt_oq",
13698   "le_oq",
13699   "unord_s",
13700   "neq_us",
13701   "nlt_uq",
13702   "nle_uq",
13703   "ord_s",
13704   "eq_us",
13705   "nge_uq",
13706   "ngt_uq",
13707   "false_os",
13708   "neq_os",
13709   "ge_oq",
13710   "gt_oq",
13711   "true_us"
13712 };
13713
13714 static void
13715 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13716 {
13717   unsigned int cmp_type;
13718
13719   FETCH_DATA (the_info, codep + 1);
13720   cmp_type = *codep++ & 0xff;
13721   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13722     {
13723       char suffix [3];
13724       char *p = obuf + strlen (obuf) - 2;
13725       suffix[0] = p[0];
13726       suffix[1] = p[1];
13727       suffix[2] = '\0';
13728       sprintf (p, "%s%s", vex_cmp_op[cmp_type], suffix);
13729     }
13730   else
13731     {
13732       /* We have a reserved extension byte.  Output it directly.  */
13733       scratchbuf[0] = '$';
13734       print_operand_value (scratchbuf + 1, 1, cmp_type);
13735       oappend (scratchbuf + intel_syntax);
13736       scratchbuf[0] = '\0';
13737     }
13738 }
13739
13740 static const char *pclmul_op[] = {
13741   "lql",
13742   "hql",
13743   "lqh",
13744   "hqh"
13745 };
13746
13747 static void
13748 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13749               int sizeflag ATTRIBUTE_UNUSED)
13750 {
13751   unsigned int pclmul_type;
13752
13753   FETCH_DATA (the_info, codep + 1);
13754   pclmul_type = *codep++ & 0xff;
13755   switch (pclmul_type)
13756     {
13757     case 0x10:
13758       pclmul_type = 2;
13759       break;
13760     case 0x11:
13761       pclmul_type = 3;
13762       break;
13763     default:
13764       break;
13765     }
13766   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13767     {
13768       char suffix [4];
13769       char *p = obuf + strlen (obuf) - 3;
13770       suffix[0] = p[0];
13771       suffix[1] = p[1];
13772       suffix[2] = p[2];
13773       suffix[3] = '\0';
13774       sprintf (p, "%s%s", pclmul_op[pclmul_type], suffix);
13775     }
13776   else
13777     {
13778       /* We have a reserved extension byte.  Output it directly.  */
13779       scratchbuf[0] = '$';
13780       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13781       oappend (scratchbuf + intel_syntax);
13782       scratchbuf[0] = '\0';
13783     }
13784 }
13785
13786 static const char *vpermil2_op[] = {
13787   "td",
13788   "td",
13789   "mo",
13790   "mz"
13791 };
13792
13793 static void
13794 VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
13795                 int sizeflag ATTRIBUTE_UNUSED)
13796 {
13797   unsigned int vpermil2_type;
13798
13799   FETCH_DATA (the_info, codep + 1);
13800   vpermil2_type = *codep++ & 0xf;
13801   if (vpermil2_type < ARRAY_SIZE (vpermil2_op))
13802     {
13803       char suffix [4];
13804       char *p = obuf + strlen (obuf) - 3;
13805       suffix[0] = p[0];
13806       suffix[1] = p[1];
13807       suffix[2] = p[2];
13808       suffix[3] = '\0';
13809       sprintf (p, "%s%s", vpermil2_op[vpermil2_type], suffix);
13810     }
13811   else
13812     {
13813       /* We have a reserved extension byte.  Output it directly.  */
13814       scratchbuf[0] = '$';
13815       print_operand_value (scratchbuf + 1, 1, vpermil2_type);
13816       oappend (scratchbuf + intel_syntax);
13817       scratchbuf[0] = '\0';
13818     }
13819 }
13820
13821 static void
13822 MOVBE_Fixup (int bytemode, int sizeflag)
13823 {
13824   /* Add proper suffix to "movbe".  */
13825   char *p = obuf + strlen (obuf);
13826
13827   switch (bytemode)
13828     {
13829     case v_mode:
13830       if (intel_syntax)
13831         break;
13832
13833       USED_REX (REX_W);
13834       if (sizeflag & SUFFIX_ALWAYS)
13835         {
13836           if (rex & REX_W)
13837             *p++ = 'q';
13838           else if (sizeflag & DFLAG)
13839             *p++ = 'l';
13840           else
13841             *p++ = 'w';
13842         }
13843       used_prefixes |= (prefixes & PREFIX_DATA);
13844       break;
13845     default:
13846       oappend (INTERNAL_DISASSEMBLER_ERROR);
13847       break;
13848     }
13849   *p = '\0';
13850
13851   OP_M (bytemode, sizeflag);
13852 }