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Add support for DragonFlyBSD target.
[binutils.git] / gas / config / tc-avr.c
blobef8cf9391526e74e2563070601cae42b40eee7e8
1 /* tc-avr.c -- Assembler code for the ATMEL AVR
2
3 Copyright 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008, 2009,
4 2010 Free Software Foundation, Inc.
5 Contributed by Denis Chertykov <denisc@overta.ru>
6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
22 Boston, MA 02110-1301, USA. */
23
24 #include "as.h"
25 #include "safe-ctype.h"
26 #include "subsegs.h"
27
28 struct avr_opcodes_s
29 {
30 char * name;
31 char * constraints;
32 char * opcode;
33 int insn_size; /* In words. */
34 int isa;
35 unsigned int bin_opcode;
36 };
37
38 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
39 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
40
41 struct avr_opcodes_s avr_opcodes[] =
42 {
43 #include "opcode/avr.h"
44 {NULL, NULL, NULL, 0, 0, 0}
45 };
46
47 const char comment_chars[] = ";";
48 const char line_comment_chars[] = "#";
49 const char line_separator_chars[] = "$";
50
51 const char *md_shortopts = "m:";
52 struct mcu_type_s
53 {
54 char *name;
55 int isa;
56 int mach;
57 };
58
59 /* XXX - devices that don't seem to exist (renamed, replaced with larger
60 ones, or planned but never produced), left here for compatibility. */
61
62 static struct mcu_type_s mcu_types[] =
63 {
64 {"avr1", AVR_ISA_AVR1, bfd_mach_avr1},
65 /* TODO: insruction set for avr2 architecture should be AVR_ISA_AVR2,
66 but set to AVR_ISA_AVR25 for some following version
67 of GCC (from 4.3) for backward compatibility. */
68 {"avr2", AVR_ISA_AVR25, bfd_mach_avr2},
69 {"avr25", AVR_ISA_AVR25, bfd_mach_avr25},
70 /* TODO: insruction set for avr3 architecture should be AVR_ISA_AVR3,
71 but set to AVR_ISA_AVR3_ALL for some following version
72 of GCC (from 4.3) for backward compatibility. */
73 {"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3},
74 {"avr31", AVR_ISA_AVR31, bfd_mach_avr31},
75 {"avr35", AVR_ISA_AVR35, bfd_mach_avr35},
76 {"avr4", AVR_ISA_AVR4, bfd_mach_avr4},
77 /* TODO: insruction set for avr5 architecture should be AVR_ISA_AVR5,
78 but set to AVR_ISA_AVR51 for some following version
79 of GCC (from 4.3) for backward compatibility. */
80 {"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
81 {"avr51", AVR_ISA_AVR51, bfd_mach_avr51},
82 {"avr6", AVR_ISA_AVR6, bfd_mach_avr6},
83 {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1},
84 {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
85 {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
86 {"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
87 {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
88 {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
89 {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
90 {"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
91 {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
92 {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
93 {"attiny15", AVR_ISA_AVR1, bfd_mach_avr1},
94 {"attiny28", AVR_ISA_AVR1, bfd_mach_avr1},
95 {"at90s2313", AVR_ISA_AVR2, bfd_mach_avr2},
96 {"at90s2323", AVR_ISA_AVR2, bfd_mach_avr2},
97 {"at90s2333", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 4433 */
98 {"at90s2343", AVR_ISA_AVR2, bfd_mach_avr2},
99 {"attiny22", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 2343 */
100 {"attiny26", AVR_ISA_2xxe, bfd_mach_avr2},
101 {"at90s4414", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8515 */
102 {"at90s4433", AVR_ISA_AVR2, bfd_mach_avr2},
103 {"at90s4434", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8535 */
104 {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2},
105 {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2},
106 {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2},
107 {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25},
108 {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25},
109 {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25},
110 {"attiny2313a",AVR_ISA_AVR25, bfd_mach_avr25},
111 {"attiny24", AVR_ISA_AVR25, bfd_mach_avr25},
112 {"attiny24a", AVR_ISA_AVR25, bfd_mach_avr25},
113 {"attiny4313", AVR_ISA_AVR25, bfd_mach_avr25},
114 {"attiny44", AVR_ISA_AVR25, bfd_mach_avr25},
115 {"attiny44a", AVR_ISA_AVR25, bfd_mach_avr25},
116 {"attiny84", AVR_ISA_AVR25, bfd_mach_avr25},
117 {"attiny84a", AVR_ISA_AVR25, bfd_mach_avr25},
118 {"attiny25", AVR_ISA_AVR25, bfd_mach_avr25},
119 {"attiny45", AVR_ISA_AVR25, bfd_mach_avr25},
120 {"attiny85", AVR_ISA_AVR25, bfd_mach_avr25},
121 {"attiny261", AVR_ISA_AVR25, bfd_mach_avr25},
122 {"attiny261a", AVR_ISA_AVR25, bfd_mach_avr25},
123 {"attiny461", AVR_ISA_AVR25, bfd_mach_avr25},
124 {"attiny461a", AVR_ISA_AVR25, bfd_mach_avr25},
125 {"attiny861", AVR_ISA_AVR25, bfd_mach_avr25},
126 {"attiny861a", AVR_ISA_AVR25, bfd_mach_avr25},
127 {"attiny87", AVR_ISA_AVR25, bfd_mach_avr25},
128 {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25},
129 {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25},
130 {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25},
131 {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25},
132 {"ata6289", AVR_ISA_AVR25, bfd_mach_avr25},
133 {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3},
134 {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3},
135 {"atmega103", AVR_ISA_AVR31, bfd_mach_avr31},
136 {"at43usb320", AVR_ISA_AVR31, bfd_mach_avr31},
137 {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35},
138 {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35},
139 {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35},
140 {"atmega8u2", AVR_ISA_AVR35, bfd_mach_avr35},
141 {"atmega16u2", AVR_ISA_AVR35, bfd_mach_avr35},
142 {"atmega32u2", AVR_ISA_AVR35, bfd_mach_avr35},
143 {"atmega8", AVR_ISA_M8, bfd_mach_avr4},
144 {"atmega48", AVR_ISA_AVR4, bfd_mach_avr4},
145 {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4},
146 {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4},
147 {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4},
148 {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4},
149 {"atmega88p", AVR_ISA_AVR4, bfd_mach_avr4},
150 {"atmega88pa", AVR_ISA_AVR4, bfd_mach_avr4},
151 {"atmega8515", AVR_ISA_M8, bfd_mach_avr4},
152 {"atmega8535", AVR_ISA_M8, bfd_mach_avr4},
153 {"atmega8hva", AVR_ISA_AVR4, bfd_mach_avr4},
154 {"at90pwm1", AVR_ISA_AVR4, bfd_mach_avr4},
155 {"at90pwm2", AVR_ISA_AVR4, bfd_mach_avr4},
156 {"at90pwm2b", AVR_ISA_AVR4, bfd_mach_avr4},
157 {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4},
158 {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4},
159 {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4},
160 {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5},
161 {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5},
162 {"atmega161", AVR_ISA_M161, bfd_mach_avr5},
163 {"atmega162", AVR_ISA_AVR5, bfd_mach_avr5},
164 {"atmega163", AVR_ISA_M161, bfd_mach_avr5},
165 {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5},
166 {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5},
167 {"atmega165", AVR_ISA_AVR5, bfd_mach_avr5},
168 {"atmega165a", AVR_ISA_AVR5, bfd_mach_avr5},
169 {"atmega165p", AVR_ISA_AVR5, bfd_mach_avr5},
170 {"atmega168", AVR_ISA_AVR5, bfd_mach_avr5},
171 {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5},
172 {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5},
173 {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5},
174 {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5},
175 {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5},
176 {"atmega169pa",AVR_ISA_AVR5, bfd_mach_avr5},
177 {"atmega32", AVR_ISA_AVR5, bfd_mach_avr5},
178 {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5},
179 {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5},
180 {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5},
181 {"atmega324pa",AVR_ISA_AVR5, bfd_mach_avr5},
182 {"atmega325", AVR_ISA_AVR5, bfd_mach_avr5},
183 {"atmega325a", AVR_ISA_AVR5, bfd_mach_avr5},
184 {"atmega325p", AVR_ISA_AVR5, bfd_mach_avr5},
185 {"atmega325pa",AVR_ISA_AVR5, bfd_mach_avr5},
186 {"atmega3250", AVR_ISA_AVR5, bfd_mach_avr5},
187 {"atmega3250a",AVR_ISA_AVR5, bfd_mach_avr5},
188 {"atmega3250p",AVR_ISA_AVR5, bfd_mach_avr5},
189 {"atmega3250pa",AVR_ISA_AVR5, bfd_mach_avr5},
190 {"atmega328", AVR_ISA_AVR5, bfd_mach_avr5},
191 {"atmega328p", AVR_ISA_AVR5, bfd_mach_avr5},
192 {"atmega329", AVR_ISA_AVR5, bfd_mach_avr5},
193 {"atmega329a", AVR_ISA_AVR5, bfd_mach_avr5},
194 {"atmega329p", AVR_ISA_AVR5, bfd_mach_avr5},
195 {"atmega329pa",AVR_ISA_AVR5, bfd_mach_avr5},
196 {"atmega3290", AVR_ISA_AVR5, bfd_mach_avr5},
197 {"atmega3290a",AVR_ISA_AVR5, bfd_mach_avr5},
198 {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5},
199 {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5},
200 {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5},
201 {"atmega64", AVR_ISA_AVR5, bfd_mach_avr5},
202 {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5},
203 {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5},
204 {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5},
205 {"atmega644p", AVR_ISA_AVR5, bfd_mach_avr5},
206 {"atmega644pa",AVR_ISA_AVR5, bfd_mach_avr5},
207 {"atmega645", AVR_ISA_AVR5, bfd_mach_avr5},
208 {"atmega645a", AVR_ISA_AVR5, bfd_mach_avr5},
209 {"atmega645p", AVR_ISA_AVR5, bfd_mach_avr5},
210 {"atmega649", AVR_ISA_AVR5, bfd_mach_avr5},
211 {"atmega649a", AVR_ISA_AVR5, bfd_mach_avr5},
212 {"atmega649p", AVR_ISA_AVR5, bfd_mach_avr5},
213 {"atmega6450", AVR_ISA_AVR5, bfd_mach_avr5},
214 {"atmega6450a",AVR_ISA_AVR5, bfd_mach_avr5},
215 {"atmega6450p",AVR_ISA_AVR5, bfd_mach_avr5},
216 {"atmega6490", AVR_ISA_AVR5, bfd_mach_avr5},
217 {"atmega6490a",AVR_ISA_AVR5, bfd_mach_avr5},
218 {"atmega6490p",AVR_ISA_AVR5, bfd_mach_avr5},
219 {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5},
220 {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5},
221 {"atmega16hvb",AVR_ISA_AVR5, bfd_mach_avr5},
222 {"atmega16hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
223 {"atmega32hvb",AVR_ISA_AVR5, bfd_mach_avr5},
224 {"atmega32hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
225 {"atmega64hve",AVR_ISA_AVR5, bfd_mach_avr5},
226 {"at90can32" , AVR_ISA_AVR5, bfd_mach_avr5},
227 {"at90can64" , AVR_ISA_AVR5, bfd_mach_avr5},
228 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
229 {"at90pwm216", AVR_ISA_AVR5, bfd_mach_avr5},
230 {"at90pwm316", AVR_ISA_AVR5, bfd_mach_avr5},
231 {"atmega32c1", AVR_ISA_AVR5, bfd_mach_avr5},
232 {"atmega64c1", AVR_ISA_AVR5, bfd_mach_avr5},
233 {"atmega16m1", AVR_ISA_AVR5, bfd_mach_avr5},
234 {"atmega32m1", AVR_ISA_AVR5, bfd_mach_avr5},
235 {"atmega64m1", AVR_ISA_AVR5, bfd_mach_avr5},
236 {"atmega16u4", AVR_ISA_AVR5, bfd_mach_avr5},
237 {"atmega32u4", AVR_ISA_AVR5, bfd_mach_avr5},
238 {"atmega32u6", AVR_ISA_AVR5, bfd_mach_avr5},
239 {"at90usb646", AVR_ISA_AVR5, bfd_mach_avr5},
240 {"at90usb647", AVR_ISA_AVR5, bfd_mach_avr5},
241 {"at90scr100", AVR_ISA_AVR5, bfd_mach_avr5},
242 {"at94k", AVR_ISA_94K, bfd_mach_avr5},
243 {"m3000", AVR_ISA_AVR5, bfd_mach_avr5},
244 {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51},
245 {"atmega1280", AVR_ISA_AVR51, bfd_mach_avr51},
246 {"atmega1281", AVR_ISA_AVR51, bfd_mach_avr51},
247 {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51},
248 {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51},
249 {"at90can128", AVR_ISA_AVR51, bfd_mach_avr51},
250 {"at90usb1286",AVR_ISA_AVR51, bfd_mach_avr51},
251 {"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51},
252 {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6},
253 {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6},
254 {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
255 {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
256 {"atxmega16x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
257 {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
258 {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
259 {"atxmega32x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
260 {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
261 {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
262 {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
263 {"atxmega64a1u",AVR_ISA_XMEGA, bfd_mach_avrxmega5},
264 {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
265 {"atxmega128b1", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
266 {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
267 {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
268 {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
269 {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
270 {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
271 {"atxmega256a3bu",AVR_ISA_XMEGA,bfd_mach_avrxmega6},
272 {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
273 {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
274 {"atxmega128a1u", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
275 {NULL, 0, 0}
276 };
277
278 /* Current MCU type. */
279 static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2};
280 static struct mcu_type_s * avr_mcu = & default_mcu;
281
282 /* AVR target-specific switches. */
283 struct avr_opt_s
284 {
285 int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */
286 int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
287 int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
288 };
289
290 static struct avr_opt_s avr_opt = { 0, 0, 0 };
291
292 const char EXP_CHARS[] = "eE";
293 const char FLT_CHARS[] = "dD";
294
295 static void avr_set_arch (int);
296
297 /* The target specific pseudo-ops which we support. */
298 const pseudo_typeS md_pseudo_table[] =
299 {
300 {"arch", avr_set_arch, 0},
301 { NULL, NULL, 0}
302 };
303
304 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
305
306 #define EXP_MOD_NAME(i) exp_mod[i].name
307 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
308 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
309 #define HAVE_PM_P(i) exp_mod[i].have_pm
310
311 struct exp_mod_s
312 {
313 char * name;
314 bfd_reloc_code_real_type reloc;
315 bfd_reloc_code_real_type neg_reloc;
316 int have_pm;
317 };
318
319 static struct exp_mod_s exp_mod[] =
320 {
321 {"hh8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 1},
322 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM, BFD_RELOC_AVR_HH8_LDI_PM_NEG, 0},
323 {"hi8", BFD_RELOC_AVR_HI8_LDI, BFD_RELOC_AVR_HI8_LDI_NEG, 1},
324 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM, BFD_RELOC_AVR_HI8_LDI_PM_NEG, 0},
325 {"lo8", BFD_RELOC_AVR_LO8_LDI, BFD_RELOC_AVR_LO8_LDI_NEG, 1},
326 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM, BFD_RELOC_AVR_LO8_LDI_PM_NEG, 0},
327 {"hlo8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 0},
328 {"hhi8", BFD_RELOC_AVR_MS8_LDI, BFD_RELOC_AVR_MS8_LDI_NEG, 0},
329 };
330
331 /* A union used to store indicies into the exp_mod[] array
332 in a hash table which expects void * data types. */
333 typedef union
334 {
335 void * ptr;
336 int index;
337 } mod_index;
338
339 /* Opcode hash table. */
340 static struct hash_control *avr_hash;
341
342 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
343 static struct hash_control *avr_mod_hash;
344
345 #define OPTION_MMCU 'm'
346 enum options
347 {
348 OPTION_ALL_OPCODES = OPTION_MD_BASE + 1,
349 OPTION_NO_SKIP_BUG,
350 OPTION_NO_WRAP
351 };
352
353 struct option md_longopts[] =
354 {
355 { "mmcu", required_argument, NULL, OPTION_MMCU },
356 { "mall-opcodes", no_argument, NULL, OPTION_ALL_OPCODES },
357 { "mno-skip-bug", no_argument, NULL, OPTION_NO_SKIP_BUG },
358 { "mno-wrap", no_argument, NULL, OPTION_NO_WRAP },
359 { NULL, no_argument, NULL, 0 }
360 };
361
362 size_t md_longopts_size = sizeof (md_longopts);
363
364 /* Display nicely formatted list of known MCU names. */
365
366 static void
367 show_mcu_list (FILE *stream)
368 {
369 int i, x;
370
371 fprintf (stream, _("Known MCU names:"));
372 x = 1000;
373
374 for (i = 0; mcu_types[i].name; i++)
375 {
376 int len = strlen (mcu_types[i].name);
377
378 x += len + 1;
379
380 if (x < 75)
381 fprintf (stream, " %s", mcu_types[i].name);
382 else
383 {
384 fprintf (stream, "\n %s", mcu_types[i].name);
385 x = len + 2;
386 }
387 }
388
389 fprintf (stream, "\n");
390 }
391
392 static inline char *
393 skip_space (char *s)
394 {
395 while (*s == ' ' || *s == '\t')
396 ++s;
397 return s;
398 }
399
400 /* Extract one word from FROM and copy it to TO. */
401
402 static char *
403 extract_word (char *from, char *to, int limit)
404 {
405 char *op_end;
406 int size = 0;
407
408 /* Drop leading whitespace. */
409 from = skip_space (from);
410 *to = 0;
411
412 /* Find the op code end. */
413 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
414 {
415 to[size++] = *op_end++;
416 if (size + 1 >= limit)
417 break;
418 }
419
420 to[size] = 0;
421 return op_end;
422 }
423
424 int
425 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
426 asection *seg ATTRIBUTE_UNUSED)
427 {
428 abort ();
429 return 0;
430 }
431
432 void
433 md_show_usage (FILE *stream)
434 {
435 fprintf (stream,
436 _("AVR Assembler options:\n"
437 " -mmcu=[avr-name] select microcontroller variant\n"
438 " [avr-name] can be:\n"
439 " avr1 - classic AVR core without data RAM\n"
440 " avr2 - classic AVR core with up to 8K program memory\n"
441 " avr25 - classic AVR core with up to 8K program memory\n"
442 " plus the MOVW instruction\n"
443 " avr3 - classic AVR core with up to 64K program memory\n"
444 " avr31 - classic AVR core with up to 128K program memory\n"
445 " avr35 - classic AVR core with up to 64K program memory\n"
446 " plus the MOVW instruction\n"
447 " avr4 - enhanced AVR core with up to 8K program memory\n"
448 " avr5 - enhanced AVR core with up to 64K program memory\n"
449 " avr51 - enhanced AVR core with up to 128K program memory\n"
450 " avr6 - enhanced AVR core with up to 256K program memory\n"
451 " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n"
452 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
453 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
454 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
455 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
456 " or immediate microcontroller name.\n"));
457 fprintf (stream,
458 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
459 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
460 " (default for avr4, avr5)\n"
461 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
462 " (default for avr3, avr5)\n"));
463 show_mcu_list (stream);
464 }
465
466 static void
467 avr_set_arch (int dummy ATTRIBUTE_UNUSED)
468 {
469 char str[20];
470
471 input_line_pointer = extract_word (input_line_pointer, str, 20);
472 md_parse_option (OPTION_MMCU, str);
473 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
474 }
475
476 int
477 md_parse_option (int c, char *arg)
478 {
479 switch (c)
480 {
481 case OPTION_MMCU:
482 {
483 int i;
484 char *s = alloca (strlen (arg) + 1);
485
486 {
487 char *t = s;
488 char *arg1 = arg;
489
490 do
491 *t = TOLOWER (*arg1++);
492 while (*t++);
493 }
494
495 for (i = 0; mcu_types[i].name; ++i)
496 if (strcmp (mcu_types[i].name, s) == 0)
497 break;
498
499 if (!mcu_types[i].name)
500 {
501 show_mcu_list (stderr);
502 as_fatal (_("unknown MCU: %s\n"), arg);
503 }
504
505 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
506 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
507 as .arch ... in the asm output at the same time. */
508 if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach)
509 avr_mcu = &mcu_types[i];
510 else
511 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
512 avr_mcu->name, mcu_types[i].name);
513 return 1;
514 }
515 case OPTION_ALL_OPCODES:
516 avr_opt.all_opcodes = 1;
517 return 1;
518 case OPTION_NO_SKIP_BUG:
519 avr_opt.no_skip_bug = 1;
520 return 1;
521 case OPTION_NO_WRAP:
522 avr_opt.no_wrap = 1;
523 return 1;
524 }
525
526 return 0;
527 }
528
529 symbolS *
530 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
531 {
532 return NULL;
533 }
534
535 char *
536 md_atof (int type, char *litP, int *sizeP)
537 {
538 return ieee_md_atof (type, litP, sizeP, FALSE);
539 }
540
541 void
542 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
543 asection *sec ATTRIBUTE_UNUSED,
544 fragS *fragP ATTRIBUTE_UNUSED)
545 {
546 abort ();
547 }
548
549 void
550 md_begin (void)
551 {
552 unsigned int i;
553 struct avr_opcodes_s *opcode;
554
555 avr_hash = hash_new ();
556
557 /* Insert unique names into hash table. This hash table then provides a
558 quick index to the first opcode with a particular name in the opcode
559 table. */
560 for (opcode = avr_opcodes; opcode->name; opcode++)
561 hash_insert (avr_hash, opcode->name, (char *) opcode);
562
563 avr_mod_hash = hash_new ();
564
565 for (i = 0; i < ARRAY_SIZE (exp_mod); ++i)
566 {
567 mod_index m;
568
569 m.index = i + 10;
570 hash_insert (avr_mod_hash, EXP_MOD_NAME (i), m.ptr);
571 }
572
573 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
574 }
575
576 /* Resolve STR as a constant expression and return the result.
577 If result greater than MAX then error. */
578
579 static unsigned int
580 avr_get_constant (char *str, int max)
581 {
582 expressionS ex;
583
584 str = skip_space (str);
585 input_line_pointer = str;
586 expression (& ex);
587
588 if (ex.X_op != O_constant)
589 as_bad (_("constant value required"));
590
591 if (ex.X_add_number > max || ex.X_add_number < 0)
592 as_bad (_("number must be positive and less than %d"), max + 1);
593
594 return ex.X_add_number;
595 }
596
597 /* Parse for ldd/std offset. */
598
599 static void
600 avr_offset_expression (expressionS *exp)
601 {
602 char *str = input_line_pointer;
603 char *tmp;
604 char op[8];
605
606 tmp = str;
607 str = extract_word (str, op, sizeof (op));
608
609 input_line_pointer = tmp;
610 expression (exp);
611
612 /* Warn about expressions that fail to use lo8 (). */
613 if (exp->X_op == O_constant)
614 {
615 int x = exp->X_add_number;
616
617 if (x < -255 || x > 255)
618 as_warn (_("constant out of 8-bit range: %d"), x);
619 }
620 }
621
622 /* Parse ordinary expression. */
623
624 static char *
625 parse_exp (char *s, expressionS *op)
626 {
627 input_line_pointer = s;
628 expression (op);
629 if (op->X_op == O_absent)
630 as_bad (_("missing operand"));
631 return input_line_pointer;
632 }
633
634 /* Parse special expressions (needed for LDI command):
635 xx8 (address)
636 xx8 (-address)
637 pm_xx8 (address)
638 pm_xx8 (-address)
639 where xx is: hh, hi, lo. */
640
641 static bfd_reloc_code_real_type
642 avr_ldi_expression (expressionS *exp)
643 {
644 char *str = input_line_pointer;
645 char *tmp;
646 char op[8];
647 int mod;
648 int linker_stubs_should_be_generated = 0;
649
650 tmp = str;
651
652 str = extract_word (str, op, sizeof (op));
653
654 if (op[0])
655 {
656 mod_index m;
657
658 m.ptr = hash_find (avr_mod_hash, op);
659 mod = m.index;
660
661 if (mod)
662 {
663 int closes = 0;
664
665 mod -= 10;
666 str = skip_space (str);
667
668 if (*str == '(')
669 {
670 bfd_reloc_code_real_type reloc_to_return;
671 int neg_p = 0;
672
673 ++str;
674
675 if (strncmp ("pm(", str, 3) == 0
676 || strncmp ("gs(",str,3) == 0
677 || strncmp ("-(gs(",str,5) == 0
678 || strncmp ("-(pm(", str, 5) == 0)
679 {
680 if (HAVE_PM_P (mod))
681 {
682 ++mod;
683 ++closes;
684 }
685 else
686 as_bad (_("illegal expression"));
687
688 if (str[0] == 'g' || str[2] == 'g')
689 linker_stubs_should_be_generated = 1;
690
691 if (*str == '-')
692 {
693 neg_p = 1;
694 ++closes;
695 str += 5;
696 }
697 else
698 str += 3;
699 }
700
701 if (*str == '-' && *(str + 1) == '(')
702 {
703 neg_p ^= 1;
704 ++closes;
705 str += 2;
706 }
707
708 input_line_pointer = str;
709 expression (exp);
710
711 do
712 {
713 if (*input_line_pointer != ')')
714 {
715 as_bad (_("`)' required"));
716 break;
717 }
718 input_line_pointer++;
719 }
720 while (closes--);
721
722 reloc_to_return =
723 neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
724 if (linker_stubs_should_be_generated)
725 {
726 switch (reloc_to_return)
727 {
728 case BFD_RELOC_AVR_LO8_LDI_PM:
729 reloc_to_return = BFD_RELOC_AVR_LO8_LDI_GS;
730 break;
731 case BFD_RELOC_AVR_HI8_LDI_PM:
732 reloc_to_return = BFD_RELOC_AVR_HI8_LDI_GS;
733 break;
734
735 default:
736 /* PR 5523: Do not generate a warning here,
737 legitimate code can trigger this case. */
738 break;
739 }
740 }
741 return reloc_to_return;
742 }
743 }
744 }
745
746 input_line_pointer = tmp;
747 expression (exp);
748
749 /* Warn about expressions that fail to use lo8 (). */
750 if (exp->X_op == O_constant)
751 {
752 int x = exp->X_add_number;
753
754 if (x < -255 || x > 255)
755 as_warn (_("constant out of 8-bit range: %d"), x);
756 }
757
758 return BFD_RELOC_AVR_LDI;
759 }
760
761 /* Parse one instruction operand.
762 Return operand bitmask. Also fixups can be generated. */
763
764 static unsigned int
765 avr_operand (struct avr_opcodes_s *opcode,
766 int where,
767 char *op,
768 char **line)
769 {
770 expressionS op_expr;
771 unsigned int op_mask = 0;
772 char *str = skip_space (*line);
773
774 switch (*op)
775 {
776 /* Any register operand. */
777 case 'w':
778 case 'd':
779 case 'r':
780 case 'a':
781 case 'v':
782 if (*str == 'r' || *str == 'R')
783 {
784 char r_name[20];
785
786 str = extract_word (str, r_name, sizeof (r_name));
787 op_mask = 0xff;
788 if (ISDIGIT (r_name[1]))
789 {
790 if (r_name[2] == '\0')
791 op_mask = r_name[1] - '0';
792 else if (r_name[1] != '0'
793 && ISDIGIT (r_name[2])
794 && r_name[3] == '\0')
795 op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0';
796 }
797 }
798 else
799 {
800 op_mask = avr_get_constant (str, 31);
801 str = input_line_pointer;
802 }
803
804 if (op_mask <= 31)
805 {
806 switch (*op)
807 {
808 case 'a':
809 if (op_mask < 16 || op_mask > 23)
810 as_bad (_("register r16-r23 required"));
811 op_mask -= 16;
812 break;
813
814 case 'd':
815 if (op_mask < 16)
816 as_bad (_("register number above 15 required"));
817 op_mask -= 16;
818 break;
819
820 case 'v':
821 if (op_mask & 1)
822 as_bad (_("even register number required"));
823 op_mask >>= 1;
824 break;
825
826 case 'w':
827 if ((op_mask & 1) || op_mask < 24)
828 as_bad (_("register r24, r26, r28 or r30 required"));
829 op_mask = (op_mask - 24) >> 1;
830 break;
831 }
832 break;
833 }
834 as_bad (_("register name or number from 0 to 31 required"));
835 break;
836
837 case 'e':
838 {
839 char c;
840
841 if (*str == '-')
842 {
843 str = skip_space (str + 1);
844 op_mask = 0x1002;
845 }
846 c = TOLOWER (*str);
847 if (c == 'x')
848 op_mask |= 0x100c;
849 else if (c == 'y')
850 op_mask |= 0x8;
851 else if (c != 'z')
852 as_bad (_("pointer register (X, Y or Z) required"));
853
854 str = skip_space (str + 1);
855 if (*str == '+')
856 {
857 ++str;
858 if (op_mask & 2)
859 as_bad (_("cannot both predecrement and postincrement"));
860 op_mask |= 0x1001;
861 }
862
863 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
864 registers, no predecrement, no postincrement. */
865 if (!avr_opt.all_opcodes && (op_mask & 0x100F)
866 && !(avr_mcu->isa & AVR_ISA_SRAM))
867 as_bad (_("addressing mode not supported"));
868 }
869 break;
870
871 case 'z':
872 if (*str == '-')
873 as_bad (_("can't predecrement"));
874
875 if (! (*str == 'z' || *str == 'Z'))
876 as_bad (_("pointer register Z required"));
877
878 str = skip_space (str + 1);
879
880 if (*str == '+')
881 {
882 ++str;
883 char *s;
884 for (s = opcode->opcode; *s; ++s)
885 {
886 if (*s == '+')
887 op_mask |= (1 << (15 - (s - opcode->opcode)));
888 }
889 }
890
891 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
892 if (!avr_opt.all_opcodes
893 && (op_mask & 0x0001)
894 && !(avr_mcu->isa & AVR_ISA_MOVW))
895 as_bad (_("postincrement not supported"));
896 break;
897
898 case 'b':
899 {
900 char c = TOLOWER (*str++);
901
902 if (c == 'y')
903 op_mask |= 0x8;
904 else if (c != 'z')
905 as_bad (_("pointer register (Y or Z) required"));
906 str = skip_space (str);
907 if (*str++ == '+')
908 {
909 input_line_pointer = str;
910 avr_offset_expression (& op_expr);
911 str = input_line_pointer;
912 fix_new_exp (frag_now, where, 3,
913 &op_expr, FALSE, BFD_RELOC_AVR_6);
914 }
915 }
916 break;
917
918 case 'h':
919 str = parse_exp (str, &op_expr);
920 fix_new_exp (frag_now, where, opcode->insn_size * 2,
921 &op_expr, FALSE, BFD_RELOC_AVR_CALL);
922 break;
923
924 case 'L':
925 str = parse_exp (str, &op_expr);
926 fix_new_exp (frag_now, where, opcode->insn_size * 2,
927 &op_expr, TRUE, BFD_RELOC_AVR_13_PCREL);
928 break;
929
930 case 'l':
931 str = parse_exp (str, &op_expr);
932 fix_new_exp (frag_now, where, opcode->insn_size * 2,
933 &op_expr, TRUE, BFD_RELOC_AVR_7_PCREL);
934 break;
935
936 case 'i':
937 str = parse_exp (str, &op_expr);
938 fix_new_exp (frag_now, where + 2, opcode->insn_size * 2,
939 &op_expr, FALSE, BFD_RELOC_16);
940 break;
941
942 case 'M':
943 {
944 bfd_reloc_code_real_type r_type;
945
946 input_line_pointer = str;
947 r_type = avr_ldi_expression (&op_expr);
948 str = input_line_pointer;
949 fix_new_exp (frag_now, where, 3,
950 &op_expr, FALSE, r_type);
951 }
952 break;
953
954 case 'n':
955 {
956 unsigned int x;
957
958 x = ~avr_get_constant (str, 255);
959 str = input_line_pointer;
960 op_mask |= (x & 0xf) | ((x << 4) & 0xf00);
961 }
962 break;
963
964 case 'K':
965 input_line_pointer = str;
966 avr_offset_expression (& op_expr);
967 str = input_line_pointer;
968 fix_new_exp (frag_now, where, 3,
969 & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
970 break;
971
972 case 'S':
973 case 's':
974 {
975 unsigned int x;
976
977 x = avr_get_constant (str, 7);
978 str = input_line_pointer;
979 if (*op == 'S')
980 x <<= 4;
981 op_mask |= x;
982 }
983 break;
984
985 case 'P':
986 {
987 unsigned int x;
988
989 x = avr_get_constant (str, 63);
990 str = input_line_pointer;
991 op_mask |= (x & 0xf) | ((x & 0x30) << 5);
992 }
993 break;
994
995 case 'p':
996 {
997 unsigned int x;
998
999 x = avr_get_constant (str, 31);
1000 str = input_line_pointer;
1001 op_mask |= x << 3;
1002 }
1003 break;
1004
1005 case 'E':
1006 {
1007 unsigned int x;
1008
1009 x = avr_get_constant (str, 15);
1010 str = input_line_pointer;
1011 op_mask |= (x << 4);
1012 }
1013 break;
1014
1015 case '?':
1016 break;
1017
1018 default:
1019 as_bad (_("unknown constraint `%c'"), *op);
1020 }
1021
1022 *line = str;
1023 return op_mask;
1024 }
1025
1026 /* Parse instruction operands.
1027 Return binary opcode. */
1028
1029 static unsigned int
1030 avr_operands (struct avr_opcodes_s *opcode, char **line)
1031 {
1032 char *op = opcode->constraints;
1033 unsigned int bin = opcode->bin_opcode;
1034 char *frag = frag_more (opcode->insn_size * 2);
1035 char *str = *line;
1036 int where = frag - frag_now->fr_literal;
1037 static unsigned int prev = 0; /* Previous opcode. */
1038
1039 /* Opcode have operands. */
1040 if (*op)
1041 {
1042 unsigned int reg1 = 0;
1043 unsigned int reg2 = 0;
1044 int reg1_present = 0;
1045 int reg2_present = 0;
1046
1047 /* Parse first operand. */
1048 if (REGISTER_P (*op))
1049 reg1_present = 1;
1050 reg1 = avr_operand (opcode, where, op, &str);
1051 ++op;
1052
1053 /* Parse second operand. */
1054 if (*op)
1055 {
1056 if (*op == ',')
1057 ++op;
1058
1059 if (*op == '=')
1060 {
1061 reg2 = reg1;
1062 reg2_present = 1;
1063 }
1064 else
1065 {
1066 if (REGISTER_P (*op))
1067 reg2_present = 1;
1068
1069 str = skip_space (str);
1070 if (*str++ != ',')
1071 as_bad (_("`,' required"));
1072 str = skip_space (str);
1073
1074 reg2 = avr_operand (opcode, where, op, &str);
1075 }
1076
1077 if (reg1_present && reg2_present)
1078 reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200);
1079 else if (reg2_present)
1080 reg2 <<= 4;
1081 }
1082 if (reg1_present)
1083 reg1 <<= 4;
1084 bin |= reg1 | reg2;
1085 }
1086
1087 /* Detect undefined combinations (like ld r31,Z+). */
1088 if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin))
1089 as_warn (_("undefined combination of operands"));
1090
1091 if (opcode->insn_size == 2)
1092 {
1093 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1094 (AVR core bug, fixed in the newer devices). */
1095 if (!(avr_opt.no_skip_bug ||
1096 (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW)))
1097 && AVR_SKIP_P (prev))
1098 as_warn (_("skipping two-word instruction"));
1099
1100 bfd_putl32 ((bfd_vma) bin, frag);
1101 }
1102 else
1103 bfd_putl16 ((bfd_vma) bin, frag);
1104
1105 prev = bin;
1106 *line = str;
1107 return bin;
1108 }
1109
1110 /* GAS will call this function for each section at the end of the assembly,
1111 to permit the CPU backend to adjust the alignment of a section. */
1112
1113 valueT
1114 md_section_align (asection *seg, valueT addr)
1115 {
1116 int align = bfd_get_section_alignment (stdoutput, seg);
1117 return ((addr + (1 << align) - 1) & (-1 << align));
1118 }
1119
1120 /* If you define this macro, it should return the offset between the
1121 address of a PC relative fixup and the position from which the PC
1122 relative adjustment should be made. On many processors, the base
1123 of a PC relative instruction is the next instruction, so this
1124 macro would return the length of an instruction. */
1125
1126 long
1127 md_pcrel_from_section (fixS *fixp, segT sec)
1128 {
1129 if (fixp->fx_addsy != (symbolS *) NULL
1130 && (!S_IS_DEFINED (fixp->fx_addsy)
1131 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1132 return 0;
1133
1134 return fixp->fx_frag->fr_address + fixp->fx_where;
1135 }
1136
1137 /* GAS will call this for each fixup. It should store the correct
1138 value in the object file. */
1139
1140 void
1141 md_apply_fix (fixS *fixP, valueT * valP, segT seg)
1142 {
1143 unsigned char *where;
1144 unsigned long insn;
1145 long value = *valP;
1146
1147 if (fixP->fx_addsy == (symbolS *) NULL)
1148 fixP->fx_done = 1;
1149
1150 else if (fixP->fx_pcrel)
1151 {
1152 segT s = S_GET_SEGMENT (fixP->fx_addsy);
1153
1154 if (s == seg || s == absolute_section)
1155 {
1156 value += S_GET_VALUE (fixP->fx_addsy);
1157 fixP->fx_done = 1;
1158 }
1159 }
1160
1161 /* We don't actually support subtracting a symbol. */
1162 if (fixP->fx_subsy != (symbolS *) NULL)
1163 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1164
1165 switch (fixP->fx_r_type)
1166 {
1167 default:
1168 fixP->fx_no_overflow = 1;
1169 break;
1170 case BFD_RELOC_AVR_7_PCREL:
1171 case BFD_RELOC_AVR_13_PCREL:
1172 case BFD_RELOC_32:
1173 case BFD_RELOC_16:
1174 case BFD_RELOC_AVR_CALL:
1175 break;
1176 }
1177
1178 if (fixP->fx_done)
1179 {
1180 /* Fetch the instruction, insert the fully resolved operand
1181 value, and stuff the instruction back again. */
1182 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1183 insn = bfd_getl16 (where);
1184
1185 switch (fixP->fx_r_type)
1186 {
1187 case BFD_RELOC_AVR_7_PCREL:
1188 if (value & 1)
1189 as_bad_where (fixP->fx_file, fixP->fx_line,
1190 _("odd address operand: %ld"), value);
1191
1192 /* Instruction addresses are always right-shifted by 1. */
1193 value >>= 1;
1194 --value; /* Correct PC. */
1195
1196 if (value < -64 || value > 63)
1197 as_bad_where (fixP->fx_file, fixP->fx_line,
1198 _("operand out of range: %ld"), value);
1199 value = (value << 3) & 0x3f8;
1200 bfd_putl16 ((bfd_vma) (value | insn), where);
1201 break;
1202
1203 case BFD_RELOC_AVR_13_PCREL:
1204 if (value & 1)
1205 as_bad_where (fixP->fx_file, fixP->fx_line,
1206 _("odd address operand: %ld"), value);
1207
1208 /* Instruction addresses are always right-shifted by 1. */
1209 value >>= 1;
1210 --value; /* Correct PC. */
1211
1212 if (value < -2048 || value > 2047)
1213 {
1214 /* No wrap for devices with >8K of program memory. */
1215 if ((avr_mcu->isa & AVR_ISA_MEGA) || avr_opt.no_wrap)
1216 as_bad_where (fixP->fx_file, fixP->fx_line,
1217 _("operand out of range: %ld"), value);
1218 }
1219
1220 value &= 0xfff;
1221 bfd_putl16 ((bfd_vma) (value | insn), where);
1222 break;
1223
1224 case BFD_RELOC_32:
1225 bfd_putl16 ((bfd_vma) value, where);
1226 break;
1227
1228 case BFD_RELOC_16:
1229 bfd_putl16 ((bfd_vma) value, where);
1230 break;
1231
1232 case BFD_RELOC_8:
1233 if (value > 255 || value < -128)
1234 as_warn_where (fixP->fx_file, fixP->fx_line,
1235 _("operand out of range: %ld"), value);
1236 *where = value;
1237 break;
1238
1239 case BFD_RELOC_AVR_16_PM:
1240 bfd_putl16 ((bfd_vma) (value >> 1), where);
1241 break;
1242
1243 case BFD_RELOC_AVR_LDI:
1244 if (value > 255)
1245 as_bad_where (fixP->fx_file, fixP->fx_line,
1246 _("operand out of range: %ld"), value);
1247 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1248 break;
1249
1250 case BFD_RELOC_AVR_6:
1251 if ((value > 63) || (value < 0))
1252 as_bad_where (fixP->fx_file, fixP->fx_line,
1253 _("operand out of range: %ld"), value);
1254 bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7) | ((value & (1 << 5)) << 8)), where);
1255 break;
1256
1257 case BFD_RELOC_AVR_6_ADIW:
1258 if ((value > 63) || (value < 0))
1259 as_bad_where (fixP->fx_file, fixP->fx_line,
1260 _("operand out of range: %ld"), value);
1261 bfd_putl16 ((bfd_vma) insn | (value & 0xf) | ((value & 0x30) << 2), where);
1262 break;
1263
1264 case BFD_RELOC_AVR_LO8_LDI:
1265 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1266 break;
1267
1268 case BFD_RELOC_AVR_HI8_LDI:
1269 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 8), where);
1270 break;
1271
1272 case BFD_RELOC_AVR_MS8_LDI:
1273 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 24), where);
1274 break;
1275
1276 case BFD_RELOC_AVR_HH8_LDI:
1277 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 16), where);
1278 break;
1279
1280 case BFD_RELOC_AVR_LO8_LDI_NEG:
1281 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value), where);
1282 break;
1283
1284 case BFD_RELOC_AVR_HI8_LDI_NEG:
1285 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 8), where);
1286 break;
1287
1288 case BFD_RELOC_AVR_MS8_LDI_NEG:
1289 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 24), where);
1290 break;
1291
1292 case BFD_RELOC_AVR_HH8_LDI_NEG:
1293 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 16), where);
1294 break;
1295
1296 case BFD_RELOC_AVR_LO8_LDI_PM:
1297 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 1), where);
1298 break;
1299
1300 case BFD_RELOC_AVR_HI8_LDI_PM:
1301 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 9), where);
1302 break;
1303
1304 case BFD_RELOC_AVR_HH8_LDI_PM:
1305 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 17), where);
1306 break;
1307
1308 case BFD_RELOC_AVR_LO8_LDI_PM_NEG:
1309 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 1), where);
1310 break;
1311
1312 case BFD_RELOC_AVR_HI8_LDI_PM_NEG:
1313 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 9), where);
1314 break;
1315
1316 case BFD_RELOC_AVR_HH8_LDI_PM_NEG:
1317 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 17), where);
1318 break;
1319
1320 case BFD_RELOC_AVR_CALL:
1321 {
1322 unsigned long x;
1323
1324 x = bfd_getl16 (where);
1325 if (value & 1)
1326 as_bad_where (fixP->fx_file, fixP->fx_line,
1327 _("odd address operand: %ld"), value);
1328 value >>= 1;
1329 x |= ((value & 0x10000) | ((value << 3) & 0x1f00000)) >> 16;
1330 bfd_putl16 ((bfd_vma) x, where);
1331 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
1332 }
1333 break;
1334
1335 default:
1336 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1337 fixP->fx_line, fixP->fx_r_type);
1338 break;
1339 }
1340 }
1341 else
1342 {
1343 switch ((int) fixP->fx_r_type)
1344 {
1345 case -BFD_RELOC_AVR_HI8_LDI_NEG:
1346 case -BFD_RELOC_AVR_HI8_LDI:
1347 case -BFD_RELOC_AVR_LO8_LDI_NEG:
1348 case -BFD_RELOC_AVR_LO8_LDI:
1349 as_bad_where (fixP->fx_file, fixP->fx_line,
1350 _("only constant expression allowed"));
1351 fixP->fx_done = 1;
1352 break;
1353 default:
1354 break;
1355 }
1356 }
1357 }
1358
1359 /* GAS will call this to generate a reloc, passing the resulting reloc
1360 to `bfd_install_relocation'. This currently works poorly, as
1361 `bfd_install_relocation' often does the wrong thing, and instances of
1362 `tc_gen_reloc' have been written to work around the problems, which
1363 in turns makes it difficult to fix `bfd_install_relocation'. */
1364
1365 /* If while processing a fixup, a reloc really needs to be created
1366 then it is done here. */
1367
1368 arelent *
1369 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED,
1370 fixS *fixp)
1371 {
1372 arelent *reloc;
1373
1374 if (fixp->fx_addsy && fixp->fx_subsy)
1375 {
1376 long value = 0;
1377
1378 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy))
1379 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section)
1380 {
1381 as_bad_where (fixp->fx_file, fixp->fx_line,
1382 "Difference of symbols in different sections is not supported");
1383 return NULL;
1384 }
1385
1386 /* We are dealing with two symbols defined in the same section.
1387 Let us fix-up them here. */
1388 value += S_GET_VALUE (fixp->fx_addsy);
1389 value -= S_GET_VALUE (fixp->fx_subsy);
1390
1391 /* When fx_addsy and fx_subsy both are zero, md_apply_fix
1392 only takes it's second operands for the fixup value. */
1393 fixp->fx_addsy = NULL;
1394 fixp->fx_subsy = NULL;
1395 md_apply_fix (fixp, (valueT *) &value, NULL);
1396
1397 return NULL;
1398 }
1399
1400 reloc = xmalloc (sizeof (arelent));
1401
1402 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1403 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1404
1405 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1406 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1407 if (reloc->howto == (reloc_howto_type *) NULL)
1408 {
1409 as_bad_where (fixp->fx_file, fixp->fx_line,
1410 _("reloc %d not supported by object file format"),
1411 (int) fixp->fx_r_type);
1412 return NULL;
1413 }
1414
1415 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1416 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1417 reloc->address = fixp->fx_offset;
1418
1419 reloc->addend = fixp->fx_offset;
1420
1421 return reloc;
1422 }
1423
1424 void
1425 md_assemble (char *str)
1426 {
1427 struct avr_opcodes_s *opcode;
1428 char op[11];
1429
1430 str = skip_space (extract_word (str, op, sizeof (op)));
1431
1432 if (!op[0])
1433 as_bad (_("can't find opcode "));
1434
1435 opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op);
1436
1437 if (opcode == NULL)
1438 {
1439 as_bad (_("unknown opcode `%s'"), op);
1440 return;
1441 }
1442
1443 /* Special case for opcodes with optional operands (lpm, elpm) -
1444 version with operands exists in avr_opcodes[] in the next entry. */
1445
1446 if (*str && *opcode->constraints == '?')
1447 ++opcode;
1448
1449 if (!avr_opt.all_opcodes && (opcode->isa & avr_mcu->isa) != opcode->isa)
1450 as_bad (_("illegal opcode %s for mcu %s"), opcode->name, avr_mcu->name);
1451
1452 dwarf2_emit_insn (0);
1453
1454 /* We used to set input_line_pointer to the result of get_operands,
1455 but that is wrong. Our caller assumes we don't change it. */
1456 {
1457 char *t = input_line_pointer;
1458
1459 avr_operands (opcode, &str);
1460 if (*skip_space (str))
1461 as_bad (_("garbage at end of line"));
1462 input_line_pointer = t;
1463 }
1464 }
1465
1466 /* Flag to pass `pm' mode between `avr_parse_cons_expression' and
1467 `avr_cons_fix_new'. */
1468 static int exp_mod_pm = 0;
1469
1470 /* Parse special CONS expression: pm (expression)
1471 or alternatively: gs (expression).
1472 These are used for addressing program memory.
1473 Relocation: BFD_RELOC_AVR_16_PM. */
1474
1475 void
1476 avr_parse_cons_expression (expressionS *exp, int nbytes)
1477 {
1478 char *tmp;
1479
1480 exp_mod_pm = 0;
1481
1482 tmp = input_line_pointer = skip_space (input_line_pointer);
1483
1484 if (nbytes == 2)
1485 {
1486 char *pm_name1 = "pm";
1487 char *pm_name2 = "gs";
1488 int len = strlen (pm_name1);
1489 /* len must be the same for both pm identifiers. */
1490
1491 if (strncasecmp (input_line_pointer, pm_name1, len) == 0
1492 || strncasecmp (input_line_pointer, pm_name2, len) == 0)
1493 {
1494 input_line_pointer = skip_space (input_line_pointer + len);
1495
1496 if (*input_line_pointer == '(')
1497 {
1498 input_line_pointer = skip_space (input_line_pointer + 1);
1499 exp_mod_pm = 1;
1500 expression (exp);
1501
1502 if (*input_line_pointer == ')')
1503 ++input_line_pointer;
1504 else
1505 {
1506 as_bad (_("`)' required"));
1507 exp_mod_pm = 0;
1508 }
1509
1510 return;
1511 }
1512
1513 input_line_pointer = tmp;
1514 }
1515 }
1516
1517 expression (exp);
1518 }
1519
1520 void
1521 avr_cons_fix_new (fragS *frag,
1522 int where,
1523 int nbytes,
1524 expressionS *exp)
1525 {
1526 if (exp_mod_pm == 0)
1527 {
1528 if (nbytes == 1)
1529 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8);
1530 else if (nbytes == 2)
1531 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16);
1532 else if (nbytes == 4)
1533 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32);
1534 else
1535 as_bad (_("illegal %srelocation size: %d"), "", nbytes);
1536 }
1537 else
1538 {
1539 if (nbytes == 2)
1540 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_AVR_16_PM);
1541 else
1542 as_bad (_("illegal %srelocation size: %d"), "`pm' ", nbytes);
1543 exp_mod_pm = 0;
1544 }
1545 }
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