1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 /* Allow override of standard little-endian ECOFF format. */
106 #ifndef ECOFF_LITTLE_FORMAT
107 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
115 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
121 /* Information about an instruction, including its format, operands
125 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
126 const struct mips_opcode
*insn_mo
;
128 /* True if this is a mips16 instruction and if we want the extended
130 bfd_boolean use_extend
;
132 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
133 unsigned short extend
;
135 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
136 a copy of INSN_MO->match with the operands filled in. */
137 unsigned long insn_opcode
;
139 /* The frag that contains the instruction. */
142 /* The offset into FRAG of the first instruction byte. */
145 /* The relocs associated with the instruction, if any. */
148 /* True if this entry cannot be moved from its current position. */
149 unsigned int fixed_p
: 1;
151 /* True if this instruction occurred in a .set noreorder block. */
152 unsigned int noreorder_p
: 1;
154 /* True for mips16 instructions that jump to an absolute address. */
155 unsigned int mips16_absolute_jump_p
: 1;
158 /* The ABI to use. */
169 /* MIPS ABI we are using for this output file. */
170 static enum mips_abi_level mips_abi
= NO_ABI
;
172 /* Whether or not we have code that can call pic code. */
173 int mips_abicalls
= FALSE
;
175 /* Whether or not we have code which can be put into a shared
177 static bfd_boolean mips_in_shared
= TRUE
;
179 /* This is the set of options which may be modified by the .set
180 pseudo-op. We use a struct so that .set push and .set pop are more
183 struct mips_set_options
185 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
186 if it has not been initialized. Changed by `.set mipsN', and the
187 -mipsN command line option, and the default CPU. */
189 /* Enabled Application Specific Extensions (ASEs). These are set to -1
190 if they have not been initialized. Changed by `.set <asename>', by
191 command line options, and based on the default architecture. */
197 /* Whether we are assembling for the mips16 processor. 0 if we are
198 not, 1 if we are, and -1 if the value has not been initialized.
199 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
200 -nomips16 command line options, and the default CPU. */
202 /* Non-zero if we should not reorder instructions. Changed by `.set
203 reorder' and `.set noreorder'. */
205 /* Non-zero if we should not permit the $at ($1) register to be used
206 in instructions. Changed by `.set at' and `.set noat'. */
208 /* Non-zero if we should warn when a macro instruction expands into
209 more than one machine instruction. Changed by `.set nomacro' and
211 int warn_about_macros
;
212 /* Non-zero if we should not move instructions. Changed by `.set
213 move', `.set volatile', `.set nomove', and `.set novolatile'. */
215 /* Non-zero if we should not optimize branches by moving the target
216 of the branch into the delay slot. Actually, we don't perform
217 this optimization anyhow. Changed by `.set bopt' and `.set
220 /* Non-zero if we should not autoextend mips16 instructions.
221 Changed by `.set autoextend' and `.set noautoextend'. */
223 /* Restrict general purpose registers and floating point registers
224 to 32 bit. This is initially determined when -mgp32 or -mfp32
225 is passed but can changed if the assembler code uses .set mipsN. */
228 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
229 command line option, and the default CPU. */
231 /* True if ".set sym32" is in effect. */
235 /* True if -mgp32 was passed. */
236 static int file_mips_gp32
= -1;
238 /* True if -mfp32 was passed. */
239 static int file_mips_fp32
= -1;
241 /* This is the struct we use to hold the current set of options. Note
242 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
243 -1 to indicate that they have not been initialized. */
245 static struct mips_set_options mips_opts
=
247 ISA_UNKNOWN
, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
250 /* These variables are filled in with the masks of registers used.
251 The object format code reads them and puts them in the appropriate
253 unsigned long mips_gprmask
;
254 unsigned long mips_cprmask
[4];
256 /* MIPS ISA we are using for this output file. */
257 static int file_mips_isa
= ISA_UNKNOWN
;
259 /* True if -mips16 was passed or implied by arguments passed on the
260 command line (e.g., by -march). */
261 static int file_ase_mips16
;
263 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
264 || mips_opts.isa == ISA_MIPS32R2 \
265 || mips_opts.isa == ISA_MIPS64 \
266 || mips_opts.isa == ISA_MIPS64R2)
268 /* True if -mips3d was passed or implied by arguments passed on the
269 command line (e.g., by -march). */
270 static int file_ase_mips3d
;
272 /* True if -mdmx was passed or implied by arguments passed on the
273 command line (e.g., by -march). */
274 static int file_ase_mdmx
;
276 /* True if -msmartmips was passed or implied by arguments passed on the
277 command line (e.g., by -march). */
278 static int file_ase_smartmips
;
280 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
281 || mips_opts.isa == ISA_MIPS32R2)
283 /* True if -mdsp was passed or implied by arguments passed on the
284 command line (e.g., by -march). */
285 static int file_ase_dsp
;
287 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
288 || mips_opts.isa == ISA_MIPS64R2)
290 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
292 /* True if -mmt was passed or implied by arguments passed on the
293 command line (e.g., by -march). */
294 static int file_ase_mt
;
296 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
297 || mips_opts.isa == ISA_MIPS64R2)
299 /* The argument of the -march= flag. The architecture we are assembling. */
300 static int file_mips_arch
= CPU_UNKNOWN
;
301 static const char *mips_arch_string
;
303 /* The argument of the -mtune= flag. The architecture for which we
305 static int mips_tune
= CPU_UNKNOWN
;
306 static const char *mips_tune_string
;
308 /* True when generating 32-bit code for a 64-bit processor. */
309 static int mips_32bitmode
= 0;
311 /* True if the given ABI requires 32-bit registers. */
312 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
314 /* Likewise 64-bit registers. */
315 #define ABI_NEEDS_64BIT_REGS(ABI) \
317 || (ABI) == N64_ABI \
320 /* Return true if ISA supports 64 bit wide gp registers. */
321 #define ISA_HAS_64BIT_REGS(ISA) \
322 ((ISA) == ISA_MIPS3 \
323 || (ISA) == ISA_MIPS4 \
324 || (ISA) == ISA_MIPS5 \
325 || (ISA) == ISA_MIPS64 \
326 || (ISA) == ISA_MIPS64R2)
328 /* Return true if ISA supports 64 bit wide float registers. */
329 #define ISA_HAS_64BIT_FPRS(ISA) \
330 ((ISA) == ISA_MIPS3 \
331 || (ISA) == ISA_MIPS4 \
332 || (ISA) == ISA_MIPS5 \
333 || (ISA) == ISA_MIPS32R2 \
334 || (ISA) == ISA_MIPS64 \
335 || (ISA) == ISA_MIPS64R2)
337 /* Return true if ISA supports 64-bit right rotate (dror et al.)
339 #define ISA_HAS_DROR(ISA) \
340 ((ISA) == ISA_MIPS64R2)
342 /* Return true if ISA supports 32-bit right rotate (ror et al.)
344 #define ISA_HAS_ROR(ISA) \
345 ((ISA) == ISA_MIPS32R2 \
346 || (ISA) == ISA_MIPS64R2 \
347 || mips_opts.ase_smartmips)
349 /* Return true if ISA supports single-precision floats in odd registers. */
350 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
351 ((ISA) == ISA_MIPS32 \
352 || (ISA) == ISA_MIPS32R2 \
353 || (ISA) == ISA_MIPS64 \
354 || (ISA) == ISA_MIPS64R2)
356 /* Return true if ISA supports move to/from high part of a 64-bit
357 floating-point register. */
358 #define ISA_HAS_MXHC1(ISA) \
359 ((ISA) == ISA_MIPS32R2 \
360 || (ISA) == ISA_MIPS64R2)
362 #define HAVE_32BIT_GPRS \
363 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
365 #define HAVE_32BIT_FPRS \
366 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
368 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
369 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
371 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
373 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
375 /* True if relocations are stored in-place. */
376 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
378 /* The ABI-derived address size. */
379 #define HAVE_64BIT_ADDRESSES \
380 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
381 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
383 /* The size of symbolic constants (i.e., expressions of the form
384 "SYMBOL" or "SYMBOL + OFFSET"). */
385 #define HAVE_32BIT_SYMBOLS \
386 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
387 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
389 /* Addresses are loaded in different ways, depending on the address size
390 in use. The n32 ABI Documentation also mandates the use of additions
391 with overflow checking, but existing implementations don't follow it. */
392 #define ADDRESS_ADD_INSN \
393 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
395 #define ADDRESS_ADDI_INSN \
396 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
398 #define ADDRESS_LOAD_INSN \
399 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
401 #define ADDRESS_STORE_INSN \
402 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
404 /* Return true if the given CPU supports the MIPS16 ASE. */
405 #define CPU_HAS_MIPS16(cpu) \
406 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
407 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
409 /* True if CPU has a dror instruction. */
410 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
412 /* True if CPU has a ror instruction. */
413 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
415 /* True if mflo and mfhi can be immediately followed by instructions
416 which write to the HI and LO registers.
418 According to MIPS specifications, MIPS ISAs I, II, and III need
419 (at least) two instructions between the reads of HI/LO and
420 instructions which write them, and later ISAs do not. Contradicting
421 the MIPS specifications, some MIPS IV processor user manuals (e.g.
422 the UM for the NEC Vr5000) document needing the instructions between
423 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
424 MIPS64 and later ISAs to have the interlocks, plus any specific
425 earlier-ISA CPUs for which CPU documentation declares that the
426 instructions are really interlocked. */
427 #define hilo_interlocks \
428 (mips_opts.isa == ISA_MIPS32 \
429 || mips_opts.isa == ISA_MIPS32R2 \
430 || mips_opts.isa == ISA_MIPS64 \
431 || mips_opts.isa == ISA_MIPS64R2 \
432 || mips_opts.arch == CPU_R4010 \
433 || mips_opts.arch == CPU_R10000 \
434 || mips_opts.arch == CPU_R12000 \
435 || mips_opts.arch == CPU_RM7000 \
436 || mips_opts.arch == CPU_VR5500 \
439 /* Whether the processor uses hardware interlocks to protect reads
440 from the GPRs after they are loaded from memory, and thus does not
441 require nops to be inserted. This applies to instructions marked
442 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
444 #define gpr_interlocks \
445 (mips_opts.isa != ISA_MIPS1 \
446 || mips_opts.arch == CPU_R3900)
448 /* Whether the processor uses hardware interlocks to avoid delays
449 required by coprocessor instructions, and thus does not require
450 nops to be inserted. This applies to instructions marked
451 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
452 between instructions marked INSN_WRITE_COND_CODE and ones marked
453 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
454 levels I, II, and III. */
455 /* Itbl support may require additional care here. */
456 #define cop_interlocks \
457 ((mips_opts.isa != ISA_MIPS1 \
458 && mips_opts.isa != ISA_MIPS2 \
459 && mips_opts.isa != ISA_MIPS3) \
460 || mips_opts.arch == CPU_R4300 \
463 /* Whether the processor uses hardware interlocks to protect reads
464 from coprocessor registers after they are loaded from memory, and
465 thus does not require nops to be inserted. This applies to
466 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
467 requires at MIPS ISA level I. */
468 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
470 /* Is this a mfhi or mflo instruction? */
471 #define MF_HILO_INSN(PINFO) \
472 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
474 /* MIPS PIC level. */
476 enum mips_pic_level mips_pic
;
478 /* 1 if we should generate 32 bit offsets from the $gp register in
479 SVR4_PIC mode. Currently has no meaning in other modes. */
480 static int mips_big_got
= 0;
482 /* 1 if trap instructions should used for overflow rather than break
484 static int mips_trap
= 0;
486 /* 1 if double width floating point constants should not be constructed
487 by assembling two single width halves into two single width floating
488 point registers which just happen to alias the double width destination
489 register. On some architectures this aliasing can be disabled by a bit
490 in the status register, and the setting of this bit cannot be determined
491 automatically at assemble time. */
492 static int mips_disable_float_construction
;
494 /* Non-zero if any .set noreorder directives were used. */
496 static int mips_any_noreorder
;
498 /* Non-zero if nops should be inserted when the register referenced in
499 an mfhi/mflo instruction is read in the next two instructions. */
500 static int mips_7000_hilo_fix
;
502 /* The size of the small data section. */
503 static unsigned int g_switch_value
= 8;
504 /* Whether the -G option was used. */
505 static int g_switch_seen
= 0;
510 /* If we can determine in advance that GP optimization won't be
511 possible, we can skip the relaxation stuff that tries to produce
512 GP-relative references. This makes delay slot optimization work
515 This function can only provide a guess, but it seems to work for
516 gcc output. It needs to guess right for gcc, otherwise gcc
517 will put what it thinks is a GP-relative instruction in a branch
520 I don't know if a fix is needed for the SVR4_PIC mode. I've only
521 fixed it for the non-PIC mode. KR 95/04/07 */
522 static int nopic_need_relax (symbolS
*, int);
524 /* handle of the OPCODE hash table */
525 static struct hash_control
*op_hash
= NULL
;
527 /* The opcode hash table we use for the mips16. */
528 static struct hash_control
*mips16_op_hash
= NULL
;
530 /* This array holds the chars that always start a comment. If the
531 pre-processor is disabled, these aren't very useful */
532 const char comment_chars
[] = "#";
534 /* This array holds the chars that only start a comment at the beginning of
535 a line. If the line seems to have the form '# 123 filename'
536 .line and .file directives will appear in the pre-processed output */
537 /* Note that input_file.c hand checks for '#' at the beginning of the
538 first line of the input file. This is because the compiler outputs
539 #NO_APP at the beginning of its output. */
540 /* Also note that C style comments are always supported. */
541 const char line_comment_chars
[] = "#";
543 /* This array holds machine specific line separator characters. */
544 const char line_separator_chars
[] = ";";
546 /* Chars that can be used to separate mant from exp in floating point nums */
547 const char EXP_CHARS
[] = "eE";
549 /* Chars that mean this number is a floating point constant */
552 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
554 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
555 changed in read.c . Ideally it shouldn't have to know about it at all,
556 but nothing is ideal around here.
559 static char *insn_error
;
561 static int auto_align
= 1;
563 /* When outputting SVR4 PIC code, the assembler needs to know the
564 offset in the stack frame from which to restore the $gp register.
565 This is set by the .cprestore pseudo-op, and saved in this
567 static offsetT mips_cprestore_offset
= -1;
569 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
570 more optimizations, it can use a register value instead of a memory-saved
571 offset and even an other register than $gp as global pointer. */
572 static offsetT mips_cpreturn_offset
= -1;
573 static int mips_cpreturn_register
= -1;
574 static int mips_gp_register
= GP
;
575 static int mips_gprel_offset
= 0;
577 /* Whether mips_cprestore_offset has been set in the current function
578 (or whether it has already been warned about, if not). */
579 static int mips_cprestore_valid
= 0;
581 /* This is the register which holds the stack frame, as set by the
582 .frame pseudo-op. This is needed to implement .cprestore. */
583 static int mips_frame_reg
= SP
;
585 /* Whether mips_frame_reg has been set in the current function
586 (or whether it has already been warned about, if not). */
587 static int mips_frame_reg_valid
= 0;
589 /* To output NOP instructions correctly, we need to keep information
590 about the previous two instructions. */
592 /* Whether we are optimizing. The default value of 2 means to remove
593 unneeded NOPs and swap branch instructions when possible. A value
594 of 1 means to not swap branches. A value of 0 means to always
596 static int mips_optimize
= 2;
598 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
599 equivalent to seeing no -g option at all. */
600 static int mips_debug
= 0;
602 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
603 #define MAX_VR4130_NOPS 4
605 /* The maximum number of NOPs needed to fill delay slots. */
606 #define MAX_DELAY_NOPS 2
608 /* The maximum number of NOPs needed for any purpose. */
611 /* A list of previous instructions, with index 0 being the most recent.
612 We need to look back MAX_NOPS instructions when filling delay slots
613 or working around processor errata. We need to look back one
614 instruction further if we're thinking about using history[0] to
615 fill a branch delay slot. */
616 static struct mips_cl_insn history
[1 + MAX_NOPS
];
618 /* Nop instructions used by emit_nop. */
619 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
621 /* The appropriate nop for the current mode. */
622 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
624 /* If this is set, it points to a frag holding nop instructions which
625 were inserted before the start of a noreorder section. If those
626 nops turn out to be unnecessary, the size of the frag can be
628 static fragS
*prev_nop_frag
;
630 /* The number of nop instructions we created in prev_nop_frag. */
631 static int prev_nop_frag_holds
;
633 /* The number of nop instructions that we know we need in
635 static int prev_nop_frag_required
;
637 /* The number of instructions we've seen since prev_nop_frag. */
638 static int prev_nop_frag_since
;
640 /* For ECOFF and ELF, relocations against symbols are done in two
641 parts, with a HI relocation and a LO relocation. Each relocation
642 has only 16 bits of space to store an addend. This means that in
643 order for the linker to handle carries correctly, it must be able
644 to locate both the HI and the LO relocation. This means that the
645 relocations must appear in order in the relocation table.
647 In order to implement this, we keep track of each unmatched HI
648 relocation. We then sort them so that they immediately precede the
649 corresponding LO relocation. */
654 struct mips_hi_fixup
*next
;
657 /* The section this fixup is in. */
661 /* The list of unmatched HI relocs. */
663 static struct mips_hi_fixup
*mips_hi_fixup_list
;
665 /* The frag containing the last explicit relocation operator.
666 Null if explicit relocations have not been used. */
668 static fragS
*prev_reloc_op_frag
;
670 /* Map normal MIPS register numbers to mips16 register numbers. */
672 #define X ILLEGAL_REG
673 static const int mips32_to_16_reg_map
[] =
675 X
, X
, 2, 3, 4, 5, 6, 7,
676 X
, X
, X
, X
, X
, X
, X
, X
,
677 0, 1, X
, X
, X
, X
, X
, X
,
678 X
, X
, X
, X
, X
, X
, X
, X
682 /* Map mips16 register numbers to normal MIPS register numbers. */
684 static const unsigned int mips16_to_32_reg_map
[] =
686 16, 17, 2, 3, 4, 5, 6, 7
689 /* Classifies the kind of instructions we're interested in when
690 implementing -mfix-vr4120. */
691 enum fix_vr4120_class
{
698 NUM_FIX_VR4120_CLASSES
701 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
702 there must be at least one other instruction between an instruction
703 of type X and an instruction of type Y. */
704 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
706 /* True if -mfix-vr4120 is in force. */
707 static int mips_fix_vr4120
;
709 /* ...likewise -mfix-vr4130. */
710 static int mips_fix_vr4130
;
712 /* We don't relax branches by default, since this causes us to expand
713 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
714 fail to compute the offset before expanding the macro to the most
715 efficient expansion. */
717 static int mips_relax_branch
;
719 /* The expansion of many macros depends on the type of symbol that
720 they refer to. For example, when generating position-dependent code,
721 a macro that refers to a symbol may have two different expansions,
722 one which uses GP-relative addresses and one which uses absolute
723 addresses. When generating SVR4-style PIC, a macro may have
724 different expansions for local and global symbols.
726 We handle these situations by generating both sequences and putting
727 them in variant frags. In position-dependent code, the first sequence
728 will be the GP-relative one and the second sequence will be the
729 absolute one. In SVR4 PIC, the first sequence will be for global
730 symbols and the second will be for local symbols.
732 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
733 SECOND are the lengths of the two sequences in bytes. These fields
734 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
735 the subtype has the following flags:
738 Set if it has been decided that we should use the second
739 sequence instead of the first.
742 Set in the first variant frag if the macro's second implementation
743 is longer than its first. This refers to the macro as a whole,
744 not an individual relaxation.
747 Set in the first variant frag if the macro appeared in a .set nomacro
748 block and if one alternative requires a warning but the other does not.
751 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
754 The frag's "opcode" points to the first fixup for relaxable code.
756 Relaxable macros are generated using a sequence such as:
758 relax_start (SYMBOL);
759 ... generate first expansion ...
761 ... generate second expansion ...
764 The code and fixups for the unwanted alternative are discarded
765 by md_convert_frag. */
766 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
768 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
769 #define RELAX_SECOND(X) ((X) & 0xff)
770 #define RELAX_USE_SECOND 0x10000
771 #define RELAX_SECOND_LONGER 0x20000
772 #define RELAX_NOMACRO 0x40000
773 #define RELAX_DELAY_SLOT 0x80000
775 /* Branch without likely bit. If label is out of range, we turn:
777 beq reg1, reg2, label
787 with the following opcode replacements:
794 bltzal <-> bgezal (with jal label instead of j label)
796 Even though keeping the delay slot instruction in the delay slot of
797 the branch would be more efficient, it would be very tricky to do
798 correctly, because we'd have to introduce a variable frag *after*
799 the delay slot instruction, and expand that instead. Let's do it
800 the easy way for now, even if the branch-not-taken case now costs
801 one additional instruction. Out-of-range branches are not supposed
802 to be common, anyway.
804 Branch likely. If label is out of range, we turn:
806 beql reg1, reg2, label
807 delay slot (annulled if branch not taken)
816 delay slot (executed only if branch taken)
819 It would be possible to generate a shorter sequence by losing the
820 likely bit, generating something like:
825 delay slot (executed only if branch taken)
837 bltzall -> bgezal (with jal label instead of j label)
838 bgezall -> bltzal (ditto)
841 but it's not clear that it would actually improve performance. */
842 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
845 | ((toofar) ? 1 : 0) \
847 | ((likely) ? 4 : 0) \
848 | ((uncond) ? 8 : 0)))
849 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
850 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
851 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
852 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
853 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
855 /* For mips16 code, we use an entirely different form of relaxation.
856 mips16 supports two versions of most instructions which take
857 immediate values: a small one which takes some small value, and a
858 larger one which takes a 16 bit value. Since branches also follow
859 this pattern, relaxing these values is required.
861 We can assemble both mips16 and normal MIPS code in a single
862 object. Therefore, we need to support this type of relaxation at
863 the same time that we support the relaxation described above. We
864 use the high bit of the subtype field to distinguish these cases.
866 The information we store for this type of relaxation is the
867 argument code found in the opcode file for this relocation, whether
868 the user explicitly requested a small or extended form, and whether
869 the relocation is in a jump or jal delay slot. That tells us the
870 size of the value, and how it should be stored. We also store
871 whether the fragment is considered to be extended or not. We also
872 store whether this is known to be a branch to a different section,
873 whether we have tried to relax this frag yet, and whether we have
874 ever extended a PC relative fragment because of a shift count. */
875 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
878 | ((small) ? 0x100 : 0) \
879 | ((ext) ? 0x200 : 0) \
880 | ((dslot) ? 0x400 : 0) \
881 | ((jal_dslot) ? 0x800 : 0))
882 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
883 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
884 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
885 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
886 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
887 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
888 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
889 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
890 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
891 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
892 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
893 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
895 /* Is the given value a sign-extended 32-bit value? */
896 #define IS_SEXT_32BIT_NUM(x) \
897 (((x) &~ (offsetT) 0x7fffffff) == 0 \
898 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
900 /* Is the given value a sign-extended 16-bit value? */
901 #define IS_SEXT_16BIT_NUM(x) \
902 (((x) &~ (offsetT) 0x7fff) == 0 \
903 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
905 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
906 #define IS_ZEXT_32BIT_NUM(x) \
907 (((x) &~ (offsetT) 0xffffffff) == 0 \
908 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
910 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
911 VALUE << SHIFT. VALUE is evaluated exactly once. */
912 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
913 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
914 | (((VALUE) & (MASK)) << (SHIFT)))
916 /* Extract bits MASK << SHIFT from STRUCT and shift them right
918 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
919 (((STRUCT) >> (SHIFT)) & (MASK))
921 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
922 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
924 include/opcode/mips.h specifies operand fields using the macros
925 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
926 with "MIPS16OP" instead of "OP". */
927 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
928 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
929 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
930 INSERT_BITS ((INSN).insn_opcode, VALUE, \
931 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
933 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
934 #define EXTRACT_OPERAND(FIELD, INSN) \
935 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
936 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
937 EXTRACT_BITS ((INSN).insn_opcode, \
938 MIPS16OP_MASK_##FIELD, \
941 /* Global variables used when generating relaxable macros. See the
942 comment above RELAX_ENCODE for more details about how relaxation
945 /* 0 if we're not emitting a relaxable macro.
946 1 if we're emitting the first of the two relaxation alternatives.
947 2 if we're emitting the second alternative. */
950 /* The first relaxable fixup in the current frag. (In other words,
951 the first fixup that refers to relaxable code.) */
954 /* sizes[0] says how many bytes of the first alternative are stored in
955 the current frag. Likewise sizes[1] for the second alternative. */
956 unsigned int sizes
[2];
958 /* The symbol on which the choice of sequence depends. */
962 /* Global variables used to decide whether a macro needs a warning. */
964 /* True if the macro is in a branch delay slot. */
965 bfd_boolean delay_slot_p
;
967 /* For relaxable macros, sizes[0] is the length of the first alternative
968 in bytes and sizes[1] is the length of the second alternative.
969 For non-relaxable macros, both elements give the length of the
971 unsigned int sizes
[2];
973 /* The first variant frag for this macro. */
975 } mips_macro_warning
;
977 /* Prototypes for static functions. */
979 #define internalError() \
980 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
982 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
984 static void append_insn
985 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
986 static void mips_no_prev_insn (void);
987 static void mips16_macro_build
988 (expressionS
*, const char *, const char *, va_list);
989 static void load_register (int, expressionS
*, int);
990 static void macro_start (void);
991 static void macro_end (void);
992 static void macro (struct mips_cl_insn
* ip
);
993 static void mips16_macro (struct mips_cl_insn
* ip
);
994 #ifdef LOSING_COMPILER
995 static void macro2 (struct mips_cl_insn
* ip
);
997 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
998 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
999 static void mips16_immed
1000 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1001 unsigned long *, bfd_boolean
*, unsigned short *);
1002 static size_t my_getSmallExpression
1003 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1004 static void my_getExpression (expressionS
*, char *);
1005 static void s_align (int);
1006 static void s_change_sec (int);
1007 static void s_change_section (int);
1008 static void s_cons (int);
1009 static void s_float_cons (int);
1010 static void s_mips_globl (int);
1011 static void s_option (int);
1012 static void s_mipsset (int);
1013 static void s_abicalls (int);
1014 static void s_cpload (int);
1015 static void s_cpsetup (int);
1016 static void s_cplocal (int);
1017 static void s_cprestore (int);
1018 static void s_cpreturn (int);
1019 static void s_gpvalue (int);
1020 static void s_gpword (int);
1021 static void s_gpdword (int);
1022 static void s_cpadd (int);
1023 static void s_insn (int);
1024 static void md_obj_begin (void);
1025 static void md_obj_end (void);
1026 static void s_mips_ent (int);
1027 static void s_mips_end (int);
1028 static void s_mips_frame (int);
1029 static void s_mips_mask (int reg_type
);
1030 static void s_mips_stab (int);
1031 static void s_mips_weakext (int);
1032 static void s_mips_file (int);
1033 static void s_mips_loc (int);
1034 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1035 static int relaxed_branch_length (fragS
*, asection
*, int);
1036 static int validate_mips_insn (const struct mips_opcode
*);
1038 /* Table and functions used to map between CPU/ISA names, and
1039 ISA levels, and CPU numbers. */
1041 struct mips_cpu_info
1043 const char *name
; /* CPU or ISA name. */
1044 int flags
; /* ASEs available, or ISA flag. */
1045 int isa
; /* ISA level. */
1046 int cpu
; /* CPU number (default CPU if ISA). */
1049 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1050 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1051 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1052 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1053 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1054 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1056 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1057 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1058 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1062 The following pseudo-ops from the Kane and Heinrich MIPS book
1063 should be defined here, but are currently unsupported: .alias,
1064 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1066 The following pseudo-ops from the Kane and Heinrich MIPS book are
1067 specific to the type of debugging information being generated, and
1068 should be defined by the object format: .aent, .begin, .bend,
1069 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1072 The following pseudo-ops from the Kane and Heinrich MIPS book are
1073 not MIPS CPU specific, but are also not specific to the object file
1074 format. This file is probably the best place to define them, but
1075 they are not currently supported: .asm0, .endr, .lab, .repeat,
1078 static const pseudo_typeS mips_pseudo_table
[] =
1080 /* MIPS specific pseudo-ops. */
1081 {"option", s_option
, 0},
1082 {"set", s_mipsset
, 0},
1083 {"rdata", s_change_sec
, 'r'},
1084 {"sdata", s_change_sec
, 's'},
1085 {"livereg", s_ignore
, 0},
1086 {"abicalls", s_abicalls
, 0},
1087 {"cpload", s_cpload
, 0},
1088 {"cpsetup", s_cpsetup
, 0},
1089 {"cplocal", s_cplocal
, 0},
1090 {"cprestore", s_cprestore
, 0},
1091 {"cpreturn", s_cpreturn
, 0},
1092 {"gpvalue", s_gpvalue
, 0},
1093 {"gpword", s_gpword
, 0},
1094 {"gpdword", s_gpdword
, 0},
1095 {"cpadd", s_cpadd
, 0},
1096 {"insn", s_insn
, 0},
1098 /* Relatively generic pseudo-ops that happen to be used on MIPS
1100 {"asciiz", stringer
, 1},
1101 {"bss", s_change_sec
, 'b'},
1103 {"half", s_cons
, 1},
1104 {"dword", s_cons
, 3},
1105 {"weakext", s_mips_weakext
, 0},
1106 {"origin", s_org
, 0},
1107 {"repeat", s_rept
, 0},
1109 /* These pseudo-ops are defined in read.c, but must be overridden
1110 here for one reason or another. */
1111 {"align", s_align
, 0},
1112 {"byte", s_cons
, 0},
1113 {"data", s_change_sec
, 'd'},
1114 {"double", s_float_cons
, 'd'},
1115 {"float", s_float_cons
, 'f'},
1116 {"globl", s_mips_globl
, 0},
1117 {"global", s_mips_globl
, 0},
1118 {"hword", s_cons
, 1},
1120 {"long", s_cons
, 2},
1121 {"octa", s_cons
, 4},
1122 {"quad", s_cons
, 3},
1123 {"section", s_change_section
, 0},
1124 {"short", s_cons
, 1},
1125 {"single", s_float_cons
, 'f'},
1126 {"stabn", s_mips_stab
, 'n'},
1127 {"text", s_change_sec
, 't'},
1128 {"word", s_cons
, 2},
1130 { "extern", ecoff_directive_extern
, 0},
1135 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1137 /* These pseudo-ops should be defined by the object file format.
1138 However, a.out doesn't support them, so we have versions here. */
1139 {"aent", s_mips_ent
, 1},
1140 {"bgnb", s_ignore
, 0},
1141 {"end", s_mips_end
, 0},
1142 {"endb", s_ignore
, 0},
1143 {"ent", s_mips_ent
, 0},
1144 {"file", s_mips_file
, 0},
1145 {"fmask", s_mips_mask
, 'F'},
1146 {"frame", s_mips_frame
, 0},
1147 {"loc", s_mips_loc
, 0},
1148 {"mask", s_mips_mask
, 'R'},
1149 {"verstamp", s_ignore
, 0},
1153 extern void pop_insert (const pseudo_typeS
*);
1156 mips_pop_insert (void)
1158 pop_insert (mips_pseudo_table
);
1159 if (! ECOFF_DEBUGGING
)
1160 pop_insert (mips_nonecoff_pseudo_table
);
1163 /* Symbols labelling the current insn. */
1165 struct insn_label_list
1167 struct insn_label_list
*next
;
1171 static struct insn_label_list
*free_insn_labels
;
1172 #define label_list tc_segment_info_data
1174 static void mips_clear_insn_labels (void);
1177 mips_clear_insn_labels (void)
1179 register struct insn_label_list
**pl
;
1180 segment_info_type
*si
;
1184 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1187 si
= seg_info (now_seg
);
1188 *pl
= si
->label_list
;
1189 si
->label_list
= NULL
;
1194 static char *expr_end
;
1196 /* Expressions which appear in instructions. These are set by
1199 static expressionS imm_expr
;
1200 static expressionS imm2_expr
;
1201 static expressionS offset_expr
;
1203 /* Relocs associated with imm_expr and offset_expr. */
1205 static bfd_reloc_code_real_type imm_reloc
[3]
1206 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1207 static bfd_reloc_code_real_type offset_reloc
[3]
1208 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1210 /* These are set by mips16_ip if an explicit extension is used. */
1212 static bfd_boolean mips16_small
, mips16_ext
;
1215 /* The pdr segment for per procedure frame/regmask info. Not used for
1218 static segT pdr_seg
;
1221 /* The default target format to use. */
1224 mips_target_format (void)
1226 switch (OUTPUT_FLAVOR
)
1228 case bfd_target_ecoff_flavour
:
1229 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1230 case bfd_target_coff_flavour
:
1232 case bfd_target_elf_flavour
:
1234 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1235 return (target_big_endian
1236 ? "elf32-bigmips-vxworks"
1237 : "elf32-littlemips-vxworks");
1240 /* This is traditional mips. */
1241 return (target_big_endian
1242 ? (HAVE_64BIT_OBJECTS
1243 ? "elf64-tradbigmips"
1245 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1246 : (HAVE_64BIT_OBJECTS
1247 ? "elf64-tradlittlemips"
1249 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1251 return (target_big_endian
1252 ? (HAVE_64BIT_OBJECTS
1255 ? "elf32-nbigmips" : "elf32-bigmips"))
1256 : (HAVE_64BIT_OBJECTS
1257 ? "elf64-littlemips"
1259 ? "elf32-nlittlemips" : "elf32-littlemips")));
1267 /* Return the length of instruction INSN. */
1269 static inline unsigned int
1270 insn_length (const struct mips_cl_insn
*insn
)
1272 if (!mips_opts
.mips16
)
1274 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1277 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1280 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1285 insn
->use_extend
= FALSE
;
1287 insn
->insn_opcode
= mo
->match
;
1290 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1291 insn
->fixp
[i
] = NULL
;
1292 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1293 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1294 insn
->mips16_absolute_jump_p
= 0;
1297 /* Install INSN at the location specified by its "frag" and "where" fields. */
1300 install_insn (const struct mips_cl_insn
*insn
)
1302 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1303 if (!mips_opts
.mips16
)
1304 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1305 else if (insn
->mips16_absolute_jump_p
)
1307 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1308 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1312 if (insn
->use_extend
)
1314 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1317 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1321 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1322 and install the opcode in the new location. */
1325 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1330 insn
->where
= where
;
1331 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1332 if (insn
->fixp
[i
] != NULL
)
1334 insn
->fixp
[i
]->fx_frag
= frag
;
1335 insn
->fixp
[i
]->fx_where
= where
;
1337 install_insn (insn
);
1340 /* Add INSN to the end of the output. */
1343 add_fixed_insn (struct mips_cl_insn
*insn
)
1345 char *f
= frag_more (insn_length (insn
));
1346 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1349 /* Start a variant frag and move INSN to the start of the variant part,
1350 marking it as fixed. The other arguments are as for frag_var. */
1353 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1354 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1356 frag_grow (max_chars
);
1357 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1359 frag_var (rs_machine_dependent
, max_chars
, var
,
1360 subtype
, symbol
, offset
, NULL
);
1363 /* Insert N copies of INSN into the history buffer, starting at
1364 position FIRST. Neither FIRST nor N need to be clipped. */
1367 insert_into_history (unsigned int first
, unsigned int n
,
1368 const struct mips_cl_insn
*insn
)
1370 if (mips_relax
.sequence
!= 2)
1374 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1376 history
[i
] = history
[i
- n
];
1382 /* Emit a nop instruction, recording it in the history buffer. */
1387 add_fixed_insn (NOP_INSN
);
1388 insert_into_history (0, 1, NOP_INSN
);
1391 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1392 the idea is to make it obvious at a glance that each errata is
1396 init_vr4120_conflicts (void)
1398 #define CONFLICT(FIRST, SECOND) \
1399 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1401 /* Errata 21 - [D]DIV[U] after [D]MACC */
1402 CONFLICT (MACC
, DIV
);
1403 CONFLICT (DMACC
, DIV
);
1405 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1406 CONFLICT (DMULT
, DMULT
);
1407 CONFLICT (DMULT
, DMACC
);
1408 CONFLICT (DMACC
, DMULT
);
1409 CONFLICT (DMACC
, DMACC
);
1411 /* Errata 24 - MT{LO,HI} after [D]MACC */
1412 CONFLICT (MACC
, MTHILO
);
1413 CONFLICT (DMACC
, MTHILO
);
1415 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1416 instruction is executed immediately after a MACC or DMACC
1417 instruction, the result of [either instruction] is incorrect." */
1418 CONFLICT (MACC
, MULT
);
1419 CONFLICT (MACC
, DMULT
);
1420 CONFLICT (DMACC
, MULT
);
1421 CONFLICT (DMACC
, DMULT
);
1423 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1424 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1425 DDIV or DDIVU instruction, the result of the MACC or
1426 DMACC instruction is incorrect.". */
1427 CONFLICT (DMULT
, MACC
);
1428 CONFLICT (DMULT
, DMACC
);
1429 CONFLICT (DIV
, MACC
);
1430 CONFLICT (DIV
, DMACC
);
1440 #define RTYPE_MASK 0x1ff00
1441 #define RTYPE_NUM 0x00100
1442 #define RTYPE_FPU 0x00200
1443 #define RTYPE_FCC 0x00400
1444 #define RTYPE_VEC 0x00800
1445 #define RTYPE_GP 0x01000
1446 #define RTYPE_CP0 0x02000
1447 #define RTYPE_PC 0x04000
1448 #define RTYPE_ACC 0x08000
1449 #define RTYPE_CCC 0x10000
1450 #define RNUM_MASK 0x000ff
1451 #define RWARN 0x80000
1453 #define GENERIC_REGISTER_NUMBERS \
1454 {"$0", RTYPE_NUM | 0}, \
1455 {"$1", RTYPE_NUM | 1}, \
1456 {"$2", RTYPE_NUM | 2}, \
1457 {"$3", RTYPE_NUM | 3}, \
1458 {"$4", RTYPE_NUM | 4}, \
1459 {"$5", RTYPE_NUM | 5}, \
1460 {"$6", RTYPE_NUM | 6}, \
1461 {"$7", RTYPE_NUM | 7}, \
1462 {"$8", RTYPE_NUM | 8}, \
1463 {"$9", RTYPE_NUM | 9}, \
1464 {"$10", RTYPE_NUM | 10}, \
1465 {"$11", RTYPE_NUM | 11}, \
1466 {"$12", RTYPE_NUM | 12}, \
1467 {"$13", RTYPE_NUM | 13}, \
1468 {"$14", RTYPE_NUM | 14}, \
1469 {"$15", RTYPE_NUM | 15}, \
1470 {"$16", RTYPE_NUM | 16}, \
1471 {"$17", RTYPE_NUM | 17}, \
1472 {"$18", RTYPE_NUM | 18}, \
1473 {"$19", RTYPE_NUM | 19}, \
1474 {"$20", RTYPE_NUM | 20}, \
1475 {"$21", RTYPE_NUM | 21}, \
1476 {"$22", RTYPE_NUM | 22}, \
1477 {"$23", RTYPE_NUM | 23}, \
1478 {"$24", RTYPE_NUM | 24}, \
1479 {"$25", RTYPE_NUM | 25}, \
1480 {"$26", RTYPE_NUM | 26}, \
1481 {"$27", RTYPE_NUM | 27}, \
1482 {"$28", RTYPE_NUM | 28}, \
1483 {"$29", RTYPE_NUM | 29}, \
1484 {"$30", RTYPE_NUM | 30}, \
1485 {"$31", RTYPE_NUM | 31}
1487 #define FPU_REGISTER_NAMES \
1488 {"$f0", RTYPE_FPU | 0}, \
1489 {"$f1", RTYPE_FPU | 1}, \
1490 {"$f2", RTYPE_FPU | 2}, \
1491 {"$f3", RTYPE_FPU | 3}, \
1492 {"$f4", RTYPE_FPU | 4}, \
1493 {"$f5", RTYPE_FPU | 5}, \
1494 {"$f6", RTYPE_FPU | 6}, \
1495 {"$f7", RTYPE_FPU | 7}, \
1496 {"$f8", RTYPE_FPU | 8}, \
1497 {"$f9", RTYPE_FPU | 9}, \
1498 {"$f10", RTYPE_FPU | 10}, \
1499 {"$f11", RTYPE_FPU | 11}, \
1500 {"$f12", RTYPE_FPU | 12}, \
1501 {"$f13", RTYPE_FPU | 13}, \
1502 {"$f14", RTYPE_FPU | 14}, \
1503 {"$f15", RTYPE_FPU | 15}, \
1504 {"$f16", RTYPE_FPU | 16}, \
1505 {"$f17", RTYPE_FPU | 17}, \
1506 {"$f18", RTYPE_FPU | 18}, \
1507 {"$f19", RTYPE_FPU | 19}, \
1508 {"$f20", RTYPE_FPU | 20}, \
1509 {"$f21", RTYPE_FPU | 21}, \
1510 {"$f22", RTYPE_FPU | 22}, \
1511 {"$f23", RTYPE_FPU | 23}, \
1512 {"$f24", RTYPE_FPU | 24}, \
1513 {"$f25", RTYPE_FPU | 25}, \
1514 {"$f26", RTYPE_FPU | 26}, \
1515 {"$f27", RTYPE_FPU | 27}, \
1516 {"$f28", RTYPE_FPU | 28}, \
1517 {"$f29", RTYPE_FPU | 29}, \
1518 {"$f30", RTYPE_FPU | 30}, \
1519 {"$f31", RTYPE_FPU | 31}
1521 #define FPU_CONDITION_CODE_NAMES \
1522 {"$fcc0", RTYPE_FCC | 0}, \
1523 {"$fcc1", RTYPE_FCC | 1}, \
1524 {"$fcc2", RTYPE_FCC | 2}, \
1525 {"$fcc3", RTYPE_FCC | 3}, \
1526 {"$fcc4", RTYPE_FCC | 4}, \
1527 {"$fcc5", RTYPE_FCC | 5}, \
1528 {"$fcc6", RTYPE_FCC | 6}, \
1529 {"$fcc7", RTYPE_FCC | 7}
1531 #define COPROC_CONDITION_CODE_NAMES \
1532 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1533 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1534 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1535 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1536 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1537 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1538 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1539 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1541 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1542 {"$a4", RTYPE_GP | 8}, \
1543 {"$a5", RTYPE_GP | 9}, \
1544 {"$a6", RTYPE_GP | 10}, \
1545 {"$a7", RTYPE_GP | 11}, \
1546 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1547 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1548 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1549 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1550 {"$t0", RTYPE_GP | 12}, \
1551 {"$t1", RTYPE_GP | 13}, \
1552 {"$t2", RTYPE_GP | 14}, \
1553 {"$t3", RTYPE_GP | 15}
1555 #define O32_SYMBOLIC_REGISTER_NAMES \
1556 {"$t0", RTYPE_GP | 8}, \
1557 {"$t1", RTYPE_GP | 9}, \
1558 {"$t2", RTYPE_GP | 10}, \
1559 {"$t3", RTYPE_GP | 11}, \
1560 {"$t4", RTYPE_GP | 12}, \
1561 {"$t5", RTYPE_GP | 13}, \
1562 {"$t6", RTYPE_GP | 14}, \
1563 {"$t7", RTYPE_GP | 15}, \
1564 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1565 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1566 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1567 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1569 /* Remaining symbolic register names */
1570 #define SYMBOLIC_REGISTER_NAMES \
1571 {"$zero", RTYPE_GP | 0}, \
1572 {"$at", RTYPE_GP | 1}, \
1573 {"$AT", RTYPE_GP | 1}, \
1574 {"$v0", RTYPE_GP | 2}, \
1575 {"$v1", RTYPE_GP | 3}, \
1576 {"$a0", RTYPE_GP | 4}, \
1577 {"$a1", RTYPE_GP | 5}, \
1578 {"$a2", RTYPE_GP | 6}, \
1579 {"$a3", RTYPE_GP | 7}, \
1580 {"$s0", RTYPE_GP | 16}, \
1581 {"$s1", RTYPE_GP | 17}, \
1582 {"$s2", RTYPE_GP | 18}, \
1583 {"$s3", RTYPE_GP | 19}, \
1584 {"$s4", RTYPE_GP | 20}, \
1585 {"$s5", RTYPE_GP | 21}, \
1586 {"$s6", RTYPE_GP | 22}, \
1587 {"$s7", RTYPE_GP | 23}, \
1588 {"$t8", RTYPE_GP | 24}, \
1589 {"$t9", RTYPE_GP | 25}, \
1590 {"$k0", RTYPE_GP | 26}, \
1591 {"$kt0", RTYPE_GP | 26}, \
1592 {"$k1", RTYPE_GP | 27}, \
1593 {"$kt1", RTYPE_GP | 27}, \
1594 {"$gp", RTYPE_GP | 28}, \
1595 {"$sp", RTYPE_GP | 29}, \
1596 {"$s8", RTYPE_GP | 30}, \
1597 {"$fp", RTYPE_GP | 30}, \
1598 {"$ra", RTYPE_GP | 31}
1600 #define MIPS16_SPECIAL_REGISTER_NAMES \
1601 {"$pc", RTYPE_PC | 0}
1603 #define MDMX_VECTOR_REGISTER_NAMES \
1604 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1605 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1606 {"$v2", RTYPE_VEC | 2}, \
1607 {"$v3", RTYPE_VEC | 3}, \
1608 {"$v4", RTYPE_VEC | 4}, \
1609 {"$v5", RTYPE_VEC | 5}, \
1610 {"$v6", RTYPE_VEC | 6}, \
1611 {"$v7", RTYPE_VEC | 7}, \
1612 {"$v8", RTYPE_VEC | 8}, \
1613 {"$v9", RTYPE_VEC | 9}, \
1614 {"$v10", RTYPE_VEC | 10}, \
1615 {"$v11", RTYPE_VEC | 11}, \
1616 {"$v12", RTYPE_VEC | 12}, \
1617 {"$v13", RTYPE_VEC | 13}, \
1618 {"$v14", RTYPE_VEC | 14}, \
1619 {"$v15", RTYPE_VEC | 15}, \
1620 {"$v16", RTYPE_VEC | 16}, \
1621 {"$v17", RTYPE_VEC | 17}, \
1622 {"$v18", RTYPE_VEC | 18}, \
1623 {"$v19", RTYPE_VEC | 19}, \
1624 {"$v20", RTYPE_VEC | 20}, \
1625 {"$v21", RTYPE_VEC | 21}, \
1626 {"$v22", RTYPE_VEC | 22}, \
1627 {"$v23", RTYPE_VEC | 23}, \
1628 {"$v24", RTYPE_VEC | 24}, \
1629 {"$v25", RTYPE_VEC | 25}, \
1630 {"$v26", RTYPE_VEC | 26}, \
1631 {"$v27", RTYPE_VEC | 27}, \
1632 {"$v28", RTYPE_VEC | 28}, \
1633 {"$v29", RTYPE_VEC | 29}, \
1634 {"$v30", RTYPE_VEC | 30}, \
1635 {"$v31", RTYPE_VEC | 31}
1637 #define MIPS_DSP_ACCUMULATOR_NAMES \
1638 {"$ac0", RTYPE_ACC | 0}, \
1639 {"$ac1", RTYPE_ACC | 1}, \
1640 {"$ac2", RTYPE_ACC | 2}, \
1641 {"$ac3", RTYPE_ACC | 3}
1643 static const struct regname reg_names
[] = {
1644 GENERIC_REGISTER_NUMBERS
,
1646 FPU_CONDITION_CODE_NAMES
,
1647 COPROC_CONDITION_CODE_NAMES
,
1649 /* The $txx registers depends on the abi,
1650 these will be added later into the symbol table from
1651 one of the tables below once mips_abi is set after
1652 parsing of arguments from the command line. */
1653 SYMBOLIC_REGISTER_NAMES
,
1655 MIPS16_SPECIAL_REGISTER_NAMES
,
1656 MDMX_VECTOR_REGISTER_NAMES
,
1657 MIPS_DSP_ACCUMULATOR_NAMES
,
1661 static const struct regname reg_names_o32
[] = {
1662 O32_SYMBOLIC_REGISTER_NAMES
,
1666 static const struct regname reg_names_n32n64
[] = {
1667 N32N64_SYMBOLIC_REGISTER_NAMES
,
1672 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1679 /* Find end of name. */
1681 if (is_name_beginner (*e
))
1683 while (is_part_of_name (*e
))
1686 /* Terminate name. */
1690 /* Look for a register symbol. */
1691 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1693 int r
= S_GET_VALUE (symbolP
);
1695 reg
= r
& RNUM_MASK
;
1696 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1697 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1698 reg
= (r
& RNUM_MASK
) - 2;
1700 /* Else see if this is a register defined in an itbl entry. */
1701 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1708 if (itbl_get_reg_val (n
, &r
))
1709 reg
= r
& RNUM_MASK
;
1712 /* Advance to next token if a register was recognised. */
1715 else if (types
& RWARN
)
1716 as_warn ("Unrecognized register name `%s'", *s
);
1724 /* This function is called once, at assembler startup time. It should set up
1725 all the tables, etc. that the MD part of the assembler will need. */
1730 const char *retval
= NULL
;
1734 if (mips_pic
!= NO_PIC
)
1736 if (g_switch_seen
&& g_switch_value
!= 0)
1737 as_bad (_("-G may not be used in position-independent code"));
1741 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1742 as_warn (_("Could not set architecture and machine"));
1744 op_hash
= hash_new ();
1746 for (i
= 0; i
< NUMOPCODES
;)
1748 const char *name
= mips_opcodes
[i
].name
;
1750 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1753 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1754 mips_opcodes
[i
].name
, retval
);
1755 /* Probably a memory allocation problem? Give up now. */
1756 as_fatal (_("Broken assembler. No assembly attempted."));
1760 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1762 if (!validate_mips_insn (&mips_opcodes
[i
]))
1764 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1766 create_insn (&nop_insn
, mips_opcodes
+ i
);
1767 nop_insn
.fixed_p
= 1;
1772 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1775 mips16_op_hash
= hash_new ();
1778 while (i
< bfd_mips16_num_opcodes
)
1780 const char *name
= mips16_opcodes
[i
].name
;
1782 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1784 as_fatal (_("internal: can't hash `%s': %s"),
1785 mips16_opcodes
[i
].name
, retval
);
1788 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1789 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1790 != mips16_opcodes
[i
].match
))
1792 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1793 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1796 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1798 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1799 mips16_nop_insn
.fixed_p
= 1;
1803 while (i
< bfd_mips16_num_opcodes
1804 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1808 as_fatal (_("Broken assembler. No assembly attempted."));
1810 /* We add all the general register names to the symbol table. This
1811 helps us detect invalid uses of them. */
1812 for (i
= 0; reg_names
[i
].name
; i
++)
1813 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1814 reg_names
[i
].num
, // & RNUM_MASK,
1815 &zero_address_frag
));
1817 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1818 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1819 reg_names_n32n64
[i
].num
, // & RNUM_MASK,
1820 &zero_address_frag
));
1822 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1823 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1824 reg_names_o32
[i
].num
, // & RNUM_MASK,
1825 &zero_address_frag
));
1827 mips_no_prev_insn ();
1830 mips_cprmask
[0] = 0;
1831 mips_cprmask
[1] = 0;
1832 mips_cprmask
[2] = 0;
1833 mips_cprmask
[3] = 0;
1835 /* set the default alignment for the text section (2**2) */
1836 record_alignment (text_section
, 2);
1838 bfd_set_gp_size (stdoutput
, g_switch_value
);
1841 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1843 /* On a native system other than VxWorks, sections must be aligned
1844 to 16 byte boundaries. When configured for an embedded ELF
1845 target, we don't bother. */
1846 if (strcmp (TARGET_OS
, "elf") != 0
1847 && strcmp (TARGET_OS
, "vxworks") != 0)
1849 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1850 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1851 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1854 /* Create a .reginfo section for register masks and a .mdebug
1855 section for debugging information. */
1863 subseg
= now_subseg
;
1865 /* The ABI says this section should be loaded so that the
1866 running program can access it. However, we don't load it
1867 if we are configured for an embedded target */
1868 flags
= SEC_READONLY
| SEC_DATA
;
1869 if (strcmp (TARGET_OS
, "elf") != 0)
1870 flags
|= SEC_ALLOC
| SEC_LOAD
;
1872 if (mips_abi
!= N64_ABI
)
1874 sec
= subseg_new (".reginfo", (subsegT
) 0);
1876 bfd_set_section_flags (stdoutput
, sec
, flags
);
1877 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1879 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1883 /* The 64-bit ABI uses a .MIPS.options section rather than
1884 .reginfo section. */
1885 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1886 bfd_set_section_flags (stdoutput
, sec
, flags
);
1887 bfd_set_section_alignment (stdoutput
, sec
, 3);
1889 /* Set up the option header. */
1891 Elf_Internal_Options opthdr
;
1894 opthdr
.kind
= ODK_REGINFO
;
1895 opthdr
.size
= (sizeof (Elf_External_Options
)
1896 + sizeof (Elf64_External_RegInfo
));
1899 f
= frag_more (sizeof (Elf_External_Options
));
1900 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1901 (Elf_External_Options
*) f
);
1903 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1907 if (ECOFF_DEBUGGING
)
1909 sec
= subseg_new (".mdebug", (subsegT
) 0);
1910 (void) bfd_set_section_flags (stdoutput
, sec
,
1911 SEC_HAS_CONTENTS
| SEC_READONLY
);
1912 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1914 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1916 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1917 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1918 SEC_READONLY
| SEC_RELOC
1920 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1923 subseg_set (seg
, subseg
);
1926 #endif /* OBJ_ELF */
1928 if (! ECOFF_DEBUGGING
)
1931 if (mips_fix_vr4120
)
1932 init_vr4120_conflicts ();
1938 if (! ECOFF_DEBUGGING
)
1943 md_assemble (char *str
)
1945 struct mips_cl_insn insn
;
1946 bfd_reloc_code_real_type unused_reloc
[3]
1947 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1949 imm_expr
.X_op
= O_absent
;
1950 imm2_expr
.X_op
= O_absent
;
1951 offset_expr
.X_op
= O_absent
;
1952 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1953 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1954 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1955 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1956 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1957 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1959 if (mips_opts
.mips16
)
1960 mips16_ip (str
, &insn
);
1963 mips_ip (str
, &insn
);
1964 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1965 str
, insn
.insn_opcode
));
1970 as_bad ("%s `%s'", insn_error
, str
);
1974 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1977 if (mips_opts
.mips16
)
1978 mips16_macro (&insn
);
1985 if (imm_expr
.X_op
!= O_absent
)
1986 append_insn (&insn
, &imm_expr
, imm_reloc
);
1987 else if (offset_expr
.X_op
!= O_absent
)
1988 append_insn (&insn
, &offset_expr
, offset_reloc
);
1990 append_insn (&insn
, NULL
, unused_reloc
);
1994 /* Return true if the given relocation might need a matching %lo().
1995 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
1996 need a matching %lo() when applied to local symbols. */
1998 static inline bfd_boolean
1999 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2001 return (HAVE_IN_PLACE_ADDENDS
2002 && (reloc
== BFD_RELOC_HI16_S
2003 || reloc
== BFD_RELOC_MIPS16_HI16_S
2004 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2005 all GOT16 relocations evaluate to "G". */
2006 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
2009 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2012 static inline bfd_boolean
2013 fixup_has_matching_lo_p (fixS
*fixp
)
2015 return (fixp
->fx_next
!= NULL
2016 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
2017 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
2018 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2019 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2022 /* See whether instruction IP reads register REG. CLASS is the type
2026 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2027 enum mips_regclass
class)
2029 if (class == MIPS16_REG
)
2031 assert (mips_opts
.mips16
);
2032 reg
= mips16_to_32_reg_map
[reg
];
2033 class = MIPS_GR_REG
;
2036 /* Don't report on general register ZERO, since it never changes. */
2037 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2040 if (class == MIPS_FP_REG
)
2042 assert (! mips_opts
.mips16
);
2043 /* If we are called with either $f0 or $f1, we must check $f0.
2044 This is not optimal, because it will introduce an unnecessary
2045 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2046 need to distinguish reading both $f0 and $f1 or just one of
2047 them. Note that we don't have to check the other way,
2048 because there is no instruction that sets both $f0 and $f1
2049 and requires a delay. */
2050 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2051 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2052 == (reg
&~ (unsigned) 1)))
2054 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2055 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2056 == (reg
&~ (unsigned) 1)))
2059 else if (! mips_opts
.mips16
)
2061 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2062 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2064 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2065 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2070 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2071 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2073 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2074 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2076 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2077 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2080 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2082 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2084 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2086 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2087 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2094 /* This function returns true if modifying a register requires a
2098 reg_needs_delay (unsigned int reg
)
2100 unsigned long prev_pinfo
;
2102 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2103 if (! mips_opts
.noreorder
2104 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2105 && ! gpr_interlocks
)
2106 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2107 && ! cop_interlocks
)))
2109 /* A load from a coprocessor or from memory. All load delays
2110 delay the use of general register rt for one instruction. */
2111 /* Itbl support may require additional care here. */
2112 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2113 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2120 /* Move all labels in insn_labels to the current insertion point. */
2123 mips_move_labels (void)
2125 segment_info_type
*si
= seg_info (now_seg
);
2126 struct insn_label_list
*l
;
2129 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2131 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2132 symbol_set_frag (l
->label
, frag_now
);
2133 val
= (valueT
) frag_now_fix ();
2134 /* mips16 text labels are stored as odd. */
2135 if (mips_opts
.mips16
)
2137 S_SET_VALUE (l
->label
, val
);
2141 /* Mark instruction labels in mips16 mode. This permits the linker to
2142 handle them specially, such as generating jalx instructions when
2143 needed. We also make them odd for the duration of the assembly, in
2144 order to generate the right sort of code. We will make them even
2145 in the adjust_symtab routine, while leaving them marked. This is
2146 convenient for the debugger and the disassembler. The linker knows
2147 to make them odd again. */
2150 mips16_mark_labels (void)
2152 segment_info_type
*si
= seg_info (now_seg
);
2153 struct insn_label_list
*l
;
2155 if (!mips_opts
.mips16
)
2158 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2160 symbolS
*label
= l
->label
;
2162 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2163 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2164 S_SET_OTHER (label
, STO_MIPS16
);
2166 if ((S_GET_VALUE (label
) & 1) == 0)
2167 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2171 /* End the current frag. Make it a variant frag and record the
2175 relax_close_frag (void)
2177 mips_macro_warning
.first_frag
= frag_now
;
2178 frag_var (rs_machine_dependent
, 0, 0,
2179 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2180 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2182 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2183 mips_relax
.first_fixup
= 0;
2186 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2187 See the comment above RELAX_ENCODE for more details. */
2190 relax_start (symbolS
*symbol
)
2192 assert (mips_relax
.sequence
== 0);
2193 mips_relax
.sequence
= 1;
2194 mips_relax
.symbol
= symbol
;
2197 /* Start generating the second version of a relaxable sequence.
2198 See the comment above RELAX_ENCODE for more details. */
2203 assert (mips_relax
.sequence
== 1);
2204 mips_relax
.sequence
= 2;
2207 /* End the current relaxable sequence. */
2212 assert (mips_relax
.sequence
== 2);
2213 relax_close_frag ();
2214 mips_relax
.sequence
= 0;
2217 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2218 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2219 by VR4120 errata. */
2222 classify_vr4120_insn (const char *name
)
2224 if (strncmp (name
, "macc", 4) == 0)
2225 return FIX_VR4120_MACC
;
2226 if (strncmp (name
, "dmacc", 5) == 0)
2227 return FIX_VR4120_DMACC
;
2228 if (strncmp (name
, "mult", 4) == 0)
2229 return FIX_VR4120_MULT
;
2230 if (strncmp (name
, "dmult", 5) == 0)
2231 return FIX_VR4120_DMULT
;
2232 if (strstr (name
, "div"))
2233 return FIX_VR4120_DIV
;
2234 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2235 return FIX_VR4120_MTHILO
;
2236 return NUM_FIX_VR4120_CLASSES
;
2239 /* Return the number of instructions that must separate INSN1 and INSN2,
2240 where INSN1 is the earlier instruction. Return the worst-case value
2241 for any INSN2 if INSN2 is null. */
2244 insns_between (const struct mips_cl_insn
*insn1
,
2245 const struct mips_cl_insn
*insn2
)
2247 unsigned long pinfo1
, pinfo2
;
2249 /* This function needs to know which pinfo flags are set for INSN2
2250 and which registers INSN2 uses. The former is stored in PINFO2 and
2251 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2252 will have every flag set and INSN2_USES_REG will always return true. */
2253 pinfo1
= insn1
->insn_mo
->pinfo
;
2254 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2256 #define INSN2_USES_REG(REG, CLASS) \
2257 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2259 /* For most targets, write-after-read dependencies on the HI and LO
2260 registers must be separated by at least two instructions. */
2261 if (!hilo_interlocks
)
2263 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2265 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2269 /* If we're working around r7000 errata, there must be two instructions
2270 between an mfhi or mflo and any instruction that uses the result. */
2271 if (mips_7000_hilo_fix
2272 && MF_HILO_INSN (pinfo1
)
2273 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2276 /* If working around VR4120 errata, check for combinations that need
2277 a single intervening instruction. */
2278 if (mips_fix_vr4120
)
2280 unsigned int class1
, class2
;
2282 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2283 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2287 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2288 if (vr4120_conflicts
[class1
] & (1 << class2
))
2293 if (!mips_opts
.mips16
)
2295 /* Check for GPR or coprocessor load delays. All such delays
2296 are on the RT register. */
2297 /* Itbl support may require additional care here. */
2298 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2299 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2301 know (pinfo1
& INSN_WRITE_GPR_T
);
2302 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2306 /* Check for generic coprocessor hazards.
2308 This case is not handled very well. There is no special
2309 knowledge of CP0 handling, and the coprocessors other than
2310 the floating point unit are not distinguished at all. */
2311 /* Itbl support may require additional care here. FIXME!
2312 Need to modify this to include knowledge about
2313 user specified delays! */
2314 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2315 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2317 /* Handle cases where INSN1 writes to a known general coprocessor
2318 register. There must be a one instruction delay before INSN2
2319 if INSN2 reads that register, otherwise no delay is needed. */
2320 if (pinfo1
& INSN_WRITE_FPR_T
)
2322 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2325 else if (pinfo1
& INSN_WRITE_FPR_S
)
2327 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2332 /* Read-after-write dependencies on the control registers
2333 require a two-instruction gap. */
2334 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2335 && (pinfo2
& INSN_READ_COND_CODE
))
2338 /* We don't know exactly what INSN1 does. If INSN2 is
2339 also a coprocessor instruction, assume there must be
2340 a one instruction gap. */
2341 if (pinfo2
& INSN_COP
)
2346 /* Check for read-after-write dependencies on the coprocessor
2347 control registers in cases where INSN1 does not need a general
2348 coprocessor delay. This means that INSN1 is a floating point
2349 comparison instruction. */
2350 /* Itbl support may require additional care here. */
2351 else if (!cop_interlocks
2352 && (pinfo1
& INSN_WRITE_COND_CODE
)
2353 && (pinfo2
& INSN_READ_COND_CODE
))
2357 #undef INSN2_USES_REG
2362 /* Return the number of nops that would be needed to work around the
2363 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2364 the MAX_VR4130_NOPS instructions described by HISTORY. */
2367 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2368 const struct mips_cl_insn
*insn
)
2372 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2373 are not affected by the errata. */
2375 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2376 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2377 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2380 /* Search for the first MFLO or MFHI. */
2381 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2382 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2384 /* Extract the destination register. */
2385 if (mips_opts
.mips16
)
2386 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2388 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2390 /* No nops are needed if INSN reads that register. */
2391 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2394 /* ...or if any of the intervening instructions do. */
2395 for (j
= 0; j
< i
; j
++)
2396 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2399 return MAX_VR4130_NOPS
- i
;
2404 /* Return the number of nops that would be needed if instruction INSN
2405 immediately followed the MAX_NOPS instructions given by HISTORY,
2406 where HISTORY[0] is the most recent instruction. If INSN is null,
2407 return the worse-case number of nops for any instruction. */
2410 nops_for_insn (const struct mips_cl_insn
*history
,
2411 const struct mips_cl_insn
*insn
)
2413 int i
, nops
, tmp_nops
;
2416 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2417 if (!history
[i
].noreorder_p
)
2419 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2420 if (tmp_nops
> nops
)
2424 if (mips_fix_vr4130
)
2426 tmp_nops
= nops_for_vr4130 (history
, insn
);
2427 if (tmp_nops
> nops
)
2434 /* The variable arguments provide NUM_INSNS extra instructions that
2435 might be added to HISTORY. Return the largest number of nops that
2436 would be needed after the extended sequence. */
2439 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2442 struct mips_cl_insn buffer
[MAX_NOPS
];
2443 struct mips_cl_insn
*cursor
;
2446 va_start (args
, history
);
2447 cursor
= buffer
+ num_insns
;
2448 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2449 while (cursor
> buffer
)
2450 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2452 nops
= nops_for_insn (buffer
, NULL
);
2457 /* Like nops_for_insn, but if INSN is a branch, take into account the
2458 worst-case delay for the branch target. */
2461 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2462 const struct mips_cl_insn
*insn
)
2466 nops
= nops_for_insn (history
, insn
);
2467 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2468 | INSN_COND_BRANCH_DELAY
2469 | INSN_COND_BRANCH_LIKELY
))
2471 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2472 if (tmp_nops
> nops
)
2475 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2477 tmp_nops
= nops_for_sequence (1, history
, insn
);
2478 if (tmp_nops
> nops
)
2484 /* Output an instruction. IP is the instruction information.
2485 ADDRESS_EXPR is an operand of the instruction to be used with
2489 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2490 bfd_reloc_code_real_type
*reloc_type
)
2492 unsigned long prev_pinfo
, pinfo
;
2493 relax_stateT prev_insn_frag_type
= 0;
2494 bfd_boolean relaxed_branch
= FALSE
;
2495 segment_info_type
*si
= seg_info (now_seg
);
2497 /* Mark instruction labels in mips16 mode. */
2498 mips16_mark_labels ();
2500 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2501 pinfo
= ip
->insn_mo
->pinfo
;
2503 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2505 /* There are a lot of optimizations we could do that we don't.
2506 In particular, we do not, in general, reorder instructions.
2507 If you use gcc with optimization, it will reorder
2508 instructions and generally do much more optimization then we
2509 do here; repeating all that work in the assembler would only
2510 benefit hand written assembly code, and does not seem worth
2512 int nops
= (mips_optimize
== 0
2513 ? nops_for_insn (history
, NULL
)
2514 : nops_for_insn_or_target (history
, ip
));
2518 unsigned long old_frag_offset
;
2521 old_frag
= frag_now
;
2522 old_frag_offset
= frag_now_fix ();
2524 for (i
= 0; i
< nops
; i
++)
2529 listing_prev_line ();
2530 /* We may be at the start of a variant frag. In case we
2531 are, make sure there is enough space for the frag
2532 after the frags created by listing_prev_line. The
2533 argument to frag_grow here must be at least as large
2534 as the argument to all other calls to frag_grow in
2535 this file. We don't have to worry about being in the
2536 middle of a variant frag, because the variants insert
2537 all needed nop instructions themselves. */
2541 mips_move_labels ();
2543 #ifndef NO_ECOFF_DEBUGGING
2544 if (ECOFF_DEBUGGING
)
2545 ecoff_fix_loc (old_frag
, old_frag_offset
);
2549 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2551 /* Work out how many nops in prev_nop_frag are needed by IP. */
2552 int nops
= nops_for_insn_or_target (history
, ip
);
2553 assert (nops
<= prev_nop_frag_holds
);
2555 /* Enforce NOPS as a minimum. */
2556 if (nops
> prev_nop_frag_required
)
2557 prev_nop_frag_required
= nops
;
2559 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2561 /* Settle for the current number of nops. Update the history
2562 accordingly (for the benefit of any future .set reorder code). */
2563 prev_nop_frag
= NULL
;
2564 insert_into_history (prev_nop_frag_since
,
2565 prev_nop_frag_holds
, NOP_INSN
);
2569 /* Allow this instruction to replace one of the nops that was
2570 tentatively added to prev_nop_frag. */
2571 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2572 prev_nop_frag_holds
--;
2573 prev_nop_frag_since
++;
2578 /* The value passed to dwarf2_emit_insn is the distance between
2579 the beginning of the current instruction and the address that
2580 should be recorded in the debug tables. For MIPS16 debug info
2581 we want to use ISA-encoded addresses, so we pass -1 for an
2582 address higher by one than the current. */
2583 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2586 /* Record the frag type before frag_var. */
2587 if (history
[0].frag
)
2588 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2591 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2592 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2593 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2594 && mips_relax_branch
2595 /* Don't try branch relaxation within .set nomacro, or within
2596 .set noat if we use $at for PIC computations. If it turns
2597 out that the branch was out-of-range, we'll get an error. */
2598 && !mips_opts
.warn_about_macros
2599 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2600 && !mips_opts
.mips16
)
2602 relaxed_branch
= TRUE
;
2603 add_relaxed_insn (ip
, (relaxed_branch_length
2605 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2606 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2609 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2610 pinfo
& INSN_COND_BRANCH_LIKELY
,
2611 pinfo
& INSN_WRITE_GPR_31
,
2613 address_expr
->X_add_symbol
,
2614 address_expr
->X_add_number
);
2615 *reloc_type
= BFD_RELOC_UNUSED
;
2617 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2619 /* We need to set up a variant frag. */
2620 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2621 add_relaxed_insn (ip
, 4, 0,
2623 (*reloc_type
- BFD_RELOC_UNUSED
,
2624 mips16_small
, mips16_ext
,
2625 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2626 history
[0].mips16_absolute_jump_p
),
2627 make_expr_symbol (address_expr
), 0);
2629 else if (mips_opts
.mips16
2631 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2633 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2634 /* Make sure there is enough room to swap this instruction with
2635 a following jump instruction. */
2637 add_fixed_insn (ip
);
2641 if (mips_opts
.mips16
2642 && mips_opts
.noreorder
2643 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2644 as_warn (_("extended instruction in delay slot"));
2646 if (mips_relax
.sequence
)
2648 /* If we've reached the end of this frag, turn it into a variant
2649 frag and record the information for the instructions we've
2651 if (frag_room () < 4)
2652 relax_close_frag ();
2653 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2656 if (mips_relax
.sequence
!= 2)
2657 mips_macro_warning
.sizes
[0] += 4;
2658 if (mips_relax
.sequence
!= 1)
2659 mips_macro_warning
.sizes
[1] += 4;
2661 if (mips_opts
.mips16
)
2664 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2666 add_fixed_insn (ip
);
2669 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2671 if (address_expr
->X_op
== O_constant
)
2675 switch (*reloc_type
)
2678 ip
->insn_opcode
|= address_expr
->X_add_number
;
2681 case BFD_RELOC_MIPS_HIGHEST
:
2682 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2683 ip
->insn_opcode
|= tmp
& 0xffff;
2686 case BFD_RELOC_MIPS_HIGHER
:
2687 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2688 ip
->insn_opcode
|= tmp
& 0xffff;
2691 case BFD_RELOC_HI16_S
:
2692 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2693 ip
->insn_opcode
|= tmp
& 0xffff;
2696 case BFD_RELOC_HI16
:
2697 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2700 case BFD_RELOC_UNUSED
:
2701 case BFD_RELOC_LO16
:
2702 case BFD_RELOC_MIPS_GOT_DISP
:
2703 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2706 case BFD_RELOC_MIPS_JMP
:
2707 if ((address_expr
->X_add_number
& 3) != 0)
2708 as_bad (_("jump to misaligned address (0x%lx)"),
2709 (unsigned long) address_expr
->X_add_number
);
2710 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2713 case BFD_RELOC_MIPS16_JMP
:
2714 if ((address_expr
->X_add_number
& 3) != 0)
2715 as_bad (_("jump to misaligned address (0x%lx)"),
2716 (unsigned long) address_expr
->X_add_number
);
2718 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2719 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2720 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2723 case BFD_RELOC_16_PCREL_S2
:
2724 if ((address_expr
->X_add_number
& 3) != 0)
2725 as_bad (_("branch to misaligned address (0x%lx)"),
2726 (unsigned long) address_expr
->X_add_number
);
2727 if (mips_relax_branch
)
2729 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2730 as_bad (_("branch address range overflow (0x%lx)"),
2731 (unsigned long) address_expr
->X_add_number
);
2732 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2739 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2742 reloc_howto_type
*howto
;
2745 /* In a compound relocation, it is the final (outermost)
2746 operator that determines the relocated field. */
2747 for (i
= 1; i
< 3; i
++)
2748 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2751 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2752 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2753 bfd_get_reloc_size (howto
),
2755 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2758 /* These relocations can have an addend that won't fit in
2759 4 octets for 64bit assembly. */
2761 && ! howto
->partial_inplace
2762 && (reloc_type
[0] == BFD_RELOC_16
2763 || reloc_type
[0] == BFD_RELOC_32
2764 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2765 || reloc_type
[0] == BFD_RELOC_HI16_S
2766 || reloc_type
[0] == BFD_RELOC_LO16
2767 || reloc_type
[0] == BFD_RELOC_GPREL16
2768 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2769 || reloc_type
[0] == BFD_RELOC_GPREL32
2770 || reloc_type
[0] == BFD_RELOC_64
2771 || reloc_type
[0] == BFD_RELOC_CTOR
2772 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2773 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2774 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2775 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2776 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2777 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2778 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2779 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2780 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2781 ip
->fixp
[0]->fx_no_overflow
= 1;
2783 if (mips_relax
.sequence
)
2785 if (mips_relax
.first_fixup
== 0)
2786 mips_relax
.first_fixup
= ip
->fixp
[0];
2788 else if (reloc_needs_lo_p (*reloc_type
))
2790 struct mips_hi_fixup
*hi_fixup
;
2792 /* Reuse the last entry if it already has a matching %lo. */
2793 hi_fixup
= mips_hi_fixup_list
;
2795 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2797 hi_fixup
= ((struct mips_hi_fixup
*)
2798 xmalloc (sizeof (struct mips_hi_fixup
)));
2799 hi_fixup
->next
= mips_hi_fixup_list
;
2800 mips_hi_fixup_list
= hi_fixup
;
2802 hi_fixup
->fixp
= ip
->fixp
[0];
2803 hi_fixup
->seg
= now_seg
;
2806 /* Add fixups for the second and third relocations, if given.
2807 Note that the ABI allows the second relocation to be
2808 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2809 moment we only use RSS_UNDEF, but we could add support
2810 for the others if it ever becomes necessary. */
2811 for (i
= 1; i
< 3; i
++)
2812 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2814 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2815 ip
->fixp
[0]->fx_size
, NULL
, 0,
2816 FALSE
, reloc_type
[i
]);
2818 /* Use fx_tcbit to mark compound relocs. */
2819 ip
->fixp
[0]->fx_tcbit
= 1;
2820 ip
->fixp
[i
]->fx_tcbit
= 1;
2826 /* Update the register mask information. */
2827 if (! mips_opts
.mips16
)
2829 if (pinfo
& INSN_WRITE_GPR_D
)
2830 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2831 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2832 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2833 if (pinfo
& INSN_READ_GPR_S
)
2834 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2835 if (pinfo
& INSN_WRITE_GPR_31
)
2836 mips_gprmask
|= 1 << RA
;
2837 if (pinfo
& INSN_WRITE_FPR_D
)
2838 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2839 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2840 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2841 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2842 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2843 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2844 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2845 if (pinfo
& INSN_COP
)
2847 /* We don't keep enough information to sort these cases out.
2848 The itbl support does keep this information however, although
2849 we currently don't support itbl fprmats as part of the cop
2850 instruction. May want to add this support in the future. */
2852 /* Never set the bit for $0, which is always zero. */
2853 mips_gprmask
&= ~1 << 0;
2857 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2858 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2859 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2860 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2861 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2862 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2863 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2864 mips_gprmask
|= 1 << TREG
;
2865 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2866 mips_gprmask
|= 1 << SP
;
2867 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2868 mips_gprmask
|= 1 << RA
;
2869 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2870 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2871 if (pinfo
& MIPS16_INSN_READ_Z
)
2872 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2873 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2874 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2877 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2879 /* Filling the branch delay slot is more complex. We try to
2880 switch the branch with the previous instruction, which we can
2881 do if the previous instruction does not set up a condition
2882 that the branch tests and if the branch is not itself the
2883 target of any branch. */
2884 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2885 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2887 if (mips_optimize
< 2
2888 /* If we have seen .set volatile or .set nomove, don't
2890 || mips_opts
.nomove
!= 0
2891 /* We can't swap if the previous instruction's position
2893 || history
[0].fixed_p
2894 /* If the previous previous insn was in a .set
2895 noreorder, we can't swap. Actually, the MIPS
2896 assembler will swap in this situation. However, gcc
2897 configured -with-gnu-as will generate code like
2903 in which we can not swap the bne and INSN. If gcc is
2904 not configured -with-gnu-as, it does not output the
2906 || history
[1].noreorder_p
2907 /* If the branch is itself the target of a branch, we
2908 can not swap. We cheat on this; all we check for is
2909 whether there is a label on this instruction. If
2910 there are any branches to anything other than a
2911 label, users must use .set noreorder. */
2912 || si
->label_list
!= NULL
2913 /* If the previous instruction is in a variant frag
2914 other than this branch's one, we cannot do the swap.
2915 This does not apply to the mips16, which uses variant
2916 frags for different purposes. */
2917 || (! mips_opts
.mips16
2918 && prev_insn_frag_type
== rs_machine_dependent
)
2919 /* Check for conflicts between the branch and the instructions
2920 before the candidate delay slot. */
2921 || nops_for_insn (history
+ 1, ip
) > 0
2922 /* Check for conflicts between the swapped sequence and the
2923 target of the branch. */
2924 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2925 /* We do not swap with a trap instruction, since it
2926 complicates trap handlers to have the trap
2927 instruction be in a delay slot. */
2928 || (prev_pinfo
& INSN_TRAP
)
2929 /* If the branch reads a register that the previous
2930 instruction sets, we can not swap. */
2931 || (! mips_opts
.mips16
2932 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2933 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2935 || (! mips_opts
.mips16
2936 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2937 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2939 || (mips_opts
.mips16
2940 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2942 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2944 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2946 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2948 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2950 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2952 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2953 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2954 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2955 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2956 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2957 && insn_uses_reg (ip
,
2958 MIPS16OP_EXTRACT_REG32R
2959 (history
[0].insn_opcode
),
2961 /* If the branch writes a register that the previous
2962 instruction sets, we can not swap (we know that
2963 branches write only to RD or to $31). */
2964 || (! mips_opts
.mips16
2965 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2966 && (((pinfo
& INSN_WRITE_GPR_D
)
2967 && (EXTRACT_OPERAND (RT
, history
[0])
2968 == EXTRACT_OPERAND (RD
, *ip
)))
2969 || ((pinfo
& INSN_WRITE_GPR_31
)
2970 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2971 || (! mips_opts
.mips16
2972 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2973 && (((pinfo
& INSN_WRITE_GPR_D
)
2974 && (EXTRACT_OPERAND (RD
, history
[0])
2975 == EXTRACT_OPERAND (RD
, *ip
)))
2976 || ((pinfo
& INSN_WRITE_GPR_31
)
2977 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2978 || (mips_opts
.mips16
2979 && (pinfo
& MIPS16_INSN_WRITE_31
)
2980 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2981 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2982 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2984 /* If the branch writes a register that the previous
2985 instruction reads, we can not swap (we know that
2986 branches only write to RD or to $31). */
2987 || (! mips_opts
.mips16
2988 && (pinfo
& INSN_WRITE_GPR_D
)
2989 && insn_uses_reg (&history
[0],
2990 EXTRACT_OPERAND (RD
, *ip
),
2992 || (! mips_opts
.mips16
2993 && (pinfo
& INSN_WRITE_GPR_31
)
2994 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2995 || (mips_opts
.mips16
2996 && (pinfo
& MIPS16_INSN_WRITE_31
)
2997 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2998 /* If one instruction sets a condition code and the
2999 other one uses a condition code, we can not swap. */
3000 || ((pinfo
& INSN_READ_COND_CODE
)
3001 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3002 || ((pinfo
& INSN_WRITE_COND_CODE
)
3003 && (prev_pinfo
& INSN_READ_COND_CODE
))
3004 /* If the previous instruction uses the PC, we can not
3006 || (mips_opts
.mips16
3007 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3008 /* If the previous instruction had a fixup in mips16
3009 mode, we can not swap. This normally means that the
3010 previous instruction was a 4 byte branch anyhow. */
3011 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3012 /* If the previous instruction is a sync, sync.l, or
3013 sync.p, we can not swap. */
3014 || (prev_pinfo
& INSN_SYNC
))
3016 if (mips_opts
.mips16
3017 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3018 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3019 && ISA_SUPPORTS_MIPS16E
)
3021 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3022 ip
->insn_opcode
|= 0x0080;
3024 insert_into_history (0, 1, ip
);
3028 /* We could do even better for unconditional branches to
3029 portions of this object file; we could pick up the
3030 instruction at the destination, put it in the delay
3031 slot, and bump the destination address. */
3032 insert_into_history (0, 1, ip
);
3036 if (mips_relax
.sequence
)
3037 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3041 /* It looks like we can actually do the swap. */
3042 struct mips_cl_insn delay
= history
[0];
3043 if (mips_opts
.mips16
)
3045 know (delay
.frag
== ip
->frag
);
3046 move_insn (ip
, delay
.frag
, delay
.where
);
3047 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3049 else if (relaxed_branch
)
3051 /* Add the delay slot instruction to the end of the
3052 current frag and shrink the fixed part of the
3053 original frag. If the branch occupies the tail of
3054 the latter, move it backwards to cover the gap. */
3055 delay
.frag
->fr_fix
-= 4;
3056 if (delay
.frag
== ip
->frag
)
3057 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3058 add_fixed_insn (&delay
);
3062 move_insn (&delay
, ip
->frag
, ip
->where
);
3063 move_insn (ip
, history
[0].frag
, history
[0].where
);
3067 insert_into_history (0, 1, &delay
);
3070 /* If that was an unconditional branch, forget the previous
3071 insn information. */
3072 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3073 mips_no_prev_insn ();
3075 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3077 /* We don't yet optimize a branch likely. What we should do
3078 is look at the target, copy the instruction found there
3079 into the delay slot, and increment the branch to jump to
3080 the next instruction. */
3081 insert_into_history (0, 1, ip
);
3085 insert_into_history (0, 1, ip
);
3088 insert_into_history (0, 1, ip
);
3090 /* We just output an insn, so the next one doesn't have a label. */
3091 mips_clear_insn_labels ();
3094 /* Forget that there was any previous instruction or label. */
3097 mips_no_prev_insn (void)
3099 prev_nop_frag
= NULL
;
3100 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3101 mips_clear_insn_labels ();
3104 /* This function must be called before we emit something other than
3105 instructions. It is like mips_no_prev_insn except that it inserts
3106 any NOPS that might be needed by previous instructions. */
3109 mips_emit_delays (void)
3111 if (! mips_opts
.noreorder
)
3113 int nops
= nops_for_insn (history
, NULL
);
3117 add_fixed_insn (NOP_INSN
);
3118 mips_move_labels ();
3121 mips_no_prev_insn ();
3124 /* Start a (possibly nested) noreorder block. */
3127 start_noreorder (void)
3129 if (mips_opts
.noreorder
== 0)
3134 /* None of the instructions before the .set noreorder can be moved. */
3135 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3136 history
[i
].fixed_p
= 1;
3138 /* Insert any nops that might be needed between the .set noreorder
3139 block and the previous instructions. We will later remove any
3140 nops that turn out not to be needed. */
3141 nops
= nops_for_insn (history
, NULL
);
3144 if (mips_optimize
!= 0)
3146 /* Record the frag which holds the nop instructions, so
3147 that we can remove them if we don't need them. */
3148 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3149 prev_nop_frag
= frag_now
;
3150 prev_nop_frag_holds
= nops
;
3151 prev_nop_frag_required
= 0;
3152 prev_nop_frag_since
= 0;
3155 for (; nops
> 0; --nops
)
3156 add_fixed_insn (NOP_INSN
);
3158 /* Move on to a new frag, so that it is safe to simply
3159 decrease the size of prev_nop_frag. */
3160 frag_wane (frag_now
);
3162 mips_move_labels ();
3164 mips16_mark_labels ();
3165 mips_clear_insn_labels ();
3167 mips_opts
.noreorder
++;
3168 mips_any_noreorder
= 1;
3171 /* End a nested noreorder block. */
3174 end_noreorder (void)
3176 mips_opts
.noreorder
--;
3177 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3179 /* Commit to inserting prev_nop_frag_required nops and go back to
3180 handling nop insertion the .set reorder way. */
3181 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3182 * (mips_opts
.mips16
? 2 : 4));
3183 insert_into_history (prev_nop_frag_since
,
3184 prev_nop_frag_required
, NOP_INSN
);
3185 prev_nop_frag
= NULL
;
3189 /* Set up global variables for the start of a new macro. */
3194 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3195 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3196 && (history
[0].insn_mo
->pinfo
3197 & (INSN_UNCOND_BRANCH_DELAY
3198 | INSN_COND_BRANCH_DELAY
3199 | INSN_COND_BRANCH_LIKELY
)) != 0);
3202 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3203 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3204 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3207 macro_warning (relax_substateT subtype
)
3209 if (subtype
& RELAX_DELAY_SLOT
)
3210 return _("Macro instruction expanded into multiple instructions"
3211 " in a branch delay slot");
3212 else if (subtype
& RELAX_NOMACRO
)
3213 return _("Macro instruction expanded into multiple instructions");
3218 /* Finish up a macro. Emit warnings as appropriate. */
3223 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3225 relax_substateT subtype
;
3227 /* Set up the relaxation warning flags. */
3229 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3230 subtype
|= RELAX_SECOND_LONGER
;
3231 if (mips_opts
.warn_about_macros
)
3232 subtype
|= RELAX_NOMACRO
;
3233 if (mips_macro_warning
.delay_slot_p
)
3234 subtype
|= RELAX_DELAY_SLOT
;
3236 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3238 /* Either the macro has a single implementation or both
3239 implementations are longer than 4 bytes. Emit the
3241 const char *msg
= macro_warning (subtype
);
3247 /* One implementation might need a warning but the other
3248 definitely doesn't. */
3249 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3254 /* Read a macro's relocation codes from *ARGS and store them in *R.
3255 The first argument in *ARGS will be either the code for a single
3256 relocation or -1 followed by the three codes that make up a
3257 composite relocation. */
3260 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3264 next
= va_arg (*args
, int);
3266 r
[0] = (bfd_reloc_code_real_type
) next
;
3268 for (i
= 0; i
< 3; i
++)
3269 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3272 /* Build an instruction created by a macro expansion. This is passed
3273 a pointer to the count of instructions created so far, an
3274 expression, the name of the instruction to build, an operand format
3275 string, and corresponding arguments. */
3278 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3280 const struct mips_opcode
*mo
;
3281 struct mips_cl_insn insn
;
3282 bfd_reloc_code_real_type r
[3];
3285 va_start (args
, fmt
);
3287 if (mips_opts
.mips16
)
3289 mips16_macro_build (ep
, name
, fmt
, args
);
3294 r
[0] = BFD_RELOC_UNUSED
;
3295 r
[1] = BFD_RELOC_UNUSED
;
3296 r
[2] = BFD_RELOC_UNUSED
;
3297 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3299 assert (strcmp (name
, mo
->name
) == 0);
3301 /* Search until we get a match for NAME. It is assumed here that
3302 macros will never generate MDMX, MIPS-3D, DSP or MT instructions. */
3303 while (strcmp (fmt
, mo
->args
) != 0
3304 || mo
->pinfo
== INSN_MACRO
3305 || !OPCODE_IS_MEMBER (mo
,
3307 | (mips_opts
.mips16
? INSN_MIPS16
: 0)
3308 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
3310 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
3314 assert (strcmp (name
, mo
->name
) == 0);
3317 create_insn (&insn
, mo
);
3335 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3340 /* Note that in the macro case, these arguments are already
3341 in MSB form. (When handling the instruction in the
3342 non-macro case, these arguments are sizes from which
3343 MSB values must be calculated.) */
3344 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3350 /* Note that in the macro case, these arguments are already
3351 in MSBD form. (When handling the instruction in the
3352 non-macro case, these arguments are sizes from which
3353 MSBD values must be calculated.) */
3354 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3365 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3369 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3374 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3380 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3385 int tmp
= va_arg (args
, int);
3387 INSERT_OPERAND (RT
, insn
, tmp
);
3388 INSERT_OPERAND (RD
, insn
, tmp
);
3394 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3401 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3405 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3409 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3413 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3417 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3424 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3430 macro_read_relocs (&args
, r
);
3431 assert (*r
== BFD_RELOC_GPREL16
3432 || *r
== BFD_RELOC_MIPS_LITERAL
3433 || *r
== BFD_RELOC_MIPS_HIGHER
3434 || *r
== BFD_RELOC_HI16_S
3435 || *r
== BFD_RELOC_LO16
3436 || *r
== BFD_RELOC_MIPS_GOT16
3437 || *r
== BFD_RELOC_MIPS_CALL16
3438 || *r
== BFD_RELOC_MIPS_GOT_DISP
3439 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3440 || *r
== BFD_RELOC_MIPS_GOT_OFST
3441 || *r
== BFD_RELOC_MIPS_GOT_LO16
3442 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3446 macro_read_relocs (&args
, r
);
3448 && (ep
->X_op
== O_constant
3449 || (ep
->X_op
== O_symbol
3450 && (*r
== BFD_RELOC_MIPS_HIGHEST
3451 || *r
== BFD_RELOC_HI16_S
3452 || *r
== BFD_RELOC_HI16
3453 || *r
== BFD_RELOC_GPREL16
3454 || *r
== BFD_RELOC_MIPS_GOT_HI16
3455 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3459 assert (ep
!= NULL
);
3462 * This allows macro() to pass an immediate expression for
3463 * creating short branches without creating a symbol.
3465 * We don't allow branch relaxation for these branches, as
3466 * they should only appear in ".set nomacro" anyway.
3468 if (ep
->X_op
== O_constant
)
3470 if ((ep
->X_add_number
& 3) != 0)
3471 as_bad (_("branch to misaligned address (0x%lx)"),
3472 (unsigned long) ep
->X_add_number
);
3473 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3474 as_bad (_("branch address range overflow (0x%lx)"),
3475 (unsigned long) ep
->X_add_number
);
3476 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3480 *r
= BFD_RELOC_16_PCREL_S2
;
3484 assert (ep
!= NULL
);
3485 *r
= BFD_RELOC_MIPS_JMP
;
3489 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3493 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3502 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3504 append_insn (&insn
, ep
, r
);
3508 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3511 struct mips_opcode
*mo
;
3512 struct mips_cl_insn insn
;
3513 bfd_reloc_code_real_type r
[3]
3514 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3516 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3518 assert (strcmp (name
, mo
->name
) == 0);
3520 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3524 assert (strcmp (name
, mo
->name
) == 0);
3527 create_insn (&insn
, mo
);
3545 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3550 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3554 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3558 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3568 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3575 regno
= va_arg (args
, int);
3576 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3577 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3598 assert (ep
!= NULL
);
3600 if (ep
->X_op
!= O_constant
)
3601 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3604 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3605 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3608 *r
= BFD_RELOC_UNUSED
;
3614 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3621 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3623 append_insn (&insn
, ep
, r
);
3627 * Sign-extend 32-bit mode constants that have bit 31 set and all
3628 * higher bits unset.
3631 normalize_constant_expr (expressionS
*ex
)
3633 if (ex
->X_op
== O_constant
3634 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3635 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3640 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3641 * all higher bits unset.
3644 normalize_address_expr (expressionS
*ex
)
3646 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3647 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3648 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3649 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3654 * Generate a "jalr" instruction with a relocation hint to the called
3655 * function. This occurs in NewABI PIC code.
3658 macro_build_jalr (expressionS
*ep
)
3667 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3669 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3670 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3674 * Generate a "lui" instruction.
3677 macro_build_lui (expressionS
*ep
, int regnum
)
3679 expressionS high_expr
;
3680 const struct mips_opcode
*mo
;
3681 struct mips_cl_insn insn
;
3682 bfd_reloc_code_real_type r
[3]
3683 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3684 const char *name
= "lui";
3685 const char *fmt
= "t,u";
3687 assert (! mips_opts
.mips16
);
3691 if (high_expr
.X_op
== O_constant
)
3693 /* we can compute the instruction now without a relocation entry */
3694 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3696 *r
= BFD_RELOC_UNUSED
;
3700 assert (ep
->X_op
== O_symbol
);
3701 /* _gp_disp is a special case, used from s_cpload.
3702 __gnu_local_gp is used if mips_no_shared. */
3703 assert (mips_pic
== NO_PIC
3705 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3706 || (! mips_in_shared
3707 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3708 "__gnu_local_gp") == 0));
3709 *r
= BFD_RELOC_HI16_S
;
3712 mo
= hash_find (op_hash
, name
);
3713 assert (strcmp (name
, mo
->name
) == 0);
3714 assert (strcmp (fmt
, mo
->args
) == 0);
3715 create_insn (&insn
, mo
);
3717 insn
.insn_opcode
= insn
.insn_mo
->match
;
3718 INSERT_OPERAND (RT
, insn
, regnum
);
3719 if (*r
== BFD_RELOC_UNUSED
)
3721 insn
.insn_opcode
|= high_expr
.X_add_number
;
3722 append_insn (&insn
, NULL
, r
);
3725 append_insn (&insn
, &high_expr
, r
);
3728 /* Generate a sequence of instructions to do a load or store from a constant
3729 offset off of a base register (breg) into/from a target register (treg),
3730 using AT if necessary. */
3732 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3733 int treg
, int breg
, int dbl
)
3735 assert (ep
->X_op
== O_constant
);
3737 /* Sign-extending 32-bit constants makes their handling easier. */
3739 normalize_constant_expr (ep
);
3741 /* Right now, this routine can only handle signed 32-bit constants. */
3742 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3743 as_warn (_("operand overflow"));
3745 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3747 /* Signed 16-bit offset will fit in the op. Easy! */
3748 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3752 /* 32-bit offset, need multiple instructions and AT, like:
3753 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3754 addu $tempreg,$tempreg,$breg
3755 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3756 to handle the complete offset. */
3757 macro_build_lui (ep
, AT
);
3758 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3759 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3762 as_bad (_("Macro used $at after \".set noat\""));
3767 * Generates code to set the $at register to true (one)
3768 * if reg is less than the immediate expression.
3771 set_at (int reg
, int unsignedp
)
3773 if (imm_expr
.X_op
== O_constant
3774 && imm_expr
.X_add_number
>= -0x8000
3775 && imm_expr
.X_add_number
< 0x8000)
3776 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3777 AT
, reg
, BFD_RELOC_LO16
);
3780 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3781 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3785 /* Warn if an expression is not a constant. */
3788 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3790 if (ex
->X_op
== O_big
)
3791 as_bad (_("unsupported large constant"));
3792 else if (ex
->X_op
!= O_constant
)
3793 as_bad (_("Instruction %s requires absolute expression"),
3796 if (HAVE_32BIT_GPRS
)
3797 normalize_constant_expr (ex
);
3800 /* Count the leading zeroes by performing a binary chop. This is a
3801 bulky bit of source, but performance is a LOT better for the
3802 majority of values than a simple loop to count the bits:
3803 for (lcnt = 0; (lcnt < 32); lcnt++)
3804 if ((v) & (1 << (31 - lcnt)))
3806 However it is not code size friendly, and the gain will drop a bit
3807 on certain cached systems.
3809 #define COUNT_TOP_ZEROES(v) \
3810 (((v) & ~0xffff) == 0 \
3811 ? ((v) & ~0xff) == 0 \
3812 ? ((v) & ~0xf) == 0 \
3813 ? ((v) & ~0x3) == 0 \
3814 ? ((v) & ~0x1) == 0 \
3819 : ((v) & ~0x7) == 0 \
3822 : ((v) & ~0x3f) == 0 \
3823 ? ((v) & ~0x1f) == 0 \
3826 : ((v) & ~0x7f) == 0 \
3829 : ((v) & ~0xfff) == 0 \
3830 ? ((v) & ~0x3ff) == 0 \
3831 ? ((v) & ~0x1ff) == 0 \
3834 : ((v) & ~0x7ff) == 0 \
3837 : ((v) & ~0x3fff) == 0 \
3838 ? ((v) & ~0x1fff) == 0 \
3841 : ((v) & ~0x7fff) == 0 \
3844 : ((v) & ~0xffffff) == 0 \
3845 ? ((v) & ~0xfffff) == 0 \
3846 ? ((v) & ~0x3ffff) == 0 \
3847 ? ((v) & ~0x1ffff) == 0 \
3850 : ((v) & ~0x7ffff) == 0 \
3853 : ((v) & ~0x3fffff) == 0 \
3854 ? ((v) & ~0x1fffff) == 0 \
3857 : ((v) & ~0x7fffff) == 0 \
3860 : ((v) & ~0xfffffff) == 0 \
3861 ? ((v) & ~0x3ffffff) == 0 \
3862 ? ((v) & ~0x1ffffff) == 0 \
3865 : ((v) & ~0x7ffffff) == 0 \
3868 : ((v) & ~0x3fffffff) == 0 \
3869 ? ((v) & ~0x1fffffff) == 0 \
3872 : ((v) & ~0x7fffffff) == 0 \
3877 * This routine generates the least number of instructions necessary to load
3878 * an absolute expression value into a register.
3881 load_register (int reg
, expressionS
*ep
, int dbl
)
3884 expressionS hi32
, lo32
;
3886 if (ep
->X_op
!= O_big
)
3888 assert (ep
->X_op
== O_constant
);
3890 /* Sign-extending 32-bit constants makes their handling easier. */
3892 normalize_constant_expr (ep
);
3894 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3896 /* We can handle 16 bit signed values with an addiu to
3897 $zero. No need to ever use daddiu here, since $zero and
3898 the result are always correct in 32 bit mode. */
3899 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3902 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3904 /* We can handle 16 bit unsigned values with an ori to
3906 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3909 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3911 /* 32 bit values require an lui. */
3912 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3913 if ((ep
->X_add_number
& 0xffff) != 0)
3914 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3919 /* The value is larger than 32 bits. */
3921 if (!dbl
|| HAVE_32BIT_GPRS
)
3925 sprintf_vma (value
, ep
->X_add_number
);
3926 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
3927 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3931 if (ep
->X_op
!= O_big
)
3934 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3935 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3936 hi32
.X_add_number
&= 0xffffffff;
3938 lo32
.X_add_number
&= 0xffffffff;
3942 assert (ep
->X_add_number
> 2);
3943 if (ep
->X_add_number
== 3)
3944 generic_bignum
[3] = 0;
3945 else if (ep
->X_add_number
> 4)
3946 as_bad (_("Number larger than 64 bits"));
3947 lo32
.X_op
= O_constant
;
3948 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3949 hi32
.X_op
= O_constant
;
3950 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3953 if (hi32
.X_add_number
== 0)
3958 unsigned long hi
, lo
;
3960 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3962 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3964 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3967 if (lo32
.X_add_number
& 0x80000000)
3969 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3970 if (lo32
.X_add_number
& 0xffff)
3971 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3976 /* Check for 16bit shifted constant. We know that hi32 is
3977 non-zero, so start the mask on the first bit of the hi32
3982 unsigned long himask
, lomask
;
3986 himask
= 0xffff >> (32 - shift
);
3987 lomask
= (0xffff << shift
) & 0xffffffff;
3991 himask
= 0xffff << (shift
- 32);
3994 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3995 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3999 tmp
.X_op
= O_constant
;
4001 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4002 | (lo32
.X_add_number
>> shift
));
4004 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4005 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4006 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4007 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4012 while (shift
<= (64 - 16));
4014 /* Find the bit number of the lowest one bit, and store the
4015 shifted value in hi/lo. */
4016 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4017 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4021 while ((lo
& 1) == 0)
4026 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4032 while ((hi
& 1) == 0)
4041 /* Optimize if the shifted value is a (power of 2) - 1. */
4042 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4043 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4045 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4050 /* This instruction will set the register to be all
4052 tmp
.X_op
= O_constant
;
4053 tmp
.X_add_number
= (offsetT
) -1;
4054 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4058 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4059 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4061 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4062 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4067 /* Sign extend hi32 before calling load_register, because we can
4068 generally get better code when we load a sign extended value. */
4069 if ((hi32
.X_add_number
& 0x80000000) != 0)
4070 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4071 load_register (reg
, &hi32
, 0);
4074 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4078 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4086 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4088 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4089 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4095 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4099 mid16
.X_add_number
>>= 16;
4100 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4101 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4104 if ((lo32
.X_add_number
& 0xffff) != 0)
4105 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4109 load_delay_nop (void)
4111 if (!gpr_interlocks
)
4112 macro_build (NULL
, "nop", "");
4115 /* Load an address into a register. */
4118 load_address (int reg
, expressionS
*ep
, int *used_at
)
4120 if (ep
->X_op
!= O_constant
4121 && ep
->X_op
!= O_symbol
)
4123 as_bad (_("expression too complex"));
4124 ep
->X_op
= O_constant
;
4127 if (ep
->X_op
== O_constant
)
4129 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4133 if (mips_pic
== NO_PIC
)
4135 /* If this is a reference to a GP relative symbol, we want
4136 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4138 lui $reg,<sym> (BFD_RELOC_HI16_S)
4139 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4140 If we have an addend, we always use the latter form.
4142 With 64bit address space and a usable $at we want
4143 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4144 lui $at,<sym> (BFD_RELOC_HI16_S)
4145 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4146 daddiu $at,<sym> (BFD_RELOC_LO16)
4150 If $at is already in use, we use a path which is suboptimal
4151 on superscalar processors.
4152 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4153 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4155 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4157 daddiu $reg,<sym> (BFD_RELOC_LO16)
4159 For GP relative symbols in 64bit address space we can use
4160 the same sequence as in 32bit address space. */
4161 if (HAVE_64BIT_SYMBOLS
)
4163 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4164 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4166 relax_start (ep
->X_add_symbol
);
4167 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4168 mips_gp_register
, BFD_RELOC_GPREL16
);
4172 if (*used_at
== 0 && !mips_opts
.noat
)
4174 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4175 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4176 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4177 BFD_RELOC_MIPS_HIGHER
);
4178 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4179 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4180 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4185 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4186 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4187 BFD_RELOC_MIPS_HIGHER
);
4188 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4189 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4190 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4191 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4194 if (mips_relax
.sequence
)
4199 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4200 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4202 relax_start (ep
->X_add_symbol
);
4203 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4204 mips_gp_register
, BFD_RELOC_GPREL16
);
4207 macro_build_lui (ep
, reg
);
4208 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4209 reg
, reg
, BFD_RELOC_LO16
);
4210 if (mips_relax
.sequence
)
4214 else if (!mips_big_got
)
4218 /* If this is a reference to an external symbol, we want
4219 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4221 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4223 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4224 If there is a constant, it must be added in after.
4226 If we have NewABI, we want
4227 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4228 unless we're referencing a global symbol with a non-zero
4229 offset, in which case cst must be added separately. */
4232 if (ep
->X_add_number
)
4234 ex
.X_add_number
= ep
->X_add_number
;
4235 ep
->X_add_number
= 0;
4236 relax_start (ep
->X_add_symbol
);
4237 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4238 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4239 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4240 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4241 ex
.X_op
= O_constant
;
4242 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4243 reg
, reg
, BFD_RELOC_LO16
);
4244 ep
->X_add_number
= ex
.X_add_number
;
4247 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4248 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4249 if (mips_relax
.sequence
)
4254 ex
.X_add_number
= ep
->X_add_number
;
4255 ep
->X_add_number
= 0;
4256 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4257 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4259 relax_start (ep
->X_add_symbol
);
4261 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4265 if (ex
.X_add_number
!= 0)
4267 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4268 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4269 ex
.X_op
= O_constant
;
4270 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4271 reg
, reg
, BFD_RELOC_LO16
);
4275 else if (mips_big_got
)
4279 /* This is the large GOT case. If this is a reference to an
4280 external symbol, we want
4281 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4283 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4285 Otherwise, for a reference to a local symbol in old ABI, we want
4286 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4288 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4289 If there is a constant, it must be added in after.
4291 In the NewABI, for local symbols, with or without offsets, we want:
4292 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4293 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4297 ex
.X_add_number
= ep
->X_add_number
;
4298 ep
->X_add_number
= 0;
4299 relax_start (ep
->X_add_symbol
);
4300 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4301 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4302 reg
, reg
, mips_gp_register
);
4303 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4304 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4305 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4306 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4307 else if (ex
.X_add_number
)
4309 ex
.X_op
= O_constant
;
4310 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4314 ep
->X_add_number
= ex
.X_add_number
;
4316 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4317 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4318 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4319 BFD_RELOC_MIPS_GOT_OFST
);
4324 ex
.X_add_number
= ep
->X_add_number
;
4325 ep
->X_add_number
= 0;
4326 relax_start (ep
->X_add_symbol
);
4327 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4328 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4329 reg
, reg
, mips_gp_register
);
4330 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4331 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4333 if (reg_needs_delay (mips_gp_register
))
4335 /* We need a nop before loading from $gp. This special
4336 check is required because the lui which starts the main
4337 instruction stream does not refer to $gp, and so will not
4338 insert the nop which may be required. */
4339 macro_build (NULL
, "nop", "");
4341 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4342 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4344 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4348 if (ex
.X_add_number
!= 0)
4350 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4351 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4352 ex
.X_op
= O_constant
;
4353 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4361 if (mips_opts
.noat
&& *used_at
== 1)
4362 as_bad (_("Macro used $at after \".set noat\""));
4365 /* Move the contents of register SOURCE into register DEST. */
4368 move_register (int dest
, int source
)
4370 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4374 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4375 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4376 The two alternatives are:
4378 Global symbol Local sybmol
4379 ------------- ------------
4380 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4382 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4384 load_got_offset emits the first instruction and add_got_offset
4385 emits the second for a 16-bit offset or add_got_offset_hilo emits
4386 a sequence to add a 32-bit offset using a scratch register. */
4389 load_got_offset (int dest
, expressionS
*local
)
4394 global
.X_add_number
= 0;
4396 relax_start (local
->X_add_symbol
);
4397 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4398 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4400 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4401 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4406 add_got_offset (int dest
, expressionS
*local
)
4410 global
.X_op
= O_constant
;
4411 global
.X_op_symbol
= NULL
;
4412 global
.X_add_symbol
= NULL
;
4413 global
.X_add_number
= local
->X_add_number
;
4415 relax_start (local
->X_add_symbol
);
4416 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4417 dest
, dest
, BFD_RELOC_LO16
);
4419 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4424 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4427 int hold_mips_optimize
;
4429 global
.X_op
= O_constant
;
4430 global
.X_op_symbol
= NULL
;
4431 global
.X_add_symbol
= NULL
;
4432 global
.X_add_number
= local
->X_add_number
;
4434 relax_start (local
->X_add_symbol
);
4435 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4437 /* Set mips_optimize around the lui instruction to avoid
4438 inserting an unnecessary nop after the lw. */
4439 hold_mips_optimize
= mips_optimize
;
4441 macro_build_lui (&global
, tmp
);
4442 mips_optimize
= hold_mips_optimize
;
4443 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4446 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4451 * This routine implements the seemingly endless macro or synthesized
4452 * instructions and addressing modes in the mips assembly language. Many
4453 * of these macros are simple and are similar to each other. These could
4454 * probably be handled by some kind of table or grammar approach instead of
4455 * this verbose method. Others are not simple macros but are more like
4456 * optimizing code generation.
4457 * One interesting optimization is when several store macros appear
4458 * consecutively that would load AT with the upper half of the same address.
4459 * The ensuing load upper instructions are ommited. This implies some kind
4460 * of global optimization. We currently only optimize within a single macro.
4461 * For many of the load and store macros if the address is specified as a
4462 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4463 * first load register 'at' with zero and use it as the base register. The
4464 * mips assembler simply uses register $zero. Just one tiny optimization
4468 macro (struct mips_cl_insn
*ip
)
4470 int treg
, sreg
, dreg
, breg
;
4486 bfd_reloc_code_real_type r
;
4487 int hold_mips_optimize
;
4489 assert (! mips_opts
.mips16
);
4491 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4492 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4493 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4494 mask
= ip
->insn_mo
->mask
;
4496 expr1
.X_op
= O_constant
;
4497 expr1
.X_op_symbol
= NULL
;
4498 expr1
.X_add_symbol
= NULL
;
4499 expr1
.X_add_number
= 1;
4513 expr1
.X_add_number
= 8;
4514 macro_build (&expr1
, "bgez", "s,p", sreg
);
4516 macro_build (NULL
, "nop", "", 0);
4518 move_register (dreg
, sreg
);
4519 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4542 if (imm_expr
.X_op
== O_constant
4543 && imm_expr
.X_add_number
>= -0x8000
4544 && imm_expr
.X_add_number
< 0x8000)
4546 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4550 load_register (AT
, &imm_expr
, dbl
);
4551 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4570 if (imm_expr
.X_op
== O_constant
4571 && imm_expr
.X_add_number
>= 0
4572 && imm_expr
.X_add_number
< 0x10000)
4574 if (mask
!= M_NOR_I
)
4575 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4578 macro_build (&imm_expr
, "ori", "t,r,i",
4579 treg
, sreg
, BFD_RELOC_LO16
);
4580 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4586 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4587 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4604 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4606 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4610 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4611 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4619 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4624 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4628 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4629 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4635 /* check for > max integer */
4636 maxnum
= 0x7fffffff;
4637 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4644 if (imm_expr
.X_op
== O_constant
4645 && imm_expr
.X_add_number
>= maxnum
4646 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4649 /* result is always false */
4651 macro_build (NULL
, "nop", "", 0);
4653 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4656 if (imm_expr
.X_op
!= O_constant
)
4657 as_bad (_("Unsupported large constant"));
4658 ++imm_expr
.X_add_number
;
4662 if (mask
== M_BGEL_I
)
4664 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4666 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4669 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4671 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4674 maxnum
= 0x7fffffff;
4675 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4682 maxnum
= - maxnum
- 1;
4683 if (imm_expr
.X_op
== O_constant
4684 && imm_expr
.X_add_number
<= maxnum
4685 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4688 /* result is always true */
4689 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4690 macro_build (&offset_expr
, "b", "p");
4695 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4705 macro_build (&offset_expr
, likely
? "beql" : "beq",
4710 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4711 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4719 && imm_expr
.X_op
== O_constant
4720 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4722 if (imm_expr
.X_op
!= O_constant
)
4723 as_bad (_("Unsupported large constant"));
4724 ++imm_expr
.X_add_number
;
4728 if (mask
== M_BGEUL_I
)
4730 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4732 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4734 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4740 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4748 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4753 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4757 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4758 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4766 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4773 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4774 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4782 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4787 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4791 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4792 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4798 maxnum
= 0x7fffffff;
4799 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4806 if (imm_expr
.X_op
== O_constant
4807 && imm_expr
.X_add_number
>= maxnum
4808 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4810 if (imm_expr
.X_op
!= O_constant
)
4811 as_bad (_("Unsupported large constant"));
4812 ++imm_expr
.X_add_number
;
4816 if (mask
== M_BLTL_I
)
4818 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4820 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4823 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4825 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4830 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4838 macro_build (&offset_expr
, likely
? "beql" : "beq",
4845 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4846 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4854 && imm_expr
.X_op
== O_constant
4855 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4857 if (imm_expr
.X_op
!= O_constant
)
4858 as_bad (_("Unsupported large constant"));
4859 ++imm_expr
.X_add_number
;
4863 if (mask
== M_BLTUL_I
)
4865 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4867 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4869 macro_build (&offset_expr
, likely
? "beql" : "beq",
4875 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4883 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4888 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4892 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4893 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4903 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4908 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4909 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4917 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4919 as_bad (_("Unsupported large constant"));
4924 pos
= (unsigned long) imm_expr
.X_add_number
;
4925 size
= (unsigned long) imm2_expr
.X_add_number
;
4930 as_bad (_("Improper position (%lu)"), pos
);
4933 if (size
== 0 || size
> 64
4934 || (pos
+ size
- 1) > 63)
4936 as_bad (_("Improper extract size (%lu, position %lu)"),
4941 if (size
<= 32 && pos
< 32)
4946 else if (size
<= 32)
4956 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4965 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4967 as_bad (_("Unsupported large constant"));
4972 pos
= (unsigned long) imm_expr
.X_add_number
;
4973 size
= (unsigned long) imm2_expr
.X_add_number
;
4978 as_bad (_("Improper position (%lu)"), pos
);
4981 if (size
== 0 || size
> 64
4982 || (pos
+ size
- 1) > 63)
4984 as_bad (_("Improper insert size (%lu, position %lu)"),
4989 if (pos
< 32 && (pos
+ size
- 1) < 32)
5004 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
5021 as_warn (_("Divide by zero."));
5023 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5025 macro_build (NULL
, "break", "c", 7);
5032 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5033 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5037 expr1
.X_add_number
= 8;
5038 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5039 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5040 macro_build (NULL
, "break", "c", 7);
5042 expr1
.X_add_number
= -1;
5044 load_register (AT
, &expr1
, dbl
);
5045 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5046 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5049 expr1
.X_add_number
= 1;
5050 load_register (AT
, &expr1
, dbl
);
5051 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5055 expr1
.X_add_number
= 0x80000000;
5056 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5060 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5061 /* We want to close the noreorder block as soon as possible, so
5062 that later insns are available for delay slot filling. */
5067 expr1
.X_add_number
= 8;
5068 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5069 macro_build (NULL
, "nop", "", 0);
5071 /* We want to close the noreorder block as soon as possible, so
5072 that later insns are available for delay slot filling. */
5075 macro_build (NULL
, "break", "c", 6);
5077 macro_build (NULL
, s
, "d", dreg
);
5116 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5118 as_warn (_("Divide by zero."));
5120 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5122 macro_build (NULL
, "break", "c", 7);
5125 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5127 if (strcmp (s2
, "mflo") == 0)
5128 move_register (dreg
, sreg
);
5130 move_register (dreg
, 0);
5133 if (imm_expr
.X_op
== O_constant
5134 && imm_expr
.X_add_number
== -1
5135 && s
[strlen (s
) - 1] != 'u')
5137 if (strcmp (s2
, "mflo") == 0)
5139 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5142 move_register (dreg
, 0);
5147 load_register (AT
, &imm_expr
, dbl
);
5148 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5149 macro_build (NULL
, s2
, "d", dreg
);
5171 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5172 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5173 /* We want to close the noreorder block as soon as possible, so
5174 that later insns are available for delay slot filling. */
5179 expr1
.X_add_number
= 8;
5180 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5181 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5183 /* We want to close the noreorder block as soon as possible, so
5184 that later insns are available for delay slot filling. */
5186 macro_build (NULL
, "break", "c", 7);
5188 macro_build (NULL
, s2
, "d", dreg
);
5200 /* Load the address of a symbol into a register. If breg is not
5201 zero, we then add a base register to it. */
5203 if (dbl
&& HAVE_32BIT_GPRS
)
5204 as_warn (_("dla used to load 32-bit register"));
5206 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5207 as_warn (_("la used to load 64-bit address"));
5209 if (offset_expr
.X_op
== O_constant
5210 && offset_expr
.X_add_number
>= -0x8000
5211 && offset_expr
.X_add_number
< 0x8000)
5213 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5214 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5218 if (!mips_opts
.noat
&& (treg
== breg
))
5228 if (offset_expr
.X_op
!= O_symbol
5229 && offset_expr
.X_op
!= O_constant
)
5231 as_bad (_("expression too complex"));
5232 offset_expr
.X_op
= O_constant
;
5235 if (offset_expr
.X_op
== O_constant
)
5236 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5237 else if (mips_pic
== NO_PIC
)
5239 /* If this is a reference to a GP relative symbol, we want
5240 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5242 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5243 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5244 If we have a constant, we need two instructions anyhow,
5245 so we may as well always use the latter form.
5247 With 64bit address space and a usable $at we want
5248 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5249 lui $at,<sym> (BFD_RELOC_HI16_S)
5250 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5251 daddiu $at,<sym> (BFD_RELOC_LO16)
5253 daddu $tempreg,$tempreg,$at
5255 If $at is already in use, we use a path which is suboptimal
5256 on superscalar processors.
5257 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5258 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5260 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5262 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5264 For GP relative symbols in 64bit address space we can use
5265 the same sequence as in 32bit address space. */
5266 if (HAVE_64BIT_SYMBOLS
)
5268 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5269 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5271 relax_start (offset_expr
.X_add_symbol
);
5272 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5273 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5277 if (used_at
== 0 && !mips_opts
.noat
)
5279 macro_build (&offset_expr
, "lui", "t,u",
5280 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5281 macro_build (&offset_expr
, "lui", "t,u",
5282 AT
, BFD_RELOC_HI16_S
);
5283 macro_build (&offset_expr
, "daddiu", "t,r,j",
5284 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5285 macro_build (&offset_expr
, "daddiu", "t,r,j",
5286 AT
, AT
, BFD_RELOC_LO16
);
5287 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5288 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5293 macro_build (&offset_expr
, "lui", "t,u",
5294 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5295 macro_build (&offset_expr
, "daddiu", "t,r,j",
5296 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5297 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5298 macro_build (&offset_expr
, "daddiu", "t,r,j",
5299 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5300 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5301 macro_build (&offset_expr
, "daddiu", "t,r,j",
5302 tempreg
, tempreg
, BFD_RELOC_LO16
);
5305 if (mips_relax
.sequence
)
5310 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5311 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5313 relax_start (offset_expr
.X_add_symbol
);
5314 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5315 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5318 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5319 as_bad (_("offset too large"));
5320 macro_build_lui (&offset_expr
, tempreg
);
5321 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5322 tempreg
, tempreg
, BFD_RELOC_LO16
);
5323 if (mips_relax
.sequence
)
5327 else if (!mips_big_got
&& !HAVE_NEWABI
)
5329 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5331 /* If this is a reference to an external symbol, and there
5332 is no constant, we want
5333 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5334 or for lca or if tempreg is PIC_CALL_REG
5335 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5336 For a local symbol, we want
5337 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5339 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5341 If we have a small constant, and this is a reference to
5342 an external symbol, we want
5343 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5345 addiu $tempreg,$tempreg,<constant>
5346 For a local symbol, we want the same instruction
5347 sequence, but we output a BFD_RELOC_LO16 reloc on the
5350 If we have a large constant, and this is a reference to
5351 an external symbol, we want
5352 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5353 lui $at,<hiconstant>
5354 addiu $at,$at,<loconstant>
5355 addu $tempreg,$tempreg,$at
5356 For a local symbol, we want the same instruction
5357 sequence, but we output a BFD_RELOC_LO16 reloc on the
5361 if (offset_expr
.X_add_number
== 0)
5363 if (mips_pic
== SVR4_PIC
5365 && (call
|| tempreg
== PIC_CALL_REG
))
5366 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5368 relax_start (offset_expr
.X_add_symbol
);
5369 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5370 lw_reloc_type
, mips_gp_register
);
5373 /* We're going to put in an addu instruction using
5374 tempreg, so we may as well insert the nop right
5379 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5380 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5382 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5383 tempreg
, tempreg
, BFD_RELOC_LO16
);
5385 /* FIXME: If breg == 0, and the next instruction uses
5386 $tempreg, then if this variant case is used an extra
5387 nop will be generated. */
5389 else if (offset_expr
.X_add_number
>= -0x8000
5390 && offset_expr
.X_add_number
< 0x8000)
5392 load_got_offset (tempreg
, &offset_expr
);
5394 add_got_offset (tempreg
, &offset_expr
);
5398 expr1
.X_add_number
= offset_expr
.X_add_number
;
5399 offset_expr
.X_add_number
=
5400 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5401 load_got_offset (tempreg
, &offset_expr
);
5402 offset_expr
.X_add_number
= expr1
.X_add_number
;
5403 /* If we are going to add in a base register, and the
5404 target register and the base register are the same,
5405 then we are using AT as a temporary register. Since
5406 we want to load the constant into AT, we add our
5407 current AT (from the global offset table) and the
5408 register into the register now, and pretend we were
5409 not using a base register. */
5413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5418 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5422 else if (!mips_big_got
&& HAVE_NEWABI
)
5424 int add_breg_early
= 0;
5426 /* If this is a reference to an external, and there is no
5427 constant, or local symbol (*), with or without a
5429 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5430 or for lca or if tempreg is PIC_CALL_REG
5431 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5433 If we have a small constant, and this is a reference to
5434 an external symbol, we want
5435 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5436 addiu $tempreg,$tempreg,<constant>
5438 If we have a large constant, and this is a reference to
5439 an external symbol, we want
5440 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5441 lui $at,<hiconstant>
5442 addiu $at,$at,<loconstant>
5443 addu $tempreg,$tempreg,$at
5445 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5446 local symbols, even though it introduces an additional
5449 if (offset_expr
.X_add_number
)
5451 expr1
.X_add_number
= offset_expr
.X_add_number
;
5452 offset_expr
.X_add_number
= 0;
5454 relax_start (offset_expr
.X_add_symbol
);
5455 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5456 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5458 if (expr1
.X_add_number
>= -0x8000
5459 && expr1
.X_add_number
< 0x8000)
5461 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5462 tempreg
, tempreg
, BFD_RELOC_LO16
);
5464 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5468 /* If we are going to add in a base register, and the
5469 target register and the base register are the same,
5470 then we are using AT as a temporary register. Since
5471 we want to load the constant into AT, we add our
5472 current AT (from the global offset table) and the
5473 register into the register now, and pretend we were
5474 not using a base register. */
5479 assert (tempreg
== AT
);
5480 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5486 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5487 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5493 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5496 offset_expr
.X_add_number
= expr1
.X_add_number
;
5498 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5499 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5502 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5503 treg
, tempreg
, breg
);
5509 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5511 relax_start (offset_expr
.X_add_symbol
);
5512 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5513 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5515 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5516 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5521 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5522 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5525 else if (mips_big_got
&& !HAVE_NEWABI
)
5528 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5529 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5530 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5532 /* This is the large GOT case. If this is a reference to an
5533 external symbol, and there is no constant, we want
5534 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5535 addu $tempreg,$tempreg,$gp
5536 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5537 or for lca or if tempreg is PIC_CALL_REG
5538 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5539 addu $tempreg,$tempreg,$gp
5540 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5541 For a local symbol, we want
5542 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5544 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5546 If we have a small constant, and this is a reference to
5547 an external symbol, we want
5548 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5549 addu $tempreg,$tempreg,$gp
5550 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5552 addiu $tempreg,$tempreg,<constant>
5553 For a local symbol, we want
5554 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5556 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5558 If we have a large constant, and this is a reference to
5559 an external symbol, we want
5560 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5561 addu $tempreg,$tempreg,$gp
5562 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5563 lui $at,<hiconstant>
5564 addiu $at,$at,<loconstant>
5565 addu $tempreg,$tempreg,$at
5566 For a local symbol, we want
5567 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5568 lui $at,<hiconstant>
5569 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5570 addu $tempreg,$tempreg,$at
5573 expr1
.X_add_number
= offset_expr
.X_add_number
;
5574 offset_expr
.X_add_number
= 0;
5575 relax_start (offset_expr
.X_add_symbol
);
5576 gpdelay
= reg_needs_delay (mips_gp_register
);
5577 if (expr1
.X_add_number
== 0 && breg
== 0
5578 && (call
|| tempreg
== PIC_CALL_REG
))
5580 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5581 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5583 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5584 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5585 tempreg
, tempreg
, mips_gp_register
);
5586 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5587 tempreg
, lw_reloc_type
, tempreg
);
5588 if (expr1
.X_add_number
== 0)
5592 /* We're going to put in an addu instruction using
5593 tempreg, so we may as well insert the nop right
5598 else if (expr1
.X_add_number
>= -0x8000
5599 && expr1
.X_add_number
< 0x8000)
5602 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5603 tempreg
, tempreg
, BFD_RELOC_LO16
);
5609 /* If we are going to add in a base register, and the
5610 target register and the base register are the same,
5611 then we are using AT as a temporary register. Since
5612 we want to load the constant into AT, we add our
5613 current AT (from the global offset table) and the
5614 register into the register now, and pretend we were
5615 not using a base register. */
5620 assert (tempreg
== AT
);
5622 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5627 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5628 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5632 offset_expr
.X_add_number
=
5633 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5638 /* This is needed because this instruction uses $gp, but
5639 the first instruction on the main stream does not. */
5640 macro_build (NULL
, "nop", "");
5643 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5644 local_reloc_type
, mips_gp_register
);
5645 if (expr1
.X_add_number
>= -0x8000
5646 && expr1
.X_add_number
< 0x8000)
5649 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5650 tempreg
, tempreg
, BFD_RELOC_LO16
);
5651 /* FIXME: If add_number is 0, and there was no base
5652 register, the external symbol case ended with a load,
5653 so if the symbol turns out to not be external, and
5654 the next instruction uses tempreg, an unnecessary nop
5655 will be inserted. */
5661 /* We must add in the base register now, as in the
5662 external symbol case. */
5663 assert (tempreg
== AT
);
5665 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5668 /* We set breg to 0 because we have arranged to add
5669 it in in both cases. */
5673 macro_build_lui (&expr1
, AT
);
5674 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5675 AT
, AT
, BFD_RELOC_LO16
);
5676 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5677 tempreg
, tempreg
, AT
);
5682 else if (mips_big_got
&& HAVE_NEWABI
)
5684 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5685 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5686 int add_breg_early
= 0;
5688 /* This is the large GOT case. If this is a reference to an
5689 external symbol, and there is no constant, we want
5690 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5691 add $tempreg,$tempreg,$gp
5692 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5693 or for lca or if tempreg is PIC_CALL_REG
5694 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5695 add $tempreg,$tempreg,$gp
5696 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5698 If we have a small constant, and this is a reference to
5699 an external symbol, we want
5700 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5701 add $tempreg,$tempreg,$gp
5702 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5703 addi $tempreg,$tempreg,<constant>
5705 If we have a large constant, and this is a reference to
5706 an external symbol, we want
5707 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5708 addu $tempreg,$tempreg,$gp
5709 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5710 lui $at,<hiconstant>
5711 addi $at,$at,<loconstant>
5712 add $tempreg,$tempreg,$at
5714 If we have NewABI, and we know it's a local symbol, we want
5715 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5716 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5717 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5719 relax_start (offset_expr
.X_add_symbol
);
5721 expr1
.X_add_number
= offset_expr
.X_add_number
;
5722 offset_expr
.X_add_number
= 0;
5724 if (expr1
.X_add_number
== 0 && breg
== 0
5725 && (call
|| tempreg
== PIC_CALL_REG
))
5727 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5728 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5730 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5731 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5732 tempreg
, tempreg
, mips_gp_register
);
5733 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5734 tempreg
, lw_reloc_type
, tempreg
);
5736 if (expr1
.X_add_number
== 0)
5738 else if (expr1
.X_add_number
>= -0x8000
5739 && expr1
.X_add_number
< 0x8000)
5741 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5742 tempreg
, tempreg
, BFD_RELOC_LO16
);
5744 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5748 /* If we are going to add in a base register, and the
5749 target register and the base register are the same,
5750 then we are using AT as a temporary register. Since
5751 we want to load the constant into AT, we add our
5752 current AT (from the global offset table) and the
5753 register into the register now, and pretend we were
5754 not using a base register. */
5759 assert (tempreg
== AT
);
5760 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5766 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5767 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5772 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5775 offset_expr
.X_add_number
= expr1
.X_add_number
;
5776 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5777 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5778 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5779 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5782 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5783 treg
, tempreg
, breg
);
5793 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5797 /* The j instruction may not be used in PIC code, since it
5798 requires an absolute address. We convert it to a b
5800 if (mips_pic
== NO_PIC
)
5801 macro_build (&offset_expr
, "j", "a");
5803 macro_build (&offset_expr
, "b", "p");
5806 /* The jal instructions must be handled as macros because when
5807 generating PIC code they expand to multi-instruction
5808 sequences. Normally they are simple instructions. */
5813 if (mips_pic
== NO_PIC
)
5814 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5817 if (sreg
!= PIC_CALL_REG
)
5818 as_warn (_("MIPS PIC call to register other than $25"));
5820 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5821 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
5823 if (mips_cprestore_offset
< 0)
5824 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5827 if (! mips_frame_reg_valid
)
5829 as_warn (_("No .frame pseudo-op used in PIC code"));
5830 /* Quiet this warning. */
5831 mips_frame_reg_valid
= 1;
5833 if (! mips_cprestore_valid
)
5835 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5836 /* Quiet this warning. */
5837 mips_cprestore_valid
= 1;
5839 expr1
.X_add_number
= mips_cprestore_offset
;
5840 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5843 HAVE_64BIT_ADDRESSES
);
5851 if (mips_pic
== NO_PIC
)
5852 macro_build (&offset_expr
, "jal", "a");
5853 else if (mips_pic
== SVR4_PIC
)
5855 /* If this is a reference to an external symbol, and we are
5856 using a small GOT, we want
5857 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5861 lw $gp,cprestore($sp)
5862 The cprestore value is set using the .cprestore
5863 pseudo-op. If we are using a big GOT, we want
5864 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5866 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5870 lw $gp,cprestore($sp)
5871 If the symbol is not external, we want
5872 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5874 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5877 lw $gp,cprestore($sp)
5879 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5880 sequences above, minus nops, unless the symbol is local,
5881 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5887 relax_start (offset_expr
.X_add_symbol
);
5888 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5889 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5892 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5893 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5899 relax_start (offset_expr
.X_add_symbol
);
5900 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5901 BFD_RELOC_MIPS_CALL_HI16
);
5902 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5903 PIC_CALL_REG
, mips_gp_register
);
5904 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5905 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5908 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5909 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5911 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5912 PIC_CALL_REG
, PIC_CALL_REG
,
5913 BFD_RELOC_MIPS_GOT_OFST
);
5917 macro_build_jalr (&offset_expr
);
5921 relax_start (offset_expr
.X_add_symbol
);
5924 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5925 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5934 gpdelay
= reg_needs_delay (mips_gp_register
);
5935 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5936 BFD_RELOC_MIPS_CALL_HI16
);
5937 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5938 PIC_CALL_REG
, mips_gp_register
);
5939 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5940 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5945 macro_build (NULL
, "nop", "");
5947 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5948 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5951 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5952 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5954 macro_build_jalr (&offset_expr
);
5956 if (mips_cprestore_offset
< 0)
5957 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5960 if (! mips_frame_reg_valid
)
5962 as_warn (_("No .frame pseudo-op used in PIC code"));
5963 /* Quiet this warning. */
5964 mips_frame_reg_valid
= 1;
5966 if (! mips_cprestore_valid
)
5968 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5969 /* Quiet this warning. */
5970 mips_cprestore_valid
= 1;
5972 if (mips_opts
.noreorder
)
5973 macro_build (NULL
, "nop", "");
5974 expr1
.X_add_number
= mips_cprestore_offset
;
5975 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5978 HAVE_64BIT_ADDRESSES
);
5982 else if (mips_pic
== VXWORKS_PIC
)
5983 as_bad (_("Non-PIC jump used in PIC library"));
6006 /* Itbl support may require additional care here. */
6011 /* Itbl support may require additional care here. */
6016 /* Itbl support may require additional care here. */
6021 /* Itbl support may require additional care here. */
6033 if (mips_opts
.arch
== CPU_R4650
)
6035 as_bad (_("opcode not supported on this processor"));
6039 /* Itbl support may require additional care here. */
6044 /* Itbl support may require additional care here. */
6049 /* Itbl support may require additional care here. */
6069 if (breg
== treg
|| coproc
|| lr
)
6090 /* Itbl support may require additional care here. */
6095 /* Itbl support may require additional care here. */
6100 /* Itbl support may require additional care here. */
6105 /* Itbl support may require additional care here. */
6124 if (mips_opts
.arch
== CPU_R4650
)
6126 as_bad (_("opcode not supported on this processor"));
6131 /* Itbl support may require additional care here. */
6135 /* Itbl support may require additional care here. */
6140 /* Itbl support may require additional care here. */
6152 /* Itbl support may require additional care here. */
6153 if (mask
== M_LWC1_AB
6154 || mask
== M_SWC1_AB
6155 || mask
== M_LDC1_AB
6156 || mask
== M_SDC1_AB
6160 else if (mask
== M_CACHE_AB
)
6167 if (offset_expr
.X_op
!= O_constant
6168 && offset_expr
.X_op
!= O_symbol
)
6170 as_bad (_("expression too complex"));
6171 offset_expr
.X_op
= O_constant
;
6174 if (HAVE_32BIT_ADDRESSES
6175 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6179 sprintf_vma (value
, offset_expr
.X_add_number
);
6180 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6183 /* A constant expression in PIC code can be handled just as it
6184 is in non PIC code. */
6185 if (offset_expr
.X_op
== O_constant
)
6187 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6188 & ~(bfd_vma
) 0xffff);
6189 normalize_address_expr (&expr1
);
6190 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6192 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6193 tempreg
, tempreg
, breg
);
6194 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6196 else if (mips_pic
== NO_PIC
)
6198 /* If this is a reference to a GP relative symbol, and there
6199 is no base register, we want
6200 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6201 Otherwise, if there is no base register, we want
6202 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6203 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6204 If we have a constant, we need two instructions anyhow,
6205 so we always use the latter form.
6207 If we have a base register, and this is a reference to a
6208 GP relative symbol, we want
6209 addu $tempreg,$breg,$gp
6210 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6212 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6213 addu $tempreg,$tempreg,$breg
6214 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6215 With a constant we always use the latter case.
6217 With 64bit address space and no base register and $at usable,
6219 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6220 lui $at,<sym> (BFD_RELOC_HI16_S)
6221 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6224 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6225 If we have a base register, we want
6226 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6227 lui $at,<sym> (BFD_RELOC_HI16_S)
6228 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6232 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6234 Without $at we can't generate the optimal path for superscalar
6235 processors here since this would require two temporary registers.
6236 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6237 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6239 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6241 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6242 If we have a base register, we want
6243 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6244 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6246 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6248 daddu $tempreg,$tempreg,$breg
6249 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6251 For GP relative symbols in 64bit address space we can use
6252 the same sequence as in 32bit address space. */
6253 if (HAVE_64BIT_SYMBOLS
)
6255 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6256 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6258 relax_start (offset_expr
.X_add_symbol
);
6261 macro_build (&offset_expr
, s
, fmt
, treg
,
6262 BFD_RELOC_GPREL16
, mips_gp_register
);
6266 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6267 tempreg
, breg
, mips_gp_register
);
6268 macro_build (&offset_expr
, s
, fmt
, treg
,
6269 BFD_RELOC_GPREL16
, tempreg
);
6274 if (used_at
== 0 && !mips_opts
.noat
)
6276 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6277 BFD_RELOC_MIPS_HIGHEST
);
6278 macro_build (&offset_expr
, "lui", "t,u", AT
,
6280 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6281 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6283 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6284 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6285 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6286 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6292 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6293 BFD_RELOC_MIPS_HIGHEST
);
6294 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6295 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6296 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6297 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6298 tempreg
, BFD_RELOC_HI16_S
);
6299 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6301 macro_build (NULL
, "daddu", "d,v,t",
6302 tempreg
, tempreg
, breg
);
6303 macro_build (&offset_expr
, s
, fmt
, treg
,
6304 BFD_RELOC_LO16
, tempreg
);
6307 if (mips_relax
.sequence
)
6314 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6315 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6317 relax_start (offset_expr
.X_add_symbol
);
6318 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6322 macro_build_lui (&offset_expr
, tempreg
);
6323 macro_build (&offset_expr
, s
, fmt
, treg
,
6324 BFD_RELOC_LO16
, tempreg
);
6325 if (mips_relax
.sequence
)
6330 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6331 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6333 relax_start (offset_expr
.X_add_symbol
);
6334 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6335 tempreg
, breg
, mips_gp_register
);
6336 macro_build (&offset_expr
, s
, fmt
, treg
,
6337 BFD_RELOC_GPREL16
, tempreg
);
6340 macro_build_lui (&offset_expr
, tempreg
);
6341 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6342 tempreg
, tempreg
, breg
);
6343 macro_build (&offset_expr
, s
, fmt
, treg
,
6344 BFD_RELOC_LO16
, tempreg
);
6345 if (mips_relax
.sequence
)
6349 else if (!mips_big_got
)
6351 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6353 /* If this is a reference to an external symbol, we want
6354 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6356 <op> $treg,0($tempreg)
6358 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6360 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6361 <op> $treg,0($tempreg)
6364 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6365 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6367 If there is a base register, we add it to $tempreg before
6368 the <op>. If there is a constant, we stick it in the
6369 <op> instruction. We don't handle constants larger than
6370 16 bits, because we have no way to load the upper 16 bits
6371 (actually, we could handle them for the subset of cases
6372 in which we are not using $at). */
6373 assert (offset_expr
.X_op
== O_symbol
);
6376 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6377 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6379 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6380 tempreg
, tempreg
, breg
);
6381 macro_build (&offset_expr
, s
, fmt
, treg
,
6382 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6385 expr1
.X_add_number
= offset_expr
.X_add_number
;
6386 offset_expr
.X_add_number
= 0;
6387 if (expr1
.X_add_number
< -0x8000
6388 || expr1
.X_add_number
>= 0x8000)
6389 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6390 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6391 lw_reloc_type
, mips_gp_register
);
6393 relax_start (offset_expr
.X_add_symbol
);
6395 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6396 tempreg
, BFD_RELOC_LO16
);
6399 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6400 tempreg
, tempreg
, breg
);
6401 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6403 else if (mips_big_got
&& !HAVE_NEWABI
)
6407 /* If this is a reference to an external symbol, we want
6408 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6409 addu $tempreg,$tempreg,$gp
6410 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6411 <op> $treg,0($tempreg)
6413 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6415 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6416 <op> $treg,0($tempreg)
6417 If there is a base register, we add it to $tempreg before
6418 the <op>. If there is a constant, we stick it in the
6419 <op> instruction. We don't handle constants larger than
6420 16 bits, because we have no way to load the upper 16 bits
6421 (actually, we could handle them for the subset of cases
6422 in which we are not using $at). */
6423 assert (offset_expr
.X_op
== O_symbol
);
6424 expr1
.X_add_number
= offset_expr
.X_add_number
;
6425 offset_expr
.X_add_number
= 0;
6426 if (expr1
.X_add_number
< -0x8000
6427 || expr1
.X_add_number
>= 0x8000)
6428 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6429 gpdelay
= reg_needs_delay (mips_gp_register
);
6430 relax_start (offset_expr
.X_add_symbol
);
6431 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6432 BFD_RELOC_MIPS_GOT_HI16
);
6433 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6435 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6436 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6439 macro_build (NULL
, "nop", "");
6440 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6441 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6443 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6444 tempreg
, BFD_RELOC_LO16
);
6448 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6449 tempreg
, tempreg
, breg
);
6450 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6452 else if (mips_big_got
&& HAVE_NEWABI
)
6454 /* If this is a reference to an external symbol, we want
6455 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6456 add $tempreg,$tempreg,$gp
6457 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6458 <op> $treg,<ofst>($tempreg)
6459 Otherwise, for local symbols, we want:
6460 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6461 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6462 assert (offset_expr
.X_op
== O_symbol
);
6463 expr1
.X_add_number
= offset_expr
.X_add_number
;
6464 offset_expr
.X_add_number
= 0;
6465 if (expr1
.X_add_number
< -0x8000
6466 || expr1
.X_add_number
>= 0x8000)
6467 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6468 relax_start (offset_expr
.X_add_symbol
);
6469 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6470 BFD_RELOC_MIPS_GOT_HI16
);
6471 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6473 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6474 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6476 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6477 tempreg
, tempreg
, breg
);
6478 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6481 offset_expr
.X_add_number
= expr1
.X_add_number
;
6482 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6483 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6485 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6486 tempreg
, tempreg
, breg
);
6487 macro_build (&offset_expr
, s
, fmt
, treg
,
6488 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6498 load_register (treg
, &imm_expr
, 0);
6502 load_register (treg
, &imm_expr
, 1);
6506 if (imm_expr
.X_op
== O_constant
)
6509 load_register (AT
, &imm_expr
, 0);
6510 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6515 assert (offset_expr
.X_op
== O_symbol
6516 && strcmp (segment_name (S_GET_SEGMENT
6517 (offset_expr
.X_add_symbol
)),
6519 && offset_expr
.X_add_number
== 0);
6520 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6521 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6526 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6527 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6528 order 32 bits of the value and the low order 32 bits are either
6529 zero or in OFFSET_EXPR. */
6530 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6532 if (HAVE_64BIT_GPRS
)
6533 load_register (treg
, &imm_expr
, 1);
6538 if (target_big_endian
)
6550 load_register (hreg
, &imm_expr
, 0);
6553 if (offset_expr
.X_op
== O_absent
)
6554 move_register (lreg
, 0);
6557 assert (offset_expr
.X_op
== O_constant
);
6558 load_register (lreg
, &offset_expr
, 0);
6565 /* We know that sym is in the .rdata section. First we get the
6566 upper 16 bits of the address. */
6567 if (mips_pic
== NO_PIC
)
6569 macro_build_lui (&offset_expr
, AT
);
6574 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6575 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6579 /* Now we load the register(s). */
6580 if (HAVE_64BIT_GPRS
)
6583 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6588 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6591 /* FIXME: How in the world do we deal with the possible
6593 offset_expr
.X_add_number
+= 4;
6594 macro_build (&offset_expr
, "lw", "t,o(b)",
6595 treg
+ 1, BFD_RELOC_LO16
, AT
);
6601 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6602 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6603 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6604 the value and the low order 32 bits are either zero or in
6606 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6609 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6610 if (HAVE_64BIT_FPRS
)
6612 assert (HAVE_64BIT_GPRS
);
6613 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6617 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6618 if (offset_expr
.X_op
== O_absent
)
6619 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6622 assert (offset_expr
.X_op
== O_constant
);
6623 load_register (AT
, &offset_expr
, 0);
6624 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6630 assert (offset_expr
.X_op
== O_symbol
6631 && offset_expr
.X_add_number
== 0);
6632 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6633 if (strcmp (s
, ".lit8") == 0)
6635 if (mips_opts
.isa
!= ISA_MIPS1
)
6637 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6638 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6641 breg
= mips_gp_register
;
6642 r
= BFD_RELOC_MIPS_LITERAL
;
6647 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6649 if (mips_pic
!= NO_PIC
)
6650 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6651 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6654 /* FIXME: This won't work for a 64 bit address. */
6655 macro_build_lui (&offset_expr
, AT
);
6658 if (mips_opts
.isa
!= ISA_MIPS1
)
6660 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6661 treg
, BFD_RELOC_LO16
, AT
);
6670 if (mips_opts
.arch
== CPU_R4650
)
6672 as_bad (_("opcode not supported on this processor"));
6675 /* Even on a big endian machine $fn comes before $fn+1. We have
6676 to adjust when loading from memory. */
6679 assert (mips_opts
.isa
== ISA_MIPS1
);
6680 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6681 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6682 /* FIXME: A possible overflow which I don't know how to deal
6684 offset_expr
.X_add_number
+= 4;
6685 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6686 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6691 * The MIPS assembler seems to check for X_add_number not
6692 * being double aligned and generating:
6695 * addiu at,at,%lo(foo+1)
6698 * But, the resulting address is the same after relocation so why
6699 * generate the extra instruction?
6701 if (mips_opts
.arch
== CPU_R4650
)
6703 as_bad (_("opcode not supported on this processor"));
6706 /* Itbl support may require additional care here. */
6708 if (mips_opts
.isa
!= ISA_MIPS1
)
6719 if (mips_opts
.arch
== CPU_R4650
)
6721 as_bad (_("opcode not supported on this processor"));
6725 if (mips_opts
.isa
!= ISA_MIPS1
)
6733 /* Itbl support may require additional care here. */
6738 if (HAVE_64BIT_GPRS
)
6749 if (HAVE_64BIT_GPRS
)
6759 if (offset_expr
.X_op
!= O_symbol
6760 && offset_expr
.X_op
!= O_constant
)
6762 as_bad (_("expression too complex"));
6763 offset_expr
.X_op
= O_constant
;
6766 if (HAVE_32BIT_ADDRESSES
6767 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6771 sprintf_vma (value
, offset_expr
.X_add_number
);
6772 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6775 /* Even on a big endian machine $fn comes before $fn+1. We have
6776 to adjust when loading from memory. We set coproc if we must
6777 load $fn+1 first. */
6778 /* Itbl support may require additional care here. */
6779 if (! target_big_endian
)
6782 if (mips_pic
== NO_PIC
6783 || offset_expr
.X_op
== O_constant
)
6785 /* If this is a reference to a GP relative symbol, we want
6786 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6787 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6788 If we have a base register, we use this
6790 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6791 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6792 If this is not a GP relative symbol, we want
6793 lui $at,<sym> (BFD_RELOC_HI16_S)
6794 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6795 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6796 If there is a base register, we add it to $at after the
6797 lui instruction. If there is a constant, we always use
6799 if (offset_expr
.X_op
== O_symbol
6800 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6801 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6803 relax_start (offset_expr
.X_add_symbol
);
6806 tempreg
= mips_gp_register
;
6810 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6811 AT
, breg
, mips_gp_register
);
6816 /* Itbl support may require additional care here. */
6817 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6818 BFD_RELOC_GPREL16
, tempreg
);
6819 offset_expr
.X_add_number
+= 4;
6821 /* Set mips_optimize to 2 to avoid inserting an
6823 hold_mips_optimize
= mips_optimize
;
6825 /* Itbl support may require additional care here. */
6826 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6827 BFD_RELOC_GPREL16
, tempreg
);
6828 mips_optimize
= hold_mips_optimize
;
6832 /* We just generated two relocs. When tc_gen_reloc
6833 handles this case, it will skip the first reloc and
6834 handle the second. The second reloc already has an
6835 extra addend of 4, which we added above. We must
6836 subtract it out, and then subtract another 4 to make
6837 the first reloc come out right. The second reloc
6838 will come out right because we are going to add 4 to
6839 offset_expr when we build its instruction below.
6841 If we have a symbol, then we don't want to include
6842 the offset, because it will wind up being included
6843 when we generate the reloc. */
6845 if (offset_expr
.X_op
== O_constant
)
6846 offset_expr
.X_add_number
-= 8;
6849 offset_expr
.X_add_number
= -4;
6850 offset_expr
.X_op
= O_constant
;
6854 macro_build_lui (&offset_expr
, AT
);
6856 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6857 /* Itbl support may require additional care here. */
6858 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6859 BFD_RELOC_LO16
, AT
);
6860 /* FIXME: How do we handle overflow here? */
6861 offset_expr
.X_add_number
+= 4;
6862 /* Itbl support may require additional care here. */
6863 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6864 BFD_RELOC_LO16
, AT
);
6865 if (mips_relax
.sequence
)
6868 else if (!mips_big_got
)
6870 /* If this is a reference to an external symbol, we want
6871 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6876 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6878 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6879 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6880 If there is a base register we add it to $at before the
6881 lwc1 instructions. If there is a constant we include it
6882 in the lwc1 instructions. */
6884 expr1
.X_add_number
= offset_expr
.X_add_number
;
6885 if (expr1
.X_add_number
< -0x8000
6886 || expr1
.X_add_number
>= 0x8000 - 4)
6887 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6888 load_got_offset (AT
, &offset_expr
);
6891 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6893 /* Set mips_optimize to 2 to avoid inserting an undesired
6895 hold_mips_optimize
= mips_optimize
;
6898 /* Itbl support may require additional care here. */
6899 relax_start (offset_expr
.X_add_symbol
);
6900 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6901 BFD_RELOC_LO16
, AT
);
6902 expr1
.X_add_number
+= 4;
6903 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6904 BFD_RELOC_LO16
, AT
);
6906 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6907 BFD_RELOC_LO16
, AT
);
6908 offset_expr
.X_add_number
+= 4;
6909 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6910 BFD_RELOC_LO16
, AT
);
6913 mips_optimize
= hold_mips_optimize
;
6915 else if (mips_big_got
)
6919 /* If this is a reference to an external symbol, we want
6920 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6922 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6927 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6929 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6930 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6931 If there is a base register we add it to $at before the
6932 lwc1 instructions. If there is a constant we include it
6933 in the lwc1 instructions. */
6935 expr1
.X_add_number
= offset_expr
.X_add_number
;
6936 offset_expr
.X_add_number
= 0;
6937 if (expr1
.X_add_number
< -0x8000
6938 || expr1
.X_add_number
>= 0x8000 - 4)
6939 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6940 gpdelay
= reg_needs_delay (mips_gp_register
);
6941 relax_start (offset_expr
.X_add_symbol
);
6942 macro_build (&offset_expr
, "lui", "t,u",
6943 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6944 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6945 AT
, AT
, mips_gp_register
);
6946 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6947 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6950 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6951 /* Itbl support may require additional care here. */
6952 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6953 BFD_RELOC_LO16
, AT
);
6954 expr1
.X_add_number
+= 4;
6956 /* Set mips_optimize to 2 to avoid inserting an undesired
6958 hold_mips_optimize
= mips_optimize
;
6960 /* Itbl support may require additional care here. */
6961 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6962 BFD_RELOC_LO16
, AT
);
6963 mips_optimize
= hold_mips_optimize
;
6964 expr1
.X_add_number
-= 4;
6967 offset_expr
.X_add_number
= expr1
.X_add_number
;
6969 macro_build (NULL
, "nop", "");
6970 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6971 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6974 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6975 /* Itbl support may require additional care here. */
6976 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6977 BFD_RELOC_LO16
, AT
);
6978 offset_expr
.X_add_number
+= 4;
6980 /* Set mips_optimize to 2 to avoid inserting an undesired
6982 hold_mips_optimize
= mips_optimize
;
6984 /* Itbl support may require additional care here. */
6985 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6986 BFD_RELOC_LO16
, AT
);
6987 mips_optimize
= hold_mips_optimize
;
7001 assert (HAVE_32BIT_ADDRESSES
);
7002 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7003 offset_expr
.X_add_number
+= 4;
7004 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
7007 /* New code added to support COPZ instructions.
7008 This code builds table entries out of the macros in mip_opcodes.
7009 R4000 uses interlocks to handle coproc delays.
7010 Other chips (like the R3000) require nops to be inserted for delays.
7012 FIXME: Currently, we require that the user handle delays.
7013 In order to fill delay slots for non-interlocked chips,
7014 we must have a way to specify delays based on the coprocessor.
7015 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7016 What are the side-effects of the cop instruction?
7017 What cache support might we have and what are its effects?
7018 Both coprocessor & memory require delays. how long???
7019 What registers are read/set/modified?
7021 If an itbl is provided to interpret cop instructions,
7022 this knowledge can be encoded in the itbl spec. */
7036 /* For now we just do C (same as Cz). The parameter will be
7037 stored in insn_opcode by mips_ip. */
7038 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7042 move_register (dreg
, sreg
);
7045 #ifdef LOSING_COMPILER
7047 /* Try and see if this is a new itbl instruction.
7048 This code builds table entries out of the macros in mip_opcodes.
7049 FIXME: For now we just assemble the expression and pass it's
7050 value along as a 32-bit immediate.
7051 We may want to have the assembler assemble this value,
7052 so that we gain the assembler's knowledge of delay slots,
7054 Would it be more efficient to use mask (id) here? */
7055 if (itbl_have_entries
7056 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7058 s
= ip
->insn_mo
->name
;
7060 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7061 macro_build (&immed_expr
, s
, "C");
7067 if (mips_opts
.noat
&& used_at
)
7068 as_bad (_("Macro used $at after \".set noat\""));
7072 macro2 (struct mips_cl_insn
*ip
)
7074 int treg
, sreg
, dreg
, breg
;
7089 bfd_reloc_code_real_type r
;
7091 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7092 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7093 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7094 mask
= ip
->insn_mo
->mask
;
7096 expr1
.X_op
= O_constant
;
7097 expr1
.X_op_symbol
= NULL
;
7098 expr1
.X_add_symbol
= NULL
;
7099 expr1
.X_add_number
= 1;
7103 #endif /* LOSING_COMPILER */
7108 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7109 macro_build (NULL
, "mflo", "d", dreg
);
7115 /* The MIPS assembler some times generates shifts and adds. I'm
7116 not trying to be that fancy. GCC should do this for us
7119 load_register (AT
, &imm_expr
, dbl
);
7120 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7121 macro_build (NULL
, "mflo", "d", dreg
);
7137 load_register (AT
, &imm_expr
, dbl
);
7138 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7139 macro_build (NULL
, "mflo", "d", dreg
);
7140 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7141 macro_build (NULL
, "mfhi", "d", AT
);
7143 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7146 expr1
.X_add_number
= 8;
7147 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7148 macro_build (NULL
, "nop", "", 0);
7149 macro_build (NULL
, "break", "c", 6);
7152 macro_build (NULL
, "mflo", "d", dreg
);
7168 load_register (AT
, &imm_expr
, dbl
);
7169 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7170 sreg
, imm
? AT
: treg
);
7171 macro_build (NULL
, "mfhi", "d", AT
);
7172 macro_build (NULL
, "mflo", "d", dreg
);
7174 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7177 expr1
.X_add_number
= 8;
7178 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7179 macro_build (NULL
, "nop", "", 0);
7180 macro_build (NULL
, "break", "c", 6);
7186 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7197 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7198 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7202 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7203 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7204 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7205 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7209 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7220 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7221 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7225 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7226 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7227 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7228 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7236 if (imm_expr
.X_op
!= O_constant
)
7237 as_bad (_("Improper rotate count"));
7238 rot
= imm_expr
.X_add_number
& 0x3f;
7239 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7241 rot
= (64 - rot
) & 0x3f;
7243 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7245 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7250 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7253 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7254 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7257 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7258 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7259 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7267 if (imm_expr
.X_op
!= O_constant
)
7268 as_bad (_("Improper rotate count"));
7269 rot
= imm_expr
.X_add_number
& 0x1f;
7270 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7272 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7277 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7281 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7282 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7283 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7288 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7290 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7294 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7295 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7296 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7297 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7301 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7303 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7307 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7308 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7309 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7310 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7318 if (imm_expr
.X_op
!= O_constant
)
7319 as_bad (_("Improper rotate count"));
7320 rot
= imm_expr
.X_add_number
& 0x3f;
7321 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7324 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7326 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7331 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7334 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7335 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7338 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7339 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7340 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7348 if (imm_expr
.X_op
!= O_constant
)
7349 as_bad (_("Improper rotate count"));
7350 rot
= imm_expr
.X_add_number
& 0x1f;
7351 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7353 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7358 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7362 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7363 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7364 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7369 if (mips_opts
.arch
== CPU_R4650
)
7371 as_bad (_("opcode not supported on this processor"));
7374 assert (mips_opts
.isa
== ISA_MIPS1
);
7375 /* Even on a big endian machine $fn comes before $fn+1. We have
7376 to adjust when storing to memory. */
7377 macro_build (&offset_expr
, "swc1", "T,o(b)",
7378 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7379 offset_expr
.X_add_number
+= 4;
7380 macro_build (&offset_expr
, "swc1", "T,o(b)",
7381 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7386 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7388 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7391 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7392 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7397 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7399 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7404 as_warn (_("Instruction %s: result is always false"),
7406 move_register (dreg
, 0);
7409 if (imm_expr
.X_op
== O_constant
7410 && imm_expr
.X_add_number
>= 0
7411 && imm_expr
.X_add_number
< 0x10000)
7413 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7415 else if (imm_expr
.X_op
== O_constant
7416 && imm_expr
.X_add_number
> -0x8000
7417 && imm_expr
.X_add_number
< 0)
7419 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7420 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7421 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7425 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7426 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7429 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7432 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7438 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7439 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7442 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7444 if (imm_expr
.X_op
== O_constant
7445 && imm_expr
.X_add_number
>= -0x8000
7446 && imm_expr
.X_add_number
< 0x8000)
7448 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7449 dreg
, sreg
, BFD_RELOC_LO16
);
7453 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7454 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7458 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7461 case M_SGT
: /* sreg > treg <==> treg < sreg */
7467 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7470 case M_SGT_I
: /* sreg > I <==> I < sreg */
7477 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7478 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7481 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7487 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7488 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7491 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7498 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7499 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7500 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7504 if (imm_expr
.X_op
== O_constant
7505 && imm_expr
.X_add_number
>= -0x8000
7506 && imm_expr
.X_add_number
< 0x8000)
7508 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7512 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7513 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7517 if (imm_expr
.X_op
== O_constant
7518 && imm_expr
.X_add_number
>= -0x8000
7519 && imm_expr
.X_add_number
< 0x8000)
7521 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7526 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7527 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7532 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7534 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7537 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7538 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7543 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7545 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7550 as_warn (_("Instruction %s: result is always true"),
7552 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7553 dreg
, 0, BFD_RELOC_LO16
);
7556 if (imm_expr
.X_op
== O_constant
7557 && imm_expr
.X_add_number
>= 0
7558 && imm_expr
.X_add_number
< 0x10000)
7560 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7562 else if (imm_expr
.X_op
== O_constant
7563 && imm_expr
.X_add_number
> -0x8000
7564 && imm_expr
.X_add_number
< 0)
7566 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7567 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7568 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7572 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7573 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7576 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7582 if (imm_expr
.X_op
== O_constant
7583 && imm_expr
.X_add_number
> -0x8000
7584 && imm_expr
.X_add_number
<= 0x8000)
7586 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7587 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7588 dreg
, sreg
, BFD_RELOC_LO16
);
7592 load_register (AT
, &imm_expr
, dbl
);
7593 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7599 if (imm_expr
.X_op
== O_constant
7600 && imm_expr
.X_add_number
> -0x8000
7601 && imm_expr
.X_add_number
<= 0x8000)
7603 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7604 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7605 dreg
, sreg
, BFD_RELOC_LO16
);
7609 load_register (AT
, &imm_expr
, dbl
);
7610 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7632 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7633 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7638 assert (mips_opts
.isa
== ISA_MIPS1
);
7640 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7641 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7644 * Is the double cfc1 instruction a bug in the mips assembler;
7645 * or is there a reason for it?
7648 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7649 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7650 macro_build (NULL
, "nop", "");
7651 expr1
.X_add_number
= 3;
7652 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7653 expr1
.X_add_number
= 2;
7654 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7655 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7656 macro_build (NULL
, "nop", "");
7657 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7659 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7660 macro_build (NULL
, "nop", "");
7671 if (offset_expr
.X_add_number
>= 0x7fff)
7672 as_bad (_("operand overflow"));
7673 if (! target_big_endian
)
7674 ++offset_expr
.X_add_number
;
7675 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7676 if (! target_big_endian
)
7677 --offset_expr
.X_add_number
;
7679 ++offset_expr
.X_add_number
;
7680 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7681 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7682 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7695 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7696 as_bad (_("operand overflow"));
7704 if (! target_big_endian
)
7705 offset_expr
.X_add_number
+= off
;
7706 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7707 if (! target_big_endian
)
7708 offset_expr
.X_add_number
-= off
;
7710 offset_expr
.X_add_number
+= off
;
7711 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7713 /* If necessary, move the result in tempreg the final destination. */
7714 if (treg
== tempreg
)
7716 /* Protect second load's delay slot. */
7718 move_register (treg
, tempreg
);
7732 load_address (AT
, &offset_expr
, &used_at
);
7734 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7735 if (! target_big_endian
)
7736 expr1
.X_add_number
= off
;
7738 expr1
.X_add_number
= 0;
7739 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7740 if (! target_big_endian
)
7741 expr1
.X_add_number
= 0;
7743 expr1
.X_add_number
= off
;
7744 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7750 load_address (AT
, &offset_expr
, &used_at
);
7752 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7753 if (target_big_endian
)
7754 expr1
.X_add_number
= 0;
7755 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7756 treg
, BFD_RELOC_LO16
, AT
);
7757 if (target_big_endian
)
7758 expr1
.X_add_number
= 1;
7760 expr1
.X_add_number
= 0;
7761 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7762 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7763 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7768 if (offset_expr
.X_add_number
>= 0x7fff)
7769 as_bad (_("operand overflow"));
7770 if (target_big_endian
)
7771 ++offset_expr
.X_add_number
;
7772 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7773 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7774 if (target_big_endian
)
7775 --offset_expr
.X_add_number
;
7777 ++offset_expr
.X_add_number
;
7778 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7791 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7792 as_bad (_("operand overflow"));
7793 if (! target_big_endian
)
7794 offset_expr
.X_add_number
+= off
;
7795 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7796 if (! target_big_endian
)
7797 offset_expr
.X_add_number
-= off
;
7799 offset_expr
.X_add_number
+= off
;
7800 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7814 load_address (AT
, &offset_expr
, &used_at
);
7816 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7817 if (! target_big_endian
)
7818 expr1
.X_add_number
= off
;
7820 expr1
.X_add_number
= 0;
7821 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7822 if (! target_big_endian
)
7823 expr1
.X_add_number
= 0;
7825 expr1
.X_add_number
= off
;
7826 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7831 load_address (AT
, &offset_expr
, &used_at
);
7833 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7834 if (! target_big_endian
)
7835 expr1
.X_add_number
= 0;
7836 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7837 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7838 if (! target_big_endian
)
7839 expr1
.X_add_number
= 1;
7841 expr1
.X_add_number
= 0;
7842 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7843 if (! target_big_endian
)
7844 expr1
.X_add_number
= 0;
7846 expr1
.X_add_number
= 1;
7847 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7848 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7849 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7853 /* FIXME: Check if this is one of the itbl macros, since they
7854 are added dynamically. */
7855 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7858 if (mips_opts
.noat
&& used_at
)
7859 as_bad (_("Macro used $at after \".set noat\""));
7862 /* Implement macros in mips16 mode. */
7865 mips16_macro (struct mips_cl_insn
*ip
)
7868 int xreg
, yreg
, zreg
, tmp
;
7871 const char *s
, *s2
, *s3
;
7873 mask
= ip
->insn_mo
->mask
;
7875 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7876 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7877 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7879 expr1
.X_op
= O_constant
;
7880 expr1
.X_op_symbol
= NULL
;
7881 expr1
.X_add_symbol
= NULL
;
7882 expr1
.X_add_number
= 1;
7902 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7903 expr1
.X_add_number
= 2;
7904 macro_build (&expr1
, "bnez", "x,p", yreg
);
7905 macro_build (NULL
, "break", "6", 7);
7907 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7908 since that causes an overflow. We should do that as well,
7909 but I don't see how to do the comparisons without a temporary
7912 macro_build (NULL
, s
, "x", zreg
);
7932 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7933 expr1
.X_add_number
= 2;
7934 macro_build (&expr1
, "bnez", "x,p", yreg
);
7935 macro_build (NULL
, "break", "6", 7);
7937 macro_build (NULL
, s2
, "x", zreg
);
7943 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7944 macro_build (NULL
, "mflo", "x", zreg
);
7952 if (imm_expr
.X_op
!= O_constant
)
7953 as_bad (_("Unsupported large constant"));
7954 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7955 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7959 if (imm_expr
.X_op
!= O_constant
)
7960 as_bad (_("Unsupported large constant"));
7961 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7962 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7966 if (imm_expr
.X_op
!= O_constant
)
7967 as_bad (_("Unsupported large constant"));
7968 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7969 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7991 goto do_reverse_branch
;
7995 goto do_reverse_branch
;
8007 goto do_reverse_branch
;
8018 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8019 macro_build (&offset_expr
, s2
, "p");
8046 goto do_addone_branch_i
;
8051 goto do_addone_branch_i
;
8066 goto do_addone_branch_i
;
8073 if (imm_expr
.X_op
!= O_constant
)
8074 as_bad (_("Unsupported large constant"));
8075 ++imm_expr
.X_add_number
;
8078 macro_build (&imm_expr
, s
, s3
, xreg
);
8079 macro_build (&offset_expr
, s2
, "p");
8083 expr1
.X_add_number
= 0;
8084 macro_build (&expr1
, "slti", "x,8", yreg
);
8086 move_register (xreg
, yreg
);
8087 expr1
.X_add_number
= 2;
8088 macro_build (&expr1
, "bteqz", "p");
8089 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8093 /* For consistency checking, verify that all bits are specified either
8094 by the match/mask part of the instruction definition, or by the
8097 validate_mips_insn (const struct mips_opcode
*opc
)
8099 const char *p
= opc
->args
;
8101 unsigned long used_bits
= opc
->mask
;
8103 if ((used_bits
& opc
->match
) != opc
->match
)
8105 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8106 opc
->name
, opc
->args
);
8109 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8119 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8120 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8121 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8122 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8123 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8124 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8125 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8126 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8127 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8128 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8129 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8130 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8131 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8133 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8134 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8135 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8137 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8138 c
, opc
->name
, opc
->args
);
8142 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8143 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8145 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8146 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8147 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8148 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8150 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8151 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8153 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8154 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8156 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8157 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8158 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8159 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8160 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8161 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8162 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8163 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8164 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8165 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8166 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8167 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8168 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8169 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8170 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8171 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8172 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8174 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8175 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8176 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8177 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8179 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8180 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8181 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8182 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8183 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8184 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8185 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8186 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8187 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8190 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8191 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8192 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8193 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8194 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8197 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8198 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8199 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8200 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8201 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8202 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8203 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8204 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8205 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8206 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8207 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8208 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8209 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8210 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8211 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8212 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8214 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8215 c
, opc
->name
, opc
->args
);
8219 if (used_bits
!= 0xffffffff)
8221 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8222 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8228 /* UDI immediates. */
8236 static const struct mips_immed mips_immed
[] = {
8237 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8238 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8239 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8240 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8244 /* Check whether an odd floating-point register is allowed. */
8246 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8248 const char *s
= insn
->name
;
8250 if (insn
->pinfo
== INSN_MACRO
)
8251 /* Let a macro pass, we'll catch it later when it is expanded. */
8254 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8256 /* Allow odd registers for single-precision ops. */
8257 switch (insn
->pinfo
& (FP_S
| FP_D
))
8261 return 1; /* both single precision - ok */
8263 return 0; /* both double precision - fail */
8268 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8269 s
= strchr (insn
->name
, '.');
8271 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8272 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8275 /* Single-precision coprocessor loads and moves are OK too. */
8276 if ((insn
->pinfo
& FP_S
)
8277 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8278 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8284 /* This routine assembles an instruction into its binary format. As a
8285 side effect, it sets one of the global variables imm_reloc or
8286 offset_reloc to the type of relocation to do if one of the operands
8287 is an address expression. */
8290 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8295 struct mips_opcode
*insn
;
8298 unsigned int lastregno
= 0;
8299 unsigned int lastpos
= 0;
8300 unsigned int limlo
, limhi
;
8303 offsetT min_range
, max_range
;
8309 /* If the instruction contains a '.', we first try to match an instruction
8310 including the '.'. Then we try again without the '.'. */
8312 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8315 /* If we stopped on whitespace, then replace the whitespace with null for
8316 the call to hash_find. Save the character we replaced just in case we
8317 have to re-parse the instruction. */
8324 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8326 /* If we didn't find the instruction in the opcode table, try again, but
8327 this time with just the instruction up to, but not including the
8331 /* Restore the character we overwrite above (if any). */
8335 /* Scan up to the first '.' or whitespace. */
8337 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8341 /* If we did not find a '.', then we can quit now. */
8344 insn_error
= "unrecognized opcode";
8348 /* Lookup the instruction in the hash table. */
8350 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8352 insn_error
= "unrecognized opcode";
8362 assert (strcmp (insn
->name
, str
) == 0);
8364 if (OPCODE_IS_MEMBER (insn
,
8366 /* We don't check for mips_opts.mips16 here since
8367 we want to allow jalx if -mips16 was specified
8368 on the command line. */
8369 | (file_ase_mips16
? INSN_MIPS16
: 0)
8370 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8371 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
8372 | ((mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
8374 | (mips_opts
.ase_mt
? INSN_MT
: 0)
8375 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)
8376 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
8382 if (insn
->pinfo
!= INSN_MACRO
)
8384 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8390 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8391 && strcmp (insn
->name
, insn
[1].name
) == 0)
8400 static char buf
[100];
8402 _("opcode not supported on this processor: %s (%s)"),
8403 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8404 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8413 create_insn (ip
, insn
);
8416 for (args
= insn
->args
;; ++args
)
8420 s
+= strspn (s
, " \t");
8424 case '\0': /* end of args */
8429 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8430 my_getExpression (&imm_expr
, s
);
8431 check_absolute_expr (ip
, &imm_expr
);
8432 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8434 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8435 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8437 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8438 imm_expr
.X_op
= O_absent
;
8442 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8443 my_getExpression (&imm_expr
, s
);
8444 check_absolute_expr (ip
, &imm_expr
);
8445 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8447 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8448 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8450 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8451 imm_expr
.X_op
= O_absent
;
8455 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8456 my_getExpression (&imm_expr
, s
);
8457 check_absolute_expr (ip
, &imm_expr
);
8458 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8460 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8461 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8463 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8464 imm_expr
.X_op
= O_absent
;
8468 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8469 my_getExpression (&imm_expr
, s
);
8470 check_absolute_expr (ip
, &imm_expr
);
8471 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8473 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8474 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8476 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8477 imm_expr
.X_op
= O_absent
;
8481 case '7': /* four dsp accumulators in bits 11,12 */
8482 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8483 s
[3] >= '0' && s
[3] <= '3')
8487 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8491 as_bad (_("Invalid dsp acc register"));
8494 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8495 my_getExpression (&imm_expr
, s
);
8496 check_absolute_expr (ip
, &imm_expr
);
8497 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8499 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8501 (unsigned long) imm_expr
.X_add_number
);
8503 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8504 imm_expr
.X_op
= O_absent
;
8508 case '9': /* four dsp accumulators in bits 21,22 */
8509 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8510 s
[3] >= '0' && s
[3] <= '3')
8514 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8518 as_bad (_("Invalid dsp acc register"));
8521 case '0': /* dsp 6-bit signed immediate in bit 20 */
8522 my_getExpression (&imm_expr
, s
);
8523 check_absolute_expr (ip
, &imm_expr
);
8524 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8525 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8526 if (imm_expr
.X_add_number
< min_range
||
8527 imm_expr
.X_add_number
> max_range
)
8529 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8530 (long) min_range
, (long) max_range
,
8531 (long) imm_expr
.X_add_number
);
8533 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8534 imm_expr
.X_op
= O_absent
;
8538 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8539 my_getExpression (&imm_expr
, s
);
8540 check_absolute_expr (ip
, &imm_expr
);
8541 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8543 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8545 (unsigned long) imm_expr
.X_add_number
);
8547 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8548 imm_expr
.X_op
= O_absent
;
8552 case ':': /* dsp 7-bit signed immediate in bit 19 */
8553 my_getExpression (&imm_expr
, s
);
8554 check_absolute_expr (ip
, &imm_expr
);
8555 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8556 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8557 if (imm_expr
.X_add_number
< min_range
||
8558 imm_expr
.X_add_number
> max_range
)
8560 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8561 (long) min_range
, (long) max_range
,
8562 (long) imm_expr
.X_add_number
);
8564 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8565 imm_expr
.X_op
= O_absent
;
8569 case '@': /* dsp 10-bit signed immediate in bit 16 */
8570 my_getExpression (&imm_expr
, s
);
8571 check_absolute_expr (ip
, &imm_expr
);
8572 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8573 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8574 if (imm_expr
.X_add_number
< min_range
||
8575 imm_expr
.X_add_number
> max_range
)
8577 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8578 (long) min_range
, (long) max_range
,
8579 (long) imm_expr
.X_add_number
);
8581 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8582 imm_expr
.X_op
= O_absent
;
8586 case '!': /* MT usermode flag bit. */
8587 my_getExpression (&imm_expr
, s
);
8588 check_absolute_expr (ip
, &imm_expr
);
8589 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8590 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8591 (unsigned long) imm_expr
.X_add_number
);
8592 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8593 imm_expr
.X_op
= O_absent
;
8597 case '$': /* MT load high flag bit. */
8598 my_getExpression (&imm_expr
, s
);
8599 check_absolute_expr (ip
, &imm_expr
);
8600 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8601 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8602 (unsigned long) imm_expr
.X_add_number
);
8603 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8604 imm_expr
.X_op
= O_absent
;
8608 case '*': /* four dsp accumulators in bits 18,19 */
8609 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8610 s
[3] >= '0' && s
[3] <= '3')
8614 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8618 as_bad (_("Invalid dsp/smartmips acc register"));
8621 case '&': /* four dsp accumulators in bits 13,14 */
8622 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8623 s
[3] >= '0' && s
[3] <= '3')
8627 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8631 as_bad (_("Invalid dsp/smartmips acc register"));
8643 INSERT_OPERAND (RS
, *ip
, lastregno
);
8647 INSERT_OPERAND (RT
, *ip
, lastregno
);
8651 INSERT_OPERAND (FT
, *ip
, lastregno
);
8655 INSERT_OPERAND (FS
, *ip
, lastregno
);
8661 /* Handle optional base register.
8662 Either the base register is omitted or
8663 we must have a left paren. */
8664 /* This is dependent on the next operand specifier
8665 is a base register specification. */
8666 assert (args
[1] == 'b' || args
[1] == '5'
8667 || args
[1] == '-' || args
[1] == '4');
8671 case ')': /* these must match exactly */
8678 case '+': /* Opcode extension character. */
8681 case '1': /* UDI immediates. */
8686 const struct mips_immed
*imm
= mips_immed
;
8688 while (imm
->type
&& imm
->type
!= *args
)
8692 my_getExpression (&imm_expr
, s
);
8693 check_absolute_expr (ip
, &imm_expr
);
8694 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8696 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8697 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8698 (unsigned long) imm_expr
.X_add_number
,
8699 (unsigned long) imm_expr
.X_add_number
);
8700 imm_expr
.X_add_number
&= imm
->mask
;
8702 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8704 imm_expr
.X_op
= O_absent
;
8709 case 'A': /* ins/ext position, becomes LSB. */
8718 my_getExpression (&imm_expr
, s
);
8719 check_absolute_expr (ip
, &imm_expr
);
8720 if ((unsigned long) imm_expr
.X_add_number
< limlo
8721 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8723 as_bad (_("Improper position (%lu)"),
8724 (unsigned long) imm_expr
.X_add_number
);
8725 imm_expr
.X_add_number
= limlo
;
8727 lastpos
= imm_expr
.X_add_number
;
8728 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8729 imm_expr
.X_op
= O_absent
;
8733 case 'B': /* ins size, becomes MSB. */
8742 my_getExpression (&imm_expr
, s
);
8743 check_absolute_expr (ip
, &imm_expr
);
8744 /* Check for negative input so that small negative numbers
8745 will not succeed incorrectly. The checks against
8746 (pos+size) transitively check "size" itself,
8747 assuming that "pos" is reasonable. */
8748 if ((long) imm_expr
.X_add_number
< 0
8749 || ((unsigned long) imm_expr
.X_add_number
8751 || ((unsigned long) imm_expr
.X_add_number
8754 as_bad (_("Improper insert size (%lu, position %lu)"),
8755 (unsigned long) imm_expr
.X_add_number
,
8756 (unsigned long) lastpos
);
8757 imm_expr
.X_add_number
= limlo
- lastpos
;
8759 INSERT_OPERAND (INSMSB
, *ip
,
8760 lastpos
+ imm_expr
.X_add_number
- 1);
8761 imm_expr
.X_op
= O_absent
;
8765 case 'C': /* ext size, becomes MSBD. */
8778 my_getExpression (&imm_expr
, s
);
8779 check_absolute_expr (ip
, &imm_expr
);
8780 /* Check for negative input so that small negative numbers
8781 will not succeed incorrectly. The checks against
8782 (pos+size) transitively check "size" itself,
8783 assuming that "pos" is reasonable. */
8784 if ((long) imm_expr
.X_add_number
< 0
8785 || ((unsigned long) imm_expr
.X_add_number
8787 || ((unsigned long) imm_expr
.X_add_number
8790 as_bad (_("Improper extract size (%lu, position %lu)"),
8791 (unsigned long) imm_expr
.X_add_number
,
8792 (unsigned long) lastpos
);
8793 imm_expr
.X_add_number
= limlo
- lastpos
;
8795 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8796 imm_expr
.X_op
= O_absent
;
8801 /* +D is for disassembly only; never match. */
8805 /* "+I" is like "I", except that imm2_expr is used. */
8806 my_getExpression (&imm2_expr
, s
);
8807 if (imm2_expr
.X_op
!= O_big
8808 && imm2_expr
.X_op
!= O_constant
)
8809 insn_error
= _("absolute expression required");
8810 if (HAVE_32BIT_GPRS
)
8811 normalize_constant_expr (&imm2_expr
);
8815 case 'T': /* Coprocessor register. */
8816 /* +T is for disassembly only; never match. */
8819 case 't': /* Coprocessor register number. */
8820 if (s
[0] == '$' && ISDIGIT (s
[1]))
8830 while (ISDIGIT (*s
));
8832 as_bad (_("Invalid register number (%d)"), regno
);
8835 INSERT_OPERAND (RT
, *ip
, regno
);
8840 as_bad (_("Invalid coprocessor 0 register number"));
8844 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8845 *args
, insn
->name
, insn
->args
);
8846 /* Further processing is fruitless. */
8851 case '<': /* must be at least one digit */
8853 * According to the manual, if the shift amount is greater
8854 * than 31 or less than 0, then the shift amount should be
8855 * mod 32. In reality the mips assembler issues an error.
8856 * We issue a warning and mask out all but the low 5 bits.
8858 my_getExpression (&imm_expr
, s
);
8859 check_absolute_expr (ip
, &imm_expr
);
8860 if ((unsigned long) imm_expr
.X_add_number
> 31)
8861 as_warn (_("Improper shift amount (%lu)"),
8862 (unsigned long) imm_expr
.X_add_number
);
8863 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8864 imm_expr
.X_op
= O_absent
;
8868 case '>': /* shift amount minus 32 */
8869 my_getExpression (&imm_expr
, s
);
8870 check_absolute_expr (ip
, &imm_expr
);
8871 if ((unsigned long) imm_expr
.X_add_number
< 32
8872 || (unsigned long) imm_expr
.X_add_number
> 63)
8874 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8875 imm_expr
.X_op
= O_absent
;
8879 case 'k': /* cache code */
8880 case 'h': /* prefx code */
8881 my_getExpression (&imm_expr
, s
);
8882 check_absolute_expr (ip
, &imm_expr
);
8883 if ((unsigned long) imm_expr
.X_add_number
> 31)
8884 as_warn (_("Invalid value for `%s' (%lu)"),
8886 (unsigned long) imm_expr
.X_add_number
);
8888 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8890 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8891 imm_expr
.X_op
= O_absent
;
8895 case 'c': /* break code */
8896 my_getExpression (&imm_expr
, s
);
8897 check_absolute_expr (ip
, &imm_expr
);
8898 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
8899 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
8901 (unsigned long) imm_expr
.X_add_number
);
8902 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8903 imm_expr
.X_op
= O_absent
;
8907 case 'q': /* lower break code */
8908 my_getExpression (&imm_expr
, s
);
8909 check_absolute_expr (ip
, &imm_expr
);
8910 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
8911 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
8913 (unsigned long) imm_expr
.X_add_number
);
8914 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8915 imm_expr
.X_op
= O_absent
;
8919 case 'B': /* 20-bit syscall/break code. */
8920 my_getExpression (&imm_expr
, s
);
8921 check_absolute_expr (ip
, &imm_expr
);
8922 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8923 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
8925 (unsigned long) imm_expr
.X_add_number
);
8926 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8927 imm_expr
.X_op
= O_absent
;
8931 case 'C': /* Coprocessor code */
8932 my_getExpression (&imm_expr
, s
);
8933 check_absolute_expr (ip
, &imm_expr
);
8934 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
8936 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8937 (unsigned long) imm_expr
.X_add_number
);
8938 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
8940 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
8941 imm_expr
.X_op
= O_absent
;
8945 case 'J': /* 19-bit wait code. */
8946 my_getExpression (&imm_expr
, s
);
8947 check_absolute_expr (ip
, &imm_expr
);
8948 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8950 as_warn (_("Illegal 19-bit code (%lu)"),
8951 (unsigned long) imm_expr
.X_add_number
);
8952 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
8954 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8955 imm_expr
.X_op
= O_absent
;
8959 case 'P': /* Performance register. */
8960 my_getExpression (&imm_expr
, s
);
8961 check_absolute_expr (ip
, &imm_expr
);
8962 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8963 as_warn (_("Invalid performance register (%lu)"),
8964 (unsigned long) imm_expr
.X_add_number
);
8965 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8966 imm_expr
.X_op
= O_absent
;
8970 case 'G': /* Coprocessor destination register. */
8971 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
8972 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
8974 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
8975 INSERT_OPERAND (RD
, *ip
, regno
);
8984 case 'b': /* base register */
8985 case 'd': /* destination register */
8986 case 's': /* source register */
8987 case 't': /* target register */
8988 case 'r': /* both target and source */
8989 case 'v': /* both dest and source */
8990 case 'w': /* both dest and target */
8991 case 'E': /* coprocessor target register */
8992 case 'K': /* 'rdhwr' destination register */
8993 case 'x': /* ignore register name */
8994 case 'z': /* must be zero register */
8995 case 'U': /* destination register (clo/clz). */
8996 case 'g': /* coprocessor destination register */
8998 if (*args
== 'E' || *args
== 'K')
8999 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9002 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9003 if (regno
== AT
&& ! mips_opts
.noat
)
9004 as_warn ("Used $at without \".set noat\"");
9013 if (c
== 'r' || c
== 'v' || c
== 'w')
9020 /* 'z' only matches $0. */
9021 if (c
== 'z' && regno
!= 0)
9024 /* Now that we have assembled one operand, we use the args string
9025 * to figure out where it goes in the instruction. */
9032 INSERT_OPERAND (RS
, *ip
, regno
);
9038 INSERT_OPERAND (RD
, *ip
, regno
);
9041 INSERT_OPERAND (RD
, *ip
, regno
);
9042 INSERT_OPERAND (RT
, *ip
, regno
);
9047 INSERT_OPERAND (RT
, *ip
, regno
);
9050 /* This case exists because on the r3000 trunc
9051 expands into a macro which requires a gp
9052 register. On the r6000 or r4000 it is
9053 assembled into a single instruction which
9054 ignores the register. Thus the insn version
9055 is MIPS_ISA2 and uses 'x', and the macro
9056 version is MIPS_ISA1 and uses 't'. */
9059 /* This case is for the div instruction, which
9060 acts differently if the destination argument
9061 is $0. This only matches $0, and is checked
9062 outside the switch. */
9065 /* Itbl operand; not yet implemented. FIXME ?? */
9067 /* What about all other operands like 'i', which
9068 can be specified in the opcode table? */
9077 INSERT_OPERAND (RS
, *ip
, lastregno
);
9080 INSERT_OPERAND (RT
, *ip
, lastregno
);
9085 case 'O': /* MDMX alignment immediate constant. */
9086 my_getExpression (&imm_expr
, s
);
9087 check_absolute_expr (ip
, &imm_expr
);
9088 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9089 as_warn ("Improper align amount (%ld), using low bits",
9090 (long) imm_expr
.X_add_number
);
9091 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9092 imm_expr
.X_op
= O_absent
;
9096 case 'Q': /* MDMX vector, element sel, or const. */
9099 /* MDMX Immediate. */
9100 my_getExpression (&imm_expr
, s
);
9101 check_absolute_expr (ip
, &imm_expr
);
9102 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9103 as_warn (_("Invalid MDMX Immediate (%ld)"),
9104 (long) imm_expr
.X_add_number
);
9105 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9106 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9107 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9109 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9110 imm_expr
.X_op
= O_absent
;
9114 /* Not MDMX Immediate. Fall through. */
9115 case 'X': /* MDMX destination register. */
9116 case 'Y': /* MDMX source register. */
9117 case 'Z': /* MDMX target register. */
9119 case 'D': /* floating point destination register */
9120 case 'S': /* floating point source register */
9121 case 'T': /* floating point target register */
9122 case 'R': /* floating point source register */
9127 || (mips_opts
.ase_mdmx
9128 && (ip
->insn_mo
->pinfo
& FP_D
)
9129 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9130 | INSN_COPROC_MEMORY_DELAY
9131 | INSN_LOAD_COPROC_DELAY
9132 | INSN_LOAD_MEMORY_DELAY
9133 | INSN_STORE_MEMORY
))))
9136 if (reg_lookup (&s
, rtype
, ®no
))
9138 if ((regno
& 1) != 0
9140 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9141 as_warn (_("Float register should be even, was %d"),
9149 if (c
== 'V' || c
== 'W')
9160 INSERT_OPERAND (FD
, *ip
, regno
);
9165 INSERT_OPERAND (FS
, *ip
, regno
);
9168 /* This is like 'Z', but also needs to fix the MDMX
9169 vector/scalar select bits. Note that the
9170 scalar immediate case is handled above. */
9173 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9174 int max_el
= (is_qh
? 3 : 7);
9176 my_getExpression(&imm_expr
, s
);
9177 check_absolute_expr (ip
, &imm_expr
);
9179 if (imm_expr
.X_add_number
> max_el
)
9180 as_bad(_("Bad element selector %ld"),
9181 (long) imm_expr
.X_add_number
);
9182 imm_expr
.X_add_number
&= max_el
;
9183 ip
->insn_opcode
|= (imm_expr
.X_add_number
9186 imm_expr
.X_op
= O_absent
;
9188 as_warn(_("Expecting ']' found '%s'"), s
);
9194 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9195 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9198 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9205 INSERT_OPERAND (FT
, *ip
, regno
);
9208 INSERT_OPERAND (FR
, *ip
, regno
);
9218 INSERT_OPERAND (FS
, *ip
, lastregno
);
9221 INSERT_OPERAND (FT
, *ip
, lastregno
);
9227 my_getExpression (&imm_expr
, s
);
9228 if (imm_expr
.X_op
!= O_big
9229 && imm_expr
.X_op
!= O_constant
)
9230 insn_error
= _("absolute expression required");
9231 if (HAVE_32BIT_GPRS
)
9232 normalize_constant_expr (&imm_expr
);
9237 my_getExpression (&offset_expr
, s
);
9238 normalize_address_expr (&offset_expr
);
9239 *imm_reloc
= BFD_RELOC_32
;
9252 unsigned char temp
[8];
9254 unsigned int length
;
9259 /* These only appear as the last operand in an
9260 instruction, and every instruction that accepts
9261 them in any variant accepts them in all variants.
9262 This means we don't have to worry about backing out
9263 any changes if the instruction does not match.
9265 The difference between them is the size of the
9266 floating point constant and where it goes. For 'F'
9267 and 'L' the constant is 64 bits; for 'f' and 'l' it
9268 is 32 bits. Where the constant is placed is based
9269 on how the MIPS assembler does things:
9272 f -- immediate value
9275 The .lit4 and .lit8 sections are only used if
9276 permitted by the -G argument.
9278 The code below needs to know whether the target register
9279 is 32 or 64 bits wide. It relies on the fact 'f' and
9280 'F' are used with GPR-based instructions and 'l' and
9281 'L' are used with FPR-based instructions. */
9283 f64
= *args
== 'F' || *args
== 'L';
9284 using_gprs
= *args
== 'F' || *args
== 'f';
9286 save_in
= input_line_pointer
;
9287 input_line_pointer
= s
;
9288 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9290 s
= input_line_pointer
;
9291 input_line_pointer
= save_in
;
9292 if (err
!= NULL
&& *err
!= '\0')
9294 as_bad (_("Bad floating point constant: %s"), err
);
9295 memset (temp
, '\0', sizeof temp
);
9296 length
= f64
? 8 : 4;
9299 assert (length
== (unsigned) (f64
? 8 : 4));
9303 && (g_switch_value
< 4
9304 || (temp
[0] == 0 && temp
[1] == 0)
9305 || (temp
[2] == 0 && temp
[3] == 0))))
9307 imm_expr
.X_op
= O_constant
;
9308 if (! target_big_endian
)
9309 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9311 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9314 && ! mips_disable_float_construction
9315 /* Constants can only be constructed in GPRs and
9316 copied to FPRs if the GPRs are at least as wide
9317 as the FPRs. Force the constant into memory if
9318 we are using 64-bit FPRs but the GPRs are only
9321 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9322 && ((temp
[0] == 0 && temp
[1] == 0)
9323 || (temp
[2] == 0 && temp
[3] == 0))
9324 && ((temp
[4] == 0 && temp
[5] == 0)
9325 || (temp
[6] == 0 && temp
[7] == 0)))
9327 /* The value is simple enough to load with a couple of
9328 instructions. If using 32-bit registers, set
9329 imm_expr to the high order 32 bits and offset_expr to
9330 the low order 32 bits. Otherwise, set imm_expr to
9331 the entire 64 bit constant. */
9332 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9334 imm_expr
.X_op
= O_constant
;
9335 offset_expr
.X_op
= O_constant
;
9336 if (! target_big_endian
)
9338 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9339 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9343 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9344 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9346 if (offset_expr
.X_add_number
== 0)
9347 offset_expr
.X_op
= O_absent
;
9349 else if (sizeof (imm_expr
.X_add_number
) > 4)
9351 imm_expr
.X_op
= O_constant
;
9352 if (! target_big_endian
)
9353 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9355 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9359 imm_expr
.X_op
= O_big
;
9360 imm_expr
.X_add_number
= 4;
9361 if (! target_big_endian
)
9363 generic_bignum
[0] = bfd_getl16 (temp
);
9364 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9365 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9366 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9370 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9371 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9372 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9373 generic_bignum
[3] = bfd_getb16 (temp
);
9379 const char *newname
;
9382 /* Switch to the right section. */
9384 subseg
= now_subseg
;
9387 default: /* unused default case avoids warnings. */
9389 newname
= RDATA_SECTION_NAME
;
9390 if (g_switch_value
>= 8)
9394 newname
= RDATA_SECTION_NAME
;
9397 assert (g_switch_value
>= 4);
9401 new_seg
= subseg_new (newname
, (subsegT
) 0);
9402 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9403 bfd_set_section_flags (stdoutput
, new_seg
,
9408 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9409 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9410 && strcmp (TARGET_OS
, "elf") != 0)
9411 record_alignment (new_seg
, 4);
9413 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9415 as_bad (_("Can't use floating point insn in this section"));
9417 /* Set the argument to the current address in the
9419 offset_expr
.X_op
= O_symbol
;
9420 offset_expr
.X_add_symbol
=
9421 symbol_new ("L0\001", now_seg
,
9422 (valueT
) frag_now_fix (), frag_now
);
9423 offset_expr
.X_add_number
= 0;
9425 /* Put the floating point number into the section. */
9426 p
= frag_more ((int) length
);
9427 memcpy (p
, temp
, length
);
9429 /* Switch back to the original section. */
9430 subseg_set (seg
, subseg
);
9435 case 'i': /* 16 bit unsigned immediate */
9436 case 'j': /* 16 bit signed immediate */
9437 *imm_reloc
= BFD_RELOC_LO16
;
9438 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9441 offsetT minval
, maxval
;
9443 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9444 && strcmp (insn
->name
, insn
[1].name
) == 0);
9446 /* If the expression was written as an unsigned number,
9447 only treat it as signed if there are no more
9451 && sizeof (imm_expr
.X_add_number
) <= 4
9452 && imm_expr
.X_op
== O_constant
9453 && imm_expr
.X_add_number
< 0
9454 && imm_expr
.X_unsigned
9458 /* For compatibility with older assemblers, we accept
9459 0x8000-0xffff as signed 16-bit numbers when only
9460 signed numbers are allowed. */
9462 minval
= 0, maxval
= 0xffff;
9464 minval
= -0x8000, maxval
= 0x7fff;
9466 minval
= -0x8000, maxval
= 0xffff;
9468 if (imm_expr
.X_op
!= O_constant
9469 || imm_expr
.X_add_number
< minval
9470 || imm_expr
.X_add_number
> maxval
)
9474 if (imm_expr
.X_op
== O_constant
9475 || imm_expr
.X_op
== O_big
)
9476 as_bad (_("expression out of range"));
9482 case 'o': /* 16 bit offset */
9483 /* Check whether there is only a single bracketed expression
9484 left. If so, it must be the base register and the
9485 constant must be zero. */
9486 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9488 offset_expr
.X_op
= O_constant
;
9489 offset_expr
.X_add_number
= 0;
9493 /* If this value won't fit into a 16 bit offset, then go
9494 find a macro that will generate the 32 bit offset
9496 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9497 && (offset_expr
.X_op
!= O_constant
9498 || offset_expr
.X_add_number
>= 0x8000
9499 || offset_expr
.X_add_number
< -0x8000))
9505 case 'p': /* pc relative offset */
9506 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9507 my_getExpression (&offset_expr
, s
);
9511 case 'u': /* upper 16 bits */
9512 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9513 && imm_expr
.X_op
== O_constant
9514 && (imm_expr
.X_add_number
< 0
9515 || imm_expr
.X_add_number
>= 0x10000))
9516 as_bad (_("lui expression not in range 0..65535"));
9520 case 'a': /* 26 bit address */
9521 my_getExpression (&offset_expr
, s
);
9523 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9526 case 'N': /* 3 bit branch condition code */
9527 case 'M': /* 3 bit compare condition code */
9529 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9531 if (!reg_lookup (&s
, rtype
, ®no
))
9533 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9534 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9535 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9536 && (regno
& 1) != 0)
9537 as_warn(_("Condition code register should be even for %s, was %d"),
9539 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9540 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9541 && (regno
& 3) != 0)
9542 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9545 INSERT_OPERAND (BCC
, *ip
, regno
);
9547 INSERT_OPERAND (CCC
, *ip
, regno
);
9551 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9562 while (ISDIGIT (*s
));
9565 c
= 8; /* Invalid sel value. */
9568 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9569 ip
->insn_opcode
|= c
;
9573 /* Must be at least one digit. */
9574 my_getExpression (&imm_expr
, s
);
9575 check_absolute_expr (ip
, &imm_expr
);
9577 if ((unsigned long) imm_expr
.X_add_number
9578 > (unsigned long) OP_MASK_VECBYTE
)
9580 as_bad (_("bad byte vector index (%ld)"),
9581 (long) imm_expr
.X_add_number
);
9582 imm_expr
.X_add_number
= 0;
9585 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9586 imm_expr
.X_op
= O_absent
;
9591 my_getExpression (&imm_expr
, s
);
9592 check_absolute_expr (ip
, &imm_expr
);
9594 if ((unsigned long) imm_expr
.X_add_number
9595 > (unsigned long) OP_MASK_VECALIGN
)
9597 as_bad (_("bad byte vector index (%ld)"),
9598 (long) imm_expr
.X_add_number
);
9599 imm_expr
.X_add_number
= 0;
9602 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9603 imm_expr
.X_op
= O_absent
;
9608 as_bad (_("bad char = '%c'\n"), *args
);
9613 /* Args don't match. */
9614 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9615 !strcmp (insn
->name
, insn
[1].name
))
9619 insn_error
= _("illegal operands");
9624 insn_error
= _("illegal operands");
9629 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9631 /* This routine assembles an instruction into its binary format when
9632 assembling for the mips16. As a side effect, it sets one of the
9633 global variables imm_reloc or offset_reloc to the type of
9634 relocation to do if one of the operands is an address expression.
9635 It also sets mips16_small and mips16_ext if the user explicitly
9636 requested a small or extended instruction. */
9639 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9643 struct mips_opcode
*insn
;
9646 unsigned int lastregno
= 0;
9652 mips16_small
= FALSE
;
9655 for (s
= str
; ISLOWER (*s
); ++s
)
9667 if (s
[1] == 't' && s
[2] == ' ')
9670 mips16_small
= TRUE
;
9674 else if (s
[1] == 'e' && s
[2] == ' ')
9683 insn_error
= _("unknown opcode");
9687 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9688 mips16_small
= TRUE
;
9690 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9692 insn_error
= _("unrecognized opcode");
9701 assert (strcmp (insn
->name
, str
) == 0);
9703 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_opts
.arch
))
9710 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
9711 && strcmp (insn
->name
, insn
[1].name
) == 0)
9720 static char buf
[100];
9722 _("opcode not supported on this processor: %s (%s)"),
9723 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
9724 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
9731 create_insn (ip
, insn
);
9732 imm_expr
.X_op
= O_absent
;
9733 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9734 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9735 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9736 imm2_expr
.X_op
= O_absent
;
9737 offset_expr
.X_op
= O_absent
;
9738 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9739 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9740 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9741 for (args
= insn
->args
; 1; ++args
)
9748 /* In this switch statement we call break if we did not find
9749 a match, continue if we did find a match, or return if we
9758 /* Stuff the immediate value in now, if we can. */
9759 if (imm_expr
.X_op
== O_constant
9760 && *imm_reloc
> BFD_RELOC_UNUSED
9761 && insn
->pinfo
!= INSN_MACRO
)
9765 switch (*offset_reloc
)
9767 case BFD_RELOC_MIPS16_HI16_S
:
9768 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9771 case BFD_RELOC_MIPS16_HI16
:
9772 tmp
= imm_expr
.X_add_number
>> 16;
9775 case BFD_RELOC_MIPS16_LO16
:
9776 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9780 case BFD_RELOC_UNUSED
:
9781 tmp
= imm_expr
.X_add_number
;
9787 *offset_reloc
= BFD_RELOC_UNUSED
;
9789 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9790 tmp
, TRUE
, mips16_small
,
9791 mips16_ext
, &ip
->insn_opcode
,
9792 &ip
->use_extend
, &ip
->extend
);
9793 imm_expr
.X_op
= O_absent
;
9794 *imm_reloc
= BFD_RELOC_UNUSED
;
9808 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9811 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9827 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9829 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9844 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
9846 if (c
== 'v' || c
== 'w')
9849 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9851 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9862 if (c
== 'v' || c
== 'w')
9864 regno
= mips16_to_32_reg_map
[lastregno
];
9878 regno
= mips32_to_16_reg_map
[regno
];
9883 regno
= ILLEGAL_REG
;
9888 regno
= ILLEGAL_REG
;
9893 regno
= ILLEGAL_REG
;
9898 if (regno
== AT
&& ! mips_opts
.noat
)
9899 as_warn (_("used $at without \".set noat\""));
9906 if (regno
== ILLEGAL_REG
)
9913 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9917 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9920 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9923 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9929 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9932 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9933 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9943 if (strncmp (s
, "$pc", 3) == 0)
9960 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9963 if (imm_expr
.X_op
!= O_constant
)
9966 ip
->use_extend
= TRUE
;
9971 /* We need to relax this instruction. */
9972 *offset_reloc
= *imm_reloc
;
9973 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9978 *imm_reloc
= BFD_RELOC_UNUSED
;
9986 my_getExpression (&imm_expr
, s
);
9987 if (imm_expr
.X_op
== O_register
)
9989 /* What we thought was an expression turned out to
9992 if (s
[0] == '(' && args
[1] == '(')
9994 /* It looks like the expression was omitted
9995 before a register indirection, which means
9996 that the expression is implicitly zero. We
9997 still set up imm_expr, so that we handle
9998 explicit extensions correctly. */
9999 imm_expr
.X_op
= O_constant
;
10000 imm_expr
.X_add_number
= 0;
10001 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10008 /* We need to relax this instruction. */
10009 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10018 /* We use offset_reloc rather than imm_reloc for the PC
10019 relative operands. This lets macros with both
10020 immediate and address operands work correctly. */
10021 my_getExpression (&offset_expr
, s
);
10023 if (offset_expr
.X_op
== O_register
)
10026 /* We need to relax this instruction. */
10027 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10031 case '6': /* break code */
10032 my_getExpression (&imm_expr
, s
);
10033 check_absolute_expr (ip
, &imm_expr
);
10034 if ((unsigned long) imm_expr
.X_add_number
> 63)
10035 as_warn (_("Invalid value for `%s' (%lu)"),
10037 (unsigned long) imm_expr
.X_add_number
);
10038 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10039 imm_expr
.X_op
= O_absent
;
10043 case 'a': /* 26 bit address */
10044 my_getExpression (&offset_expr
, s
);
10046 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10047 ip
->insn_opcode
<<= 16;
10050 case 'l': /* register list for entry macro */
10051 case 'L': /* register list for exit macro */
10061 unsigned int freg
, reg1
, reg2
;
10063 while (*s
== ' ' || *s
== ',')
10065 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10067 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10071 as_bad (_("can't parse register list"));
10081 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10082 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10084 as_bad (_("invalid register list"));
10088 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10090 mask
&= ~ (7 << 3);
10093 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10095 mask
&= ~ (7 << 3);
10098 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10099 mask
|= (reg2
- 3) << 3;
10100 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10101 mask
|= (reg2
- 15) << 1;
10102 else if (reg1
== RA
&& reg2
== RA
)
10106 as_bad (_("invalid register list"));
10110 /* The mask is filled in in the opcode table for the
10111 benefit of the disassembler. We remove it before
10112 applying the actual mask. */
10113 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10114 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10118 case 'm': /* Register list for save insn. */
10119 case 'M': /* Register list for restore insn. */
10122 int framesz
= 0, seen_framesz
= 0;
10123 int args
= 0, statics
= 0, sregs
= 0;
10127 unsigned int reg1
, reg2
;
10129 SKIP_SPACE_TABS (s
);
10132 SKIP_SPACE_TABS (s
);
10134 my_getExpression (&imm_expr
, s
);
10135 if (imm_expr
.X_op
== O_constant
)
10137 /* Handle the frame size. */
10140 as_bad (_("more than one frame size in list"));
10144 framesz
= imm_expr
.X_add_number
;
10145 imm_expr
.X_op
= O_absent
;
10150 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10152 as_bad (_("can't parse register list"));
10164 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10167 as_bad (_("can't parse register list"));
10172 while (reg1
<= reg2
)
10174 if (reg1
>= 4 && reg1
<= 7)
10176 if (c
== 'm' && !seen_framesz
)
10178 args
|= 1 << (reg1
- 4);
10180 /* statics $a0-$a3 */
10181 statics
|= 1 << (reg1
- 4);
10183 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10186 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10188 else if (reg1
== 31)
10190 /* Add $ra to insn. */
10195 as_bad (_("unexpected register in list"));
10203 /* Encode args/statics combination. */
10204 if (args
& statics
)
10205 as_bad (_("arg/static registers overlap"));
10206 else if (args
== 0xf)
10207 /* All $a0-$a3 are args. */
10208 opcode
|= MIPS16_ALL_ARGS
<< 16;
10209 else if (statics
== 0xf)
10210 /* All $a0-$a3 are statics. */
10211 opcode
|= MIPS16_ALL_STATICS
<< 16;
10214 int narg
= 0, nstat
= 0;
10216 /* Count arg registers. */
10223 as_bad (_("invalid arg register list"));
10225 /* Count static registers. */
10226 while (statics
& 0x8)
10228 statics
= (statics
<< 1) & 0xf;
10232 as_bad (_("invalid static register list"));
10234 /* Encode args/statics. */
10235 opcode
|= ((narg
<< 2) | nstat
) << 16;
10238 /* Encode $s0/$s1. */
10239 if (sregs
& (1 << 0)) /* $s0 */
10241 if (sregs
& (1 << 1)) /* $s1 */
10247 /* Count regs $s2-$s8. */
10255 as_bad (_("invalid static register list"));
10256 /* Encode $s2-$s8. */
10257 opcode
|= nsreg
<< 24;
10260 /* Encode frame size. */
10262 as_bad (_("missing frame size"));
10263 else if ((framesz
& 7) != 0 || framesz
< 0
10264 || framesz
> 0xff * 8)
10265 as_bad (_("invalid frame size"));
10266 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10269 opcode
|= (((framesz
& 0xf0) << 16)
10270 | (framesz
& 0x0f));
10273 /* Finally build the instruction. */
10274 if ((opcode
>> 16) != 0 || framesz
== 0)
10276 ip
->use_extend
= TRUE
;
10277 ip
->extend
= opcode
>> 16;
10279 ip
->insn_opcode
|= opcode
& 0x7f;
10283 case 'e': /* extend code */
10284 my_getExpression (&imm_expr
, s
);
10285 check_absolute_expr (ip
, &imm_expr
);
10286 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10288 as_warn (_("Invalid value for `%s' (%lu)"),
10290 (unsigned long) imm_expr
.X_add_number
);
10291 imm_expr
.X_add_number
&= 0x7ff;
10293 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10294 imm_expr
.X_op
= O_absent
;
10304 /* Args don't match. */
10305 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10306 strcmp (insn
->name
, insn
[1].name
) == 0)
10313 insn_error
= _("illegal operands");
10319 /* This structure holds information we know about a mips16 immediate
10322 struct mips16_immed_operand
10324 /* The type code used in the argument string in the opcode table. */
10326 /* The number of bits in the short form of the opcode. */
10328 /* The number of bits in the extended form of the opcode. */
10330 /* The amount by which the short form is shifted when it is used;
10331 for example, the sw instruction has a shift count of 2. */
10333 /* The amount by which the short form is shifted when it is stored
10334 into the instruction code. */
10336 /* Non-zero if the short form is unsigned. */
10338 /* Non-zero if the extended form is unsigned. */
10340 /* Non-zero if the value is PC relative. */
10344 /* The mips16 immediate operand types. */
10346 static const struct mips16_immed_operand mips16_immed_operands
[] =
10348 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10349 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10350 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10351 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10352 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10353 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10354 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10355 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10356 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10357 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10358 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10359 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10360 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10361 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10362 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10363 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10364 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10365 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10366 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10367 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10368 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10371 #define MIPS16_NUM_IMMED \
10372 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10374 /* Handle a mips16 instruction with an immediate value. This or's the
10375 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10376 whether an extended value is needed; if one is needed, it sets
10377 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10378 If SMALL is true, an unextended opcode was explicitly requested.
10379 If EXT is true, an extended opcode was explicitly requested. If
10380 WARN is true, warn if EXT does not match reality. */
10383 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10384 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10385 unsigned long *insn
, bfd_boolean
*use_extend
,
10386 unsigned short *extend
)
10388 const struct mips16_immed_operand
*op
;
10389 int mintiny
, maxtiny
;
10390 bfd_boolean needext
;
10392 op
= mips16_immed_operands
;
10393 while (op
->type
!= type
)
10396 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10401 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10404 maxtiny
= 1 << op
->nbits
;
10409 maxtiny
= (1 << op
->nbits
) - 1;
10414 mintiny
= - (1 << (op
->nbits
- 1));
10415 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10418 /* Branch offsets have an implicit 0 in the lowest bit. */
10419 if (type
== 'p' || type
== 'q')
10422 if ((val
& ((1 << op
->shift
) - 1)) != 0
10423 || val
< (mintiny
<< op
->shift
)
10424 || val
> (maxtiny
<< op
->shift
))
10429 if (warn
&& ext
&& ! needext
)
10430 as_warn_where (file
, line
,
10431 _("extended operand requested but not required"));
10432 if (small
&& needext
)
10433 as_bad_where (file
, line
, _("invalid unextended operand value"));
10435 if (small
|| (! ext
&& ! needext
))
10439 *use_extend
= FALSE
;
10440 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10441 insnval
<<= op
->op_shift
;
10446 long minext
, maxext
;
10452 maxext
= (1 << op
->extbits
) - 1;
10456 minext
= - (1 << (op
->extbits
- 1));
10457 maxext
= (1 << (op
->extbits
- 1)) - 1;
10459 if (val
< minext
|| val
> maxext
)
10460 as_bad_where (file
, line
,
10461 _("operand value out of range for instruction"));
10463 *use_extend
= TRUE
;
10464 if (op
->extbits
== 16)
10466 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10469 else if (op
->extbits
== 15)
10471 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10476 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10480 *extend
= (unsigned short) extval
;
10485 struct percent_op_match
10488 bfd_reloc_code_real_type reloc
;
10491 static const struct percent_op_match mips_percent_op
[] =
10493 {"%lo", BFD_RELOC_LO16
},
10495 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10496 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10497 {"%call16", BFD_RELOC_MIPS_CALL16
},
10498 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10499 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10500 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10501 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10502 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10503 {"%got", BFD_RELOC_MIPS_GOT16
},
10504 {"%gp_rel", BFD_RELOC_GPREL16
},
10505 {"%half", BFD_RELOC_16
},
10506 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10507 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10508 {"%neg", BFD_RELOC_MIPS_SUB
},
10509 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10510 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10511 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10512 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10513 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10514 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10515 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10517 {"%hi", BFD_RELOC_HI16_S
}
10520 static const struct percent_op_match mips16_percent_op
[] =
10522 {"%lo", BFD_RELOC_MIPS16_LO16
},
10523 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10524 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10528 /* Return true if *STR points to a relocation operator. When returning true,
10529 move *STR over the operator and store its relocation code in *RELOC.
10530 Leave both *STR and *RELOC alone when returning false. */
10533 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10535 const struct percent_op_match
*percent_op
;
10538 if (mips_opts
.mips16
)
10540 percent_op
= mips16_percent_op
;
10541 limit
= ARRAY_SIZE (mips16_percent_op
);
10545 percent_op
= mips_percent_op
;
10546 limit
= ARRAY_SIZE (mips_percent_op
);
10549 for (i
= 0; i
< limit
; i
++)
10550 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10552 int len
= strlen (percent_op
[i
].str
);
10554 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10557 *str
+= strlen (percent_op
[i
].str
);
10558 *reloc
= percent_op
[i
].reloc
;
10560 /* Check whether the output BFD supports this relocation.
10561 If not, issue an error and fall back on something safe. */
10562 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10564 as_bad ("relocation %s isn't supported by the current ABI",
10565 percent_op
[i
].str
);
10566 *reloc
= BFD_RELOC_UNUSED
;
10574 /* Parse string STR as a 16-bit relocatable operand. Store the
10575 expression in *EP and the relocations in the array starting
10576 at RELOC. Return the number of relocation operators used.
10578 On exit, EXPR_END points to the first character after the expression. */
10581 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10584 bfd_reloc_code_real_type reversed_reloc
[3];
10585 size_t reloc_index
, i
;
10586 int crux_depth
, str_depth
;
10589 /* Search for the start of the main expression, recoding relocations
10590 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10591 of the main expression and with CRUX_DEPTH containing the number
10592 of open brackets at that point. */
10599 crux_depth
= str_depth
;
10601 /* Skip over whitespace and brackets, keeping count of the number
10603 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10608 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10609 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10611 my_getExpression (ep
, crux
);
10614 /* Match every open bracket. */
10615 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10619 if (crux_depth
> 0)
10620 as_bad ("unclosed '('");
10624 if (reloc_index
!= 0)
10626 prev_reloc_op_frag
= frag_now
;
10627 for (i
= 0; i
< reloc_index
; i
++)
10628 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10631 return reloc_index
;
10635 my_getExpression (expressionS
*ep
, char *str
)
10640 save_in
= input_line_pointer
;
10641 input_line_pointer
= str
;
10643 expr_end
= input_line_pointer
;
10644 input_line_pointer
= save_in
;
10646 /* If we are in mips16 mode, and this is an expression based on `.',
10647 then we bump the value of the symbol by 1 since that is how other
10648 text symbols are handled. We don't bother to handle complex
10649 expressions, just `.' plus or minus a constant. */
10650 if (mips_opts
.mips16
10651 && ep
->X_op
== O_symbol
10652 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10653 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10654 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10655 && symbol_constant_p (ep
->X_add_symbol
)
10656 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10657 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10660 /* Turn a string in input_line_pointer into a floating point constant
10661 of type TYPE, and store the appropriate bytes in *LITP. The number
10662 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10663 returned, or NULL on OK. */
10666 md_atof (int type
, char *litP
, int *sizeP
)
10669 LITTLENUM_TYPE words
[4];
10685 return _("bad call to md_atof");
10688 t
= atof_ieee (input_line_pointer
, type
, words
);
10690 input_line_pointer
= t
;
10694 if (! target_big_endian
)
10696 for (i
= prec
- 1; i
>= 0; i
--)
10698 md_number_to_chars (litP
, words
[i
], 2);
10704 for (i
= 0; i
< prec
; i
++)
10706 md_number_to_chars (litP
, words
[i
], 2);
10715 md_number_to_chars (char *buf
, valueT val
, int n
)
10717 if (target_big_endian
)
10718 number_to_chars_bigendian (buf
, val
, n
);
10720 number_to_chars_littleendian (buf
, val
, n
);
10724 static int support_64bit_objects(void)
10726 const char **list
, **l
;
10729 list
= bfd_target_list ();
10730 for (l
= list
; *l
!= NULL
; l
++)
10732 /* This is traditional mips */
10733 if (strcmp (*l
, "elf64-tradbigmips") == 0
10734 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10736 if (strcmp (*l
, "elf64-bigmips") == 0
10737 || strcmp (*l
, "elf64-littlemips") == 0)
10740 yes
= (*l
!= NULL
);
10744 #endif /* OBJ_ELF */
10746 const char *md_shortopts
= "O::g::G:";
10748 struct option md_longopts
[] =
10750 /* Options which specify architecture. */
10751 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10752 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10753 {"march", required_argument
, NULL
, OPTION_MARCH
},
10754 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10755 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10756 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10757 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10758 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10759 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10760 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10761 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10762 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10763 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10764 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10765 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10766 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10767 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10768 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10769 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10770 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10771 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10772 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10773 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10774 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10776 /* Options which specify Application Specific Extensions (ASEs). */
10777 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10778 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10779 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10780 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10781 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10782 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10783 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10784 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10785 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10786 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10787 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10788 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10789 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10790 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10791 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10792 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10793 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10794 #define OPTION_MT (OPTION_ASE_BASE + 8)
10795 {"mmt", no_argument
, NULL
, OPTION_MT
},
10796 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10797 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
10798 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
10799 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
10800 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
10801 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
10803 /* Old-style architecture options. Don't add more of these. */
10804 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
10805 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10806 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10807 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10808 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10809 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10810 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10811 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10812 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10813 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10814 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10815 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10816 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10817 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10818 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10819 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10820 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10822 /* Options which enable bug fixes. */
10823 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10824 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10825 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10826 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10827 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10828 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10829 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10830 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10831 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10832 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10833 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10834 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10835 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10836 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10838 /* Miscellaneous options. */
10839 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10840 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10841 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10842 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10843 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10844 {"break", no_argument
, NULL
, OPTION_BREAK
},
10845 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10846 #define OPTION_EB (OPTION_MISC_BASE + 2)
10847 {"EB", no_argument
, NULL
, OPTION_EB
},
10848 #define OPTION_EL (OPTION_MISC_BASE + 3)
10849 {"EL", no_argument
, NULL
, OPTION_EL
},
10850 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10851 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10852 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10853 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10854 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10855 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10856 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10857 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10858 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10859 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10860 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10861 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10862 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10863 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10864 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10865 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10866 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10867 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10868 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10869 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10870 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10871 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10872 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10873 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10875 /* ELF-specific options. */
10877 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10878 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10879 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10880 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10881 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10882 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10883 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10884 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10885 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10886 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10887 #define OPTION_32 (OPTION_ELF_BASE + 4)
10888 {"32", no_argument
, NULL
, OPTION_32
},
10889 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10890 {"n32", no_argument
, NULL
, OPTION_N32
},
10891 #define OPTION_64 (OPTION_ELF_BASE + 6)
10892 {"64", no_argument
, NULL
, OPTION_64
},
10893 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10894 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10895 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10896 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10897 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10898 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10899 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10900 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10901 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10902 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
10903 #endif /* OBJ_ELF */
10905 {NULL
, no_argument
, NULL
, 0}
10907 size_t md_longopts_size
= sizeof (md_longopts
);
10909 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10910 NEW_VALUE. Warn if another value was already specified. Note:
10911 we have to defer parsing the -march and -mtune arguments in order
10912 to handle 'from-abi' correctly, since the ABI might be specified
10913 in a later argument. */
10916 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10918 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10919 as_warn (_("A different %s was already specified, is now %s"),
10920 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10923 *string_ptr
= new_value
;
10927 md_parse_option (int c
, char *arg
)
10931 case OPTION_CONSTRUCT_FLOATS
:
10932 mips_disable_float_construction
= 0;
10935 case OPTION_NO_CONSTRUCT_FLOATS
:
10936 mips_disable_float_construction
= 1;
10948 target_big_endian
= 1;
10952 target_big_endian
= 0;
10956 if (arg
&& arg
[1] == '0')
10966 mips_debug
= atoi (arg
);
10967 /* When the MIPS assembler sees -g or -g2, it does not do
10968 optimizations which limit full symbolic debugging. We take
10969 that to be equivalent to -O0. */
10970 if (mips_debug
== 2)
10975 file_mips_isa
= ISA_MIPS1
;
10979 file_mips_isa
= ISA_MIPS2
;
10983 file_mips_isa
= ISA_MIPS3
;
10987 file_mips_isa
= ISA_MIPS4
;
10991 file_mips_isa
= ISA_MIPS5
;
10994 case OPTION_MIPS32
:
10995 file_mips_isa
= ISA_MIPS32
;
10998 case OPTION_MIPS32R2
:
10999 file_mips_isa
= ISA_MIPS32R2
;
11002 case OPTION_MIPS64R2
:
11003 file_mips_isa
= ISA_MIPS64R2
;
11006 case OPTION_MIPS64
:
11007 file_mips_isa
= ISA_MIPS64
;
11011 mips_set_option_string (&mips_tune_string
, arg
);
11015 mips_set_option_string (&mips_arch_string
, arg
);
11019 mips_set_option_string (&mips_arch_string
, "4650");
11020 mips_set_option_string (&mips_tune_string
, "4650");
11023 case OPTION_NO_M4650
:
11027 mips_set_option_string (&mips_arch_string
, "4010");
11028 mips_set_option_string (&mips_tune_string
, "4010");
11031 case OPTION_NO_M4010
:
11035 mips_set_option_string (&mips_arch_string
, "4100");
11036 mips_set_option_string (&mips_tune_string
, "4100");
11039 case OPTION_NO_M4100
:
11043 mips_set_option_string (&mips_arch_string
, "3900");
11044 mips_set_option_string (&mips_tune_string
, "3900");
11047 case OPTION_NO_M3900
:
11051 mips_opts
.ase_mdmx
= 1;
11054 case OPTION_NO_MDMX
:
11055 mips_opts
.ase_mdmx
= 0;
11059 mips_opts
.ase_dsp
= 1;
11062 case OPTION_NO_DSP
:
11063 mips_opts
.ase_dsp
= 0;
11067 mips_opts
.ase_mt
= 1;
11071 mips_opts
.ase_mt
= 0;
11074 case OPTION_MIPS16
:
11075 mips_opts
.mips16
= 1;
11076 mips_no_prev_insn ();
11079 case OPTION_NO_MIPS16
:
11080 mips_opts
.mips16
= 0;
11081 mips_no_prev_insn ();
11084 case OPTION_MIPS3D
:
11085 mips_opts
.ase_mips3d
= 1;
11088 case OPTION_NO_MIPS3D
:
11089 mips_opts
.ase_mips3d
= 0;
11092 case OPTION_SMARTMIPS
:
11093 mips_opts
.ase_smartmips
= 1;
11096 case OPTION_NO_SMARTMIPS
:
11097 mips_opts
.ase_smartmips
= 0;
11100 case OPTION_FIX_VR4120
:
11101 mips_fix_vr4120
= 1;
11104 case OPTION_NO_FIX_VR4120
:
11105 mips_fix_vr4120
= 0;
11108 case OPTION_FIX_VR4130
:
11109 mips_fix_vr4130
= 1;
11112 case OPTION_NO_FIX_VR4130
:
11113 mips_fix_vr4130
= 0;
11116 case OPTION_RELAX_BRANCH
:
11117 mips_relax_branch
= 1;
11120 case OPTION_NO_RELAX_BRANCH
:
11121 mips_relax_branch
= 0;
11124 case OPTION_MSHARED
:
11125 mips_in_shared
= TRUE
;
11128 case OPTION_MNO_SHARED
:
11129 mips_in_shared
= FALSE
;
11132 case OPTION_MSYM32
:
11133 mips_opts
.sym32
= TRUE
;
11136 case OPTION_MNO_SYM32
:
11137 mips_opts
.sym32
= FALSE
;
11141 /* When generating ELF code, we permit -KPIC and -call_shared to
11142 select SVR4_PIC, and -non_shared to select no PIC. This is
11143 intended to be compatible with Irix 5. */
11144 case OPTION_CALL_SHARED
:
11145 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11147 as_bad (_("-call_shared is supported only for ELF format"));
11150 mips_pic
= SVR4_PIC
;
11151 mips_abicalls
= TRUE
;
11154 case OPTION_NON_SHARED
:
11155 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11157 as_bad (_("-non_shared is supported only for ELF format"));
11161 mips_abicalls
= FALSE
;
11164 /* The -xgot option tells the assembler to use 32 bit offsets
11165 when accessing the got in SVR4_PIC mode. It is for Irix
11170 #endif /* OBJ_ELF */
11173 g_switch_value
= atoi (arg
);
11178 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11181 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11183 as_bad (_("-32 is supported for ELF format only"));
11186 mips_abi
= O32_ABI
;
11190 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11192 as_bad (_("-n32 is supported for ELF format only"));
11195 mips_abi
= N32_ABI
;
11199 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11201 as_bad (_("-64 is supported for ELF format only"));
11204 mips_abi
= N64_ABI
;
11205 if (! support_64bit_objects())
11206 as_fatal (_("No compiled in support for 64 bit object file format"));
11208 #endif /* OBJ_ELF */
11211 file_mips_gp32
= 1;
11215 file_mips_gp32
= 0;
11219 file_mips_fp32
= 1;
11223 file_mips_fp32
= 0;
11228 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11230 as_bad (_("-mabi is supported for ELF format only"));
11233 if (strcmp (arg
, "32") == 0)
11234 mips_abi
= O32_ABI
;
11235 else if (strcmp (arg
, "o64") == 0)
11236 mips_abi
= O64_ABI
;
11237 else if (strcmp (arg
, "n32") == 0)
11238 mips_abi
= N32_ABI
;
11239 else if (strcmp (arg
, "64") == 0)
11241 mips_abi
= N64_ABI
;
11242 if (! support_64bit_objects())
11243 as_fatal (_("No compiled in support for 64 bit object file "
11246 else if (strcmp (arg
, "eabi") == 0)
11247 mips_abi
= EABI_ABI
;
11250 as_fatal (_("invalid abi -mabi=%s"), arg
);
11254 #endif /* OBJ_ELF */
11256 case OPTION_M7000_HILO_FIX
:
11257 mips_7000_hilo_fix
= TRUE
;
11260 case OPTION_MNO_7000_HILO_FIX
:
11261 mips_7000_hilo_fix
= FALSE
;
11265 case OPTION_MDEBUG
:
11266 mips_flag_mdebug
= TRUE
;
11269 case OPTION_NO_MDEBUG
:
11270 mips_flag_mdebug
= FALSE
;
11274 mips_flag_pdr
= TRUE
;
11277 case OPTION_NO_PDR
:
11278 mips_flag_pdr
= FALSE
;
11281 case OPTION_MVXWORKS_PIC
:
11282 mips_pic
= VXWORKS_PIC
;
11284 #endif /* OBJ_ELF */
11293 /* Set up globals to generate code for the ISA or processor
11294 described by INFO. */
11297 mips_set_architecture (const struct mips_cpu_info
*info
)
11301 file_mips_arch
= info
->cpu
;
11302 mips_opts
.arch
= info
->cpu
;
11303 mips_opts
.isa
= info
->isa
;
11308 /* Likewise for tuning. */
11311 mips_set_tune (const struct mips_cpu_info
*info
)
11314 mips_tune
= info
->cpu
;
11319 mips_after_parse_args (void)
11321 const struct mips_cpu_info
*arch_info
= 0;
11322 const struct mips_cpu_info
*tune_info
= 0;
11324 /* GP relative stuff not working for PE */
11325 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11327 if (g_switch_seen
&& g_switch_value
!= 0)
11328 as_bad (_("-G not supported in this configuration."));
11329 g_switch_value
= 0;
11332 if (mips_abi
== NO_ABI
)
11333 mips_abi
= MIPS_DEFAULT_ABI
;
11335 /* The following code determines the architecture and register size.
11336 Similar code was added to GCC 3.3 (see override_options() in
11337 config/mips/mips.c). The GAS and GCC code should be kept in sync
11338 as much as possible. */
11340 if (mips_arch_string
!= 0)
11341 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11343 if (file_mips_isa
!= ISA_UNKNOWN
)
11345 /* Handle -mipsN. At this point, file_mips_isa contains the
11346 ISA level specified by -mipsN, while arch_info->isa contains
11347 the -march selection (if any). */
11348 if (arch_info
!= 0)
11350 /* -march takes precedence over -mipsN, since it is more descriptive.
11351 There's no harm in specifying both as long as the ISA levels
11353 if (file_mips_isa
!= arch_info
->isa
)
11354 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11355 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11356 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11359 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11362 if (arch_info
== 0)
11363 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11365 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11366 as_bad ("-march=%s is not compatible with the selected ABI",
11369 mips_set_architecture (arch_info
);
11371 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11372 if (mips_tune_string
!= 0)
11373 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11375 if (tune_info
== 0)
11376 mips_set_tune (arch_info
);
11378 mips_set_tune (tune_info
);
11380 if (file_mips_gp32
>= 0)
11382 /* The user specified the size of the integer registers. Make sure
11383 it agrees with the ABI and ISA. */
11384 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11385 as_bad (_("-mgp64 used with a 32-bit processor"));
11386 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11387 as_bad (_("-mgp32 used with a 64-bit ABI"));
11388 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11389 as_bad (_("-mgp64 used with a 32-bit ABI"));
11393 /* Infer the integer register size from the ABI and processor.
11394 Restrict ourselves to 32-bit registers if that's all the
11395 processor has, or if the ABI cannot handle 64-bit registers. */
11396 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11397 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11400 switch (file_mips_fp32
)
11404 /* No user specified float register size.
11405 ??? GAS treats single-float processors as though they had 64-bit
11406 float registers (although it complains when double-precision
11407 instructions are used). As things stand, saying they have 32-bit
11408 registers would lead to spurious "register must be even" messages.
11409 So here we assume float registers are never smaller than the
11411 if (file_mips_gp32
== 0)
11412 /* 64-bit integer registers implies 64-bit float registers. */
11413 file_mips_fp32
= 0;
11414 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11415 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11416 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11417 file_mips_fp32
= 0;
11419 /* 32-bit float registers. */
11420 file_mips_fp32
= 1;
11423 /* The user specified the size of the float registers. Check if it
11424 agrees with the ABI and ISA. */
11426 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11427 as_bad (_("-mfp64 used with a 32-bit fpu"));
11428 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11429 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11430 as_warn (_("-mfp64 used with a 32-bit ABI"));
11433 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11434 as_warn (_("-mfp32 used with a 64-bit ABI"));
11438 /* End of GCC-shared inference code. */
11440 /* This flag is set when we have a 64-bit capable CPU but use only
11441 32-bit wide registers. Note that EABI does not use it. */
11442 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11443 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11444 || mips_abi
== O32_ABI
))
11445 mips_32bitmode
= 1;
11447 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11448 as_bad (_("trap exception not supported at ISA 1"));
11450 /* If the selected architecture includes support for ASEs, enable
11451 generation of code for them. */
11452 if (mips_opts
.mips16
== -1)
11453 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11454 if (mips_opts
.ase_mips3d
== -1)
11455 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11456 && file_mips_fp32
== 0) ? 1 : 0;
11457 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11458 as_bad (_("-mfp32 used with -mips3d"));
11460 if (mips_opts
.ase_mdmx
== -1)
11461 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11462 && file_mips_fp32
== 0) ? 1 : 0;
11463 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11464 as_bad (_("-mfp32 used with -mdmx"));
11466 if (mips_opts
.ase_smartmips
== -1)
11467 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11468 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11469 as_warn ("%s ISA does not support SmartMIPS",
11470 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11472 if (mips_opts
.ase_dsp
== -1)
11473 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11474 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11475 as_warn ("%s ISA does not support DSP ASE",
11476 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11478 if (mips_opts
.ase_mt
== -1)
11479 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11480 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11481 as_warn ("%s ISA does not support MT ASE",
11482 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11484 file_mips_isa
= mips_opts
.isa
;
11485 file_ase_mips16
= mips_opts
.mips16
;
11486 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11487 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11488 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11489 file_ase_dsp
= mips_opts
.ase_dsp
;
11490 file_ase_mt
= mips_opts
.ase_mt
;
11491 mips_opts
.gp32
= file_mips_gp32
;
11492 mips_opts
.fp32
= file_mips_fp32
;
11494 if (mips_flag_mdebug
< 0)
11496 #ifdef OBJ_MAYBE_ECOFF
11497 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11498 mips_flag_mdebug
= 1;
11500 #endif /* OBJ_MAYBE_ECOFF */
11501 mips_flag_mdebug
= 0;
11506 mips_init_after_args (void)
11508 /* initialize opcodes */
11509 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11510 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11514 md_pcrel_from (fixS
*fixP
)
11516 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11517 switch (fixP
->fx_r_type
)
11519 case BFD_RELOC_16_PCREL_S2
:
11520 case BFD_RELOC_MIPS_JMP
:
11521 /* Return the address of the delay slot. */
11528 /* This is called before the symbol table is processed. In order to
11529 work with gcc when using mips-tfile, we must keep all local labels.
11530 However, in other cases, we want to discard them. If we were
11531 called with -g, but we didn't see any debugging information, it may
11532 mean that gcc is smuggling debugging information through to
11533 mips-tfile, in which case we must generate all local labels. */
11536 mips_frob_file_before_adjust (void)
11538 #ifndef NO_ECOFF_DEBUGGING
11539 if (ECOFF_DEBUGGING
11541 && ! ecoff_debugging_seen
)
11542 flag_keep_locals
= 1;
11546 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11547 the corresponding LO16 reloc. This is called before md_apply_fix and
11548 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11549 relocation operators.
11551 For our purposes, a %lo() expression matches a %got() or %hi()
11554 (a) it refers to the same symbol; and
11555 (b) the offset applied in the %lo() expression is no lower than
11556 the offset applied in the %got() or %hi().
11558 (b) allows us to cope with code like:
11561 lh $4,%lo(foo+2)($4)
11563 ...which is legal on RELA targets, and has a well-defined behaviour
11564 if the user knows that adding 2 to "foo" will not induce a carry to
11567 When several %lo()s match a particular %got() or %hi(), we use the
11568 following rules to distinguish them:
11570 (1) %lo()s with smaller offsets are a better match than %lo()s with
11573 (2) %lo()s with no matching %got() or %hi() are better than those
11574 that already have a matching %got() or %hi().
11576 (3) later %lo()s are better than earlier %lo()s.
11578 These rules are applied in order.
11580 (1) means, among other things, that %lo()s with identical offsets are
11581 chosen if they exist.
11583 (2) means that we won't associate several high-part relocations with
11584 the same low-part relocation unless there's no alternative. Having
11585 several high parts for the same low part is a GNU extension; this rule
11586 allows careful users to avoid it.
11588 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11589 with the last high-part relocation being at the front of the list.
11590 It therefore makes sense to choose the last matching low-part
11591 relocation, all other things being equal. It's also easier
11592 to code that way. */
11595 mips_frob_file (void)
11597 struct mips_hi_fixup
*l
;
11599 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11601 segment_info_type
*seginfo
;
11602 bfd_boolean matched_lo_p
;
11603 fixS
**hi_pos
, **lo_pos
, **pos
;
11605 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11607 /* If a GOT16 relocation turns out to be against a global symbol,
11608 there isn't supposed to be a matching LO. */
11609 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11610 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11613 /* Check quickly whether the next fixup happens to be a matching %lo. */
11614 if (fixup_has_matching_lo_p (l
->fixp
))
11617 seginfo
= seg_info (l
->seg
);
11619 /* Set HI_POS to the position of this relocation in the chain.
11620 Set LO_POS to the position of the chosen low-part relocation.
11621 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11622 relocation that matches an immediately-preceding high-part
11626 matched_lo_p
= FALSE
;
11627 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11629 if (*pos
== l
->fixp
)
11632 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
11633 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
11634 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11635 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11637 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11639 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11642 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11643 && fixup_has_matching_lo_p (*pos
));
11646 /* If we found a match, remove the high-part relocation from its
11647 current position and insert it before the low-part relocation.
11648 Make the offsets match so that fixup_has_matching_lo_p()
11651 We don't warn about unmatched high-part relocations since some
11652 versions of gcc have been known to emit dead "lui ...%hi(...)"
11654 if (lo_pos
!= NULL
)
11656 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11657 if (l
->fixp
->fx_next
!= *lo_pos
)
11659 *hi_pos
= l
->fixp
->fx_next
;
11660 l
->fixp
->fx_next
= *lo_pos
;
11667 /* We may have combined relocations without symbols in the N32/N64 ABI.
11668 We have to prevent gas from dropping them. */
11671 mips_force_relocation (fixS
*fixp
)
11673 if (generic_force_reloc (fixp
))
11677 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11678 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11679 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11680 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11686 /* Apply a fixup to the object file. */
11689 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11693 reloc_howto_type
*howto
;
11695 /* We ignore generic BFD relocations we don't know about. */
11696 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11700 assert (fixP
->fx_size
== 4
11701 || fixP
->fx_r_type
== BFD_RELOC_16
11702 || fixP
->fx_r_type
== BFD_RELOC_64
11703 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11704 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11705 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11706 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11708 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11710 assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
11712 /* Don't treat parts of a composite relocation as done. There are two
11715 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11716 should nevertheless be emitted if the first part is.
11718 (2) In normal usage, composite relocations are never assembly-time
11719 constants. The easiest way of dealing with the pathological
11720 exceptions is to generate a relocation against STN_UNDEF and
11721 leave everything up to the linker. */
11722 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
11725 switch (fixP
->fx_r_type
)
11727 case BFD_RELOC_MIPS_TLS_GD
:
11728 case BFD_RELOC_MIPS_TLS_LDM
:
11729 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11730 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11731 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11732 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11733 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11734 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11737 case BFD_RELOC_MIPS_JMP
:
11738 case BFD_RELOC_MIPS_SHIFT5
:
11739 case BFD_RELOC_MIPS_SHIFT6
:
11740 case BFD_RELOC_MIPS_GOT_DISP
:
11741 case BFD_RELOC_MIPS_GOT_PAGE
:
11742 case BFD_RELOC_MIPS_GOT_OFST
:
11743 case BFD_RELOC_MIPS_SUB
:
11744 case BFD_RELOC_MIPS_INSERT_A
:
11745 case BFD_RELOC_MIPS_INSERT_B
:
11746 case BFD_RELOC_MIPS_DELETE
:
11747 case BFD_RELOC_MIPS_HIGHEST
:
11748 case BFD_RELOC_MIPS_HIGHER
:
11749 case BFD_RELOC_MIPS_SCN_DISP
:
11750 case BFD_RELOC_MIPS_REL16
:
11751 case BFD_RELOC_MIPS_RELGOT
:
11752 case BFD_RELOC_MIPS_JALR
:
11753 case BFD_RELOC_HI16
:
11754 case BFD_RELOC_HI16_S
:
11755 case BFD_RELOC_GPREL16
:
11756 case BFD_RELOC_MIPS_LITERAL
:
11757 case BFD_RELOC_MIPS_CALL16
:
11758 case BFD_RELOC_MIPS_GOT16
:
11759 case BFD_RELOC_GPREL32
:
11760 case BFD_RELOC_MIPS_GOT_HI16
:
11761 case BFD_RELOC_MIPS_GOT_LO16
:
11762 case BFD_RELOC_MIPS_CALL_HI16
:
11763 case BFD_RELOC_MIPS_CALL_LO16
:
11764 case BFD_RELOC_MIPS16_GPREL
:
11765 case BFD_RELOC_MIPS16_HI16
:
11766 case BFD_RELOC_MIPS16_HI16_S
:
11767 /* Nothing needed to do. The value comes from the reloc entry */
11770 case BFD_RELOC_MIPS16_JMP
:
11771 /* We currently always generate a reloc against a symbol, which
11772 means that we don't want an addend even if the symbol is
11778 /* This is handled like BFD_RELOC_32, but we output a sign
11779 extended value if we are only 32 bits. */
11782 if (8 <= sizeof (valueT
))
11783 md_number_to_chars ((char *) buf
, *valP
, 8);
11788 if ((*valP
& 0x80000000) != 0)
11792 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11794 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11800 case BFD_RELOC_RVA
:
11802 /* If we are deleting this reloc entry, we must fill in the
11803 value now. This can happen if we have a .word which is not
11804 resolved when it appears but is later defined. */
11806 md_number_to_chars ((char *) buf
, *valP
, 4);
11810 /* If we are deleting this reloc entry, we must fill in the
11813 md_number_to_chars ((char *) buf
, *valP
, 2);
11816 case BFD_RELOC_LO16
:
11817 case BFD_RELOC_MIPS16_LO16
:
11818 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11819 may be safe to remove, but if so it's not obvious. */
11820 /* When handling an embedded PIC switch statement, we can wind
11821 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11824 if (*valP
+ 0x8000 > 0xffff)
11825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11826 _("relocation overflow"));
11827 if (target_big_endian
)
11829 md_number_to_chars ((char *) buf
, *valP
, 2);
11833 case BFD_RELOC_16_PCREL_S2
:
11834 if ((*valP
& 0x3) != 0)
11835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11836 _("Branch to misaligned address (%lx)"), (long) *valP
);
11839 * We need to save the bits in the instruction since fixup_segment()
11840 * might be deleting the relocation entry (i.e., a branch within
11841 * the current segment).
11843 if (! fixP
->fx_done
)
11846 /* update old instruction data */
11847 if (target_big_endian
)
11848 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11850 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11852 if (*valP
+ 0x20000 <= 0x3ffff)
11854 insn
|= (*valP
>> 2) & 0xffff;
11855 md_number_to_chars ((char *) buf
, insn
, 4);
11857 else if (mips_pic
== NO_PIC
11859 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11860 && (fixP
->fx_frag
->fr_address
11861 < text_section
->vma
+ bfd_get_section_size (text_section
))
11862 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11863 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11864 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11866 /* The branch offset is too large. If this is an
11867 unconditional branch, and we are not generating PIC code,
11868 we can convert it to an absolute jump instruction. */
11869 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11870 insn
= 0x0c000000; /* jal */
11872 insn
= 0x08000000; /* j */
11873 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11875 fixP
->fx_addsy
= section_symbol (text_section
);
11876 *valP
+= md_pcrel_from (fixP
);
11877 md_number_to_chars ((char *) buf
, insn
, 4);
11881 /* If we got here, we have branch-relaxation disabled,
11882 and there's nothing we can do to fix this instruction
11883 without turning it into a longer sequence. */
11884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11885 _("Branch out of range"));
11889 case BFD_RELOC_VTABLE_INHERIT
:
11892 && !S_IS_DEFINED (fixP
->fx_addsy
)
11893 && !S_IS_WEAK (fixP
->fx_addsy
))
11894 S_SET_WEAK (fixP
->fx_addsy
);
11897 case BFD_RELOC_VTABLE_ENTRY
:
11905 /* Remember value for tc_gen_reloc. */
11906 fixP
->fx_addnumber
= *valP
;
11916 name
= input_line_pointer
;
11917 c
= get_symbol_end ();
11918 p
= (symbolS
*) symbol_find_or_make (name
);
11919 *input_line_pointer
= c
;
11923 /* Align the current frag to a given power of two. The MIPS assembler
11924 also automatically adjusts any preceding label. */
11927 mips_align (int to
, int fill
, symbolS
*label
)
11929 mips_emit_delays ();
11930 frag_align (to
, fill
, 0);
11931 record_alignment (now_seg
, to
);
11934 assert (S_GET_SEGMENT (label
) == now_seg
);
11935 symbol_set_frag (label
, frag_now
);
11936 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11940 /* Align to a given power of two. .align 0 turns off the automatic
11941 alignment used by the data creating pseudo-ops. */
11944 s_align (int x ATTRIBUTE_UNUSED
)
11948 long max_alignment
= 15;
11952 o Note that the assembler pulls down any immediately preceding label
11953 to the aligned address.
11954 o It's not documented but auto alignment is reinstated by
11955 a .align pseudo instruction.
11956 o Note also that after auto alignment is turned off the mips assembler
11957 issues an error on attempt to assemble an improperly aligned data item.
11962 temp
= get_absolute_expression ();
11963 if (temp
> max_alignment
)
11964 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11967 as_warn (_("Alignment negative: 0 assumed."));
11970 if (*input_line_pointer
== ',')
11972 ++input_line_pointer
;
11973 temp_fill
= get_absolute_expression ();
11979 segment_info_type
*si
= seg_info (now_seg
);
11980 struct insn_label_list
*l
= si
->label_list
;
11981 /* Auto alignment should be switched on by next section change */
11983 mips_align (temp
, (int) temp_fill
, l
!= NULL
? l
->label
: NULL
);
11990 demand_empty_rest_of_line ();
11994 s_change_sec (int sec
)
11999 /* The ELF backend needs to know that we are changing sections, so
12000 that .previous works correctly. We could do something like check
12001 for an obj_section_change_hook macro, but that might be confusing
12002 as it would not be appropriate to use it in the section changing
12003 functions in read.c, since obj-elf.c intercepts those. FIXME:
12004 This should be cleaner, somehow. */
12005 obj_elf_section_change_hook ();
12008 mips_emit_delays ();
12018 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12019 demand_empty_rest_of_line ();
12023 seg
= subseg_new (RDATA_SECTION_NAME
,
12024 (subsegT
) get_absolute_expression ());
12025 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12027 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12028 | SEC_READONLY
| SEC_RELOC
12030 if (strcmp (TARGET_OS
, "elf") != 0)
12031 record_alignment (seg
, 4);
12033 demand_empty_rest_of_line ();
12037 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12038 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12040 bfd_set_section_flags (stdoutput
, seg
,
12041 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12042 if (strcmp (TARGET_OS
, "elf") != 0)
12043 record_alignment (seg
, 4);
12045 demand_empty_rest_of_line ();
12053 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12056 char *section_name
;
12061 int section_entry_size
;
12062 int section_alignment
;
12064 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12067 section_name
= input_line_pointer
;
12068 c
= get_symbol_end ();
12070 next_c
= *(input_line_pointer
+ 1);
12072 /* Do we have .section Name<,"flags">? */
12073 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12075 /* just after name is now '\0'. */
12076 *input_line_pointer
= c
;
12077 input_line_pointer
= section_name
;
12078 obj_elf_section (ignore
);
12081 input_line_pointer
++;
12083 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12085 section_type
= get_absolute_expression ();
12088 if (*input_line_pointer
++ == ',')
12089 section_flag
= get_absolute_expression ();
12092 if (*input_line_pointer
++ == ',')
12093 section_entry_size
= get_absolute_expression ();
12095 section_entry_size
= 0;
12096 if (*input_line_pointer
++ == ',')
12097 section_alignment
= get_absolute_expression ();
12099 section_alignment
= 0;
12101 section_name
= xstrdup (section_name
);
12103 /* When using the generic form of .section (as implemented by obj-elf.c),
12104 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12105 traditionally had to fall back on the more common @progbits instead.
12107 There's nothing really harmful in this, since bfd will correct
12108 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12109 means that, for backwards compatibility, the special_section entries
12110 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12112 Even so, we shouldn't force users of the MIPS .section syntax to
12113 incorrectly label the sections as SHT_PROGBITS. The best compromise
12114 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12115 generic type-checking code. */
12116 if (section_type
== SHT_MIPS_DWARF
)
12117 section_type
= SHT_PROGBITS
;
12119 obj_elf_change_section (section_name
, section_type
, section_flag
,
12120 section_entry_size
, 0, 0, 0);
12122 if (now_seg
->name
!= section_name
)
12123 free (section_name
);
12124 #endif /* OBJ_ELF */
12128 mips_enable_auto_align (void)
12134 s_cons (int log_size
)
12136 segment_info_type
*si
= seg_info (now_seg
);
12137 struct insn_label_list
*l
= si
->label_list
;
12140 label
= l
!= NULL
? l
->label
: NULL
;
12141 mips_emit_delays ();
12142 if (log_size
> 0 && auto_align
)
12143 mips_align (log_size
, 0, label
);
12144 mips_clear_insn_labels ();
12145 cons (1 << log_size
);
12149 s_float_cons (int type
)
12151 segment_info_type
*si
= seg_info (now_seg
);
12152 struct insn_label_list
*l
= si
->label_list
;
12155 label
= l
!= NULL
? l
->label
: NULL
;
12157 mips_emit_delays ();
12162 mips_align (3, 0, label
);
12164 mips_align (2, 0, label
);
12167 mips_clear_insn_labels ();
12172 /* Handle .globl. We need to override it because on Irix 5 you are
12175 where foo is an undefined symbol, to mean that foo should be
12176 considered to be the address of a function. */
12179 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12188 name
= input_line_pointer
;
12189 c
= get_symbol_end ();
12190 symbolP
= symbol_find_or_make (name
);
12191 S_SET_EXTERNAL (symbolP
);
12193 *input_line_pointer
= c
;
12194 SKIP_WHITESPACE ();
12196 /* On Irix 5, every global symbol that is not explicitly labelled as
12197 being a function is apparently labelled as being an object. */
12200 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12201 && (*input_line_pointer
!= ','))
12206 secname
= input_line_pointer
;
12207 c
= get_symbol_end ();
12208 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12210 as_bad (_("%s: no such section"), secname
);
12211 *input_line_pointer
= c
;
12213 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12214 flag
= BSF_FUNCTION
;
12217 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12219 c
= *input_line_pointer
;
12222 input_line_pointer
++;
12223 SKIP_WHITESPACE ();
12224 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12230 demand_empty_rest_of_line ();
12234 s_option (int x ATTRIBUTE_UNUSED
)
12239 opt
= input_line_pointer
;
12240 c
= get_symbol_end ();
12244 /* FIXME: What does this mean? */
12246 else if (strncmp (opt
, "pic", 3) == 0)
12250 i
= atoi (opt
+ 3);
12255 mips_pic
= SVR4_PIC
;
12256 mips_abicalls
= TRUE
;
12259 as_bad (_(".option pic%d not supported"), i
);
12261 if (mips_pic
== SVR4_PIC
)
12263 if (g_switch_seen
&& g_switch_value
!= 0)
12264 as_warn (_("-G may not be used with SVR4 PIC code"));
12265 g_switch_value
= 0;
12266 bfd_set_gp_size (stdoutput
, 0);
12270 as_warn (_("Unrecognized option \"%s\""), opt
);
12272 *input_line_pointer
= c
;
12273 demand_empty_rest_of_line ();
12276 /* This structure is used to hold a stack of .set values. */
12278 struct mips_option_stack
12280 struct mips_option_stack
*next
;
12281 struct mips_set_options options
;
12284 static struct mips_option_stack
*mips_opts_stack
;
12286 /* Handle the .set pseudo-op. */
12289 s_mipsset (int x ATTRIBUTE_UNUSED
)
12291 char *name
= input_line_pointer
, ch
;
12293 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12294 ++input_line_pointer
;
12295 ch
= *input_line_pointer
;
12296 *input_line_pointer
= '\0';
12298 if (strcmp (name
, "reorder") == 0)
12300 if (mips_opts
.noreorder
)
12303 else if (strcmp (name
, "noreorder") == 0)
12305 if (!mips_opts
.noreorder
)
12306 start_noreorder ();
12308 else if (strcmp (name
, "at") == 0)
12310 mips_opts
.noat
= 0;
12312 else if (strcmp (name
, "noat") == 0)
12314 mips_opts
.noat
= 1;
12316 else if (strcmp (name
, "macro") == 0)
12318 mips_opts
.warn_about_macros
= 0;
12320 else if (strcmp (name
, "nomacro") == 0)
12322 if (mips_opts
.noreorder
== 0)
12323 as_bad (_("`noreorder' must be set before `nomacro'"));
12324 mips_opts
.warn_about_macros
= 1;
12326 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12328 mips_opts
.nomove
= 0;
12330 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12332 mips_opts
.nomove
= 1;
12334 else if (strcmp (name
, "bopt") == 0)
12336 mips_opts
.nobopt
= 0;
12338 else if (strcmp (name
, "nobopt") == 0)
12340 mips_opts
.nobopt
= 1;
12342 else if (strcmp (name
, "gp=default") == 0)
12343 mips_opts
.gp32
= file_mips_gp32
;
12344 else if (strcmp (name
, "gp=32") == 0)
12345 mips_opts
.gp32
= 1;
12346 else if (strcmp (name
, "gp=64") == 0)
12348 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12349 as_warn ("%s isa does not support 64-bit registers",
12350 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12351 mips_opts
.gp32
= 0;
12353 else if (strcmp (name
, "fp=default") == 0)
12354 mips_opts
.fp32
= file_mips_fp32
;
12355 else if (strcmp (name
, "fp=32") == 0)
12356 mips_opts
.fp32
= 1;
12357 else if (strcmp (name
, "fp=64") == 0)
12359 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12360 as_warn ("%s isa does not support 64-bit floating point registers",
12361 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12362 mips_opts
.fp32
= 0;
12364 else if (strcmp (name
, "mips16") == 0
12365 || strcmp (name
, "MIPS-16") == 0)
12366 mips_opts
.mips16
= 1;
12367 else if (strcmp (name
, "nomips16") == 0
12368 || strcmp (name
, "noMIPS-16") == 0)
12369 mips_opts
.mips16
= 0;
12370 else if (strcmp (name
, "smartmips") == 0)
12372 if (!ISA_SUPPORTS_SMARTMIPS
)
12373 as_warn ("%s ISA does not support SmartMIPS ASE",
12374 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12375 mips_opts
.ase_smartmips
= 1;
12377 else if (strcmp (name
, "nosmartmips") == 0)
12378 mips_opts
.ase_smartmips
= 0;
12379 else if (strcmp (name
, "mips3d") == 0)
12380 mips_opts
.ase_mips3d
= 1;
12381 else if (strcmp (name
, "nomips3d") == 0)
12382 mips_opts
.ase_mips3d
= 0;
12383 else if (strcmp (name
, "mdmx") == 0)
12384 mips_opts
.ase_mdmx
= 1;
12385 else if (strcmp (name
, "nomdmx") == 0)
12386 mips_opts
.ase_mdmx
= 0;
12387 else if (strcmp (name
, "dsp") == 0)
12389 if (!ISA_SUPPORTS_DSP_ASE
)
12390 as_warn ("%s ISA does not support DSP ASE",
12391 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12392 mips_opts
.ase_dsp
= 1;
12394 else if (strcmp (name
, "nodsp") == 0)
12395 mips_opts
.ase_dsp
= 0;
12396 else if (strcmp (name
, "mt") == 0)
12398 if (!ISA_SUPPORTS_MT_ASE
)
12399 as_warn ("%s ISA does not support MT ASE",
12400 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12401 mips_opts
.ase_mt
= 1;
12403 else if (strcmp (name
, "nomt") == 0)
12404 mips_opts
.ase_mt
= 0;
12405 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12409 /* Permit the user to change the ISA and architecture on the fly.
12410 Needless to say, misuse can cause serious problems. */
12411 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12414 mips_opts
.isa
= file_mips_isa
;
12415 mips_opts
.arch
= file_mips_arch
;
12417 else if (strncmp (name
, "arch=", 5) == 0)
12419 const struct mips_cpu_info
*p
;
12421 p
= mips_parse_cpu("internal use", name
+ 5);
12423 as_bad (_("unknown architecture %s"), name
+ 5);
12426 mips_opts
.arch
= p
->cpu
;
12427 mips_opts
.isa
= p
->isa
;
12430 else if (strncmp (name
, "mips", 4) == 0)
12432 const struct mips_cpu_info
*p
;
12434 p
= mips_parse_cpu("internal use", name
);
12436 as_bad (_("unknown ISA level %s"), name
+ 4);
12439 mips_opts
.arch
= p
->cpu
;
12440 mips_opts
.isa
= p
->isa
;
12444 as_bad (_("unknown ISA or architecture %s"), name
);
12446 switch (mips_opts
.isa
)
12454 mips_opts
.gp32
= 1;
12455 mips_opts
.fp32
= 1;
12462 mips_opts
.gp32
= 0;
12463 mips_opts
.fp32
= 0;
12466 as_bad (_("unknown ISA level %s"), name
+ 4);
12471 mips_opts
.gp32
= file_mips_gp32
;
12472 mips_opts
.fp32
= file_mips_fp32
;
12475 else if (strcmp (name
, "autoextend") == 0)
12476 mips_opts
.noautoextend
= 0;
12477 else if (strcmp (name
, "noautoextend") == 0)
12478 mips_opts
.noautoextend
= 1;
12479 else if (strcmp (name
, "push") == 0)
12481 struct mips_option_stack
*s
;
12483 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12484 s
->next
= mips_opts_stack
;
12485 s
->options
= mips_opts
;
12486 mips_opts_stack
= s
;
12488 else if (strcmp (name
, "pop") == 0)
12490 struct mips_option_stack
*s
;
12492 s
= mips_opts_stack
;
12494 as_bad (_(".set pop with no .set push"));
12497 /* If we're changing the reorder mode we need to handle
12498 delay slots correctly. */
12499 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12500 start_noreorder ();
12501 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12504 mips_opts
= s
->options
;
12505 mips_opts_stack
= s
->next
;
12509 else if (strcmp (name
, "sym32") == 0)
12510 mips_opts
.sym32
= TRUE
;
12511 else if (strcmp (name
, "nosym32") == 0)
12512 mips_opts
.sym32
= FALSE
;
12515 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12517 *input_line_pointer
= ch
;
12518 demand_empty_rest_of_line ();
12521 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12522 .option pic2. It means to generate SVR4 PIC calls. */
12525 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12527 mips_pic
= SVR4_PIC
;
12528 mips_abicalls
= TRUE
;
12530 if (g_switch_seen
&& g_switch_value
!= 0)
12531 as_warn (_("-G may not be used with SVR4 PIC code"));
12532 g_switch_value
= 0;
12534 bfd_set_gp_size (stdoutput
, 0);
12535 demand_empty_rest_of_line ();
12538 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12539 PIC code. It sets the $gp register for the function based on the
12540 function address, which is in the register named in the argument.
12541 This uses a relocation against _gp_disp, which is handled specially
12542 by the linker. The result is:
12543 lui $gp,%hi(_gp_disp)
12544 addiu $gp,$gp,%lo(_gp_disp)
12545 addu $gp,$gp,.cpload argument
12546 The .cpload argument is normally $25 == $t9.
12548 The -mno-shared option changes this to:
12549 lui $gp,%hi(__gnu_local_gp)
12550 addiu $gp,$gp,%lo(__gnu_local_gp)
12551 and the argument is ignored. This saves an instruction, but the
12552 resulting code is not position independent; it uses an absolute
12553 address for __gnu_local_gp. Thus code assembled with -mno-shared
12554 can go into an ordinary executable, but not into a shared library. */
12557 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12563 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12564 .cpload is ignored. */
12565 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12571 /* .cpload should be in a .set noreorder section. */
12572 if (mips_opts
.noreorder
== 0)
12573 as_warn (_(".cpload not in noreorder section"));
12575 reg
= tc_get_register (0);
12577 /* If we need to produce a 64-bit address, we are better off using
12578 the default instruction sequence. */
12579 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12581 ex
.X_op
= O_symbol
;
12582 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12584 ex
.X_op_symbol
= NULL
;
12585 ex
.X_add_number
= 0;
12587 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12588 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12591 macro_build_lui (&ex
, mips_gp_register
);
12592 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12593 mips_gp_register
, BFD_RELOC_LO16
);
12595 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12596 mips_gp_register
, reg
);
12599 demand_empty_rest_of_line ();
12602 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12603 .cpsetup $reg1, offset|$reg2, label
12605 If offset is given, this results in:
12606 sd $gp, offset($sp)
12607 lui $gp, %hi(%neg(%gp_rel(label)))
12608 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12609 daddu $gp, $gp, $reg1
12611 If $reg2 is given, this results in:
12612 daddu $reg2, $gp, $0
12613 lui $gp, %hi(%neg(%gp_rel(label)))
12614 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12615 daddu $gp, $gp, $reg1
12616 $reg1 is normally $25 == $t9.
12618 The -mno-shared option replaces the last three instructions with
12620 addiu $gp,$gp,%lo(_gp)
12624 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12626 expressionS ex_off
;
12627 expressionS ex_sym
;
12630 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12631 We also need NewABI support. */
12632 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12638 reg1
= tc_get_register (0);
12639 SKIP_WHITESPACE ();
12640 if (*input_line_pointer
!= ',')
12642 as_bad (_("missing argument separator ',' for .cpsetup"));
12646 ++input_line_pointer
;
12647 SKIP_WHITESPACE ();
12648 if (*input_line_pointer
== '$')
12650 mips_cpreturn_register
= tc_get_register (0);
12651 mips_cpreturn_offset
= -1;
12655 mips_cpreturn_offset
= get_absolute_expression ();
12656 mips_cpreturn_register
= -1;
12658 SKIP_WHITESPACE ();
12659 if (*input_line_pointer
!= ',')
12661 as_bad (_("missing argument separator ',' for .cpsetup"));
12665 ++input_line_pointer
;
12666 SKIP_WHITESPACE ();
12667 expression (&ex_sym
);
12670 if (mips_cpreturn_register
== -1)
12672 ex_off
.X_op
= O_constant
;
12673 ex_off
.X_add_symbol
= NULL
;
12674 ex_off
.X_op_symbol
= NULL
;
12675 ex_off
.X_add_number
= mips_cpreturn_offset
;
12677 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12678 BFD_RELOC_LO16
, SP
);
12681 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12682 mips_gp_register
, 0);
12684 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12686 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12687 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12690 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12691 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12692 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12694 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12695 mips_gp_register
, reg1
);
12701 ex
.X_op
= O_symbol
;
12702 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12703 ex
.X_op_symbol
= NULL
;
12704 ex
.X_add_number
= 0;
12706 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12707 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12709 macro_build_lui (&ex
, mips_gp_register
);
12710 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12711 mips_gp_register
, BFD_RELOC_LO16
);
12716 demand_empty_rest_of_line ();
12720 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12722 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12723 .cplocal is ignored. */
12724 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12730 mips_gp_register
= tc_get_register (0);
12731 demand_empty_rest_of_line ();
12734 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12735 offset from $sp. The offset is remembered, and after making a PIC
12736 call $gp is restored from that location. */
12739 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12743 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12744 .cprestore is ignored. */
12745 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12751 mips_cprestore_offset
= get_absolute_expression ();
12752 mips_cprestore_valid
= 1;
12754 ex
.X_op
= O_constant
;
12755 ex
.X_add_symbol
= NULL
;
12756 ex
.X_op_symbol
= NULL
;
12757 ex
.X_add_number
= mips_cprestore_offset
;
12760 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12761 SP
, HAVE_64BIT_ADDRESSES
);
12764 demand_empty_rest_of_line ();
12767 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12768 was given in the preceding .cpsetup, it results in:
12769 ld $gp, offset($sp)
12771 If a register $reg2 was given there, it results in:
12772 daddu $gp, $reg2, $0
12775 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12779 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12780 We also need NewABI support. */
12781 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12788 if (mips_cpreturn_register
== -1)
12790 ex
.X_op
= O_constant
;
12791 ex
.X_add_symbol
= NULL
;
12792 ex
.X_op_symbol
= NULL
;
12793 ex
.X_add_number
= mips_cpreturn_offset
;
12795 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12798 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12799 mips_cpreturn_register
, 0);
12802 demand_empty_rest_of_line ();
12805 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12806 code. It sets the offset to use in gp_rel relocations. */
12809 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12811 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12812 We also need NewABI support. */
12813 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12819 mips_gprel_offset
= get_absolute_expression ();
12821 demand_empty_rest_of_line ();
12824 /* Handle the .gpword pseudo-op. This is used when generating PIC
12825 code. It generates a 32 bit GP relative reloc. */
12828 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12830 segment_info_type
*si
;
12831 struct insn_label_list
*l
;
12836 /* When not generating PIC code, this is treated as .word. */
12837 if (mips_pic
!= SVR4_PIC
)
12843 si
= seg_info (now_seg
);
12844 l
= si
->label_list
;
12845 label
= l
!= NULL
? l
->label
: NULL
;
12846 mips_emit_delays ();
12848 mips_align (2, 0, label
);
12849 mips_clear_insn_labels ();
12853 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12855 as_bad (_("Unsupported use of .gpword"));
12856 ignore_rest_of_line ();
12860 md_number_to_chars (p
, 0, 4);
12861 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12862 BFD_RELOC_GPREL32
);
12864 demand_empty_rest_of_line ();
12868 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12870 segment_info_type
*si
;
12871 struct insn_label_list
*l
;
12876 /* When not generating PIC code, this is treated as .dword. */
12877 if (mips_pic
!= SVR4_PIC
)
12883 si
= seg_info (now_seg
);
12884 l
= si
->label_list
;
12885 label
= l
!= NULL
? l
->label
: NULL
;
12886 mips_emit_delays ();
12888 mips_align (3, 0, label
);
12889 mips_clear_insn_labels ();
12893 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12895 as_bad (_("Unsupported use of .gpdword"));
12896 ignore_rest_of_line ();
12900 md_number_to_chars (p
, 0, 8);
12901 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12902 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12904 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12905 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12906 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12908 demand_empty_rest_of_line ();
12911 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12912 tables in SVR4 PIC code. */
12915 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12919 /* This is ignored when not generating SVR4 PIC code. */
12920 if (mips_pic
!= SVR4_PIC
)
12926 /* Add $gp to the register named as an argument. */
12928 reg
= tc_get_register (0);
12929 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12932 demand_empty_rest_of_line ();
12935 /* Handle the .insn pseudo-op. This marks instruction labels in
12936 mips16 mode. This permits the linker to handle them specially,
12937 such as generating jalx instructions when needed. We also make
12938 them odd for the duration of the assembly, in order to generate the
12939 right sort of code. We will make them even in the adjust_symtab
12940 routine, while leaving them marked. This is convenient for the
12941 debugger and the disassembler. The linker knows to make them odd
12945 s_insn (int ignore ATTRIBUTE_UNUSED
)
12947 mips16_mark_labels ();
12949 demand_empty_rest_of_line ();
12952 /* Handle a .stabn directive. We need these in order to mark a label
12953 as being a mips16 text label correctly. Sometimes the compiler
12954 will emit a label, followed by a .stabn, and then switch sections.
12955 If the label and .stabn are in mips16 mode, then the label is
12956 really a mips16 text label. */
12959 s_mips_stab (int type
)
12962 mips16_mark_labels ();
12967 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12971 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12978 name
= input_line_pointer
;
12979 c
= get_symbol_end ();
12980 symbolP
= symbol_find_or_make (name
);
12981 S_SET_WEAK (symbolP
);
12982 *input_line_pointer
= c
;
12984 SKIP_WHITESPACE ();
12986 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12988 if (S_IS_DEFINED (symbolP
))
12990 as_bad ("ignoring attempt to redefine symbol %s",
12991 S_GET_NAME (symbolP
));
12992 ignore_rest_of_line ();
12996 if (*input_line_pointer
== ',')
12998 ++input_line_pointer
;
12999 SKIP_WHITESPACE ();
13003 if (exp
.X_op
!= O_symbol
)
13005 as_bad ("bad .weakext directive");
13006 ignore_rest_of_line ();
13009 symbol_set_value_expression (symbolP
, &exp
);
13012 demand_empty_rest_of_line ();
13015 /* Parse a register string into a number. Called from the ECOFF code
13016 to parse .frame. The argument is non-zero if this is the frame
13017 register, so that we can record it in mips_frame_reg. */
13020 tc_get_register (int frame
)
13024 SKIP_WHITESPACE ();
13025 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13029 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13030 mips_frame_reg_valid
= 1;
13031 mips_cprestore_valid
= 0;
13037 md_section_align (asection
*seg
, valueT addr
)
13039 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13042 /* We don't need to align ELF sections to the full alignment.
13043 However, Irix 5 may prefer that we align them at least to a 16
13044 byte boundary. We don't bother to align the sections if we are
13045 targeted for an embedded system. */
13046 if (strcmp (TARGET_OS
, "elf") == 0)
13052 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13055 /* Utility routine, called from above as well. If called while the
13056 input file is still being read, it's only an approximation. (For
13057 example, a symbol may later become defined which appeared to be
13058 undefined earlier.) */
13061 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13066 if (g_switch_value
> 0)
13068 const char *symname
;
13071 /* Find out whether this symbol can be referenced off the $gp
13072 register. It can be if it is smaller than the -G size or if
13073 it is in the .sdata or .sbss section. Certain symbols can
13074 not be referenced off the $gp, although it appears as though
13076 symname
= S_GET_NAME (sym
);
13077 if (symname
!= (const char *) NULL
13078 && (strcmp (symname
, "eprol") == 0
13079 || strcmp (symname
, "etext") == 0
13080 || strcmp (symname
, "_gp") == 0
13081 || strcmp (symname
, "edata") == 0
13082 || strcmp (symname
, "_fbss") == 0
13083 || strcmp (symname
, "_fdata") == 0
13084 || strcmp (symname
, "_ftext") == 0
13085 || strcmp (symname
, "end") == 0
13086 || strcmp (symname
, "_gp_disp") == 0))
13088 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13090 #ifndef NO_ECOFF_DEBUGGING
13091 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13092 && (symbol_get_obj (sym
)->ecoff_extern_size
13093 <= g_switch_value
))
13095 /* We must defer this decision until after the whole
13096 file has been read, since there might be a .extern
13097 after the first use of this symbol. */
13098 || (before_relaxing
13099 #ifndef NO_ECOFF_DEBUGGING
13100 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13102 && S_GET_VALUE (sym
) == 0)
13103 || (S_GET_VALUE (sym
) != 0
13104 && S_GET_VALUE (sym
) <= g_switch_value
)))
13108 const char *segname
;
13110 segname
= segment_name (S_GET_SEGMENT (sym
));
13111 assert (strcmp (segname
, ".lit8") != 0
13112 && strcmp (segname
, ".lit4") != 0);
13113 change
= (strcmp (segname
, ".sdata") != 0
13114 && strcmp (segname
, ".sbss") != 0
13115 && strncmp (segname
, ".sdata.", 7) != 0
13116 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13121 /* We are not optimizing for the $gp register. */
13126 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13129 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13132 bfd_boolean linkonce
;
13134 /* Handle the case of a symbol equated to another symbol. */
13135 while (symbol_equated_reloc_p (sym
))
13139 /* It's possible to get a loop here in a badly written
13141 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13147 symsec
= S_GET_SEGMENT (sym
);
13149 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13151 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
13153 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
13157 /* The GNU toolchain uses an extension for ELF: a section
13158 beginning with the magic string .gnu.linkonce is a linkonce
13160 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
13161 sizeof ".gnu.linkonce" - 1) == 0)
13165 /* This must duplicate the test in adjust_reloc_syms. */
13166 return (symsec
!= &bfd_und_section
13167 && symsec
!= &bfd_abs_section
13168 && ! bfd_is_com_section (symsec
)
13171 /* A global or weak symbol is treated as external. */
13172 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13173 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13179 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13180 extended opcode. SEC is the section the frag is in. */
13183 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13186 const struct mips16_immed_operand
*op
;
13188 int mintiny
, maxtiny
;
13192 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13194 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13197 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13198 op
= mips16_immed_operands
;
13199 while (op
->type
!= type
)
13202 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13207 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13210 maxtiny
= 1 << op
->nbits
;
13215 maxtiny
= (1 << op
->nbits
) - 1;
13220 mintiny
= - (1 << (op
->nbits
- 1));
13221 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13224 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13225 val
= S_GET_VALUE (fragp
->fr_symbol
);
13226 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13232 /* We won't have the section when we are called from
13233 mips_relax_frag. However, we will always have been called
13234 from md_estimate_size_before_relax first. If this is a
13235 branch to a different section, we mark it as such. If SEC is
13236 NULL, and the frag is not marked, then it must be a branch to
13237 the same section. */
13240 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13245 /* Must have been called from md_estimate_size_before_relax. */
13248 fragp
->fr_subtype
=
13249 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13251 /* FIXME: We should support this, and let the linker
13252 catch branches and loads that are out of range. */
13253 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13254 _("unsupported PC relative reference to different section"));
13258 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13259 /* Assume non-extended on the first relaxation pass.
13260 The address we have calculated will be bogus if this is
13261 a forward branch to another frag, as the forward frag
13262 will have fr_address == 0. */
13266 /* In this case, we know for sure that the symbol fragment is in
13267 the same section. If the relax_marker of the symbol fragment
13268 differs from the relax_marker of this fragment, we have not
13269 yet adjusted the symbol fragment fr_address. We want to add
13270 in STRETCH in order to get a better estimate of the address.
13271 This particularly matters because of the shift bits. */
13273 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13277 /* Adjust stretch for any alignment frag. Note that if have
13278 been expanding the earlier code, the symbol may be
13279 defined in what appears to be an earlier frag. FIXME:
13280 This doesn't handle the fr_subtype field, which specifies
13281 a maximum number of bytes to skip when doing an
13283 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13285 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13288 stretch
= - ((- stretch
)
13289 & ~ ((1 << (int) f
->fr_offset
) - 1));
13291 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13300 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13302 /* The base address rules are complicated. The base address of
13303 a branch is the following instruction. The base address of a
13304 PC relative load or add is the instruction itself, but if it
13305 is in a delay slot (in which case it can not be extended) use
13306 the address of the instruction whose delay slot it is in. */
13307 if (type
== 'p' || type
== 'q')
13311 /* If we are currently assuming that this frag should be
13312 extended, then, the current address is two bytes
13314 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13317 /* Ignore the low bit in the target, since it will be set
13318 for a text label. */
13319 if ((val
& 1) != 0)
13322 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13324 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13327 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13329 /* Branch offsets have an implicit 0 in the lowest bit. */
13330 if (type
== 'p' || type
== 'q')
13333 /* If any of the shifted bits are set, we must use an extended
13334 opcode. If the address depends on the size of this
13335 instruction, this can lead to a loop, so we arrange to always
13336 use an extended opcode. We only check this when we are in
13337 the main relaxation loop, when SEC is NULL. */
13338 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13340 fragp
->fr_subtype
=
13341 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13345 /* If we are about to mark a frag as extended because the value
13346 is precisely maxtiny + 1, then there is a chance of an
13347 infinite loop as in the following code:
13352 In this case when the la is extended, foo is 0x3fc bytes
13353 away, so the la can be shrunk, but then foo is 0x400 away, so
13354 the la must be extended. To avoid this loop, we mark the
13355 frag as extended if it was small, and is about to become
13356 extended with a value of maxtiny + 1. */
13357 if (val
== ((maxtiny
+ 1) << op
->shift
)
13358 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13361 fragp
->fr_subtype
=
13362 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13366 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13367 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13369 if ((val
& ((1 << op
->shift
) - 1)) != 0
13370 || val
< (mintiny
<< op
->shift
)
13371 || val
> (maxtiny
<< op
->shift
))
13377 /* Compute the length of a branch sequence, and adjust the
13378 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13379 worst-case length is computed, with UPDATE being used to indicate
13380 whether an unconditional (-1), branch-likely (+1) or regular (0)
13381 branch is to be computed. */
13383 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13385 bfd_boolean toofar
;
13389 && S_IS_DEFINED (fragp
->fr_symbol
)
13390 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13395 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13397 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13401 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13404 /* If the symbol is not defined or it's in a different segment,
13405 assume the user knows what's going on and emit a short
13411 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13413 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13414 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13415 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13421 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13424 if (mips_pic
!= NO_PIC
)
13426 /* Additional space for PIC loading of target address. */
13428 if (mips_opts
.isa
== ISA_MIPS1
)
13429 /* Additional space for $at-stabilizing nop. */
13433 /* If branch is conditional. */
13434 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13441 /* Estimate the size of a frag before relaxing. Unless this is the
13442 mips16, we are not really relaxing here, and the final size is
13443 encoded in the subtype information. For the mips16, we have to
13444 decide whether we are using an extended opcode or not. */
13447 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13451 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13454 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13456 return fragp
->fr_var
;
13459 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13460 /* We don't want to modify the EXTENDED bit here; it might get us
13461 into infinite loops. We change it only in mips_relax_frag(). */
13462 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13464 if (mips_pic
== NO_PIC
)
13465 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13466 else if (mips_pic
== SVR4_PIC
)
13467 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13468 else if (mips_pic
== VXWORKS_PIC
)
13469 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13476 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13477 return -RELAX_FIRST (fragp
->fr_subtype
);
13480 return -RELAX_SECOND (fragp
->fr_subtype
);
13483 /* This is called to see whether a reloc against a defined symbol
13484 should be converted into a reloc against a section. */
13487 mips_fix_adjustable (fixS
*fixp
)
13489 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13490 about the format of the offset in the .o file. */
13491 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13494 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13495 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13498 if (fixp
->fx_addsy
== NULL
)
13501 /* If symbol SYM is in a mergeable section, relocations of the form
13502 SYM + 0 can usually be made section-relative. The mergeable data
13503 is then identified by the section offset rather than by the symbol.
13505 However, if we're generating REL LO16 relocations, the offset is split
13506 between the LO16 and parterning high part relocation. The linker will
13507 need to recalculate the complete offset in order to correctly identify
13510 The linker has traditionally not looked for the parterning high part
13511 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13512 placed anywhere. Rather than break backwards compatibility by changing
13513 this, it seems better not to force the issue, and instead keep the
13514 original symbol. This will work with either linker behavior. */
13515 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13516 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13517 || reloc_needs_lo_p (fixp
->fx_r_type
))
13518 && HAVE_IN_PLACE_ADDENDS
13519 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13523 /* Don't adjust relocations against mips16 symbols, so that the linker
13524 can find them if it needs to set up a stub. */
13525 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13526 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13527 && fixp
->fx_subsy
== NULL
)
13534 /* Translate internal representation of relocation info to BFD target
13538 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13540 static arelent
*retval
[4];
13542 bfd_reloc_code_real_type code
;
13544 memset (retval
, 0, sizeof(retval
));
13545 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13546 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13547 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13548 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13550 if (fixp
->fx_pcrel
)
13552 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
13554 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13555 Relocations want only the symbol offset. */
13556 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13557 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13559 /* A gruesome hack which is a result of the gruesome gas
13560 reloc handling. What's worse, for COFF (as opposed to
13561 ECOFF), we might need yet another copy of reloc->address.
13562 See bfd_install_relocation. */
13563 reloc
->addend
+= reloc
->address
;
13567 reloc
->addend
= fixp
->fx_addnumber
;
13569 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13570 entry to be used in the relocation's section offset. */
13571 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13573 reloc
->address
= reloc
->addend
;
13577 code
= fixp
->fx_r_type
;
13579 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13580 if (reloc
->howto
== NULL
)
13582 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13583 _("Can not represent %s relocation in this object file format"),
13584 bfd_get_reloc_code_name (code
));
13591 /* Relax a machine dependent frag. This returns the amount by which
13592 the current size of the frag should change. */
13595 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13597 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13599 offsetT old_var
= fragp
->fr_var
;
13601 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13603 return fragp
->fr_var
- old_var
;
13606 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13609 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13611 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13613 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13618 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13620 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13627 /* Convert a machine dependent frag. */
13630 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13632 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13635 unsigned long insn
;
13639 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13641 if (target_big_endian
)
13642 insn
= bfd_getb32 (buf
);
13644 insn
= bfd_getl32 (buf
);
13646 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13648 /* We generate a fixup instead of applying it right now
13649 because, if there are linker relaxations, we're going to
13650 need the relocations. */
13651 exp
.X_op
= O_symbol
;
13652 exp
.X_add_symbol
= fragp
->fr_symbol
;
13653 exp
.X_add_number
= fragp
->fr_offset
;
13655 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13656 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
13657 fixp
->fx_file
= fragp
->fr_file
;
13658 fixp
->fx_line
= fragp
->fr_line
;
13660 md_number_to_chars ((char *) buf
, insn
, 4);
13667 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13668 _("relaxed out-of-range branch into a jump"));
13670 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13673 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13675 /* Reverse the branch. */
13676 switch ((insn
>> 28) & 0xf)
13679 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13680 have the condition reversed by tweaking a single
13681 bit, and their opcodes all have 0x4???????. */
13682 assert ((insn
& 0xf1000000) == 0x41000000);
13683 insn
^= 0x00010000;
13687 /* bltz 0x04000000 bgez 0x04010000
13688 bltzal 0x04100000 bgezal 0x04110000 */
13689 assert ((insn
& 0xfc0e0000) == 0x04000000);
13690 insn
^= 0x00010000;
13694 /* beq 0x10000000 bne 0x14000000
13695 blez 0x18000000 bgtz 0x1c000000 */
13696 insn
^= 0x04000000;
13704 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13706 /* Clear the and-link bit. */
13707 assert ((insn
& 0xfc1c0000) == 0x04100000);
13709 /* bltzal 0x04100000 bgezal 0x04110000
13710 bltzall 0x04120000 bgezall 0x04130000 */
13711 insn
&= ~0x00100000;
13714 /* Branch over the branch (if the branch was likely) or the
13715 full jump (not likely case). Compute the offset from the
13716 current instruction to branch to. */
13717 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13721 /* How many bytes in instructions we've already emitted? */
13722 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13723 /* How many bytes in instructions from here to the end? */
13724 i
= fragp
->fr_var
- i
;
13726 /* Convert to instruction count. */
13728 /* Branch counts from the next instruction. */
13731 /* Branch over the jump. */
13732 md_number_to_chars ((char *) buf
, insn
, 4);
13736 md_number_to_chars ((char *) buf
, 0, 4);
13739 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13741 /* beql $0, $0, 2f */
13743 /* Compute the PC offset from the current instruction to
13744 the end of the variable frag. */
13745 /* How many bytes in instructions we've already emitted? */
13746 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13747 /* How many bytes in instructions from here to the end? */
13748 i
= fragp
->fr_var
- i
;
13749 /* Convert to instruction count. */
13751 /* Don't decrement i, because we want to branch over the
13755 md_number_to_chars ((char *) buf
, insn
, 4);
13758 md_number_to_chars ((char *) buf
, 0, 4);
13763 if (mips_pic
== NO_PIC
)
13766 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13767 ? 0x0c000000 : 0x08000000);
13768 exp
.X_op
= O_symbol
;
13769 exp
.X_add_symbol
= fragp
->fr_symbol
;
13770 exp
.X_add_number
= fragp
->fr_offset
;
13772 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13773 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
13774 fixp
->fx_file
= fragp
->fr_file
;
13775 fixp
->fx_line
= fragp
->fr_line
;
13777 md_number_to_chars ((char *) buf
, insn
, 4);
13782 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13783 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13784 exp
.X_op
= O_symbol
;
13785 exp
.X_add_symbol
= fragp
->fr_symbol
;
13786 exp
.X_add_number
= fragp
->fr_offset
;
13788 if (fragp
->fr_offset
)
13790 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13791 exp
.X_add_number
= 0;
13794 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13795 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
13796 fixp
->fx_file
= fragp
->fr_file
;
13797 fixp
->fx_line
= fragp
->fr_line
;
13799 md_number_to_chars ((char *) buf
, insn
, 4);
13802 if (mips_opts
.isa
== ISA_MIPS1
)
13805 md_number_to_chars ((char *) buf
, 0, 4);
13809 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13810 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13812 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13813 4, &exp
, FALSE
, BFD_RELOC_LO16
);
13814 fixp
->fx_file
= fragp
->fr_file
;
13815 fixp
->fx_line
= fragp
->fr_line
;
13817 md_number_to_chars ((char *) buf
, insn
, 4);
13821 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13826 md_number_to_chars ((char *) buf
, insn
, 4);
13831 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13832 + fragp
->fr_fix
+ fragp
->fr_var
);
13834 fragp
->fr_fix
+= fragp
->fr_var
;
13839 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13842 const struct mips16_immed_operand
*op
;
13843 bfd_boolean small
, ext
;
13846 unsigned long insn
;
13847 bfd_boolean use_extend
;
13848 unsigned short extend
;
13850 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13851 op
= mips16_immed_operands
;
13852 while (op
->type
!= type
)
13855 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13866 resolve_symbol_value (fragp
->fr_symbol
);
13867 val
= S_GET_VALUE (fragp
->fr_symbol
);
13872 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13874 /* The rules for the base address of a PC relative reloc are
13875 complicated; see mips16_extended_frag. */
13876 if (type
== 'p' || type
== 'q')
13881 /* Ignore the low bit in the target, since it will be
13882 set for a text label. */
13883 if ((val
& 1) != 0)
13886 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13888 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13891 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13894 /* Make sure the section winds up with the alignment we have
13897 record_alignment (asec
, op
->shift
);
13901 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13902 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13903 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13904 _("extended instruction in delay slot"));
13906 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13908 if (target_big_endian
)
13909 insn
= bfd_getb16 (buf
);
13911 insn
= bfd_getl16 (buf
);
13913 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13914 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13915 small
, ext
, &insn
, &use_extend
, &extend
);
13919 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13920 fragp
->fr_fix
+= 2;
13924 md_number_to_chars ((char *) buf
, insn
, 2);
13925 fragp
->fr_fix
+= 2;
13933 first
= RELAX_FIRST (fragp
->fr_subtype
);
13934 second
= RELAX_SECOND (fragp
->fr_subtype
);
13935 fixp
= (fixS
*) fragp
->fr_opcode
;
13937 /* Possibly emit a warning if we've chosen the longer option. */
13938 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13939 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13941 const char *msg
= macro_warning (fragp
->fr_subtype
);
13943 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13946 /* Go through all the fixups for the first sequence. Disable them
13947 (by marking them as done) if we're going to use the second
13948 sequence instead. */
13950 && fixp
->fx_frag
== fragp
13951 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13953 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13955 fixp
= fixp
->fx_next
;
13958 /* Go through the fixups for the second sequence. Disable them if
13959 we're going to use the first sequence, otherwise adjust their
13960 addresses to account for the relaxation. */
13961 while (fixp
&& fixp
->fx_frag
== fragp
)
13963 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13964 fixp
->fx_where
-= first
;
13967 fixp
= fixp
->fx_next
;
13970 /* Now modify the frag contents. */
13971 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13975 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13976 memmove (start
, start
+ first
, second
);
13977 fragp
->fr_fix
-= first
;
13980 fragp
->fr_fix
-= second
;
13986 /* This function is called after the relocs have been generated.
13987 We've been storing mips16 text labels as odd. Here we convert them
13988 back to even for the convenience of the debugger. */
13991 mips_frob_file_after_relocs (void)
13994 unsigned int count
, i
;
13996 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13999 syms
= bfd_get_outsymbols (stdoutput
);
14000 count
= bfd_get_symcount (stdoutput
);
14001 for (i
= 0; i
< count
; i
++, syms
++)
14003 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
14004 && ((*syms
)->value
& 1) != 0)
14006 (*syms
)->value
&= ~1;
14007 /* If the symbol has an odd size, it was probably computed
14008 incorrectly, so adjust that as well. */
14009 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14010 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14017 /* This function is called whenever a label is defined. It is used
14018 when handling branch delays; if a branch has a label, we assume we
14019 can not move it. */
14022 mips_define_label (symbolS
*sym
)
14024 segment_info_type
*si
= seg_info (now_seg
);
14025 struct insn_label_list
*l
;
14027 if (free_insn_labels
== NULL
)
14028 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14031 l
= free_insn_labels
;
14032 free_insn_labels
= l
->next
;
14036 l
->next
= si
->label_list
;
14037 si
->label_list
= l
;
14040 dwarf2_emit_label (sym
);
14044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14046 /* Some special processing for a MIPS ELF file. */
14049 mips_elf_final_processing (void)
14051 /* Write out the register information. */
14052 if (mips_abi
!= N64_ABI
)
14056 s
.ri_gprmask
= mips_gprmask
;
14057 s
.ri_cprmask
[0] = mips_cprmask
[0];
14058 s
.ri_cprmask
[1] = mips_cprmask
[1];
14059 s
.ri_cprmask
[2] = mips_cprmask
[2];
14060 s
.ri_cprmask
[3] = mips_cprmask
[3];
14061 /* The gp_value field is set by the MIPS ELF backend. */
14063 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14064 ((Elf32_External_RegInfo
*)
14065 mips_regmask_frag
));
14069 Elf64_Internal_RegInfo s
;
14071 s
.ri_gprmask
= mips_gprmask
;
14073 s
.ri_cprmask
[0] = mips_cprmask
[0];
14074 s
.ri_cprmask
[1] = mips_cprmask
[1];
14075 s
.ri_cprmask
[2] = mips_cprmask
[2];
14076 s
.ri_cprmask
[3] = mips_cprmask
[3];
14077 /* The gp_value field is set by the MIPS ELF backend. */
14079 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14080 ((Elf64_External_RegInfo
*)
14081 mips_regmask_frag
));
14084 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14085 sort of BFD interface for this. */
14086 if (mips_any_noreorder
)
14087 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14088 if (mips_pic
!= NO_PIC
)
14090 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14091 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14094 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14096 /* Set MIPS ELF flags for ASEs. */
14097 /* We may need to define a new flag for DSP ASE, and set this flag when
14098 file_ase_dsp is true. */
14099 /* We may need to define a new flag for MT ASE, and set this flag when
14100 file_ase_mt is true. */
14101 if (file_ase_mips16
)
14102 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14103 #if 0 /* XXX FIXME */
14104 if (file_ase_mips3d
)
14105 elf_elfheader (stdoutput
)->e_flags
|= ???;
14108 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14110 /* Set the MIPS ELF ABI flags. */
14111 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14112 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14113 else if (mips_abi
== O64_ABI
)
14114 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14115 else if (mips_abi
== EABI_ABI
)
14117 if (!file_mips_gp32
)
14118 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14120 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14122 else if (mips_abi
== N32_ABI
)
14123 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14125 /* Nothing to do for N64_ABI. */
14127 if (mips_32bitmode
)
14128 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14130 #if 0 /* XXX FIXME */
14131 /* 32 bit code with 64 bit FP registers. */
14132 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14133 elf_elfheader (stdoutput
)->e_flags
|= ???;
14137 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14139 typedef struct proc
{
14141 symbolS
*func_end_sym
;
14142 unsigned long reg_mask
;
14143 unsigned long reg_offset
;
14144 unsigned long fpreg_mask
;
14145 unsigned long fpreg_offset
;
14146 unsigned long frame_offset
;
14147 unsigned long frame_reg
;
14148 unsigned long pc_reg
;
14151 static procS cur_proc
;
14152 static procS
*cur_proc_ptr
;
14153 static int numprocs
;
14155 /* Fill in an rs_align_code fragment. */
14158 mips_handle_align (fragS
*fragp
)
14160 if (fragp
->fr_type
!= rs_align_code
)
14163 if (mips_opts
.mips16
)
14165 static const unsigned char be_nop
[] = { 0x65, 0x00 };
14166 static const unsigned char le_nop
[] = { 0x00, 0x65 };
14171 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14172 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14180 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
14184 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14188 md_obj_begin (void)
14195 /* check for premature end, nesting errors, etc */
14197 as_warn (_("missing .end at end of assembly"));
14206 if (*input_line_pointer
== '-')
14208 ++input_line_pointer
;
14211 if (!ISDIGIT (*input_line_pointer
))
14212 as_bad (_("expected simple number"));
14213 if (input_line_pointer
[0] == '0')
14215 if (input_line_pointer
[1] == 'x')
14217 input_line_pointer
+= 2;
14218 while (ISXDIGIT (*input_line_pointer
))
14221 val
|= hex_value (*input_line_pointer
++);
14223 return negative
? -val
: val
;
14227 ++input_line_pointer
;
14228 while (ISDIGIT (*input_line_pointer
))
14231 val
|= *input_line_pointer
++ - '0';
14233 return negative
? -val
: val
;
14236 if (!ISDIGIT (*input_line_pointer
))
14238 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14239 *input_line_pointer
, *input_line_pointer
);
14240 as_warn (_("invalid number"));
14243 while (ISDIGIT (*input_line_pointer
))
14246 val
+= *input_line_pointer
++ - '0';
14248 return negative
? -val
: val
;
14251 /* The .file directive; just like the usual .file directive, but there
14252 is an initial number which is the ECOFF file index. In the non-ECOFF
14253 case .file implies DWARF-2. */
14256 s_mips_file (int x ATTRIBUTE_UNUSED
)
14258 static int first_file_directive
= 0;
14260 if (ECOFF_DEBUGGING
)
14269 filename
= dwarf2_directive_file (0);
14271 /* Versions of GCC up to 3.1 start files with a ".file"
14272 directive even for stabs output. Make sure that this
14273 ".file" is handled. Note that you need a version of GCC
14274 after 3.1 in order to support DWARF-2 on MIPS. */
14275 if (filename
!= NULL
&& ! first_file_directive
)
14277 (void) new_logical_line (filename
, -1);
14278 s_app_file_string (filename
, 0);
14280 first_file_directive
= 1;
14284 /* The .loc directive, implying DWARF-2. */
14287 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14289 if (!ECOFF_DEBUGGING
)
14290 dwarf2_directive_loc (0);
14293 /* The .end directive. */
14296 s_mips_end (int x ATTRIBUTE_UNUSED
)
14300 /* Following functions need their own .frame and .cprestore directives. */
14301 mips_frame_reg_valid
= 0;
14302 mips_cprestore_valid
= 0;
14304 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14307 demand_empty_rest_of_line ();
14312 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14313 as_warn (_(".end not in text section"));
14317 as_warn (_(".end directive without a preceding .ent directive."));
14318 demand_empty_rest_of_line ();
14324 assert (S_GET_NAME (p
));
14325 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14326 as_warn (_(".end symbol does not match .ent symbol."));
14328 if (debug_type
== DEBUG_STABS
)
14329 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14333 as_warn (_(".end directive missing or unknown symbol"));
14336 /* Create an expression to calculate the size of the function. */
14337 if (p
&& cur_proc_ptr
)
14339 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14340 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14343 exp
->X_op
= O_subtract
;
14344 exp
->X_add_symbol
= symbol_temp_new_now ();
14345 exp
->X_op_symbol
= p
;
14346 exp
->X_add_number
= 0;
14348 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14351 /* Generate a .pdr section. */
14352 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
14355 segT saved_seg
= now_seg
;
14356 subsegT saved_subseg
= now_subseg
;
14361 dot
= frag_now_fix ();
14363 #ifdef md_flush_pending_output
14364 md_flush_pending_output ();
14368 subseg_set (pdr_seg
, 0);
14370 /* Write the symbol. */
14371 exp
.X_op
= O_symbol
;
14372 exp
.X_add_symbol
= p
;
14373 exp
.X_add_number
= 0;
14374 emit_expr (&exp
, 4);
14376 fragp
= frag_more (7 * 4);
14378 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14379 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14380 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14381 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14382 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14383 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14384 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14386 subseg_set (saved_seg
, saved_subseg
);
14388 #endif /* OBJ_ELF */
14390 cur_proc_ptr
= NULL
;
14393 /* The .aent and .ent directives. */
14396 s_mips_ent (int aent
)
14400 symbolP
= get_symbol ();
14401 if (*input_line_pointer
== ',')
14402 ++input_line_pointer
;
14403 SKIP_WHITESPACE ();
14404 if (ISDIGIT (*input_line_pointer
)
14405 || *input_line_pointer
== '-')
14408 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14409 as_warn (_(".ent or .aent not in text section."));
14411 if (!aent
&& cur_proc_ptr
)
14412 as_warn (_("missing .end"));
14416 /* This function needs its own .frame and .cprestore directives. */
14417 mips_frame_reg_valid
= 0;
14418 mips_cprestore_valid
= 0;
14420 cur_proc_ptr
= &cur_proc
;
14421 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14423 cur_proc_ptr
->func_sym
= symbolP
;
14425 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14429 if (debug_type
== DEBUG_STABS
)
14430 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14431 S_GET_NAME (symbolP
));
14434 demand_empty_rest_of_line ();
14437 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14438 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14439 s_mips_frame is used so that we can set the PDR information correctly.
14440 We can't use the ecoff routines because they make reference to the ecoff
14441 symbol table (in the mdebug section). */
14444 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14447 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14451 if (cur_proc_ptr
== (procS
*) NULL
)
14453 as_warn (_(".frame outside of .ent"));
14454 demand_empty_rest_of_line ();
14458 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14460 SKIP_WHITESPACE ();
14461 if (*input_line_pointer
++ != ','
14462 || get_absolute_expression_and_terminator (&val
) != ',')
14464 as_warn (_("Bad .frame directive"));
14465 --input_line_pointer
;
14466 demand_empty_rest_of_line ();
14470 cur_proc_ptr
->frame_offset
= val
;
14471 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14473 demand_empty_rest_of_line ();
14476 #endif /* OBJ_ELF */
14480 /* The .fmask and .mask directives. If the mdebug section is present
14481 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14482 embedded targets, s_mips_mask is used so that we can set the PDR
14483 information correctly. We can't use the ecoff routines because they
14484 make reference to the ecoff symbol table (in the mdebug section). */
14487 s_mips_mask (int reg_type
)
14490 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14494 if (cur_proc_ptr
== (procS
*) NULL
)
14496 as_warn (_(".mask/.fmask outside of .ent"));
14497 demand_empty_rest_of_line ();
14501 if (get_absolute_expression_and_terminator (&mask
) != ',')
14503 as_warn (_("Bad .mask/.fmask directive"));
14504 --input_line_pointer
;
14505 demand_empty_rest_of_line ();
14509 off
= get_absolute_expression ();
14511 if (reg_type
== 'F')
14513 cur_proc_ptr
->fpreg_mask
= mask
;
14514 cur_proc_ptr
->fpreg_offset
= off
;
14518 cur_proc_ptr
->reg_mask
= mask
;
14519 cur_proc_ptr
->reg_offset
= off
;
14522 demand_empty_rest_of_line ();
14525 #endif /* OBJ_ELF */
14526 s_ignore (reg_type
);
14529 /* A table describing all the processors gas knows about. Names are
14530 matched in the order listed.
14532 To ease comparison, please keep this table in the same order as
14533 gcc's mips_cpu_info_table[]. */
14534 static const struct mips_cpu_info mips_cpu_info_table
[] =
14536 /* Entries for generic ISAs */
14537 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
14538 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
14539 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
14540 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
14541 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
14542 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
14543 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14544 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
14545 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
14548 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14549 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14550 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14553 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14556 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14557 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14558 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14559 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14560 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14561 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14562 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14563 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14564 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14565 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14566 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14567 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14570 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14571 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14572 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14573 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14574 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14575 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14576 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14577 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14578 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14579 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14580 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14581 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14582 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14585 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14586 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14587 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14588 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
14590 /* MIPS 32 Release 2 */
14591 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14592 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14593 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14594 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14595 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14596 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14597 { "24k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14598 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14599 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14600 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14601 /* 24ke is a 24k with DSP ASE, other ASEs are optional. */
14602 { "24ke", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14603 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14604 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14605 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14606 /* 34k is a 24k with MT ASE, other ASEs are optional. */
14607 { "34kc", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14608 { "34kf", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14609 { "34kx", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14612 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14613 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14614 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
14616 /* MIPS 64 Release 2 */
14617 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64R2
, CPU_MIPS64R2
},
14619 /* Broadcom SB-1 CPU core */
14620 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
14621 ISA_MIPS64
, CPU_SB1
},
14628 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14629 with a final "000" replaced by "k". Ignore case.
14631 Note: this function is shared between GCC and GAS. */
14634 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14636 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14637 given
++, canonical
++;
14639 return ((*given
== 0 && *canonical
== 0)
14640 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14644 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14645 CPU name. We've traditionally allowed a lot of variation here.
14647 Note: this function is shared between GCC and GAS. */
14650 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14652 /* First see if the name matches exactly, or with a final "000"
14653 turned into "k". */
14654 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14657 /* If not, try comparing based on numerical designation alone.
14658 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14659 if (TOLOWER (*given
) == 'r')
14661 if (!ISDIGIT (*given
))
14664 /* Skip over some well-known prefixes in the canonical name,
14665 hoping to find a number there too. */
14666 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14668 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14670 else if (TOLOWER (canonical
[0]) == 'r')
14673 return mips_strict_matching_cpu_name_p (canonical
, given
);
14677 /* Parse an option that takes the name of a processor as its argument.
14678 OPTION is the name of the option and CPU_STRING is the argument.
14679 Return the corresponding processor enumeration if the CPU_STRING is
14680 recognized, otherwise report an error and return null.
14682 A similar function exists in GCC. */
14684 static const struct mips_cpu_info
*
14685 mips_parse_cpu (const char *option
, const char *cpu_string
)
14687 const struct mips_cpu_info
*p
;
14689 /* 'from-abi' selects the most compatible architecture for the given
14690 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14691 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14692 version. Look first at the -mgp options, if given, otherwise base
14693 the choice on MIPS_DEFAULT_64BIT.
14695 Treat NO_ABI like the EABIs. One reason to do this is that the
14696 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14697 architecture. This code picks MIPS I for 'mips' and MIPS III for
14698 'mips64', just as we did in the days before 'from-abi'. */
14699 if (strcasecmp (cpu_string
, "from-abi") == 0)
14701 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14702 return mips_cpu_info_from_isa (ISA_MIPS1
);
14704 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14705 return mips_cpu_info_from_isa (ISA_MIPS3
);
14707 if (file_mips_gp32
>= 0)
14708 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14710 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14715 /* 'default' has traditionally been a no-op. Probably not very useful. */
14716 if (strcasecmp (cpu_string
, "default") == 0)
14719 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14720 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14723 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14727 /* Return the canonical processor information for ISA (a member of the
14728 ISA_MIPS* enumeration). */
14730 static const struct mips_cpu_info
*
14731 mips_cpu_info_from_isa (int isa
)
14735 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14736 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
14737 && isa
== mips_cpu_info_table
[i
].isa
)
14738 return (&mips_cpu_info_table
[i
]);
14743 static const struct mips_cpu_info
*
14744 mips_cpu_info_from_arch (int arch
)
14748 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14749 if (arch
== mips_cpu_info_table
[i
].cpu
)
14750 return (&mips_cpu_info_table
[i
]);
14756 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14760 fprintf (stream
, "%24s", "");
14765 fprintf (stream
, ", ");
14769 if (*col_p
+ strlen (string
) > 72)
14771 fprintf (stream
, "\n%24s", "");
14775 fprintf (stream
, "%s", string
);
14776 *col_p
+= strlen (string
);
14782 md_show_usage (FILE *stream
)
14787 fprintf (stream
, _("\
14789 -EB generate big endian output\n\
14790 -EL generate little endian output\n\
14791 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14792 -G NUM allow referencing objects up to NUM bytes\n\
14793 implicitly with the gp register [default 8]\n"));
14794 fprintf (stream
, _("\
14795 -mips1 generate MIPS ISA I instructions\n\
14796 -mips2 generate MIPS ISA II instructions\n\
14797 -mips3 generate MIPS ISA III instructions\n\
14798 -mips4 generate MIPS ISA IV instructions\n\
14799 -mips5 generate MIPS ISA V instructions\n\
14800 -mips32 generate MIPS32 ISA instructions\n\
14801 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14802 -mips64 generate MIPS64 ISA instructions\n\
14803 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14804 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14808 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14809 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14810 show (stream
, "from-abi", &column
, &first
);
14811 fputc ('\n', stream
);
14813 fprintf (stream
, _("\
14814 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14815 -no-mCPU don't generate code specific to CPU.\n\
14816 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14820 show (stream
, "3900", &column
, &first
);
14821 show (stream
, "4010", &column
, &first
);
14822 show (stream
, "4100", &column
, &first
);
14823 show (stream
, "4650", &column
, &first
);
14824 fputc ('\n', stream
);
14826 fprintf (stream
, _("\
14827 -mips16 generate mips16 instructions\n\
14828 -no-mips16 do not generate mips16 instructions\n"));
14829 fprintf (stream
, _("\
14830 -msmartmips generate smartmips instructions\n\
14831 -mno-smartmips do not generate smartmips instructions\n"));
14832 fprintf (stream
, _("\
14833 -mdsp generate DSP instructions\n\
14834 -mno-dsp do not generate DSP instructions\n"));
14835 fprintf (stream
, _("\
14836 -mmt generate MT instructions\n\
14837 -mno-mt do not generate MT instructions\n"));
14838 fprintf (stream
, _("\
14839 -mfix-vr4120 work around certain VR4120 errata\n\
14840 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14841 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14842 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14843 -mno-shared optimize output for executables\n\
14844 -msym32 assume all symbols have 32-bit values\n\
14845 -O0 remove unneeded NOPs, do not swap branches\n\
14846 -O remove unneeded NOPs and swap branches\n\
14847 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14848 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14849 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14851 fprintf (stream
, _("\
14852 -KPIC, -call_shared generate SVR4 position independent code\n\
14853 -non_shared do not generate position independent code\n\
14854 -xgot assume a 32 bit GOT\n\
14855 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14856 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14858 -mabi=ABI create ABI conformant object file for:\n"));
14862 show (stream
, "32", &column
, &first
);
14863 show (stream
, "o64", &column
, &first
);
14864 show (stream
, "n32", &column
, &first
);
14865 show (stream
, "64", &column
, &first
);
14866 show (stream
, "eabi", &column
, &first
);
14868 fputc ('\n', stream
);
14870 fprintf (stream
, _("\
14871 -32 create o32 ABI object file (default)\n\
14872 -n32 create n32 ABI object file\n\
14873 -64 create 64 ABI object file\n"));
14878 mips_dwarf2_format (void)
14880 if (mips_abi
== N64_ABI
)
14883 return dwarf2_format_64bit_irix
;
14885 return dwarf2_format_64bit
;
14889 return dwarf2_format_32bit
;
14893 mips_dwarf2_addr_size (void)
14895 if (mips_abi
== N64_ABI
)
14901 /* Standard calling conventions leave the CFA at SP on entry. */
14903 mips_cfi_frame_initial_instructions (void)
14905 cfi_add_CFA_def_cfa_register (SP
);
14909 tc_mips_regname_to_dw2regnum (char *regname
)
14911 unsigned int regnum
= -1;
14914 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))