1 @ VFP Instructions for v1xD variants
(Single precision only
)
2 @ Same as vfp1xD.s
, but for Thumb-
2
8 @ First we test the basic syntax
and bit patterns of the opcodes.
9 @ Most of these tests deliberatly use s0
/r0 to avoid setting
10 @ any more bits than necessary.
12 @ Comparison operations
21 @ Monadic data operations
28 @ Dyadic data operations
40 @ Load
/store operations
45 @ Load
/store multiple operations
75 @ Conversion operations
85 @ ARM from VFP operations
92 @ VFP From ARM operations
99 @ Now we test that the register fields are updated correctly for
100 @ each class of instruction.
102 @ Single register operations
(compare-zero
):
108 @ Two register comparison operations
:
118 @ Two register data operations
(monadic
)
128 @ Three register data operations
(dyadic
)
141 @ Conversion operations
157 @ Move to VFP from ARM
170 @ Move to ARM from VFP
183 @ Load
/store operations
189 flds s0
, [r0, #-1020]
193 fsts s21
, [r12, #804]
195 @ Load
/store multiple operations
205 fldmias
r0, {s30-s31
}
217 fstmiax
r0, {d14-d15
}
221 @ Check that we assemble all the register names correctly
256 @ Now we check the placement of the conditional execution substring.
257 @ On VFP this is always at the end of the instruction.
258 @ We use different register numbers here to check for correct
261 @ Comparison operations
272 @ Monadic data operations
280 @ Dyadic data operations
284 fmacseq s31
, s30
, s29
286 fmscseq s28
, s27
, s26
287 fmulseq s25
, s24
, s23
288 fnmacseq s22
, s21
, s20
289 fnmscseq s19
, s18
, s17
291 fnmulseq s16
, s15
, s14
292 fsubseq s13
, s12
, s11
294 @ Load
/store operations
299 @ Load
/store multiple operations
333 fstmfdxeq
r10!, {d12
}
335 @ Conversion operations
346 @ ARM from VFP operations
351 @ VFP From ARM operations
357 @
2 nops to pad to
16-byte boundary