opcodes/openrisc-desc.h

   1 /* CPU data header for openrisc.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2010 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef OPENRISC_CPU_H
  26 #define OPENRISC_CPU_H
  27
  28 #define CGEN_ARCH openrisc
  29
  30 /* Given symbol S, return openrisc_cgen_<S>.  */
  31 #define CGEN_SYM(s) openrisc##_cgen_##s
  32
  33
  34 /* Selected cpu families.  */
  35 #define HAVE_CPU_OPENRISCBF
  36
  37 #define CGEN_INSN_LSB0_P 1
  38
  39 /* Minimum size of any insn (in bytes).  */
  40 #define CGEN_MIN_INSN_SIZE 4
  41
  42 /* Maximum size of any insn (in bytes).  */
  43 #define CGEN_MAX_INSN_SIZE 4
  44
  45 #define CGEN_INT_INSN_P 1
  46
  47 /* Maximum number of syntax elements in an instruction.  */
  48 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 14
  49
  50 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
  51    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
  52    we can't hash on everything up to the space.  */
  53 #define CGEN_MNEMONIC_OPERANDS
  54
  55 /* Maximum number of fields in an instruction.  */
  56 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
  57
  58 /* Enums.  */
  59
  60 /* Enum declaration for exception vectors.  */
  61 typedef enum e_exception {
  62   E_RESET, E_BUSERR, E_DPF, E_IPF
  63  , E_EXTINT, E_ALIGN, E_ILLEGAL, E_PEINT
  64  , E_DTLBMISS, E_ITLBMISS, E_RRANGE, E_SYSCALL
  65  , E_BREAK, E_RESERVED
  66 } E_EXCEPTION;
  67
  68 /* Enum declaration for FIXME.  */
  69 typedef enum insn_class {
  70   OP1_0, OP1_1, OP1_2, OP1_3
  71 } INSN_CLASS;
  72
  73 /* Enum declaration for FIXME.  */
  74 typedef enum insn_sub {
  75   OP2_0, OP2_1, OP2_2, OP2_3
  76  , OP2_4, OP2_5, OP2_6, OP2_7
  77  , OP2_8, OP2_9, OP2_10, OP2_11
  78  , OP2_12, OP2_13, OP2_14, OP2_15
  79 } INSN_SUB;
  80
  81 /* Enum declaration for FIXME.  */
  82 typedef enum insn_op3 {
  83   OP3_0, OP3_1, OP3_2, OP3_3
  84 } INSN_OP3;
  85
  86 /* Enum declaration for FIXME.  */
  87 typedef enum insn_op4 {
  88   OP4_0, OP4_1, OP4_2, OP4_3
  89  , OP4_4, OP4_5, OP4_6, OP4_7
  90 } INSN_OP4;
  91
  92 /* Enum declaration for FIXME.  */
  93 typedef enum insn_op5 {
  94   OP5_0, OP5_1, OP5_2, OP5_3
  95  , OP5_4, OP5_5, OP5_6, OP5_7
  96  , OP5_8, OP5_9, OP5_10, OP5_11
  97  , OP5_12, OP5_13, OP5_14, OP5_15
  98  , OP5_16, OP5_17, OP5_18, OP5_19
  99  , OP5_20, OP5_21, OP5_22, OP5_23
 100  , OP5_24, OP5_25, OP5_26, OP5_27
 101  , OP5_28, OP5_29, OP5_30, OP5_31
 102 } INSN_OP5;
 103
 104 /* Enum declaration for FIXME.  */
 105 typedef enum insn_op6 {
 106   OP6_0, OP6_1, OP6_2, OP6_3
 107  , OP6_4, OP6_5, OP6_6, OP6_7
 108 } INSN_OP6;
 109
 110 /* Enum declaration for FIXME.  */
 111 typedef enum insn_op7 {
 112   OP7_0, OP7_1, OP7_2, OP7_3
 113  , OP7_4, OP7_5, OP7_6, OP7_7
 114  , OP7_8, OP7_9, OP7_10, OP7_11
 115  , OP7_12, OP7_13, OP7_14, OP7_15
 116 } INSN_OP7;
 117
 118 /* Attributes.  */
 119
 120 /* Enum declaration for machine type selection.  */
 121 typedef enum mach_attr {
 122   MACH_BASE, MACH_OPENRISC, MACH_OR1300, MACH_MAX
 123 } MACH_ATTR;
 124
 125 /* Enum declaration for instruction set selection.  */
 126 typedef enum isa_attr {
 127   ISA_OR32, ISA_MAX
 128 } ISA_ATTR;
 129
 130 /* Enum declaration for if this model has caches.  */
 131 typedef enum has_cache_attr {
 132   HAS_CACHE_DATA_CACHE, HAS_CACHE_INSN_CACHE
 133 } HAS_CACHE_ATTR;
 134
 135 /* Number of architecture variants.  */
 136 #define MAX_ISAS  1
 137 #define MAX_MACHS ((int) MACH_MAX)
 138
 139 /* Ifield support.  */
 140
 141 /* Ifield attribute indices.  */
 142
 143 /* Enum declaration for cgen_ifld attrs.  */
 144 typedef enum cgen_ifld_attr {
 145   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 146  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 147  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
 148 } CGEN_IFLD_ATTR;
 149
 150 /* Number of non-boolean elements in cgen_ifld_attr.  */
 151 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
 152
 153 /* cgen_ifld attribute accessor macros.  */
 154 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
 155 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
 156 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
 157 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
 158 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
 159 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
 160 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
 161
 162 /* Enum declaration for openrisc ifield types.  */
 163 typedef enum ifield_type {
 164   OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB
 165  , OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3, OPENRISC_F_SIMM16
 166  , OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16, OPENRISC_F_LO16
 167  , OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3, OPENRISC_F_OP4
 168  , OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7, OPENRISC_F_I16_1
 169  , OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26, OPENRISC_F_I16NC
 170  , OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1, OPENRISC_F_F_7_3
 171  , OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX
 172 } IFIELD_TYPE;
 173
 174 #define MAX_IFLD ((int) OPENRISC_F_MAX)
 175
 176 /* Hardware attribute indices.  */
 177
 178 /* Enum declaration for cgen_hw attrs.  */
 179 typedef enum cgen_hw_attr {
 180   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 181  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
 182 } CGEN_HW_ATTR;
 183
 184 /* Number of non-boolean elements in cgen_hw_attr.  */
 185 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
 186
 187 /* cgen_hw attribute accessor macros.  */
 188 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
 189 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
 190 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
 191 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
 192 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
 193
 194 /* Enum declaration for openrisc hardware types.  */
 195 typedef enum cgen_hw_type {
 196   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 197  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_SR
 198  , HW_H_HI16, HW_H_LO16, HW_H_CBIT, HW_H_DELAY_INSN
 199  , HW_MAX
 200 } CGEN_HW_TYPE;
 201
 202 #define MAX_HW ((int) HW_MAX)
 203
 204 /* Operand attribute indices.  */
 205
 206 /* Enum declaration for cgen_operand attrs.  */
 207 typedef enum cgen_operand_attr {
 208   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 209  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 210  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
 211 } CGEN_OPERAND_ATTR;
 212
 213 /* Number of non-boolean elements in cgen_operand_attr.  */
 214 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
 215
 216 /* cgen_operand attribute accessor macros.  */
 217 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
 218 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
 219 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
 220 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
 221 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
 222 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
 223 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
 224 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
 225 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
 226
 227 /* Enum declaration for openrisc operand types.  */
 228 typedef enum cgen_operand_type {
 229   OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16
 230  , OPENRISC_OPERAND_UIMM_16, OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5
 231  , OPENRISC_OPERAND_RD, OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23
 232  , OPENRISC_OPERAND_OP_F_3, OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC
 233  , OPENRISC_OPERAND_MAX
 234 } CGEN_OPERAND_TYPE;
 235
 236 /* Number of operands types.  */
 237 #define MAX_OPERANDS 16
 238
 239 /* Maximum number of operands referenced by any insn.  */
 240 #define MAX_OPERAND_INSTANCES 8
 241
 242 /* Insn attribute indices.  */
 243
 244 /* Enum declaration for cgen_insn attrs.  */
 245 typedef enum cgen_insn_attr {
 246   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 247  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
 248  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
 249  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
 250 } CGEN_INSN_ATTR;
 251
 252 /* Number of non-boolean elements in cgen_insn_attr.  */
 253 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
 254
 255 /* cgen_insn attribute accessor macros.  */
 256 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
 257 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
 258 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
 259 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
 260 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
 261 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
 262 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
 263 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
 264 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
 265 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
 266 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
 267 #define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0)
 268
 269 /* cgen.h uses things we just defined.  */
 270 #include "opcode/cgen.h"
 271
 272 extern const struct cgen_ifld openrisc_cgen_ifld_table[];
 273
 274 /* Attributes.  */
 275 extern const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[];
 276 extern const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[];
 277 extern const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[];
 278 extern const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[];
 279
 280 /* Hardware decls.  */
 281
 282 extern CGEN_KEYWORD openrisc_cgen_opval_h_gr;
 283
 284 extern const CGEN_HW_ENTRY openrisc_cgen_hw_table[];
 285
 286
 287
 288 #endif /* OPENRISC_CPU_H */