1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
10 This file is part of GAS.
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
32 #include "opcode/mips.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 #define AT mips_opts.at
107 /* Allow override of standard little-endian ECOFF format. */
109 #ifndef ECOFF_LITTLE_FORMAT
110 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
113 extern int target_big_endian
;
115 /* The name of the readonly data section. */
116 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* Information about an instruction, including its format, operands
128 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
129 const struct mips_opcode
*insn_mo
;
131 /* True if this is a mips16 instruction and if we want the extended
133 bfd_boolean use_extend
;
135 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
136 unsigned short extend
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. */
140 unsigned long insn_opcode
;
142 /* The frag that contains the instruction. */
145 /* The offset into FRAG of the first instruction byte. */
148 /* The relocs associated with the instruction, if any. */
151 /* True if this entry cannot be moved from its current position. */
152 unsigned int fixed_p
: 1;
154 /* True if this instruction occurred in a .set noreorder block. */
155 unsigned int noreorder_p
: 1;
157 /* True for mips16 instructions that jump to an absolute address. */
158 unsigned int mips16_absolute_jump_p
: 1;
161 /* The ABI to use. */
172 /* MIPS ABI we are using for this output file. */
173 static enum mips_abi_level mips_abi
= NO_ABI
;
175 /* Whether or not we have code that can call pic code. */
176 int mips_abicalls
= FALSE
;
178 /* Whether or not we have code which can be put into a shared
180 static bfd_boolean mips_in_shared
= TRUE
;
182 /* This is the set of options which may be modified by the .set
183 pseudo-op. We use a struct so that .set push and .set pop are more
186 struct mips_set_options
188 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
189 if it has not been initialized. Changed by `.set mipsN', and the
190 -mipsN command line option, and the default CPU. */
192 /* Enabled Application Specific Extensions (ASEs). These are set to -1
193 if they have not been initialized. Changed by `.set <asename>', by
194 command line options, and based on the default architecture. */
201 /* Whether we are assembling for the mips16 processor. 0 if we are
202 not, 1 if we are, and -1 if the value has not been initialized.
203 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
204 -nomips16 command line options, and the default CPU. */
206 /* Non-zero if we should not reorder instructions. Changed by `.set
207 reorder' and `.set noreorder'. */
209 /* Non-zero if we should not permit the register designated "assembler
210 temporary" to be used in instructions. The value is the register
211 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
212 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
214 /* Non-zero if we should warn when a macro instruction expands into
215 more than one machine instruction. Changed by `.set nomacro' and
217 int warn_about_macros
;
218 /* Non-zero if we should not move instructions. Changed by `.set
219 move', `.set volatile', `.set nomove', and `.set novolatile'. */
221 /* Non-zero if we should not optimize branches by moving the target
222 of the branch into the delay slot. Actually, we don't perform
223 this optimization anyhow. Changed by `.set bopt' and `.set
226 /* Non-zero if we should not autoextend mips16 instructions.
227 Changed by `.set autoextend' and `.set noautoextend'. */
229 /* Restrict general purpose registers and floating point registers
230 to 32 bit. This is initially determined when -mgp32 or -mfp32
231 is passed but can changed if the assembler code uses .set mipsN. */
234 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
235 command line option, and the default CPU. */
237 /* True if ".set sym32" is in effect. */
239 /* True if floating-point operations are not allowed. Changed by .set
240 softfloat or .set hardfloat, by command line options -msoft-float or
241 -mhard-float. The default is false. */
242 bfd_boolean soft_float
;
244 /* True if only single-precision floating-point operations are allowed.
245 Changed by .set singlefloat or .set doublefloat, command-line options
246 -msingle-float or -mdouble-float. The default is false. */
247 bfd_boolean single_float
;
250 /* This is the struct we use to hold the current set of options. Note
251 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
252 -1 to indicate that they have not been initialized. */
254 /* True if -mgp32 was passed. */
255 static int file_mips_gp32
= -1;
257 /* True if -mfp32 was passed. */
258 static int file_mips_fp32
= -1;
260 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
261 static int file_mips_soft_float
= 0;
263 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
264 static int file_mips_single_float
= 0;
266 static struct mips_set_options mips_opts
=
268 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
269 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
270 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
271 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
272 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
273 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
276 /* These variables are filled in with the masks of registers used.
277 The object format code reads them and puts them in the appropriate
279 unsigned long mips_gprmask
;
280 unsigned long mips_cprmask
[4];
282 /* MIPS ISA we are using for this output file. */
283 static int file_mips_isa
= ISA_UNKNOWN
;
285 /* True if -mips16 was passed or implied by arguments passed on the
286 command line (e.g., by -march). */
287 static int file_ase_mips16
;
289 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
290 || mips_opts.isa == ISA_MIPS32R2 \
291 || mips_opts.isa == ISA_MIPS64 \
292 || mips_opts.isa == ISA_MIPS64R2)
294 /* True if we want to create R_MIPS_JALR for jalr $25. */
296 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
298 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
299 because there's no place for any addend, the only acceptable
300 expression is a bare symbol. */
301 #define MIPS_JALR_HINT_P(EXPR) \
302 (!HAVE_IN_PLACE_ADDENDS \
303 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
306 /* True if -mips3d was passed or implied by arguments passed on the
307 command line (e.g., by -march). */
308 static int file_ase_mips3d
;
310 /* True if -mdmx was passed or implied by arguments passed on the
311 command line (e.g., by -march). */
312 static int file_ase_mdmx
;
314 /* True if -msmartmips was passed or implied by arguments passed on the
315 command line (e.g., by -march). */
316 static int file_ase_smartmips
;
318 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
319 || mips_opts.isa == ISA_MIPS32R2)
321 /* True if -mdsp was passed or implied by arguments passed on the
322 command line (e.g., by -march). */
323 static int file_ase_dsp
;
325 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
326 || mips_opts.isa == ISA_MIPS64R2)
328 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
330 /* True if -mdspr2 was passed or implied by arguments passed on the
331 command line (e.g., by -march). */
332 static int file_ase_dspr2
;
334 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
335 || mips_opts.isa == ISA_MIPS64R2)
337 /* True if -mmt was passed or implied by arguments passed on the
338 command line (e.g., by -march). */
339 static int file_ase_mt
;
341 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
342 || mips_opts.isa == ISA_MIPS64R2)
344 /* The argument of the -march= flag. The architecture we are assembling. */
345 static int file_mips_arch
= CPU_UNKNOWN
;
346 static const char *mips_arch_string
;
348 /* The argument of the -mtune= flag. The architecture for which we
350 static int mips_tune
= CPU_UNKNOWN
;
351 static const char *mips_tune_string
;
353 /* True when generating 32-bit code for a 64-bit processor. */
354 static int mips_32bitmode
= 0;
356 /* True if the given ABI requires 32-bit registers. */
357 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
359 /* Likewise 64-bit registers. */
360 #define ABI_NEEDS_64BIT_REGS(ABI) \
362 || (ABI) == N64_ABI \
365 /* Return true if ISA supports 64 bit wide gp registers. */
366 #define ISA_HAS_64BIT_REGS(ISA) \
367 ((ISA) == ISA_MIPS3 \
368 || (ISA) == ISA_MIPS4 \
369 || (ISA) == ISA_MIPS5 \
370 || (ISA) == ISA_MIPS64 \
371 || (ISA) == ISA_MIPS64R2)
373 /* Return true if ISA supports 64 bit wide float registers. */
374 #define ISA_HAS_64BIT_FPRS(ISA) \
375 ((ISA) == ISA_MIPS3 \
376 || (ISA) == ISA_MIPS4 \
377 || (ISA) == ISA_MIPS5 \
378 || (ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2)
382 /* Return true if ISA supports 64-bit right rotate (dror et al.)
384 #define ISA_HAS_DROR(ISA) \
385 ((ISA) == ISA_MIPS64R2)
387 /* Return true if ISA supports 32-bit right rotate (ror et al.)
389 #define ISA_HAS_ROR(ISA) \
390 ((ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS64R2 \
392 || mips_opts.ase_smartmips)
394 /* Return true if ISA supports single-precision floats in odd registers. */
395 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
396 ((ISA) == ISA_MIPS32 \
397 || (ISA) == ISA_MIPS32R2 \
398 || (ISA) == ISA_MIPS64 \
399 || (ISA) == ISA_MIPS64R2)
401 /* Return true if ISA supports move to/from high part of a 64-bit
402 floating-point register. */
403 #define ISA_HAS_MXHC1(ISA) \
404 ((ISA) == ISA_MIPS32R2 \
405 || (ISA) == ISA_MIPS64R2)
407 #define HAVE_32BIT_GPRS \
408 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
410 #define HAVE_32BIT_FPRS \
411 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
413 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
414 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
416 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
418 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
420 /* True if relocations are stored in-place. */
421 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
423 /* The ABI-derived address size. */
424 #define HAVE_64BIT_ADDRESSES \
425 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
426 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
428 /* The size of symbolic constants (i.e., expressions of the form
429 "SYMBOL" or "SYMBOL + OFFSET"). */
430 #define HAVE_32BIT_SYMBOLS \
431 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
432 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
434 /* Addresses are loaded in different ways, depending on the address size
435 in use. The n32 ABI Documentation also mandates the use of additions
436 with overflow checking, but existing implementations don't follow it. */
437 #define ADDRESS_ADD_INSN \
438 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
440 #define ADDRESS_ADDI_INSN \
441 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
443 #define ADDRESS_LOAD_INSN \
444 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
446 #define ADDRESS_STORE_INSN \
447 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
449 /* Return true if the given CPU supports the MIPS16 ASE. */
450 #define CPU_HAS_MIPS16(cpu) \
451 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
452 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
454 /* True if CPU has a dror instruction. */
455 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
457 /* True if CPU has a ror instruction. */
458 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
460 /* True if CPU has seq/sne and seqi/snei instructions. */
461 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
463 /* True if CPU does not implement the all the coprocessor insns. For these
464 CPUs only those COP insns are accepted that are explicitly marked to be
465 available on the CPU. ISA membership for COP insns is ignored. */
466 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
468 /* True if mflo and mfhi can be immediately followed by instructions
469 which write to the HI and LO registers.
471 According to MIPS specifications, MIPS ISAs I, II, and III need
472 (at least) two instructions between the reads of HI/LO and
473 instructions which write them, and later ISAs do not. Contradicting
474 the MIPS specifications, some MIPS IV processor user manuals (e.g.
475 the UM for the NEC Vr5000) document needing the instructions between
476 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
477 MIPS64 and later ISAs to have the interlocks, plus any specific
478 earlier-ISA CPUs for which CPU documentation declares that the
479 instructions are really interlocked. */
480 #define hilo_interlocks \
481 (mips_opts.isa == ISA_MIPS32 \
482 || mips_opts.isa == ISA_MIPS32R2 \
483 || mips_opts.isa == ISA_MIPS64 \
484 || mips_opts.isa == ISA_MIPS64R2 \
485 || mips_opts.arch == CPU_R4010 \
486 || mips_opts.arch == CPU_R10000 \
487 || mips_opts.arch == CPU_R12000 \
488 || mips_opts.arch == CPU_R14000 \
489 || mips_opts.arch == CPU_R16000 \
490 || mips_opts.arch == CPU_RM7000 \
491 || mips_opts.arch == CPU_VR5500 \
494 /* Whether the processor uses hardware interlocks to protect reads
495 from the GPRs after they are loaded from memory, and thus does not
496 require nops to be inserted. This applies to instructions marked
497 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
499 #define gpr_interlocks \
500 (mips_opts.isa != ISA_MIPS1 \
501 || mips_opts.arch == CPU_R3900)
503 /* Whether the processor uses hardware interlocks to avoid delays
504 required by coprocessor instructions, and thus does not require
505 nops to be inserted. This applies to instructions marked
506 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
507 between instructions marked INSN_WRITE_COND_CODE and ones marked
508 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
509 levels I, II, and III. */
510 /* Itbl support may require additional care here. */
511 #define cop_interlocks \
512 ((mips_opts.isa != ISA_MIPS1 \
513 && mips_opts.isa != ISA_MIPS2 \
514 && mips_opts.isa != ISA_MIPS3) \
515 || mips_opts.arch == CPU_R4300 \
518 /* Whether the processor uses hardware interlocks to protect reads
519 from coprocessor registers after they are loaded from memory, and
520 thus does not require nops to be inserted. This applies to
521 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
522 requires at MIPS ISA level I. */
523 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
525 /* Is this a mfhi or mflo instruction? */
526 #define MF_HILO_INSN(PINFO) \
527 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
529 /* Returns true for a (non floating-point) coprocessor instruction. Reading
530 or writing the condition code is only possible on the coprocessors and
531 these insns are not marked with INSN_COP. Thus for these insns use the
532 condition-code flags. */
533 #define COP_INSN(PINFO) \
534 (PINFO != INSN_MACRO \
535 && ((PINFO) & (FP_S | FP_D)) == 0 \
536 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
538 /* MIPS PIC level. */
540 enum mips_pic_level mips_pic
;
542 /* 1 if we should generate 32 bit offsets from the $gp register in
543 SVR4_PIC mode. Currently has no meaning in other modes. */
544 static int mips_big_got
= 0;
546 /* 1 if trap instructions should used for overflow rather than break
548 static int mips_trap
= 0;
550 /* 1 if double width floating point constants should not be constructed
551 by assembling two single width halves into two single width floating
552 point registers which just happen to alias the double width destination
553 register. On some architectures this aliasing can be disabled by a bit
554 in the status register, and the setting of this bit cannot be determined
555 automatically at assemble time. */
556 static int mips_disable_float_construction
;
558 /* Non-zero if any .set noreorder directives were used. */
560 static int mips_any_noreorder
;
562 /* Non-zero if nops should be inserted when the register referenced in
563 an mfhi/mflo instruction is read in the next two instructions. */
564 static int mips_7000_hilo_fix
;
566 /* The size of objects in the small data section. */
567 static unsigned int g_switch_value
= 8;
568 /* Whether the -G option was used. */
569 static int g_switch_seen
= 0;
574 /* If we can determine in advance that GP optimization won't be
575 possible, we can skip the relaxation stuff that tries to produce
576 GP-relative references. This makes delay slot optimization work
579 This function can only provide a guess, but it seems to work for
580 gcc output. It needs to guess right for gcc, otherwise gcc
581 will put what it thinks is a GP-relative instruction in a branch
584 I don't know if a fix is needed for the SVR4_PIC mode. I've only
585 fixed it for the non-PIC mode. KR 95/04/07 */
586 static int nopic_need_relax (symbolS
*, int);
588 /* handle of the OPCODE hash table */
589 static struct hash_control
*op_hash
= NULL
;
591 /* The opcode hash table we use for the mips16. */
592 static struct hash_control
*mips16_op_hash
= NULL
;
594 /* This array holds the chars that always start a comment. If the
595 pre-processor is disabled, these aren't very useful */
596 const char comment_chars
[] = "#";
598 /* This array holds the chars that only start a comment at the beginning of
599 a line. If the line seems to have the form '# 123 filename'
600 .line and .file directives will appear in the pre-processed output */
601 /* Note that input_file.c hand checks for '#' at the beginning of the
602 first line of the input file. This is because the compiler outputs
603 #NO_APP at the beginning of its output. */
604 /* Also note that C style comments are always supported. */
605 const char line_comment_chars
[] = "#";
607 /* This array holds machine specific line separator characters. */
608 const char line_separator_chars
[] = ";";
610 /* Chars that can be used to separate mant from exp in floating point nums */
611 const char EXP_CHARS
[] = "eE";
613 /* Chars that mean this number is a floating point constant */
616 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
618 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
619 changed in read.c . Ideally it shouldn't have to know about it at all,
620 but nothing is ideal around here.
623 static char *insn_error
;
625 static int auto_align
= 1;
627 /* When outputting SVR4 PIC code, the assembler needs to know the
628 offset in the stack frame from which to restore the $gp register.
629 This is set by the .cprestore pseudo-op, and saved in this
631 static offsetT mips_cprestore_offset
= -1;
633 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
634 more optimizations, it can use a register value instead of a memory-saved
635 offset and even an other register than $gp as global pointer. */
636 static offsetT mips_cpreturn_offset
= -1;
637 static int mips_cpreturn_register
= -1;
638 static int mips_gp_register
= GP
;
639 static int mips_gprel_offset
= 0;
641 /* Whether mips_cprestore_offset has been set in the current function
642 (or whether it has already been warned about, if not). */
643 static int mips_cprestore_valid
= 0;
645 /* This is the register which holds the stack frame, as set by the
646 .frame pseudo-op. This is needed to implement .cprestore. */
647 static int mips_frame_reg
= SP
;
649 /* Whether mips_frame_reg has been set in the current function
650 (or whether it has already been warned about, if not). */
651 static int mips_frame_reg_valid
= 0;
653 /* To output NOP instructions correctly, we need to keep information
654 about the previous two instructions. */
656 /* Whether we are optimizing. The default value of 2 means to remove
657 unneeded NOPs and swap branch instructions when possible. A value
658 of 1 means to not swap branches. A value of 0 means to always
660 static int mips_optimize
= 2;
662 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
663 equivalent to seeing no -g option at all. */
664 static int mips_debug
= 0;
666 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
667 #define MAX_VR4130_NOPS 4
669 /* The maximum number of NOPs needed to fill delay slots. */
670 #define MAX_DELAY_NOPS 2
672 /* The maximum number of NOPs needed for any purpose. */
675 /* A list of previous instructions, with index 0 being the most recent.
676 We need to look back MAX_NOPS instructions when filling delay slots
677 or working around processor errata. We need to look back one
678 instruction further if we're thinking about using history[0] to
679 fill a branch delay slot. */
680 static struct mips_cl_insn history
[1 + MAX_NOPS
];
682 /* Nop instructions used by emit_nop. */
683 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
685 /* The appropriate nop for the current mode. */
686 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
688 /* If this is set, it points to a frag holding nop instructions which
689 were inserted before the start of a noreorder section. If those
690 nops turn out to be unnecessary, the size of the frag can be
692 static fragS
*prev_nop_frag
;
694 /* The number of nop instructions we created in prev_nop_frag. */
695 static int prev_nop_frag_holds
;
697 /* The number of nop instructions that we know we need in
699 static int prev_nop_frag_required
;
701 /* The number of instructions we've seen since prev_nop_frag. */
702 static int prev_nop_frag_since
;
704 /* For ECOFF and ELF, relocations against symbols are done in two
705 parts, with a HI relocation and a LO relocation. Each relocation
706 has only 16 bits of space to store an addend. This means that in
707 order for the linker to handle carries correctly, it must be able
708 to locate both the HI and the LO relocation. This means that the
709 relocations must appear in order in the relocation table.
711 In order to implement this, we keep track of each unmatched HI
712 relocation. We then sort them so that they immediately precede the
713 corresponding LO relocation. */
718 struct mips_hi_fixup
*next
;
721 /* The section this fixup is in. */
725 /* The list of unmatched HI relocs. */
727 static struct mips_hi_fixup
*mips_hi_fixup_list
;
729 /* The frag containing the last explicit relocation operator.
730 Null if explicit relocations have not been used. */
732 static fragS
*prev_reloc_op_frag
;
734 /* Map normal MIPS register numbers to mips16 register numbers. */
736 #define X ILLEGAL_REG
737 static const int mips32_to_16_reg_map
[] =
739 X
, X
, 2, 3, 4, 5, 6, 7,
740 X
, X
, X
, X
, X
, X
, X
, X
,
741 0, 1, X
, X
, X
, X
, X
, X
,
742 X
, X
, X
, X
, X
, X
, X
, X
746 /* Map mips16 register numbers to normal MIPS register numbers. */
748 static const unsigned int mips16_to_32_reg_map
[] =
750 16, 17, 2, 3, 4, 5, 6, 7
753 /* Classifies the kind of instructions we're interested in when
754 implementing -mfix-vr4120. */
755 enum fix_vr4120_class
763 NUM_FIX_VR4120_CLASSES
766 /* ...likewise -mfix-loongson2f-jump. */
767 static bfd_boolean mips_fix_loongson2f_jump
;
769 /* ...likewise -mfix-loongson2f-nop. */
770 static bfd_boolean mips_fix_loongson2f_nop
;
772 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
773 static bfd_boolean mips_fix_loongson2f
;
775 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
776 there must be at least one other instruction between an instruction
777 of type X and an instruction of type Y. */
778 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
780 /* True if -mfix-vr4120 is in force. */
781 static int mips_fix_vr4120
;
783 /* ...likewise -mfix-vr4130. */
784 static int mips_fix_vr4130
;
786 /* ...likewise -mfix-24k. */
787 static int mips_fix_24k
;
789 /* ...likewise -mfix-cn63xxp1 */
790 static bfd_boolean mips_fix_cn63xxp1
;
792 /* We don't relax branches by default, since this causes us to expand
793 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
794 fail to compute the offset before expanding the macro to the most
795 efficient expansion. */
797 static int mips_relax_branch
;
799 /* The expansion of many macros depends on the type of symbol that
800 they refer to. For example, when generating position-dependent code,
801 a macro that refers to a symbol may have two different expansions,
802 one which uses GP-relative addresses and one which uses absolute
803 addresses. When generating SVR4-style PIC, a macro may have
804 different expansions for local and global symbols.
806 We handle these situations by generating both sequences and putting
807 them in variant frags. In position-dependent code, the first sequence
808 will be the GP-relative one and the second sequence will be the
809 absolute one. In SVR4 PIC, the first sequence will be for global
810 symbols and the second will be for local symbols.
812 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
813 SECOND are the lengths of the two sequences in bytes. These fields
814 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
815 the subtype has the following flags:
818 Set if it has been decided that we should use the second
819 sequence instead of the first.
822 Set in the first variant frag if the macro's second implementation
823 is longer than its first. This refers to the macro as a whole,
824 not an individual relaxation.
827 Set in the first variant frag if the macro appeared in a .set nomacro
828 block and if one alternative requires a warning but the other does not.
831 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
834 The frag's "opcode" points to the first fixup for relaxable code.
836 Relaxable macros are generated using a sequence such as:
838 relax_start (SYMBOL);
839 ... generate first expansion ...
841 ... generate second expansion ...
844 The code and fixups for the unwanted alternative are discarded
845 by md_convert_frag. */
846 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
848 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
849 #define RELAX_SECOND(X) ((X) & 0xff)
850 #define RELAX_USE_SECOND 0x10000
851 #define RELAX_SECOND_LONGER 0x20000
852 #define RELAX_NOMACRO 0x40000
853 #define RELAX_DELAY_SLOT 0x80000
855 /* Branch without likely bit. If label is out of range, we turn:
857 beq reg1, reg2, label
867 with the following opcode replacements:
874 bltzal <-> bgezal (with jal label instead of j label)
876 Even though keeping the delay slot instruction in the delay slot of
877 the branch would be more efficient, it would be very tricky to do
878 correctly, because we'd have to introduce a variable frag *after*
879 the delay slot instruction, and expand that instead. Let's do it
880 the easy way for now, even if the branch-not-taken case now costs
881 one additional instruction. Out-of-range branches are not supposed
882 to be common, anyway.
884 Branch likely. If label is out of range, we turn:
886 beql reg1, reg2, label
887 delay slot (annulled if branch not taken)
896 delay slot (executed only if branch taken)
899 It would be possible to generate a shorter sequence by losing the
900 likely bit, generating something like:
905 delay slot (executed only if branch taken)
917 bltzall -> bgezal (with jal label instead of j label)
918 bgezall -> bltzal (ditto)
921 but it's not clear that it would actually improve performance. */
922 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
925 | ((toofar) ? 1 : 0) \
927 | ((likely) ? 4 : 0) \
928 | ((uncond) ? 8 : 0)))
929 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
930 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
931 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
932 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
933 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
935 /* For mips16 code, we use an entirely different form of relaxation.
936 mips16 supports two versions of most instructions which take
937 immediate values: a small one which takes some small value, and a
938 larger one which takes a 16 bit value. Since branches also follow
939 this pattern, relaxing these values is required.
941 We can assemble both mips16 and normal MIPS code in a single
942 object. Therefore, we need to support this type of relaxation at
943 the same time that we support the relaxation described above. We
944 use the high bit of the subtype field to distinguish these cases.
946 The information we store for this type of relaxation is the
947 argument code found in the opcode file for this relocation, whether
948 the user explicitly requested a small or extended form, and whether
949 the relocation is in a jump or jal delay slot. That tells us the
950 size of the value, and how it should be stored. We also store
951 whether the fragment is considered to be extended or not. We also
952 store whether this is known to be a branch to a different section,
953 whether we have tried to relax this frag yet, and whether we have
954 ever extended a PC relative fragment because of a shift count. */
955 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
958 | ((small) ? 0x100 : 0) \
959 | ((ext) ? 0x200 : 0) \
960 | ((dslot) ? 0x400 : 0) \
961 | ((jal_dslot) ? 0x800 : 0))
962 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
963 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
964 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
965 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
966 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
967 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
968 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
969 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
970 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
971 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
972 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
973 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
975 /* Is the given value a sign-extended 32-bit value? */
976 #define IS_SEXT_32BIT_NUM(x) \
977 (((x) &~ (offsetT) 0x7fffffff) == 0 \
978 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
980 /* Is the given value a sign-extended 16-bit value? */
981 #define IS_SEXT_16BIT_NUM(x) \
982 (((x) &~ (offsetT) 0x7fff) == 0 \
983 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
985 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
986 #define IS_ZEXT_32BIT_NUM(x) \
987 (((x) &~ (offsetT) 0xffffffff) == 0 \
988 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
990 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
991 VALUE << SHIFT. VALUE is evaluated exactly once. */
992 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
993 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
994 | (((VALUE) & (MASK)) << (SHIFT)))
996 /* Extract bits MASK << SHIFT from STRUCT and shift them right
998 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
999 (((STRUCT) >> (SHIFT)) & (MASK))
1001 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1002 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1004 include/opcode/mips.h specifies operand fields using the macros
1005 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1006 with "MIPS16OP" instead of "OP". */
1007 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
1008 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1009 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1010 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1011 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1013 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1014 #define EXTRACT_OPERAND(FIELD, INSN) \
1015 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1016 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1017 EXTRACT_BITS ((INSN).insn_opcode, \
1018 MIPS16OP_MASK_##FIELD, \
1019 MIPS16OP_SH_##FIELD)
1021 /* Global variables used when generating relaxable macros. See the
1022 comment above RELAX_ENCODE for more details about how relaxation
1025 /* 0 if we're not emitting a relaxable macro.
1026 1 if we're emitting the first of the two relaxation alternatives.
1027 2 if we're emitting the second alternative. */
1030 /* The first relaxable fixup in the current frag. (In other words,
1031 the first fixup that refers to relaxable code.) */
1034 /* sizes[0] says how many bytes of the first alternative are stored in
1035 the current frag. Likewise sizes[1] for the second alternative. */
1036 unsigned int sizes
[2];
1038 /* The symbol on which the choice of sequence depends. */
1042 /* Global variables used to decide whether a macro needs a warning. */
1044 /* True if the macro is in a branch delay slot. */
1045 bfd_boolean delay_slot_p
;
1047 /* For relaxable macros, sizes[0] is the length of the first alternative
1048 in bytes and sizes[1] is the length of the second alternative.
1049 For non-relaxable macros, both elements give the length of the
1051 unsigned int sizes
[2];
1053 /* The first variant frag for this macro. */
1055 } mips_macro_warning
;
1057 /* Prototypes for static functions. */
1059 #define internalError() \
1060 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1062 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1064 static void append_insn
1065 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*);
1066 static void mips_no_prev_insn (void);
1067 static void macro_build (expressionS
*, const char *, const char *, ...);
1068 static void mips16_macro_build
1069 (expressionS
*, const char *, const char *, va_list *);
1070 static void load_register (int, expressionS
*, int);
1071 static void macro_start (void);
1072 static void macro_end (void);
1073 static void macro (struct mips_cl_insn
* ip
);
1074 static void mips16_macro (struct mips_cl_insn
* ip
);
1075 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1076 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1077 static void mips16_immed
1078 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1079 unsigned long *, bfd_boolean
*, unsigned short *);
1080 static size_t my_getSmallExpression
1081 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1082 static void my_getExpression (expressionS
*, char *);
1083 static void s_align (int);
1084 static void s_change_sec (int);
1085 static void s_change_section (int);
1086 static void s_cons (int);
1087 static void s_float_cons (int);
1088 static void s_mips_globl (int);
1089 static void s_option (int);
1090 static void s_mipsset (int);
1091 static void s_abicalls (int);
1092 static void s_cpload (int);
1093 static void s_cpsetup (int);
1094 static void s_cplocal (int);
1095 static void s_cprestore (int);
1096 static void s_cpreturn (int);
1097 static void s_dtprelword (int);
1098 static void s_dtpreldword (int);
1099 static void s_gpvalue (int);
1100 static void s_gpword (int);
1101 static void s_gpdword (int);
1102 static void s_cpadd (int);
1103 static void s_insn (int);
1104 static void md_obj_begin (void);
1105 static void md_obj_end (void);
1106 static void s_mips_ent (int);
1107 static void s_mips_end (int);
1108 static void s_mips_frame (int);
1109 static void s_mips_mask (int reg_type
);
1110 static void s_mips_stab (int);
1111 static void s_mips_weakext (int);
1112 static void s_mips_file (int);
1113 static void s_mips_loc (int);
1114 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1115 static int relaxed_branch_length (fragS
*, asection
*, int);
1116 static int validate_mips_insn (const struct mips_opcode
*);
1118 /* Table and functions used to map between CPU/ISA names, and
1119 ISA levels, and CPU numbers. */
1121 struct mips_cpu_info
1123 const char *name
; /* CPU or ISA name. */
1124 int flags
; /* ASEs available, or ISA flag. */
1125 int isa
; /* ISA level. */
1126 int cpu
; /* CPU number (default CPU if ISA). */
1129 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1130 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1131 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1132 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1133 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1134 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1135 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1137 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1138 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1139 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1143 The following pseudo-ops from the Kane and Heinrich MIPS book
1144 should be defined here, but are currently unsupported: .alias,
1145 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1147 The following pseudo-ops from the Kane and Heinrich MIPS book are
1148 specific to the type of debugging information being generated, and
1149 should be defined by the object format: .aent, .begin, .bend,
1150 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1153 The following pseudo-ops from the Kane and Heinrich MIPS book are
1154 not MIPS CPU specific, but are also not specific to the object file
1155 format. This file is probably the best place to define them, but
1156 they are not currently supported: .asm0, .endr, .lab, .struct. */
1158 static const pseudo_typeS mips_pseudo_table
[] =
1160 /* MIPS specific pseudo-ops. */
1161 {"option", s_option
, 0},
1162 {"set", s_mipsset
, 0},
1163 {"rdata", s_change_sec
, 'r'},
1164 {"sdata", s_change_sec
, 's'},
1165 {"livereg", s_ignore
, 0},
1166 {"abicalls", s_abicalls
, 0},
1167 {"cpload", s_cpload
, 0},
1168 {"cpsetup", s_cpsetup
, 0},
1169 {"cplocal", s_cplocal
, 0},
1170 {"cprestore", s_cprestore
, 0},
1171 {"cpreturn", s_cpreturn
, 0},
1172 {"dtprelword", s_dtprelword
, 0},
1173 {"dtpreldword", s_dtpreldword
, 0},
1174 {"gpvalue", s_gpvalue
, 0},
1175 {"gpword", s_gpword
, 0},
1176 {"gpdword", s_gpdword
, 0},
1177 {"cpadd", s_cpadd
, 0},
1178 {"insn", s_insn
, 0},
1180 /* Relatively generic pseudo-ops that happen to be used on MIPS
1182 {"asciiz", stringer
, 8 + 1},
1183 {"bss", s_change_sec
, 'b'},
1185 {"half", s_cons
, 1},
1186 {"dword", s_cons
, 3},
1187 {"weakext", s_mips_weakext
, 0},
1188 {"origin", s_org
, 0},
1189 {"repeat", s_rept
, 0},
1191 /* For MIPS this is non-standard, but we define it for consistency. */
1192 {"sbss", s_change_sec
, 'B'},
1194 /* These pseudo-ops are defined in read.c, but must be overridden
1195 here for one reason or another. */
1196 {"align", s_align
, 0},
1197 {"byte", s_cons
, 0},
1198 {"data", s_change_sec
, 'd'},
1199 {"double", s_float_cons
, 'd'},
1200 {"float", s_float_cons
, 'f'},
1201 {"globl", s_mips_globl
, 0},
1202 {"global", s_mips_globl
, 0},
1203 {"hword", s_cons
, 1},
1205 {"long", s_cons
, 2},
1206 {"octa", s_cons
, 4},
1207 {"quad", s_cons
, 3},
1208 {"section", s_change_section
, 0},
1209 {"short", s_cons
, 1},
1210 {"single", s_float_cons
, 'f'},
1211 {"stabn", s_mips_stab
, 'n'},
1212 {"text", s_change_sec
, 't'},
1213 {"word", s_cons
, 2},
1215 { "extern", ecoff_directive_extern
, 0},
1220 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1222 /* These pseudo-ops should be defined by the object file format.
1223 However, a.out doesn't support them, so we have versions here. */
1224 {"aent", s_mips_ent
, 1},
1225 {"bgnb", s_ignore
, 0},
1226 {"end", s_mips_end
, 0},
1227 {"endb", s_ignore
, 0},
1228 {"ent", s_mips_ent
, 0},
1229 {"file", s_mips_file
, 0},
1230 {"fmask", s_mips_mask
, 'F'},
1231 {"frame", s_mips_frame
, 0},
1232 {"loc", s_mips_loc
, 0},
1233 {"mask", s_mips_mask
, 'R'},
1234 {"verstamp", s_ignore
, 0},
1238 extern void pop_insert (const pseudo_typeS
*);
1241 mips_pop_insert (void)
1243 pop_insert (mips_pseudo_table
);
1244 if (! ECOFF_DEBUGGING
)
1245 pop_insert (mips_nonecoff_pseudo_table
);
1248 /* Symbols labelling the current insn. */
1250 struct insn_label_list
1252 struct insn_label_list
*next
;
1256 static struct insn_label_list
*free_insn_labels
;
1257 #define label_list tc_segment_info_data.labels
1259 static void mips_clear_insn_labels (void);
1262 mips_clear_insn_labels (void)
1264 register struct insn_label_list
**pl
;
1265 segment_info_type
*si
;
1269 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1272 si
= seg_info (now_seg
);
1273 *pl
= si
->label_list
;
1274 si
->label_list
= NULL
;
1279 static char *expr_end
;
1281 /* Expressions which appear in instructions. These are set by
1284 static expressionS imm_expr
;
1285 static expressionS imm2_expr
;
1286 static expressionS offset_expr
;
1288 /* Relocs associated with imm_expr and offset_expr. */
1290 static bfd_reloc_code_real_type imm_reloc
[3]
1291 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1292 static bfd_reloc_code_real_type offset_reloc
[3]
1293 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1295 /* These are set by mips16_ip if an explicit extension is used. */
1297 static bfd_boolean mips16_small
, mips16_ext
;
1300 /* The pdr segment for per procedure frame/regmask info. Not used for
1303 static segT pdr_seg
;
1306 /* The default target format to use. */
1309 mips_target_format (void)
1311 switch (OUTPUT_FLAVOR
)
1313 case bfd_target_ecoff_flavour
:
1314 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1315 case bfd_target_coff_flavour
:
1317 case bfd_target_elf_flavour
:
1319 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1320 return (target_big_endian
1321 ? "elf32-bigmips-vxworks"
1322 : "elf32-littlemips-vxworks");
1325 /* This is traditional mips. */
1326 return (target_big_endian
1327 ? (HAVE_64BIT_OBJECTS
1328 ? "elf64-tradbigmips"
1330 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1331 : (HAVE_64BIT_OBJECTS
1332 ? "elf64-tradlittlemips"
1334 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1336 return (target_big_endian
1337 ? (HAVE_64BIT_OBJECTS
1340 ? "elf32-nbigmips" : "elf32-bigmips"))
1341 : (HAVE_64BIT_OBJECTS
1342 ? "elf64-littlemips"
1344 ? "elf32-nlittlemips" : "elf32-littlemips")));
1352 /* Return the length of instruction INSN. */
1354 static inline unsigned int
1355 insn_length (const struct mips_cl_insn
*insn
)
1357 if (!mips_opts
.mips16
)
1359 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1362 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1365 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1370 insn
->use_extend
= FALSE
;
1372 insn
->insn_opcode
= mo
->match
;
1375 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1376 insn
->fixp
[i
] = NULL
;
1377 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1378 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1379 insn
->mips16_absolute_jump_p
= 0;
1382 /* Record the current MIPS16 mode in now_seg. */
1385 mips_record_mips16_mode (void)
1387 segment_info_type
*si
;
1389 si
= seg_info (now_seg
);
1390 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1391 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1394 /* Install INSN at the location specified by its "frag" and "where" fields. */
1397 install_insn (const struct mips_cl_insn
*insn
)
1399 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1400 if (!mips_opts
.mips16
)
1401 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1402 else if (insn
->mips16_absolute_jump_p
)
1404 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1405 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1409 if (insn
->use_extend
)
1411 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1414 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1416 mips_record_mips16_mode ();
1419 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1420 and install the opcode in the new location. */
1423 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1428 insn
->where
= where
;
1429 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1430 if (insn
->fixp
[i
] != NULL
)
1432 insn
->fixp
[i
]->fx_frag
= frag
;
1433 insn
->fixp
[i
]->fx_where
= where
;
1435 install_insn (insn
);
1438 /* Add INSN to the end of the output. */
1441 add_fixed_insn (struct mips_cl_insn
*insn
)
1443 char *f
= frag_more (insn_length (insn
));
1444 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1447 /* Start a variant frag and move INSN to the start of the variant part,
1448 marking it as fixed. The other arguments are as for frag_var. */
1451 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1452 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1454 frag_grow (max_chars
);
1455 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1457 frag_var (rs_machine_dependent
, max_chars
, var
,
1458 subtype
, symbol
, offset
, NULL
);
1461 /* Insert N copies of INSN into the history buffer, starting at
1462 position FIRST. Neither FIRST nor N need to be clipped. */
1465 insert_into_history (unsigned int first
, unsigned int n
,
1466 const struct mips_cl_insn
*insn
)
1468 if (mips_relax
.sequence
!= 2)
1472 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1474 history
[i
] = history
[i
- n
];
1480 /* Emit a nop instruction, recording it in the history buffer. */
1485 add_fixed_insn (NOP_INSN
);
1486 insert_into_history (0, 1, NOP_INSN
);
1489 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1490 the idea is to make it obvious at a glance that each errata is
1494 init_vr4120_conflicts (void)
1496 #define CONFLICT(FIRST, SECOND) \
1497 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1499 /* Errata 21 - [D]DIV[U] after [D]MACC */
1500 CONFLICT (MACC
, DIV
);
1501 CONFLICT (DMACC
, DIV
);
1503 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1504 CONFLICT (DMULT
, DMULT
);
1505 CONFLICT (DMULT
, DMACC
);
1506 CONFLICT (DMACC
, DMULT
);
1507 CONFLICT (DMACC
, DMACC
);
1509 /* Errata 24 - MT{LO,HI} after [D]MACC */
1510 CONFLICT (MACC
, MTHILO
);
1511 CONFLICT (DMACC
, MTHILO
);
1513 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1514 instruction is executed immediately after a MACC or DMACC
1515 instruction, the result of [either instruction] is incorrect." */
1516 CONFLICT (MACC
, MULT
);
1517 CONFLICT (MACC
, DMULT
);
1518 CONFLICT (DMACC
, MULT
);
1519 CONFLICT (DMACC
, DMULT
);
1521 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1522 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1523 DDIV or DDIVU instruction, the result of the MACC or
1524 DMACC instruction is incorrect.". */
1525 CONFLICT (DMULT
, MACC
);
1526 CONFLICT (DMULT
, DMACC
);
1527 CONFLICT (DIV
, MACC
);
1528 CONFLICT (DIV
, DMACC
);
1538 #define RTYPE_MASK 0x1ff00
1539 #define RTYPE_NUM 0x00100
1540 #define RTYPE_FPU 0x00200
1541 #define RTYPE_FCC 0x00400
1542 #define RTYPE_VEC 0x00800
1543 #define RTYPE_GP 0x01000
1544 #define RTYPE_CP0 0x02000
1545 #define RTYPE_PC 0x04000
1546 #define RTYPE_ACC 0x08000
1547 #define RTYPE_CCC 0x10000
1548 #define RNUM_MASK 0x000ff
1549 #define RWARN 0x80000
1551 #define GENERIC_REGISTER_NUMBERS \
1552 {"$0", RTYPE_NUM | 0}, \
1553 {"$1", RTYPE_NUM | 1}, \
1554 {"$2", RTYPE_NUM | 2}, \
1555 {"$3", RTYPE_NUM | 3}, \
1556 {"$4", RTYPE_NUM | 4}, \
1557 {"$5", RTYPE_NUM | 5}, \
1558 {"$6", RTYPE_NUM | 6}, \
1559 {"$7", RTYPE_NUM | 7}, \
1560 {"$8", RTYPE_NUM | 8}, \
1561 {"$9", RTYPE_NUM | 9}, \
1562 {"$10", RTYPE_NUM | 10}, \
1563 {"$11", RTYPE_NUM | 11}, \
1564 {"$12", RTYPE_NUM | 12}, \
1565 {"$13", RTYPE_NUM | 13}, \
1566 {"$14", RTYPE_NUM | 14}, \
1567 {"$15", RTYPE_NUM | 15}, \
1568 {"$16", RTYPE_NUM | 16}, \
1569 {"$17", RTYPE_NUM | 17}, \
1570 {"$18", RTYPE_NUM | 18}, \
1571 {"$19", RTYPE_NUM | 19}, \
1572 {"$20", RTYPE_NUM | 20}, \
1573 {"$21", RTYPE_NUM | 21}, \
1574 {"$22", RTYPE_NUM | 22}, \
1575 {"$23", RTYPE_NUM | 23}, \
1576 {"$24", RTYPE_NUM | 24}, \
1577 {"$25", RTYPE_NUM | 25}, \
1578 {"$26", RTYPE_NUM | 26}, \
1579 {"$27", RTYPE_NUM | 27}, \
1580 {"$28", RTYPE_NUM | 28}, \
1581 {"$29", RTYPE_NUM | 29}, \
1582 {"$30", RTYPE_NUM | 30}, \
1583 {"$31", RTYPE_NUM | 31}
1585 #define FPU_REGISTER_NAMES \
1586 {"$f0", RTYPE_FPU | 0}, \
1587 {"$f1", RTYPE_FPU | 1}, \
1588 {"$f2", RTYPE_FPU | 2}, \
1589 {"$f3", RTYPE_FPU | 3}, \
1590 {"$f4", RTYPE_FPU | 4}, \
1591 {"$f5", RTYPE_FPU | 5}, \
1592 {"$f6", RTYPE_FPU | 6}, \
1593 {"$f7", RTYPE_FPU | 7}, \
1594 {"$f8", RTYPE_FPU | 8}, \
1595 {"$f9", RTYPE_FPU | 9}, \
1596 {"$f10", RTYPE_FPU | 10}, \
1597 {"$f11", RTYPE_FPU | 11}, \
1598 {"$f12", RTYPE_FPU | 12}, \
1599 {"$f13", RTYPE_FPU | 13}, \
1600 {"$f14", RTYPE_FPU | 14}, \
1601 {"$f15", RTYPE_FPU | 15}, \
1602 {"$f16", RTYPE_FPU | 16}, \
1603 {"$f17", RTYPE_FPU | 17}, \
1604 {"$f18", RTYPE_FPU | 18}, \
1605 {"$f19", RTYPE_FPU | 19}, \
1606 {"$f20", RTYPE_FPU | 20}, \
1607 {"$f21", RTYPE_FPU | 21}, \
1608 {"$f22", RTYPE_FPU | 22}, \
1609 {"$f23", RTYPE_FPU | 23}, \
1610 {"$f24", RTYPE_FPU | 24}, \
1611 {"$f25", RTYPE_FPU | 25}, \
1612 {"$f26", RTYPE_FPU | 26}, \
1613 {"$f27", RTYPE_FPU | 27}, \
1614 {"$f28", RTYPE_FPU | 28}, \
1615 {"$f29", RTYPE_FPU | 29}, \
1616 {"$f30", RTYPE_FPU | 30}, \
1617 {"$f31", RTYPE_FPU | 31}
1619 #define FPU_CONDITION_CODE_NAMES \
1620 {"$fcc0", RTYPE_FCC | 0}, \
1621 {"$fcc1", RTYPE_FCC | 1}, \
1622 {"$fcc2", RTYPE_FCC | 2}, \
1623 {"$fcc3", RTYPE_FCC | 3}, \
1624 {"$fcc4", RTYPE_FCC | 4}, \
1625 {"$fcc5", RTYPE_FCC | 5}, \
1626 {"$fcc6", RTYPE_FCC | 6}, \
1627 {"$fcc7", RTYPE_FCC | 7}
1629 #define COPROC_CONDITION_CODE_NAMES \
1630 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1631 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1632 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1633 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1634 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1635 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1636 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1637 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1639 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1640 {"$a4", RTYPE_GP | 8}, \
1641 {"$a5", RTYPE_GP | 9}, \
1642 {"$a6", RTYPE_GP | 10}, \
1643 {"$a7", RTYPE_GP | 11}, \
1644 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1645 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1646 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1647 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1648 {"$t0", RTYPE_GP | 12}, \
1649 {"$t1", RTYPE_GP | 13}, \
1650 {"$t2", RTYPE_GP | 14}, \
1651 {"$t3", RTYPE_GP | 15}
1653 #define O32_SYMBOLIC_REGISTER_NAMES \
1654 {"$t0", RTYPE_GP | 8}, \
1655 {"$t1", RTYPE_GP | 9}, \
1656 {"$t2", RTYPE_GP | 10}, \
1657 {"$t3", RTYPE_GP | 11}, \
1658 {"$t4", RTYPE_GP | 12}, \
1659 {"$t5", RTYPE_GP | 13}, \
1660 {"$t6", RTYPE_GP | 14}, \
1661 {"$t7", RTYPE_GP | 15}, \
1662 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1663 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1664 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1665 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1667 /* Remaining symbolic register names */
1668 #define SYMBOLIC_REGISTER_NAMES \
1669 {"$zero", RTYPE_GP | 0}, \
1670 {"$at", RTYPE_GP | 1}, \
1671 {"$AT", RTYPE_GP | 1}, \
1672 {"$v0", RTYPE_GP | 2}, \
1673 {"$v1", RTYPE_GP | 3}, \
1674 {"$a0", RTYPE_GP | 4}, \
1675 {"$a1", RTYPE_GP | 5}, \
1676 {"$a2", RTYPE_GP | 6}, \
1677 {"$a3", RTYPE_GP | 7}, \
1678 {"$s0", RTYPE_GP | 16}, \
1679 {"$s1", RTYPE_GP | 17}, \
1680 {"$s2", RTYPE_GP | 18}, \
1681 {"$s3", RTYPE_GP | 19}, \
1682 {"$s4", RTYPE_GP | 20}, \
1683 {"$s5", RTYPE_GP | 21}, \
1684 {"$s6", RTYPE_GP | 22}, \
1685 {"$s7", RTYPE_GP | 23}, \
1686 {"$t8", RTYPE_GP | 24}, \
1687 {"$t9", RTYPE_GP | 25}, \
1688 {"$k0", RTYPE_GP | 26}, \
1689 {"$kt0", RTYPE_GP | 26}, \
1690 {"$k1", RTYPE_GP | 27}, \
1691 {"$kt1", RTYPE_GP | 27}, \
1692 {"$gp", RTYPE_GP | 28}, \
1693 {"$sp", RTYPE_GP | 29}, \
1694 {"$s8", RTYPE_GP | 30}, \
1695 {"$fp", RTYPE_GP | 30}, \
1696 {"$ra", RTYPE_GP | 31}
1698 #define MIPS16_SPECIAL_REGISTER_NAMES \
1699 {"$pc", RTYPE_PC | 0}
1701 #define MDMX_VECTOR_REGISTER_NAMES \
1702 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1703 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1704 {"$v2", RTYPE_VEC | 2}, \
1705 {"$v3", RTYPE_VEC | 3}, \
1706 {"$v4", RTYPE_VEC | 4}, \
1707 {"$v5", RTYPE_VEC | 5}, \
1708 {"$v6", RTYPE_VEC | 6}, \
1709 {"$v7", RTYPE_VEC | 7}, \
1710 {"$v8", RTYPE_VEC | 8}, \
1711 {"$v9", RTYPE_VEC | 9}, \
1712 {"$v10", RTYPE_VEC | 10}, \
1713 {"$v11", RTYPE_VEC | 11}, \
1714 {"$v12", RTYPE_VEC | 12}, \
1715 {"$v13", RTYPE_VEC | 13}, \
1716 {"$v14", RTYPE_VEC | 14}, \
1717 {"$v15", RTYPE_VEC | 15}, \
1718 {"$v16", RTYPE_VEC | 16}, \
1719 {"$v17", RTYPE_VEC | 17}, \
1720 {"$v18", RTYPE_VEC | 18}, \
1721 {"$v19", RTYPE_VEC | 19}, \
1722 {"$v20", RTYPE_VEC | 20}, \
1723 {"$v21", RTYPE_VEC | 21}, \
1724 {"$v22", RTYPE_VEC | 22}, \
1725 {"$v23", RTYPE_VEC | 23}, \
1726 {"$v24", RTYPE_VEC | 24}, \
1727 {"$v25", RTYPE_VEC | 25}, \
1728 {"$v26", RTYPE_VEC | 26}, \
1729 {"$v27", RTYPE_VEC | 27}, \
1730 {"$v28", RTYPE_VEC | 28}, \
1731 {"$v29", RTYPE_VEC | 29}, \
1732 {"$v30", RTYPE_VEC | 30}, \
1733 {"$v31", RTYPE_VEC | 31}
1735 #define MIPS_DSP_ACCUMULATOR_NAMES \
1736 {"$ac0", RTYPE_ACC | 0}, \
1737 {"$ac1", RTYPE_ACC | 1}, \
1738 {"$ac2", RTYPE_ACC | 2}, \
1739 {"$ac3", RTYPE_ACC | 3}
1741 static const struct regname reg_names
[] = {
1742 GENERIC_REGISTER_NUMBERS
,
1744 FPU_CONDITION_CODE_NAMES
,
1745 COPROC_CONDITION_CODE_NAMES
,
1747 /* The $txx registers depends on the abi,
1748 these will be added later into the symbol table from
1749 one of the tables below once mips_abi is set after
1750 parsing of arguments from the command line. */
1751 SYMBOLIC_REGISTER_NAMES
,
1753 MIPS16_SPECIAL_REGISTER_NAMES
,
1754 MDMX_VECTOR_REGISTER_NAMES
,
1755 MIPS_DSP_ACCUMULATOR_NAMES
,
1759 static const struct regname reg_names_o32
[] = {
1760 O32_SYMBOLIC_REGISTER_NAMES
,
1764 static const struct regname reg_names_n32n64
[] = {
1765 N32N64_SYMBOLIC_REGISTER_NAMES
,
1770 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1777 /* Find end of name. */
1779 if (is_name_beginner (*e
))
1781 while (is_part_of_name (*e
))
1784 /* Terminate name. */
1788 /* Look for a register symbol. */
1789 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1791 int r
= S_GET_VALUE (symbolP
);
1793 reg
= r
& RNUM_MASK
;
1794 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1795 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1796 reg
= (r
& RNUM_MASK
) - 2;
1798 /* Else see if this is a register defined in an itbl entry. */
1799 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1806 if (itbl_get_reg_val (n
, &r
))
1807 reg
= r
& RNUM_MASK
;
1810 /* Advance to next token if a register was recognised. */
1813 else if (types
& RWARN
)
1814 as_warn (_("Unrecognized register name `%s'"), *s
);
1822 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1823 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1826 is_opcode_valid (const struct mips_opcode
*mo
)
1828 int isa
= mips_opts
.isa
;
1831 if (mips_opts
.ase_mdmx
)
1833 if (mips_opts
.ase_dsp
)
1835 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1837 if (mips_opts
.ase_dspr2
)
1839 if (mips_opts
.ase_mt
)
1841 if (mips_opts
.ase_mips3d
)
1843 if (mips_opts
.ase_smartmips
)
1844 isa
|= INSN_SMARTMIPS
;
1846 /* Don't accept instructions based on the ISA if the CPU does not implement
1847 all the coprocessor insns. */
1848 if (NO_ISA_COP (mips_opts
.arch
)
1849 && COP_INSN (mo
->pinfo
))
1852 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1855 /* Check whether the instruction or macro requires single-precision or
1856 double-precision floating-point support. Note that this information is
1857 stored differently in the opcode table for insns and macros. */
1858 if (mo
->pinfo
== INSN_MACRO
)
1860 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1861 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1865 fp_s
= mo
->pinfo
& FP_S
;
1866 fp_d
= mo
->pinfo
& FP_D
;
1869 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1872 if (fp_s
&& mips_opts
.soft_float
)
1878 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1879 selected ISA and architecture. */
1882 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1884 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1887 /* This function is called once, at assembler startup time. It should set up
1888 all the tables, etc. that the MD part of the assembler will need. */
1893 const char *retval
= NULL
;
1897 if (mips_pic
!= NO_PIC
)
1899 if (g_switch_seen
&& g_switch_value
!= 0)
1900 as_bad (_("-G may not be used in position-independent code"));
1904 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1905 as_warn (_("Could not set architecture and machine"));
1907 op_hash
= hash_new ();
1909 for (i
= 0; i
< NUMOPCODES
;)
1911 const char *name
= mips_opcodes
[i
].name
;
1913 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1916 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1917 mips_opcodes
[i
].name
, retval
);
1918 /* Probably a memory allocation problem? Give up now. */
1919 as_fatal (_("Broken assembler. No assembly attempted."));
1923 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1925 if (!validate_mips_insn (&mips_opcodes
[i
]))
1927 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1929 create_insn (&nop_insn
, mips_opcodes
+ i
);
1930 if (mips_fix_loongson2f_nop
)
1931 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
1932 nop_insn
.fixed_p
= 1;
1937 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1940 mips16_op_hash
= hash_new ();
1943 while (i
< bfd_mips16_num_opcodes
)
1945 const char *name
= mips16_opcodes
[i
].name
;
1947 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1949 as_fatal (_("internal: can't hash `%s': %s"),
1950 mips16_opcodes
[i
].name
, retval
);
1953 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1954 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1955 != mips16_opcodes
[i
].match
))
1957 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1958 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1961 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1963 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1964 mips16_nop_insn
.fixed_p
= 1;
1968 while (i
< bfd_mips16_num_opcodes
1969 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1973 as_fatal (_("Broken assembler. No assembly attempted."));
1975 /* We add all the general register names to the symbol table. This
1976 helps us detect invalid uses of them. */
1977 for (i
= 0; reg_names
[i
].name
; i
++)
1978 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1979 reg_names
[i
].num
, /* & RNUM_MASK, */
1980 &zero_address_frag
));
1982 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1983 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1984 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
1985 &zero_address_frag
));
1987 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1988 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1989 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
1990 &zero_address_frag
));
1992 mips_no_prev_insn ();
1995 mips_cprmask
[0] = 0;
1996 mips_cprmask
[1] = 0;
1997 mips_cprmask
[2] = 0;
1998 mips_cprmask
[3] = 0;
2000 /* set the default alignment for the text section (2**2) */
2001 record_alignment (text_section
, 2);
2003 bfd_set_gp_size (stdoutput
, g_switch_value
);
2008 /* On a native system other than VxWorks, sections must be aligned
2009 to 16 byte boundaries. When configured for an embedded ELF
2010 target, we don't bother. */
2011 if (strncmp (TARGET_OS
, "elf", 3) != 0
2012 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
2014 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
2015 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
2016 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
2019 /* Create a .reginfo section for register masks and a .mdebug
2020 section for debugging information. */
2028 subseg
= now_subseg
;
2030 /* The ABI says this section should be loaded so that the
2031 running program can access it. However, we don't load it
2032 if we are configured for an embedded target */
2033 flags
= SEC_READONLY
| SEC_DATA
;
2034 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2035 flags
|= SEC_ALLOC
| SEC_LOAD
;
2037 if (mips_abi
!= N64_ABI
)
2039 sec
= subseg_new (".reginfo", (subsegT
) 0);
2041 bfd_set_section_flags (stdoutput
, sec
, flags
);
2042 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2044 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2048 /* The 64-bit ABI uses a .MIPS.options section rather than
2049 .reginfo section. */
2050 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2051 bfd_set_section_flags (stdoutput
, sec
, flags
);
2052 bfd_set_section_alignment (stdoutput
, sec
, 3);
2054 /* Set up the option header. */
2056 Elf_Internal_Options opthdr
;
2059 opthdr
.kind
= ODK_REGINFO
;
2060 opthdr
.size
= (sizeof (Elf_External_Options
)
2061 + sizeof (Elf64_External_RegInfo
));
2064 f
= frag_more (sizeof (Elf_External_Options
));
2065 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2066 (Elf_External_Options
*) f
);
2068 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2072 if (ECOFF_DEBUGGING
)
2074 sec
= subseg_new (".mdebug", (subsegT
) 0);
2075 (void) bfd_set_section_flags (stdoutput
, sec
,
2076 SEC_HAS_CONTENTS
| SEC_READONLY
);
2077 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2079 else if (mips_flag_pdr
)
2081 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2082 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2083 SEC_READONLY
| SEC_RELOC
2085 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2088 subseg_set (seg
, subseg
);
2091 #endif /* OBJ_ELF */
2093 if (! ECOFF_DEBUGGING
)
2096 if (mips_fix_vr4120
)
2097 init_vr4120_conflicts ();
2103 if (! ECOFF_DEBUGGING
)
2108 md_assemble (char *str
)
2110 struct mips_cl_insn insn
;
2111 bfd_reloc_code_real_type unused_reloc
[3]
2112 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2114 imm_expr
.X_op
= O_absent
;
2115 imm2_expr
.X_op
= O_absent
;
2116 offset_expr
.X_op
= O_absent
;
2117 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2118 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2119 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2120 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2121 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2122 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2124 if (mips_opts
.mips16
)
2125 mips16_ip (str
, &insn
);
2128 mips_ip (str
, &insn
);
2129 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2130 str
, insn
.insn_opcode
));
2135 as_bad ("%s `%s'", insn_error
, str
);
2139 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2142 if (mips_opts
.mips16
)
2143 mips16_macro (&insn
);
2150 if (imm_expr
.X_op
!= O_absent
)
2151 append_insn (&insn
, &imm_expr
, imm_reloc
);
2152 else if (offset_expr
.X_op
!= O_absent
)
2153 append_insn (&insn
, &offset_expr
, offset_reloc
);
2155 append_insn (&insn
, NULL
, unused_reloc
);
2159 /* Convenience functions for abstracting away the differences between
2160 MIPS16 and non-MIPS16 relocations. */
2162 static inline bfd_boolean
2163 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2167 case BFD_RELOC_MIPS16_JMP
:
2168 case BFD_RELOC_MIPS16_GPREL
:
2169 case BFD_RELOC_MIPS16_GOT16
:
2170 case BFD_RELOC_MIPS16_CALL16
:
2171 case BFD_RELOC_MIPS16_HI16_S
:
2172 case BFD_RELOC_MIPS16_HI16
:
2173 case BFD_RELOC_MIPS16_LO16
:
2181 static inline bfd_boolean
2182 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2184 return reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
;
2187 static inline bfd_boolean
2188 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2190 return reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
;
2193 static inline bfd_boolean
2194 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2196 return reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
;
2199 /* Return true if the given relocation might need a matching %lo().
2200 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2201 need a matching %lo() when applied to local symbols. */
2203 static inline bfd_boolean
2204 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2206 return (HAVE_IN_PLACE_ADDENDS
2207 && (hi16_reloc_p (reloc
)
2208 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2209 all GOT16 relocations evaluate to "G". */
2210 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2213 /* Return the type of %lo() reloc needed by RELOC, given that
2214 reloc_needs_lo_p. */
2216 static inline bfd_reloc_code_real_type
2217 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2219 return mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
: BFD_RELOC_LO16
;
2222 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2225 static inline bfd_boolean
2226 fixup_has_matching_lo_p (fixS
*fixp
)
2228 return (fixp
->fx_next
!= NULL
2229 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2230 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2231 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2234 /* See whether instruction IP reads register REG. CLASS is the type
2238 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2239 enum mips_regclass regclass
)
2241 if (regclass
== MIPS16_REG
)
2243 gas_assert (mips_opts
.mips16
);
2244 reg
= mips16_to_32_reg_map
[reg
];
2245 regclass
= MIPS_GR_REG
;
2248 /* Don't report on general register ZERO, since it never changes. */
2249 if (regclass
== MIPS_GR_REG
&& reg
== ZERO
)
2252 if (regclass
== MIPS_FP_REG
)
2254 gas_assert (! mips_opts
.mips16
);
2255 /* If we are called with either $f0 or $f1, we must check $f0.
2256 This is not optimal, because it will introduce an unnecessary
2257 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2258 need to distinguish reading both $f0 and $f1 or just one of
2259 them. Note that we don't have to check the other way,
2260 because there is no instruction that sets both $f0 and $f1
2261 and requires a delay. */
2262 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2263 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2264 == (reg
&~ (unsigned) 1)))
2266 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2267 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2268 == (reg
&~ (unsigned) 1)))
2271 else if (! mips_opts
.mips16
)
2273 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2274 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2276 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2277 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2282 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2283 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2285 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2286 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2288 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2289 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2292 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2294 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2296 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2298 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2299 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2306 /* This function returns true if modifying a register requires a
2310 reg_needs_delay (unsigned int reg
)
2312 unsigned long prev_pinfo
;
2314 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2315 if (! mips_opts
.noreorder
2316 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2317 && ! gpr_interlocks
)
2318 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2319 && ! cop_interlocks
)))
2321 /* A load from a coprocessor or from memory. All load delays
2322 delay the use of general register rt for one instruction. */
2323 /* Itbl support may require additional care here. */
2324 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2325 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2332 /* Move all labels in insn_labels to the current insertion point. */
2335 mips_move_labels (void)
2337 segment_info_type
*si
= seg_info (now_seg
);
2338 struct insn_label_list
*l
;
2341 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2343 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2344 symbol_set_frag (l
->label
, frag_now
);
2345 val
= (valueT
) frag_now_fix ();
2346 /* mips16 text labels are stored as odd. */
2347 if (mips_opts
.mips16
)
2349 S_SET_VALUE (l
->label
, val
);
2354 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2356 bfd_boolean linkonce
= FALSE
;
2357 segT symseg
= S_GET_SEGMENT (sym
);
2359 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2361 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2364 /* The GNU toolchain uses an extension for ELF: a section
2365 beginning with the magic string .gnu.linkonce is a
2366 linkonce section. */
2367 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2368 sizeof ".gnu.linkonce" - 1) == 0)
2375 /* Mark instruction labels in mips16 mode. This permits the linker to
2376 handle them specially, such as generating jalx instructions when
2377 needed. We also make them odd for the duration of the assembly, in
2378 order to generate the right sort of code. We will make them even
2379 in the adjust_symtab routine, while leaving them marked. This is
2380 convenient for the debugger and the disassembler. The linker knows
2381 to make them odd again. */
2384 mips16_mark_labels (void)
2386 segment_info_type
*si
= seg_info (now_seg
);
2387 struct insn_label_list
*l
;
2389 if (!mips_opts
.mips16
)
2392 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2394 symbolS
*label
= l
->label
;
2396 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2398 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2400 if ((S_GET_VALUE (label
) & 1) == 0
2401 /* Don't adjust the address if the label is global or weak, or
2402 in a link-once section, since we'll be emitting symbol reloc
2403 references to it which will be patched up by the linker, and
2404 the final value of the symbol may or may not be MIPS16. */
2405 && ! S_IS_WEAK (label
)
2406 && ! S_IS_EXTERNAL (label
)
2407 && ! s_is_linkonce (label
, now_seg
))
2408 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2412 /* End the current frag. Make it a variant frag and record the
2416 relax_close_frag (void)
2418 mips_macro_warning
.first_frag
= frag_now
;
2419 frag_var (rs_machine_dependent
, 0, 0,
2420 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2421 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2423 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2424 mips_relax
.first_fixup
= 0;
2427 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2428 See the comment above RELAX_ENCODE for more details. */
2431 relax_start (symbolS
*symbol
)
2433 gas_assert (mips_relax
.sequence
== 0);
2434 mips_relax
.sequence
= 1;
2435 mips_relax
.symbol
= symbol
;
2438 /* Start generating the second version of a relaxable sequence.
2439 See the comment above RELAX_ENCODE for more details. */
2444 gas_assert (mips_relax
.sequence
== 1);
2445 mips_relax
.sequence
= 2;
2448 /* End the current relaxable sequence. */
2453 gas_assert (mips_relax
.sequence
== 2);
2454 relax_close_frag ();
2455 mips_relax
.sequence
= 0;
2458 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2459 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2460 by VR4120 errata. */
2463 classify_vr4120_insn (const char *name
)
2465 if (strncmp (name
, "macc", 4) == 0)
2466 return FIX_VR4120_MACC
;
2467 if (strncmp (name
, "dmacc", 5) == 0)
2468 return FIX_VR4120_DMACC
;
2469 if (strncmp (name
, "mult", 4) == 0)
2470 return FIX_VR4120_MULT
;
2471 if (strncmp (name
, "dmult", 5) == 0)
2472 return FIX_VR4120_DMULT
;
2473 if (strstr (name
, "div"))
2474 return FIX_VR4120_DIV
;
2475 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2476 return FIX_VR4120_MTHILO
;
2477 return NUM_FIX_VR4120_CLASSES
;
2480 #define INSN_ERET 0x42000018
2481 #define INSN_DERET 0x4200001f
2483 /* Return the number of instructions that must separate INSN1 and INSN2,
2484 where INSN1 is the earlier instruction. Return the worst-case value
2485 for any INSN2 if INSN2 is null. */
2488 insns_between (const struct mips_cl_insn
*insn1
,
2489 const struct mips_cl_insn
*insn2
)
2491 unsigned long pinfo1
, pinfo2
;
2493 /* This function needs to know which pinfo flags are set for INSN2
2494 and which registers INSN2 uses. The former is stored in PINFO2 and
2495 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2496 will have every flag set and INSN2_USES_REG will always return true. */
2497 pinfo1
= insn1
->insn_mo
->pinfo
;
2498 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2500 #define INSN2_USES_REG(REG, CLASS) \
2501 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2503 /* For most targets, write-after-read dependencies on the HI and LO
2504 registers must be separated by at least two instructions. */
2505 if (!hilo_interlocks
)
2507 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2509 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2513 /* If we're working around r7000 errata, there must be two instructions
2514 between an mfhi or mflo and any instruction that uses the result. */
2515 if (mips_7000_hilo_fix
2516 && MF_HILO_INSN (pinfo1
)
2517 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2520 /* If we're working around 24K errata, one instruction is required
2521 if an ERET or DERET is followed by a branch instruction. */
2524 if (insn1
->insn_opcode
== INSN_ERET
2525 || insn1
->insn_opcode
== INSN_DERET
)
2528 || insn2
->insn_opcode
== INSN_ERET
2529 || insn2
->insn_opcode
== INSN_DERET
2530 || (insn2
->insn_mo
->pinfo
2531 & (INSN_UNCOND_BRANCH_DELAY
2532 | INSN_COND_BRANCH_DELAY
2533 | INSN_COND_BRANCH_LIKELY
)) != 0)
2538 /* If working around VR4120 errata, check for combinations that need
2539 a single intervening instruction. */
2540 if (mips_fix_vr4120
)
2542 unsigned int class1
, class2
;
2544 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2545 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2549 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2550 if (vr4120_conflicts
[class1
] & (1 << class2
))
2555 if (!mips_opts
.mips16
)
2557 /* Check for GPR or coprocessor load delays. All such delays
2558 are on the RT register. */
2559 /* Itbl support may require additional care here. */
2560 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2561 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2563 know (pinfo1
& INSN_WRITE_GPR_T
);
2564 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2568 /* Check for generic coprocessor hazards.
2570 This case is not handled very well. There is no special
2571 knowledge of CP0 handling, and the coprocessors other than
2572 the floating point unit are not distinguished at all. */
2573 /* Itbl support may require additional care here. FIXME!
2574 Need to modify this to include knowledge about
2575 user specified delays! */
2576 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2577 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2579 /* Handle cases where INSN1 writes to a known general coprocessor
2580 register. There must be a one instruction delay before INSN2
2581 if INSN2 reads that register, otherwise no delay is needed. */
2582 if (pinfo1
& INSN_WRITE_FPR_T
)
2584 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2587 else if (pinfo1
& INSN_WRITE_FPR_S
)
2589 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2594 /* Read-after-write dependencies on the control registers
2595 require a two-instruction gap. */
2596 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2597 && (pinfo2
& INSN_READ_COND_CODE
))
2600 /* We don't know exactly what INSN1 does. If INSN2 is
2601 also a coprocessor instruction, assume there must be
2602 a one instruction gap. */
2603 if (pinfo2
& INSN_COP
)
2608 /* Check for read-after-write dependencies on the coprocessor
2609 control registers in cases where INSN1 does not need a general
2610 coprocessor delay. This means that INSN1 is a floating point
2611 comparison instruction. */
2612 /* Itbl support may require additional care here. */
2613 else if (!cop_interlocks
2614 && (pinfo1
& INSN_WRITE_COND_CODE
)
2615 && (pinfo2
& INSN_READ_COND_CODE
))
2619 #undef INSN2_USES_REG
2624 /* Return the number of nops that would be needed to work around the
2625 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2626 the MAX_VR4130_NOPS instructions described by HIST. */
2629 nops_for_vr4130 (const struct mips_cl_insn
*hist
,
2630 const struct mips_cl_insn
*insn
)
2634 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2635 are not affected by the errata. */
2637 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2638 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2639 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2642 /* Search for the first MFLO or MFHI. */
2643 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2644 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
2646 /* Extract the destination register. */
2647 if (mips_opts
.mips16
)
2648 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, hist
[i
])];
2650 reg
= EXTRACT_OPERAND (RD
, hist
[i
]);
2652 /* No nops are needed if INSN reads that register. */
2653 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2656 /* ...or if any of the intervening instructions do. */
2657 for (j
= 0; j
< i
; j
++)
2658 if (insn_uses_reg (&hist
[j
], reg
, MIPS_GR_REG
))
2661 return MAX_VR4130_NOPS
- i
;
2666 /* Return the number of nops that would be needed if instruction INSN
2667 immediately followed the MAX_NOPS instructions given by HIST,
2668 where HIST[0] is the most recent instruction. If INSN is null,
2669 return the worse-case number of nops for any instruction. */
2672 nops_for_insn (const struct mips_cl_insn
*hist
,
2673 const struct mips_cl_insn
*insn
)
2675 int i
, nops
, tmp_nops
;
2678 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2680 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
2681 if (tmp_nops
> nops
)
2685 if (mips_fix_vr4130
)
2687 tmp_nops
= nops_for_vr4130 (hist
, insn
);
2688 if (tmp_nops
> nops
)
2695 /* The variable arguments provide NUM_INSNS extra instructions that
2696 might be added to HIST. Return the largest number of nops that
2697 would be needed after the extended sequence. */
2700 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*hist
, ...)
2703 struct mips_cl_insn buffer
[MAX_NOPS
];
2704 struct mips_cl_insn
*cursor
;
2707 va_start (args
, hist
);
2708 cursor
= buffer
+ num_insns
;
2709 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2710 while (cursor
> buffer
)
2711 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2713 nops
= nops_for_insn (buffer
, NULL
);
2718 /* Like nops_for_insn, but if INSN is a branch, take into account the
2719 worst-case delay for the branch target. */
2722 nops_for_insn_or_target (const struct mips_cl_insn
*hist
,
2723 const struct mips_cl_insn
*insn
)
2727 nops
= nops_for_insn (hist
, insn
);
2728 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2729 | INSN_COND_BRANCH_DELAY
2730 | INSN_COND_BRANCH_LIKELY
))
2732 tmp_nops
= nops_for_sequence (2, hist
, insn
, NOP_INSN
);
2733 if (tmp_nops
> nops
)
2736 else if (mips_opts
.mips16
2737 && (insn
->insn_mo
->pinfo
& (MIPS16_INSN_UNCOND_BRANCH
2738 | MIPS16_INSN_COND_BRANCH
)))
2740 tmp_nops
= nops_for_sequence (1, hist
, insn
);
2741 if (tmp_nops
> nops
)
2747 /* Fix NOP issue: Replace nops by "or at,at,zero". */
2750 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
2752 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
2753 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
2756 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
2757 jr target pc &= 'hffff_ffff_cfff_ffff. */
2760 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
2762 if (strcmp (ip
->insn_mo
->name
, "j") == 0
2763 || strcmp (ip
->insn_mo
->name
, "jr") == 0
2764 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
2772 sreg
= EXTRACT_OPERAND (RS
, *ip
);
2773 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
2776 ep
.X_op
= O_constant
;
2777 ep
.X_add_number
= 0xcfff0000;
2778 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
2779 ep
.X_add_number
= 0xffff;
2780 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
2781 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
2786 fix_loongson2f (struct mips_cl_insn
* ip
)
2788 if (mips_fix_loongson2f_nop
)
2789 fix_loongson2f_nop (ip
);
2791 if (mips_fix_loongson2f_jump
)
2792 fix_loongson2f_jump (ip
);
2795 /* Output an instruction. IP is the instruction information.
2796 ADDRESS_EXPR is an operand of the instruction to be used with
2800 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2801 bfd_reloc_code_real_type
*reloc_type
)
2803 unsigned long prev_pinfo
, pinfo
;
2804 relax_stateT prev_insn_frag_type
= 0;
2805 bfd_boolean relaxed_branch
= FALSE
;
2806 segment_info_type
*si
= seg_info (now_seg
);
2808 if (mips_fix_loongson2f
)
2809 fix_loongson2f (ip
);
2811 /* Mark instruction labels in mips16 mode. */
2812 mips16_mark_labels ();
2814 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2815 pinfo
= ip
->insn_mo
->pinfo
;
2817 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2819 /* There are a lot of optimizations we could do that we don't.
2820 In particular, we do not, in general, reorder instructions.
2821 If you use gcc with optimization, it will reorder
2822 instructions and generally do much more optimization then we
2823 do here; repeating all that work in the assembler would only
2824 benefit hand written assembly code, and does not seem worth
2826 int nops
= (mips_optimize
== 0
2827 ? nops_for_insn (history
, NULL
)
2828 : nops_for_insn_or_target (history
, ip
));
2832 unsigned long old_frag_offset
;
2835 old_frag
= frag_now
;
2836 old_frag_offset
= frag_now_fix ();
2838 for (i
= 0; i
< nops
; i
++)
2843 listing_prev_line ();
2844 /* We may be at the start of a variant frag. In case we
2845 are, make sure there is enough space for the frag
2846 after the frags created by listing_prev_line. The
2847 argument to frag_grow here must be at least as large
2848 as the argument to all other calls to frag_grow in
2849 this file. We don't have to worry about being in the
2850 middle of a variant frag, because the variants insert
2851 all needed nop instructions themselves. */
2855 mips_move_labels ();
2857 #ifndef NO_ECOFF_DEBUGGING
2858 if (ECOFF_DEBUGGING
)
2859 ecoff_fix_loc (old_frag
, old_frag_offset
);
2863 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2865 /* Work out how many nops in prev_nop_frag are needed by IP. */
2866 int nops
= nops_for_insn_or_target (history
, ip
);
2867 gas_assert (nops
<= prev_nop_frag_holds
);
2869 /* Enforce NOPS as a minimum. */
2870 if (nops
> prev_nop_frag_required
)
2871 prev_nop_frag_required
= nops
;
2873 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2875 /* Settle for the current number of nops. Update the history
2876 accordingly (for the benefit of any future .set reorder code). */
2877 prev_nop_frag
= NULL
;
2878 insert_into_history (prev_nop_frag_since
,
2879 prev_nop_frag_holds
, NOP_INSN
);
2883 /* Allow this instruction to replace one of the nops that was
2884 tentatively added to prev_nop_frag. */
2885 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2886 prev_nop_frag_holds
--;
2887 prev_nop_frag_since
++;
2892 /* The value passed to dwarf2_emit_insn is the distance between
2893 the beginning of the current instruction and the address that
2894 should be recorded in the debug tables. For MIPS16 debug info
2895 we want to use ISA-encoded addresses, so we pass -1 for an
2896 address higher by one than the current. */
2897 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2900 /* Record the frag type before frag_var. */
2901 if (history
[0].frag
)
2902 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2905 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2906 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2907 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2908 && mips_relax_branch
2909 /* Don't try branch relaxation within .set nomacro, or within
2910 .set noat if we use $at for PIC computations. If it turns
2911 out that the branch was out-of-range, we'll get an error. */
2912 && !mips_opts
.warn_about_macros
2913 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2914 && !mips_opts
.mips16
)
2916 relaxed_branch
= TRUE
;
2917 add_relaxed_insn (ip
, (relaxed_branch_length
2919 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2920 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2923 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2924 pinfo
& INSN_COND_BRANCH_LIKELY
,
2925 pinfo
& INSN_WRITE_GPR_31
,
2927 address_expr
->X_add_symbol
,
2928 address_expr
->X_add_number
);
2929 *reloc_type
= BFD_RELOC_UNUSED
;
2931 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2933 /* We need to set up a variant frag. */
2934 gas_assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2935 add_relaxed_insn (ip
, 4, 0,
2937 (*reloc_type
- BFD_RELOC_UNUSED
,
2938 mips16_small
, mips16_ext
,
2939 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2940 history
[0].mips16_absolute_jump_p
),
2941 make_expr_symbol (address_expr
), 0);
2943 else if (mips_opts
.mips16
2945 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2947 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2948 /* Make sure there is enough room to swap this instruction with
2949 a following jump instruction. */
2951 add_fixed_insn (ip
);
2955 if (mips_opts
.mips16
2956 && mips_opts
.noreorder
2957 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2958 as_warn (_("extended instruction in delay slot"));
2960 if (mips_relax
.sequence
)
2962 /* If we've reached the end of this frag, turn it into a variant
2963 frag and record the information for the instructions we've
2965 if (frag_room () < 4)
2966 relax_close_frag ();
2967 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2970 if (mips_relax
.sequence
!= 2)
2971 mips_macro_warning
.sizes
[0] += 4;
2972 if (mips_relax
.sequence
!= 1)
2973 mips_macro_warning
.sizes
[1] += 4;
2975 if (mips_opts
.mips16
)
2978 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2980 add_fixed_insn (ip
);
2983 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2985 if (address_expr
->X_op
== O_constant
)
2989 switch (*reloc_type
)
2992 ip
->insn_opcode
|= address_expr
->X_add_number
;
2995 case BFD_RELOC_MIPS_HIGHEST
:
2996 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2997 ip
->insn_opcode
|= tmp
& 0xffff;
3000 case BFD_RELOC_MIPS_HIGHER
:
3001 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
3002 ip
->insn_opcode
|= tmp
& 0xffff;
3005 case BFD_RELOC_HI16_S
:
3006 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
3007 ip
->insn_opcode
|= tmp
& 0xffff;
3010 case BFD_RELOC_HI16
:
3011 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
3014 case BFD_RELOC_UNUSED
:
3015 case BFD_RELOC_LO16
:
3016 case BFD_RELOC_MIPS_GOT_DISP
:
3017 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
3020 case BFD_RELOC_MIPS_JMP
:
3021 if ((address_expr
->X_add_number
& 3) != 0)
3022 as_bad (_("jump to misaligned address (0x%lx)"),
3023 (unsigned long) address_expr
->X_add_number
);
3024 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
3027 case BFD_RELOC_MIPS16_JMP
:
3028 if ((address_expr
->X_add_number
& 3) != 0)
3029 as_bad (_("jump to misaligned address (0x%lx)"),
3030 (unsigned long) address_expr
->X_add_number
);
3032 (((address_expr
->X_add_number
& 0x7c0000) << 3)
3033 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
3034 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
3037 case BFD_RELOC_16_PCREL_S2
:
3038 if ((address_expr
->X_add_number
& 3) != 0)
3039 as_bad (_("branch to misaligned address (0x%lx)"),
3040 (unsigned long) address_expr
->X_add_number
);
3041 if (mips_relax_branch
)
3043 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
3044 as_bad (_("branch address range overflow (0x%lx)"),
3045 (unsigned long) address_expr
->X_add_number
);
3046 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
3053 else if (*reloc_type
< BFD_RELOC_UNUSED
)
3056 reloc_howto_type
*howto
;
3059 /* In a compound relocation, it is the final (outermost)
3060 operator that determines the relocated field. */
3061 for (i
= 1; i
< 3; i
++)
3062 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
3065 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
3068 /* To reproduce this failure try assembling gas/testsuites/
3069 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3071 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type
[i
- 1]);
3072 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
3075 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
3076 bfd_get_reloc_size (howto
),
3078 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
3081 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3082 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
3083 && ip
->fixp
[0]->fx_addsy
)
3084 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
3086 /* These relocations can have an addend that won't fit in
3087 4 octets for 64bit assembly. */
3089 && ! howto
->partial_inplace
3090 && (reloc_type
[0] == BFD_RELOC_16
3091 || reloc_type
[0] == BFD_RELOC_32
3092 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
3093 || reloc_type
[0] == BFD_RELOC_GPREL16
3094 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
3095 || reloc_type
[0] == BFD_RELOC_GPREL32
3096 || reloc_type
[0] == BFD_RELOC_64
3097 || reloc_type
[0] == BFD_RELOC_CTOR
3098 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
3099 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
3100 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
3101 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
3102 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
3103 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
3104 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
3105 || hi16_reloc_p (reloc_type
[0])
3106 || lo16_reloc_p (reloc_type
[0])))
3107 ip
->fixp
[0]->fx_no_overflow
= 1;
3109 if (mips_relax
.sequence
)
3111 if (mips_relax
.first_fixup
== 0)
3112 mips_relax
.first_fixup
= ip
->fixp
[0];
3114 else if (reloc_needs_lo_p (*reloc_type
))
3116 struct mips_hi_fixup
*hi_fixup
;
3118 /* Reuse the last entry if it already has a matching %lo. */
3119 hi_fixup
= mips_hi_fixup_list
;
3121 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
3123 hi_fixup
= ((struct mips_hi_fixup
*)
3124 xmalloc (sizeof (struct mips_hi_fixup
)));
3125 hi_fixup
->next
= mips_hi_fixup_list
;
3126 mips_hi_fixup_list
= hi_fixup
;
3128 hi_fixup
->fixp
= ip
->fixp
[0];
3129 hi_fixup
->seg
= now_seg
;
3132 /* Add fixups for the second and third relocations, if given.
3133 Note that the ABI allows the second relocation to be
3134 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3135 moment we only use RSS_UNDEF, but we could add support
3136 for the others if it ever becomes necessary. */
3137 for (i
= 1; i
< 3; i
++)
3138 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
3140 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
3141 ip
->fixp
[0]->fx_size
, NULL
, 0,
3142 FALSE
, reloc_type
[i
]);
3144 /* Use fx_tcbit to mark compound relocs. */
3145 ip
->fixp
[0]->fx_tcbit
= 1;
3146 ip
->fixp
[i
]->fx_tcbit
= 1;
3152 /* Update the register mask information. */
3153 if (! mips_opts
.mips16
)
3155 if (pinfo
& INSN_WRITE_GPR_D
)
3156 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
3157 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
3158 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
3159 if (pinfo
& INSN_READ_GPR_S
)
3160 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
3161 if (pinfo
& INSN_WRITE_GPR_31
)
3162 mips_gprmask
|= 1 << RA
;
3163 if (pinfo
& INSN_WRITE_FPR_D
)
3164 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
3165 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
3166 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
3167 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
3168 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
3169 if ((pinfo
& INSN_READ_FPR_R
) != 0)
3170 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
3171 if (pinfo
& INSN_COP
)
3173 /* We don't keep enough information to sort these cases out.
3174 The itbl support does keep this information however, although
3175 we currently don't support itbl fprmats as part of the cop
3176 instruction. May want to add this support in the future. */
3178 /* Never set the bit for $0, which is always zero. */
3179 mips_gprmask
&= ~1 << 0;
3183 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3184 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3185 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3186 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3187 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3188 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3189 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3190 mips_gprmask
|= 1 << TREG
;
3191 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3192 mips_gprmask
|= 1 << SP
;
3193 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3194 mips_gprmask
|= 1 << RA
;
3195 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3196 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3197 if (pinfo
& MIPS16_INSN_READ_Z
)
3198 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3199 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3200 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3203 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3205 /* Filling the branch delay slot is more complex. We try to
3206 switch the branch with the previous instruction, which we can
3207 do if the previous instruction does not set up a condition
3208 that the branch tests and if the branch is not itself the
3209 target of any branch. */
3210 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3211 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3213 if (mips_optimize
< 2
3214 /* If we have seen .set volatile or .set nomove, don't
3216 || mips_opts
.nomove
!= 0
3217 /* We can't swap if the previous instruction's position
3219 || history
[0].fixed_p
3220 /* If the previous previous insn was in a .set
3221 noreorder, we can't swap. Actually, the MIPS
3222 assembler will swap in this situation. However, gcc
3223 configured -with-gnu-as will generate code like
3229 in which we can not swap the bne and INSN. If gcc is
3230 not configured -with-gnu-as, it does not output the
3232 || history
[1].noreorder_p
3233 /* If the branch is itself the target of a branch, we
3234 can not swap. We cheat on this; all we check for is
3235 whether there is a label on this instruction. If
3236 there are any branches to anything other than a
3237 label, users must use .set noreorder. */
3238 || si
->label_list
!= NULL
3239 /* If the previous instruction is in a variant frag
3240 other than this branch's one, we cannot do the swap.
3241 This does not apply to the mips16, which uses variant
3242 frags for different purposes. */
3243 || (! mips_opts
.mips16
3244 && prev_insn_frag_type
== rs_machine_dependent
)
3245 /* Check for conflicts between the branch and the instructions
3246 before the candidate delay slot. */
3247 || nops_for_insn (history
+ 1, ip
) > 0
3248 /* Check for conflicts between the swapped sequence and the
3249 target of the branch. */
3250 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
3251 /* We do not swap with a trap instruction, since it
3252 complicates trap handlers to have the trap
3253 instruction be in a delay slot. */
3254 || (prev_pinfo
& INSN_TRAP
)
3255 /* If the branch reads a register that the previous
3256 instruction sets, we can not swap. */
3257 || (! mips_opts
.mips16
3258 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3259 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3261 || (! mips_opts
.mips16
3262 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3263 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3265 || (mips_opts
.mips16
3266 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3268 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3270 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3272 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3274 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3276 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3278 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3279 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3280 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3281 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3282 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3283 && insn_uses_reg (ip
,
3284 MIPS16OP_EXTRACT_REG32R
3285 (history
[0].insn_opcode
),
3287 /* If the branch writes a register that the previous
3288 instruction sets, we can not swap (we know that
3289 branches write only to RD or to $31). */
3290 || (! mips_opts
.mips16
3291 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3292 && (((pinfo
& INSN_WRITE_GPR_D
)
3293 && (EXTRACT_OPERAND (RT
, history
[0])
3294 == EXTRACT_OPERAND (RD
, *ip
)))
3295 || ((pinfo
& INSN_WRITE_GPR_31
)
3296 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3297 || (! mips_opts
.mips16
3298 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3299 && (((pinfo
& INSN_WRITE_GPR_D
)
3300 && (EXTRACT_OPERAND (RD
, history
[0])
3301 == EXTRACT_OPERAND (RD
, *ip
)))
3302 || ((pinfo
& INSN_WRITE_GPR_31
)
3303 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3304 || (mips_opts
.mips16
3305 && (pinfo
& MIPS16_INSN_WRITE_31
)
3306 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3307 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3308 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3310 /* If the branch writes a register that the previous
3311 instruction reads, we can not swap (we know that
3312 branches only write to RD or to $31). */
3313 || (! mips_opts
.mips16
3314 && (pinfo
& INSN_WRITE_GPR_D
)
3315 && insn_uses_reg (&history
[0],
3316 EXTRACT_OPERAND (RD
, *ip
),
3318 || (! mips_opts
.mips16
3319 && (pinfo
& INSN_WRITE_GPR_31
)
3320 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3321 || (mips_opts
.mips16
3322 && (pinfo
& MIPS16_INSN_WRITE_31
)
3323 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3324 /* If one instruction sets a condition code and the
3325 other one uses a condition code, we can not swap. */
3326 || ((pinfo
& INSN_READ_COND_CODE
)
3327 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3328 || ((pinfo
& INSN_WRITE_COND_CODE
)
3329 && (prev_pinfo
& INSN_READ_COND_CODE
))
3330 /* If the previous instruction uses the PC, we can not
3332 || (mips_opts
.mips16
3333 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3334 /* If the previous instruction had a fixup in mips16
3335 mode, we can not swap. This normally means that the
3336 previous instruction was a 4 byte branch anyhow. */
3337 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3338 /* If the previous instruction is a sync, sync.l, or
3339 sync.p, we can not swap. */
3340 || (prev_pinfo
& INSN_SYNC
)
3341 /* If the previous instruction is an ERET or
3342 DERET, avoid the swap. */
3343 || (history
[0].insn_opcode
== INSN_ERET
)
3344 || (history
[0].insn_opcode
== INSN_DERET
))
3346 if (mips_opts
.mips16
3347 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3348 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3349 && ISA_SUPPORTS_MIPS16E
)
3351 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3352 ip
->insn_opcode
|= 0x0080;
3354 insert_into_history (0, 1, ip
);
3358 /* We could do even better for unconditional branches to
3359 portions of this object file; we could pick up the
3360 instruction at the destination, put it in the delay
3361 slot, and bump the destination address. */
3362 insert_into_history (0, 1, ip
);
3366 if (mips_relax
.sequence
)
3367 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3371 /* It looks like we can actually do the swap. */
3372 struct mips_cl_insn delay
= history
[0];
3373 if (mips_opts
.mips16
)
3375 know (delay
.frag
== ip
->frag
);
3376 move_insn (ip
, delay
.frag
, delay
.where
);
3377 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3379 else if (relaxed_branch
)
3381 /* Add the delay slot instruction to the end of the
3382 current frag and shrink the fixed part of the
3383 original frag. If the branch occupies the tail of
3384 the latter, move it backwards to cover the gap. */
3385 delay
.frag
->fr_fix
-= 4;
3386 if (delay
.frag
== ip
->frag
)
3387 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3388 add_fixed_insn (&delay
);
3392 move_insn (&delay
, ip
->frag
, ip
->where
);
3393 move_insn (ip
, history
[0].frag
, history
[0].where
);
3397 insert_into_history (0, 1, &delay
);
3400 /* If that was an unconditional branch, forget the previous
3401 insn information. */
3402 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3404 mips_no_prev_insn ();
3407 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3409 /* We don't yet optimize a branch likely. What we should do
3410 is look at the target, copy the instruction found there
3411 into the delay slot, and increment the branch to jump to
3412 the next instruction. */
3413 insert_into_history (0, 1, ip
);
3417 insert_into_history (0, 1, ip
);
3420 insert_into_history (0, 1, ip
);
3422 /* We just output an insn, so the next one doesn't have a label. */
3423 mips_clear_insn_labels ();
3426 /* Forget that there was any previous instruction or label. */
3429 mips_no_prev_insn (void)
3431 prev_nop_frag
= NULL
;
3432 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3433 mips_clear_insn_labels ();
3436 /* This function must be called before we emit something other than
3437 instructions. It is like mips_no_prev_insn except that it inserts
3438 any NOPS that might be needed by previous instructions. */
3441 mips_emit_delays (void)
3443 if (! mips_opts
.noreorder
)
3445 int nops
= nops_for_insn (history
, NULL
);
3449 add_fixed_insn (NOP_INSN
);
3450 mips_move_labels ();
3453 mips_no_prev_insn ();
3456 /* Start a (possibly nested) noreorder block. */
3459 start_noreorder (void)
3461 if (mips_opts
.noreorder
== 0)
3466 /* None of the instructions before the .set noreorder can be moved. */
3467 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3468 history
[i
].fixed_p
= 1;
3470 /* Insert any nops that might be needed between the .set noreorder
3471 block and the previous instructions. We will later remove any
3472 nops that turn out not to be needed. */
3473 nops
= nops_for_insn (history
, NULL
);
3476 if (mips_optimize
!= 0)
3478 /* Record the frag which holds the nop instructions, so
3479 that we can remove them if we don't need them. */
3480 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3481 prev_nop_frag
= frag_now
;
3482 prev_nop_frag_holds
= nops
;
3483 prev_nop_frag_required
= 0;
3484 prev_nop_frag_since
= 0;
3487 for (; nops
> 0; --nops
)
3488 add_fixed_insn (NOP_INSN
);
3490 /* Move on to a new frag, so that it is safe to simply
3491 decrease the size of prev_nop_frag. */
3492 frag_wane (frag_now
);
3494 mips_move_labels ();
3496 mips16_mark_labels ();
3497 mips_clear_insn_labels ();
3499 mips_opts
.noreorder
++;
3500 mips_any_noreorder
= 1;
3503 /* End a nested noreorder block. */
3506 end_noreorder (void)
3509 mips_opts
.noreorder
--;
3510 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3512 /* Commit to inserting prev_nop_frag_required nops and go back to
3513 handling nop insertion the .set reorder way. */
3514 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3515 * (mips_opts
.mips16
? 2 : 4));
3516 insert_into_history (prev_nop_frag_since
,
3517 prev_nop_frag_required
, NOP_INSN
);
3518 prev_nop_frag
= NULL
;
3522 /* Set up global variables for the start of a new macro. */
3527 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3528 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3529 && (history
[0].insn_mo
->pinfo
3530 & (INSN_UNCOND_BRANCH_DELAY
3531 | INSN_COND_BRANCH_DELAY
3532 | INSN_COND_BRANCH_LIKELY
)) != 0);
3535 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3536 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3537 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3540 macro_warning (relax_substateT subtype
)
3542 if (subtype
& RELAX_DELAY_SLOT
)
3543 return _("Macro instruction expanded into multiple instructions"
3544 " in a branch delay slot");
3545 else if (subtype
& RELAX_NOMACRO
)
3546 return _("Macro instruction expanded into multiple instructions");
3551 /* Finish up a macro. Emit warnings as appropriate. */
3556 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3558 relax_substateT subtype
;
3560 /* Set up the relaxation warning flags. */
3562 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3563 subtype
|= RELAX_SECOND_LONGER
;
3564 if (mips_opts
.warn_about_macros
)
3565 subtype
|= RELAX_NOMACRO
;
3566 if (mips_macro_warning
.delay_slot_p
)
3567 subtype
|= RELAX_DELAY_SLOT
;
3569 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3571 /* Either the macro has a single implementation or both
3572 implementations are longer than 4 bytes. Emit the
3574 const char *msg
= macro_warning (subtype
);
3576 as_warn ("%s", msg
);
3580 /* One implementation might need a warning but the other
3581 definitely doesn't. */
3582 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3587 /* Read a macro's relocation codes from *ARGS and store them in *R.
3588 The first argument in *ARGS will be either the code for a single
3589 relocation or -1 followed by the three codes that make up a
3590 composite relocation. */
3593 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3597 next
= va_arg (*args
, int);
3599 r
[0] = (bfd_reloc_code_real_type
) next
;
3601 for (i
= 0; i
< 3; i
++)
3602 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3605 /* Build an instruction created by a macro expansion. This is passed
3606 a pointer to the count of instructions created so far, an
3607 expression, the name of the instruction to build, an operand format
3608 string, and corresponding arguments. */
3611 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3613 const struct mips_opcode
*mo
;
3614 struct mips_cl_insn insn
;
3615 bfd_reloc_code_real_type r
[3];
3618 va_start (args
, fmt
);
3620 if (mips_opts
.mips16
)
3622 mips16_macro_build (ep
, name
, fmt
, &args
);
3627 r
[0] = BFD_RELOC_UNUSED
;
3628 r
[1] = BFD_RELOC_UNUSED
;
3629 r
[2] = BFD_RELOC_UNUSED
;
3630 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3632 gas_assert (strcmp (name
, mo
->name
) == 0);
3636 /* Search until we get a match for NAME. It is assumed here that
3637 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3638 if (strcmp (fmt
, mo
->args
) == 0
3639 && mo
->pinfo
!= INSN_MACRO
3640 && is_opcode_valid (mo
))
3644 gas_assert (mo
->name
);
3645 gas_assert (strcmp (name
, mo
->name
) == 0);
3648 create_insn (&insn
, mo
);
3666 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3671 /* Note that in the macro case, these arguments are already
3672 in MSB form. (When handling the instruction in the
3673 non-macro case, these arguments are sizes from which
3674 MSB values must be calculated.) */
3675 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3681 /* Note that in the macro case, these arguments are already
3682 in MSBD form. (When handling the instruction in the
3683 non-macro case, these arguments are sizes from which
3684 MSBD values must be calculated.) */
3685 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3689 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3698 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3704 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3708 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3713 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3719 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3724 int tmp
= va_arg (args
, int);
3726 INSERT_OPERAND (RT
, insn
, tmp
);
3727 INSERT_OPERAND (RD
, insn
, tmp
);
3733 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3740 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3744 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3748 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3752 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3756 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3763 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3769 macro_read_relocs (&args
, r
);
3770 gas_assert (*r
== BFD_RELOC_GPREL16
3771 || *r
== BFD_RELOC_MIPS_LITERAL
3772 || *r
== BFD_RELOC_MIPS_HIGHER
3773 || *r
== BFD_RELOC_HI16_S
3774 || *r
== BFD_RELOC_LO16
3775 || *r
== BFD_RELOC_MIPS_GOT16
3776 || *r
== BFD_RELOC_MIPS_CALL16
3777 || *r
== BFD_RELOC_MIPS_GOT_DISP
3778 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3779 || *r
== BFD_RELOC_MIPS_GOT_OFST
3780 || *r
== BFD_RELOC_MIPS_GOT_LO16
3781 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3785 macro_read_relocs (&args
, r
);
3786 gas_assert (ep
!= NULL
3787 && (ep
->X_op
== O_constant
3788 || (ep
->X_op
== O_symbol
3789 && (*r
== BFD_RELOC_MIPS_HIGHEST
3790 || *r
== BFD_RELOC_HI16_S
3791 || *r
== BFD_RELOC_HI16
3792 || *r
== BFD_RELOC_GPREL16
3793 || *r
== BFD_RELOC_MIPS_GOT_HI16
3794 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3798 gas_assert (ep
!= NULL
);
3801 * This allows macro() to pass an immediate expression for
3802 * creating short branches without creating a symbol.
3804 * We don't allow branch relaxation for these branches, as
3805 * they should only appear in ".set nomacro" anyway.
3807 if (ep
->X_op
== O_constant
)
3809 if ((ep
->X_add_number
& 3) != 0)
3810 as_bad (_("branch to misaligned address (0x%lx)"),
3811 (unsigned long) ep
->X_add_number
);
3812 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3813 as_bad (_("branch address range overflow (0x%lx)"),
3814 (unsigned long) ep
->X_add_number
);
3815 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3819 *r
= BFD_RELOC_16_PCREL_S2
;
3823 gas_assert (ep
!= NULL
);
3824 *r
= BFD_RELOC_MIPS_JMP
;
3828 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3832 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3841 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3843 append_insn (&insn
, ep
, r
);
3847 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3850 struct mips_opcode
*mo
;
3851 struct mips_cl_insn insn
;
3852 bfd_reloc_code_real_type r
[3]
3853 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3855 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3857 gas_assert (strcmp (name
, mo
->name
) == 0);
3859 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3862 gas_assert (mo
->name
);
3863 gas_assert (strcmp (name
, mo
->name
) == 0);
3866 create_insn (&insn
, mo
);
3884 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (*args
, int));
3889 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (*args
, int));
3893 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (*args
, int));
3897 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (*args
, int));
3907 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (*args
, int));
3914 regno
= va_arg (*args
, int);
3915 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3916 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3937 gas_assert (ep
!= NULL
);
3939 if (ep
->X_op
!= O_constant
)
3940 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3943 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3944 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3947 *r
= BFD_RELOC_UNUSED
;
3953 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (*args
, int));
3960 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3962 append_insn (&insn
, ep
, r
);
3966 * Sign-extend 32-bit mode constants that have bit 31 set and all
3967 * higher bits unset.
3970 normalize_constant_expr (expressionS
*ex
)
3972 if (ex
->X_op
== O_constant
3973 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3974 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3979 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3980 * all higher bits unset.
3983 normalize_address_expr (expressionS
*ex
)
3985 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3986 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3987 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3988 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3993 * Generate a "jalr" instruction with a relocation hint to the called
3994 * function. This occurs in NewABI PIC code.
3997 macro_build_jalr (expressionS
*ep
)
4001 if (MIPS_JALR_HINT_P (ep
))
4006 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
4007 if (MIPS_JALR_HINT_P (ep
))
4008 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
4009 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
4013 * Generate a "lui" instruction.
4016 macro_build_lui (expressionS
*ep
, int regnum
)
4018 expressionS high_expr
;
4019 const struct mips_opcode
*mo
;
4020 struct mips_cl_insn insn
;
4021 bfd_reloc_code_real_type r
[3]
4022 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4023 const char *name
= "lui";
4024 const char *fmt
= "t,u";
4026 gas_assert (! mips_opts
.mips16
);
4030 if (high_expr
.X_op
== O_constant
)
4032 /* We can compute the instruction now without a relocation entry. */
4033 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
4035 *r
= BFD_RELOC_UNUSED
;
4039 gas_assert (ep
->X_op
== O_symbol
);
4040 /* _gp_disp is a special case, used from s_cpload.
4041 __gnu_local_gp is used if mips_no_shared. */
4042 gas_assert (mips_pic
== NO_PIC
4044 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
4045 || (! mips_in_shared
4046 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
4047 "__gnu_local_gp") == 0));
4048 *r
= BFD_RELOC_HI16_S
;
4051 mo
= hash_find (op_hash
, name
);
4052 gas_assert (strcmp (name
, mo
->name
) == 0);
4053 gas_assert (strcmp (fmt
, mo
->args
) == 0);
4054 create_insn (&insn
, mo
);
4056 insn
.insn_opcode
= insn
.insn_mo
->match
;
4057 INSERT_OPERAND (RT
, insn
, regnum
);
4058 if (*r
== BFD_RELOC_UNUSED
)
4060 insn
.insn_opcode
|= high_expr
.X_add_number
;
4061 append_insn (&insn
, NULL
, r
);
4064 append_insn (&insn
, &high_expr
, r
);
4067 /* Generate a sequence of instructions to do a load or store from a constant
4068 offset off of a base register (breg) into/from a target register (treg),
4069 using AT if necessary. */
4071 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
4072 int treg
, int breg
, int dbl
)
4074 gas_assert (ep
->X_op
== O_constant
);
4076 /* Sign-extending 32-bit constants makes their handling easier. */
4078 normalize_constant_expr (ep
);
4080 /* Right now, this routine can only handle signed 32-bit constants. */
4081 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
4082 as_warn (_("operand overflow"));
4084 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
4086 /* Signed 16-bit offset will fit in the op. Easy! */
4087 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
4091 /* 32-bit offset, need multiple instructions and AT, like:
4092 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4093 addu $tempreg,$tempreg,$breg
4094 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4095 to handle the complete offset. */
4096 macro_build_lui (ep
, AT
);
4097 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
4098 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
4101 as_bad (_("Macro used $at after \".set noat\""));
4106 * Generates code to set the $at register to true (one)
4107 * if reg is less than the immediate expression.
4110 set_at (int reg
, int unsignedp
)
4112 if (imm_expr
.X_op
== O_constant
4113 && imm_expr
.X_add_number
>= -0x8000
4114 && imm_expr
.X_add_number
< 0x8000)
4115 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
4116 AT
, reg
, BFD_RELOC_LO16
);
4119 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4120 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
4124 /* Warn if an expression is not a constant. */
4127 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
4129 if (ex
->X_op
== O_big
)
4130 as_bad (_("unsupported large constant"));
4131 else if (ex
->X_op
!= O_constant
)
4132 as_bad (_("Instruction %s requires absolute expression"),
4135 if (HAVE_32BIT_GPRS
)
4136 normalize_constant_expr (ex
);
4139 /* Count the leading zeroes by performing a binary chop. This is a
4140 bulky bit of source, but performance is a LOT better for the
4141 majority of values than a simple loop to count the bits:
4142 for (lcnt = 0; (lcnt < 32); lcnt++)
4143 if ((v) & (1 << (31 - lcnt)))
4145 However it is not code size friendly, and the gain will drop a bit
4146 on certain cached systems.
4148 #define COUNT_TOP_ZEROES(v) \
4149 (((v) & ~0xffff) == 0 \
4150 ? ((v) & ~0xff) == 0 \
4151 ? ((v) & ~0xf) == 0 \
4152 ? ((v) & ~0x3) == 0 \
4153 ? ((v) & ~0x1) == 0 \
4158 : ((v) & ~0x7) == 0 \
4161 : ((v) & ~0x3f) == 0 \
4162 ? ((v) & ~0x1f) == 0 \
4165 : ((v) & ~0x7f) == 0 \
4168 : ((v) & ~0xfff) == 0 \
4169 ? ((v) & ~0x3ff) == 0 \
4170 ? ((v) & ~0x1ff) == 0 \
4173 : ((v) & ~0x7ff) == 0 \
4176 : ((v) & ~0x3fff) == 0 \
4177 ? ((v) & ~0x1fff) == 0 \
4180 : ((v) & ~0x7fff) == 0 \
4183 : ((v) & ~0xffffff) == 0 \
4184 ? ((v) & ~0xfffff) == 0 \
4185 ? ((v) & ~0x3ffff) == 0 \
4186 ? ((v) & ~0x1ffff) == 0 \
4189 : ((v) & ~0x7ffff) == 0 \
4192 : ((v) & ~0x3fffff) == 0 \
4193 ? ((v) & ~0x1fffff) == 0 \
4196 : ((v) & ~0x7fffff) == 0 \
4199 : ((v) & ~0xfffffff) == 0 \
4200 ? ((v) & ~0x3ffffff) == 0 \
4201 ? ((v) & ~0x1ffffff) == 0 \
4204 : ((v) & ~0x7ffffff) == 0 \
4207 : ((v) & ~0x3fffffff) == 0 \
4208 ? ((v) & ~0x1fffffff) == 0 \
4211 : ((v) & ~0x7fffffff) == 0 \
4216 * This routine generates the least number of instructions necessary to load
4217 * an absolute expression value into a register.
4220 load_register (int reg
, expressionS
*ep
, int dbl
)
4223 expressionS hi32
, lo32
;
4225 if (ep
->X_op
!= O_big
)
4227 gas_assert (ep
->X_op
== O_constant
);
4229 /* Sign-extending 32-bit constants makes their handling easier. */
4231 normalize_constant_expr (ep
);
4233 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4235 /* We can handle 16 bit signed values with an addiu to
4236 $zero. No need to ever use daddiu here, since $zero and
4237 the result are always correct in 32 bit mode. */
4238 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4241 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4243 /* We can handle 16 bit unsigned values with an ori to
4245 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4248 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4250 /* 32 bit values require an lui. */
4251 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4252 if ((ep
->X_add_number
& 0xffff) != 0)
4253 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4258 /* The value is larger than 32 bits. */
4260 if (!dbl
|| HAVE_32BIT_GPRS
)
4264 sprintf_vma (value
, ep
->X_add_number
);
4265 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4266 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4270 if (ep
->X_op
!= O_big
)
4273 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4274 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4275 hi32
.X_add_number
&= 0xffffffff;
4277 lo32
.X_add_number
&= 0xffffffff;
4281 gas_assert (ep
->X_add_number
> 2);
4282 if (ep
->X_add_number
== 3)
4283 generic_bignum
[3] = 0;
4284 else if (ep
->X_add_number
> 4)
4285 as_bad (_("Number larger than 64 bits"));
4286 lo32
.X_op
= O_constant
;
4287 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4288 hi32
.X_op
= O_constant
;
4289 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4292 if (hi32
.X_add_number
== 0)
4297 unsigned long hi
, lo
;
4299 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4301 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4303 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4306 if (lo32
.X_add_number
& 0x80000000)
4308 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4309 if (lo32
.X_add_number
& 0xffff)
4310 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4315 /* Check for 16bit shifted constant. We know that hi32 is
4316 non-zero, so start the mask on the first bit of the hi32
4321 unsigned long himask
, lomask
;
4325 himask
= 0xffff >> (32 - shift
);
4326 lomask
= (0xffff << shift
) & 0xffffffff;
4330 himask
= 0xffff << (shift
- 32);
4333 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4334 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4338 tmp
.X_op
= O_constant
;
4340 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4341 | (lo32
.X_add_number
>> shift
));
4343 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4344 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4345 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4346 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4351 while (shift
<= (64 - 16));
4353 /* Find the bit number of the lowest one bit, and store the
4354 shifted value in hi/lo. */
4355 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4356 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4360 while ((lo
& 1) == 0)
4365 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4371 while ((hi
& 1) == 0)
4380 /* Optimize if the shifted value is a (power of 2) - 1. */
4381 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4382 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4384 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4389 /* This instruction will set the register to be all
4391 tmp
.X_op
= O_constant
;
4392 tmp
.X_add_number
= (offsetT
) -1;
4393 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4397 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4398 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4400 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4401 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4406 /* Sign extend hi32 before calling load_register, because we can
4407 generally get better code when we load a sign extended value. */
4408 if ((hi32
.X_add_number
& 0x80000000) != 0)
4409 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4410 load_register (reg
, &hi32
, 0);
4413 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4417 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4425 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4427 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4428 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4434 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4438 mid16
.X_add_number
>>= 16;
4439 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4440 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4443 if ((lo32
.X_add_number
& 0xffff) != 0)
4444 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4448 load_delay_nop (void)
4450 if (!gpr_interlocks
)
4451 macro_build (NULL
, "nop", "");
4454 /* Load an address into a register. */
4457 load_address (int reg
, expressionS
*ep
, int *used_at
)
4459 if (ep
->X_op
!= O_constant
4460 && ep
->X_op
!= O_symbol
)
4462 as_bad (_("expression too complex"));
4463 ep
->X_op
= O_constant
;
4466 if (ep
->X_op
== O_constant
)
4468 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4472 if (mips_pic
== NO_PIC
)
4474 /* If this is a reference to a GP relative symbol, we want
4475 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4477 lui $reg,<sym> (BFD_RELOC_HI16_S)
4478 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4479 If we have an addend, we always use the latter form.
4481 With 64bit address space and a usable $at we want
4482 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4483 lui $at,<sym> (BFD_RELOC_HI16_S)
4484 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4485 daddiu $at,<sym> (BFD_RELOC_LO16)
4489 If $at is already in use, we use a path which is suboptimal
4490 on superscalar processors.
4491 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4492 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4494 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4496 daddiu $reg,<sym> (BFD_RELOC_LO16)
4498 For GP relative symbols in 64bit address space we can use
4499 the same sequence as in 32bit address space. */
4500 if (HAVE_64BIT_SYMBOLS
)
4502 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4503 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4505 relax_start (ep
->X_add_symbol
);
4506 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4507 mips_gp_register
, BFD_RELOC_GPREL16
);
4511 if (*used_at
== 0 && mips_opts
.at
)
4513 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4514 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4515 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4516 BFD_RELOC_MIPS_HIGHER
);
4517 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4518 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4519 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4524 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4525 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4526 BFD_RELOC_MIPS_HIGHER
);
4527 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4528 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4529 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4530 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4533 if (mips_relax
.sequence
)
4538 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4539 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4541 relax_start (ep
->X_add_symbol
);
4542 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4543 mips_gp_register
, BFD_RELOC_GPREL16
);
4546 macro_build_lui (ep
, reg
);
4547 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4548 reg
, reg
, BFD_RELOC_LO16
);
4549 if (mips_relax
.sequence
)
4553 else if (!mips_big_got
)
4557 /* If this is a reference to an external symbol, we want
4558 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4560 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4562 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4563 If there is a constant, it must be added in after.
4565 If we have NewABI, we want
4566 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4567 unless we're referencing a global symbol with a non-zero
4568 offset, in which case cst must be added separately. */
4571 if (ep
->X_add_number
)
4573 ex
.X_add_number
= ep
->X_add_number
;
4574 ep
->X_add_number
= 0;
4575 relax_start (ep
->X_add_symbol
);
4576 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4577 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4578 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4579 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4580 ex
.X_op
= O_constant
;
4581 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4582 reg
, reg
, BFD_RELOC_LO16
);
4583 ep
->X_add_number
= ex
.X_add_number
;
4586 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4587 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4588 if (mips_relax
.sequence
)
4593 ex
.X_add_number
= ep
->X_add_number
;
4594 ep
->X_add_number
= 0;
4595 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4596 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4598 relax_start (ep
->X_add_symbol
);
4600 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4604 if (ex
.X_add_number
!= 0)
4606 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4607 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4608 ex
.X_op
= O_constant
;
4609 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4610 reg
, reg
, BFD_RELOC_LO16
);
4614 else if (mips_big_got
)
4618 /* This is the large GOT case. If this is a reference to an
4619 external symbol, we want
4620 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4622 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4624 Otherwise, for a reference to a local symbol in old ABI, we want
4625 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4627 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4628 If there is a constant, it must be added in after.
4630 In the NewABI, for local symbols, with or without offsets, we want:
4631 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4632 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4636 ex
.X_add_number
= ep
->X_add_number
;
4637 ep
->X_add_number
= 0;
4638 relax_start (ep
->X_add_symbol
);
4639 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4640 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4641 reg
, reg
, mips_gp_register
);
4642 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4643 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4644 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4645 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4646 else if (ex
.X_add_number
)
4648 ex
.X_op
= O_constant
;
4649 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4653 ep
->X_add_number
= ex
.X_add_number
;
4655 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4656 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4657 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4658 BFD_RELOC_MIPS_GOT_OFST
);
4663 ex
.X_add_number
= ep
->X_add_number
;
4664 ep
->X_add_number
= 0;
4665 relax_start (ep
->X_add_symbol
);
4666 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4668 reg
, reg
, mips_gp_register
);
4669 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4670 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4672 if (reg_needs_delay (mips_gp_register
))
4674 /* We need a nop before loading from $gp. This special
4675 check is required because the lui which starts the main
4676 instruction stream does not refer to $gp, and so will not
4677 insert the nop which may be required. */
4678 macro_build (NULL
, "nop", "");
4680 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4681 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4683 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4687 if (ex
.X_add_number
!= 0)
4689 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4690 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4691 ex
.X_op
= O_constant
;
4692 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4700 if (!mips_opts
.at
&& *used_at
== 1)
4701 as_bad (_("Macro used $at after \".set noat\""));
4704 /* Move the contents of register SOURCE into register DEST. */
4707 move_register (int dest
, int source
)
4709 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4713 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4714 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4715 The two alternatives are:
4717 Global symbol Local sybmol
4718 ------------- ------------
4719 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4721 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4723 load_got_offset emits the first instruction and add_got_offset
4724 emits the second for a 16-bit offset or add_got_offset_hilo emits
4725 a sequence to add a 32-bit offset using a scratch register. */
4728 load_got_offset (int dest
, expressionS
*local
)
4733 global
.X_add_number
= 0;
4735 relax_start (local
->X_add_symbol
);
4736 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4737 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4739 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4740 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4745 add_got_offset (int dest
, expressionS
*local
)
4749 global
.X_op
= O_constant
;
4750 global
.X_op_symbol
= NULL
;
4751 global
.X_add_symbol
= NULL
;
4752 global
.X_add_number
= local
->X_add_number
;
4754 relax_start (local
->X_add_symbol
);
4755 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4756 dest
, dest
, BFD_RELOC_LO16
);
4758 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4763 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4766 int hold_mips_optimize
;
4768 global
.X_op
= O_constant
;
4769 global
.X_op_symbol
= NULL
;
4770 global
.X_add_symbol
= NULL
;
4771 global
.X_add_number
= local
->X_add_number
;
4773 relax_start (local
->X_add_symbol
);
4774 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4776 /* Set mips_optimize around the lui instruction to avoid
4777 inserting an unnecessary nop after the lw. */
4778 hold_mips_optimize
= mips_optimize
;
4780 macro_build_lui (&global
, tmp
);
4781 mips_optimize
= hold_mips_optimize
;
4782 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4785 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4790 * This routine implements the seemingly endless macro or synthesized
4791 * instructions and addressing modes in the mips assembly language. Many
4792 * of these macros are simple and are similar to each other. These could
4793 * probably be handled by some kind of table or grammar approach instead of
4794 * this verbose method. Others are not simple macros but are more like
4795 * optimizing code generation.
4796 * One interesting optimization is when several store macros appear
4797 * consecutively that would load AT with the upper half of the same address.
4798 * The ensuing load upper instructions are ommited. This implies some kind
4799 * of global optimization. We currently only optimize within a single macro.
4800 * For many of the load and store macros if the address is specified as a
4801 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4802 * first load register 'at' with zero and use it as the base register. The
4803 * mips assembler simply uses register $zero. Just one tiny optimization
4807 macro (struct mips_cl_insn
*ip
)
4809 unsigned int treg
, sreg
, dreg
, breg
;
4810 unsigned int tempreg
;
4825 bfd_reloc_code_real_type r
;
4826 int hold_mips_optimize
;
4828 gas_assert (! mips_opts
.mips16
);
4830 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4831 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4832 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4833 mask
= ip
->insn_mo
->mask
;
4835 expr1
.X_op
= O_constant
;
4836 expr1
.X_op_symbol
= NULL
;
4837 expr1
.X_add_symbol
= NULL
;
4838 expr1
.X_add_number
= 1;
4852 expr1
.X_add_number
= 8;
4853 macro_build (&expr1
, "bgez", "s,p", sreg
);
4855 macro_build (NULL
, "nop", "", 0);
4857 move_register (dreg
, sreg
);
4858 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4881 if (imm_expr
.X_op
== O_constant
4882 && imm_expr
.X_add_number
>= -0x8000
4883 && imm_expr
.X_add_number
< 0x8000)
4885 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4889 load_register (AT
, &imm_expr
, dbl
);
4890 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4909 if (imm_expr
.X_op
== O_constant
4910 && imm_expr
.X_add_number
>= 0
4911 && imm_expr
.X_add_number
< 0x10000)
4913 if (mask
!= M_NOR_I
)
4914 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4917 macro_build (&imm_expr
, "ori", "t,r,i",
4918 treg
, sreg
, BFD_RELOC_LO16
);
4919 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4925 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4926 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4930 switch (imm_expr
.X_add_number
)
4933 macro_build (NULL
, "nop", "");
4936 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4939 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4940 (int)imm_expr
.X_add_number
);
4959 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4961 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4965 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4966 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4974 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4979 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4983 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4984 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4990 /* check for > max integer */
4991 maxnum
= 0x7fffffff;
4992 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4999 if (imm_expr
.X_op
== O_constant
5000 && imm_expr
.X_add_number
>= maxnum
5001 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5004 /* result is always false */
5006 macro_build (NULL
, "nop", "", 0);
5008 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
5011 if (imm_expr
.X_op
!= O_constant
)
5012 as_bad (_("Unsupported large constant"));
5013 ++imm_expr
.X_add_number
;
5017 if (mask
== M_BGEL_I
)
5019 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5021 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
5024 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5026 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5029 maxnum
= 0x7fffffff;
5030 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5037 maxnum
= - maxnum
- 1;
5038 if (imm_expr
.X_op
== O_constant
5039 && imm_expr
.X_add_number
<= maxnum
5040 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5043 /* result is always true */
5044 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
5045 macro_build (&offset_expr
, "b", "p");
5050 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5060 macro_build (&offset_expr
, likely
? "beql" : "beq",
5065 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5066 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5074 && imm_expr
.X_op
== O_constant
5075 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
5077 if (imm_expr
.X_op
!= O_constant
)
5078 as_bad (_("Unsupported large constant"));
5079 ++imm_expr
.X_add_number
;
5083 if (mask
== M_BGEUL_I
)
5085 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5087 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5089 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5095 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5103 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5108 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
5112 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5113 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5121 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5128 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5129 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5137 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5142 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
5146 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5147 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5153 maxnum
= 0x7fffffff;
5154 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5161 if (imm_expr
.X_op
== O_constant
5162 && imm_expr
.X_add_number
>= maxnum
5163 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5165 if (imm_expr
.X_op
!= O_constant
)
5166 as_bad (_("Unsupported large constant"));
5167 ++imm_expr
.X_add_number
;
5171 if (mask
== M_BLTL_I
)
5173 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5175 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5178 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5180 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5185 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5193 macro_build (&offset_expr
, likely
? "beql" : "beq",
5200 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5201 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5209 && imm_expr
.X_op
== O_constant
5210 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
5212 if (imm_expr
.X_op
!= O_constant
)
5213 as_bad (_("Unsupported large constant"));
5214 ++imm_expr
.X_add_number
;
5218 if (mask
== M_BLTUL_I
)
5220 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5222 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5224 macro_build (&offset_expr
, likely
? "beql" : "beq",
5230 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5238 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5243 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5247 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5248 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5258 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5263 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5264 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5272 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5274 as_bad (_("Unsupported large constant"));
5279 pos
= (unsigned long) imm_expr
.X_add_number
;
5280 size
= (unsigned long) imm2_expr
.X_add_number
;
5285 as_bad (_("Improper position (%lu)"), pos
);
5288 if (size
== 0 || size
> 64
5289 || (pos
+ size
- 1) > 63)
5291 as_bad (_("Improper extract size (%lu, position %lu)"),
5296 if (size
<= 32 && pos
< 32)
5301 else if (size
<= 32)
5311 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
5320 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5322 as_bad (_("Unsupported large constant"));
5327 pos
= (unsigned long) imm_expr
.X_add_number
;
5328 size
= (unsigned long) imm2_expr
.X_add_number
;
5333 as_bad (_("Improper position (%lu)"), pos
);
5336 if (size
== 0 || size
> 64
5337 || (pos
+ size
- 1) > 63)
5339 as_bad (_("Improper insert size (%lu, position %lu)"),
5344 if (pos
< 32 && (pos
+ size
- 1) < 32)
5359 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5360 (int) (pos
+ size
- 1));
5376 as_warn (_("Divide by zero."));
5378 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5380 macro_build (NULL
, "break", "c", 7);
5387 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5388 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5392 expr1
.X_add_number
= 8;
5393 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5394 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5395 macro_build (NULL
, "break", "c", 7);
5397 expr1
.X_add_number
= -1;
5399 load_register (AT
, &expr1
, dbl
);
5400 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5401 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5404 expr1
.X_add_number
= 1;
5405 load_register (AT
, &expr1
, dbl
);
5406 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5410 expr1
.X_add_number
= 0x80000000;
5411 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5415 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5416 /* We want to close the noreorder block as soon as possible, so
5417 that later insns are available for delay slot filling. */
5422 expr1
.X_add_number
= 8;
5423 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5424 macro_build (NULL
, "nop", "", 0);
5426 /* We want to close the noreorder block as soon as possible, so
5427 that later insns are available for delay slot filling. */
5430 macro_build (NULL
, "break", "c", 6);
5432 macro_build (NULL
, s
, "d", dreg
);
5471 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5473 as_warn (_("Divide by zero."));
5475 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5477 macro_build (NULL
, "break", "c", 7);
5480 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5482 if (strcmp (s2
, "mflo") == 0)
5483 move_register (dreg
, sreg
);
5485 move_register (dreg
, 0);
5488 if (imm_expr
.X_op
== O_constant
5489 && imm_expr
.X_add_number
== -1
5490 && s
[strlen (s
) - 1] != 'u')
5492 if (strcmp (s2
, "mflo") == 0)
5494 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5497 move_register (dreg
, 0);
5502 load_register (AT
, &imm_expr
, dbl
);
5503 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5504 macro_build (NULL
, s2
, "d", dreg
);
5526 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5527 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5528 /* We want to close the noreorder block as soon as possible, so
5529 that later insns are available for delay slot filling. */
5534 expr1
.X_add_number
= 8;
5535 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5536 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5538 /* We want to close the noreorder block as soon as possible, so
5539 that later insns are available for delay slot filling. */
5541 macro_build (NULL
, "break", "c", 7);
5543 macro_build (NULL
, s2
, "d", dreg
);
5555 /* Load the address of a symbol into a register. If breg is not
5556 zero, we then add a base register to it. */
5558 if (dbl
&& HAVE_32BIT_GPRS
)
5559 as_warn (_("dla used to load 32-bit register"));
5561 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5562 as_warn (_("la used to load 64-bit address"));
5564 if (offset_expr
.X_op
== O_constant
5565 && offset_expr
.X_add_number
>= -0x8000
5566 && offset_expr
.X_add_number
< 0x8000)
5568 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5569 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5573 if (mips_opts
.at
&& (treg
== breg
))
5583 if (offset_expr
.X_op
!= O_symbol
5584 && offset_expr
.X_op
!= O_constant
)
5586 as_bad (_("expression too complex"));
5587 offset_expr
.X_op
= O_constant
;
5590 if (offset_expr
.X_op
== O_constant
)
5591 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5592 else if (mips_pic
== NO_PIC
)
5594 /* If this is a reference to a GP relative symbol, we want
5595 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5597 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5598 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5599 If we have a constant, we need two instructions anyhow,
5600 so we may as well always use the latter form.
5602 With 64bit address space and a usable $at we want
5603 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5604 lui $at,<sym> (BFD_RELOC_HI16_S)
5605 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5606 daddiu $at,<sym> (BFD_RELOC_LO16)
5608 daddu $tempreg,$tempreg,$at
5610 If $at is already in use, we use a path which is suboptimal
5611 on superscalar processors.
5612 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5613 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5615 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5617 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5619 For GP relative symbols in 64bit address space we can use
5620 the same sequence as in 32bit address space. */
5621 if (HAVE_64BIT_SYMBOLS
)
5623 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5624 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5626 relax_start (offset_expr
.X_add_symbol
);
5627 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5628 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5632 if (used_at
== 0 && mips_opts
.at
)
5634 macro_build (&offset_expr
, "lui", "t,u",
5635 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5636 macro_build (&offset_expr
, "lui", "t,u",
5637 AT
, BFD_RELOC_HI16_S
);
5638 macro_build (&offset_expr
, "daddiu", "t,r,j",
5639 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5640 macro_build (&offset_expr
, "daddiu", "t,r,j",
5641 AT
, AT
, BFD_RELOC_LO16
);
5642 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5643 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5648 macro_build (&offset_expr
, "lui", "t,u",
5649 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5650 macro_build (&offset_expr
, "daddiu", "t,r,j",
5651 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5652 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5653 macro_build (&offset_expr
, "daddiu", "t,r,j",
5654 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5655 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5656 macro_build (&offset_expr
, "daddiu", "t,r,j",
5657 tempreg
, tempreg
, BFD_RELOC_LO16
);
5660 if (mips_relax
.sequence
)
5665 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5666 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5668 relax_start (offset_expr
.X_add_symbol
);
5669 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5670 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5673 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5674 as_bad (_("offset too large"));
5675 macro_build_lui (&offset_expr
, tempreg
);
5676 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5677 tempreg
, tempreg
, BFD_RELOC_LO16
);
5678 if (mips_relax
.sequence
)
5682 else if (!mips_big_got
&& !HAVE_NEWABI
)
5684 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5686 /* If this is a reference to an external symbol, and there
5687 is no constant, we want
5688 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5689 or for lca or if tempreg is PIC_CALL_REG
5690 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5691 For a local symbol, we want
5692 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5694 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5696 If we have a small constant, and this is a reference to
5697 an external symbol, we want
5698 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5700 addiu $tempreg,$tempreg,<constant>
5701 For a local symbol, we want the same instruction
5702 sequence, but we output a BFD_RELOC_LO16 reloc on the
5705 If we have a large constant, and this is a reference to
5706 an external symbol, we want
5707 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5708 lui $at,<hiconstant>
5709 addiu $at,$at,<loconstant>
5710 addu $tempreg,$tempreg,$at
5711 For a local symbol, we want the same instruction
5712 sequence, but we output a BFD_RELOC_LO16 reloc on the
5716 if (offset_expr
.X_add_number
== 0)
5718 if (mips_pic
== SVR4_PIC
5720 && (call
|| tempreg
== PIC_CALL_REG
))
5721 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5723 relax_start (offset_expr
.X_add_symbol
);
5724 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5725 lw_reloc_type
, mips_gp_register
);
5728 /* We're going to put in an addu instruction using
5729 tempreg, so we may as well insert the nop right
5734 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5735 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5737 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5738 tempreg
, tempreg
, BFD_RELOC_LO16
);
5740 /* FIXME: If breg == 0, and the next instruction uses
5741 $tempreg, then if this variant case is used an extra
5742 nop will be generated. */
5744 else if (offset_expr
.X_add_number
>= -0x8000
5745 && offset_expr
.X_add_number
< 0x8000)
5747 load_got_offset (tempreg
, &offset_expr
);
5749 add_got_offset (tempreg
, &offset_expr
);
5753 expr1
.X_add_number
= offset_expr
.X_add_number
;
5754 offset_expr
.X_add_number
=
5755 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5756 load_got_offset (tempreg
, &offset_expr
);
5757 offset_expr
.X_add_number
= expr1
.X_add_number
;
5758 /* If we are going to add in a base register, and the
5759 target register and the base register are the same,
5760 then we are using AT as a temporary register. Since
5761 we want to load the constant into AT, we add our
5762 current AT (from the global offset table) and the
5763 register into the register now, and pretend we were
5764 not using a base register. */
5768 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5773 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5777 else if (!mips_big_got
&& HAVE_NEWABI
)
5779 int add_breg_early
= 0;
5781 /* If this is a reference to an external, and there is no
5782 constant, or local symbol (*), with or without a
5784 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5785 or for lca or if tempreg is PIC_CALL_REG
5786 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5788 If we have a small constant, and this is a reference to
5789 an external symbol, we want
5790 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5791 addiu $tempreg,$tempreg,<constant>
5793 If we have a large constant, and this is a reference to
5794 an external symbol, we want
5795 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5796 lui $at,<hiconstant>
5797 addiu $at,$at,<loconstant>
5798 addu $tempreg,$tempreg,$at
5800 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5801 local symbols, even though it introduces an additional
5804 if (offset_expr
.X_add_number
)
5806 expr1
.X_add_number
= offset_expr
.X_add_number
;
5807 offset_expr
.X_add_number
= 0;
5809 relax_start (offset_expr
.X_add_symbol
);
5810 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5811 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5813 if (expr1
.X_add_number
>= -0x8000
5814 && expr1
.X_add_number
< 0x8000)
5816 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5817 tempreg
, tempreg
, BFD_RELOC_LO16
);
5819 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5821 /* If we are going to add in a base register, and the
5822 target register and the base register are the same,
5823 then we are using AT as a temporary register. Since
5824 we want to load the constant into AT, we add our
5825 current AT (from the global offset table) and the
5826 register into the register now, and pretend we were
5827 not using a base register. */
5832 gas_assert (tempreg
== AT
);
5833 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5839 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5840 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5846 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5849 offset_expr
.X_add_number
= expr1
.X_add_number
;
5851 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5852 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5855 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5856 treg
, tempreg
, breg
);
5862 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5864 relax_start (offset_expr
.X_add_symbol
);
5865 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5866 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5868 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5869 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5874 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5875 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5878 else if (mips_big_got
&& !HAVE_NEWABI
)
5881 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5882 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5883 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5885 /* This is the large GOT case. If this is a reference to an
5886 external symbol, and there is no constant, we want
5887 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5888 addu $tempreg,$tempreg,$gp
5889 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5890 or for lca or if tempreg is PIC_CALL_REG
5891 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5892 addu $tempreg,$tempreg,$gp
5893 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5894 For a local symbol, we want
5895 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5897 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5899 If we have a small constant, and this is a reference to
5900 an external symbol, we want
5901 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5902 addu $tempreg,$tempreg,$gp
5903 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5905 addiu $tempreg,$tempreg,<constant>
5906 For a local symbol, we want
5907 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5909 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5911 If we have a large constant, and this is a reference to
5912 an external symbol, we want
5913 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5914 addu $tempreg,$tempreg,$gp
5915 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5916 lui $at,<hiconstant>
5917 addiu $at,$at,<loconstant>
5918 addu $tempreg,$tempreg,$at
5919 For a local symbol, we want
5920 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5921 lui $at,<hiconstant>
5922 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5923 addu $tempreg,$tempreg,$at
5926 expr1
.X_add_number
= offset_expr
.X_add_number
;
5927 offset_expr
.X_add_number
= 0;
5928 relax_start (offset_expr
.X_add_symbol
);
5929 gpdelay
= reg_needs_delay (mips_gp_register
);
5930 if (expr1
.X_add_number
== 0 && breg
== 0
5931 && (call
|| tempreg
== PIC_CALL_REG
))
5933 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5934 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5936 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5937 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5938 tempreg
, tempreg
, mips_gp_register
);
5939 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5940 tempreg
, lw_reloc_type
, tempreg
);
5941 if (expr1
.X_add_number
== 0)
5945 /* We're going to put in an addu instruction using
5946 tempreg, so we may as well insert the nop right
5951 else if (expr1
.X_add_number
>= -0x8000
5952 && expr1
.X_add_number
< 0x8000)
5955 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5956 tempreg
, tempreg
, BFD_RELOC_LO16
);
5960 /* If we are going to add in a base register, and the
5961 target register and the base register are the same,
5962 then we are using AT as a temporary register. Since
5963 we want to load the constant into AT, we add our
5964 current AT (from the global offset table) and the
5965 register into the register now, and pretend we were
5966 not using a base register. */
5971 gas_assert (tempreg
== AT
);
5973 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5978 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5979 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5983 offset_expr
.X_add_number
=
5984 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5989 /* This is needed because this instruction uses $gp, but
5990 the first instruction on the main stream does not. */
5991 macro_build (NULL
, "nop", "");
5994 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5995 local_reloc_type
, mips_gp_register
);
5996 if (expr1
.X_add_number
>= -0x8000
5997 && expr1
.X_add_number
< 0x8000)
6000 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6001 tempreg
, tempreg
, BFD_RELOC_LO16
);
6002 /* FIXME: If add_number is 0, and there was no base
6003 register, the external symbol case ended with a load,
6004 so if the symbol turns out to not be external, and
6005 the next instruction uses tempreg, an unnecessary nop
6006 will be inserted. */
6012 /* We must add in the base register now, as in the
6013 external symbol case. */
6014 gas_assert (tempreg
== AT
);
6016 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6019 /* We set breg to 0 because we have arranged to add
6020 it in in both cases. */
6024 macro_build_lui (&expr1
, AT
);
6025 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6026 AT
, AT
, BFD_RELOC_LO16
);
6027 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6028 tempreg
, tempreg
, AT
);
6033 else if (mips_big_got
&& HAVE_NEWABI
)
6035 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
6036 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
6037 int add_breg_early
= 0;
6039 /* This is the large GOT case. If this is a reference to an
6040 external symbol, and there is no constant, we want
6041 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6042 add $tempreg,$tempreg,$gp
6043 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6044 or for lca or if tempreg is PIC_CALL_REG
6045 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6046 add $tempreg,$tempreg,$gp
6047 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6049 If we have a small constant, and this is a reference to
6050 an external symbol, we want
6051 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6052 add $tempreg,$tempreg,$gp
6053 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6054 addi $tempreg,$tempreg,<constant>
6056 If we have a large constant, and this is a reference to
6057 an external symbol, we want
6058 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6059 addu $tempreg,$tempreg,$gp
6060 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6061 lui $at,<hiconstant>
6062 addi $at,$at,<loconstant>
6063 add $tempreg,$tempreg,$at
6065 If we have NewABI, and we know it's a local symbol, we want
6066 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6067 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6068 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6070 relax_start (offset_expr
.X_add_symbol
);
6072 expr1
.X_add_number
= offset_expr
.X_add_number
;
6073 offset_expr
.X_add_number
= 0;
6075 if (expr1
.X_add_number
== 0 && breg
== 0
6076 && (call
|| tempreg
== PIC_CALL_REG
))
6078 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
6079 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
6081 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
6082 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6083 tempreg
, tempreg
, mips_gp_register
);
6084 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6085 tempreg
, lw_reloc_type
, tempreg
);
6087 if (expr1
.X_add_number
== 0)
6089 else if (expr1
.X_add_number
>= -0x8000
6090 && expr1
.X_add_number
< 0x8000)
6092 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
6093 tempreg
, tempreg
, BFD_RELOC_LO16
);
6095 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
6097 /* If we are going to add in a base register, and the
6098 target register and the base register are the same,
6099 then we are using AT as a temporary register. Since
6100 we want to load the constant into AT, we add our
6101 current AT (from the global offset table) and the
6102 register into the register now, and pretend we were
6103 not using a base register. */
6108 gas_assert (tempreg
== AT
);
6109 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6115 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6116 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6121 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6124 offset_expr
.X_add_number
= expr1
.X_add_number
;
6125 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6126 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6127 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6128 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
6131 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6132 treg
, tempreg
, breg
);
6142 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
6147 unsigned long temp
= (treg
<< 16) | (0x01);
6148 macro_build (NULL
, "c2", "C", temp
);
6150 /* AT is not used, just return */
6155 unsigned long temp
= (0x02);
6156 macro_build (NULL
, "c2", "C", temp
);
6158 /* AT is not used, just return */
6163 unsigned long temp
= (treg
<< 16) | (0x02);
6164 macro_build (NULL
, "c2", "C", temp
);
6166 /* AT is not used, just return */
6170 macro_build (NULL
, "c2", "C", 3);
6171 /* AT is not used, just return */
6176 unsigned long temp
= (treg
<< 16) | 0x03;
6177 macro_build (NULL
, "c2", "C", temp
);
6179 /* AT is not used, just return */
6183 /* The j instruction may not be used in PIC code, since it
6184 requires an absolute address. We convert it to a b
6186 if (mips_pic
== NO_PIC
)
6187 macro_build (&offset_expr
, "j", "a");
6189 macro_build (&offset_expr
, "b", "p");
6192 /* The jal instructions must be handled as macros because when
6193 generating PIC code they expand to multi-instruction
6194 sequences. Normally they are simple instructions. */
6199 if (mips_pic
== NO_PIC
)
6200 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6203 if (sreg
!= PIC_CALL_REG
)
6204 as_warn (_("MIPS PIC call to register other than $25"));
6206 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6207 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6209 if (mips_cprestore_offset
< 0)
6210 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6213 if (! mips_frame_reg_valid
)
6215 as_warn (_("No .frame pseudo-op used in PIC code"));
6216 /* Quiet this warning. */
6217 mips_frame_reg_valid
= 1;
6219 if (! mips_cprestore_valid
)
6221 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6222 /* Quiet this warning. */
6223 mips_cprestore_valid
= 1;
6225 if (mips_opts
.noreorder
)
6226 macro_build (NULL
, "nop", "");
6227 expr1
.X_add_number
= mips_cprestore_offset
;
6228 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6231 HAVE_64BIT_ADDRESSES
);
6239 if (mips_pic
== NO_PIC
)
6240 macro_build (&offset_expr
, "jal", "a");
6241 else if (mips_pic
== SVR4_PIC
)
6243 /* If this is a reference to an external symbol, and we are
6244 using a small GOT, we want
6245 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6249 lw $gp,cprestore($sp)
6250 The cprestore value is set using the .cprestore
6251 pseudo-op. If we are using a big GOT, we want
6252 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6254 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6258 lw $gp,cprestore($sp)
6259 If the symbol is not external, we want
6260 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6262 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6265 lw $gp,cprestore($sp)
6267 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6268 sequences above, minus nops, unless the symbol is local,
6269 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6275 relax_start (offset_expr
.X_add_symbol
);
6276 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6277 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6280 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6281 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6287 relax_start (offset_expr
.X_add_symbol
);
6288 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6289 BFD_RELOC_MIPS_CALL_HI16
);
6290 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6291 PIC_CALL_REG
, mips_gp_register
);
6292 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6293 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6296 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6297 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6299 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6300 PIC_CALL_REG
, PIC_CALL_REG
,
6301 BFD_RELOC_MIPS_GOT_OFST
);
6305 macro_build_jalr (&offset_expr
);
6309 relax_start (offset_expr
.X_add_symbol
);
6312 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6313 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6322 gpdelay
= reg_needs_delay (mips_gp_register
);
6323 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6324 BFD_RELOC_MIPS_CALL_HI16
);
6325 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6326 PIC_CALL_REG
, mips_gp_register
);
6327 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6328 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6333 macro_build (NULL
, "nop", "");
6335 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6336 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6339 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6340 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6342 macro_build_jalr (&offset_expr
);
6344 if (mips_cprestore_offset
< 0)
6345 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6348 if (! mips_frame_reg_valid
)
6350 as_warn (_("No .frame pseudo-op used in PIC code"));
6351 /* Quiet this warning. */
6352 mips_frame_reg_valid
= 1;
6354 if (! mips_cprestore_valid
)
6356 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6357 /* Quiet this warning. */
6358 mips_cprestore_valid
= 1;
6360 if (mips_opts
.noreorder
)
6361 macro_build (NULL
, "nop", "");
6362 expr1
.X_add_number
= mips_cprestore_offset
;
6363 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6366 HAVE_64BIT_ADDRESSES
);
6370 else if (mips_pic
== VXWORKS_PIC
)
6371 as_bad (_("Non-PIC jump used in PIC library"));
6394 /* Itbl support may require additional care here. */
6399 /* Itbl support may require additional care here. */
6404 /* Itbl support may require additional care here. */
6409 /* Itbl support may require additional care here. */
6422 /* Itbl support may require additional care here. */
6427 /* Itbl support may require additional care here. */
6432 /* Itbl support may require additional care here. */
6452 if (breg
== treg
|| coproc
|| lr
)
6473 /* Itbl support may require additional care here. */
6478 /* Itbl support may require additional care here. */
6483 /* Itbl support may require additional care here. */
6488 /* Itbl support may require additional care here. */
6509 /* Itbl support may require additional care here. */
6513 /* Itbl support may require additional care here. */
6518 /* Itbl support may require additional care here. */
6531 && NO_ISA_COP (mips_opts
.arch
)
6532 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6534 as_bad (_("opcode not supported on this processor: %s"),
6535 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6539 /* Itbl support may require additional care here. */
6540 if (mask
== M_LWC1_AB
6541 || mask
== M_SWC1_AB
6542 || mask
== M_LDC1_AB
6543 || mask
== M_SDC1_AB
6547 else if (mask
== M_CACHE_AB
)
6554 if (offset_expr
.X_op
!= O_constant
6555 && offset_expr
.X_op
!= O_symbol
)
6557 as_bad (_("expression too complex"));
6558 offset_expr
.X_op
= O_constant
;
6561 if (HAVE_32BIT_ADDRESSES
6562 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6566 sprintf_vma (value
, offset_expr
.X_add_number
);
6567 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6570 /* A constant expression in PIC code can be handled just as it
6571 is in non PIC code. */
6572 if (offset_expr
.X_op
== O_constant
)
6574 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6575 & ~(bfd_vma
) 0xffff);
6576 normalize_address_expr (&expr1
);
6577 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6579 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6580 tempreg
, tempreg
, breg
);
6581 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6583 else if (mips_pic
== NO_PIC
)
6585 /* If this is a reference to a GP relative symbol, and there
6586 is no base register, we want
6587 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6588 Otherwise, if there is no base register, we want
6589 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6590 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6591 If we have a constant, we need two instructions anyhow,
6592 so we always use the latter form.
6594 If we have a base register, and this is a reference to a
6595 GP relative symbol, we want
6596 addu $tempreg,$breg,$gp
6597 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6599 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6600 addu $tempreg,$tempreg,$breg
6601 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6602 With a constant we always use the latter case.
6604 With 64bit address space and no base register and $at usable,
6606 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6607 lui $at,<sym> (BFD_RELOC_HI16_S)
6608 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6611 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6612 If we have a base register, we want
6613 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6614 lui $at,<sym> (BFD_RELOC_HI16_S)
6615 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6619 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6621 Without $at we can't generate the optimal path for superscalar
6622 processors here since this would require two temporary registers.
6623 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6624 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6626 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6628 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6629 If we have a base register, we want
6630 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6631 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6633 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6635 daddu $tempreg,$tempreg,$breg
6636 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6638 For GP relative symbols in 64bit address space we can use
6639 the same sequence as in 32bit address space. */
6640 if (HAVE_64BIT_SYMBOLS
)
6642 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6643 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6645 relax_start (offset_expr
.X_add_symbol
);
6648 macro_build (&offset_expr
, s
, fmt
, treg
,
6649 BFD_RELOC_GPREL16
, mips_gp_register
);
6653 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6654 tempreg
, breg
, mips_gp_register
);
6655 macro_build (&offset_expr
, s
, fmt
, treg
,
6656 BFD_RELOC_GPREL16
, tempreg
);
6661 if (used_at
== 0 && mips_opts
.at
)
6663 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6664 BFD_RELOC_MIPS_HIGHEST
);
6665 macro_build (&offset_expr
, "lui", "t,u", AT
,
6667 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6668 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6670 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6671 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6672 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6673 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6679 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6680 BFD_RELOC_MIPS_HIGHEST
);
6681 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6682 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6683 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6684 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6685 tempreg
, BFD_RELOC_HI16_S
);
6686 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6688 macro_build (NULL
, "daddu", "d,v,t",
6689 tempreg
, tempreg
, breg
);
6690 macro_build (&offset_expr
, s
, fmt
, treg
,
6691 BFD_RELOC_LO16
, tempreg
);
6694 if (mips_relax
.sequence
)
6701 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6702 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6704 relax_start (offset_expr
.X_add_symbol
);
6705 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6709 macro_build_lui (&offset_expr
, tempreg
);
6710 macro_build (&offset_expr
, s
, fmt
, treg
,
6711 BFD_RELOC_LO16
, tempreg
);
6712 if (mips_relax
.sequence
)
6717 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6718 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6720 relax_start (offset_expr
.X_add_symbol
);
6721 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6722 tempreg
, breg
, mips_gp_register
);
6723 macro_build (&offset_expr
, s
, fmt
, treg
,
6724 BFD_RELOC_GPREL16
, tempreg
);
6727 macro_build_lui (&offset_expr
, tempreg
);
6728 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6729 tempreg
, tempreg
, breg
);
6730 macro_build (&offset_expr
, s
, fmt
, treg
,
6731 BFD_RELOC_LO16
, tempreg
);
6732 if (mips_relax
.sequence
)
6736 else if (!mips_big_got
)
6738 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6740 /* If this is a reference to an external symbol, we want
6741 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6743 <op> $treg,0($tempreg)
6745 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6747 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6748 <op> $treg,0($tempreg)
6751 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6752 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6754 If there is a base register, we add it to $tempreg before
6755 the <op>. If there is a constant, we stick it in the
6756 <op> instruction. We don't handle constants larger than
6757 16 bits, because we have no way to load the upper 16 bits
6758 (actually, we could handle them for the subset of cases
6759 in which we are not using $at). */
6760 gas_assert (offset_expr
.X_op
== O_symbol
);
6763 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6764 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6766 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6767 tempreg
, tempreg
, breg
);
6768 macro_build (&offset_expr
, s
, fmt
, treg
,
6769 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6772 expr1
.X_add_number
= offset_expr
.X_add_number
;
6773 offset_expr
.X_add_number
= 0;
6774 if (expr1
.X_add_number
< -0x8000
6775 || expr1
.X_add_number
>= 0x8000)
6776 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6777 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6778 lw_reloc_type
, mips_gp_register
);
6780 relax_start (offset_expr
.X_add_symbol
);
6782 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6783 tempreg
, BFD_RELOC_LO16
);
6786 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6787 tempreg
, tempreg
, breg
);
6788 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6790 else if (mips_big_got
&& !HAVE_NEWABI
)
6794 /* If this is a reference to an external symbol, we want
6795 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6796 addu $tempreg,$tempreg,$gp
6797 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6798 <op> $treg,0($tempreg)
6800 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6802 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6803 <op> $treg,0($tempreg)
6804 If there is a base register, we add it to $tempreg before
6805 the <op>. If there is a constant, we stick it in the
6806 <op> instruction. We don't handle constants larger than
6807 16 bits, because we have no way to load the upper 16 bits
6808 (actually, we could handle them for the subset of cases
6809 in which we are not using $at). */
6810 gas_assert (offset_expr
.X_op
== O_symbol
);
6811 expr1
.X_add_number
= offset_expr
.X_add_number
;
6812 offset_expr
.X_add_number
= 0;
6813 if (expr1
.X_add_number
< -0x8000
6814 || expr1
.X_add_number
>= 0x8000)
6815 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6816 gpdelay
= reg_needs_delay (mips_gp_register
);
6817 relax_start (offset_expr
.X_add_symbol
);
6818 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6819 BFD_RELOC_MIPS_GOT_HI16
);
6820 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6822 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6823 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6826 macro_build (NULL
, "nop", "");
6827 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6828 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6830 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6831 tempreg
, BFD_RELOC_LO16
);
6835 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6836 tempreg
, tempreg
, breg
);
6837 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6839 else if (mips_big_got
&& HAVE_NEWABI
)
6841 /* If this is a reference to an external symbol, we want
6842 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6843 add $tempreg,$tempreg,$gp
6844 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6845 <op> $treg,<ofst>($tempreg)
6846 Otherwise, for local symbols, we want:
6847 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6848 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6849 gas_assert (offset_expr
.X_op
== O_symbol
);
6850 expr1
.X_add_number
= offset_expr
.X_add_number
;
6851 offset_expr
.X_add_number
= 0;
6852 if (expr1
.X_add_number
< -0x8000
6853 || expr1
.X_add_number
>= 0x8000)
6854 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6855 relax_start (offset_expr
.X_add_symbol
);
6856 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6857 BFD_RELOC_MIPS_GOT_HI16
);
6858 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6860 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6861 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6863 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6864 tempreg
, tempreg
, breg
);
6865 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6868 offset_expr
.X_add_number
= expr1
.X_add_number
;
6869 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6870 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6872 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6873 tempreg
, tempreg
, breg
);
6874 macro_build (&offset_expr
, s
, fmt
, treg
,
6875 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6885 load_register (treg
, &imm_expr
, 0);
6889 load_register (treg
, &imm_expr
, 1);
6893 if (imm_expr
.X_op
== O_constant
)
6896 load_register (AT
, &imm_expr
, 0);
6897 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6902 gas_assert (offset_expr
.X_op
== O_symbol
6903 && strcmp (segment_name (S_GET_SEGMENT
6904 (offset_expr
.X_add_symbol
)),
6906 && offset_expr
.X_add_number
== 0);
6907 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6908 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6913 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6914 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6915 order 32 bits of the value and the low order 32 bits are either
6916 zero or in OFFSET_EXPR. */
6917 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6919 if (HAVE_64BIT_GPRS
)
6920 load_register (treg
, &imm_expr
, 1);
6925 if (target_big_endian
)
6937 load_register (hreg
, &imm_expr
, 0);
6940 if (offset_expr
.X_op
== O_absent
)
6941 move_register (lreg
, 0);
6944 gas_assert (offset_expr
.X_op
== O_constant
);
6945 load_register (lreg
, &offset_expr
, 0);
6952 /* We know that sym is in the .rdata section. First we get the
6953 upper 16 bits of the address. */
6954 if (mips_pic
== NO_PIC
)
6956 macro_build_lui (&offset_expr
, AT
);
6961 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6962 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6966 /* Now we load the register(s). */
6967 if (HAVE_64BIT_GPRS
)
6970 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6975 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6978 /* FIXME: How in the world do we deal with the possible
6980 offset_expr
.X_add_number
+= 4;
6981 macro_build (&offset_expr
, "lw", "t,o(b)",
6982 treg
+ 1, BFD_RELOC_LO16
, AT
);
6988 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6989 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6990 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6991 the value and the low order 32 bits are either zero or in
6993 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6996 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6997 if (HAVE_64BIT_FPRS
)
6999 gas_assert (HAVE_64BIT_GPRS
);
7000 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
7004 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
7005 if (offset_expr
.X_op
== O_absent
)
7006 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
7009 gas_assert (offset_expr
.X_op
== O_constant
);
7010 load_register (AT
, &offset_expr
, 0);
7011 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
7017 gas_assert (offset_expr
.X_op
== O_symbol
7018 && offset_expr
.X_add_number
== 0);
7019 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
7020 if (strcmp (s
, ".lit8") == 0)
7022 if (mips_opts
.isa
!= ISA_MIPS1
)
7024 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
7025 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
7028 breg
= mips_gp_register
;
7029 r
= BFD_RELOC_MIPS_LITERAL
;
7034 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
7036 if (mips_pic
!= NO_PIC
)
7037 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7038 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7041 /* FIXME: This won't work for a 64 bit address. */
7042 macro_build_lui (&offset_expr
, AT
);
7045 if (mips_opts
.isa
!= ISA_MIPS1
)
7047 macro_build (&offset_expr
, "ldc1", "T,o(b)",
7048 treg
, BFD_RELOC_LO16
, AT
);
7057 /* Even on a big endian machine $fn comes before $fn+1. We have
7058 to adjust when loading from memory. */
7061 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7062 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7063 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
7064 /* FIXME: A possible overflow which I don't know how to deal
7066 offset_expr
.X_add_number
+= 4;
7067 macro_build (&offset_expr
, "lwc1", "T,o(b)",
7068 target_big_endian
? treg
: treg
+ 1, r
, breg
);
7073 * The MIPS assembler seems to check for X_add_number not
7074 * being double aligned and generating:
7077 * addiu at,at,%lo(foo+1)
7080 * But, the resulting address is the same after relocation so why
7081 * generate the extra instruction?
7083 /* Itbl support may require additional care here. */
7085 if (mips_opts
.isa
!= ISA_MIPS1
)
7096 if (mips_opts
.isa
!= ISA_MIPS1
)
7104 /* Itbl support may require additional care here. */
7109 if (HAVE_64BIT_GPRS
)
7120 if (HAVE_64BIT_GPRS
)
7130 if (offset_expr
.X_op
!= O_symbol
7131 && offset_expr
.X_op
!= O_constant
)
7133 as_bad (_("expression too complex"));
7134 offset_expr
.X_op
= O_constant
;
7137 if (HAVE_32BIT_ADDRESSES
7138 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7142 sprintf_vma (value
, offset_expr
.X_add_number
);
7143 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7146 /* Even on a big endian machine $fn comes before $fn+1. We have
7147 to adjust when loading from memory. We set coproc if we must
7148 load $fn+1 first. */
7149 /* Itbl support may require additional care here. */
7150 if (! target_big_endian
)
7153 if (mips_pic
== NO_PIC
7154 || offset_expr
.X_op
== O_constant
)
7156 /* If this is a reference to a GP relative symbol, we want
7157 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7158 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7159 If we have a base register, we use this
7161 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7162 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7163 If this is not a GP relative symbol, we want
7164 lui $at,<sym> (BFD_RELOC_HI16_S)
7165 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7166 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7167 If there is a base register, we add it to $at after the
7168 lui instruction. If there is a constant, we always use
7170 if (offset_expr
.X_op
== O_symbol
7171 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7172 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7174 relax_start (offset_expr
.X_add_symbol
);
7177 tempreg
= mips_gp_register
;
7181 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7182 AT
, breg
, mips_gp_register
);
7187 /* Itbl support may require additional care here. */
7188 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7189 BFD_RELOC_GPREL16
, tempreg
);
7190 offset_expr
.X_add_number
+= 4;
7192 /* Set mips_optimize to 2 to avoid inserting an
7194 hold_mips_optimize
= mips_optimize
;
7196 /* Itbl support may require additional care here. */
7197 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7198 BFD_RELOC_GPREL16
, tempreg
);
7199 mips_optimize
= hold_mips_optimize
;
7203 offset_expr
.X_add_number
-= 4;
7206 macro_build_lui (&offset_expr
, AT
);
7208 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7209 /* Itbl support may require additional care here. */
7210 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7211 BFD_RELOC_LO16
, AT
);
7212 /* FIXME: How do we handle overflow here? */
7213 offset_expr
.X_add_number
+= 4;
7214 /* Itbl support may require additional care here. */
7215 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7216 BFD_RELOC_LO16
, AT
);
7217 if (mips_relax
.sequence
)
7220 else if (!mips_big_got
)
7222 /* If this is a reference to an external symbol, we want
7223 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7228 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7230 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7231 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7232 If there is a base register we add it to $at before the
7233 lwc1 instructions. If there is a constant we include it
7234 in the lwc1 instructions. */
7236 expr1
.X_add_number
= offset_expr
.X_add_number
;
7237 if (expr1
.X_add_number
< -0x8000
7238 || expr1
.X_add_number
>= 0x8000 - 4)
7239 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7240 load_got_offset (AT
, &offset_expr
);
7243 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7245 /* Set mips_optimize to 2 to avoid inserting an undesired
7247 hold_mips_optimize
= mips_optimize
;
7250 /* Itbl support may require additional care here. */
7251 relax_start (offset_expr
.X_add_symbol
);
7252 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7253 BFD_RELOC_LO16
, AT
);
7254 expr1
.X_add_number
+= 4;
7255 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7256 BFD_RELOC_LO16
, AT
);
7258 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7259 BFD_RELOC_LO16
, AT
);
7260 offset_expr
.X_add_number
+= 4;
7261 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7262 BFD_RELOC_LO16
, AT
);
7265 mips_optimize
= hold_mips_optimize
;
7267 else if (mips_big_got
)
7271 /* If this is a reference to an external symbol, we want
7272 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7274 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7279 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7281 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7282 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7283 If there is a base register we add it to $at before the
7284 lwc1 instructions. If there is a constant we include it
7285 in the lwc1 instructions. */
7287 expr1
.X_add_number
= offset_expr
.X_add_number
;
7288 offset_expr
.X_add_number
= 0;
7289 if (expr1
.X_add_number
< -0x8000
7290 || expr1
.X_add_number
>= 0x8000 - 4)
7291 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7292 gpdelay
= reg_needs_delay (mips_gp_register
);
7293 relax_start (offset_expr
.X_add_symbol
);
7294 macro_build (&offset_expr
, "lui", "t,u",
7295 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7296 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7297 AT
, AT
, mips_gp_register
);
7298 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7299 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7302 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7303 /* Itbl support may require additional care here. */
7304 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7305 BFD_RELOC_LO16
, AT
);
7306 expr1
.X_add_number
+= 4;
7308 /* Set mips_optimize to 2 to avoid inserting an undesired
7310 hold_mips_optimize
= mips_optimize
;
7312 /* Itbl support may require additional care here. */
7313 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7314 BFD_RELOC_LO16
, AT
);
7315 mips_optimize
= hold_mips_optimize
;
7316 expr1
.X_add_number
-= 4;
7319 offset_expr
.X_add_number
= expr1
.X_add_number
;
7321 macro_build (NULL
, "nop", "");
7322 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7323 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7326 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7327 /* Itbl support may require additional care here. */
7328 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7329 BFD_RELOC_LO16
, AT
);
7330 offset_expr
.X_add_number
+= 4;
7332 /* Set mips_optimize to 2 to avoid inserting an undesired
7334 hold_mips_optimize
= mips_optimize
;
7336 /* Itbl support may require additional care here. */
7337 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7338 BFD_RELOC_LO16
, AT
);
7339 mips_optimize
= hold_mips_optimize
;
7348 s
= HAVE_64BIT_GPRS
? "ld" : "lw";
7351 s
= HAVE_64BIT_GPRS
? "sd" : "sw";
7353 macro_build (&offset_expr
, s
, "t,o(b)", treg
,
7354 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7356 if (!HAVE_64BIT_GPRS
)
7358 offset_expr
.X_add_number
+= 4;
7359 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1,
7360 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
7365 /* New code added to support COPZ instructions.
7366 This code builds table entries out of the macros in mip_opcodes.
7367 R4000 uses interlocks to handle coproc delays.
7368 Other chips (like the R3000) require nops to be inserted for delays.
7370 FIXME: Currently, we require that the user handle delays.
7371 In order to fill delay slots for non-interlocked chips,
7372 we must have a way to specify delays based on the coprocessor.
7373 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7374 What are the side-effects of the cop instruction?
7375 What cache support might we have and what are its effects?
7376 Both coprocessor & memory require delays. how long???
7377 What registers are read/set/modified?
7379 If an itbl is provided to interpret cop instructions,
7380 this knowledge can be encoded in the itbl spec. */
7394 if (NO_ISA_COP (mips_opts
.arch
)
7395 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7397 as_bad (_("opcode not supported on this processor: %s"),
7398 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7402 /* For now we just do C (same as Cz). The parameter will be
7403 stored in insn_opcode by mips_ip. */
7404 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7408 move_register (dreg
, sreg
);
7414 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7415 macro_build (NULL
, "mflo", "d", dreg
);
7421 /* The MIPS assembler some times generates shifts and adds. I'm
7422 not trying to be that fancy. GCC should do this for us
7425 load_register (AT
, &imm_expr
, dbl
);
7426 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7427 macro_build (NULL
, "mflo", "d", dreg
);
7443 load_register (AT
, &imm_expr
, dbl
);
7444 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7445 macro_build (NULL
, "mflo", "d", dreg
);
7446 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7447 macro_build (NULL
, "mfhi", "d", AT
);
7449 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7452 expr1
.X_add_number
= 8;
7453 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7454 macro_build (NULL
, "nop", "", 0);
7455 macro_build (NULL
, "break", "c", 6);
7458 macro_build (NULL
, "mflo", "d", dreg
);
7474 load_register (AT
, &imm_expr
, dbl
);
7475 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7476 sreg
, imm
? AT
: treg
);
7477 macro_build (NULL
, "mfhi", "d", AT
);
7478 macro_build (NULL
, "mflo", "d", dreg
);
7480 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7483 expr1
.X_add_number
= 8;
7484 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7485 macro_build (NULL
, "nop", "", 0);
7486 macro_build (NULL
, "break", "c", 6);
7492 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7503 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7504 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7508 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7509 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7510 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7511 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7515 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7526 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7527 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7531 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7532 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7533 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7534 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7543 if (imm_expr
.X_op
!= O_constant
)
7544 as_bad (_("Improper rotate count"));
7545 rot
= imm_expr
.X_add_number
& 0x3f;
7546 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7548 rot
= (64 - rot
) & 0x3f;
7550 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7552 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7557 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7560 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7561 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7564 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7565 macro_build (NULL
, rr
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7566 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7574 if (imm_expr
.X_op
!= O_constant
)
7575 as_bad (_("Improper rotate count"));
7576 rot
= imm_expr
.X_add_number
& 0x1f;
7577 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7579 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7584 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7588 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7589 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7590 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7595 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7597 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7601 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7602 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7603 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7604 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7608 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7610 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7614 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7615 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7616 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7617 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7626 if (imm_expr
.X_op
!= O_constant
)
7627 as_bad (_("Improper rotate count"));
7628 rot
= imm_expr
.X_add_number
& 0x3f;
7629 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7632 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7634 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7639 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7642 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7643 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7646 macro_build (NULL
, rr
, "d,w,<", AT
, sreg
, rot
);
7647 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7648 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7656 if (imm_expr
.X_op
!= O_constant
)
7657 as_bad (_("Improper rotate count"));
7658 rot
= imm_expr
.X_add_number
& 0x1f;
7659 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7661 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7666 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7670 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7671 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7672 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7677 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7678 /* Even on a big endian machine $fn comes before $fn+1. We have
7679 to adjust when storing to memory. */
7680 macro_build (&offset_expr
, "swc1", "T,o(b)",
7681 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7682 offset_expr
.X_add_number
+= 4;
7683 macro_build (&offset_expr
, "swc1", "T,o(b)",
7684 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7689 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7691 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7694 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7695 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7700 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7702 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7707 as_warn (_("Instruction %s: result is always false"),
7709 move_register (dreg
, 0);
7712 if (CPU_HAS_SEQ (mips_opts
.arch
)
7713 && -512 <= imm_expr
.X_add_number
7714 && imm_expr
.X_add_number
< 512)
7716 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7717 (int) imm_expr
.X_add_number
);
7720 if (imm_expr
.X_op
== O_constant
7721 && imm_expr
.X_add_number
>= 0
7722 && imm_expr
.X_add_number
< 0x10000)
7724 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7726 else if (imm_expr
.X_op
== O_constant
7727 && imm_expr
.X_add_number
> -0x8000
7728 && imm_expr
.X_add_number
< 0)
7730 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7731 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7732 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7734 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7737 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7738 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7743 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7744 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7747 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7750 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7756 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7757 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7760 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7762 if (imm_expr
.X_op
== O_constant
7763 && imm_expr
.X_add_number
>= -0x8000
7764 && imm_expr
.X_add_number
< 0x8000)
7766 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7767 dreg
, sreg
, BFD_RELOC_LO16
);
7771 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7772 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7776 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7779 case M_SGT
: /* sreg > treg <==> treg < sreg */
7785 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7788 case M_SGT_I
: /* sreg > I <==> I < sreg */
7795 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7796 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7799 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7805 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7806 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7809 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7816 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7817 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7818 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7822 if (imm_expr
.X_op
== O_constant
7823 && imm_expr
.X_add_number
>= -0x8000
7824 && imm_expr
.X_add_number
< 0x8000)
7826 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7830 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7831 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7835 if (imm_expr
.X_op
== O_constant
7836 && imm_expr
.X_add_number
>= -0x8000
7837 && imm_expr
.X_add_number
< 0x8000)
7839 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7844 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7845 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7850 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7852 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7855 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7856 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7861 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7863 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7868 as_warn (_("Instruction %s: result is always true"),
7870 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7871 dreg
, 0, BFD_RELOC_LO16
);
7874 if (CPU_HAS_SEQ (mips_opts
.arch
)
7875 && -512 <= imm_expr
.X_add_number
7876 && imm_expr
.X_add_number
< 512)
7878 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
7879 (int) imm_expr
.X_add_number
);
7882 if (imm_expr
.X_op
== O_constant
7883 && imm_expr
.X_add_number
>= 0
7884 && imm_expr
.X_add_number
< 0x10000)
7886 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7888 else if (imm_expr
.X_op
== O_constant
7889 && imm_expr
.X_add_number
> -0x8000
7890 && imm_expr
.X_add_number
< 0)
7892 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7893 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7894 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7896 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7899 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7900 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
7905 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7906 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7909 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7915 if (imm_expr
.X_op
== O_constant
7916 && imm_expr
.X_add_number
> -0x8000
7917 && imm_expr
.X_add_number
<= 0x8000)
7919 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7920 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7921 dreg
, sreg
, BFD_RELOC_LO16
);
7925 load_register (AT
, &imm_expr
, dbl
);
7926 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7932 if (imm_expr
.X_op
== O_constant
7933 && imm_expr
.X_add_number
> -0x8000
7934 && imm_expr
.X_add_number
<= 0x8000)
7936 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7937 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7938 dreg
, sreg
, BFD_RELOC_LO16
);
7942 load_register (AT
, &imm_expr
, dbl
);
7943 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7965 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7966 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7971 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
7973 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7974 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7977 * Is the double cfc1 instruction a bug in the mips assembler;
7978 * or is there a reason for it?
7981 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7982 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7983 macro_build (NULL
, "nop", "");
7984 expr1
.X_add_number
= 3;
7985 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7986 expr1
.X_add_number
= 2;
7987 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7988 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7989 macro_build (NULL
, "nop", "");
7990 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7992 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7993 macro_build (NULL
, "nop", "");
8004 if (offset_expr
.X_add_number
>= 0x7fff)
8005 as_bad (_("operand overflow"));
8006 if (! target_big_endian
)
8007 ++offset_expr
.X_add_number
;
8008 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8009 if (! target_big_endian
)
8010 --offset_expr
.X_add_number
;
8012 ++offset_expr
.X_add_number
;
8013 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8014 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
8015 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8028 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8029 as_bad (_("operand overflow"));
8037 if (! target_big_endian
)
8038 offset_expr
.X_add_number
+= off
;
8039 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8040 if (! target_big_endian
)
8041 offset_expr
.X_add_number
-= off
;
8043 offset_expr
.X_add_number
+= off
;
8044 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
8046 /* If necessary, move the result in tempreg the final destination. */
8047 if (treg
== tempreg
)
8049 /* Protect second load's delay slot. */
8051 move_register (treg
, tempreg
);
8065 load_address (AT
, &offset_expr
, &used_at
);
8067 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8068 if (! target_big_endian
)
8069 expr1
.X_add_number
= off
;
8071 expr1
.X_add_number
= 0;
8072 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8073 if (! target_big_endian
)
8074 expr1
.X_add_number
= 0;
8076 expr1
.X_add_number
= off
;
8077 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8083 load_address (AT
, &offset_expr
, &used_at
);
8085 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8086 if (target_big_endian
)
8087 expr1
.X_add_number
= 0;
8088 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
8089 treg
, BFD_RELOC_LO16
, AT
);
8090 if (target_big_endian
)
8091 expr1
.X_add_number
= 1;
8093 expr1
.X_add_number
= 0;
8094 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8095 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8096 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8101 if (offset_expr
.X_add_number
>= 0x7fff)
8102 as_bad (_("operand overflow"));
8103 if (target_big_endian
)
8104 ++offset_expr
.X_add_number
;
8105 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8106 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
8107 if (target_big_endian
)
8108 --offset_expr
.X_add_number
;
8110 ++offset_expr
.X_add_number
;
8111 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8124 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8125 as_bad (_("operand overflow"));
8126 if (! target_big_endian
)
8127 offset_expr
.X_add_number
+= off
;
8128 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8129 if (! target_big_endian
)
8130 offset_expr
.X_add_number
-= off
;
8132 offset_expr
.X_add_number
+= off
;
8133 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8147 load_address (AT
, &offset_expr
, &used_at
);
8149 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8150 if (! target_big_endian
)
8151 expr1
.X_add_number
= off
;
8153 expr1
.X_add_number
= 0;
8154 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8155 if (! target_big_endian
)
8156 expr1
.X_add_number
= 0;
8158 expr1
.X_add_number
= off
;
8159 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8164 load_address (AT
, &offset_expr
, &used_at
);
8166 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8167 if (! target_big_endian
)
8168 expr1
.X_add_number
= 0;
8169 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8170 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8171 if (! target_big_endian
)
8172 expr1
.X_add_number
= 1;
8174 expr1
.X_add_number
= 0;
8175 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8176 if (! target_big_endian
)
8177 expr1
.X_add_number
= 0;
8179 expr1
.X_add_number
= 1;
8180 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8181 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8182 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8186 /* FIXME: Check if this is one of the itbl macros, since they
8187 are added dynamically. */
8188 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8191 if (!mips_opts
.at
&& used_at
)
8192 as_bad (_("Macro used $at after \".set noat\""));
8195 /* Implement macros in mips16 mode. */
8198 mips16_macro (struct mips_cl_insn
*ip
)
8201 int xreg
, yreg
, zreg
, tmp
;
8204 const char *s
, *s2
, *s3
;
8206 mask
= ip
->insn_mo
->mask
;
8208 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8209 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8210 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8212 expr1
.X_op
= O_constant
;
8213 expr1
.X_op_symbol
= NULL
;
8214 expr1
.X_add_symbol
= NULL
;
8215 expr1
.X_add_number
= 1;
8235 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8236 expr1
.X_add_number
= 2;
8237 macro_build (&expr1
, "bnez", "x,p", yreg
);
8238 macro_build (NULL
, "break", "6", 7);
8240 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8241 since that causes an overflow. We should do that as well,
8242 but I don't see how to do the comparisons without a temporary
8245 macro_build (NULL
, s
, "x", zreg
);
8265 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8266 expr1
.X_add_number
= 2;
8267 macro_build (&expr1
, "bnez", "x,p", yreg
);
8268 macro_build (NULL
, "break", "6", 7);
8270 macro_build (NULL
, s2
, "x", zreg
);
8276 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8277 macro_build (NULL
, "mflo", "x", zreg
);
8285 if (imm_expr
.X_op
!= O_constant
)
8286 as_bad (_("Unsupported large constant"));
8287 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8288 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8292 if (imm_expr
.X_op
!= O_constant
)
8293 as_bad (_("Unsupported large constant"));
8294 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8295 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8299 if (imm_expr
.X_op
!= O_constant
)
8300 as_bad (_("Unsupported large constant"));
8301 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8302 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8324 goto do_reverse_branch
;
8328 goto do_reverse_branch
;
8340 goto do_reverse_branch
;
8351 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8352 macro_build (&offset_expr
, s2
, "p");
8379 goto do_addone_branch_i
;
8384 goto do_addone_branch_i
;
8399 goto do_addone_branch_i
;
8406 if (imm_expr
.X_op
!= O_constant
)
8407 as_bad (_("Unsupported large constant"));
8408 ++imm_expr
.X_add_number
;
8411 macro_build (&imm_expr
, s
, s3
, xreg
);
8412 macro_build (&offset_expr
, s2
, "p");
8416 expr1
.X_add_number
= 0;
8417 macro_build (&expr1
, "slti", "x,8", yreg
);
8419 move_register (xreg
, yreg
);
8420 expr1
.X_add_number
= 2;
8421 macro_build (&expr1
, "bteqz", "p");
8422 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8426 /* For consistency checking, verify that all bits are specified either
8427 by the match/mask part of the instruction definition, or by the
8430 validate_mips_insn (const struct mips_opcode
*opc
)
8432 const char *p
= opc
->args
;
8434 unsigned long used_bits
= opc
->mask
;
8436 if ((used_bits
& opc
->match
) != opc
->match
)
8438 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8439 opc
->name
, opc
->args
);
8442 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8452 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8453 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8454 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8455 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8456 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8457 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8458 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8459 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8460 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8461 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8462 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8463 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8464 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8466 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8467 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8468 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8469 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8470 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8471 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8472 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8473 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8474 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8475 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8478 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8479 c
, opc
->name
, opc
->args
);
8483 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8484 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8486 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8487 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8488 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8489 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8491 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8492 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8494 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8495 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8497 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8498 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8499 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8500 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8501 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8502 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8503 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8504 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8505 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8506 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8507 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8508 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8509 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8510 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8511 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8512 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8513 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8515 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8516 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8517 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8518 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8520 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8521 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8522 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8523 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8524 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8525 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8526 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8527 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8528 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8531 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8532 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8533 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8534 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8535 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8538 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8539 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8540 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8541 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8542 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8543 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8544 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8545 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8546 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8547 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8548 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8549 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8550 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8551 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8552 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8553 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8554 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8555 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8557 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8558 c
, opc
->name
, opc
->args
);
8562 if (used_bits
!= 0xffffffff)
8564 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8565 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8571 /* UDI immediates. */
8579 static const struct mips_immed mips_immed
[] = {
8580 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8581 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8582 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8583 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8587 /* Check whether an odd floating-point register is allowed. */
8589 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8591 const char *s
= insn
->name
;
8593 if (insn
->pinfo
== INSN_MACRO
)
8594 /* Let a macro pass, we'll catch it later when it is expanded. */
8597 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8599 /* Allow odd registers for single-precision ops. */
8600 switch (insn
->pinfo
& (FP_S
| FP_D
))
8604 return 1; /* both single precision - ok */
8606 return 0; /* both double precision - fail */
8611 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8612 s
= strchr (insn
->name
, '.');
8614 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8615 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8618 /* Single-precision coprocessor loads and moves are OK too. */
8619 if ((insn
->pinfo
& FP_S
)
8620 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8621 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8627 /* This routine assembles an instruction into its binary format. As a
8628 side effect, it sets one of the global variables imm_reloc or
8629 offset_reloc to the type of relocation to do if one of the operands
8630 is an address expression. */
8633 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8638 struct mips_opcode
*insn
;
8641 unsigned int lastregno
= 0;
8642 unsigned int lastpos
= 0;
8643 unsigned int limlo
, limhi
;
8646 offsetT min_range
, max_range
;
8652 /* If the instruction contains a '.', we first try to match an instruction
8653 including the '.'. Then we try again without the '.'. */
8655 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8658 /* If we stopped on whitespace, then replace the whitespace with null for
8659 the call to hash_find. Save the character we replaced just in case we
8660 have to re-parse the instruction. */
8667 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8669 /* If we didn't find the instruction in the opcode table, try again, but
8670 this time with just the instruction up to, but not including the
8674 /* Restore the character we overwrite above (if any). */
8678 /* Scan up to the first '.' or whitespace. */
8680 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8684 /* If we did not find a '.', then we can quit now. */
8687 insn_error
= _("unrecognized opcode");
8691 /* Lookup the instruction in the hash table. */
8693 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8695 insn_error
= _("unrecognized opcode");
8705 gas_assert (strcmp (insn
->name
, str
) == 0);
8707 ok
= is_opcode_valid (insn
);
8710 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8711 && strcmp (insn
->name
, insn
[1].name
) == 0)
8720 static char buf
[100];
8722 _("opcode not supported on this processor: %s (%s)"),
8723 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8724 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8733 create_insn (ip
, insn
);
8736 lastregno
= 0xffffffff;
8737 for (args
= insn
->args
;; ++args
)
8741 s
+= strspn (s
, " \t");
8745 case '\0': /* end of args */
8750 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8751 my_getExpression (&imm_expr
, s
);
8752 check_absolute_expr (ip
, &imm_expr
);
8753 if ((unsigned long) imm_expr
.X_add_number
!= 1
8754 && (unsigned long) imm_expr
.X_add_number
!= 3)
8756 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8757 (unsigned long) imm_expr
.X_add_number
);
8759 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8760 imm_expr
.X_op
= O_absent
;
8764 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8765 my_getExpression (&imm_expr
, s
);
8766 check_absolute_expr (ip
, &imm_expr
);
8767 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8769 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8770 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8772 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8773 imm_expr
.X_op
= O_absent
;
8777 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8778 my_getExpression (&imm_expr
, s
);
8779 check_absolute_expr (ip
, &imm_expr
);
8780 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8782 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8783 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8785 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8786 imm_expr
.X_op
= O_absent
;
8790 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8791 my_getExpression (&imm_expr
, s
);
8792 check_absolute_expr (ip
, &imm_expr
);
8793 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8795 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8796 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8798 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8799 imm_expr
.X_op
= O_absent
;
8803 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8804 my_getExpression (&imm_expr
, s
);
8805 check_absolute_expr (ip
, &imm_expr
);
8806 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8808 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8809 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8811 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8812 imm_expr
.X_op
= O_absent
;
8816 case '7': /* four dsp accumulators in bits 11,12 */
8817 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8818 s
[3] >= '0' && s
[3] <= '3')
8822 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8826 as_bad (_("Invalid dsp acc register"));
8829 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8830 my_getExpression (&imm_expr
, s
);
8831 check_absolute_expr (ip
, &imm_expr
);
8832 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8834 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8836 (unsigned long) imm_expr
.X_add_number
);
8838 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8839 imm_expr
.X_op
= O_absent
;
8843 case '9': /* four dsp accumulators in bits 21,22 */
8844 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8845 s
[3] >= '0' && s
[3] <= '3')
8849 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8853 as_bad (_("Invalid dsp acc register"));
8856 case '0': /* dsp 6-bit signed immediate in bit 20 */
8857 my_getExpression (&imm_expr
, s
);
8858 check_absolute_expr (ip
, &imm_expr
);
8859 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8860 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8861 if (imm_expr
.X_add_number
< min_range
||
8862 imm_expr
.X_add_number
> max_range
)
8864 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8865 (long) min_range
, (long) max_range
,
8866 (long) imm_expr
.X_add_number
);
8868 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8869 imm_expr
.X_op
= O_absent
;
8873 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8874 my_getExpression (&imm_expr
, s
);
8875 check_absolute_expr (ip
, &imm_expr
);
8876 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8878 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8880 (unsigned long) imm_expr
.X_add_number
);
8882 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8883 imm_expr
.X_op
= O_absent
;
8887 case ':': /* dsp 7-bit signed immediate in bit 19 */
8888 my_getExpression (&imm_expr
, s
);
8889 check_absolute_expr (ip
, &imm_expr
);
8890 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8891 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8892 if (imm_expr
.X_add_number
< min_range
||
8893 imm_expr
.X_add_number
> max_range
)
8895 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8896 (long) min_range
, (long) max_range
,
8897 (long) imm_expr
.X_add_number
);
8899 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8900 imm_expr
.X_op
= O_absent
;
8904 case '@': /* dsp 10-bit signed immediate in bit 16 */
8905 my_getExpression (&imm_expr
, s
);
8906 check_absolute_expr (ip
, &imm_expr
);
8907 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8908 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8909 if (imm_expr
.X_add_number
< min_range
||
8910 imm_expr
.X_add_number
> max_range
)
8912 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8913 (long) min_range
, (long) max_range
,
8914 (long) imm_expr
.X_add_number
);
8916 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8917 imm_expr
.X_op
= O_absent
;
8921 case '!': /* MT usermode flag bit. */
8922 my_getExpression (&imm_expr
, s
);
8923 check_absolute_expr (ip
, &imm_expr
);
8924 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8925 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8926 (unsigned long) imm_expr
.X_add_number
);
8927 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8928 imm_expr
.X_op
= O_absent
;
8932 case '$': /* MT load high flag bit. */
8933 my_getExpression (&imm_expr
, s
);
8934 check_absolute_expr (ip
, &imm_expr
);
8935 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8936 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8937 (unsigned long) imm_expr
.X_add_number
);
8938 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8939 imm_expr
.X_op
= O_absent
;
8943 case '*': /* four dsp accumulators in bits 18,19 */
8944 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8945 s
[3] >= '0' && s
[3] <= '3')
8949 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8953 as_bad (_("Invalid dsp/smartmips acc register"));
8956 case '&': /* four dsp accumulators in bits 13,14 */
8957 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8958 s
[3] >= '0' && s
[3] <= '3')
8962 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8966 as_bad (_("Invalid dsp/smartmips acc register"));
8978 INSERT_OPERAND (RS
, *ip
, lastregno
);
8982 INSERT_OPERAND (RT
, *ip
, lastregno
);
8986 INSERT_OPERAND (FT
, *ip
, lastregno
);
8990 INSERT_OPERAND (FS
, *ip
, lastregno
);
8996 /* Handle optional base register.
8997 Either the base register is omitted or
8998 we must have a left paren. */
8999 /* This is dependent on the next operand specifier
9000 is a base register specification. */
9001 gas_assert (args
[1] == 'b' || args
[1] == '5'
9002 || args
[1] == '-' || args
[1] == '4');
9006 case ')': /* these must match exactly */
9013 case '+': /* Opcode extension character. */
9016 case '1': /* UDI immediates. */
9021 const struct mips_immed
*imm
= mips_immed
;
9023 while (imm
->type
&& imm
->type
!= *args
)
9027 my_getExpression (&imm_expr
, s
);
9028 check_absolute_expr (ip
, &imm_expr
);
9029 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
9031 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9032 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
9033 (unsigned long) imm_expr
.X_add_number
,
9034 (unsigned long) imm_expr
.X_add_number
);
9035 imm_expr
.X_add_number
&= imm
->mask
;
9037 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
9039 imm_expr
.X_op
= O_absent
;
9044 case 'A': /* ins/ext position, becomes LSB. */
9053 my_getExpression (&imm_expr
, s
);
9054 check_absolute_expr (ip
, &imm_expr
);
9055 if ((unsigned long) imm_expr
.X_add_number
< limlo
9056 || (unsigned long) imm_expr
.X_add_number
> limhi
)
9058 as_bad (_("Improper position (%lu)"),
9059 (unsigned long) imm_expr
.X_add_number
);
9060 imm_expr
.X_add_number
= limlo
;
9062 lastpos
= imm_expr
.X_add_number
;
9063 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9064 imm_expr
.X_op
= O_absent
;
9068 case 'B': /* ins size, becomes MSB. */
9077 my_getExpression (&imm_expr
, s
);
9078 check_absolute_expr (ip
, &imm_expr
);
9079 /* Check for negative input so that small negative numbers
9080 will not succeed incorrectly. The checks against
9081 (pos+size) transitively check "size" itself,
9082 assuming that "pos" is reasonable. */
9083 if ((long) imm_expr
.X_add_number
< 0
9084 || ((unsigned long) imm_expr
.X_add_number
9086 || ((unsigned long) imm_expr
.X_add_number
9089 as_bad (_("Improper insert size (%lu, position %lu)"),
9090 (unsigned long) imm_expr
.X_add_number
,
9091 (unsigned long) lastpos
);
9092 imm_expr
.X_add_number
= limlo
- lastpos
;
9094 INSERT_OPERAND (INSMSB
, *ip
,
9095 lastpos
+ imm_expr
.X_add_number
- 1);
9096 imm_expr
.X_op
= O_absent
;
9100 case 'C': /* ext size, becomes MSBD. */
9113 my_getExpression (&imm_expr
, s
);
9114 check_absolute_expr (ip
, &imm_expr
);
9115 /* Check for negative input so that small negative numbers
9116 will not succeed incorrectly. The checks against
9117 (pos+size) transitively check "size" itself,
9118 assuming that "pos" is reasonable. */
9119 if ((long) imm_expr
.X_add_number
< 0
9120 || ((unsigned long) imm_expr
.X_add_number
9122 || ((unsigned long) imm_expr
.X_add_number
9125 as_bad (_("Improper extract size (%lu, position %lu)"),
9126 (unsigned long) imm_expr
.X_add_number
,
9127 (unsigned long) lastpos
);
9128 imm_expr
.X_add_number
= limlo
- lastpos
;
9130 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9131 imm_expr
.X_op
= O_absent
;
9136 /* +D is for disassembly only; never match. */
9140 /* "+I" is like "I", except that imm2_expr is used. */
9141 my_getExpression (&imm2_expr
, s
);
9142 if (imm2_expr
.X_op
!= O_big
9143 && imm2_expr
.X_op
!= O_constant
)
9144 insn_error
= _("absolute expression required");
9145 if (HAVE_32BIT_GPRS
)
9146 normalize_constant_expr (&imm2_expr
);
9150 case 'T': /* Coprocessor register. */
9151 /* +T is for disassembly only; never match. */
9154 case 't': /* Coprocessor register number. */
9155 if (s
[0] == '$' && ISDIGIT (s
[1]))
9165 while (ISDIGIT (*s
));
9167 as_bad (_("Invalid register number (%d)"), regno
);
9170 INSERT_OPERAND (RT
, *ip
, regno
);
9175 as_bad (_("Invalid coprocessor 0 register number"));
9179 /* bbit[01] and bbit[01]32 bit index. Give error if index
9180 is not in the valid range. */
9181 my_getExpression (&imm_expr
, s
);
9182 check_absolute_expr (ip
, &imm_expr
);
9183 if ((unsigned) imm_expr
.X_add_number
> 31)
9185 as_bad (_("Improper bit index (%lu)"),
9186 (unsigned long) imm_expr
.X_add_number
);
9187 imm_expr
.X_add_number
= 0;
9189 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9190 imm_expr
.X_op
= O_absent
;
9195 /* bbit[01] bit index when bbit is used but we generate
9196 bbit[01]32 because the index is over 32. Move to the
9197 next candidate if index is not in the valid range. */
9198 my_getExpression (&imm_expr
, s
);
9199 check_absolute_expr (ip
, &imm_expr
);
9200 if ((unsigned) imm_expr
.X_add_number
< 32
9201 || (unsigned) imm_expr
.X_add_number
> 63)
9203 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9204 imm_expr
.X_op
= O_absent
;
9209 /* cins, cins32, exts and exts32 position field. Give error
9210 if it's not in the valid range. */
9211 my_getExpression (&imm_expr
, s
);
9212 check_absolute_expr (ip
, &imm_expr
);
9213 if ((unsigned) imm_expr
.X_add_number
> 31)
9215 as_bad (_("Improper position (%lu)"),
9216 (unsigned long) imm_expr
.X_add_number
);
9217 imm_expr
.X_add_number
= 0;
9219 /* Make the pos explicit to simplify +S. */
9220 lastpos
= imm_expr
.X_add_number
+ 32;
9221 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9222 imm_expr
.X_op
= O_absent
;
9227 /* cins, cins32, exts and exts32 position field. Move to
9228 the next candidate if it's not in the valid range. */
9229 my_getExpression (&imm_expr
, s
);
9230 check_absolute_expr (ip
, &imm_expr
);
9231 if ((unsigned) imm_expr
.X_add_number
< 32
9232 || (unsigned) imm_expr
.X_add_number
> 63)
9234 lastpos
= imm_expr
.X_add_number
;
9235 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9236 imm_expr
.X_op
= O_absent
;
9241 /* cins and exts length-minus-one field. */
9242 my_getExpression (&imm_expr
, s
);
9243 check_absolute_expr (ip
, &imm_expr
);
9244 if ((unsigned long) imm_expr
.X_add_number
> 31)
9246 as_bad (_("Improper size (%lu)"),
9247 (unsigned long) imm_expr
.X_add_number
);
9248 imm_expr
.X_add_number
= 0;
9250 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9251 imm_expr
.X_op
= O_absent
;
9256 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9257 length-minus-one field. */
9258 my_getExpression (&imm_expr
, s
);
9259 check_absolute_expr (ip
, &imm_expr
);
9260 if ((long) imm_expr
.X_add_number
< 0
9261 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9263 as_bad (_("Improper size (%lu)"),
9264 (unsigned long) imm_expr
.X_add_number
);
9265 imm_expr
.X_add_number
= 0;
9267 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9268 imm_expr
.X_op
= O_absent
;
9273 /* seqi/snei immediate field. */
9274 my_getExpression (&imm_expr
, s
);
9275 check_absolute_expr (ip
, &imm_expr
);
9276 if ((long) imm_expr
.X_add_number
< -512
9277 || (long) imm_expr
.X_add_number
>= 512)
9279 as_bad (_("Improper immediate (%ld)"),
9280 (long) imm_expr
.X_add_number
);
9281 imm_expr
.X_add_number
= 0;
9283 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9284 imm_expr
.X_op
= O_absent
;
9289 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9290 *args
, insn
->name
, insn
->args
);
9291 /* Further processing is fruitless. */
9296 case '<': /* must be at least one digit */
9298 * According to the manual, if the shift amount is greater
9299 * than 31 or less than 0, then the shift amount should be
9300 * mod 32. In reality the mips assembler issues an error.
9301 * We issue a warning and mask out all but the low 5 bits.
9303 my_getExpression (&imm_expr
, s
);
9304 check_absolute_expr (ip
, &imm_expr
);
9305 if ((unsigned long) imm_expr
.X_add_number
> 31)
9306 as_warn (_("Improper shift amount (%lu)"),
9307 (unsigned long) imm_expr
.X_add_number
);
9308 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9309 imm_expr
.X_op
= O_absent
;
9313 case '>': /* shift amount minus 32 */
9314 my_getExpression (&imm_expr
, s
);
9315 check_absolute_expr (ip
, &imm_expr
);
9316 if ((unsigned long) imm_expr
.X_add_number
< 32
9317 || (unsigned long) imm_expr
.X_add_number
> 63)
9319 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9320 imm_expr
.X_op
= O_absent
;
9324 case 'k': /* cache code */
9325 case 'h': /* prefx code */
9326 case '1': /* sync type */
9327 my_getExpression (&imm_expr
, s
);
9328 check_absolute_expr (ip
, &imm_expr
);
9329 if ((unsigned long) imm_expr
.X_add_number
> 31)
9330 as_warn (_("Invalid value for `%s' (%lu)"),
9332 (unsigned long) imm_expr
.X_add_number
);
9335 if (mips_fix_cn63xxp1
&& strcmp ("pref", insn
->name
) == 0)
9336 switch (imm_expr
.X_add_number
)
9345 case 31: /* These are ok. */
9348 default: /* The rest must be changed to 28. */
9349 imm_expr
.X_add_number
= 28;
9352 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9354 else if (*args
== 'h')
9355 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9357 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9358 imm_expr
.X_op
= O_absent
;
9362 case 'c': /* break code */
9363 my_getExpression (&imm_expr
, s
);
9364 check_absolute_expr (ip
, &imm_expr
);
9365 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9366 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9368 (unsigned long) imm_expr
.X_add_number
);
9369 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9370 imm_expr
.X_op
= O_absent
;
9374 case 'q': /* lower break code */
9375 my_getExpression (&imm_expr
, s
);
9376 check_absolute_expr (ip
, &imm_expr
);
9377 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9378 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9380 (unsigned long) imm_expr
.X_add_number
);
9381 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9382 imm_expr
.X_op
= O_absent
;
9386 case 'B': /* 20-bit syscall/break code. */
9387 my_getExpression (&imm_expr
, s
);
9388 check_absolute_expr (ip
, &imm_expr
);
9389 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9390 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9392 (unsigned long) imm_expr
.X_add_number
);
9393 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9394 imm_expr
.X_op
= O_absent
;
9398 case 'C': /* Coprocessor code */
9399 my_getExpression (&imm_expr
, s
);
9400 check_absolute_expr (ip
, &imm_expr
);
9401 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9403 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9404 (unsigned long) imm_expr
.X_add_number
);
9405 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9407 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9408 imm_expr
.X_op
= O_absent
;
9412 case 'J': /* 19-bit wait code. */
9413 my_getExpression (&imm_expr
, s
);
9414 check_absolute_expr (ip
, &imm_expr
);
9415 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9417 as_warn (_("Illegal 19-bit code (%lu)"),
9418 (unsigned long) imm_expr
.X_add_number
);
9419 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9421 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9422 imm_expr
.X_op
= O_absent
;
9426 case 'P': /* Performance register. */
9427 my_getExpression (&imm_expr
, s
);
9428 check_absolute_expr (ip
, &imm_expr
);
9429 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9430 as_warn (_("Invalid performance register (%lu)"),
9431 (unsigned long) imm_expr
.X_add_number
);
9432 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9433 imm_expr
.X_op
= O_absent
;
9437 case 'G': /* Coprocessor destination register. */
9438 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9439 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9441 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9442 INSERT_OPERAND (RD
, *ip
, regno
);
9451 case 'b': /* base register */
9452 case 'd': /* destination register */
9453 case 's': /* source register */
9454 case 't': /* target register */
9455 case 'r': /* both target and source */
9456 case 'v': /* both dest and source */
9457 case 'w': /* both dest and target */
9458 case 'E': /* coprocessor target register */
9459 case 'K': /* 'rdhwr' destination register */
9460 case 'x': /* ignore register name */
9461 case 'z': /* must be zero register */
9462 case 'U': /* destination register (clo/clz). */
9463 case 'g': /* coprocessor destination register */
9465 if (*args
== 'E' || *args
== 'K')
9466 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9469 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9470 if (regno
== AT
&& mips_opts
.at
)
9472 if (mips_opts
.at
== ATREG
)
9473 as_warn (_("used $at without \".set noat\""));
9475 as_warn (_("used $%u with \".set at=$%u\""),
9476 regno
, mips_opts
.at
);
9486 if (c
== 'r' || c
== 'v' || c
== 'w')
9493 /* 'z' only matches $0. */
9494 if (c
== 'z' && regno
!= 0)
9497 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
9499 if (regno
== lastregno
)
9501 insn_error
= _("source and destination must be different");
9504 if (regno
== 31 && lastregno
== 0xffffffff)
9506 insn_error
= _("a destination register must be supplied");
9510 /* Now that we have assembled one operand, we use the args string
9511 * to figure out where it goes in the instruction. */
9518 INSERT_OPERAND (RS
, *ip
, regno
);
9524 INSERT_OPERAND (RD
, *ip
, regno
);
9527 INSERT_OPERAND (RD
, *ip
, regno
);
9528 INSERT_OPERAND (RT
, *ip
, regno
);
9533 INSERT_OPERAND (RT
, *ip
, regno
);
9536 /* This case exists because on the r3000 trunc
9537 expands into a macro which requires a gp
9538 register. On the r6000 or r4000 it is
9539 assembled into a single instruction which
9540 ignores the register. Thus the insn version
9541 is MIPS_ISA2 and uses 'x', and the macro
9542 version is MIPS_ISA1 and uses 't'. */
9545 /* This case is for the div instruction, which
9546 acts differently if the destination argument
9547 is $0. This only matches $0, and is checked
9548 outside the switch. */
9551 /* Itbl operand; not yet implemented. FIXME ?? */
9553 /* What about all other operands like 'i', which
9554 can be specified in the opcode table? */
9563 INSERT_OPERAND (RS
, *ip
, lastregno
);
9566 INSERT_OPERAND (RT
, *ip
, lastregno
);
9571 case 'O': /* MDMX alignment immediate constant. */
9572 my_getExpression (&imm_expr
, s
);
9573 check_absolute_expr (ip
, &imm_expr
);
9574 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9575 as_warn (_("Improper align amount (%ld), using low bits"),
9576 (long) imm_expr
.X_add_number
);
9577 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9578 imm_expr
.X_op
= O_absent
;
9582 case 'Q': /* MDMX vector, element sel, or const. */
9585 /* MDMX Immediate. */
9586 my_getExpression (&imm_expr
, s
);
9587 check_absolute_expr (ip
, &imm_expr
);
9588 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9589 as_warn (_("Invalid MDMX Immediate (%ld)"),
9590 (long) imm_expr
.X_add_number
);
9591 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9592 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9593 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9595 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9596 imm_expr
.X_op
= O_absent
;
9600 /* Not MDMX Immediate. Fall through. */
9601 case 'X': /* MDMX destination register. */
9602 case 'Y': /* MDMX source register. */
9603 case 'Z': /* MDMX target register. */
9605 case 'D': /* floating point destination register */
9606 case 'S': /* floating point source register */
9607 case 'T': /* floating point target register */
9608 case 'R': /* floating point source register */
9613 || (mips_opts
.ase_mdmx
9614 && (ip
->insn_mo
->pinfo
& FP_D
)
9615 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9616 | INSN_COPROC_MEMORY_DELAY
9617 | INSN_LOAD_COPROC_DELAY
9618 | INSN_LOAD_MEMORY_DELAY
9619 | INSN_STORE_MEMORY
))))
9622 if (reg_lookup (&s
, rtype
, ®no
))
9624 if ((regno
& 1) != 0
9626 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9627 as_warn (_("Float register should be even, was %d"),
9635 if (c
== 'V' || c
== 'W')
9646 INSERT_OPERAND (FD
, *ip
, regno
);
9651 INSERT_OPERAND (FS
, *ip
, regno
);
9654 /* This is like 'Z', but also needs to fix the MDMX
9655 vector/scalar select bits. Note that the
9656 scalar immediate case is handled above. */
9659 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9660 int max_el
= (is_qh
? 3 : 7);
9662 my_getExpression(&imm_expr
, s
);
9663 check_absolute_expr (ip
, &imm_expr
);
9665 if (imm_expr
.X_add_number
> max_el
)
9666 as_bad (_("Bad element selector %ld"),
9667 (long) imm_expr
.X_add_number
);
9668 imm_expr
.X_add_number
&= max_el
;
9669 ip
->insn_opcode
|= (imm_expr
.X_add_number
9672 imm_expr
.X_op
= O_absent
;
9674 as_warn (_("Expecting ']' found '%s'"), s
);
9680 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9681 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9684 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9691 INSERT_OPERAND (FT
, *ip
, regno
);
9694 INSERT_OPERAND (FR
, *ip
, regno
);
9704 INSERT_OPERAND (FS
, *ip
, lastregno
);
9707 INSERT_OPERAND (FT
, *ip
, lastregno
);
9713 my_getExpression (&imm_expr
, s
);
9714 if (imm_expr
.X_op
!= O_big
9715 && imm_expr
.X_op
!= O_constant
)
9716 insn_error
= _("absolute expression required");
9717 if (HAVE_32BIT_GPRS
)
9718 normalize_constant_expr (&imm_expr
);
9723 my_getExpression (&offset_expr
, s
);
9724 normalize_address_expr (&offset_expr
);
9725 *imm_reloc
= BFD_RELOC_32
;
9738 unsigned char temp
[8];
9740 unsigned int length
;
9745 /* These only appear as the last operand in an
9746 instruction, and every instruction that accepts
9747 them in any variant accepts them in all variants.
9748 This means we don't have to worry about backing out
9749 any changes if the instruction does not match.
9751 The difference between them is the size of the
9752 floating point constant and where it goes. For 'F'
9753 and 'L' the constant is 64 bits; for 'f' and 'l' it
9754 is 32 bits. Where the constant is placed is based
9755 on how the MIPS assembler does things:
9758 f -- immediate value
9761 The .lit4 and .lit8 sections are only used if
9762 permitted by the -G argument.
9764 The code below needs to know whether the target register
9765 is 32 or 64 bits wide. It relies on the fact 'f' and
9766 'F' are used with GPR-based instructions and 'l' and
9767 'L' are used with FPR-based instructions. */
9769 f64
= *args
== 'F' || *args
== 'L';
9770 using_gprs
= *args
== 'F' || *args
== 'f';
9772 save_in
= input_line_pointer
;
9773 input_line_pointer
= s
;
9774 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9776 s
= input_line_pointer
;
9777 input_line_pointer
= save_in
;
9778 if (err
!= NULL
&& *err
!= '\0')
9780 as_bad (_("Bad floating point constant: %s"), err
);
9781 memset (temp
, '\0', sizeof temp
);
9782 length
= f64
? 8 : 4;
9785 gas_assert (length
== (unsigned) (f64
? 8 : 4));
9789 && (g_switch_value
< 4
9790 || (temp
[0] == 0 && temp
[1] == 0)
9791 || (temp
[2] == 0 && temp
[3] == 0))))
9793 imm_expr
.X_op
= O_constant
;
9794 if (! target_big_endian
)
9795 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9797 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9800 && ! mips_disable_float_construction
9801 /* Constants can only be constructed in GPRs and
9802 copied to FPRs if the GPRs are at least as wide
9803 as the FPRs. Force the constant into memory if
9804 we are using 64-bit FPRs but the GPRs are only
9807 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9808 && ((temp
[0] == 0 && temp
[1] == 0)
9809 || (temp
[2] == 0 && temp
[3] == 0))
9810 && ((temp
[4] == 0 && temp
[5] == 0)
9811 || (temp
[6] == 0 && temp
[7] == 0)))
9813 /* The value is simple enough to load with a couple of
9814 instructions. If using 32-bit registers, set
9815 imm_expr to the high order 32 bits and offset_expr to
9816 the low order 32 bits. Otherwise, set imm_expr to
9817 the entire 64 bit constant. */
9818 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9820 imm_expr
.X_op
= O_constant
;
9821 offset_expr
.X_op
= O_constant
;
9822 if (! target_big_endian
)
9824 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9825 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9829 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9830 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9832 if (offset_expr
.X_add_number
== 0)
9833 offset_expr
.X_op
= O_absent
;
9835 else if (sizeof (imm_expr
.X_add_number
) > 4)
9837 imm_expr
.X_op
= O_constant
;
9838 if (! target_big_endian
)
9839 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9841 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9845 imm_expr
.X_op
= O_big
;
9846 imm_expr
.X_add_number
= 4;
9847 if (! target_big_endian
)
9849 generic_bignum
[0] = bfd_getl16 (temp
);
9850 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9851 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9852 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9856 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9857 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9858 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9859 generic_bignum
[3] = bfd_getb16 (temp
);
9865 const char *newname
;
9868 /* Switch to the right section. */
9870 subseg
= now_subseg
;
9873 default: /* unused default case avoids warnings. */
9875 newname
= RDATA_SECTION_NAME
;
9876 if (g_switch_value
>= 8)
9880 newname
= RDATA_SECTION_NAME
;
9883 gas_assert (g_switch_value
>= 4);
9887 new_seg
= subseg_new (newname
, (subsegT
) 0);
9889 bfd_set_section_flags (stdoutput
, new_seg
,
9894 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9895 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
9896 record_alignment (new_seg
, 4);
9898 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9900 as_bad (_("Can't use floating point insn in this section"));
9902 /* Set the argument to the current address in the
9904 offset_expr
.X_op
= O_symbol
;
9905 offset_expr
.X_add_symbol
= symbol_temp_new_now ();
9906 offset_expr
.X_add_number
= 0;
9908 /* Put the floating point number into the section. */
9909 p
= frag_more ((int) length
);
9910 memcpy (p
, temp
, length
);
9912 /* Switch back to the original section. */
9913 subseg_set (seg
, subseg
);
9918 case 'i': /* 16 bit unsigned immediate */
9919 case 'j': /* 16 bit signed immediate */
9920 *imm_reloc
= BFD_RELOC_LO16
;
9921 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9924 offsetT minval
, maxval
;
9926 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9927 && strcmp (insn
->name
, insn
[1].name
) == 0);
9929 /* If the expression was written as an unsigned number,
9930 only treat it as signed if there are no more
9934 && sizeof (imm_expr
.X_add_number
) <= 4
9935 && imm_expr
.X_op
== O_constant
9936 && imm_expr
.X_add_number
< 0
9937 && imm_expr
.X_unsigned
9941 /* For compatibility with older assemblers, we accept
9942 0x8000-0xffff as signed 16-bit numbers when only
9943 signed numbers are allowed. */
9945 minval
= 0, maxval
= 0xffff;
9947 minval
= -0x8000, maxval
= 0x7fff;
9949 minval
= -0x8000, maxval
= 0xffff;
9951 if (imm_expr
.X_op
!= O_constant
9952 || imm_expr
.X_add_number
< minval
9953 || imm_expr
.X_add_number
> maxval
)
9957 if (imm_expr
.X_op
== O_constant
9958 || imm_expr
.X_op
== O_big
)
9959 as_bad (_("expression out of range"));
9965 case 'o': /* 16 bit offset */
9966 offset_reloc
[0] = BFD_RELOC_LO16
;
9967 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9968 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9970 /* Check whether there is only a single bracketed expression
9971 left. If so, it must be the base register and the
9972 constant must be zero. */
9973 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9975 offset_expr
.X_op
= O_constant
;
9976 offset_expr
.X_add_number
= 0;
9980 /* If this value won't fit into a 16 bit offset, then go
9981 find a macro that will generate the 32 bit offset
9983 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9984 && (offset_expr
.X_op
!= O_constant
9985 || offset_expr
.X_add_number
>= 0x8000
9986 || offset_expr
.X_add_number
< -0x8000))
9992 case 'p': /* pc relative offset */
9993 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9994 my_getExpression (&offset_expr
, s
);
9998 case 'u': /* upper 16 bits */
9999 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
10000 && imm_expr
.X_op
== O_constant
10001 && (imm_expr
.X_add_number
< 0
10002 || imm_expr
.X_add_number
>= 0x10000))
10003 as_bad (_("lui expression not in range 0..65535"));
10007 case 'a': /* 26 bit address */
10008 my_getExpression (&offset_expr
, s
);
10010 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
10013 case 'N': /* 3 bit branch condition code */
10014 case 'M': /* 3 bit compare condition code */
10016 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
10017 rtype
|= RTYPE_FCC
;
10018 if (!reg_lookup (&s
, rtype
, ®no
))
10020 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
10021 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
10022 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
10023 && (regno
& 1) != 0)
10024 as_warn (_("Condition code register should be even for %s, was %d"),
10026 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
10027 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
10028 && (regno
& 3) != 0)
10029 as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
10032 INSERT_OPERAND (BCC
, *ip
, regno
);
10034 INSERT_OPERAND (CCC
, *ip
, regno
);
10038 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
10049 while (ISDIGIT (*s
));
10052 c
= 8; /* Invalid sel value. */
10055 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
10056 ip
->insn_opcode
|= c
;
10060 /* Must be at least one digit. */
10061 my_getExpression (&imm_expr
, s
);
10062 check_absolute_expr (ip
, &imm_expr
);
10064 if ((unsigned long) imm_expr
.X_add_number
10065 > (unsigned long) OP_MASK_VECBYTE
)
10067 as_bad (_("bad byte vector index (%ld)"),
10068 (long) imm_expr
.X_add_number
);
10069 imm_expr
.X_add_number
= 0;
10072 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
10073 imm_expr
.X_op
= O_absent
;
10078 my_getExpression (&imm_expr
, s
);
10079 check_absolute_expr (ip
, &imm_expr
);
10081 if ((unsigned long) imm_expr
.X_add_number
10082 > (unsigned long) OP_MASK_VECALIGN
)
10084 as_bad (_("bad byte vector index (%ld)"),
10085 (long) imm_expr
.X_add_number
);
10086 imm_expr
.X_add_number
= 0;
10089 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
10090 imm_expr
.X_op
= O_absent
;
10095 as_bad (_("bad char = '%c'\n"), *args
);
10100 /* Args don't match. */
10101 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
10102 !strcmp (insn
->name
, insn
[1].name
))
10106 insn_error
= _("illegal operands");
10110 *(--argsStart
) = save_c
;
10111 insn_error
= _("illegal operands");
10116 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10118 /* This routine assembles an instruction into its binary format when
10119 assembling for the mips16. As a side effect, it sets one of the
10120 global variables imm_reloc or offset_reloc to the type of
10121 relocation to do if one of the operands is an address expression.
10122 It also sets mips16_small and mips16_ext if the user explicitly
10123 requested a small or extended instruction. */
10126 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
10130 struct mips_opcode
*insn
;
10132 unsigned int regno
;
10133 unsigned int lastregno
= 0;
10139 mips16_small
= FALSE
;
10140 mips16_ext
= FALSE
;
10142 for (s
= str
; ISLOWER (*s
); ++s
)
10154 if (s
[1] == 't' && s
[2] == ' ')
10157 mips16_small
= TRUE
;
10161 else if (s
[1] == 'e' && s
[2] == ' ')
10168 /* Fall through. */
10170 insn_error
= _("unknown opcode");
10174 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10175 mips16_small
= TRUE
;
10177 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10179 insn_error
= _("unrecognized opcode");
10188 gas_assert (strcmp (insn
->name
, str
) == 0);
10190 ok
= is_opcode_valid_16 (insn
);
10193 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10194 && strcmp (insn
->name
, insn
[1].name
) == 0)
10203 static char buf
[100];
10205 _("opcode not supported on this processor: %s (%s)"),
10206 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10207 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10214 create_insn (ip
, insn
);
10215 imm_expr
.X_op
= O_absent
;
10216 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10217 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10218 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10219 imm2_expr
.X_op
= O_absent
;
10220 offset_expr
.X_op
= O_absent
;
10221 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10222 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10223 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10224 for (args
= insn
->args
; 1; ++args
)
10231 /* In this switch statement we call break if we did not find
10232 a match, continue if we did find a match, or return if we
10241 /* Stuff the immediate value in now, if we can. */
10242 if (imm_expr
.X_op
== O_constant
10243 && *imm_reloc
> BFD_RELOC_UNUSED
10244 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
10245 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
10246 && insn
->pinfo
!= INSN_MACRO
)
10250 switch (*offset_reloc
)
10252 case BFD_RELOC_MIPS16_HI16_S
:
10253 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10256 case BFD_RELOC_MIPS16_HI16
:
10257 tmp
= imm_expr
.X_add_number
>> 16;
10260 case BFD_RELOC_MIPS16_LO16
:
10261 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10265 case BFD_RELOC_UNUSED
:
10266 tmp
= imm_expr
.X_add_number
;
10272 *offset_reloc
= BFD_RELOC_UNUSED
;
10274 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10275 tmp
, TRUE
, mips16_small
,
10276 mips16_ext
, &ip
->insn_opcode
,
10277 &ip
->use_extend
, &ip
->extend
);
10278 imm_expr
.X_op
= O_absent
;
10279 *imm_reloc
= BFD_RELOC_UNUSED
;
10293 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10296 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10312 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10314 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10318 /* Fall through. */
10329 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10331 if (c
== 'v' || c
== 'w')
10334 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10336 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10347 if (c
== 'v' || c
== 'w')
10349 regno
= mips16_to_32_reg_map
[lastregno
];
10363 regno
= mips32_to_16_reg_map
[regno
];
10368 regno
= ILLEGAL_REG
;
10373 regno
= ILLEGAL_REG
;
10378 regno
= ILLEGAL_REG
;
10383 if (regno
== AT
&& mips_opts
.at
)
10385 if (mips_opts
.at
== ATREG
)
10386 as_warn (_("used $at without \".set noat\""));
10388 as_warn (_("used $%u with \".set at=$%u\""),
10389 regno
, mips_opts
.at
);
10397 if (regno
== ILLEGAL_REG
)
10404 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10408 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10411 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10414 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10420 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10423 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10424 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10434 if (strncmp (s
, "$pc", 3) == 0)
10451 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10454 if (imm_expr
.X_op
!= O_constant
)
10457 ip
->use_extend
= TRUE
;
10462 /* We need to relax this instruction. */
10463 *offset_reloc
= *imm_reloc
;
10464 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10469 *imm_reloc
= BFD_RELOC_UNUSED
;
10470 /* Fall through. */
10477 my_getExpression (&imm_expr
, s
);
10478 if (imm_expr
.X_op
== O_register
)
10480 /* What we thought was an expression turned out to
10483 if (s
[0] == '(' && args
[1] == '(')
10485 /* It looks like the expression was omitted
10486 before a register indirection, which means
10487 that the expression is implicitly zero. We
10488 still set up imm_expr, so that we handle
10489 explicit extensions correctly. */
10490 imm_expr
.X_op
= O_constant
;
10491 imm_expr
.X_add_number
= 0;
10492 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10499 /* We need to relax this instruction. */
10500 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10509 /* We use offset_reloc rather than imm_reloc for the PC
10510 relative operands. This lets macros with both
10511 immediate and address operands work correctly. */
10512 my_getExpression (&offset_expr
, s
);
10514 if (offset_expr
.X_op
== O_register
)
10517 /* We need to relax this instruction. */
10518 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10522 case '6': /* break code */
10523 my_getExpression (&imm_expr
, s
);
10524 check_absolute_expr (ip
, &imm_expr
);
10525 if ((unsigned long) imm_expr
.X_add_number
> 63)
10526 as_warn (_("Invalid value for `%s' (%lu)"),
10528 (unsigned long) imm_expr
.X_add_number
);
10529 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10530 imm_expr
.X_op
= O_absent
;
10534 case 'a': /* 26 bit address */
10535 my_getExpression (&offset_expr
, s
);
10537 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10538 ip
->insn_opcode
<<= 16;
10541 case 'l': /* register list for entry macro */
10542 case 'L': /* register list for exit macro */
10552 unsigned int freg
, reg1
, reg2
;
10554 while (*s
== ' ' || *s
== ',')
10556 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10558 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10562 as_bad (_("can't parse register list"));
10572 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10573 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10575 as_bad (_("invalid register list"));
10579 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10581 mask
&= ~ (7 << 3);
10584 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10586 mask
&= ~ (7 << 3);
10589 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10590 mask
|= (reg2
- 3) << 3;
10591 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10592 mask
|= (reg2
- 15) << 1;
10593 else if (reg1
== RA
&& reg2
== RA
)
10597 as_bad (_("invalid register list"));
10601 /* The mask is filled in in the opcode table for the
10602 benefit of the disassembler. We remove it before
10603 applying the actual mask. */
10604 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10605 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10609 case 'm': /* Register list for save insn. */
10610 case 'M': /* Register list for restore insn. */
10613 int framesz
= 0, seen_framesz
= 0;
10614 int nargs
= 0, statics
= 0, sregs
= 0;
10618 unsigned int reg1
, reg2
;
10620 SKIP_SPACE_TABS (s
);
10623 SKIP_SPACE_TABS (s
);
10625 my_getExpression (&imm_expr
, s
);
10626 if (imm_expr
.X_op
== O_constant
)
10628 /* Handle the frame size. */
10631 as_bad (_("more than one frame size in list"));
10635 framesz
= imm_expr
.X_add_number
;
10636 imm_expr
.X_op
= O_absent
;
10641 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10643 as_bad (_("can't parse register list"));
10655 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10658 as_bad (_("can't parse register list"));
10663 while (reg1
<= reg2
)
10665 if (reg1
>= 4 && reg1
<= 7)
10669 nargs
|= 1 << (reg1
- 4);
10671 /* statics $a0-$a3 */
10672 statics
|= 1 << (reg1
- 4);
10674 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10677 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10679 else if (reg1
== 31)
10681 /* Add $ra to insn. */
10686 as_bad (_("unexpected register in list"));
10694 /* Encode args/statics combination. */
10695 if (nargs
& statics
)
10696 as_bad (_("arg/static registers overlap"));
10697 else if (nargs
== 0xf)
10698 /* All $a0-$a3 are args. */
10699 opcode
|= MIPS16_ALL_ARGS
<< 16;
10700 else if (statics
== 0xf)
10701 /* All $a0-$a3 are statics. */
10702 opcode
|= MIPS16_ALL_STATICS
<< 16;
10705 int narg
= 0, nstat
= 0;
10707 /* Count arg registers. */
10708 while (nargs
& 0x1)
10714 as_bad (_("invalid arg register list"));
10716 /* Count static registers. */
10717 while (statics
& 0x8)
10719 statics
= (statics
<< 1) & 0xf;
10723 as_bad (_("invalid static register list"));
10725 /* Encode args/statics. */
10726 opcode
|= ((narg
<< 2) | nstat
) << 16;
10729 /* Encode $s0/$s1. */
10730 if (sregs
& (1 << 0)) /* $s0 */
10732 if (sregs
& (1 << 1)) /* $s1 */
10738 /* Count regs $s2-$s8. */
10746 as_bad (_("invalid static register list"));
10747 /* Encode $s2-$s8. */
10748 opcode
|= nsreg
<< 24;
10751 /* Encode frame size. */
10753 as_bad (_("missing frame size"));
10754 else if ((framesz
& 7) != 0 || framesz
< 0
10755 || framesz
> 0xff * 8)
10756 as_bad (_("invalid frame size"));
10757 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10760 opcode
|= (((framesz
& 0xf0) << 16)
10761 | (framesz
& 0x0f));
10764 /* Finally build the instruction. */
10765 if ((opcode
>> 16) != 0 || framesz
== 0)
10767 ip
->use_extend
= TRUE
;
10768 ip
->extend
= opcode
>> 16;
10770 ip
->insn_opcode
|= opcode
& 0x7f;
10774 case 'e': /* extend code */
10775 my_getExpression (&imm_expr
, s
);
10776 check_absolute_expr (ip
, &imm_expr
);
10777 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10779 as_warn (_("Invalid value for `%s' (%lu)"),
10781 (unsigned long) imm_expr
.X_add_number
);
10782 imm_expr
.X_add_number
&= 0x7ff;
10784 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10785 imm_expr
.X_op
= O_absent
;
10795 /* Args don't match. */
10796 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10797 strcmp (insn
->name
, insn
[1].name
) == 0)
10804 insn_error
= _("illegal operands");
10810 /* This structure holds information we know about a mips16 immediate
10813 struct mips16_immed_operand
10815 /* The type code used in the argument string in the opcode table. */
10817 /* The number of bits in the short form of the opcode. */
10819 /* The number of bits in the extended form of the opcode. */
10821 /* The amount by which the short form is shifted when it is used;
10822 for example, the sw instruction has a shift count of 2. */
10824 /* The amount by which the short form is shifted when it is stored
10825 into the instruction code. */
10827 /* Non-zero if the short form is unsigned. */
10829 /* Non-zero if the extended form is unsigned. */
10831 /* Non-zero if the value is PC relative. */
10835 /* The mips16 immediate operand types. */
10837 static const struct mips16_immed_operand mips16_immed_operands
[] =
10839 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10840 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10841 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10842 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10843 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10844 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10845 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10846 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10847 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10848 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10849 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10850 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10851 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10852 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10853 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10854 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10855 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10856 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10857 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10858 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10859 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10862 #define MIPS16_NUM_IMMED \
10863 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10865 /* Handle a mips16 instruction with an immediate value. This or's the
10866 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10867 whether an extended value is needed; if one is needed, it sets
10868 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10869 If SMALL is true, an unextended opcode was explicitly requested.
10870 If EXT is true, an extended opcode was explicitly requested. If
10871 WARN is true, warn if EXT does not match reality. */
10874 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10875 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10876 unsigned long *insn
, bfd_boolean
*use_extend
,
10877 unsigned short *extend
)
10879 const struct mips16_immed_operand
*op
;
10880 int mintiny
, maxtiny
;
10881 bfd_boolean needext
;
10883 op
= mips16_immed_operands
;
10884 while (op
->type
!= type
)
10887 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10892 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10895 maxtiny
= 1 << op
->nbits
;
10900 maxtiny
= (1 << op
->nbits
) - 1;
10905 mintiny
= - (1 << (op
->nbits
- 1));
10906 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10909 /* Branch offsets have an implicit 0 in the lowest bit. */
10910 if (type
== 'p' || type
== 'q')
10913 if ((val
& ((1 << op
->shift
) - 1)) != 0
10914 || val
< (mintiny
<< op
->shift
)
10915 || val
> (maxtiny
<< op
->shift
))
10920 if (warn
&& ext
&& ! needext
)
10921 as_warn_where (file
, line
,
10922 _("extended operand requested but not required"));
10923 if (small
&& needext
)
10924 as_bad_where (file
, line
, _("invalid unextended operand value"));
10926 if (small
|| (! ext
&& ! needext
))
10930 *use_extend
= FALSE
;
10931 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10932 insnval
<<= op
->op_shift
;
10937 long minext
, maxext
;
10943 maxext
= (1 << op
->extbits
) - 1;
10947 minext
= - (1 << (op
->extbits
- 1));
10948 maxext
= (1 << (op
->extbits
- 1)) - 1;
10950 if (val
< minext
|| val
> maxext
)
10951 as_bad_where (file
, line
,
10952 _("operand value out of range for instruction"));
10954 *use_extend
= TRUE
;
10955 if (op
->extbits
== 16)
10957 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10960 else if (op
->extbits
== 15)
10962 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10967 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10971 *extend
= (unsigned short) extval
;
10976 struct percent_op_match
10979 bfd_reloc_code_real_type reloc
;
10982 static const struct percent_op_match mips_percent_op
[] =
10984 {"%lo", BFD_RELOC_LO16
},
10986 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10987 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10988 {"%call16", BFD_RELOC_MIPS_CALL16
},
10989 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10990 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10991 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10992 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10993 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10994 {"%got", BFD_RELOC_MIPS_GOT16
},
10995 {"%gp_rel", BFD_RELOC_GPREL16
},
10996 {"%half", BFD_RELOC_16
},
10997 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10998 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10999 {"%neg", BFD_RELOC_MIPS_SUB
},
11000 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
11001 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
11002 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
11003 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
11004 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
11005 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
11006 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
11008 {"%hi", BFD_RELOC_HI16_S
}
11011 static const struct percent_op_match mips16_percent_op
[] =
11013 {"%lo", BFD_RELOC_MIPS16_LO16
},
11014 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
11015 {"%got", BFD_RELOC_MIPS16_GOT16
},
11016 {"%call16", BFD_RELOC_MIPS16_CALL16
},
11017 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
11021 /* Return true if *STR points to a relocation operator. When returning true,
11022 move *STR over the operator and store its relocation code in *RELOC.
11023 Leave both *STR and *RELOC alone when returning false. */
11026 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
11028 const struct percent_op_match
*percent_op
;
11031 if (mips_opts
.mips16
)
11033 percent_op
= mips16_percent_op
;
11034 limit
= ARRAY_SIZE (mips16_percent_op
);
11038 percent_op
= mips_percent_op
;
11039 limit
= ARRAY_SIZE (mips_percent_op
);
11042 for (i
= 0; i
< limit
; i
++)
11043 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
11045 int len
= strlen (percent_op
[i
].str
);
11047 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
11050 *str
+= strlen (percent_op
[i
].str
);
11051 *reloc
= percent_op
[i
].reloc
;
11053 /* Check whether the output BFD supports this relocation.
11054 If not, issue an error and fall back on something safe. */
11055 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
11057 as_bad (_("relocation %s isn't supported by the current ABI"),
11058 percent_op
[i
].str
);
11059 *reloc
= BFD_RELOC_UNUSED
;
11067 /* Parse string STR as a 16-bit relocatable operand. Store the
11068 expression in *EP and the relocations in the array starting
11069 at RELOC. Return the number of relocation operators used.
11071 On exit, EXPR_END points to the first character after the expression. */
11074 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
11077 bfd_reloc_code_real_type reversed_reloc
[3];
11078 size_t reloc_index
, i
;
11079 int crux_depth
, str_depth
;
11082 /* Search for the start of the main expression, recoding relocations
11083 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11084 of the main expression and with CRUX_DEPTH containing the number
11085 of open brackets at that point. */
11092 crux_depth
= str_depth
;
11094 /* Skip over whitespace and brackets, keeping count of the number
11096 while (*str
== ' ' || *str
== '\t' || *str
== '(')
11101 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
11102 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
11104 my_getExpression (ep
, crux
);
11107 /* Match every open bracket. */
11108 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
11112 if (crux_depth
> 0)
11113 as_bad (_("unclosed '('"));
11117 if (reloc_index
!= 0)
11119 prev_reloc_op_frag
= frag_now
;
11120 for (i
= 0; i
< reloc_index
; i
++)
11121 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
11124 return reloc_index
;
11128 my_getExpression (expressionS
*ep
, char *str
)
11133 save_in
= input_line_pointer
;
11134 input_line_pointer
= str
;
11136 expr_end
= input_line_pointer
;
11137 input_line_pointer
= save_in
;
11139 /* If we are in mips16 mode, and this is an expression based on `.',
11140 then we bump the value of the symbol by 1 since that is how other
11141 text symbols are handled. We don't bother to handle complex
11142 expressions, just `.' plus or minus a constant. */
11143 if (mips_opts
.mips16
11144 && ep
->X_op
== O_symbol
11145 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
11146 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
11147 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
11148 && symbol_constant_p (ep
->X_add_symbol
)
11149 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
11150 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
11154 md_atof (int type
, char *litP
, int *sizeP
)
11156 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11160 md_number_to_chars (char *buf
, valueT val
, int n
)
11162 if (target_big_endian
)
11163 number_to_chars_bigendian (buf
, val
, n
);
11165 number_to_chars_littleendian (buf
, val
, n
);
11169 static int support_64bit_objects(void)
11171 const char **list
, **l
;
11174 list
= bfd_target_list ();
11175 for (l
= list
; *l
!= NULL
; l
++)
11177 /* This is traditional mips */
11178 if (strcmp (*l
, "elf64-tradbigmips") == 0
11179 || strcmp (*l
, "elf64-tradlittlemips") == 0)
11181 if (strcmp (*l
, "elf64-bigmips") == 0
11182 || strcmp (*l
, "elf64-littlemips") == 0)
11185 yes
= (*l
!= NULL
);
11189 #endif /* OBJ_ELF */
11191 const char *md_shortopts
= "O::g::G:";
11195 OPTION_MARCH
= OPTION_MD_BASE
,
11217 OPTION_NO_SMARTMIPS
,
11220 OPTION_COMPAT_ARCH_BASE
,
11229 OPTION_M7000_HILO_FIX
,
11230 OPTION_MNO_7000_HILO_FIX
,
11233 OPTION_FIX_LOONGSON2F_JUMP
,
11234 OPTION_NO_FIX_LOONGSON2F_JUMP
,
11235 OPTION_FIX_LOONGSON2F_NOP
,
11236 OPTION_NO_FIX_LOONGSON2F_NOP
,
11238 OPTION_NO_FIX_VR4120
,
11240 OPTION_NO_FIX_VR4130
,
11241 OPTION_FIX_CN63XXP1
,
11242 OPTION_NO_FIX_CN63XXP1
,
11249 OPTION_CONSTRUCT_FLOATS
,
11250 OPTION_NO_CONSTRUCT_FLOATS
,
11253 OPTION_RELAX_BRANCH
,
11254 OPTION_NO_RELAX_BRANCH
,
11261 OPTION_SINGLE_FLOAT
,
11262 OPTION_DOUBLE_FLOAT
,
11265 OPTION_CALL_SHARED
,
11266 OPTION_CALL_NONPIC
,
11276 OPTION_MVXWORKS_PIC
,
11277 #endif /* OBJ_ELF */
11281 struct option md_longopts
[] =
11283 /* Options which specify architecture. */
11284 {"march", required_argument
, NULL
, OPTION_MARCH
},
11285 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11286 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11287 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11288 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11289 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11290 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11291 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11292 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11293 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11294 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11295 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11297 /* Options which specify Application Specific Extensions (ASEs). */
11298 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11299 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11300 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11301 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11302 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11303 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11304 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11305 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11306 {"mmt", no_argument
, NULL
, OPTION_MT
},
11307 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11308 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11309 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11310 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11311 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11313 /* Old-style architecture options. Don't add more of these. */
11314 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11315 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11316 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11317 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11318 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11319 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11320 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11321 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11323 /* Options which enable bug fixes. */
11324 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11325 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11326 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11327 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
11328 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
11329 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
11330 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
11331 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11332 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11333 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11334 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11335 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
11336 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
11337 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
11338 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
11340 /* Miscellaneous options. */
11341 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11342 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11343 {"break", no_argument
, NULL
, OPTION_BREAK
},
11344 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11345 {"EB", no_argument
, NULL
, OPTION_EB
},
11346 {"EL", no_argument
, NULL
, OPTION_EL
},
11347 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11348 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11349 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11350 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11351 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11352 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11353 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11354 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11355 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11356 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11357 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11358 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11359 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11360 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11361 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11362 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11364 /* Strictly speaking this next option is ELF specific,
11365 but we allow it for other ports as well in order to
11366 make testing easier. */
11367 {"32", no_argument
, NULL
, OPTION_32
},
11369 /* ELF-specific options. */
11371 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11372 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11373 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
11374 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11375 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11376 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11377 {"n32", no_argument
, NULL
, OPTION_N32
},
11378 {"64", no_argument
, NULL
, OPTION_64
},
11379 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11380 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11381 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11382 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11383 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11384 #endif /* OBJ_ELF */
11386 {NULL
, no_argument
, NULL
, 0}
11388 size_t md_longopts_size
= sizeof (md_longopts
);
11390 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11391 NEW_VALUE. Warn if another value was already specified. Note:
11392 we have to defer parsing the -march and -mtune arguments in order
11393 to handle 'from-abi' correctly, since the ABI might be specified
11394 in a later argument. */
11397 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11399 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11400 as_warn (_("A different %s was already specified, is now %s"),
11401 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11404 *string_ptr
= new_value
;
11408 md_parse_option (int c
, char *arg
)
11412 case OPTION_CONSTRUCT_FLOATS
:
11413 mips_disable_float_construction
= 0;
11416 case OPTION_NO_CONSTRUCT_FLOATS
:
11417 mips_disable_float_construction
= 1;
11429 target_big_endian
= 1;
11433 target_big_endian
= 0;
11439 else if (arg
[0] == '0')
11441 else if (arg
[0] == '1')
11451 mips_debug
= atoi (arg
);
11455 file_mips_isa
= ISA_MIPS1
;
11459 file_mips_isa
= ISA_MIPS2
;
11463 file_mips_isa
= ISA_MIPS3
;
11467 file_mips_isa
= ISA_MIPS4
;
11471 file_mips_isa
= ISA_MIPS5
;
11474 case OPTION_MIPS32
:
11475 file_mips_isa
= ISA_MIPS32
;
11478 case OPTION_MIPS32R2
:
11479 file_mips_isa
= ISA_MIPS32R2
;
11482 case OPTION_MIPS64R2
:
11483 file_mips_isa
= ISA_MIPS64R2
;
11486 case OPTION_MIPS64
:
11487 file_mips_isa
= ISA_MIPS64
;
11491 mips_set_option_string (&mips_tune_string
, arg
);
11495 mips_set_option_string (&mips_arch_string
, arg
);
11499 mips_set_option_string (&mips_arch_string
, "4650");
11500 mips_set_option_string (&mips_tune_string
, "4650");
11503 case OPTION_NO_M4650
:
11507 mips_set_option_string (&mips_arch_string
, "4010");
11508 mips_set_option_string (&mips_tune_string
, "4010");
11511 case OPTION_NO_M4010
:
11515 mips_set_option_string (&mips_arch_string
, "4100");
11516 mips_set_option_string (&mips_tune_string
, "4100");
11519 case OPTION_NO_M4100
:
11523 mips_set_option_string (&mips_arch_string
, "3900");
11524 mips_set_option_string (&mips_tune_string
, "3900");
11527 case OPTION_NO_M3900
:
11531 mips_opts
.ase_mdmx
= 1;
11534 case OPTION_NO_MDMX
:
11535 mips_opts
.ase_mdmx
= 0;
11539 mips_opts
.ase_dsp
= 1;
11540 mips_opts
.ase_dspr2
= 0;
11543 case OPTION_NO_DSP
:
11544 mips_opts
.ase_dsp
= 0;
11545 mips_opts
.ase_dspr2
= 0;
11549 mips_opts
.ase_dspr2
= 1;
11550 mips_opts
.ase_dsp
= 1;
11553 case OPTION_NO_DSPR2
:
11554 mips_opts
.ase_dspr2
= 0;
11555 mips_opts
.ase_dsp
= 0;
11559 mips_opts
.ase_mt
= 1;
11563 mips_opts
.ase_mt
= 0;
11566 case OPTION_MIPS16
:
11567 mips_opts
.mips16
= 1;
11568 mips_no_prev_insn ();
11571 case OPTION_NO_MIPS16
:
11572 mips_opts
.mips16
= 0;
11573 mips_no_prev_insn ();
11576 case OPTION_MIPS3D
:
11577 mips_opts
.ase_mips3d
= 1;
11580 case OPTION_NO_MIPS3D
:
11581 mips_opts
.ase_mips3d
= 0;
11584 case OPTION_SMARTMIPS
:
11585 mips_opts
.ase_smartmips
= 1;
11588 case OPTION_NO_SMARTMIPS
:
11589 mips_opts
.ase_smartmips
= 0;
11592 case OPTION_FIX_24K
:
11596 case OPTION_NO_FIX_24K
:
11600 case OPTION_FIX_LOONGSON2F_JUMP
:
11601 mips_fix_loongson2f_jump
= TRUE
;
11604 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
11605 mips_fix_loongson2f_jump
= FALSE
;
11608 case OPTION_FIX_LOONGSON2F_NOP
:
11609 mips_fix_loongson2f_nop
= TRUE
;
11612 case OPTION_NO_FIX_LOONGSON2F_NOP
:
11613 mips_fix_loongson2f_nop
= FALSE
;
11616 case OPTION_FIX_VR4120
:
11617 mips_fix_vr4120
= 1;
11620 case OPTION_NO_FIX_VR4120
:
11621 mips_fix_vr4120
= 0;
11624 case OPTION_FIX_VR4130
:
11625 mips_fix_vr4130
= 1;
11628 case OPTION_NO_FIX_VR4130
:
11629 mips_fix_vr4130
= 0;
11632 case OPTION_FIX_CN63XXP1
:
11633 mips_fix_cn63xxp1
= TRUE
;
11636 case OPTION_NO_FIX_CN63XXP1
:
11637 mips_fix_cn63xxp1
= FALSE
;
11640 case OPTION_RELAX_BRANCH
:
11641 mips_relax_branch
= 1;
11644 case OPTION_NO_RELAX_BRANCH
:
11645 mips_relax_branch
= 0;
11648 case OPTION_MSHARED
:
11649 mips_in_shared
= TRUE
;
11652 case OPTION_MNO_SHARED
:
11653 mips_in_shared
= FALSE
;
11656 case OPTION_MSYM32
:
11657 mips_opts
.sym32
= TRUE
;
11660 case OPTION_MNO_SYM32
:
11661 mips_opts
.sym32
= FALSE
;
11665 /* When generating ELF code, we permit -KPIC and -call_shared to
11666 select SVR4_PIC, and -non_shared to select no PIC. This is
11667 intended to be compatible with Irix 5. */
11668 case OPTION_CALL_SHARED
:
11671 as_bad (_("-call_shared is supported only for ELF format"));
11674 mips_pic
= SVR4_PIC
;
11675 mips_abicalls
= TRUE
;
11678 case OPTION_CALL_NONPIC
:
11681 as_bad (_("-call_nonpic is supported only for ELF format"));
11685 mips_abicalls
= TRUE
;
11688 case OPTION_NON_SHARED
:
11691 as_bad (_("-non_shared is supported only for ELF format"));
11695 mips_abicalls
= FALSE
;
11698 /* The -xgot option tells the assembler to use 32 bit offsets
11699 when accessing the got in SVR4_PIC mode. It is for Irix
11704 #endif /* OBJ_ELF */
11707 g_switch_value
= atoi (arg
);
11711 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11715 mips_abi
= O32_ABI
;
11716 /* We silently ignore -32 for non-ELF targets. This greatly
11717 simplifies the construction of the MIPS GAS test cases. */
11724 as_bad (_("-n32 is supported for ELF format only"));
11727 mips_abi
= N32_ABI
;
11733 as_bad (_("-64 is supported for ELF format only"));
11736 mips_abi
= N64_ABI
;
11737 if (!support_64bit_objects())
11738 as_fatal (_("No compiled in support for 64 bit object file format"));
11740 #endif /* OBJ_ELF */
11743 file_mips_gp32
= 1;
11747 file_mips_gp32
= 0;
11751 file_mips_fp32
= 1;
11755 file_mips_fp32
= 0;
11758 case OPTION_SINGLE_FLOAT
:
11759 file_mips_single_float
= 1;
11762 case OPTION_DOUBLE_FLOAT
:
11763 file_mips_single_float
= 0;
11766 case OPTION_SOFT_FLOAT
:
11767 file_mips_soft_float
= 1;
11770 case OPTION_HARD_FLOAT
:
11771 file_mips_soft_float
= 0;
11778 as_bad (_("-mabi is supported for ELF format only"));
11781 if (strcmp (arg
, "32") == 0)
11782 mips_abi
= O32_ABI
;
11783 else if (strcmp (arg
, "o64") == 0)
11784 mips_abi
= O64_ABI
;
11785 else if (strcmp (arg
, "n32") == 0)
11786 mips_abi
= N32_ABI
;
11787 else if (strcmp (arg
, "64") == 0)
11789 mips_abi
= N64_ABI
;
11790 if (! support_64bit_objects())
11791 as_fatal (_("No compiled in support for 64 bit object file "
11794 else if (strcmp (arg
, "eabi") == 0)
11795 mips_abi
= EABI_ABI
;
11798 as_fatal (_("invalid abi -mabi=%s"), arg
);
11802 #endif /* OBJ_ELF */
11804 case OPTION_M7000_HILO_FIX
:
11805 mips_7000_hilo_fix
= TRUE
;
11808 case OPTION_MNO_7000_HILO_FIX
:
11809 mips_7000_hilo_fix
= FALSE
;
11813 case OPTION_MDEBUG
:
11814 mips_flag_mdebug
= TRUE
;
11817 case OPTION_NO_MDEBUG
:
11818 mips_flag_mdebug
= FALSE
;
11822 mips_flag_pdr
= TRUE
;
11825 case OPTION_NO_PDR
:
11826 mips_flag_pdr
= FALSE
;
11829 case OPTION_MVXWORKS_PIC
:
11830 mips_pic
= VXWORKS_PIC
;
11832 #endif /* OBJ_ELF */
11838 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
11843 /* Set up globals to generate code for the ISA or processor
11844 described by INFO. */
11847 mips_set_architecture (const struct mips_cpu_info
*info
)
11851 file_mips_arch
= info
->cpu
;
11852 mips_opts
.arch
= info
->cpu
;
11853 mips_opts
.isa
= info
->isa
;
11858 /* Likewise for tuning. */
11861 mips_set_tune (const struct mips_cpu_info
*info
)
11864 mips_tune
= info
->cpu
;
11869 mips_after_parse_args (void)
11871 const struct mips_cpu_info
*arch_info
= 0;
11872 const struct mips_cpu_info
*tune_info
= 0;
11874 /* GP relative stuff not working for PE */
11875 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11877 if (g_switch_seen
&& g_switch_value
!= 0)
11878 as_bad (_("-G not supported in this configuration."));
11879 g_switch_value
= 0;
11882 if (mips_abi
== NO_ABI
)
11883 mips_abi
= MIPS_DEFAULT_ABI
;
11885 /* The following code determines the architecture and register size.
11886 Similar code was added to GCC 3.3 (see override_options() in
11887 config/mips/mips.c). The GAS and GCC code should be kept in sync
11888 as much as possible. */
11890 if (mips_arch_string
!= 0)
11891 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11893 if (file_mips_isa
!= ISA_UNKNOWN
)
11895 /* Handle -mipsN. At this point, file_mips_isa contains the
11896 ISA level specified by -mipsN, while arch_info->isa contains
11897 the -march selection (if any). */
11898 if (arch_info
!= 0)
11900 /* -march takes precedence over -mipsN, since it is more descriptive.
11901 There's no harm in specifying both as long as the ISA levels
11903 if (file_mips_isa
!= arch_info
->isa
)
11904 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11905 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11906 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11909 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11912 if (arch_info
== 0)
11913 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11915 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11916 as_bad (_("-march=%s is not compatible with the selected ABI"),
11919 mips_set_architecture (arch_info
);
11921 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11922 if (mips_tune_string
!= 0)
11923 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11925 if (tune_info
== 0)
11926 mips_set_tune (arch_info
);
11928 mips_set_tune (tune_info
);
11930 if (file_mips_gp32
>= 0)
11932 /* The user specified the size of the integer registers. Make sure
11933 it agrees with the ABI and ISA. */
11934 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11935 as_bad (_("-mgp64 used with a 32-bit processor"));
11936 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11937 as_bad (_("-mgp32 used with a 64-bit ABI"));
11938 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11939 as_bad (_("-mgp64 used with a 32-bit ABI"));
11943 /* Infer the integer register size from the ABI and processor.
11944 Restrict ourselves to 32-bit registers if that's all the
11945 processor has, or if the ABI cannot handle 64-bit registers. */
11946 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11947 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11950 switch (file_mips_fp32
)
11954 /* No user specified float register size.
11955 ??? GAS treats single-float processors as though they had 64-bit
11956 float registers (although it complains when double-precision
11957 instructions are used). As things stand, saying they have 32-bit
11958 registers would lead to spurious "register must be even" messages.
11959 So here we assume float registers are never smaller than the
11961 if (file_mips_gp32
== 0)
11962 /* 64-bit integer registers implies 64-bit float registers. */
11963 file_mips_fp32
= 0;
11964 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11965 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11966 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11967 file_mips_fp32
= 0;
11969 /* 32-bit float registers. */
11970 file_mips_fp32
= 1;
11973 /* The user specified the size of the float registers. Check if it
11974 agrees with the ABI and ISA. */
11976 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11977 as_bad (_("-mfp64 used with a 32-bit fpu"));
11978 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11979 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11980 as_warn (_("-mfp64 used with a 32-bit ABI"));
11983 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11984 as_warn (_("-mfp32 used with a 64-bit ABI"));
11988 /* End of GCC-shared inference code. */
11990 /* This flag is set when we have a 64-bit capable CPU but use only
11991 32-bit wide registers. Note that EABI does not use it. */
11992 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11993 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11994 || mips_abi
== O32_ABI
))
11995 mips_32bitmode
= 1;
11997 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11998 as_bad (_("trap exception not supported at ISA 1"));
12000 /* If the selected architecture includes support for ASEs, enable
12001 generation of code for them. */
12002 if (mips_opts
.mips16
== -1)
12003 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
12004 if (mips_opts
.ase_mips3d
== -1)
12005 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
12006 && file_mips_fp32
== 0) ? 1 : 0;
12007 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
12008 as_bad (_("-mfp32 used with -mips3d"));
12010 if (mips_opts
.ase_mdmx
== -1)
12011 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
12012 && file_mips_fp32
== 0) ? 1 : 0;
12013 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
12014 as_bad (_("-mfp32 used with -mdmx"));
12016 if (mips_opts
.ase_smartmips
== -1)
12017 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
12018 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
12019 as_warn (_("%s ISA does not support SmartMIPS"),
12020 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12022 if (mips_opts
.ase_dsp
== -1)
12023 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12024 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
12025 as_warn (_("%s ISA does not support DSP ASE"),
12026 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12028 if (mips_opts
.ase_dspr2
== -1)
12030 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
12031 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
12033 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
12034 as_warn (_("%s ISA does not support DSP R2 ASE"),
12035 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12037 if (mips_opts
.ase_mt
== -1)
12038 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
12039 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
12040 as_warn (_("%s ISA does not support MT ASE"),
12041 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12043 file_mips_isa
= mips_opts
.isa
;
12044 file_ase_mips16
= mips_opts
.mips16
;
12045 file_ase_mips3d
= mips_opts
.ase_mips3d
;
12046 file_ase_mdmx
= mips_opts
.ase_mdmx
;
12047 file_ase_smartmips
= mips_opts
.ase_smartmips
;
12048 file_ase_dsp
= mips_opts
.ase_dsp
;
12049 file_ase_dspr2
= mips_opts
.ase_dspr2
;
12050 file_ase_mt
= mips_opts
.ase_mt
;
12051 mips_opts
.gp32
= file_mips_gp32
;
12052 mips_opts
.fp32
= file_mips_fp32
;
12053 mips_opts
.soft_float
= file_mips_soft_float
;
12054 mips_opts
.single_float
= file_mips_single_float
;
12056 if (mips_flag_mdebug
< 0)
12058 #ifdef OBJ_MAYBE_ECOFF
12059 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
12060 mips_flag_mdebug
= 1;
12062 #endif /* OBJ_MAYBE_ECOFF */
12063 mips_flag_mdebug
= 0;
12068 mips_init_after_args (void)
12070 /* initialize opcodes */
12071 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
12072 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
12076 md_pcrel_from (fixS
*fixP
)
12078 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
12079 switch (fixP
->fx_r_type
)
12081 case BFD_RELOC_16_PCREL_S2
:
12082 case BFD_RELOC_MIPS_JMP
:
12083 /* Return the address of the delay slot. */
12086 /* We have no relocation type for PC relative MIPS16 instructions. */
12087 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
12088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12089 _("PC relative MIPS16 instruction references a different section"));
12094 /* This is called before the symbol table is processed. In order to
12095 work with gcc when using mips-tfile, we must keep all local labels.
12096 However, in other cases, we want to discard them. If we were
12097 called with -g, but we didn't see any debugging information, it may
12098 mean that gcc is smuggling debugging information through to
12099 mips-tfile, in which case we must generate all local labels. */
12102 mips_frob_file_before_adjust (void)
12104 #ifndef NO_ECOFF_DEBUGGING
12105 if (ECOFF_DEBUGGING
12107 && ! ecoff_debugging_seen
)
12108 flag_keep_locals
= 1;
12112 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12113 the corresponding LO16 reloc. This is called before md_apply_fix and
12114 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12115 relocation operators.
12117 For our purposes, a %lo() expression matches a %got() or %hi()
12120 (a) it refers to the same symbol; and
12121 (b) the offset applied in the %lo() expression is no lower than
12122 the offset applied in the %got() or %hi().
12124 (b) allows us to cope with code like:
12127 lh $4,%lo(foo+2)($4)
12129 ...which is legal on RELA targets, and has a well-defined behaviour
12130 if the user knows that adding 2 to "foo" will not induce a carry to
12133 When several %lo()s match a particular %got() or %hi(), we use the
12134 following rules to distinguish them:
12136 (1) %lo()s with smaller offsets are a better match than %lo()s with
12139 (2) %lo()s with no matching %got() or %hi() are better than those
12140 that already have a matching %got() or %hi().
12142 (3) later %lo()s are better than earlier %lo()s.
12144 These rules are applied in order.
12146 (1) means, among other things, that %lo()s with identical offsets are
12147 chosen if they exist.
12149 (2) means that we won't associate several high-part relocations with
12150 the same low-part relocation unless there's no alternative. Having
12151 several high parts for the same low part is a GNU extension; this rule
12152 allows careful users to avoid it.
12154 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12155 with the last high-part relocation being at the front of the list.
12156 It therefore makes sense to choose the last matching low-part
12157 relocation, all other things being equal. It's also easier
12158 to code that way. */
12161 mips_frob_file (void)
12163 struct mips_hi_fixup
*l
;
12164 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
12166 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
12168 segment_info_type
*seginfo
;
12169 bfd_boolean matched_lo_p
;
12170 fixS
**hi_pos
, **lo_pos
, **pos
;
12172 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
12174 /* If a GOT16 relocation turns out to be against a global symbol,
12175 there isn't supposed to be a matching LO. */
12176 if (got16_reloc_p (l
->fixp
->fx_r_type
)
12177 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
12180 /* Check quickly whether the next fixup happens to be a matching %lo. */
12181 if (fixup_has_matching_lo_p (l
->fixp
))
12184 seginfo
= seg_info (l
->seg
);
12186 /* Set HI_POS to the position of this relocation in the chain.
12187 Set LO_POS to the position of the chosen low-part relocation.
12188 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12189 relocation that matches an immediately-preceding high-part
12193 matched_lo_p
= FALSE
;
12194 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
12196 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
12198 if (*pos
== l
->fixp
)
12201 if ((*pos
)->fx_r_type
== looking_for_rtype
12202 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
12203 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
12205 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
12207 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
12210 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
12211 && fixup_has_matching_lo_p (*pos
));
12214 /* If we found a match, remove the high-part relocation from its
12215 current position and insert it before the low-part relocation.
12216 Make the offsets match so that fixup_has_matching_lo_p()
12219 We don't warn about unmatched high-part relocations since some
12220 versions of gcc have been known to emit dead "lui ...%hi(...)"
12222 if (lo_pos
!= NULL
)
12224 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12225 if (l
->fixp
->fx_next
!= *lo_pos
)
12227 *hi_pos
= l
->fixp
->fx_next
;
12228 l
->fixp
->fx_next
= *lo_pos
;
12235 /* We may have combined relocations without symbols in the N32/N64 ABI.
12236 We have to prevent gas from dropping them. */
12239 mips_force_relocation (fixS
*fixp
)
12241 if (generic_force_reloc (fixp
))
12245 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12246 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12247 || hi16_reloc_p (fixp
->fx_r_type
)
12248 || lo16_reloc_p (fixp
->fx_r_type
)))
12254 /* Apply a fixup to the object file. */
12257 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12261 reloc_howto_type
*howto
;
12263 /* We ignore generic BFD relocations we don't know about. */
12264 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12268 gas_assert (fixP
->fx_size
== 4
12269 || fixP
->fx_r_type
== BFD_RELOC_16
12270 || fixP
->fx_r_type
== BFD_RELOC_64
12271 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12272 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12273 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12274 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12275 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12277 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12279 gas_assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12281 /* Don't treat parts of a composite relocation as done. There are two
12284 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12285 should nevertheless be emitted if the first part is.
12287 (2) In normal usage, composite relocations are never assembly-time
12288 constants. The easiest way of dealing with the pathological
12289 exceptions is to generate a relocation against STN_UNDEF and
12290 leave everything up to the linker. */
12291 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12294 switch (fixP
->fx_r_type
)
12296 case BFD_RELOC_MIPS_TLS_GD
:
12297 case BFD_RELOC_MIPS_TLS_LDM
:
12298 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12299 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12300 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12301 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12302 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12303 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12304 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12305 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12308 case BFD_RELOC_MIPS_JMP
:
12309 case BFD_RELOC_MIPS_SHIFT5
:
12310 case BFD_RELOC_MIPS_SHIFT6
:
12311 case BFD_RELOC_MIPS_GOT_DISP
:
12312 case BFD_RELOC_MIPS_GOT_PAGE
:
12313 case BFD_RELOC_MIPS_GOT_OFST
:
12314 case BFD_RELOC_MIPS_SUB
:
12315 case BFD_RELOC_MIPS_INSERT_A
:
12316 case BFD_RELOC_MIPS_INSERT_B
:
12317 case BFD_RELOC_MIPS_DELETE
:
12318 case BFD_RELOC_MIPS_HIGHEST
:
12319 case BFD_RELOC_MIPS_HIGHER
:
12320 case BFD_RELOC_MIPS_SCN_DISP
:
12321 case BFD_RELOC_MIPS_REL16
:
12322 case BFD_RELOC_MIPS_RELGOT
:
12323 case BFD_RELOC_MIPS_JALR
:
12324 case BFD_RELOC_HI16
:
12325 case BFD_RELOC_HI16_S
:
12326 case BFD_RELOC_GPREL16
:
12327 case BFD_RELOC_MIPS_LITERAL
:
12328 case BFD_RELOC_MIPS_CALL16
:
12329 case BFD_RELOC_MIPS_GOT16
:
12330 case BFD_RELOC_GPREL32
:
12331 case BFD_RELOC_MIPS_GOT_HI16
:
12332 case BFD_RELOC_MIPS_GOT_LO16
:
12333 case BFD_RELOC_MIPS_CALL_HI16
:
12334 case BFD_RELOC_MIPS_CALL_LO16
:
12335 case BFD_RELOC_MIPS16_GPREL
:
12336 case BFD_RELOC_MIPS16_GOT16
:
12337 case BFD_RELOC_MIPS16_CALL16
:
12338 case BFD_RELOC_MIPS16_HI16
:
12339 case BFD_RELOC_MIPS16_HI16_S
:
12340 case BFD_RELOC_MIPS16_JMP
:
12341 /* Nothing needed to do. The value comes from the reloc entry. */
12345 /* This is handled like BFD_RELOC_32, but we output a sign
12346 extended value if we are only 32 bits. */
12349 if (8 <= sizeof (valueT
))
12350 md_number_to_chars ((char *) buf
, *valP
, 8);
12355 if ((*valP
& 0x80000000) != 0)
12359 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12361 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12367 case BFD_RELOC_RVA
:
12370 /* If we are deleting this reloc entry, we must fill in the
12371 value now. This can happen if we have a .word which is not
12372 resolved when it appears but is later defined. */
12374 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12377 case BFD_RELOC_LO16
:
12378 case BFD_RELOC_MIPS16_LO16
:
12379 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12380 may be safe to remove, but if so it's not obvious. */
12381 /* When handling an embedded PIC switch statement, we can wind
12382 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12385 if (*valP
+ 0x8000 > 0xffff)
12386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12387 _("relocation overflow"));
12388 if (target_big_endian
)
12390 md_number_to_chars ((char *) buf
, *valP
, 2);
12394 case BFD_RELOC_16_PCREL_S2
:
12395 if ((*valP
& 0x3) != 0)
12396 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12397 _("Branch to misaligned address (%lx)"), (long) *valP
);
12399 /* We need to save the bits in the instruction since fixup_segment()
12400 might be deleting the relocation entry (i.e., a branch within
12401 the current segment). */
12402 if (! fixP
->fx_done
)
12405 /* Update old instruction data. */
12406 if (target_big_endian
)
12407 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12409 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12411 if (*valP
+ 0x20000 <= 0x3ffff)
12413 insn
|= (*valP
>> 2) & 0xffff;
12414 md_number_to_chars ((char *) buf
, insn
, 4);
12416 else if (mips_pic
== NO_PIC
12418 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12419 && (fixP
->fx_frag
->fr_address
12420 < text_section
->vma
+ bfd_get_section_size (text_section
))
12421 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12422 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12423 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12425 /* The branch offset is too large. If this is an
12426 unconditional branch, and we are not generating PIC code,
12427 we can convert it to an absolute jump instruction. */
12428 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12429 insn
= 0x0c000000; /* jal */
12431 insn
= 0x08000000; /* j */
12432 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12434 fixP
->fx_addsy
= section_symbol (text_section
);
12435 *valP
+= md_pcrel_from (fixP
);
12436 md_number_to_chars ((char *) buf
, insn
, 4);
12440 /* If we got here, we have branch-relaxation disabled,
12441 and there's nothing we can do to fix this instruction
12442 without turning it into a longer sequence. */
12443 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12444 _("Branch out of range"));
12448 case BFD_RELOC_VTABLE_INHERIT
:
12451 && !S_IS_DEFINED (fixP
->fx_addsy
)
12452 && !S_IS_WEAK (fixP
->fx_addsy
))
12453 S_SET_WEAK (fixP
->fx_addsy
);
12456 case BFD_RELOC_VTABLE_ENTRY
:
12464 /* Remember value for tc_gen_reloc. */
12465 fixP
->fx_addnumber
= *valP
;
12475 name
= input_line_pointer
;
12476 c
= get_symbol_end ();
12477 p
= (symbolS
*) symbol_find_or_make (name
);
12478 *input_line_pointer
= c
;
12482 /* Align the current frag to a given power of two. If a particular
12483 fill byte should be used, FILL points to an integer that contains
12484 that byte, otherwise FILL is null.
12486 The MIPS assembler also automatically adjusts any preceding
12490 mips_align (int to
, int *fill
, symbolS
*label
)
12492 mips_emit_delays ();
12493 mips_record_mips16_mode ();
12494 if (fill
== NULL
&& subseg_text_p (now_seg
))
12495 frag_align_code (to
, 0);
12497 frag_align (to
, fill
? *fill
: 0, 0);
12498 record_alignment (now_seg
, to
);
12501 gas_assert (S_GET_SEGMENT (label
) == now_seg
);
12502 symbol_set_frag (label
, frag_now
);
12503 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12507 /* Align to a given power of two. .align 0 turns off the automatic
12508 alignment used by the data creating pseudo-ops. */
12511 s_align (int x ATTRIBUTE_UNUSED
)
12513 int temp
, fill_value
, *fill_ptr
;
12514 long max_alignment
= 28;
12516 /* o Note that the assembler pulls down any immediately preceding label
12517 to the aligned address.
12518 o It's not documented but auto alignment is reinstated by
12519 a .align pseudo instruction.
12520 o Note also that after auto alignment is turned off the mips assembler
12521 issues an error on attempt to assemble an improperly aligned data item.
12524 temp
= get_absolute_expression ();
12525 if (temp
> max_alignment
)
12526 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12529 as_warn (_("Alignment negative: 0 assumed."));
12532 if (*input_line_pointer
== ',')
12534 ++input_line_pointer
;
12535 fill_value
= get_absolute_expression ();
12536 fill_ptr
= &fill_value
;
12542 segment_info_type
*si
= seg_info (now_seg
);
12543 struct insn_label_list
*l
= si
->label_list
;
12544 /* Auto alignment should be switched on by next section change. */
12546 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12553 demand_empty_rest_of_line ();
12557 s_change_sec (int sec
)
12562 /* The ELF backend needs to know that we are changing sections, so
12563 that .previous works correctly. We could do something like check
12564 for an obj_section_change_hook macro, but that might be confusing
12565 as it would not be appropriate to use it in the section changing
12566 functions in read.c, since obj-elf.c intercepts those. FIXME:
12567 This should be cleaner, somehow. */
12569 obj_elf_section_change_hook ();
12572 mips_emit_delays ();
12583 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12584 demand_empty_rest_of_line ();
12588 seg
= subseg_new (RDATA_SECTION_NAME
,
12589 (subsegT
) get_absolute_expression ());
12592 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12593 | SEC_READONLY
| SEC_RELOC
12595 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12596 record_alignment (seg
, 4);
12598 demand_empty_rest_of_line ();
12602 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12605 bfd_set_section_flags (stdoutput
, seg
,
12606 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12607 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12608 record_alignment (seg
, 4);
12610 demand_empty_rest_of_line ();
12614 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
12617 bfd_set_section_flags (stdoutput
, seg
, SEC_ALLOC
);
12618 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12619 record_alignment (seg
, 4);
12621 demand_empty_rest_of_line ();
12629 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12632 char *section_name
;
12637 int section_entry_size
;
12638 int section_alignment
;
12643 section_name
= input_line_pointer
;
12644 c
= get_symbol_end ();
12646 next_c
= *(input_line_pointer
+ 1);
12648 /* Do we have .section Name<,"flags">? */
12649 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12651 /* just after name is now '\0'. */
12652 *input_line_pointer
= c
;
12653 input_line_pointer
= section_name
;
12654 obj_elf_section (ignore
);
12657 input_line_pointer
++;
12659 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12661 section_type
= get_absolute_expression ();
12664 if (*input_line_pointer
++ == ',')
12665 section_flag
= get_absolute_expression ();
12668 if (*input_line_pointer
++ == ',')
12669 section_entry_size
= get_absolute_expression ();
12671 section_entry_size
= 0;
12672 if (*input_line_pointer
++ == ',')
12673 section_alignment
= get_absolute_expression ();
12675 section_alignment
= 0;
12676 /* FIXME: really ignore? */
12677 (void) section_alignment
;
12679 section_name
= xstrdup (section_name
);
12681 /* When using the generic form of .section (as implemented by obj-elf.c),
12682 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12683 traditionally had to fall back on the more common @progbits instead.
12685 There's nothing really harmful in this, since bfd will correct
12686 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12687 means that, for backwards compatibility, the special_section entries
12688 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12690 Even so, we shouldn't force users of the MIPS .section syntax to
12691 incorrectly label the sections as SHT_PROGBITS. The best compromise
12692 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12693 generic type-checking code. */
12694 if (section_type
== SHT_MIPS_DWARF
)
12695 section_type
= SHT_PROGBITS
;
12697 obj_elf_change_section (section_name
, section_type
, section_flag
,
12698 section_entry_size
, 0, 0, 0);
12700 if (now_seg
->name
!= section_name
)
12701 free (section_name
);
12702 #endif /* OBJ_ELF */
12706 mips_enable_auto_align (void)
12712 s_cons (int log_size
)
12714 segment_info_type
*si
= seg_info (now_seg
);
12715 struct insn_label_list
*l
= si
->label_list
;
12718 label
= l
!= NULL
? l
->label
: NULL
;
12719 mips_emit_delays ();
12720 if (log_size
> 0 && auto_align
)
12721 mips_align (log_size
, 0, label
);
12722 mips_clear_insn_labels ();
12723 cons (1 << log_size
);
12727 s_float_cons (int type
)
12729 segment_info_type
*si
= seg_info (now_seg
);
12730 struct insn_label_list
*l
= si
->label_list
;
12733 label
= l
!= NULL
? l
->label
: NULL
;
12735 mips_emit_delays ();
12740 mips_align (3, 0, label
);
12742 mips_align (2, 0, label
);
12745 mips_clear_insn_labels ();
12750 /* Handle .globl. We need to override it because on Irix 5 you are
12753 where foo is an undefined symbol, to mean that foo should be
12754 considered to be the address of a function. */
12757 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12766 name
= input_line_pointer
;
12767 c
= get_symbol_end ();
12768 symbolP
= symbol_find_or_make (name
);
12769 S_SET_EXTERNAL (symbolP
);
12771 *input_line_pointer
= c
;
12772 SKIP_WHITESPACE ();
12774 /* On Irix 5, every global symbol that is not explicitly labelled as
12775 being a function is apparently labelled as being an object. */
12778 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12779 && (*input_line_pointer
!= ','))
12784 secname
= input_line_pointer
;
12785 c
= get_symbol_end ();
12786 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12788 as_bad (_("%s: no such section"), secname
);
12789 *input_line_pointer
= c
;
12791 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12792 flag
= BSF_FUNCTION
;
12795 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12797 c
= *input_line_pointer
;
12800 input_line_pointer
++;
12801 SKIP_WHITESPACE ();
12802 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12808 demand_empty_rest_of_line ();
12812 s_option (int x ATTRIBUTE_UNUSED
)
12817 opt
= input_line_pointer
;
12818 c
= get_symbol_end ();
12822 /* FIXME: What does this mean? */
12824 else if (strncmp (opt
, "pic", 3) == 0)
12828 i
= atoi (opt
+ 3);
12833 mips_pic
= SVR4_PIC
;
12834 mips_abicalls
= TRUE
;
12837 as_bad (_(".option pic%d not supported"), i
);
12839 if (mips_pic
== SVR4_PIC
)
12841 if (g_switch_seen
&& g_switch_value
!= 0)
12842 as_warn (_("-G may not be used with SVR4 PIC code"));
12843 g_switch_value
= 0;
12844 bfd_set_gp_size (stdoutput
, 0);
12848 as_warn (_("Unrecognized option \"%s\""), opt
);
12850 *input_line_pointer
= c
;
12851 demand_empty_rest_of_line ();
12854 /* This structure is used to hold a stack of .set values. */
12856 struct mips_option_stack
12858 struct mips_option_stack
*next
;
12859 struct mips_set_options options
;
12862 static struct mips_option_stack
*mips_opts_stack
;
12864 /* Handle the .set pseudo-op. */
12867 s_mipsset (int x ATTRIBUTE_UNUSED
)
12869 char *name
= input_line_pointer
, ch
;
12871 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12872 ++input_line_pointer
;
12873 ch
= *input_line_pointer
;
12874 *input_line_pointer
= '\0';
12876 if (strcmp (name
, "reorder") == 0)
12878 if (mips_opts
.noreorder
)
12881 else if (strcmp (name
, "noreorder") == 0)
12883 if (!mips_opts
.noreorder
)
12884 start_noreorder ();
12886 else if (strncmp (name
, "at=", 3) == 0)
12888 char *s
= name
+ 3;
12890 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12891 as_bad (_("Unrecognized register name `%s'"), s
);
12893 else if (strcmp (name
, "at") == 0)
12895 mips_opts
.at
= ATREG
;
12897 else if (strcmp (name
, "noat") == 0)
12899 mips_opts
.at
= ZERO
;
12901 else if (strcmp (name
, "macro") == 0)
12903 mips_opts
.warn_about_macros
= 0;
12905 else if (strcmp (name
, "nomacro") == 0)
12907 if (mips_opts
.noreorder
== 0)
12908 as_bad (_("`noreorder' must be set before `nomacro'"));
12909 mips_opts
.warn_about_macros
= 1;
12911 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12913 mips_opts
.nomove
= 0;
12915 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12917 mips_opts
.nomove
= 1;
12919 else if (strcmp (name
, "bopt") == 0)
12921 mips_opts
.nobopt
= 0;
12923 else if (strcmp (name
, "nobopt") == 0)
12925 mips_opts
.nobopt
= 1;
12927 else if (strcmp (name
, "gp=default") == 0)
12928 mips_opts
.gp32
= file_mips_gp32
;
12929 else if (strcmp (name
, "gp=32") == 0)
12930 mips_opts
.gp32
= 1;
12931 else if (strcmp (name
, "gp=64") == 0)
12933 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12934 as_warn (_("%s isa does not support 64-bit registers"),
12935 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12936 mips_opts
.gp32
= 0;
12938 else if (strcmp (name
, "fp=default") == 0)
12939 mips_opts
.fp32
= file_mips_fp32
;
12940 else if (strcmp (name
, "fp=32") == 0)
12941 mips_opts
.fp32
= 1;
12942 else if (strcmp (name
, "fp=64") == 0)
12944 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12945 as_warn (_("%s isa does not support 64-bit floating point registers"),
12946 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12947 mips_opts
.fp32
= 0;
12949 else if (strcmp (name
, "softfloat") == 0)
12950 mips_opts
.soft_float
= 1;
12951 else if (strcmp (name
, "hardfloat") == 0)
12952 mips_opts
.soft_float
= 0;
12953 else if (strcmp (name
, "singlefloat") == 0)
12954 mips_opts
.single_float
= 1;
12955 else if (strcmp (name
, "doublefloat") == 0)
12956 mips_opts
.single_float
= 0;
12957 else if (strcmp (name
, "mips16") == 0
12958 || strcmp (name
, "MIPS-16") == 0)
12959 mips_opts
.mips16
= 1;
12960 else if (strcmp (name
, "nomips16") == 0
12961 || strcmp (name
, "noMIPS-16") == 0)
12962 mips_opts
.mips16
= 0;
12963 else if (strcmp (name
, "smartmips") == 0)
12965 if (!ISA_SUPPORTS_SMARTMIPS
)
12966 as_warn (_("%s ISA does not support SmartMIPS ASE"),
12967 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12968 mips_opts
.ase_smartmips
= 1;
12970 else if (strcmp (name
, "nosmartmips") == 0)
12971 mips_opts
.ase_smartmips
= 0;
12972 else if (strcmp (name
, "mips3d") == 0)
12973 mips_opts
.ase_mips3d
= 1;
12974 else if (strcmp (name
, "nomips3d") == 0)
12975 mips_opts
.ase_mips3d
= 0;
12976 else if (strcmp (name
, "mdmx") == 0)
12977 mips_opts
.ase_mdmx
= 1;
12978 else if (strcmp (name
, "nomdmx") == 0)
12979 mips_opts
.ase_mdmx
= 0;
12980 else if (strcmp (name
, "dsp") == 0)
12982 if (!ISA_SUPPORTS_DSP_ASE
)
12983 as_warn (_("%s ISA does not support DSP ASE"),
12984 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12985 mips_opts
.ase_dsp
= 1;
12986 mips_opts
.ase_dspr2
= 0;
12988 else if (strcmp (name
, "nodsp") == 0)
12990 mips_opts
.ase_dsp
= 0;
12991 mips_opts
.ase_dspr2
= 0;
12993 else if (strcmp (name
, "dspr2") == 0)
12995 if (!ISA_SUPPORTS_DSPR2_ASE
)
12996 as_warn (_("%s ISA does not support DSP R2 ASE"),
12997 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12998 mips_opts
.ase_dspr2
= 1;
12999 mips_opts
.ase_dsp
= 1;
13001 else if (strcmp (name
, "nodspr2") == 0)
13003 mips_opts
.ase_dspr2
= 0;
13004 mips_opts
.ase_dsp
= 0;
13006 else if (strcmp (name
, "mt") == 0)
13008 if (!ISA_SUPPORTS_MT_ASE
)
13009 as_warn (_("%s ISA does not support MT ASE"),
13010 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
13011 mips_opts
.ase_mt
= 1;
13013 else if (strcmp (name
, "nomt") == 0)
13014 mips_opts
.ase_mt
= 0;
13015 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
13019 /* Permit the user to change the ISA and architecture on the fly.
13020 Needless to say, misuse can cause serious problems. */
13021 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
13024 mips_opts
.isa
= file_mips_isa
;
13025 mips_opts
.arch
= file_mips_arch
;
13027 else if (strncmp (name
, "arch=", 5) == 0)
13029 const struct mips_cpu_info
*p
;
13031 p
= mips_parse_cpu("internal use", name
+ 5);
13033 as_bad (_("unknown architecture %s"), name
+ 5);
13036 mips_opts
.arch
= p
->cpu
;
13037 mips_opts
.isa
= p
->isa
;
13040 else if (strncmp (name
, "mips", 4) == 0)
13042 const struct mips_cpu_info
*p
;
13044 p
= mips_parse_cpu("internal use", name
);
13046 as_bad (_("unknown ISA level %s"), name
+ 4);
13049 mips_opts
.arch
= p
->cpu
;
13050 mips_opts
.isa
= p
->isa
;
13054 as_bad (_("unknown ISA or architecture %s"), name
);
13056 switch (mips_opts
.isa
)
13064 mips_opts
.gp32
= 1;
13065 mips_opts
.fp32
= 1;
13072 mips_opts
.gp32
= 0;
13073 mips_opts
.fp32
= 0;
13076 as_bad (_("unknown ISA level %s"), name
+ 4);
13081 mips_opts
.gp32
= file_mips_gp32
;
13082 mips_opts
.fp32
= file_mips_fp32
;
13085 else if (strcmp (name
, "autoextend") == 0)
13086 mips_opts
.noautoextend
= 0;
13087 else if (strcmp (name
, "noautoextend") == 0)
13088 mips_opts
.noautoextend
= 1;
13089 else if (strcmp (name
, "push") == 0)
13091 struct mips_option_stack
*s
;
13093 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
13094 s
->next
= mips_opts_stack
;
13095 s
->options
= mips_opts
;
13096 mips_opts_stack
= s
;
13098 else if (strcmp (name
, "pop") == 0)
13100 struct mips_option_stack
*s
;
13102 s
= mips_opts_stack
;
13104 as_bad (_(".set pop with no .set push"));
13107 /* If we're changing the reorder mode we need to handle
13108 delay slots correctly. */
13109 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
13110 start_noreorder ();
13111 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
13114 mips_opts
= s
->options
;
13115 mips_opts_stack
= s
->next
;
13119 else if (strcmp (name
, "sym32") == 0)
13120 mips_opts
.sym32
= TRUE
;
13121 else if (strcmp (name
, "nosym32") == 0)
13122 mips_opts
.sym32
= FALSE
;
13123 else if (strchr (name
, ','))
13125 /* Generic ".set" directive; use the generic handler. */
13126 *input_line_pointer
= ch
;
13127 input_line_pointer
= name
;
13133 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
13135 *input_line_pointer
= ch
;
13136 demand_empty_rest_of_line ();
13139 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
13140 .option pic2. It means to generate SVR4 PIC calls. */
13143 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
13145 mips_pic
= SVR4_PIC
;
13146 mips_abicalls
= TRUE
;
13148 if (g_switch_seen
&& g_switch_value
!= 0)
13149 as_warn (_("-G may not be used with SVR4 PIC code"));
13150 g_switch_value
= 0;
13152 bfd_set_gp_size (stdoutput
, 0);
13153 demand_empty_rest_of_line ();
13156 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13157 PIC code. It sets the $gp register for the function based on the
13158 function address, which is in the register named in the argument.
13159 This uses a relocation against _gp_disp, which is handled specially
13160 by the linker. The result is:
13161 lui $gp,%hi(_gp_disp)
13162 addiu $gp,$gp,%lo(_gp_disp)
13163 addu $gp,$gp,.cpload argument
13164 The .cpload argument is normally $25 == $t9.
13166 The -mno-shared option changes this to:
13167 lui $gp,%hi(__gnu_local_gp)
13168 addiu $gp,$gp,%lo(__gnu_local_gp)
13169 and the argument is ignored. This saves an instruction, but the
13170 resulting code is not position independent; it uses an absolute
13171 address for __gnu_local_gp. Thus code assembled with -mno-shared
13172 can go into an ordinary executable, but not into a shared library. */
13175 s_cpload (int ignore ATTRIBUTE_UNUSED
)
13181 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13182 .cpload is ignored. */
13183 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13189 /* .cpload should be in a .set noreorder section. */
13190 if (mips_opts
.noreorder
== 0)
13191 as_warn (_(".cpload not in noreorder section"));
13193 reg
= tc_get_register (0);
13195 /* If we need to produce a 64-bit address, we are better off using
13196 the default instruction sequence. */
13197 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
13199 ex
.X_op
= O_symbol
;
13200 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
13202 ex
.X_op_symbol
= NULL
;
13203 ex
.X_add_number
= 0;
13205 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13206 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13209 macro_build_lui (&ex
, mips_gp_register
);
13210 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13211 mips_gp_register
, BFD_RELOC_LO16
);
13213 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
13214 mips_gp_register
, reg
);
13217 demand_empty_rest_of_line ();
13220 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13221 .cpsetup $reg1, offset|$reg2, label
13223 If offset is given, this results in:
13224 sd $gp, offset($sp)
13225 lui $gp, %hi(%neg(%gp_rel(label)))
13226 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13227 daddu $gp, $gp, $reg1
13229 If $reg2 is given, this results in:
13230 daddu $reg2, $gp, $0
13231 lui $gp, %hi(%neg(%gp_rel(label)))
13232 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13233 daddu $gp, $gp, $reg1
13234 $reg1 is normally $25 == $t9.
13236 The -mno-shared option replaces the last three instructions with
13238 addiu $gp,$gp,%lo(_gp) */
13241 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13243 expressionS ex_off
;
13244 expressionS ex_sym
;
13247 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13248 We also need NewABI support. */
13249 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13255 reg1
= tc_get_register (0);
13256 SKIP_WHITESPACE ();
13257 if (*input_line_pointer
!= ',')
13259 as_bad (_("missing argument separator ',' for .cpsetup"));
13263 ++input_line_pointer
;
13264 SKIP_WHITESPACE ();
13265 if (*input_line_pointer
== '$')
13267 mips_cpreturn_register
= tc_get_register (0);
13268 mips_cpreturn_offset
= -1;
13272 mips_cpreturn_offset
= get_absolute_expression ();
13273 mips_cpreturn_register
= -1;
13275 SKIP_WHITESPACE ();
13276 if (*input_line_pointer
!= ',')
13278 as_bad (_("missing argument separator ',' for .cpsetup"));
13282 ++input_line_pointer
;
13283 SKIP_WHITESPACE ();
13284 expression (&ex_sym
);
13287 if (mips_cpreturn_register
== -1)
13289 ex_off
.X_op
= O_constant
;
13290 ex_off
.X_add_symbol
= NULL
;
13291 ex_off
.X_op_symbol
= NULL
;
13292 ex_off
.X_add_number
= mips_cpreturn_offset
;
13294 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13295 BFD_RELOC_LO16
, SP
);
13298 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13299 mips_gp_register
, 0);
13301 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13303 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13304 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13307 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13308 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13309 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13311 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13312 mips_gp_register
, reg1
);
13318 ex
.X_op
= O_symbol
;
13319 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13320 ex
.X_op_symbol
= NULL
;
13321 ex
.X_add_number
= 0;
13323 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13324 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13326 macro_build_lui (&ex
, mips_gp_register
);
13327 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13328 mips_gp_register
, BFD_RELOC_LO16
);
13333 demand_empty_rest_of_line ();
13337 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13339 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13340 .cplocal is ignored. */
13341 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13347 mips_gp_register
= tc_get_register (0);
13348 demand_empty_rest_of_line ();
13351 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13352 offset from $sp. The offset is remembered, and after making a PIC
13353 call $gp is restored from that location. */
13356 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13360 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13361 .cprestore is ignored. */
13362 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13368 mips_cprestore_offset
= get_absolute_expression ();
13369 mips_cprestore_valid
= 1;
13371 ex
.X_op
= O_constant
;
13372 ex
.X_add_symbol
= NULL
;
13373 ex
.X_op_symbol
= NULL
;
13374 ex
.X_add_number
= mips_cprestore_offset
;
13377 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13378 SP
, HAVE_64BIT_ADDRESSES
);
13381 demand_empty_rest_of_line ();
13384 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13385 was given in the preceding .cpsetup, it results in:
13386 ld $gp, offset($sp)
13388 If a register $reg2 was given there, it results in:
13389 daddu $gp, $reg2, $0 */
13392 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13396 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13397 We also need NewABI support. */
13398 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13405 if (mips_cpreturn_register
== -1)
13407 ex
.X_op
= O_constant
;
13408 ex
.X_add_symbol
= NULL
;
13409 ex
.X_op_symbol
= NULL
;
13410 ex
.X_add_number
= mips_cpreturn_offset
;
13412 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13415 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13416 mips_cpreturn_register
, 0);
13419 demand_empty_rest_of_line ();
13422 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13423 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13424 use in DWARF debug information. */
13427 s_dtprel_internal (size_t bytes
)
13434 if (ex
.X_op
!= O_symbol
)
13436 as_bad (_("Unsupported use of %s"), (bytes
== 8
13439 ignore_rest_of_line ();
13442 p
= frag_more (bytes
);
13443 md_number_to_chars (p
, 0, bytes
);
13444 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13446 ? BFD_RELOC_MIPS_TLS_DTPREL64
13447 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13449 demand_empty_rest_of_line ();
13452 /* Handle .dtprelword. */
13455 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13457 s_dtprel_internal (4);
13460 /* Handle .dtpreldword. */
13463 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13465 s_dtprel_internal (8);
13468 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13469 code. It sets the offset to use in gp_rel relocations. */
13472 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13474 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13475 We also need NewABI support. */
13476 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13482 mips_gprel_offset
= get_absolute_expression ();
13484 demand_empty_rest_of_line ();
13487 /* Handle the .gpword pseudo-op. This is used when generating PIC
13488 code. It generates a 32 bit GP relative reloc. */
13491 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13493 segment_info_type
*si
;
13494 struct insn_label_list
*l
;
13499 /* When not generating PIC code, this is treated as .word. */
13500 if (mips_pic
!= SVR4_PIC
)
13506 si
= seg_info (now_seg
);
13507 l
= si
->label_list
;
13508 label
= l
!= NULL
? l
->label
: NULL
;
13509 mips_emit_delays ();
13511 mips_align (2, 0, label
);
13512 mips_clear_insn_labels ();
13516 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13518 as_bad (_("Unsupported use of .gpword"));
13519 ignore_rest_of_line ();
13523 md_number_to_chars (p
, 0, 4);
13524 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13525 BFD_RELOC_GPREL32
);
13527 demand_empty_rest_of_line ();
13531 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13533 segment_info_type
*si
;
13534 struct insn_label_list
*l
;
13539 /* When not generating PIC code, this is treated as .dword. */
13540 if (mips_pic
!= SVR4_PIC
)
13546 si
= seg_info (now_seg
);
13547 l
= si
->label_list
;
13548 label
= l
!= NULL
? l
->label
: NULL
;
13549 mips_emit_delays ();
13551 mips_align (3, 0, label
);
13552 mips_clear_insn_labels ();
13556 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13558 as_bad (_("Unsupported use of .gpdword"));
13559 ignore_rest_of_line ();
13563 md_number_to_chars (p
, 0, 8);
13564 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13565 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13567 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13568 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13569 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13571 demand_empty_rest_of_line ();
13574 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13575 tables in SVR4 PIC code. */
13578 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13582 /* This is ignored when not generating SVR4 PIC code. */
13583 if (mips_pic
!= SVR4_PIC
)
13589 /* Add $gp to the register named as an argument. */
13591 reg
= tc_get_register (0);
13592 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13595 demand_empty_rest_of_line ();
13598 /* Handle the .insn pseudo-op. This marks instruction labels in
13599 mips16 mode. This permits the linker to handle them specially,
13600 such as generating jalx instructions when needed. We also make
13601 them odd for the duration of the assembly, in order to generate the
13602 right sort of code. We will make them even in the adjust_symtab
13603 routine, while leaving them marked. This is convenient for the
13604 debugger and the disassembler. The linker knows to make them odd
13608 s_insn (int ignore ATTRIBUTE_UNUSED
)
13610 mips16_mark_labels ();
13612 demand_empty_rest_of_line ();
13615 /* Handle a .stabn directive. We need these in order to mark a label
13616 as being a mips16 text label correctly. Sometimes the compiler
13617 will emit a label, followed by a .stabn, and then switch sections.
13618 If the label and .stabn are in mips16 mode, then the label is
13619 really a mips16 text label. */
13622 s_mips_stab (int type
)
13625 mips16_mark_labels ();
13630 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13633 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13640 name
= input_line_pointer
;
13641 c
= get_symbol_end ();
13642 symbolP
= symbol_find_or_make (name
);
13643 S_SET_WEAK (symbolP
);
13644 *input_line_pointer
= c
;
13646 SKIP_WHITESPACE ();
13648 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13650 if (S_IS_DEFINED (symbolP
))
13652 as_bad (_("ignoring attempt to redefine symbol %s"),
13653 S_GET_NAME (symbolP
));
13654 ignore_rest_of_line ();
13658 if (*input_line_pointer
== ',')
13660 ++input_line_pointer
;
13661 SKIP_WHITESPACE ();
13665 if (exp
.X_op
!= O_symbol
)
13667 as_bad (_("bad .weakext directive"));
13668 ignore_rest_of_line ();
13671 symbol_set_value_expression (symbolP
, &exp
);
13674 demand_empty_rest_of_line ();
13677 /* Parse a register string into a number. Called from the ECOFF code
13678 to parse .frame. The argument is non-zero if this is the frame
13679 register, so that we can record it in mips_frame_reg. */
13682 tc_get_register (int frame
)
13686 SKIP_WHITESPACE ();
13687 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13691 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13692 mips_frame_reg_valid
= 1;
13693 mips_cprestore_valid
= 0;
13699 md_section_align (asection
*seg
, valueT addr
)
13701 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13705 /* We don't need to align ELF sections to the full alignment.
13706 However, Irix 5 may prefer that we align them at least to a 16
13707 byte boundary. We don't bother to align the sections if we
13708 are targeted for an embedded system. */
13709 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13715 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13718 /* Utility routine, called from above as well. If called while the
13719 input file is still being read, it's only an approximation. (For
13720 example, a symbol may later become defined which appeared to be
13721 undefined earlier.) */
13724 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13729 if (g_switch_value
> 0)
13731 const char *symname
;
13734 /* Find out whether this symbol can be referenced off the $gp
13735 register. It can be if it is smaller than the -G size or if
13736 it is in the .sdata or .sbss section. Certain symbols can
13737 not be referenced off the $gp, although it appears as though
13739 symname
= S_GET_NAME (sym
);
13740 if (symname
!= (const char *) NULL
13741 && (strcmp (symname
, "eprol") == 0
13742 || strcmp (symname
, "etext") == 0
13743 || strcmp (symname
, "_gp") == 0
13744 || strcmp (symname
, "edata") == 0
13745 || strcmp (symname
, "_fbss") == 0
13746 || strcmp (symname
, "_fdata") == 0
13747 || strcmp (symname
, "_ftext") == 0
13748 || strcmp (symname
, "end") == 0
13749 || strcmp (symname
, "_gp_disp") == 0))
13751 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13753 #ifndef NO_ECOFF_DEBUGGING
13754 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13755 && (symbol_get_obj (sym
)->ecoff_extern_size
13756 <= g_switch_value
))
13758 /* We must defer this decision until after the whole
13759 file has been read, since there might be a .extern
13760 after the first use of this symbol. */
13761 || (before_relaxing
13762 #ifndef NO_ECOFF_DEBUGGING
13763 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13765 && S_GET_VALUE (sym
) == 0)
13766 || (S_GET_VALUE (sym
) != 0
13767 && S_GET_VALUE (sym
) <= g_switch_value
)))
13771 const char *segname
;
13773 segname
= segment_name (S_GET_SEGMENT (sym
));
13774 gas_assert (strcmp (segname
, ".lit8") != 0
13775 && strcmp (segname
, ".lit4") != 0);
13776 change
= (strcmp (segname
, ".sdata") != 0
13777 && strcmp (segname
, ".sbss") != 0
13778 && strncmp (segname
, ".sdata.", 7) != 0
13779 && strncmp (segname
, ".sbss.", 6) != 0
13780 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13781 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13786 /* We are not optimizing for the $gp register. */
13791 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13794 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13798 /* Handle the case of a symbol equated to another symbol. */
13799 while (symbol_equated_reloc_p (sym
))
13803 /* It's possible to get a loop here in a badly written program. */
13804 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13810 if (symbol_section_p (sym
))
13813 symsec
= S_GET_SEGMENT (sym
);
13815 /* This must duplicate the test in adjust_reloc_syms. */
13816 return (symsec
!= &bfd_und_section
13817 && symsec
!= &bfd_abs_section
13818 && !bfd_is_com_section (symsec
)
13819 && !s_is_linkonce (sym
, segtype
)
13821 /* A global or weak symbol is treated as external. */
13822 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13828 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13829 extended opcode. SEC is the section the frag is in. */
13832 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13835 const struct mips16_immed_operand
*op
;
13837 int mintiny
, maxtiny
;
13841 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13843 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13846 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13847 op
= mips16_immed_operands
;
13848 while (op
->type
!= type
)
13851 gas_assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13856 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13859 maxtiny
= 1 << op
->nbits
;
13864 maxtiny
= (1 << op
->nbits
) - 1;
13869 mintiny
= - (1 << (op
->nbits
- 1));
13870 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13873 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13874 val
= S_GET_VALUE (fragp
->fr_symbol
);
13875 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13881 /* We won't have the section when we are called from
13882 mips_relax_frag. However, we will always have been called
13883 from md_estimate_size_before_relax first. If this is a
13884 branch to a different section, we mark it as such. If SEC is
13885 NULL, and the frag is not marked, then it must be a branch to
13886 the same section. */
13889 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13894 /* Must have been called from md_estimate_size_before_relax. */
13897 fragp
->fr_subtype
=
13898 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13900 /* FIXME: We should support this, and let the linker
13901 catch branches and loads that are out of range. */
13902 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13903 _("unsupported PC relative reference to different section"));
13907 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13908 /* Assume non-extended on the first relaxation pass.
13909 The address we have calculated will be bogus if this is
13910 a forward branch to another frag, as the forward frag
13911 will have fr_address == 0. */
13915 /* In this case, we know for sure that the symbol fragment is in
13916 the same section. If the relax_marker of the symbol fragment
13917 differs from the relax_marker of this fragment, we have not
13918 yet adjusted the symbol fragment fr_address. We want to add
13919 in STRETCH in order to get a better estimate of the address.
13920 This particularly matters because of the shift bits. */
13922 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13926 /* Adjust stretch for any alignment frag. Note that if have
13927 been expanding the earlier code, the symbol may be
13928 defined in what appears to be an earlier frag. FIXME:
13929 This doesn't handle the fr_subtype field, which specifies
13930 a maximum number of bytes to skip when doing an
13932 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13934 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13937 stretch
= - ((- stretch
)
13938 & ~ ((1 << (int) f
->fr_offset
) - 1));
13940 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13949 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13951 /* The base address rules are complicated. The base address of
13952 a branch is the following instruction. The base address of a
13953 PC relative load or add is the instruction itself, but if it
13954 is in a delay slot (in which case it can not be extended) use
13955 the address of the instruction whose delay slot it is in. */
13956 if (type
== 'p' || type
== 'q')
13960 /* If we are currently assuming that this frag should be
13961 extended, then, the current address is two bytes
13963 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13966 /* Ignore the low bit in the target, since it will be set
13967 for a text label. */
13968 if ((val
& 1) != 0)
13971 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13973 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13976 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13978 /* Branch offsets have an implicit 0 in the lowest bit. */
13979 if (type
== 'p' || type
== 'q')
13982 /* If any of the shifted bits are set, we must use an extended
13983 opcode. If the address depends on the size of this
13984 instruction, this can lead to a loop, so we arrange to always
13985 use an extended opcode. We only check this when we are in
13986 the main relaxation loop, when SEC is NULL. */
13987 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13989 fragp
->fr_subtype
=
13990 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13994 /* If we are about to mark a frag as extended because the value
13995 is precisely maxtiny + 1, then there is a chance of an
13996 infinite loop as in the following code:
14001 In this case when the la is extended, foo is 0x3fc bytes
14002 away, so the la can be shrunk, but then foo is 0x400 away, so
14003 the la must be extended. To avoid this loop, we mark the
14004 frag as extended if it was small, and is about to become
14005 extended with a value of maxtiny + 1. */
14006 if (val
== ((maxtiny
+ 1) << op
->shift
)
14007 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
14010 fragp
->fr_subtype
=
14011 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
14015 else if (symsec
!= absolute_section
&& sec
!= NULL
)
14016 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
14018 if ((val
& ((1 << op
->shift
) - 1)) != 0
14019 || val
< (mintiny
<< op
->shift
)
14020 || val
> (maxtiny
<< op
->shift
))
14026 /* Compute the length of a branch sequence, and adjust the
14027 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14028 worst-case length is computed, with UPDATE being used to indicate
14029 whether an unconditional (-1), branch-likely (+1) or regular (0)
14030 branch is to be computed. */
14032 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
14034 bfd_boolean toofar
;
14038 && S_IS_DEFINED (fragp
->fr_symbol
)
14039 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
14044 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
14046 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
14050 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
14053 /* If the symbol is not defined or it's in a different segment,
14054 assume the user knows what's going on and emit a short
14060 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14062 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
14063 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
14064 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
14070 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
14073 if (mips_pic
!= NO_PIC
)
14075 /* Additional space for PIC loading of target address. */
14077 if (mips_opts
.isa
== ISA_MIPS1
)
14078 /* Additional space for $at-stabilizing nop. */
14082 /* If branch is conditional. */
14083 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
14090 /* Estimate the size of a frag before relaxing. Unless this is the
14091 mips16, we are not really relaxing here, and the final size is
14092 encoded in the subtype information. For the mips16, we have to
14093 decide whether we are using an extended opcode or not. */
14096 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
14100 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14103 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
14105 return fragp
->fr_var
;
14108 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14109 /* We don't want to modify the EXTENDED bit here; it might get us
14110 into infinite loops. We change it only in mips_relax_frag(). */
14111 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
14113 if (mips_pic
== NO_PIC
)
14114 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
14115 else if (mips_pic
== SVR4_PIC
)
14116 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
14117 else if (mips_pic
== VXWORKS_PIC
)
14118 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14125 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
14126 return -RELAX_FIRST (fragp
->fr_subtype
);
14129 return -RELAX_SECOND (fragp
->fr_subtype
);
14132 /* This is called to see whether a reloc against a defined symbol
14133 should be converted into a reloc against a section. */
14136 mips_fix_adjustable (fixS
*fixp
)
14138 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
14139 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14142 if (fixp
->fx_addsy
== NULL
)
14145 /* If symbol SYM is in a mergeable section, relocations of the form
14146 SYM + 0 can usually be made section-relative. The mergeable data
14147 is then identified by the section offset rather than by the symbol.
14149 However, if we're generating REL LO16 relocations, the offset is split
14150 between the LO16 and parterning high part relocation. The linker will
14151 need to recalculate the complete offset in order to correctly identify
14154 The linker has traditionally not looked for the parterning high part
14155 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14156 placed anywhere. Rather than break backwards compatibility by changing
14157 this, it seems better not to force the issue, and instead keep the
14158 original symbol. This will work with either linker behavior. */
14159 if ((lo16_reloc_p (fixp
->fx_r_type
)
14160 || reloc_needs_lo_p (fixp
->fx_r_type
))
14161 && HAVE_IN_PLACE_ADDENDS
14162 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
14165 /* There is no place to store an in-place offset for JALR relocations. */
14166 if (fixp
->fx_r_type
== BFD_RELOC_MIPS_JALR
&& HAVE_IN_PLACE_ADDENDS
)
14170 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14171 to a floating-point stub. The same is true for non-R_MIPS16_26
14172 relocations against MIPS16 functions; in this case, the stub becomes
14173 the function's canonical address.
14175 Floating-point stubs are stored in unique .mips16.call.* or
14176 .mips16.fn.* sections. If a stub T for function F is in section S,
14177 the first relocation in section S must be against F; this is how the
14178 linker determines the target function. All relocations that might
14179 resolve to T must also be against F. We therefore have the following
14180 restrictions, which are given in an intentionally-redundant way:
14182 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14185 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14186 if that stub might be used.
14188 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14191 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14192 that stub might be used.
14194 There is a further restriction:
14196 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14197 on targets with in-place addends; the relocation field cannot
14198 encode the low bit.
14200 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14201 against a MIPS16 symbol.
14203 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14204 relocation against some symbol R, no relocation against R may be
14205 reduced. (Note that this deals with (2) as well as (1) because
14206 relocations against global symbols will never be reduced on ELF
14207 targets.) This approach is a little simpler than trying to detect
14208 stub sections, and gives the "all or nothing" per-symbol consistency
14209 that we have for MIPS16 symbols. */
14211 && fixp
->fx_subsy
== NULL
14212 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
14213 || *symbol_get_tc (fixp
->fx_addsy
)))
14220 /* Translate internal representation of relocation info to BFD target
14224 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14226 static arelent
*retval
[4];
14228 bfd_reloc_code_real_type code
;
14230 memset (retval
, 0, sizeof(retval
));
14231 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
14232 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14233 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14234 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14236 if (fixp
->fx_pcrel
)
14238 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14240 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14241 Relocations want only the symbol offset. */
14242 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14245 /* A gruesome hack which is a result of the gruesome gas
14246 reloc handling. What's worse, for COFF (as opposed to
14247 ECOFF), we might need yet another copy of reloc->address.
14248 See bfd_install_relocation. */
14249 reloc
->addend
+= reloc
->address
;
14253 reloc
->addend
= fixp
->fx_addnumber
;
14255 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14256 entry to be used in the relocation's section offset. */
14257 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14259 reloc
->address
= reloc
->addend
;
14263 code
= fixp
->fx_r_type
;
14265 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14266 if (reloc
->howto
== NULL
)
14268 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14269 _("Can not represent %s relocation in this object file format"),
14270 bfd_get_reloc_code_name (code
));
14277 /* Relax a machine dependent frag. This returns the amount by which
14278 the current size of the frag should change. */
14281 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14283 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14285 offsetT old_var
= fragp
->fr_var
;
14287 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14289 return fragp
->fr_var
- old_var
;
14292 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14295 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14297 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14299 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14304 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14306 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14313 /* Convert a machine dependent frag. */
14316 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14318 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14321 unsigned long insn
;
14325 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14327 if (target_big_endian
)
14328 insn
= bfd_getb32 (buf
);
14330 insn
= bfd_getl32 (buf
);
14332 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14334 /* We generate a fixup instead of applying it right now
14335 because, if there are linker relaxations, we're going to
14336 need the relocations. */
14337 exp
.X_op
= O_symbol
;
14338 exp
.X_add_symbol
= fragp
->fr_symbol
;
14339 exp
.X_add_number
= fragp
->fr_offset
;
14341 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14342 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14343 fixp
->fx_file
= fragp
->fr_file
;
14344 fixp
->fx_line
= fragp
->fr_line
;
14346 md_number_to_chars ((char *) buf
, insn
, 4);
14353 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14354 _("relaxed out-of-range branch into a jump"));
14356 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14359 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14361 /* Reverse the branch. */
14362 switch ((insn
>> 28) & 0xf)
14365 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14366 have the condition reversed by tweaking a single
14367 bit, and their opcodes all have 0x4???????. */
14368 gas_assert ((insn
& 0xf1000000) == 0x41000000);
14369 insn
^= 0x00010000;
14373 /* bltz 0x04000000 bgez 0x04010000
14374 bltzal 0x04100000 bgezal 0x04110000 */
14375 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
14376 insn
^= 0x00010000;
14380 /* beq 0x10000000 bne 0x14000000
14381 blez 0x18000000 bgtz 0x1c000000 */
14382 insn
^= 0x04000000;
14390 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14392 /* Clear the and-link bit. */
14393 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
14395 /* bltzal 0x04100000 bgezal 0x04110000
14396 bltzall 0x04120000 bgezall 0x04130000 */
14397 insn
&= ~0x00100000;
14400 /* Branch over the branch (if the branch was likely) or the
14401 full jump (not likely case). Compute the offset from the
14402 current instruction to branch to. */
14403 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14407 /* How many bytes in instructions we've already emitted? */
14408 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14409 /* How many bytes in instructions from here to the end? */
14410 i
= fragp
->fr_var
- i
;
14412 /* Convert to instruction count. */
14414 /* Branch counts from the next instruction. */
14417 /* Branch over the jump. */
14418 md_number_to_chars ((char *) buf
, insn
, 4);
14422 md_number_to_chars ((char *) buf
, 0, 4);
14425 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14427 /* beql $0, $0, 2f */
14429 /* Compute the PC offset from the current instruction to
14430 the end of the variable frag. */
14431 /* How many bytes in instructions we've already emitted? */
14432 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14433 /* How many bytes in instructions from here to the end? */
14434 i
= fragp
->fr_var
- i
;
14435 /* Convert to instruction count. */
14437 /* Don't decrement i, because we want to branch over the
14441 md_number_to_chars ((char *) buf
, insn
, 4);
14444 md_number_to_chars ((char *) buf
, 0, 4);
14449 if (mips_pic
== NO_PIC
)
14452 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14453 ? 0x0c000000 : 0x08000000);
14454 exp
.X_op
= O_symbol
;
14455 exp
.X_add_symbol
= fragp
->fr_symbol
;
14456 exp
.X_add_number
= fragp
->fr_offset
;
14458 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14459 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14460 fixp
->fx_file
= fragp
->fr_file
;
14461 fixp
->fx_line
= fragp
->fr_line
;
14463 md_number_to_chars ((char *) buf
, insn
, 4);
14468 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14469 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14470 exp
.X_op
= O_symbol
;
14471 exp
.X_add_symbol
= fragp
->fr_symbol
;
14472 exp
.X_add_number
= fragp
->fr_offset
;
14474 if (fragp
->fr_offset
)
14476 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14477 exp
.X_add_number
= 0;
14480 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14481 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14482 fixp
->fx_file
= fragp
->fr_file
;
14483 fixp
->fx_line
= fragp
->fr_line
;
14485 md_number_to_chars ((char *) buf
, insn
, 4);
14488 if (mips_opts
.isa
== ISA_MIPS1
)
14491 md_number_to_chars ((char *) buf
, 0, 4);
14495 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14496 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14498 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14499 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14500 fixp
->fx_file
= fragp
->fr_file
;
14501 fixp
->fx_line
= fragp
->fr_line
;
14503 md_number_to_chars ((char *) buf
, insn
, 4);
14507 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14512 md_number_to_chars ((char *) buf
, insn
, 4);
14517 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
14518 + fragp
->fr_fix
+ fragp
->fr_var
);
14520 fragp
->fr_fix
+= fragp
->fr_var
;
14525 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14528 const struct mips16_immed_operand
*op
;
14529 bfd_boolean small
, ext
;
14532 unsigned long insn
;
14533 bfd_boolean use_extend
;
14534 unsigned short extend
;
14536 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14537 op
= mips16_immed_operands
;
14538 while (op
->type
!= type
)
14541 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14552 resolve_symbol_value (fragp
->fr_symbol
);
14553 val
= S_GET_VALUE (fragp
->fr_symbol
);
14558 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14560 /* The rules for the base address of a PC relative reloc are
14561 complicated; see mips16_extended_frag. */
14562 if (type
== 'p' || type
== 'q')
14567 /* Ignore the low bit in the target, since it will be
14568 set for a text label. */
14569 if ((val
& 1) != 0)
14572 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14574 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14577 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14580 /* Make sure the section winds up with the alignment we have
14583 record_alignment (asec
, op
->shift
);
14587 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14588 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14589 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14590 _("extended instruction in delay slot"));
14592 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14594 if (target_big_endian
)
14595 insn
= bfd_getb16 (buf
);
14597 insn
= bfd_getl16 (buf
);
14599 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14600 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14601 small
, ext
, &insn
, &use_extend
, &extend
);
14605 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14606 fragp
->fr_fix
+= 2;
14610 md_number_to_chars ((char *) buf
, insn
, 2);
14611 fragp
->fr_fix
+= 2;
14619 first
= RELAX_FIRST (fragp
->fr_subtype
);
14620 second
= RELAX_SECOND (fragp
->fr_subtype
);
14621 fixp
= (fixS
*) fragp
->fr_opcode
;
14623 /* Possibly emit a warning if we've chosen the longer option. */
14624 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14625 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14627 const char *msg
= macro_warning (fragp
->fr_subtype
);
14629 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
14632 /* Go through all the fixups for the first sequence. Disable them
14633 (by marking them as done) if we're going to use the second
14634 sequence instead. */
14636 && fixp
->fx_frag
== fragp
14637 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14639 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14641 fixp
= fixp
->fx_next
;
14644 /* Go through the fixups for the second sequence. Disable them if
14645 we're going to use the first sequence, otherwise adjust their
14646 addresses to account for the relaxation. */
14647 while (fixp
&& fixp
->fx_frag
== fragp
)
14649 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14650 fixp
->fx_where
-= first
;
14653 fixp
= fixp
->fx_next
;
14656 /* Now modify the frag contents. */
14657 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14661 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14662 memmove (start
, start
+ first
, second
);
14663 fragp
->fr_fix
-= first
;
14666 fragp
->fr_fix
-= second
;
14672 /* This function is called after the relocs have been generated.
14673 We've been storing mips16 text labels as odd. Here we convert them
14674 back to even for the convenience of the debugger. */
14677 mips_frob_file_after_relocs (void)
14680 unsigned int count
, i
;
14685 syms
= bfd_get_outsymbols (stdoutput
);
14686 count
= bfd_get_symcount (stdoutput
);
14687 for (i
= 0; i
< count
; i
++, syms
++)
14689 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
14690 && ((*syms
)->value
& 1) != 0)
14692 (*syms
)->value
&= ~1;
14693 /* If the symbol has an odd size, it was probably computed
14694 incorrectly, so adjust that as well. */
14695 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14696 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14703 /* This function is called whenever a label is defined. It is used
14704 when handling branch delays; if a branch has a label, we assume we
14705 can not move it. */
14708 mips_define_label (symbolS
*sym
)
14710 segment_info_type
*si
= seg_info (now_seg
);
14711 struct insn_label_list
*l
;
14713 if (free_insn_labels
== NULL
)
14714 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14717 l
= free_insn_labels
;
14718 free_insn_labels
= l
->next
;
14722 l
->next
= si
->label_list
;
14723 si
->label_list
= l
;
14726 dwarf2_emit_label (sym
);
14730 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14732 /* Some special processing for a MIPS ELF file. */
14735 mips_elf_final_processing (void)
14737 /* Write out the register information. */
14738 if (mips_abi
!= N64_ABI
)
14742 s
.ri_gprmask
= mips_gprmask
;
14743 s
.ri_cprmask
[0] = mips_cprmask
[0];
14744 s
.ri_cprmask
[1] = mips_cprmask
[1];
14745 s
.ri_cprmask
[2] = mips_cprmask
[2];
14746 s
.ri_cprmask
[3] = mips_cprmask
[3];
14747 /* The gp_value field is set by the MIPS ELF backend. */
14749 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14750 ((Elf32_External_RegInfo
*)
14751 mips_regmask_frag
));
14755 Elf64_Internal_RegInfo s
;
14757 s
.ri_gprmask
= mips_gprmask
;
14759 s
.ri_cprmask
[0] = mips_cprmask
[0];
14760 s
.ri_cprmask
[1] = mips_cprmask
[1];
14761 s
.ri_cprmask
[2] = mips_cprmask
[2];
14762 s
.ri_cprmask
[3] = mips_cprmask
[3];
14763 /* The gp_value field is set by the MIPS ELF backend. */
14765 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14766 ((Elf64_External_RegInfo
*)
14767 mips_regmask_frag
));
14770 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14771 sort of BFD interface for this. */
14772 if (mips_any_noreorder
)
14773 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14774 if (mips_pic
!= NO_PIC
)
14776 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14777 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14780 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14782 /* Set MIPS ELF flags for ASEs. */
14783 /* We may need to define a new flag for DSP ASE, and set this flag when
14784 file_ase_dsp is true. */
14785 /* Same for DSP R2. */
14786 /* We may need to define a new flag for MT ASE, and set this flag when
14787 file_ase_mt is true. */
14788 if (file_ase_mips16
)
14789 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14790 #if 0 /* XXX FIXME */
14791 if (file_ase_mips3d
)
14792 elf_elfheader (stdoutput
)->e_flags
|= ???;
14795 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14797 /* Set the MIPS ELF ABI flags. */
14798 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14799 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14800 else if (mips_abi
== O64_ABI
)
14801 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14802 else if (mips_abi
== EABI_ABI
)
14804 if (!file_mips_gp32
)
14805 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14807 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14809 else if (mips_abi
== N32_ABI
)
14810 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14812 /* Nothing to do for N64_ABI. */
14814 if (mips_32bitmode
)
14815 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14817 #if 0 /* XXX FIXME */
14818 /* 32 bit code with 64 bit FP registers. */
14819 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14820 elf_elfheader (stdoutput
)->e_flags
|= ???;
14824 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14826 typedef struct proc
{
14828 symbolS
*func_end_sym
;
14829 unsigned long reg_mask
;
14830 unsigned long reg_offset
;
14831 unsigned long fpreg_mask
;
14832 unsigned long fpreg_offset
;
14833 unsigned long frame_offset
;
14834 unsigned long frame_reg
;
14835 unsigned long pc_reg
;
14838 static procS cur_proc
;
14839 static procS
*cur_proc_ptr
;
14840 static int numprocs
;
14842 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14846 mips_nop_opcode (void)
14848 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14851 /* Fill in an rs_align_code fragment. This only needs to do something
14852 for MIPS16 code, where 0 is not a nop. */
14855 mips_handle_align (fragS
*fragp
)
14858 int bytes
, size
, excess
;
14861 if (fragp
->fr_type
!= rs_align_code
)
14864 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14867 opcode
= mips16_nop_insn
.insn_opcode
;
14872 opcode
= nop_insn
.insn_opcode
;
14876 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14877 excess
= bytes
% size
;
14880 /* If we're not inserting a whole number of instructions,
14881 pad the end of the fixed part of the frag with zeros. */
14882 memset (p
, 0, excess
);
14884 fragp
->fr_fix
+= excess
;
14887 md_number_to_chars (p
, opcode
, size
);
14888 fragp
->fr_var
= size
;
14892 md_obj_begin (void)
14899 /* Check for premature end, nesting errors, etc. */
14901 as_warn (_("missing .end at end of assembly"));
14910 if (*input_line_pointer
== '-')
14912 ++input_line_pointer
;
14915 if (!ISDIGIT (*input_line_pointer
))
14916 as_bad (_("expected simple number"));
14917 if (input_line_pointer
[0] == '0')
14919 if (input_line_pointer
[1] == 'x')
14921 input_line_pointer
+= 2;
14922 while (ISXDIGIT (*input_line_pointer
))
14925 val
|= hex_value (*input_line_pointer
++);
14927 return negative
? -val
: val
;
14931 ++input_line_pointer
;
14932 while (ISDIGIT (*input_line_pointer
))
14935 val
|= *input_line_pointer
++ - '0';
14937 return negative
? -val
: val
;
14940 if (!ISDIGIT (*input_line_pointer
))
14942 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14943 *input_line_pointer
, *input_line_pointer
);
14944 as_warn (_("invalid number"));
14947 while (ISDIGIT (*input_line_pointer
))
14950 val
+= *input_line_pointer
++ - '0';
14952 return negative
? -val
: val
;
14955 /* The .file directive; just like the usual .file directive, but there
14956 is an initial number which is the ECOFF file index. In the non-ECOFF
14957 case .file implies DWARF-2. */
14960 s_mips_file (int x ATTRIBUTE_UNUSED
)
14962 static int first_file_directive
= 0;
14964 if (ECOFF_DEBUGGING
)
14973 filename
= dwarf2_directive_file (0);
14975 /* Versions of GCC up to 3.1 start files with a ".file"
14976 directive even for stabs output. Make sure that this
14977 ".file" is handled. Note that you need a version of GCC
14978 after 3.1 in order to support DWARF-2 on MIPS. */
14979 if (filename
!= NULL
&& ! first_file_directive
)
14981 (void) new_logical_line (filename
, -1);
14982 s_app_file_string (filename
, 0);
14984 first_file_directive
= 1;
14988 /* The .loc directive, implying DWARF-2. */
14991 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14993 if (!ECOFF_DEBUGGING
)
14994 dwarf2_directive_loc (0);
14997 /* The .end directive. */
15000 s_mips_end (int x ATTRIBUTE_UNUSED
)
15004 /* Following functions need their own .frame and .cprestore directives. */
15005 mips_frame_reg_valid
= 0;
15006 mips_cprestore_valid
= 0;
15008 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
15011 demand_empty_rest_of_line ();
15016 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15017 as_warn (_(".end not in text section"));
15021 as_warn (_(".end directive without a preceding .ent directive."));
15022 demand_empty_rest_of_line ();
15028 gas_assert (S_GET_NAME (p
));
15029 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
15030 as_warn (_(".end symbol does not match .ent symbol."));
15032 if (debug_type
== DEBUG_STABS
)
15033 stabs_generate_asm_endfunc (S_GET_NAME (p
),
15037 as_warn (_(".end directive missing or unknown symbol"));
15040 /* Create an expression to calculate the size of the function. */
15041 if (p
&& cur_proc_ptr
)
15043 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
15044 expressionS
*exp
= xmalloc (sizeof (expressionS
));
15047 exp
->X_op
= O_subtract
;
15048 exp
->X_add_symbol
= symbol_temp_new_now ();
15049 exp
->X_op_symbol
= p
;
15050 exp
->X_add_number
= 0;
15052 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
15055 /* Generate a .pdr section. */
15056 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
15058 segT saved_seg
= now_seg
;
15059 subsegT saved_subseg
= now_subseg
;
15063 #ifdef md_flush_pending_output
15064 md_flush_pending_output ();
15067 gas_assert (pdr_seg
);
15068 subseg_set (pdr_seg
, 0);
15070 /* Write the symbol. */
15071 exp
.X_op
= O_symbol
;
15072 exp
.X_add_symbol
= p
;
15073 exp
.X_add_number
= 0;
15074 emit_expr (&exp
, 4);
15076 fragp
= frag_more (7 * 4);
15078 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
15079 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
15080 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
15081 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
15082 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
15083 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
15084 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
15086 subseg_set (saved_seg
, saved_subseg
);
15088 #endif /* OBJ_ELF */
15090 cur_proc_ptr
= NULL
;
15093 /* The .aent and .ent directives. */
15096 s_mips_ent (int aent
)
15100 symbolP
= get_symbol ();
15101 if (*input_line_pointer
== ',')
15102 ++input_line_pointer
;
15103 SKIP_WHITESPACE ();
15104 if (ISDIGIT (*input_line_pointer
)
15105 || *input_line_pointer
== '-')
15108 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
15109 as_warn (_(".ent or .aent not in text section."));
15111 if (!aent
&& cur_proc_ptr
)
15112 as_warn (_("missing .end"));
15116 /* This function needs its own .frame and .cprestore directives. */
15117 mips_frame_reg_valid
= 0;
15118 mips_cprestore_valid
= 0;
15120 cur_proc_ptr
= &cur_proc
;
15121 memset (cur_proc_ptr
, '\0', sizeof (procS
));
15123 cur_proc_ptr
->func_sym
= symbolP
;
15127 if (debug_type
== DEBUG_STABS
)
15128 stabs_generate_asm_func (S_GET_NAME (symbolP
),
15129 S_GET_NAME (symbolP
));
15132 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
15134 demand_empty_rest_of_line ();
15137 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
15138 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15139 s_mips_frame is used so that we can set the PDR information correctly.
15140 We can't use the ecoff routines because they make reference to the ecoff
15141 symbol table (in the mdebug section). */
15144 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
15147 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15151 if (cur_proc_ptr
== (procS
*) NULL
)
15153 as_warn (_(".frame outside of .ent"));
15154 demand_empty_rest_of_line ();
15158 cur_proc_ptr
->frame_reg
= tc_get_register (1);
15160 SKIP_WHITESPACE ();
15161 if (*input_line_pointer
++ != ','
15162 || get_absolute_expression_and_terminator (&val
) != ',')
15164 as_warn (_("Bad .frame directive"));
15165 --input_line_pointer
;
15166 demand_empty_rest_of_line ();
15170 cur_proc_ptr
->frame_offset
= val
;
15171 cur_proc_ptr
->pc_reg
= tc_get_register (0);
15173 demand_empty_rest_of_line ();
15176 #endif /* OBJ_ELF */
15180 /* The .fmask and .mask directives. If the mdebug section is present
15181 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15182 embedded targets, s_mips_mask is used so that we can set the PDR
15183 information correctly. We can't use the ecoff routines because they
15184 make reference to the ecoff symbol table (in the mdebug section). */
15187 s_mips_mask (int reg_type
)
15190 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15194 if (cur_proc_ptr
== (procS
*) NULL
)
15196 as_warn (_(".mask/.fmask outside of .ent"));
15197 demand_empty_rest_of_line ();
15201 if (get_absolute_expression_and_terminator (&mask
) != ',')
15203 as_warn (_("Bad .mask/.fmask directive"));
15204 --input_line_pointer
;
15205 demand_empty_rest_of_line ();
15209 off
= get_absolute_expression ();
15211 if (reg_type
== 'F')
15213 cur_proc_ptr
->fpreg_mask
= mask
;
15214 cur_proc_ptr
->fpreg_offset
= off
;
15218 cur_proc_ptr
->reg_mask
= mask
;
15219 cur_proc_ptr
->reg_offset
= off
;
15222 demand_empty_rest_of_line ();
15225 #endif /* OBJ_ELF */
15226 s_ignore (reg_type
);
15229 /* A table describing all the processors gas knows about. Names are
15230 matched in the order listed.
15232 To ease comparison, please keep this table in the same order as
15233 gcc's mips_cpu_info_table[]. */
15234 static const struct mips_cpu_info mips_cpu_info_table
[] =
15236 /* Entries for generic ISAs */
15237 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
15238 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
15239 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
15240 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
15241 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
15242 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15243 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15244 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15245 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15248 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15249 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15250 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15253 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15256 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15257 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15258 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15259 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15260 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15261 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15262 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15263 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15264 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15265 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15266 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15267 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15268 /* ST Microelectronics Loongson 2E and 2F cores */
15269 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15270 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15273 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15274 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15275 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15276 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
15277 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
15278 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15279 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15280 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15281 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15282 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15283 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15284 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15285 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15286 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15287 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15290 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15291 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15292 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15293 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15295 /* MIPS 32 Release 2 */
15296 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15297 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15298 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15299 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15300 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15301 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15302 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15303 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15304 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15305 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15306 /* Deprecated forms of the above. */
15307 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15308 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15309 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15310 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15311 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15312 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15313 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15314 /* Deprecated forms of the above. */
15315 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15316 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15317 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15318 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15319 ISA_MIPS32R2
, CPU_MIPS32R2
},
15320 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15321 ISA_MIPS32R2
, CPU_MIPS32R2
},
15322 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15323 ISA_MIPS32R2
, CPU_MIPS32R2
},
15324 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15325 ISA_MIPS32R2
, CPU_MIPS32R2
},
15326 /* Deprecated forms of the above. */
15327 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15328 ISA_MIPS32R2
, CPU_MIPS32R2
},
15329 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15330 ISA_MIPS32R2
, CPU_MIPS32R2
},
15331 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15332 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15333 ISA_MIPS32R2
, CPU_MIPS32R2
},
15334 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15335 ISA_MIPS32R2
, CPU_MIPS32R2
},
15336 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15337 ISA_MIPS32R2
, CPU_MIPS32R2
},
15338 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15339 ISA_MIPS32R2
, CPU_MIPS32R2
},
15340 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15341 ISA_MIPS32R2
, CPU_MIPS32R2
},
15342 /* Deprecated forms of the above. */
15343 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15344 ISA_MIPS32R2
, CPU_MIPS32R2
},
15345 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15346 ISA_MIPS32R2
, CPU_MIPS32R2
},
15347 /* 1004K cores are multiprocessor versions of the 34K. */
15348 { "1004kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15349 ISA_MIPS32R2
, CPU_MIPS32R2
},
15350 { "1004kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15351 ISA_MIPS32R2
, CPU_MIPS32R2
},
15352 { "1004kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15353 ISA_MIPS32R2
, CPU_MIPS32R2
},
15354 { "1004kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15355 ISA_MIPS32R2
, CPU_MIPS32R2
},
15358 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15359 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15360 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15361 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15362 { "loongson3a", 0, ISA_MIPS64
, CPU_LOONGSON_3A
},
15364 /* Broadcom SB-1 CPU core */
15365 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15366 ISA_MIPS64
, CPU_SB1
},
15367 /* Broadcom SB-1A CPU core */
15368 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15369 ISA_MIPS64
, CPU_SB1
},
15371 /* MIPS 64 Release 2 */
15373 /* Cavium Networks Octeon CPU core */
15374 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15377 { "xlr", 0, ISA_MIPS64
, CPU_XLR
},
15384 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15385 with a final "000" replaced by "k". Ignore case.
15387 Note: this function is shared between GCC and GAS. */
15390 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15392 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15393 given
++, canonical
++;
15395 return ((*given
== 0 && *canonical
== 0)
15396 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15400 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15401 CPU name. We've traditionally allowed a lot of variation here.
15403 Note: this function is shared between GCC and GAS. */
15406 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15408 /* First see if the name matches exactly, or with a final "000"
15409 turned into "k". */
15410 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15413 /* If not, try comparing based on numerical designation alone.
15414 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15415 if (TOLOWER (*given
) == 'r')
15417 if (!ISDIGIT (*given
))
15420 /* Skip over some well-known prefixes in the canonical name,
15421 hoping to find a number there too. */
15422 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15424 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15426 else if (TOLOWER (canonical
[0]) == 'r')
15429 return mips_strict_matching_cpu_name_p (canonical
, given
);
15433 /* Parse an option that takes the name of a processor as its argument.
15434 OPTION is the name of the option and CPU_STRING is the argument.
15435 Return the corresponding processor enumeration if the CPU_STRING is
15436 recognized, otherwise report an error and return null.
15438 A similar function exists in GCC. */
15440 static const struct mips_cpu_info
*
15441 mips_parse_cpu (const char *option
, const char *cpu_string
)
15443 const struct mips_cpu_info
*p
;
15445 /* 'from-abi' selects the most compatible architecture for the given
15446 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15447 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15448 version. Look first at the -mgp options, if given, otherwise base
15449 the choice on MIPS_DEFAULT_64BIT.
15451 Treat NO_ABI like the EABIs. One reason to do this is that the
15452 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15453 architecture. This code picks MIPS I for 'mips' and MIPS III for
15454 'mips64', just as we did in the days before 'from-abi'. */
15455 if (strcasecmp (cpu_string
, "from-abi") == 0)
15457 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15458 return mips_cpu_info_from_isa (ISA_MIPS1
);
15460 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15461 return mips_cpu_info_from_isa (ISA_MIPS3
);
15463 if (file_mips_gp32
>= 0)
15464 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15466 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15471 /* 'default' has traditionally been a no-op. Probably not very useful. */
15472 if (strcasecmp (cpu_string
, "default") == 0)
15475 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15476 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15479 as_bad (_("Bad value (%s) for %s"), cpu_string
, option
);
15483 /* Return the canonical processor information for ISA (a member of the
15484 ISA_MIPS* enumeration). */
15486 static const struct mips_cpu_info
*
15487 mips_cpu_info_from_isa (int isa
)
15491 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15492 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15493 && isa
== mips_cpu_info_table
[i
].isa
)
15494 return (&mips_cpu_info_table
[i
]);
15499 static const struct mips_cpu_info
*
15500 mips_cpu_info_from_arch (int arch
)
15504 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15505 if (arch
== mips_cpu_info_table
[i
].cpu
)
15506 return (&mips_cpu_info_table
[i
]);
15512 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15516 fprintf (stream
, "%24s", "");
15521 fprintf (stream
, ", ");
15525 if (*col_p
+ strlen (string
) > 72)
15527 fprintf (stream
, "\n%24s", "");
15531 fprintf (stream
, "%s", string
);
15532 *col_p
+= strlen (string
);
15538 md_show_usage (FILE *stream
)
15543 fprintf (stream
, _("\
15545 -EB generate big endian output\n\
15546 -EL generate little endian output\n\
15547 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15548 -G NUM allow referencing objects up to NUM bytes\n\
15549 implicitly with the gp register [default 8]\n"));
15550 fprintf (stream
, _("\
15551 -mips1 generate MIPS ISA I instructions\n\
15552 -mips2 generate MIPS ISA II instructions\n\
15553 -mips3 generate MIPS ISA III instructions\n\
15554 -mips4 generate MIPS ISA IV instructions\n\
15555 -mips5 generate MIPS ISA V instructions\n\
15556 -mips32 generate MIPS32 ISA instructions\n\
15557 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15558 -mips64 generate MIPS64 ISA instructions\n\
15559 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15560 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15564 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15565 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15566 show (stream
, "from-abi", &column
, &first
);
15567 fputc ('\n', stream
);
15569 fprintf (stream
, _("\
15570 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15571 -no-mCPU don't generate code specific to CPU.\n\
15572 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15576 show (stream
, "3900", &column
, &first
);
15577 show (stream
, "4010", &column
, &first
);
15578 show (stream
, "4100", &column
, &first
);
15579 show (stream
, "4650", &column
, &first
);
15580 fputc ('\n', stream
);
15582 fprintf (stream
, _("\
15583 -mips16 generate mips16 instructions\n\
15584 -no-mips16 do not generate mips16 instructions\n"));
15585 fprintf (stream
, _("\
15586 -msmartmips generate smartmips instructions\n\
15587 -mno-smartmips do not generate smartmips instructions\n"));
15588 fprintf (stream
, _("\
15589 -mdsp generate DSP instructions\n\
15590 -mno-dsp do not generate DSP instructions\n"));
15591 fprintf (stream
, _("\
15592 -mdspr2 generate DSP R2 instructions\n\
15593 -mno-dspr2 do not generate DSP R2 instructions\n"));
15594 fprintf (stream
, _("\
15595 -mmt generate MT instructions\n\
15596 -mno-mt do not generate MT instructions\n"));
15597 fprintf (stream
, _("\
15598 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15599 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15600 -mfix-vr4120 work around certain VR4120 errata\n\
15601 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15602 -mfix-24k insert a nop after ERET and DERET instructions\n\
15603 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15604 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15605 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15606 -msym32 assume all symbols have 32-bit values\n\
15607 -O0 remove unneeded NOPs, do not swap branches\n\
15608 -O remove unneeded NOPs and swap branches\n\
15609 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15610 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15611 fprintf (stream
, _("\
15612 -mhard-float allow floating-point instructions\n\
15613 -msoft-float do not allow floating-point instructions\n\
15614 -msingle-float only allow 32-bit floating-point operations\n\
15615 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15616 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15619 fprintf (stream
, _("\
15620 -KPIC, -call_shared generate SVR4 position independent code\n\
15621 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15622 -mvxworks-pic generate VxWorks position independent code\n\
15623 -non_shared do not generate code that can operate with DSOs\n\
15624 -xgot assume a 32 bit GOT\n\
15625 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15626 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15627 position dependent (non shared) code\n\
15628 -mabi=ABI create ABI conformant object file for:\n"));
15632 show (stream
, "32", &column
, &first
);
15633 show (stream
, "o64", &column
, &first
);
15634 show (stream
, "n32", &column
, &first
);
15635 show (stream
, "64", &column
, &first
);
15636 show (stream
, "eabi", &column
, &first
);
15638 fputc ('\n', stream
);
15640 fprintf (stream
, _("\
15641 -32 create o32 ABI object file (default)\n\
15642 -n32 create n32 ABI object file\n\
15643 -64 create 64 ABI object file\n"));
15649 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
15651 if (HAVE_64BIT_SYMBOLS
)
15652 return dwarf2_format_64bit_irix
;
15654 return dwarf2_format_32bit
;
15659 mips_dwarf2_addr_size (void)
15661 if (HAVE_64BIT_OBJECTS
)
15667 /* Standard calling conventions leave the CFA at SP on entry. */
15669 mips_cfi_frame_initial_instructions (void)
15671 cfi_add_CFA_def_cfa_register (SP
);
15675 tc_mips_regname_to_dw2regnum (char *regname
)
15677 unsigned int regnum
= -1;
15680 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))