1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const template *match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "k6", PROCESSOR_K6
,
582 { "k6_2", PROCESSOR_K6
,
584 { "athlon", PROCESSOR_ATHLON
,
586 { "sledgehammer", PROCESSOR_K8
,
588 { "opteron", PROCESSOR_K8
,
590 { "k8", PROCESSOR_K8
,
592 { "amdfam10", PROCESSOR_AMDFAM10
,
593 CPU_AMDFAM10_FLAGS
},
594 { ".mmx", PROCESSOR_UNKNOWN
,
596 { ".sse", PROCESSOR_UNKNOWN
,
598 { ".sse2", PROCESSOR_UNKNOWN
,
600 { ".sse3", PROCESSOR_UNKNOWN
,
602 { ".ssse3", PROCESSOR_UNKNOWN
,
604 { ".sse4.1", PROCESSOR_UNKNOWN
,
606 { ".sse4.2", PROCESSOR_UNKNOWN
,
608 { ".sse4", PROCESSOR_UNKNOWN
,
610 { ".avx", PROCESSOR_UNKNOWN
,
612 { ".vmx", PROCESSOR_UNKNOWN
,
614 { ".smx", PROCESSOR_UNKNOWN
,
616 { ".xsave", PROCESSOR_UNKNOWN
,
618 { ".aes", PROCESSOR_UNKNOWN
,
620 { ".pclmul", PROCESSOR_UNKNOWN
,
622 { ".clmul", PROCESSOR_UNKNOWN
,
624 { ".fma", PROCESSOR_UNKNOWN
,
626 { ".fma4", PROCESSOR_UNKNOWN
,
628 { ".movbe", PROCESSOR_UNKNOWN
,
630 { ".ept", PROCESSOR_UNKNOWN
,
632 { ".clflush", PROCESSOR_UNKNOWN
,
634 { ".syscall", PROCESSOR_UNKNOWN
,
636 { ".rdtscp", PROCESSOR_UNKNOWN
,
638 { ".3dnow", PROCESSOR_UNKNOWN
,
640 { ".3dnowa", PROCESSOR_UNKNOWN
,
642 { ".padlock", PROCESSOR_UNKNOWN
,
644 { ".pacifica", PROCESSOR_UNKNOWN
,
646 { ".svme", PROCESSOR_UNKNOWN
,
648 { ".sse4a", PROCESSOR_UNKNOWN
,
650 { ".abm", PROCESSOR_UNKNOWN
,
655 /* Like s_lcomm_internal in gas/read.c but the alignment string
656 is allowed to be optional. */
659 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
666 && *input_line_pointer
== ',')
668 align
= parse_align (needs_align
- 1);
670 if (align
== (addressT
) -1)
685 bss_alloc (symbolP
, size
, align
);
690 pe_lcomm (int needs_align
)
692 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
696 const pseudo_typeS md_pseudo_table
[] =
698 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
699 {"align", s_align_bytes
, 0},
701 {"align", s_align_ptwo
, 0},
703 {"arch", set_cpu_arch
, 0},
707 {"lcomm", pe_lcomm
, 1},
709 {"ffloat", float_cons
, 'f'},
710 {"dfloat", float_cons
, 'd'},
711 {"tfloat", float_cons
, 'x'},
713 {"slong", signed_cons
, 4},
714 {"noopt", s_ignore
, 0},
715 {"optim", s_ignore
, 0},
716 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
717 {"code16", set_code_flag
, CODE_16BIT
},
718 {"code32", set_code_flag
, CODE_32BIT
},
719 {"code64", set_code_flag
, CODE_64BIT
},
720 {"intel_syntax", set_intel_syntax
, 1},
721 {"att_syntax", set_intel_syntax
, 0},
722 {"intel_mnemonic", set_intel_mnemonic
, 1},
723 {"att_mnemonic", set_intel_mnemonic
, 0},
724 {"allow_index_reg", set_allow_index_reg
, 1},
725 {"disallow_index_reg", set_allow_index_reg
, 0},
726 {"sse_check", set_sse_check
, 0},
727 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
728 {"largecomm", handle_large_common
, 0},
730 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
731 {"loc", dwarf2_directive_loc
, 0},
732 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
735 {"secrel32", pe_directive_secrel
, 0},
740 /* For interface with expression (). */
741 extern char *input_line_pointer
;
743 /* Hash table for instruction mnemonic lookup. */
744 static struct hash_control
*op_hash
;
746 /* Hash table for register lookup. */
747 static struct hash_control
*reg_hash
;
750 i386_align_code (fragS
*fragP
, int count
)
752 /* Various efficient no-op patterns for aligning code labels.
753 Note: Don't try to assemble the instructions in the comments.
754 0L and 0w are not legal. */
755 static const char f32_1
[] =
757 static const char f32_2
[] =
758 {0x66,0x90}; /* xchg %ax,%ax */
759 static const char f32_3
[] =
760 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
761 static const char f32_4
[] =
762 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
763 static const char f32_5
[] =
765 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
766 static const char f32_6
[] =
767 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
768 static const char f32_7
[] =
769 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
770 static const char f32_8
[] =
772 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
773 static const char f32_9
[] =
774 {0x89,0xf6, /* movl %esi,%esi */
775 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
776 static const char f32_10
[] =
777 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
778 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
779 static const char f32_11
[] =
780 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
781 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
782 static const char f32_12
[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
784 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
785 static const char f32_13
[] =
786 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
787 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
788 static const char f32_14
[] =
789 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
790 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
791 static const char f16_3
[] =
792 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
793 static const char f16_4
[] =
794 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
795 static const char f16_5
[] =
797 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
798 static const char f16_6
[] =
799 {0x89,0xf6, /* mov %si,%si */
800 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
801 static const char f16_7
[] =
802 {0x8d,0x74,0x00, /* lea 0(%si),%si */
803 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
804 static const char f16_8
[] =
805 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
806 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
807 static const char jump_31
[] =
808 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
809 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
810 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
811 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
812 static const char *const f32_patt
[] = {
813 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
814 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
816 static const char *const f16_patt
[] = {
817 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
820 static const char alt_3
[] =
822 /* nopl 0(%[re]ax) */
823 static const char alt_4
[] =
824 {0x0f,0x1f,0x40,0x00};
825 /* nopl 0(%[re]ax,%[re]ax,1) */
826 static const char alt_5
[] =
827 {0x0f,0x1f,0x44,0x00,0x00};
828 /* nopw 0(%[re]ax,%[re]ax,1) */
829 static const char alt_6
[] =
830 {0x66,0x0f,0x1f,0x44,0x00,0x00};
831 /* nopl 0L(%[re]ax) */
832 static const char alt_7
[] =
833 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
834 /* nopl 0L(%[re]ax,%[re]ax,1) */
835 static const char alt_8
[] =
836 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
837 /* nopw 0L(%[re]ax,%[re]ax,1) */
838 static const char alt_9
[] =
839 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
840 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
841 static const char alt_10
[] =
842 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
844 nopw %cs:0L(%[re]ax,%[re]ax,1) */
845 static const char alt_long_11
[] =
847 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
850 nopw %cs:0L(%[re]ax,%[re]ax,1) */
851 static const char alt_long_12
[] =
854 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_long_13
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 nopw %cs:0L(%[re]ax,%[re]ax,1) */
869 static const char alt_long_14
[] =
874 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 nopw %cs:0L(%[re]ax,%[re]ax,1) */
881 static const char alt_long_15
[] =
887 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
888 /* nopl 0(%[re]ax,%[re]ax,1)
889 nopw 0(%[re]ax,%[re]ax,1) */
890 static const char alt_short_11
[] =
891 {0x0f,0x1f,0x44,0x00,0x00,
892 0x66,0x0f,0x1f,0x44,0x00,0x00};
893 /* nopw 0(%[re]ax,%[re]ax,1)
894 nopw 0(%[re]ax,%[re]ax,1) */
895 static const char alt_short_12
[] =
896 {0x66,0x0f,0x1f,0x44,0x00,0x00,
897 0x66,0x0f,0x1f,0x44,0x00,0x00};
898 /* nopw 0(%[re]ax,%[re]ax,1)
900 static const char alt_short_13
[] =
901 {0x66,0x0f,0x1f,0x44,0x00,0x00,
902 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
905 static const char alt_short_14
[] =
906 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
907 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
909 nopl 0L(%[re]ax,%[re]ax,1) */
910 static const char alt_short_15
[] =
911 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
912 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 static const char *const alt_short_patt
[] = {
914 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
915 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
916 alt_short_14
, alt_short_15
918 static const char *const alt_long_patt
[] = {
919 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
920 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
921 alt_long_14
, alt_long_15
924 /* Only align for at least a positive non-zero boundary. */
925 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
928 /* We need to decide which NOP sequence to use for 32bit and
929 64bit. When -mtune= is used:
931 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
932 PROCESSOR_GENERIC32, f32_patt will be used.
933 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
934 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
935 PROCESSOR_GENERIC64, alt_long_patt will be used.
936 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
937 PROCESSOR_AMDFAM10, alt_short_patt will be used.
939 When -mtune= isn't used, alt_long_patt will be used if
940 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
943 When -march= or .arch is used, we can't use anything beyond
944 cpu_arch_isa_flags. */
946 if (flag_code
== CODE_16BIT
)
950 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
952 /* Adjust jump offset. */
953 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
956 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
957 f16_patt
[count
- 1], count
);
961 const char *const *patt
= NULL
;
963 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
965 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
966 switch (cpu_arch_tune
)
968 case PROCESSOR_UNKNOWN
:
969 /* We use cpu_arch_isa_flags to check if we SHOULD
970 optimize for Cpu686. */
971 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
972 patt
= alt_long_patt
;
976 case PROCESSOR_PENTIUMPRO
:
977 case PROCESSOR_PENTIUM4
:
978 case PROCESSOR_NOCONA
:
980 case PROCESSOR_CORE2
:
981 case PROCESSOR_COREI7
:
982 case PROCESSOR_GENERIC64
:
983 patt
= alt_long_patt
;
986 case PROCESSOR_ATHLON
:
988 case PROCESSOR_AMDFAM10
:
989 patt
= alt_short_patt
;
993 case PROCESSOR_PENTIUM
:
994 case PROCESSOR_GENERIC32
:
1001 switch (fragP
->tc_frag_data
.tune
)
1003 case PROCESSOR_UNKNOWN
:
1004 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1005 PROCESSOR_UNKNOWN. */
1009 case PROCESSOR_I386
:
1010 case PROCESSOR_I486
:
1011 case PROCESSOR_PENTIUM
:
1013 case PROCESSOR_ATHLON
:
1015 case PROCESSOR_AMDFAM10
:
1016 case PROCESSOR_GENERIC32
:
1017 /* We use cpu_arch_isa_flags to check if we CAN optimize
1019 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1020 patt
= alt_short_patt
;
1024 case PROCESSOR_PENTIUMPRO
:
1025 case PROCESSOR_PENTIUM4
:
1026 case PROCESSOR_NOCONA
:
1027 case PROCESSOR_CORE
:
1028 case PROCESSOR_CORE2
:
1029 case PROCESSOR_COREI7
:
1030 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1031 patt
= alt_long_patt
;
1035 case PROCESSOR_GENERIC64
:
1036 patt
= alt_long_patt
;
1041 if (patt
== f32_patt
)
1043 /* If the padding is less than 15 bytes, we use the normal
1044 ones. Otherwise, we use a jump instruction and adjust
1047 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1048 patt
[count
- 1], count
);
1051 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1053 /* Adjust jump offset. */
1054 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1059 /* Maximum length of an instruction is 15 byte. If the
1060 padding is greater than 15 bytes and we don't use jump,
1061 we have to break it into smaller pieces. */
1062 int padding
= count
;
1063 while (padding
> 15)
1066 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1071 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1072 patt
[padding
- 1], padding
);
1075 fragP
->fr_var
= count
;
1079 operand_type_all_zero (const union i386_operand_type
*x
)
1081 switch (ARRAY_SIZE(x
->array
))
1090 return !x
->array
[0];
1097 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1099 switch (ARRAY_SIZE(x
->array
))
1114 operand_type_equal (const union i386_operand_type
*x
,
1115 const union i386_operand_type
*y
)
1117 switch (ARRAY_SIZE(x
->array
))
1120 if (x
->array
[2] != y
->array
[2])
1123 if (x
->array
[1] != y
->array
[1])
1126 return x
->array
[0] == y
->array
[0];
1134 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1136 switch (ARRAY_SIZE(x
->array
))
1145 return !x
->array
[0];
1152 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1154 switch (ARRAY_SIZE(x
->array
))
1169 cpu_flags_equal (const union i386_cpu_flags
*x
,
1170 const union i386_cpu_flags
*y
)
1172 switch (ARRAY_SIZE(x
->array
))
1175 if (x
->array
[2] != y
->array
[2])
1178 if (x
->array
[1] != y
->array
[1])
1181 return x
->array
[0] == y
->array
[0];
1189 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1191 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1192 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1195 static INLINE i386_cpu_flags
1196 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1198 switch (ARRAY_SIZE (x
.array
))
1201 x
.array
[2] &= y
.array
[2];
1203 x
.array
[1] &= y
.array
[1];
1205 x
.array
[0] &= y
.array
[0];
1213 static INLINE i386_cpu_flags
1214 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1216 switch (ARRAY_SIZE (x
.array
))
1219 x
.array
[2] |= y
.array
[2];
1221 x
.array
[1] |= y
.array
[1];
1223 x
.array
[0] |= y
.array
[0];
1231 #define CPU_FLAGS_ARCH_MATCH 0x1
1232 #define CPU_FLAGS_64BIT_MATCH 0x2
1233 #define CPU_FLAGS_AES_MATCH 0x4
1234 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1235 #define CPU_FLAGS_AVX_MATCH 0x10
1237 #define CPU_FLAGS_32BIT_MATCH \
1238 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1239 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1240 #define CPU_FLAGS_PERFECT_MATCH \
1241 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1243 /* Return CPU flags match bits. */
1246 cpu_flags_match (const template *t
)
1248 i386_cpu_flags x
= t
->cpu_flags
;
1249 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1251 x
.bitfield
.cpu64
= 0;
1252 x
.bitfield
.cpuno64
= 0;
1254 if (cpu_flags_all_zero (&x
))
1256 /* This instruction is available on all archs. */
1257 match
|= CPU_FLAGS_32BIT_MATCH
;
1261 /* This instruction is available only on some archs. */
1262 i386_cpu_flags cpu
= cpu_arch_flags
;
1264 cpu
.bitfield
.cpu64
= 0;
1265 cpu
.bitfield
.cpuno64
= 0;
1266 cpu
= cpu_flags_and (x
, cpu
);
1267 if (!cpu_flags_all_zero (&cpu
))
1269 if (x
.bitfield
.cpuavx
)
1271 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1272 if (cpu
.bitfield
.cpuavx
)
1274 /* Check SSE2AVX. */
1275 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1277 match
|= (CPU_FLAGS_ARCH_MATCH
1278 | CPU_FLAGS_AVX_MATCH
);
1280 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1281 match
|= CPU_FLAGS_AES_MATCH
;
1283 if (!x
.bitfield
.cpupclmul
1284 || cpu
.bitfield
.cpupclmul
)
1285 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1289 match
|= CPU_FLAGS_ARCH_MATCH
;
1292 match
|= CPU_FLAGS_32BIT_MATCH
;
1298 static INLINE i386_operand_type
1299 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1301 switch (ARRAY_SIZE (x
.array
))
1304 x
.array
[2] &= y
.array
[2];
1306 x
.array
[1] &= y
.array
[1];
1308 x
.array
[0] &= y
.array
[0];
1316 static INLINE i386_operand_type
1317 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1319 switch (ARRAY_SIZE (x
.array
))
1322 x
.array
[2] |= y
.array
[2];
1324 x
.array
[1] |= y
.array
[1];
1326 x
.array
[0] |= y
.array
[0];
1334 static INLINE i386_operand_type
1335 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1337 switch (ARRAY_SIZE (x
.array
))
1340 x
.array
[2] ^= y
.array
[2];
1342 x
.array
[1] ^= y
.array
[1];
1344 x
.array
[0] ^= y
.array
[0];
1352 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1353 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1354 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1355 static const i386_operand_type inoutportreg
1356 = OPERAND_TYPE_INOUTPORTREG
;
1357 static const i386_operand_type reg16_inoutportreg
1358 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1359 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1360 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1361 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1362 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1363 static const i386_operand_type anydisp
1364 = OPERAND_TYPE_ANYDISP
;
1365 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1366 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1367 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1368 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1369 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1370 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1371 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1372 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1373 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1374 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1375 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1386 operand_type_check (i386_operand_type t
, enum operand_type c
)
1391 return (t
.bitfield
.reg8
1394 || t
.bitfield
.reg64
);
1397 return (t
.bitfield
.imm8
1401 || t
.bitfield
.imm32s
1402 || t
.bitfield
.imm64
);
1405 return (t
.bitfield
.disp8
1406 || t
.bitfield
.disp16
1407 || t
.bitfield
.disp32
1408 || t
.bitfield
.disp32s
1409 || t
.bitfield
.disp64
);
1412 return (t
.bitfield
.disp8
1413 || t
.bitfield
.disp16
1414 || t
.bitfield
.disp32
1415 || t
.bitfield
.disp32s
1416 || t
.bitfield
.disp64
1417 || t
.bitfield
.baseindex
);
1426 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1427 operand J for instruction template T. */
1430 match_reg_size (const template *t
, unsigned int j
)
1432 return !((i
.types
[j
].bitfield
.byte
1433 && !t
->operand_types
[j
].bitfield
.byte
)
1434 || (i
.types
[j
].bitfield
.word
1435 && !t
->operand_types
[j
].bitfield
.word
)
1436 || (i
.types
[j
].bitfield
.dword
1437 && !t
->operand_types
[j
].bitfield
.dword
)
1438 || (i
.types
[j
].bitfield
.qword
1439 && !t
->operand_types
[j
].bitfield
.qword
));
1442 /* Return 1 if there is no conflict in any size on operand J for
1443 instruction template T. */
1446 match_mem_size (const template *t
, unsigned int j
)
1448 return (match_reg_size (t
, j
)
1449 && !((i
.types
[j
].bitfield
.unspecified
1450 && !t
->operand_types
[j
].bitfield
.unspecified
)
1451 || (i
.types
[j
].bitfield
.fword
1452 && !t
->operand_types
[j
].bitfield
.fword
)
1453 || (i
.types
[j
].bitfield
.tbyte
1454 && !t
->operand_types
[j
].bitfield
.tbyte
)
1455 || (i
.types
[j
].bitfield
.xmmword
1456 && !t
->operand_types
[j
].bitfield
.xmmword
)
1457 || (i
.types
[j
].bitfield
.ymmword
1458 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1461 /* Return 1 if there is no size conflict on any operands for
1462 instruction template T. */
1465 operand_size_match (const template *t
)
1470 /* Don't check jump instructions. */
1471 if (t
->opcode_modifier
.jump
1472 || t
->opcode_modifier
.jumpbyte
1473 || t
->opcode_modifier
.jumpdword
1474 || t
->opcode_modifier
.jumpintersegment
)
1477 /* Check memory and accumulator operand size. */
1478 for (j
= 0; j
< i
.operands
; j
++)
1480 if (t
->operand_types
[j
].bitfield
.anysize
)
1483 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1489 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1497 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1500 /* Check reverse. */
1501 gas_assert (i
.operands
== 2);
1504 for (j
= 0; j
< 2; j
++)
1506 if (t
->operand_types
[j
].bitfield
.acc
1507 && !match_reg_size (t
, j
? 0 : 1))
1513 if (i
.types
[j
].bitfield
.mem
1514 && !match_mem_size (t
, j
? 0 : 1))
1525 operand_type_match (i386_operand_type overlap
,
1526 i386_operand_type given
)
1528 i386_operand_type temp
= overlap
;
1530 temp
.bitfield
.jumpabsolute
= 0;
1531 temp
.bitfield
.unspecified
= 0;
1532 temp
.bitfield
.byte
= 0;
1533 temp
.bitfield
.word
= 0;
1534 temp
.bitfield
.dword
= 0;
1535 temp
.bitfield
.fword
= 0;
1536 temp
.bitfield
.qword
= 0;
1537 temp
.bitfield
.tbyte
= 0;
1538 temp
.bitfield
.xmmword
= 0;
1539 temp
.bitfield
.ymmword
= 0;
1540 if (operand_type_all_zero (&temp
))
1543 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1544 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1547 /* If given types g0 and g1 are registers they must be of the same type
1548 unless the expected operand type register overlap is null.
1549 Note that Acc in a template matches every size of reg. */
1552 operand_type_register_match (i386_operand_type m0
,
1553 i386_operand_type g0
,
1554 i386_operand_type t0
,
1555 i386_operand_type m1
,
1556 i386_operand_type g1
,
1557 i386_operand_type t1
)
1559 if (!operand_type_check (g0
, reg
))
1562 if (!operand_type_check (g1
, reg
))
1565 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1566 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1567 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1568 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1571 if (m0
.bitfield
.acc
)
1573 t0
.bitfield
.reg8
= 1;
1574 t0
.bitfield
.reg16
= 1;
1575 t0
.bitfield
.reg32
= 1;
1576 t0
.bitfield
.reg64
= 1;
1579 if (m1
.bitfield
.acc
)
1581 t1
.bitfield
.reg8
= 1;
1582 t1
.bitfield
.reg16
= 1;
1583 t1
.bitfield
.reg32
= 1;
1584 t1
.bitfield
.reg64
= 1;
1587 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1588 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1589 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1590 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1593 static INLINE
unsigned int
1594 mode_from_disp_size (i386_operand_type t
)
1596 if (t
.bitfield
.disp8
)
1598 else if (t
.bitfield
.disp16
1599 || t
.bitfield
.disp32
1600 || t
.bitfield
.disp32s
)
1607 fits_in_signed_byte (offsetT num
)
1609 return (num
>= -128) && (num
<= 127);
1613 fits_in_unsigned_byte (offsetT num
)
1615 return (num
& 0xff) == num
;
1619 fits_in_unsigned_word (offsetT num
)
1621 return (num
& 0xffff) == num
;
1625 fits_in_signed_word (offsetT num
)
1627 return (-32768 <= num
) && (num
<= 32767);
1631 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1636 return (!(((offsetT
) -1 << 31) & num
)
1637 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1639 } /* fits_in_signed_long() */
1642 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1647 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1649 } /* fits_in_unsigned_long() */
1651 static i386_operand_type
1652 smallest_imm_type (offsetT num
)
1654 i386_operand_type t
;
1656 operand_type_set (&t
, 0);
1657 t
.bitfield
.imm64
= 1;
1659 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1661 /* This code is disabled on the 486 because all the Imm1 forms
1662 in the opcode table are slower on the i486. They're the
1663 versions with the implicitly specified single-position
1664 displacement, which has another syntax if you really want to
1666 t
.bitfield
.imm1
= 1;
1667 t
.bitfield
.imm8
= 1;
1668 t
.bitfield
.imm8s
= 1;
1669 t
.bitfield
.imm16
= 1;
1670 t
.bitfield
.imm32
= 1;
1671 t
.bitfield
.imm32s
= 1;
1673 else if (fits_in_signed_byte (num
))
1675 t
.bitfield
.imm8
= 1;
1676 t
.bitfield
.imm8s
= 1;
1677 t
.bitfield
.imm16
= 1;
1678 t
.bitfield
.imm32
= 1;
1679 t
.bitfield
.imm32s
= 1;
1681 else if (fits_in_unsigned_byte (num
))
1683 t
.bitfield
.imm8
= 1;
1684 t
.bitfield
.imm16
= 1;
1685 t
.bitfield
.imm32
= 1;
1686 t
.bitfield
.imm32s
= 1;
1688 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1690 t
.bitfield
.imm16
= 1;
1691 t
.bitfield
.imm32
= 1;
1692 t
.bitfield
.imm32s
= 1;
1694 else if (fits_in_signed_long (num
))
1696 t
.bitfield
.imm32
= 1;
1697 t
.bitfield
.imm32s
= 1;
1699 else if (fits_in_unsigned_long (num
))
1700 t
.bitfield
.imm32
= 1;
1706 offset_in_range (offsetT val
, int size
)
1712 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1713 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1714 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1716 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1721 /* If BFD64, sign extend val. */
1722 if (!use_rela_relocations
)
1723 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1724 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1726 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1728 char buf1
[40], buf2
[40];
1730 sprint_value (buf1
, val
);
1731 sprint_value (buf2
, val
& mask
);
1732 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1737 /* Returns 0 if attempting to add a prefix where one from the same
1738 class already exists, 1 if non rep/repne added, 2 if rep/repne
1741 add_prefix (unsigned int prefix
)
1746 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1747 && flag_code
== CODE_64BIT
)
1749 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1750 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1751 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1762 case CS_PREFIX_OPCODE
:
1763 case DS_PREFIX_OPCODE
:
1764 case ES_PREFIX_OPCODE
:
1765 case FS_PREFIX_OPCODE
:
1766 case GS_PREFIX_OPCODE
:
1767 case SS_PREFIX_OPCODE
:
1771 case REPNE_PREFIX_OPCODE
:
1772 case REPE_PREFIX_OPCODE
:
1775 case LOCK_PREFIX_OPCODE
:
1783 case ADDR_PREFIX_OPCODE
:
1787 case DATA_PREFIX_OPCODE
:
1791 if (i
.prefix
[q
] != 0)
1799 i
.prefix
[q
] |= prefix
;
1802 as_bad (_("same type of prefix used twice"));
1808 set_code_flag (int value
)
1811 if (flag_code
== CODE_64BIT
)
1813 cpu_arch_flags
.bitfield
.cpu64
= 1;
1814 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1818 cpu_arch_flags
.bitfield
.cpu64
= 0;
1819 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1821 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1823 as_bad (_("64bit mode not supported on this CPU."));
1825 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1827 as_bad (_("32bit mode not supported on this CPU."));
1829 stackop_size
= '\0';
1833 set_16bit_gcc_code_flag (int new_code_flag
)
1835 flag_code
= new_code_flag
;
1836 if (flag_code
!= CODE_16BIT
)
1838 cpu_arch_flags
.bitfield
.cpu64
= 0;
1839 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1840 stackop_size
= LONG_MNEM_SUFFIX
;
1844 set_intel_syntax (int syntax_flag
)
1846 /* Find out if register prefixing is specified. */
1847 int ask_naked_reg
= 0;
1850 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1852 char *string
= input_line_pointer
;
1853 int e
= get_symbol_end ();
1855 if (strcmp (string
, "prefix") == 0)
1857 else if (strcmp (string
, "noprefix") == 0)
1860 as_bad (_("bad argument to syntax directive."));
1861 *input_line_pointer
= e
;
1863 demand_empty_rest_of_line ();
1865 intel_syntax
= syntax_flag
;
1867 if (ask_naked_reg
== 0)
1868 allow_naked_reg
= (intel_syntax
1869 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1871 allow_naked_reg
= (ask_naked_reg
< 0);
1873 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1875 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1876 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1877 register_prefix
= allow_naked_reg
? "" : "%";
1881 set_intel_mnemonic (int mnemonic_flag
)
1883 intel_mnemonic
= mnemonic_flag
;
1887 set_allow_index_reg (int flag
)
1889 allow_index_reg
= flag
;
1893 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1897 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1899 char *string
= input_line_pointer
;
1900 int e
= get_symbol_end ();
1902 if (strcmp (string
, "none") == 0)
1903 sse_check
= sse_check_none
;
1904 else if (strcmp (string
, "warning") == 0)
1905 sse_check
= sse_check_warning
;
1906 else if (strcmp (string
, "error") == 0)
1907 sse_check
= sse_check_error
;
1909 as_bad (_("bad argument to sse_check directive."));
1910 *input_line_pointer
= e
;
1913 as_bad (_("missing argument for sse_check directive"));
1915 demand_empty_rest_of_line ();
1919 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1923 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1925 char *string
= input_line_pointer
;
1926 int e
= get_symbol_end ();
1928 i386_cpu_flags flags
;
1930 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1932 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1936 cpu_arch_name
= cpu_arch
[i
].name
;
1937 cpu_sub_arch_name
= NULL
;
1938 cpu_arch_flags
= cpu_arch
[i
].flags
;
1939 if (flag_code
== CODE_64BIT
)
1941 cpu_arch_flags
.bitfield
.cpu64
= 1;
1942 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1946 cpu_arch_flags
.bitfield
.cpu64
= 0;
1947 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1949 cpu_arch_isa
= cpu_arch
[i
].type
;
1950 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1951 if (!cpu_arch_tune_set
)
1953 cpu_arch_tune
= cpu_arch_isa
;
1954 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1959 flags
= cpu_flags_or (cpu_arch_flags
,
1961 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1963 if (cpu_sub_arch_name
)
1965 char *name
= cpu_sub_arch_name
;
1966 cpu_sub_arch_name
= concat (name
,
1968 (const char *) NULL
);
1972 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1973 cpu_arch_flags
= flags
;
1975 *input_line_pointer
= e
;
1976 demand_empty_rest_of_line ();
1980 if (i
>= ARRAY_SIZE (cpu_arch
))
1981 as_bad (_("no such architecture: `%s'"), string
);
1983 *input_line_pointer
= e
;
1986 as_bad (_("missing cpu architecture"));
1988 no_cond_jump_promotion
= 0;
1989 if (*input_line_pointer
== ','
1990 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1992 char *string
= ++input_line_pointer
;
1993 int e
= get_symbol_end ();
1995 if (strcmp (string
, "nojumps") == 0)
1996 no_cond_jump_promotion
= 1;
1997 else if (strcmp (string
, "jumps") == 0)
2000 as_bad (_("no such architecture modifier: `%s'"), string
);
2002 *input_line_pointer
= e
;
2005 demand_empty_rest_of_line ();
2011 if (!strcmp (default_arch
, "x86_64"))
2012 return bfd_mach_x86_64
;
2013 else if (!strcmp (default_arch
, "i386"))
2014 return bfd_mach_i386_i386
;
2016 as_fatal (_("Unknown architecture"));
2022 const char *hash_err
;
2024 /* Initialize op_hash hash table. */
2025 op_hash
= hash_new ();
2028 const template *optab
;
2029 templates
*core_optab
;
2031 /* Setup for loop. */
2033 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2034 core_optab
->start
= optab
;
2039 if (optab
->name
== NULL
2040 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2042 /* different name --> ship out current template list;
2043 add to hash table; & begin anew. */
2044 core_optab
->end
= optab
;
2045 hash_err
= hash_insert (op_hash
,
2047 (void *) core_optab
);
2050 as_fatal (_("Internal Error: Can't hash %s: %s"),
2054 if (optab
->name
== NULL
)
2056 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2057 core_optab
->start
= optab
;
2062 /* Initialize reg_hash hash table. */
2063 reg_hash
= hash_new ();
2065 const reg_entry
*regtab
;
2066 unsigned int regtab_size
= i386_regtab_size
;
2068 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2070 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2072 as_fatal (_("Internal Error: Can't hash %s: %s"),
2078 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2083 for (c
= 0; c
< 256; c
++)
2088 mnemonic_chars
[c
] = c
;
2089 register_chars
[c
] = c
;
2090 operand_chars
[c
] = c
;
2092 else if (ISLOWER (c
))
2094 mnemonic_chars
[c
] = c
;
2095 register_chars
[c
] = c
;
2096 operand_chars
[c
] = c
;
2098 else if (ISUPPER (c
))
2100 mnemonic_chars
[c
] = TOLOWER (c
);
2101 register_chars
[c
] = mnemonic_chars
[c
];
2102 operand_chars
[c
] = c
;
2105 if (ISALPHA (c
) || ISDIGIT (c
))
2106 identifier_chars
[c
] = c
;
2109 identifier_chars
[c
] = c
;
2110 operand_chars
[c
] = c
;
2115 identifier_chars
['@'] = '@';
2118 identifier_chars
['?'] = '?';
2119 operand_chars
['?'] = '?';
2121 digit_chars
['-'] = '-';
2122 mnemonic_chars
['_'] = '_';
2123 mnemonic_chars
['-'] = '-';
2124 mnemonic_chars
['.'] = '.';
2125 identifier_chars
['_'] = '_';
2126 identifier_chars
['.'] = '.';
2128 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2129 operand_chars
[(unsigned char) *p
] = *p
;
2132 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2135 record_alignment (text_section
, 2);
2136 record_alignment (data_section
, 2);
2137 record_alignment (bss_section
, 2);
2141 if (flag_code
== CODE_64BIT
)
2143 x86_dwarf2_return_column
= 16;
2144 x86_cie_data_alignment
= -8;
2148 x86_dwarf2_return_column
= 8;
2149 x86_cie_data_alignment
= -4;
2154 i386_print_statistics (FILE *file
)
2156 hash_print_statistics (file
, "i386 opcode", op_hash
);
2157 hash_print_statistics (file
, "i386 register", reg_hash
);
2162 /* Debugging routines for md_assemble. */
2163 static void pte (template *);
2164 static void pt (i386_operand_type
);
2165 static void pe (expressionS
*);
2166 static void ps (symbolS
*);
2169 pi (char *line
, i386_insn
*x
)
2173 fprintf (stdout
, "%s: template ", line
);
2175 fprintf (stdout
, " address: base %s index %s scale %x\n",
2176 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2177 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2178 x
->log2_scale_factor
);
2179 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2180 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2181 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2182 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2183 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2184 (x
->rex
& REX_W
) != 0,
2185 (x
->rex
& REX_R
) != 0,
2186 (x
->rex
& REX_X
) != 0,
2187 (x
->rex
& REX_B
) != 0);
2188 for (i
= 0; i
< x
->operands
; i
++)
2190 fprintf (stdout
, " #%d: ", i
+ 1);
2192 fprintf (stdout
, "\n");
2193 if (x
->types
[i
].bitfield
.reg8
2194 || x
->types
[i
].bitfield
.reg16
2195 || x
->types
[i
].bitfield
.reg32
2196 || x
->types
[i
].bitfield
.reg64
2197 || x
->types
[i
].bitfield
.regmmx
2198 || x
->types
[i
].bitfield
.regxmm
2199 || x
->types
[i
].bitfield
.regymm
2200 || x
->types
[i
].bitfield
.sreg2
2201 || x
->types
[i
].bitfield
.sreg3
2202 || x
->types
[i
].bitfield
.control
2203 || x
->types
[i
].bitfield
.debug
2204 || x
->types
[i
].bitfield
.test
)
2205 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2206 if (operand_type_check (x
->types
[i
], imm
))
2208 if (operand_type_check (x
->types
[i
], disp
))
2209 pe (x
->op
[i
].disps
);
2217 fprintf (stdout
, " %d operands ", t
->operands
);
2218 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2219 if (t
->extension_opcode
!= None
)
2220 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2221 if (t
->opcode_modifier
.d
)
2222 fprintf (stdout
, "D");
2223 if (t
->opcode_modifier
.w
)
2224 fprintf (stdout
, "W");
2225 fprintf (stdout
, "\n");
2226 for (i
= 0; i
< t
->operands
; i
++)
2228 fprintf (stdout
, " #%d type ", i
+ 1);
2229 pt (t
->operand_types
[i
]);
2230 fprintf (stdout
, "\n");
2237 fprintf (stdout
, " operation %d\n", e
->X_op
);
2238 fprintf (stdout
, " add_number %ld (%lx)\n",
2239 (long) e
->X_add_number
, (long) e
->X_add_number
);
2240 if (e
->X_add_symbol
)
2242 fprintf (stdout
, " add_symbol ");
2243 ps (e
->X_add_symbol
);
2244 fprintf (stdout
, "\n");
2248 fprintf (stdout
, " op_symbol ");
2249 ps (e
->X_op_symbol
);
2250 fprintf (stdout
, "\n");
2257 fprintf (stdout
, "%s type %s%s",
2259 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2260 segment_name (S_GET_SEGMENT (s
)));
2263 static struct type_name
2265 i386_operand_type mask
;
2268 const type_names
[] =
2270 { OPERAND_TYPE_REG8
, "r8" },
2271 { OPERAND_TYPE_REG16
, "r16" },
2272 { OPERAND_TYPE_REG32
, "r32" },
2273 { OPERAND_TYPE_REG64
, "r64" },
2274 { OPERAND_TYPE_IMM8
, "i8" },
2275 { OPERAND_TYPE_IMM8
, "i8s" },
2276 { OPERAND_TYPE_IMM16
, "i16" },
2277 { OPERAND_TYPE_IMM32
, "i32" },
2278 { OPERAND_TYPE_IMM32S
, "i32s" },
2279 { OPERAND_TYPE_IMM64
, "i64" },
2280 { OPERAND_TYPE_IMM1
, "i1" },
2281 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2282 { OPERAND_TYPE_DISP8
, "d8" },
2283 { OPERAND_TYPE_DISP16
, "d16" },
2284 { OPERAND_TYPE_DISP32
, "d32" },
2285 { OPERAND_TYPE_DISP32S
, "d32s" },
2286 { OPERAND_TYPE_DISP64
, "d64" },
2287 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2288 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2289 { OPERAND_TYPE_CONTROL
, "control reg" },
2290 { OPERAND_TYPE_TEST
, "test reg" },
2291 { OPERAND_TYPE_DEBUG
, "debug reg" },
2292 { OPERAND_TYPE_FLOATREG
, "FReg" },
2293 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2294 { OPERAND_TYPE_SREG2
, "SReg2" },
2295 { OPERAND_TYPE_SREG3
, "SReg3" },
2296 { OPERAND_TYPE_ACC
, "Acc" },
2297 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2298 { OPERAND_TYPE_REGMMX
, "rMMX" },
2299 { OPERAND_TYPE_REGXMM
, "rXMM" },
2300 { OPERAND_TYPE_REGYMM
, "rYMM" },
2301 { OPERAND_TYPE_ESSEG
, "es" },
2305 pt (i386_operand_type t
)
2308 i386_operand_type a
;
2310 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2312 a
= operand_type_and (t
, type_names
[j
].mask
);
2313 if (!operand_type_all_zero (&a
))
2314 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2319 #endif /* DEBUG386 */
2321 static bfd_reloc_code_real_type
2322 reloc (unsigned int size
,
2325 bfd_reloc_code_real_type other
)
2327 if (other
!= NO_RELOC
)
2329 reloc_howto_type
*reloc
;
2334 case BFD_RELOC_X86_64_GOT32
:
2335 return BFD_RELOC_X86_64_GOT64
;
2337 case BFD_RELOC_X86_64_PLTOFF64
:
2338 return BFD_RELOC_X86_64_PLTOFF64
;
2340 case BFD_RELOC_X86_64_GOTPC32
:
2341 other
= BFD_RELOC_X86_64_GOTPC64
;
2343 case BFD_RELOC_X86_64_GOTPCREL
:
2344 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2346 case BFD_RELOC_X86_64_TPOFF32
:
2347 other
= BFD_RELOC_X86_64_TPOFF64
;
2349 case BFD_RELOC_X86_64_DTPOFF32
:
2350 other
= BFD_RELOC_X86_64_DTPOFF64
;
2356 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2357 if (size
== 4 && flag_code
!= CODE_64BIT
)
2360 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2362 as_bad (_("unknown relocation (%u)"), other
);
2363 else if (size
!= bfd_get_reloc_size (reloc
))
2364 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2365 bfd_get_reloc_size (reloc
),
2367 else if (pcrel
&& !reloc
->pc_relative
)
2368 as_bad (_("non-pc-relative relocation for pc-relative field"));
2369 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2371 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2373 as_bad (_("relocated field and relocation type differ in signedness"));
2382 as_bad (_("there are no unsigned pc-relative relocations"));
2385 case 1: return BFD_RELOC_8_PCREL
;
2386 case 2: return BFD_RELOC_16_PCREL
;
2387 case 4: return BFD_RELOC_32_PCREL
;
2388 case 8: return BFD_RELOC_64_PCREL
;
2390 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2397 case 4: return BFD_RELOC_X86_64_32S
;
2402 case 1: return BFD_RELOC_8
;
2403 case 2: return BFD_RELOC_16
;
2404 case 4: return BFD_RELOC_32
;
2405 case 8: return BFD_RELOC_64
;
2407 as_bad (_("cannot do %s %u byte relocation"),
2408 sign
> 0 ? "signed" : "unsigned", size
);
2414 /* Here we decide which fixups can be adjusted to make them relative to
2415 the beginning of the section instead of the symbol. Basically we need
2416 to make sure that the dynamic relocations are done correctly, so in
2417 some cases we force the original symbol to be used. */
2420 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2422 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2426 /* Don't adjust pc-relative references to merge sections in 64-bit
2428 if (use_rela_relocations
2429 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2433 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2434 and changed later by validate_fix. */
2435 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2436 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2439 /* adjust_reloc_syms doesn't know about the GOT. */
2440 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2441 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2442 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2443 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2444 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2445 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2446 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2447 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2448 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2449 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2450 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2451 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2452 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2453 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2454 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2455 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2456 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2457 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2458 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2459 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2460 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2461 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2462 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2463 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2464 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2465 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2466 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2467 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2470 if (fixP
->fx_addsy
!= NULL
2471 && symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_GNU_INDIRECT_FUNCTION
)
2478 intel_float_operand (const char *mnemonic
)
2480 /* Note that the value returned is meaningful only for opcodes with (memory)
2481 operands, hence the code here is free to improperly handle opcodes that
2482 have no operands (for better performance and smaller code). */
2484 if (mnemonic
[0] != 'f')
2485 return 0; /* non-math */
2487 switch (mnemonic
[1])
2489 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2490 the fs segment override prefix not currently handled because no
2491 call path can make opcodes without operands get here */
2493 return 2 /* integer op */;
2495 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2496 return 3; /* fldcw/fldenv */
2499 if (mnemonic
[2] != 'o' /* fnop */)
2500 return 3; /* non-waiting control op */
2503 if (mnemonic
[2] == 's')
2504 return 3; /* frstor/frstpm */
2507 if (mnemonic
[2] == 'a')
2508 return 3; /* fsave */
2509 if (mnemonic
[2] == 't')
2511 switch (mnemonic
[3])
2513 case 'c': /* fstcw */
2514 case 'd': /* fstdw */
2515 case 'e': /* fstenv */
2516 case 's': /* fsts[gw] */
2522 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2523 return 0; /* fxsave/fxrstor are not really math ops */
2530 /* Build the VEX prefix. */
2533 build_vex_prefix (const template *t
)
2535 unsigned int register_specifier
;
2536 unsigned int implied_prefix
;
2537 unsigned int vector_length
;
2539 /* Check register specifier. */
2540 if (i
.vex
.register_specifier
)
2542 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2543 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2544 register_specifier
+= 8;
2545 register_specifier
= ~register_specifier
& 0xf;
2548 register_specifier
= 0xf;
2550 /* Use 2-byte VEX prefix by swappping destination and source
2553 && i
.operands
== i
.reg_operands
2554 && i
.tm
.opcode_modifier
.vex0f
2555 && i
.tm
.opcode_modifier
.s
2558 unsigned int xchg
= i
.operands
- 1;
2559 union i386_op temp_op
;
2560 i386_operand_type temp_type
;
2562 temp_type
= i
.types
[xchg
];
2563 i
.types
[xchg
] = i
.types
[0];
2564 i
.types
[0] = temp_type
;
2565 temp_op
= i
.op
[xchg
];
2566 i
.op
[xchg
] = i
.op
[0];
2569 gas_assert (i
.rm
.mode
== 3);
2573 i
.rm
.regmem
= i
.rm
.reg
;
2576 /* Use the next insn. */
2580 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2582 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2587 case DATA_PREFIX_OPCODE
:
2590 case REPE_PREFIX_OPCODE
:
2593 case REPNE_PREFIX_OPCODE
:
2600 /* Use 2-byte VEX prefix if possible. */
2601 if (i
.tm
.opcode_modifier
.vex0f
2602 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2604 /* 2-byte VEX prefix. */
2608 i
.vex
.bytes
[0] = 0xc5;
2610 /* Check the REX.R bit. */
2611 r
= (i
.rex
& REX_R
) ? 0 : 1;
2612 i
.vex
.bytes
[1] = (r
<< 7
2613 | register_specifier
<< 3
2614 | vector_length
<< 2
2619 /* 3-byte VEX prefix. */
2622 if (i
.tm
.opcode_modifier
.vex0f
)
2624 else if (i
.tm
.opcode_modifier
.vex0f38
)
2626 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2632 i
.vex
.bytes
[0] = 0xc4;
2634 /* The high 3 bits of the second VEX byte are 1's compliment
2635 of RXB bits from REX. */
2636 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2638 /* Check the REX.W bit. */
2639 w
= (i
.rex
& REX_W
) ? 1 : 0;
2640 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2645 if (i
.tm
.opcode_modifier
.vexw1
)
2649 i
.vex
.bytes
[2] = (w
<< 7
2650 | register_specifier
<< 3
2651 | vector_length
<< 2
2657 process_immext (void)
2661 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2663 /* SSE3 Instructions have the fixed operands with an opcode
2664 suffix which is coded in the same place as an 8-bit immediate
2665 field would be. Here we check those operands and remove them
2669 for (x
= 0; x
< i
.operands
; x
++)
2670 if (i
.op
[x
].regs
->reg_num
!= x
)
2671 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2672 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2678 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2679 which is coded in the same place as an 8-bit immediate field
2680 would be. Here we fake an 8-bit immediate operand from the
2681 opcode suffix stored in tm.extension_opcode.
2683 AVX instructions also use this encoding, for some of
2684 3 argument instructions. */
2686 gas_assert (i
.imm_operands
== 0
2688 || (i
.tm
.opcode_modifier
.vex
2689 && i
.operands
<= 4)));
2691 exp
= &im_expressions
[i
.imm_operands
++];
2692 i
.op
[i
.operands
].imms
= exp
;
2693 i
.types
[i
.operands
] = imm8
;
2695 exp
->X_op
= O_constant
;
2696 exp
->X_add_number
= i
.tm
.extension_opcode
;
2697 i
.tm
.extension_opcode
= None
;
2700 /* This is the guts of the machine-dependent assembler. LINE points to a
2701 machine dependent instruction. This function is supposed to emit
2702 the frags/bytes it assembles to. */
2705 md_assemble (char *line
)
2708 char mnemonic
[MAX_MNEM_SIZE
];
2711 /* Initialize globals. */
2712 memset (&i
, '\0', sizeof (i
));
2713 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2714 i
.reloc
[j
] = NO_RELOC
;
2715 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2716 memset (im_expressions
, '\0', sizeof (im_expressions
));
2717 save_stack_p
= save_stack
;
2719 /* First parse an instruction mnemonic & call i386_operand for the operands.
2720 We assume that the scrubber has arranged it so that line[0] is the valid
2721 start of a (possibly prefixed) mnemonic. */
2723 line
= parse_insn (line
, mnemonic
);
2727 line
= parse_operands (line
, mnemonic
);
2732 /* Now we've parsed the mnemonic into a set of templates, and have the
2733 operands at hand. */
2735 /* All intel opcodes have reversed operands except for "bound" and
2736 "enter". We also don't reverse intersegment "jmp" and "call"
2737 instructions with 2 immediate operands so that the immediate segment
2738 precedes the offset, as it does when in AT&T mode. */
2741 && (strcmp (mnemonic
, "bound") != 0)
2742 && (strcmp (mnemonic
, "invlpga") != 0)
2743 && !(operand_type_check (i
.types
[0], imm
)
2744 && operand_type_check (i
.types
[1], imm
)))
2747 /* The order of the immediates should be reversed
2748 for 2 immediates extrq and insertq instructions */
2749 if (i
.imm_operands
== 2
2750 && (strcmp (mnemonic
, "extrq") == 0
2751 || strcmp (mnemonic
, "insertq") == 0))
2752 swap_2_operands (0, 1);
2757 /* Don't optimize displacement for movabs since it only takes 64bit
2760 && (flag_code
!= CODE_64BIT
2761 || strcmp (mnemonic
, "movabs") != 0))
2764 /* Next, we find a template that matches the given insn,
2765 making sure the overlap of the given operands types is consistent
2766 with the template operand types. */
2768 if (!(t
= match_template ()))
2771 if (sse_check
!= sse_check_none
2772 && !i
.tm
.opcode_modifier
.noavx
2773 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2774 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2775 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2776 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2777 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2778 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2780 (sse_check
== sse_check_warning
2782 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2785 /* Zap movzx and movsx suffix. The suffix has been set from
2786 "word ptr" or "byte ptr" on the source operand in Intel syntax
2787 or extracted from mnemonic in AT&T syntax. But we'll use
2788 the destination register to choose the suffix for encoding. */
2789 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2791 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2792 there is no suffix, the default will be byte extension. */
2793 if (i
.reg_operands
!= 2
2796 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2801 if (i
.tm
.opcode_modifier
.fwait
)
2802 if (!add_prefix (FWAIT_OPCODE
))
2805 /* Check string instruction segment overrides. */
2806 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2808 if (!check_string ())
2810 i
.disp_operands
= 0;
2813 if (!process_suffix ())
2816 /* Update operand types. */
2817 for (j
= 0; j
< i
.operands
; j
++)
2818 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2820 /* Make still unresolved immediate matches conform to size of immediate
2821 given in i.suffix. */
2822 if (!finalize_imm ())
2825 if (i
.types
[0].bitfield
.imm1
)
2826 i
.imm_operands
= 0; /* kludge for shift insns. */
2828 /* We only need to check those implicit registers for instructions
2829 with 3 operands or less. */
2830 if (i
.operands
<= 3)
2831 for (j
= 0; j
< i
.operands
; j
++)
2832 if (i
.types
[j
].bitfield
.inoutportreg
2833 || i
.types
[j
].bitfield
.shiftcount
2834 || i
.types
[j
].bitfield
.acc
2835 || i
.types
[j
].bitfield
.floatacc
)
2838 /* ImmExt should be processed after SSE2AVX. */
2839 if (!i
.tm
.opcode_modifier
.sse2avx
2840 && i
.tm
.opcode_modifier
.immext
)
2843 /* For insns with operands there are more diddles to do to the opcode. */
2846 if (!process_operands ())
2849 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2851 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2852 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2855 if (i
.tm
.opcode_modifier
.vex
)
2856 build_vex_prefix (t
);
2858 /* Handle conversion of 'int $3' --> special int3 insn. */
2859 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2861 i
.tm
.base_opcode
= INT3_OPCODE
;
2865 if ((i
.tm
.opcode_modifier
.jump
2866 || i
.tm
.opcode_modifier
.jumpbyte
2867 || i
.tm
.opcode_modifier
.jumpdword
)
2868 && i
.op
[0].disps
->X_op
== O_constant
)
2870 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2871 the absolute address given by the constant. Since ix86 jumps and
2872 calls are pc relative, we need to generate a reloc. */
2873 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2874 i
.op
[0].disps
->X_op
= O_symbol
;
2877 if (i
.tm
.opcode_modifier
.rex64
)
2880 /* For 8 bit registers we need an empty rex prefix. Also if the
2881 instruction already has a prefix, we need to convert old
2882 registers to new ones. */
2884 if ((i
.types
[0].bitfield
.reg8
2885 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2886 || (i
.types
[1].bitfield
.reg8
2887 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2888 || ((i
.types
[0].bitfield
.reg8
2889 || i
.types
[1].bitfield
.reg8
)
2894 i
.rex
|= REX_OPCODE
;
2895 for (x
= 0; x
< 2; x
++)
2897 /* Look for 8 bit operand that uses old registers. */
2898 if (i
.types
[x
].bitfield
.reg8
2899 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2901 /* In case it is "hi" register, give up. */
2902 if (i
.op
[x
].regs
->reg_num
> 3)
2903 as_bad (_("can't encode register '%s%s' in an "
2904 "instruction requiring REX prefix."),
2905 register_prefix
, i
.op
[x
].regs
->reg_name
);
2907 /* Otherwise it is equivalent to the extended register.
2908 Since the encoding doesn't change this is merely
2909 cosmetic cleanup for debug output. */
2911 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2917 add_prefix (REX_OPCODE
| i
.rex
);
2919 /* We are ready to output the insn. */
2924 parse_insn (char *line
, char *mnemonic
)
2927 char *token_start
= l
;
2933 /* Non-zero if we found a prefix only acceptable with string insns. */
2934 const char *expecting_string_instruction
= NULL
;
2939 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2944 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2946 as_bad (_("no such instruction: `%s'"), token_start
);
2951 if (!is_space_char (*l
)
2952 && *l
!= END_OF_INSN
2954 || (*l
!= PREFIX_SEPARATOR
2957 as_bad (_("invalid character %s in mnemonic"),
2958 output_invalid (*l
));
2961 if (token_start
== l
)
2963 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2964 as_bad (_("expecting prefix; got nothing"));
2966 as_bad (_("expecting mnemonic; got nothing"));
2970 /* Look up instruction (or prefix) via hash table. */
2971 current_templates
= hash_find (op_hash
, mnemonic
);
2973 if (*l
!= END_OF_INSN
2974 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2975 && current_templates
2976 && current_templates
->start
->opcode_modifier
.isprefix
)
2978 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2980 as_bad ((flag_code
!= CODE_64BIT
2981 ? _("`%s' is only supported in 64-bit mode")
2982 : _("`%s' is not supported in 64-bit mode")),
2983 current_templates
->start
->name
);
2986 /* If we are in 16-bit mode, do not allow addr16 or data16.
2987 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2988 if ((current_templates
->start
->opcode_modifier
.size16
2989 || current_templates
->start
->opcode_modifier
.size32
)
2990 && flag_code
!= CODE_64BIT
2991 && (current_templates
->start
->opcode_modifier
.size32
2992 ^ (flag_code
== CODE_16BIT
)))
2994 as_bad (_("redundant %s prefix"),
2995 current_templates
->start
->name
);
2998 /* Add prefix, checking for repeated prefixes. */
2999 switch (add_prefix (current_templates
->start
->base_opcode
))
3004 expecting_string_instruction
= current_templates
->start
->name
;
3007 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3014 if (!current_templates
)
3016 /* Check if we should swap operand in encoding. */
3017 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3023 current_templates
= hash_find (op_hash
, mnemonic
);
3026 if (!current_templates
)
3029 /* See if we can get a match by trimming off a suffix. */
3032 case WORD_MNEM_SUFFIX
:
3033 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3034 i
.suffix
= SHORT_MNEM_SUFFIX
;
3036 case BYTE_MNEM_SUFFIX
:
3037 case QWORD_MNEM_SUFFIX
:
3038 i
.suffix
= mnem_p
[-1];
3040 current_templates
= hash_find (op_hash
, mnemonic
);
3042 case SHORT_MNEM_SUFFIX
:
3043 case LONG_MNEM_SUFFIX
:
3046 i
.suffix
= mnem_p
[-1];
3048 current_templates
= hash_find (op_hash
, mnemonic
);
3056 if (intel_float_operand (mnemonic
) == 1)
3057 i
.suffix
= SHORT_MNEM_SUFFIX
;
3059 i
.suffix
= LONG_MNEM_SUFFIX
;
3061 current_templates
= hash_find (op_hash
, mnemonic
);
3065 if (!current_templates
)
3067 as_bad (_("no such instruction: `%s'"), token_start
);
3072 if (current_templates
->start
->opcode_modifier
.jump
3073 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3075 /* Check for a branch hint. We allow ",pt" and ",pn" for
3076 predict taken and predict not taken respectively.
3077 I'm not sure that branch hints actually do anything on loop
3078 and jcxz insns (JumpByte) for current Pentium4 chips. They
3079 may work in the future and it doesn't hurt to accept them
3081 if (l
[0] == ',' && l
[1] == 'p')
3085 if (!add_prefix (DS_PREFIX_OPCODE
))
3089 else if (l
[2] == 'n')
3091 if (!add_prefix (CS_PREFIX_OPCODE
))
3097 /* Any other comma loses. */
3100 as_bad (_("invalid character %s in mnemonic"),
3101 output_invalid (*l
));
3105 /* Check if instruction is supported on specified architecture. */
3107 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3109 supported
|= cpu_flags_match (t
);
3110 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3114 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3116 as_bad (flag_code
== CODE_64BIT
3117 ? _("`%s' is not supported in 64-bit mode")
3118 : _("`%s' is only supported in 64-bit mode"),
3119 current_templates
->start
->name
);
3122 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3124 as_bad (_("`%s' is not supported on `%s%s'"),
3125 current_templates
->start
->name
,
3126 cpu_arch_name
? cpu_arch_name
: default_arch
,
3127 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3132 if (!cpu_arch_flags
.bitfield
.cpui386
3133 && (flag_code
!= CODE_16BIT
))
3135 as_warn (_("use .code16 to ensure correct addressing mode"));
3138 /* Check for rep/repne without a string instruction. */
3139 if (expecting_string_instruction
)
3141 static templates override
;
3143 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3144 if (t
->opcode_modifier
.isstring
)
3146 if (t
>= current_templates
->end
)
3148 as_bad (_("expecting string instruction after `%s'"),
3149 expecting_string_instruction
);
3152 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3153 if (!t
->opcode_modifier
.isstring
)
3156 current_templates
= &override
;
3163 parse_operands (char *l
, const char *mnemonic
)
3167 /* 1 if operand is pending after ','. */
3168 unsigned int expecting_operand
= 0;
3170 /* Non-zero if operand parens not balanced. */
3171 unsigned int paren_not_balanced
;
3173 while (*l
!= END_OF_INSN
)
3175 /* Skip optional white space before operand. */
3176 if (is_space_char (*l
))
3178 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3180 as_bad (_("invalid character %s before operand %d"),
3181 output_invalid (*l
),
3185 token_start
= l
; /* after white space */
3186 paren_not_balanced
= 0;
3187 while (paren_not_balanced
|| *l
!= ',')
3189 if (*l
== END_OF_INSN
)
3191 if (paren_not_balanced
)
3194 as_bad (_("unbalanced parenthesis in operand %d."),
3197 as_bad (_("unbalanced brackets in operand %d."),
3202 break; /* we are done */
3204 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3206 as_bad (_("invalid character %s in operand %d"),
3207 output_invalid (*l
),
3214 ++paren_not_balanced
;
3216 --paren_not_balanced
;
3221 ++paren_not_balanced
;
3223 --paren_not_balanced
;
3227 if (l
!= token_start
)
3228 { /* Yes, we've read in another operand. */
3229 unsigned int operand_ok
;
3230 this_operand
= i
.operands
++;
3231 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3232 if (i
.operands
> MAX_OPERANDS
)
3234 as_bad (_("spurious operands; (%d operands/instruction max)"),
3238 /* Now parse operand adding info to 'i' as we go along. */
3239 END_STRING_AND_SAVE (l
);
3243 i386_intel_operand (token_start
,
3244 intel_float_operand (mnemonic
));
3246 operand_ok
= i386_att_operand (token_start
);
3248 RESTORE_END_STRING (l
);
3254 if (expecting_operand
)
3256 expecting_operand_after_comma
:
3257 as_bad (_("expecting operand after ','; got nothing"));
3262 as_bad (_("expecting operand before ','; got nothing"));
3267 /* Now *l must be either ',' or END_OF_INSN. */
3270 if (*++l
== END_OF_INSN
)
3272 /* Just skip it, if it's \n complain. */
3273 goto expecting_operand_after_comma
;
3275 expecting_operand
= 1;
3282 swap_2_operands (int xchg1
, int xchg2
)
3284 union i386_op temp_op
;
3285 i386_operand_type temp_type
;
3286 enum bfd_reloc_code_real temp_reloc
;
3288 temp_type
= i
.types
[xchg2
];
3289 i
.types
[xchg2
] = i
.types
[xchg1
];
3290 i
.types
[xchg1
] = temp_type
;
3291 temp_op
= i
.op
[xchg2
];
3292 i
.op
[xchg2
] = i
.op
[xchg1
];
3293 i
.op
[xchg1
] = temp_op
;
3294 temp_reloc
= i
.reloc
[xchg2
];
3295 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3296 i
.reloc
[xchg1
] = temp_reloc
;
3300 swap_operands (void)
3306 swap_2_operands (1, i
.operands
- 2);
3309 swap_2_operands (0, i
.operands
- 1);
3315 if (i
.mem_operands
== 2)
3317 const seg_entry
*temp_seg
;
3318 temp_seg
= i
.seg
[0];
3319 i
.seg
[0] = i
.seg
[1];
3320 i
.seg
[1] = temp_seg
;
3324 /* Try to ensure constant immediates are represented in the smallest
3329 char guess_suffix
= 0;
3333 guess_suffix
= i
.suffix
;
3334 else if (i
.reg_operands
)
3336 /* Figure out a suffix from the last register operand specified.
3337 We can't do this properly yet, ie. excluding InOutPortReg,
3338 but the following works for instructions with immediates.
3339 In any case, we can't set i.suffix yet. */
3340 for (op
= i
.operands
; --op
>= 0;)
3341 if (i
.types
[op
].bitfield
.reg8
)
3343 guess_suffix
= BYTE_MNEM_SUFFIX
;
3346 else if (i
.types
[op
].bitfield
.reg16
)
3348 guess_suffix
= WORD_MNEM_SUFFIX
;
3351 else if (i
.types
[op
].bitfield
.reg32
)
3353 guess_suffix
= LONG_MNEM_SUFFIX
;
3356 else if (i
.types
[op
].bitfield
.reg64
)
3358 guess_suffix
= QWORD_MNEM_SUFFIX
;
3362 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3363 guess_suffix
= WORD_MNEM_SUFFIX
;
3365 for (op
= i
.operands
; --op
>= 0;)
3366 if (operand_type_check (i
.types
[op
], imm
))
3368 switch (i
.op
[op
].imms
->X_op
)
3371 /* If a suffix is given, this operand may be shortened. */
3372 switch (guess_suffix
)
3374 case LONG_MNEM_SUFFIX
:
3375 i
.types
[op
].bitfield
.imm32
= 1;
3376 i
.types
[op
].bitfield
.imm64
= 1;
3378 case WORD_MNEM_SUFFIX
:
3379 i
.types
[op
].bitfield
.imm16
= 1;
3380 i
.types
[op
].bitfield
.imm32
= 1;
3381 i
.types
[op
].bitfield
.imm32s
= 1;
3382 i
.types
[op
].bitfield
.imm64
= 1;
3384 case BYTE_MNEM_SUFFIX
:
3385 i
.types
[op
].bitfield
.imm8
= 1;
3386 i
.types
[op
].bitfield
.imm8s
= 1;
3387 i
.types
[op
].bitfield
.imm16
= 1;
3388 i
.types
[op
].bitfield
.imm32
= 1;
3389 i
.types
[op
].bitfield
.imm32s
= 1;
3390 i
.types
[op
].bitfield
.imm64
= 1;
3394 /* If this operand is at most 16 bits, convert it
3395 to a signed 16 bit number before trying to see
3396 whether it will fit in an even smaller size.
3397 This allows a 16-bit operand such as $0xffe0 to
3398 be recognised as within Imm8S range. */
3399 if ((i
.types
[op
].bitfield
.imm16
)
3400 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3402 i
.op
[op
].imms
->X_add_number
=
3403 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3405 if ((i
.types
[op
].bitfield
.imm32
)
3406 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3409 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3410 ^ ((offsetT
) 1 << 31))
3411 - ((offsetT
) 1 << 31));
3414 = operand_type_or (i
.types
[op
],
3415 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3417 /* We must avoid matching of Imm32 templates when 64bit
3418 only immediate is available. */
3419 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3420 i
.types
[op
].bitfield
.imm32
= 0;
3427 /* Symbols and expressions. */
3429 /* Convert symbolic operand to proper sizes for matching, but don't
3430 prevent matching a set of insns that only supports sizes other
3431 than those matching the insn suffix. */
3433 i386_operand_type mask
, allowed
;
3436 operand_type_set (&mask
, 0);
3437 operand_type_set (&allowed
, 0);
3439 for (t
= current_templates
->start
;
3440 t
< current_templates
->end
;
3442 allowed
= operand_type_or (allowed
,
3443 t
->operand_types
[op
]);
3444 switch (guess_suffix
)
3446 case QWORD_MNEM_SUFFIX
:
3447 mask
.bitfield
.imm64
= 1;
3448 mask
.bitfield
.imm32s
= 1;
3450 case LONG_MNEM_SUFFIX
:
3451 mask
.bitfield
.imm32
= 1;
3453 case WORD_MNEM_SUFFIX
:
3454 mask
.bitfield
.imm16
= 1;
3456 case BYTE_MNEM_SUFFIX
:
3457 mask
.bitfield
.imm8
= 1;
3462 allowed
= operand_type_and (mask
, allowed
);
3463 if (!operand_type_all_zero (&allowed
))
3464 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3471 /* Try to use the smallest displacement type too. */
3473 optimize_disp (void)
3477 for (op
= i
.operands
; --op
>= 0;)
3478 if (operand_type_check (i
.types
[op
], disp
))
3480 if (i
.op
[op
].disps
->X_op
== O_constant
)
3482 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3484 if (i
.types
[op
].bitfield
.disp16
3485 && (disp
& ~(offsetT
) 0xffff) == 0)
3487 /* If this operand is at most 16 bits, convert
3488 to a signed 16 bit number and don't use 64bit
3490 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3491 i
.types
[op
].bitfield
.disp64
= 0;
3493 if (i
.types
[op
].bitfield
.disp32
3494 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3496 /* If this operand is at most 32 bits, convert
3497 to a signed 32 bit number and don't use 64bit
3499 disp
&= (((offsetT
) 2 << 31) - 1);
3500 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3501 i
.types
[op
].bitfield
.disp64
= 0;
3503 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3505 i
.types
[op
].bitfield
.disp8
= 0;
3506 i
.types
[op
].bitfield
.disp16
= 0;
3507 i
.types
[op
].bitfield
.disp32
= 0;
3508 i
.types
[op
].bitfield
.disp32s
= 0;
3509 i
.types
[op
].bitfield
.disp64
= 0;
3513 else if (flag_code
== CODE_64BIT
)
3515 if (fits_in_signed_long (disp
))
3517 i
.types
[op
].bitfield
.disp64
= 0;
3518 i
.types
[op
].bitfield
.disp32s
= 1;
3520 if (fits_in_unsigned_long (disp
))
3521 i
.types
[op
].bitfield
.disp32
= 1;
3523 if ((i
.types
[op
].bitfield
.disp32
3524 || i
.types
[op
].bitfield
.disp32s
3525 || i
.types
[op
].bitfield
.disp16
)
3526 && fits_in_signed_byte (disp
))
3527 i
.types
[op
].bitfield
.disp8
= 1;
3529 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3530 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3532 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3533 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3534 i
.types
[op
].bitfield
.disp8
= 0;
3535 i
.types
[op
].bitfield
.disp16
= 0;
3536 i
.types
[op
].bitfield
.disp32
= 0;
3537 i
.types
[op
].bitfield
.disp32s
= 0;
3538 i
.types
[op
].bitfield
.disp64
= 0;
3541 /* We only support 64bit displacement on constants. */
3542 i
.types
[op
].bitfield
.disp64
= 0;
3546 static const template *
3547 match_template (void)
3549 /* Points to template once we've found it. */
3551 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3552 i386_operand_type overlap4
;
3553 unsigned int found_reverse_match
;
3554 i386_opcode_modifier suffix_check
;
3555 i386_operand_type operand_types
[MAX_OPERANDS
];
3556 int addr_prefix_disp
;
3558 unsigned int found_cpu_match
;
3559 unsigned int check_register
;
3561 #if MAX_OPERANDS != 5
3562 # error "MAX_OPERANDS must be 5."
3565 found_reverse_match
= 0;
3566 addr_prefix_disp
= -1;
3568 memset (&suffix_check
, 0, sizeof (suffix_check
));
3569 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3570 suffix_check
.no_bsuf
= 1;
3571 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3572 suffix_check
.no_wsuf
= 1;
3573 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3574 suffix_check
.no_ssuf
= 1;
3575 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3576 suffix_check
.no_lsuf
= 1;
3577 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3578 suffix_check
.no_qsuf
= 1;
3579 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3580 suffix_check
.no_ldsuf
= 1;
3582 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3584 addr_prefix_disp
= -1;
3586 /* Must have right number of operands. */
3587 if (i
.operands
!= t
->operands
)
3590 /* Check processor support. */
3591 found_cpu_match
= (cpu_flags_match (t
)
3592 == CPU_FLAGS_PERFECT_MATCH
);
3593 if (!found_cpu_match
)
3596 /* Check old gcc support. */
3597 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3600 /* Check AT&T mnemonic. */
3601 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3604 /* Check AT&T syntax Intel syntax. */
3605 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3606 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3609 /* Check the suffix, except for some instructions in intel mode. */
3610 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3611 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3612 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3613 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3614 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3615 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3616 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3619 if (!operand_size_match (t
))
3622 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3623 operand_types
[j
] = t
->operand_types
[j
];
3625 /* In general, don't allow 64-bit operands in 32-bit mode. */
3626 if (i
.suffix
== QWORD_MNEM_SUFFIX
3627 && flag_code
!= CODE_64BIT
3629 ? (!t
->opcode_modifier
.ignoresize
3630 && !intel_float_operand (t
->name
))
3631 : intel_float_operand (t
->name
) != 2)
3632 && ((!operand_types
[0].bitfield
.regmmx
3633 && !operand_types
[0].bitfield
.regxmm
3634 && !operand_types
[0].bitfield
.regymm
)
3635 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3636 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3637 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3638 && (t
->base_opcode
!= 0x0fc7
3639 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3642 /* In general, don't allow 32-bit operands on pre-386. */
3643 else if (i
.suffix
== LONG_MNEM_SUFFIX
3644 && !cpu_arch_flags
.bitfield
.cpui386
3646 ? (!t
->opcode_modifier
.ignoresize
3647 && !intel_float_operand (t
->name
))
3648 : intel_float_operand (t
->name
) != 2)
3649 && ((!operand_types
[0].bitfield
.regmmx
3650 && !operand_types
[0].bitfield
.regxmm
)
3651 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3652 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3655 /* Do not verify operands when there are none. */
3659 /* We've found a match; break out of loop. */
3663 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3664 into Disp32/Disp16/Disp32 operand. */
3665 if (i
.prefix
[ADDR_PREFIX
] != 0)
3667 /* There should be only one Disp operand. */
3671 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3673 if (operand_types
[j
].bitfield
.disp16
)
3675 addr_prefix_disp
= j
;
3676 operand_types
[j
].bitfield
.disp32
= 1;
3677 operand_types
[j
].bitfield
.disp16
= 0;
3683 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3685 if (operand_types
[j
].bitfield
.disp32
)
3687 addr_prefix_disp
= j
;
3688 operand_types
[j
].bitfield
.disp32
= 0;
3689 operand_types
[j
].bitfield
.disp16
= 1;
3695 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3697 if (operand_types
[j
].bitfield
.disp64
)
3699 addr_prefix_disp
= j
;
3700 operand_types
[j
].bitfield
.disp64
= 0;
3701 operand_types
[j
].bitfield
.disp32
= 1;
3709 /* We check register size only if size of operands can be
3710 encoded the canonical way. */
3711 check_register
= t
->opcode_modifier
.w
;
3712 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3713 switch (t
->operands
)
3716 if (!operand_type_match (overlap0
, i
.types
[0]))
3720 /* xchg %eax, %eax is a special case. It is an aliase for nop
3721 only in 32bit mode and we can use opcode 0x90. In 64bit
3722 mode, we can't use 0x90 for xchg %eax, %eax since it should
3723 zero-extend %eax to %rax. */
3724 if (flag_code
== CODE_64BIT
3725 && t
->base_opcode
== 0x90
3726 && operand_type_equal (&i
.types
[0], &acc32
)
3727 && operand_type_equal (&i
.types
[1], &acc32
))
3731 /* If we swap operand in encoding, we either match
3732 the next one or reverse direction of operands. */
3733 if (t
->opcode_modifier
.s
)
3735 else if (t
->opcode_modifier
.d
)
3740 /* If we swap operand in encoding, we match the next one. */
3741 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3745 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3746 if (!operand_type_match (overlap0
, i
.types
[0])
3747 || !operand_type_match (overlap1
, i
.types
[1])
3749 && !operand_type_register_match (overlap0
, i
.types
[0],
3751 overlap1
, i
.types
[1],
3754 /* Check if other direction is valid ... */
3755 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3759 /* Try reversing direction of operands. */
3760 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3761 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3762 if (!operand_type_match (overlap0
, i
.types
[0])
3763 || !operand_type_match (overlap1
, i
.types
[1])
3765 && !operand_type_register_match (overlap0
,
3772 /* Does not match either direction. */
3775 /* found_reverse_match holds which of D or FloatDR
3777 if (t
->opcode_modifier
.d
)
3778 found_reverse_match
= Opcode_D
;
3779 else if (t
->opcode_modifier
.floatd
)
3780 found_reverse_match
= Opcode_FloatD
;
3782 found_reverse_match
= 0;
3783 if (t
->opcode_modifier
.floatr
)
3784 found_reverse_match
|= Opcode_FloatR
;
3788 /* Found a forward 2 operand match here. */
3789 switch (t
->operands
)
3792 overlap4
= operand_type_and (i
.types
[4],
3795 overlap3
= operand_type_and (i
.types
[3],
3798 overlap2
= operand_type_and (i
.types
[2],
3803 switch (t
->operands
)
3806 if (!operand_type_match (overlap4
, i
.types
[4])
3807 || !operand_type_register_match (overlap3
,
3815 if (!operand_type_match (overlap3
, i
.types
[3])
3817 && !operand_type_register_match (overlap2
,
3825 /* Here we make use of the fact that there are no
3826 reverse match 3 operand instructions, and all 3
3827 operand instructions only need to be checked for
3828 register consistency between operands 2 and 3. */
3829 if (!operand_type_match (overlap2
, i
.types
[2])
3831 && !operand_type_register_match (overlap1
,
3841 /* Found either forward/reverse 2, 3 or 4 operand match here:
3842 slip through to break. */
3844 if (!found_cpu_match
)
3846 found_reverse_match
= 0;
3850 /* We've found a match; break out of loop. */
3854 if (t
== current_templates
->end
)
3856 /* We found no match. */
3858 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3859 current_templates
->start
->name
);
3861 as_bad (_("suffix or operands invalid for `%s'"),
3862 current_templates
->start
->name
);
3866 if (!quiet_warnings
)
3869 && (i
.types
[0].bitfield
.jumpabsolute
3870 != operand_types
[0].bitfield
.jumpabsolute
))
3872 as_warn (_("indirect %s without `*'"), t
->name
);
3875 if (t
->opcode_modifier
.isprefix
3876 && t
->opcode_modifier
.ignoresize
)
3878 /* Warn them that a data or address size prefix doesn't
3879 affect assembly of the next line of code. */
3880 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3884 /* Copy the template we found. */
3887 if (addr_prefix_disp
!= -1)
3888 i
.tm
.operand_types
[addr_prefix_disp
]
3889 = operand_types
[addr_prefix_disp
];
3891 if (found_reverse_match
)
3893 /* If we found a reverse match we must alter the opcode
3894 direction bit. found_reverse_match holds bits to change
3895 (different for int & float insns). */
3897 i
.tm
.base_opcode
^= found_reverse_match
;
3899 i
.tm
.operand_types
[0] = operand_types
[1];
3900 i
.tm
.operand_types
[1] = operand_types
[0];
3909 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3910 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3912 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3914 as_bad (_("`%s' operand %d must use `%ses' segment"),
3920 /* There's only ever one segment override allowed per instruction.
3921 This instruction possibly has a legal segment override on the
3922 second operand, so copy the segment to where non-string
3923 instructions store it, allowing common code. */
3924 i
.seg
[0] = i
.seg
[1];
3926 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3928 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3930 as_bad (_("`%s' operand %d must use `%ses' segment"),
3941 process_suffix (void)
3943 /* If matched instruction specifies an explicit instruction mnemonic
3945 if (i
.tm
.opcode_modifier
.size16
)
3946 i
.suffix
= WORD_MNEM_SUFFIX
;
3947 else if (i
.tm
.opcode_modifier
.size32
)
3948 i
.suffix
= LONG_MNEM_SUFFIX
;
3949 else if (i
.tm
.opcode_modifier
.size64
)
3950 i
.suffix
= QWORD_MNEM_SUFFIX
;
3951 else if (i
.reg_operands
)
3953 /* If there's no instruction mnemonic suffix we try to invent one
3954 based on register operands. */
3957 /* We take i.suffix from the last register operand specified,
3958 Destination register type is more significant than source
3959 register type. crc32 in SSE4.2 prefers source register
3961 if (i
.tm
.base_opcode
== 0xf20f38f1)
3963 if (i
.types
[0].bitfield
.reg16
)
3964 i
.suffix
= WORD_MNEM_SUFFIX
;
3965 else if (i
.types
[0].bitfield
.reg32
)
3966 i
.suffix
= LONG_MNEM_SUFFIX
;
3967 else if (i
.types
[0].bitfield
.reg64
)
3968 i
.suffix
= QWORD_MNEM_SUFFIX
;
3970 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3972 if (i
.types
[0].bitfield
.reg8
)
3973 i
.suffix
= BYTE_MNEM_SUFFIX
;
3980 if (i
.tm
.base_opcode
== 0xf20f38f1
3981 || i
.tm
.base_opcode
== 0xf20f38f0)
3983 /* We have to know the operand size for crc32. */
3984 as_bad (_("ambiguous memory operand size for `%s`"),
3989 for (op
= i
.operands
; --op
>= 0;)
3990 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3992 if (i
.types
[op
].bitfield
.reg8
)
3994 i
.suffix
= BYTE_MNEM_SUFFIX
;
3997 else if (i
.types
[op
].bitfield
.reg16
)
3999 i
.suffix
= WORD_MNEM_SUFFIX
;
4002 else if (i
.types
[op
].bitfield
.reg32
)
4004 i
.suffix
= LONG_MNEM_SUFFIX
;
4007 else if (i
.types
[op
].bitfield
.reg64
)
4009 i
.suffix
= QWORD_MNEM_SUFFIX
;
4015 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4017 if (!check_byte_reg ())
4020 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4022 if (!check_long_reg ())
4025 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4028 && i
.tm
.opcode_modifier
.ignoresize
4029 && i
.tm
.opcode_modifier
.no_qsuf
)
4031 else if (!check_qword_reg ())
4034 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4036 if (!check_word_reg ())
4039 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4040 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4042 /* Skip if the instruction has x/y suffix. match_template
4043 should check if it is a valid suffix. */
4045 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4046 /* Do nothing if the instruction is going to ignore the prefix. */
4051 else if (i
.tm
.opcode_modifier
.defaultsize
4053 /* exclude fldenv/frstor/fsave/fstenv */
4054 && i
.tm
.opcode_modifier
.no_ssuf
)
4056 i
.suffix
= stackop_size
;
4058 else if (intel_syntax
4060 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4061 || i
.tm
.opcode_modifier
.jumpbyte
4062 || i
.tm
.opcode_modifier
.jumpintersegment
4063 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4064 && i
.tm
.extension_opcode
<= 3)))
4069 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4071 i
.suffix
= QWORD_MNEM_SUFFIX
;
4075 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4076 i
.suffix
= LONG_MNEM_SUFFIX
;
4079 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4080 i
.suffix
= WORD_MNEM_SUFFIX
;
4089 if (i
.tm
.opcode_modifier
.w
)
4091 as_bad (_("no instruction mnemonic suffix given and "
4092 "no register operands; can't size instruction"));
4098 unsigned int suffixes
;
4100 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4101 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4103 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4105 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4107 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4109 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4112 /* There are more than suffix matches. */
4113 if (i
.tm
.opcode_modifier
.w
4114 || ((suffixes
& (suffixes
- 1))
4115 && !i
.tm
.opcode_modifier
.defaultsize
4116 && !i
.tm
.opcode_modifier
.ignoresize
))
4118 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4124 /* Change the opcode based on the operand size given by i.suffix;
4125 We don't need to change things for byte insns. */
4128 && i
.suffix
!= BYTE_MNEM_SUFFIX
4129 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4130 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4132 /* It's not a byte, select word/dword operation. */
4133 if (i
.tm
.opcode_modifier
.w
)
4135 if (i
.tm
.opcode_modifier
.shortform
)
4136 i
.tm
.base_opcode
|= 8;
4138 i
.tm
.base_opcode
|= 1;
4141 /* Now select between word & dword operations via the operand
4142 size prefix, except for instructions that will ignore this
4144 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4146 /* The address size override prefix changes the size of the
4148 if ((flag_code
== CODE_32BIT
4149 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4150 || (flag_code
!= CODE_32BIT
4151 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4152 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4155 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4156 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4157 && !i
.tm
.opcode_modifier
.ignoresize
4158 && !i
.tm
.opcode_modifier
.floatmf
4159 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4160 || (flag_code
== CODE_64BIT
4161 && i
.tm
.opcode_modifier
.jumpbyte
)))
4163 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4165 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4166 prefix
= ADDR_PREFIX_OPCODE
;
4168 if (!add_prefix (prefix
))
4172 /* Set mode64 for an operand. */
4173 if (i
.suffix
== QWORD_MNEM_SUFFIX
4174 && flag_code
== CODE_64BIT
4175 && !i
.tm
.opcode_modifier
.norex64
)
4177 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4178 need rex64. cmpxchg8b is also a special case. */
4179 if (! (i
.operands
== 2
4180 && i
.tm
.base_opcode
== 0x90
4181 && i
.tm
.extension_opcode
== None
4182 && operand_type_equal (&i
.types
[0], &acc64
)
4183 && operand_type_equal (&i
.types
[1], &acc64
))
4184 && ! (i
.operands
== 1
4185 && i
.tm
.base_opcode
== 0xfc7
4186 && i
.tm
.extension_opcode
== 1
4187 && !operand_type_check (i
.types
[0], reg
)
4188 && operand_type_check (i
.types
[0], anymem
)))
4192 /* Size floating point instruction. */
4193 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4194 if (i
.tm
.opcode_modifier
.floatmf
)
4195 i
.tm
.base_opcode
^= 4;
4202 check_byte_reg (void)
4206 for (op
= i
.operands
; --op
>= 0;)
4208 /* If this is an eight bit register, it's OK. If it's the 16 or
4209 32 bit version of an eight bit register, we will just use the
4210 low portion, and that's OK too. */
4211 if (i
.types
[op
].bitfield
.reg8
)
4214 /* Don't generate this warning if not needed. */
4215 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4218 /* crc32 doesn't generate this warning. */
4219 if (i
.tm
.base_opcode
== 0xf20f38f0)
4222 if ((i
.types
[op
].bitfield
.reg16
4223 || i
.types
[op
].bitfield
.reg32
4224 || i
.types
[op
].bitfield
.reg64
)
4225 && i
.op
[op
].regs
->reg_num
< 4)
4227 /* Prohibit these changes in the 64bit mode, since the
4228 lowering is more complicated. */
4229 if (flag_code
== CODE_64BIT
4230 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4232 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4233 register_prefix
, i
.op
[op
].regs
->reg_name
,
4237 #if REGISTER_WARNINGS
4239 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4240 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4242 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4243 ? REGNAM_AL
- REGNAM_AX
4244 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4246 i
.op
[op
].regs
->reg_name
,
4251 /* Any other register is bad. */
4252 if (i
.types
[op
].bitfield
.reg16
4253 || i
.types
[op
].bitfield
.reg32
4254 || i
.types
[op
].bitfield
.reg64
4255 || i
.types
[op
].bitfield
.regmmx
4256 || i
.types
[op
].bitfield
.regxmm
4257 || i
.types
[op
].bitfield
.regymm
4258 || i
.types
[op
].bitfield
.sreg2
4259 || i
.types
[op
].bitfield
.sreg3
4260 || i
.types
[op
].bitfield
.control
4261 || i
.types
[op
].bitfield
.debug
4262 || i
.types
[op
].bitfield
.test
4263 || i
.types
[op
].bitfield
.floatreg
4264 || i
.types
[op
].bitfield
.floatacc
)
4266 as_bad (_("`%s%s' not allowed with `%s%c'"),
4268 i
.op
[op
].regs
->reg_name
,
4278 check_long_reg (void)
4282 for (op
= i
.operands
; --op
>= 0;)
4283 /* Reject eight bit registers, except where the template requires
4284 them. (eg. movzb) */
4285 if (i
.types
[op
].bitfield
.reg8
4286 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4287 || i
.tm
.operand_types
[op
].bitfield
.reg32
4288 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4290 as_bad (_("`%s%s' not allowed with `%s%c'"),
4292 i
.op
[op
].regs
->reg_name
,
4297 /* Warn if the e prefix on a general reg is missing. */
4298 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4299 && i
.types
[op
].bitfield
.reg16
4300 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4301 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4303 /* Prohibit these changes in the 64bit mode, since the
4304 lowering is more complicated. */
4305 if (flag_code
== CODE_64BIT
)
4307 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4308 register_prefix
, i
.op
[op
].regs
->reg_name
,
4312 #if REGISTER_WARNINGS
4314 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4316 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4318 i
.op
[op
].regs
->reg_name
,
4322 /* Warn if the r prefix on a general reg is missing. */
4323 else if (i
.types
[op
].bitfield
.reg64
4324 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4325 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4328 && i
.tm
.opcode_modifier
.toqword
4329 && !i
.types
[0].bitfield
.regxmm
)
4331 /* Convert to QWORD. We want REX byte. */
4332 i
.suffix
= QWORD_MNEM_SUFFIX
;
4336 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4337 register_prefix
, i
.op
[op
].regs
->reg_name
,
4346 check_qword_reg (void)
4350 for (op
= i
.operands
; --op
>= 0; )
4351 /* Reject eight bit registers, except where the template requires
4352 them. (eg. movzb) */
4353 if (i
.types
[op
].bitfield
.reg8
4354 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4355 || i
.tm
.operand_types
[op
].bitfield
.reg32
4356 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4358 as_bad (_("`%s%s' not allowed with `%s%c'"),
4360 i
.op
[op
].regs
->reg_name
,
4365 /* Warn if the e prefix on a general reg is missing. */
4366 else if ((i
.types
[op
].bitfield
.reg16
4367 || i
.types
[op
].bitfield
.reg32
)
4368 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4369 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4371 /* Prohibit these changes in the 64bit mode, since the
4372 lowering is more complicated. */
4374 && i
.tm
.opcode_modifier
.todword
4375 && !i
.types
[0].bitfield
.regxmm
)
4377 /* Convert to DWORD. We don't want REX byte. */
4378 i
.suffix
= LONG_MNEM_SUFFIX
;
4382 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4383 register_prefix
, i
.op
[op
].regs
->reg_name
,
4392 check_word_reg (void)
4395 for (op
= i
.operands
; --op
>= 0;)
4396 /* Reject eight bit registers, except where the template requires
4397 them. (eg. movzb) */
4398 if (i
.types
[op
].bitfield
.reg8
4399 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4400 || i
.tm
.operand_types
[op
].bitfield
.reg32
4401 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4403 as_bad (_("`%s%s' not allowed with `%s%c'"),
4405 i
.op
[op
].regs
->reg_name
,
4410 /* Warn if the e prefix on a general reg is present. */
4411 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4412 && i
.types
[op
].bitfield
.reg32
4413 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4414 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4416 /* Prohibit these changes in the 64bit mode, since the
4417 lowering is more complicated. */
4418 if (flag_code
== CODE_64BIT
)
4420 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4421 register_prefix
, i
.op
[op
].regs
->reg_name
,
4426 #if REGISTER_WARNINGS
4427 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4429 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4431 i
.op
[op
].regs
->reg_name
,
4439 update_imm (unsigned int j
)
4441 i386_operand_type overlap
= i
.types
[j
];
4442 if ((overlap
.bitfield
.imm8
4443 || overlap
.bitfield
.imm8s
4444 || overlap
.bitfield
.imm16
4445 || overlap
.bitfield
.imm32
4446 || overlap
.bitfield
.imm32s
4447 || overlap
.bitfield
.imm64
)
4448 && !operand_type_equal (&overlap
, &imm8
)
4449 && !operand_type_equal (&overlap
, &imm8s
)
4450 && !operand_type_equal (&overlap
, &imm16
)
4451 && !operand_type_equal (&overlap
, &imm32
)
4452 && !operand_type_equal (&overlap
, &imm32s
)
4453 && !operand_type_equal (&overlap
, &imm64
))
4457 i386_operand_type temp
;
4459 operand_type_set (&temp
, 0);
4460 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4462 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4463 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4465 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4466 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4467 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4469 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4470 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4473 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4476 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4477 || operand_type_equal (&overlap
, &imm16_32
)
4478 || operand_type_equal (&overlap
, &imm16_32s
))
4480 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4485 if (!operand_type_equal (&overlap
, &imm8
)
4486 && !operand_type_equal (&overlap
, &imm8s
)
4487 && !operand_type_equal (&overlap
, &imm16
)
4488 && !operand_type_equal (&overlap
, &imm32
)
4489 && !operand_type_equal (&overlap
, &imm32s
)
4490 && !operand_type_equal (&overlap
, &imm64
))
4492 as_bad (_("no instruction mnemonic suffix given; "
4493 "can't determine immediate size"));
4497 i
.types
[j
] = overlap
;
4507 /* Update the first 2 immediate operands. */
4508 n
= i
.operands
> 2 ? 2 : i
.operands
;
4511 for (j
= 0; j
< n
; j
++)
4512 if (update_imm (j
) == 0)
4515 /* The 3rd operand can't be immediate operand. */
4516 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4523 bad_implicit_operand (int xmm
)
4525 const char *reg
= xmm
? "xmm0" : "ymm0";
4527 as_bad (_("the last operand of `%s' must be `%s%s'"),
4528 i
.tm
.name
, register_prefix
, reg
);
4530 as_bad (_("the first operand of `%s' must be `%s%s'"),
4531 i
.tm
.name
, register_prefix
, reg
);
4536 process_operands (void)
4538 /* Default segment register this instruction will use for memory
4539 accesses. 0 means unknown. This is only for optimizing out
4540 unnecessary segment overrides. */
4541 const seg_entry
*default_seg
= 0;
4543 if (i
.tm
.opcode_modifier
.sse2avx
4544 && (i
.tm
.opcode_modifier
.vexnds
4545 || i
.tm
.opcode_modifier
.vexndd
))
4547 unsigned int dup
= i
.operands
;
4548 unsigned int dest
= dup
- 1;
4551 /* The destination must be an xmm register. */
4552 gas_assert (i
.reg_operands
4553 && MAX_OPERANDS
> dup
4554 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4556 if (i
.tm
.opcode_modifier
.firstxmm0
)
4558 /* The first operand is implicit and must be xmm0. */
4559 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4560 if (i
.op
[0].regs
->reg_num
!= 0)
4561 return bad_implicit_operand (1);
4563 if (i
.tm
.opcode_modifier
.vex3sources
)
4565 /* Keep xmm0 for instructions with VEX prefix and 3
4571 /* We remove the first xmm0 and keep the number of
4572 operands unchanged, which in fact duplicates the
4574 for (j
= 1; j
< i
.operands
; j
++)
4576 i
.op
[j
- 1] = i
.op
[j
];
4577 i
.types
[j
- 1] = i
.types
[j
];
4578 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4582 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4584 gas_assert ((MAX_OPERANDS
- 1) > dup
4585 && i
.tm
.opcode_modifier
.vex3sources
);
4587 /* Add the implicit xmm0 for instructions with VEX prefix
4589 for (j
= i
.operands
; j
> 0; j
--)
4591 i
.op
[j
] = i
.op
[j
- 1];
4592 i
.types
[j
] = i
.types
[j
- 1];
4593 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4596 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4597 i
.types
[0] = regxmm
;
4598 i
.tm
.operand_types
[0] = regxmm
;
4601 i
.reg_operands
+= 2;
4606 i
.op
[dup
] = i
.op
[dest
];
4607 i
.types
[dup
] = i
.types
[dest
];
4608 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4617 i
.op
[dup
] = i
.op
[dest
];
4618 i
.types
[dup
] = i
.types
[dest
];
4619 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4622 if (i
.tm
.opcode_modifier
.immext
)
4625 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4629 /* The first operand is implicit and must be xmm0/ymm0. */
4630 gas_assert (i
.reg_operands
4631 && (operand_type_equal (&i
.types
[0], ®xmm
)
4632 || operand_type_equal (&i
.types
[0], ®ymm
)));
4633 if (i
.op
[0].regs
->reg_num
!= 0)
4634 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4636 for (j
= 1; j
< i
.operands
; j
++)
4638 i
.op
[j
- 1] = i
.op
[j
];
4639 i
.types
[j
- 1] = i
.types
[j
];
4641 /* We need to adjust fields in i.tm since they are used by
4642 build_modrm_byte. */
4643 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4650 else if (i
.tm
.opcode_modifier
.regkludge
)
4652 /* The imul $imm, %reg instruction is converted into
4653 imul $imm, %reg, %reg, and the clr %reg instruction
4654 is converted into xor %reg, %reg. */
4656 unsigned int first_reg_op
;
4658 if (operand_type_check (i
.types
[0], reg
))
4662 /* Pretend we saw the extra register operand. */
4663 gas_assert (i
.reg_operands
== 1
4664 && i
.op
[first_reg_op
+ 1].regs
== 0);
4665 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4666 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4671 if (i
.tm
.opcode_modifier
.shortform
)
4673 if (i
.types
[0].bitfield
.sreg2
4674 || i
.types
[0].bitfield
.sreg3
)
4676 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4677 && i
.op
[0].regs
->reg_num
== 1)
4679 as_bad (_("you can't `pop %scs'"), register_prefix
);
4682 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4683 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4688 /* The register or float register operand is in operand
4692 if (i
.types
[0].bitfield
.floatreg
4693 || operand_type_check (i
.types
[0], reg
))
4697 /* Register goes in low 3 bits of opcode. */
4698 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4699 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4701 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4703 /* Warn about some common errors, but press on regardless.
4704 The first case can be generated by gcc (<= 2.8.1). */
4705 if (i
.operands
== 2)
4707 /* Reversed arguments on faddp, fsubp, etc. */
4708 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4709 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4710 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4714 /* Extraneous `l' suffix on fp insn. */
4715 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4716 register_prefix
, i
.op
[0].regs
->reg_name
);
4721 else if (i
.tm
.opcode_modifier
.modrm
)
4723 /* The opcode is completed (modulo i.tm.extension_opcode which
4724 must be put into the modrm byte). Now, we make the modrm and
4725 index base bytes based on all the info we've collected. */
4727 default_seg
= build_modrm_byte ();
4729 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4733 else if (i
.tm
.opcode_modifier
.isstring
)
4735 /* For the string instructions that allow a segment override
4736 on one of their operands, the default segment is ds. */
4740 if (i
.tm
.base_opcode
== 0x8d /* lea */
4743 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4745 /* If a segment was explicitly specified, and the specified segment
4746 is not the default, use an opcode prefix to select it. If we
4747 never figured out what the default segment is, then default_seg
4748 will be zero at this point, and the specified segment prefix will
4750 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4752 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4758 static const seg_entry
*
4759 build_modrm_byte (void)
4761 const seg_entry
*default_seg
= 0;
4762 unsigned int source
, dest
;
4765 /* The first operand of instructions with VEX prefix and 3 sources
4766 must be VEX_Imm4. */
4767 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4770 unsigned int nds
, reg
;
4772 if (i
.tm
.opcode_modifier
.veximmext
4773 && i
.tm
.opcode_modifier
.immext
)
4775 dest
= i
.operands
- 2;
4776 gas_assert (dest
== 3);
4779 dest
= i
.operands
- 1;
4782 /* This instruction must have 4 register operands
4783 or 3 register operands plus 1 memory operand.
4784 It must have VexNDS and VexImmExt. */
4785 gas_assert ((i
.reg_operands
== 4
4786 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4787 && i
.tm
.opcode_modifier
.vexnds
4788 && i
.tm
.opcode_modifier
.veximmext
4789 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4790 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4792 /* Generate an 8bit immediate operand to encode the register
4794 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
4795 i
.op
[i
.operands
].imms
= exp
;
4796 i
.types
[i
.operands
] = imm8
;
4798 /* If VexW1 is set, the first operand is the source and
4799 the second operand is encoded in the immediate operand. */
4800 if (i
.tm
.opcode_modifier
.vexw1
)
4810 /* FMA4 swaps REG and NDS. */
4811 if (i
.tm
.cpu_flags
.bitfield
.cpufma4
)
4818 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4819 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4821 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4822 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4824 exp
->X_op
= O_constant
;
4826 = ((i
.op
[reg
].regs
->reg_num
4827 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4828 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4833 /* i.reg_operands MUST be the number of real register operands;
4834 implicit registers do not count. If there are 3 register
4835 operands, it must be a instruction with VexNDS. For a
4836 instruction with VexNDD, the destination register is encoded
4837 in VEX prefix. If there are 4 register operands, it must be
4838 a instruction with VEX prefix and 3 sources. */
4839 if (i
.mem_operands
== 0
4840 && ((i
.reg_operands
== 2
4841 && !i
.tm
.opcode_modifier
.vexndd
)
4842 || (i
.reg_operands
== 3
4843 && i
.tm
.opcode_modifier
.vexnds
)
4844 || (i
.reg_operands
== 4 && vex_3_sources
)))
4852 /* When there are 3 operands, one of them may be immediate,
4853 which may be the first or the last operand. Otherwise,
4854 the first operand must be shift count register (cl) or it
4855 is an instruction with VexNDS. */
4856 gas_assert (i
.imm_operands
== 1
4857 || (i
.imm_operands
== 0
4858 && (i
.tm
.opcode_modifier
.vexnds
4859 || i
.types
[0].bitfield
.shiftcount
)));
4860 if (operand_type_check (i
.types
[0], imm
)
4861 || i
.types
[0].bitfield
.shiftcount
)
4867 /* When there are 4 operands, the first two must be 8bit
4868 immediate operands. The source operand will be the 3rd
4871 For instructions with VexNDS, if the first operand
4872 an imm8, the source operand is the 2nd one. If the last
4873 operand is imm8, the source operand is the first one. */
4874 gas_assert ((i
.imm_operands
== 2
4875 && i
.types
[0].bitfield
.imm8
4876 && i
.types
[1].bitfield
.imm8
)
4877 || (i
.tm
.opcode_modifier
.vexnds
4878 && i
.imm_operands
== 1
4879 && (i
.types
[0].bitfield
.imm8
4880 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4881 if (i
.tm
.opcode_modifier
.vexnds
)
4883 if (i
.types
[0].bitfield
.imm8
)
4901 if (i
.tm
.opcode_modifier
.vexnds
)
4903 /* For instructions with VexNDS, the register-only
4904 source operand must be XMM or YMM register. It is
4905 encoded in VEX prefix. We need to clear RegMem bit
4906 before calling operand_type_equal. */
4907 i386_operand_type op
= i
.tm
.operand_types
[dest
];
4908 op
.bitfield
.regmem
= 0;
4909 if ((dest
+ 1) >= i
.operands
4910 || (!operand_type_equal (&op
, ®xmm
)
4911 && !operand_type_equal (&op
, ®ymm
)))
4913 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
4919 /* One of the register operands will be encoded in the i.tm.reg
4920 field, the other in the combined i.tm.mode and i.tm.regmem
4921 fields. If no form of this instruction supports a memory
4922 destination operand, then we assume the source operand may
4923 sometimes be a memory operand and so we need to store the
4924 destination in the i.rm.reg field. */
4925 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4926 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4928 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4929 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4930 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4932 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4937 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4938 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4939 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4941 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4944 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4946 if (!i
.types
[0].bitfield
.control
4947 && !i
.types
[1].bitfield
.control
)
4949 i
.rex
&= ~(REX_R
| REX_B
);
4950 add_prefix (LOCK_PREFIX_OPCODE
);
4954 { /* If it's not 2 reg operands... */
4959 unsigned int fake_zero_displacement
= 0;
4962 for (op
= 0; op
< i
.operands
; op
++)
4963 if (operand_type_check (i
.types
[op
], anymem
))
4965 gas_assert (op
< i
.operands
);
4969 if (i
.base_reg
== 0)
4972 if (!i
.disp_operands
)
4973 fake_zero_displacement
= 1;
4974 if (i
.index_reg
== 0)
4976 /* Operand is just <disp> */
4977 if (flag_code
== CODE_64BIT
)
4979 /* 64bit mode overwrites the 32bit absolute
4980 addressing by RIP relative addressing and
4981 absolute addressing is encoded by one of the
4982 redundant SIB forms. */
4983 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4984 i
.sib
.base
= NO_BASE_REGISTER
;
4985 i
.sib
.index
= NO_INDEX_REGISTER
;
4986 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
4987 ? disp32s
: disp32
);
4989 else if ((flag_code
== CODE_16BIT
)
4990 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4992 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
4993 i
.types
[op
] = disp16
;
4997 i
.rm
.regmem
= NO_BASE_REGISTER
;
4998 i
.types
[op
] = disp32
;
5001 else /* !i.base_reg && i.index_reg */
5003 if (i
.index_reg
->reg_num
== RegEiz
5004 || i
.index_reg
->reg_num
== RegRiz
)
5005 i
.sib
.index
= NO_INDEX_REGISTER
;
5007 i
.sib
.index
= i
.index_reg
->reg_num
;
5008 i
.sib
.base
= NO_BASE_REGISTER
;
5009 i
.sib
.scale
= i
.log2_scale_factor
;
5010 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5011 i
.types
[op
].bitfield
.disp8
= 0;
5012 i
.types
[op
].bitfield
.disp16
= 0;
5013 i
.types
[op
].bitfield
.disp64
= 0;
5014 if (flag_code
!= CODE_64BIT
)
5016 /* Must be 32 bit */
5017 i
.types
[op
].bitfield
.disp32
= 1;
5018 i
.types
[op
].bitfield
.disp32s
= 0;
5022 i
.types
[op
].bitfield
.disp32
= 0;
5023 i
.types
[op
].bitfield
.disp32s
= 1;
5025 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5029 /* RIP addressing for 64bit mode. */
5030 else if (i
.base_reg
->reg_num
== RegRip
||
5031 i
.base_reg
->reg_num
== RegEip
)
5033 i
.rm
.regmem
= NO_BASE_REGISTER
;
5034 i
.types
[op
].bitfield
.disp8
= 0;
5035 i
.types
[op
].bitfield
.disp16
= 0;
5036 i
.types
[op
].bitfield
.disp32
= 0;
5037 i
.types
[op
].bitfield
.disp32s
= 1;
5038 i
.types
[op
].bitfield
.disp64
= 0;
5039 i
.flags
[op
] |= Operand_PCrel
;
5040 if (! i
.disp_operands
)
5041 fake_zero_displacement
= 1;
5043 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5045 switch (i
.base_reg
->reg_num
)
5048 if (i
.index_reg
== 0)
5050 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5051 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5055 if (i
.index_reg
== 0)
5058 if (operand_type_check (i
.types
[op
], disp
) == 0)
5060 /* fake (%bp) into 0(%bp) */
5061 i
.types
[op
].bitfield
.disp8
= 1;
5062 fake_zero_displacement
= 1;
5065 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5066 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5068 default: /* (%si) -> 4 or (%di) -> 5 */
5069 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5071 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5073 else /* i.base_reg and 32/64 bit mode */
5075 if (flag_code
== CODE_64BIT
5076 && operand_type_check (i
.types
[op
], disp
))
5078 i386_operand_type temp
;
5079 operand_type_set (&temp
, 0);
5080 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5082 if (i
.prefix
[ADDR_PREFIX
] == 0)
5083 i
.types
[op
].bitfield
.disp32s
= 1;
5085 i
.types
[op
].bitfield
.disp32
= 1;
5088 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5089 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5091 i
.sib
.base
= i
.base_reg
->reg_num
;
5092 /* x86-64 ignores REX prefix bit here to avoid decoder
5094 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5097 if (i
.disp_operands
== 0)
5099 fake_zero_displacement
= 1;
5100 i
.types
[op
].bitfield
.disp8
= 1;
5103 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5107 i
.sib
.scale
= i
.log2_scale_factor
;
5108 if (i
.index_reg
== 0)
5110 /* <disp>(%esp) becomes two byte modrm with no index
5111 register. We've already stored the code for esp
5112 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5113 Any base register besides %esp will not use the
5114 extra modrm byte. */
5115 i
.sib
.index
= NO_INDEX_REGISTER
;
5119 if (i
.index_reg
->reg_num
== RegEiz
5120 || i
.index_reg
->reg_num
== RegRiz
)
5121 i
.sib
.index
= NO_INDEX_REGISTER
;
5123 i
.sib
.index
= i
.index_reg
->reg_num
;
5124 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5125 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5130 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5131 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5134 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5137 if (fake_zero_displacement
)
5139 /* Fakes a zero displacement assuming that i.types[op]
5140 holds the correct displacement size. */
5143 gas_assert (i
.op
[op
].disps
== 0);
5144 exp
= &disp_expressions
[i
.disp_operands
++];
5145 i
.op
[op
].disps
= exp
;
5146 exp
->X_op
= O_constant
;
5147 exp
->X_add_number
= 0;
5148 exp
->X_add_symbol
= (symbolS
*) 0;
5149 exp
->X_op_symbol
= (symbolS
*) 0;
5157 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5158 (if any) based on i.tm.extension_opcode. Again, we must be
5159 careful to make sure that segment/control/debug/test/MMX
5160 registers are coded into the i.rm.reg field. */
5164 unsigned int vex_reg
= ~0;
5166 for (op
= 0; op
< i
.operands
; op
++)
5167 if (i
.types
[op
].bitfield
.reg8
5168 || i
.types
[op
].bitfield
.reg16
5169 || i
.types
[op
].bitfield
.reg32
5170 || i
.types
[op
].bitfield
.reg64
5171 || i
.types
[op
].bitfield
.regmmx
5172 || i
.types
[op
].bitfield
.regxmm
5173 || i
.types
[op
].bitfield
.regymm
5174 || i
.types
[op
].bitfield
.sreg2
5175 || i
.types
[op
].bitfield
.sreg3
5176 || i
.types
[op
].bitfield
.control
5177 || i
.types
[op
].bitfield
.debug
5178 || i
.types
[op
].bitfield
.test
)
5183 else if (i
.tm
.opcode_modifier
.vexnds
)
5185 /* For instructions with VexNDS, the register-only
5186 source operand is encoded in VEX prefix. */
5187 gas_assert (mem
!= (unsigned int) ~0);
5192 gas_assert (op
< i
.operands
);
5197 gas_assert (vex_reg
< i
.operands
);
5200 else if (i
.tm
.opcode_modifier
.vexndd
)
5202 /* For instructions with VexNDD, there should be
5203 no memory operand and the register destination
5204 is encoded in VEX prefix. */
5205 gas_assert (i
.mem_operands
== 0
5206 && (op
+ 2) == i
.operands
);
5210 gas_assert (op
< i
.operands
);
5212 if (vex_reg
!= (unsigned int) ~0)
5214 gas_assert (i
.reg_operands
== 2);
5216 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5218 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5221 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5224 /* If there is an extension opcode to put here, the
5225 register number must be put into the regmem field. */
5226 if (i
.tm
.extension_opcode
!= None
)
5228 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5229 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5234 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5235 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5239 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5240 must set it to 3 to indicate this is a register operand
5241 in the regmem field. */
5242 if (!i
.mem_operands
)
5246 /* Fill in i.rm.reg field with extension opcode (if any). */
5247 if (i
.tm
.extension_opcode
!= None
)
5248 i
.rm
.reg
= i
.tm
.extension_opcode
;
5254 output_branch (void)
5259 relax_substateT subtype
;
5264 if (flag_code
== CODE_16BIT
)
5268 if (i
.prefix
[DATA_PREFIX
] != 0)
5274 /* Pentium4 branch hints. */
5275 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5276 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5281 if (i
.prefix
[REX_PREFIX
] != 0)
5287 if (i
.prefixes
!= 0 && !intel_syntax
)
5288 as_warn (_("skipping prefixes on this instruction"));
5290 /* It's always a symbol; End frag & setup for relax.
5291 Make sure there is enough room in this frag for the largest
5292 instruction we may generate in md_convert_frag. This is 2
5293 bytes for the opcode and room for the prefix and largest
5295 frag_grow (prefix
+ 2 + 4);
5296 /* Prefix and 1 opcode byte go in fr_fix. */
5297 p
= frag_more (prefix
+ 1);
5298 if (i
.prefix
[DATA_PREFIX
] != 0)
5299 *p
++ = DATA_PREFIX_OPCODE
;
5300 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5301 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5302 *p
++ = i
.prefix
[SEG_PREFIX
];
5303 if (i
.prefix
[REX_PREFIX
] != 0)
5304 *p
++ = i
.prefix
[REX_PREFIX
];
5305 *p
= i
.tm
.base_opcode
;
5307 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5308 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5309 else if (cpu_arch_flags
.bitfield
.cpui386
)
5310 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5312 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5315 sym
= i
.op
[0].disps
->X_add_symbol
;
5316 off
= i
.op
[0].disps
->X_add_number
;
5318 if (i
.op
[0].disps
->X_op
!= O_constant
5319 && i
.op
[0].disps
->X_op
!= O_symbol
)
5321 /* Handle complex expressions. */
5322 sym
= make_expr_symbol (i
.op
[0].disps
);
5326 /* 1 possible extra opcode + 4 byte displacement go in var part.
5327 Pass reloc in fr_var. */
5328 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5338 if (i
.tm
.opcode_modifier
.jumpbyte
)
5340 /* This is a loop or jecxz type instruction. */
5342 if (i
.prefix
[ADDR_PREFIX
] != 0)
5344 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5347 /* Pentium4 branch hints. */
5348 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5349 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5351 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5360 if (flag_code
== CODE_16BIT
)
5363 if (i
.prefix
[DATA_PREFIX
] != 0)
5365 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5375 if (i
.prefix
[REX_PREFIX
] != 0)
5377 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5381 if (i
.prefixes
!= 0 && !intel_syntax
)
5382 as_warn (_("skipping prefixes on this instruction"));
5384 p
= frag_more (1 + size
);
5385 *p
++ = i
.tm
.base_opcode
;
5387 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5388 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5390 /* All jumps handled here are signed, but don't use a signed limit
5391 check for 32 and 16 bit jumps as we want to allow wrap around at
5392 4G and 64k respectively. */
5394 fixP
->fx_signed
= 1;
5398 output_interseg_jump (void)
5406 if (flag_code
== CODE_16BIT
)
5410 if (i
.prefix
[DATA_PREFIX
] != 0)
5416 if (i
.prefix
[REX_PREFIX
] != 0)
5426 if (i
.prefixes
!= 0 && !intel_syntax
)
5427 as_warn (_("skipping prefixes on this instruction"));
5429 /* 1 opcode; 2 segment; offset */
5430 p
= frag_more (prefix
+ 1 + 2 + size
);
5432 if (i
.prefix
[DATA_PREFIX
] != 0)
5433 *p
++ = DATA_PREFIX_OPCODE
;
5435 if (i
.prefix
[REX_PREFIX
] != 0)
5436 *p
++ = i
.prefix
[REX_PREFIX
];
5438 *p
++ = i
.tm
.base_opcode
;
5439 if (i
.op
[1].imms
->X_op
== O_constant
)
5441 offsetT n
= i
.op
[1].imms
->X_add_number
;
5444 && !fits_in_unsigned_word (n
)
5445 && !fits_in_signed_word (n
))
5447 as_bad (_("16-bit jump out of range"));
5450 md_number_to_chars (p
, n
, size
);
5453 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5454 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5455 if (i
.op
[0].imms
->X_op
!= O_constant
)
5456 as_bad (_("can't handle non absolute segment in `%s'"),
5458 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5464 fragS
*insn_start_frag
;
5465 offsetT insn_start_off
;
5467 /* Tie dwarf2 debug info to the address at the start of the insn.
5468 We can't do this after the insn has been output as the current
5469 frag may have been closed off. eg. by frag_var. */
5470 dwarf2_emit_insn (0);
5472 insn_start_frag
= frag_now
;
5473 insn_start_off
= frag_now_fix ();
5476 if (i
.tm
.opcode_modifier
.jump
)
5478 else if (i
.tm
.opcode_modifier
.jumpbyte
5479 || i
.tm
.opcode_modifier
.jumpdword
)
5481 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5482 output_interseg_jump ();
5485 /* Output normal instructions here. */
5489 unsigned int prefix
;
5491 /* Since the VEX prefix contains the implicit prefix, we don't
5492 need the explicit prefix. */
5493 if (!i
.tm
.opcode_modifier
.vex
)
5495 switch (i
.tm
.opcode_length
)
5498 if (i
.tm
.base_opcode
& 0xff000000)
5500 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5505 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5507 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5508 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5511 if (prefix
!= REPE_PREFIX_OPCODE
5512 || (i
.prefix
[LOCKREP_PREFIX
]
5513 != REPE_PREFIX_OPCODE
))
5514 add_prefix (prefix
);
5517 add_prefix (prefix
);
5526 /* The prefix bytes. */
5527 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5529 FRAG_APPEND_1_CHAR (*q
);
5532 if (i
.tm
.opcode_modifier
.vex
)
5534 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5539 /* REX byte is encoded in VEX prefix. */
5543 FRAG_APPEND_1_CHAR (*q
);
5546 /* There should be no other prefixes for instructions
5551 /* Now the VEX prefix. */
5552 p
= frag_more (i
.vex
.length
);
5553 for (j
= 0; j
< i
.vex
.length
; j
++)
5554 p
[j
] = i
.vex
.bytes
[j
];
5557 /* Now the opcode; be careful about word order here! */
5558 if (i
.tm
.opcode_length
== 1)
5560 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5564 switch (i
.tm
.opcode_length
)
5568 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5578 /* Put out high byte first: can't use md_number_to_chars! */
5579 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5580 *p
= i
.tm
.base_opcode
& 0xff;
5583 /* Now the modrm byte and sib byte (if present). */
5584 if (i
.tm
.opcode_modifier
.modrm
)
5586 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5589 /* If i.rm.regmem == ESP (4)
5590 && i.rm.mode != (Register mode)
5592 ==> need second modrm byte. */
5593 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5595 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5596 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5598 | i
.sib
.scale
<< 6));
5601 if (i
.disp_operands
)
5602 output_disp (insn_start_frag
, insn_start_off
);
5605 output_imm (insn_start_frag
, insn_start_off
);
5611 pi ("" /*line*/, &i
);
5613 #endif /* DEBUG386 */
5616 /* Return the size of the displacement operand N. */
5619 disp_size (unsigned int n
)
5622 if (i
.types
[n
].bitfield
.disp64
)
5624 else if (i
.types
[n
].bitfield
.disp8
)
5626 else if (i
.types
[n
].bitfield
.disp16
)
5631 /* Return the size of the immediate operand N. */
5634 imm_size (unsigned int n
)
5637 if (i
.types
[n
].bitfield
.imm64
)
5639 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5641 else if (i
.types
[n
].bitfield
.imm16
)
5647 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5652 for (n
= 0; n
< i
.operands
; n
++)
5654 if (operand_type_check (i
.types
[n
], disp
))
5656 if (i
.op
[n
].disps
->X_op
== O_constant
)
5658 int size
= disp_size (n
);
5661 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5663 p
= frag_more (size
);
5664 md_number_to_chars (p
, val
, size
);
5668 enum bfd_reloc_code_real reloc_type
;
5669 int size
= disp_size (n
);
5670 int sign
= i
.types
[n
].bitfield
.disp32s
;
5671 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5673 /* We can't have 8 bit displacement here. */
5674 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5676 /* The PC relative address is computed relative
5677 to the instruction boundary, so in case immediate
5678 fields follows, we need to adjust the value. */
5679 if (pcrel
&& i
.imm_operands
)
5684 for (n1
= 0; n1
< i
.operands
; n1
++)
5685 if (operand_type_check (i
.types
[n1
], imm
))
5687 /* Only one immediate is allowed for PC
5688 relative address. */
5689 gas_assert (sz
== 0);
5691 i
.op
[n
].disps
->X_add_number
-= sz
;
5693 /* We should find the immediate. */
5694 gas_assert (sz
!= 0);
5697 p
= frag_more (size
);
5698 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5700 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5701 && (((reloc_type
== BFD_RELOC_32
5702 || reloc_type
== BFD_RELOC_X86_64_32S
5703 || (reloc_type
== BFD_RELOC_64
5705 && (i
.op
[n
].disps
->X_op
== O_symbol
5706 || (i
.op
[n
].disps
->X_op
== O_add
5707 && ((symbol_get_value_expression
5708 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5710 || reloc_type
== BFD_RELOC_32_PCREL
))
5714 if (insn_start_frag
== frag_now
)
5715 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5720 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5721 for (fr
= insn_start_frag
->fr_next
;
5722 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5724 add
+= p
- frag_now
->fr_literal
;
5729 reloc_type
= BFD_RELOC_386_GOTPC
;
5730 i
.op
[n
].imms
->X_add_number
+= add
;
5732 else if (reloc_type
== BFD_RELOC_64
)
5733 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5735 /* Don't do the adjustment for x86-64, as there
5736 the pcrel addressing is relative to the _next_
5737 insn, and that is taken care of in other code. */
5738 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5740 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5741 i
.op
[n
].disps
, pcrel
, reloc_type
);
5748 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5753 for (n
= 0; n
< i
.operands
; n
++)
5755 if (operand_type_check (i
.types
[n
], imm
))
5757 if (i
.op
[n
].imms
->X_op
== O_constant
)
5759 int size
= imm_size (n
);
5762 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5764 p
= frag_more (size
);
5765 md_number_to_chars (p
, val
, size
);
5769 /* Not absolute_section.
5770 Need a 32-bit fixup (don't support 8bit
5771 non-absolute imms). Try to support other
5773 enum bfd_reloc_code_real reloc_type
;
5774 int size
= imm_size (n
);
5777 if (i
.types
[n
].bitfield
.imm32s
5778 && (i
.suffix
== QWORD_MNEM_SUFFIX
5779 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5784 p
= frag_more (size
);
5785 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5787 /* This is tough to explain. We end up with this one if we
5788 * have operands that look like
5789 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5790 * obtain the absolute address of the GOT, and it is strongly
5791 * preferable from a performance point of view to avoid using
5792 * a runtime relocation for this. The actual sequence of
5793 * instructions often look something like:
5798 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5800 * The call and pop essentially return the absolute address
5801 * of the label .L66 and store it in %ebx. The linker itself
5802 * will ultimately change the first operand of the addl so
5803 * that %ebx points to the GOT, but to keep things simple, the
5804 * .o file must have this operand set so that it generates not
5805 * the absolute address of .L66, but the absolute address of
5806 * itself. This allows the linker itself simply treat a GOTPC
5807 * relocation as asking for a pcrel offset to the GOT to be
5808 * added in, and the addend of the relocation is stored in the
5809 * operand field for the instruction itself.
5811 * Our job here is to fix the operand so that it would add
5812 * the correct offset so that %ebx would point to itself. The
5813 * thing that is tricky is that .-.L66 will point to the
5814 * beginning of the instruction, so we need to further modify
5815 * the operand so that it will point to itself. There are
5816 * other cases where you have something like:
5818 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5820 * and here no correction would be required. Internally in
5821 * the assembler we treat operands of this form as not being
5822 * pcrel since the '.' is explicitly mentioned, and I wonder
5823 * whether it would simplify matters to do it this way. Who
5824 * knows. In earlier versions of the PIC patches, the
5825 * pcrel_adjust field was used to store the correction, but
5826 * since the expression is not pcrel, I felt it would be
5827 * confusing to do it this way. */
5829 if ((reloc_type
== BFD_RELOC_32
5830 || reloc_type
== BFD_RELOC_X86_64_32S
5831 || reloc_type
== BFD_RELOC_64
)
5833 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5834 && (i
.op
[n
].imms
->X_op
== O_symbol
5835 || (i
.op
[n
].imms
->X_op
== O_add
5836 && ((symbol_get_value_expression
5837 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5842 if (insn_start_frag
== frag_now
)
5843 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5848 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5849 for (fr
= insn_start_frag
->fr_next
;
5850 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5852 add
+= p
- frag_now
->fr_literal
;
5856 reloc_type
= BFD_RELOC_386_GOTPC
;
5858 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5860 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5861 i
.op
[n
].imms
->X_add_number
+= add
;
5863 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5864 i
.op
[n
].imms
, 0, reloc_type
);
5870 /* x86_cons_fix_new is called via the expression parsing code when a
5871 reloc is needed. We use this hook to get the correct .got reloc. */
5872 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5873 static int cons_sign
= -1;
5876 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5879 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5881 got_reloc
= NO_RELOC
;
5884 if (exp
->X_op
== O_secrel
)
5886 exp
->X_op
= O_symbol
;
5887 r
= BFD_RELOC_32_SECREL
;
5891 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5894 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5895 # define lex_got(reloc, adjust, types) NULL
5897 /* Parse operands of the form
5898 <symbol>@GOTOFF+<nnn>
5899 and similar .plt or .got references.
5901 If we find one, set up the correct relocation in RELOC and copy the
5902 input string, minus the `@GOTOFF' into a malloc'd buffer for
5903 parsing by the calling routine. Return this buffer, and if ADJUST
5904 is non-null set it to the length of the string we removed from the
5905 input line. Otherwise return NULL. */
5907 lex_got (enum bfd_reloc_code_real
*reloc
,
5909 i386_operand_type
*types
)
5911 /* Some of the relocations depend on the size of what field is to
5912 be relocated. But in our callers i386_immediate and i386_displacement
5913 we don't yet know the operand size (this will be set by insn
5914 matching). Hence we record the word32 relocation here,
5915 and adjust the reloc according to the real size in reloc(). */
5916 static const struct {
5918 const enum bfd_reloc_code_real rel
[2];
5919 const i386_operand_type types64
;
5922 BFD_RELOC_X86_64_PLTOFF64
},
5923 OPERAND_TYPE_IMM64
},
5924 { "PLT", { BFD_RELOC_386_PLT32
,
5925 BFD_RELOC_X86_64_PLT32
},
5926 OPERAND_TYPE_IMM32_32S_DISP32
},
5928 BFD_RELOC_X86_64_GOTPLT64
},
5929 OPERAND_TYPE_IMM64_DISP64
},
5930 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
5931 BFD_RELOC_X86_64_GOTOFF64
},
5932 OPERAND_TYPE_IMM64_DISP64
},
5934 BFD_RELOC_X86_64_GOTPCREL
},
5935 OPERAND_TYPE_IMM32_32S_DISP32
},
5936 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
5937 BFD_RELOC_X86_64_TLSGD
},
5938 OPERAND_TYPE_IMM32_32S_DISP32
},
5939 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
5941 OPERAND_TYPE_NONE
},
5943 BFD_RELOC_X86_64_TLSLD
},
5944 OPERAND_TYPE_IMM32_32S_DISP32
},
5945 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5946 BFD_RELOC_X86_64_GOTTPOFF
},
5947 OPERAND_TYPE_IMM32_32S_DISP32
},
5948 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5949 BFD_RELOC_X86_64_TPOFF32
},
5950 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5951 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5953 OPERAND_TYPE_NONE
},
5954 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5955 BFD_RELOC_X86_64_DTPOFF32
},
5957 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5958 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
5960 OPERAND_TYPE_NONE
},
5961 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
5963 OPERAND_TYPE_NONE
},
5964 { "GOT", { BFD_RELOC_386_GOT32
,
5965 BFD_RELOC_X86_64_GOT32
},
5966 OPERAND_TYPE_IMM32_32S_64_DISP32
},
5967 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
5968 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
5969 OPERAND_TYPE_IMM32_32S_DISP32
},
5970 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
5971 BFD_RELOC_X86_64_TLSDESC_CALL
},
5972 OPERAND_TYPE_IMM32_32S_DISP32
},
5980 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
5981 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
5984 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
5988 len
= strlen (gotrel
[j
].str
);
5989 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
5991 if (gotrel
[j
].rel
[object_64bit
] != 0)
5994 char *tmpbuf
, *past_reloc
;
5996 *reloc
= gotrel
[j
].rel
[object_64bit
];
6002 if (flag_code
!= CODE_64BIT
)
6004 types
->bitfield
.imm32
= 1;
6005 types
->bitfield
.disp32
= 1;
6008 *types
= gotrel
[j
].types64
;
6011 if (GOT_symbol
== NULL
)
6012 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6014 /* The length of the first part of our input line. */
6015 first
= cp
- input_line_pointer
;
6017 /* The second part goes from after the reloc token until
6018 (and including) an end_of_line char or comma. */
6019 past_reloc
= cp
+ 1 + len
;
6021 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6023 second
= cp
+ 1 - past_reloc
;
6025 /* Allocate and copy string. The trailing NUL shouldn't
6026 be necessary, but be safe. */
6027 tmpbuf
= xmalloc (first
+ second
+ 2);
6028 memcpy (tmpbuf
, input_line_pointer
, first
);
6029 if (second
!= 0 && *past_reloc
!= ' ')
6030 /* Replace the relocation token with ' ', so that
6031 errors like foo@GOTOFF1 will be detected. */
6032 tmpbuf
[first
++] = ' ';
6033 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6034 tmpbuf
[first
+ second
] = '\0';
6038 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6039 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6044 /* Might be a symbol version string. Don't as_bad here. */
6049 x86_cons (expressionS
*exp
, int size
)
6051 intel_syntax
= -intel_syntax
;
6053 if (size
== 4 || (object_64bit
&& size
== 8))
6055 /* Handle @GOTOFF and the like in an expression. */
6057 char *gotfree_input_line
;
6060 save
= input_line_pointer
;
6061 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6062 if (gotfree_input_line
)
6063 input_line_pointer
= gotfree_input_line
;
6067 if (gotfree_input_line
)
6069 /* expression () has merrily parsed up to the end of line,
6070 or a comma - in the wrong buffer. Transfer how far
6071 input_line_pointer has moved to the right buffer. */
6072 input_line_pointer
= (save
6073 + (input_line_pointer
- gotfree_input_line
)
6075 free (gotfree_input_line
);
6076 if (exp
->X_op
== O_constant
6077 || exp
->X_op
== O_absent
6078 || exp
->X_op
== O_illegal
6079 || exp
->X_op
== O_register
6080 || exp
->X_op
== O_big
)
6082 char c
= *input_line_pointer
;
6083 *input_line_pointer
= 0;
6084 as_bad (_("missing or invalid expression `%s'"), save
);
6085 *input_line_pointer
= c
;
6092 intel_syntax
= -intel_syntax
;
6095 i386_intel_simplify (exp
);
6099 static void signed_cons (int size
)
6101 if (flag_code
== CODE_64BIT
)
6109 pe_directive_secrel (dummy
)
6110 int dummy ATTRIBUTE_UNUSED
;
6117 if (exp
.X_op
== O_symbol
)
6118 exp
.X_op
= O_secrel
;
6120 emit_expr (&exp
, 4);
6122 while (*input_line_pointer
++ == ',');
6124 input_line_pointer
--;
6125 demand_empty_rest_of_line ();
6130 i386_immediate (char *imm_start
)
6132 char *save_input_line_pointer
;
6133 char *gotfree_input_line
;
6136 i386_operand_type types
;
6138 operand_type_set (&types
, ~0);
6140 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6142 as_bad (_("at most %d immediate operands are allowed"),
6143 MAX_IMMEDIATE_OPERANDS
);
6147 exp
= &im_expressions
[i
.imm_operands
++];
6148 i
.op
[this_operand
].imms
= exp
;
6150 if (is_space_char (*imm_start
))
6153 save_input_line_pointer
= input_line_pointer
;
6154 input_line_pointer
= imm_start
;
6156 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6157 if (gotfree_input_line
)
6158 input_line_pointer
= gotfree_input_line
;
6160 exp_seg
= expression (exp
);
6163 if (*input_line_pointer
)
6164 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6166 input_line_pointer
= save_input_line_pointer
;
6167 if (gotfree_input_line
)
6169 free (gotfree_input_line
);
6171 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6172 exp
->X_op
= O_illegal
;
6175 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6179 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6180 i386_operand_type types
, const char *imm_start
)
6182 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6184 as_bad (_("missing or invalid immediate expression `%s'"),
6188 else if (exp
->X_op
== O_constant
)
6190 /* Size it properly later. */
6191 i
.types
[this_operand
].bitfield
.imm64
= 1;
6192 /* If BFD64, sign extend val. */
6193 if (!use_rela_relocations
6194 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6196 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6198 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6199 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6200 && exp_seg
!= absolute_section
6201 && exp_seg
!= text_section
6202 && exp_seg
!= data_section
6203 && exp_seg
!= bss_section
6204 && exp_seg
!= undefined_section
6205 && !bfd_is_com_section (exp_seg
))
6207 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6211 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6213 as_bad (_("illegal immediate register operand %s"), imm_start
);
6218 /* This is an address. The size of the address will be
6219 determined later, depending on destination register,
6220 suffix, or the default for the section. */
6221 i
.types
[this_operand
].bitfield
.imm8
= 1;
6222 i
.types
[this_operand
].bitfield
.imm16
= 1;
6223 i
.types
[this_operand
].bitfield
.imm32
= 1;
6224 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6225 i
.types
[this_operand
].bitfield
.imm64
= 1;
6226 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6234 i386_scale (char *scale
)
6237 char *save
= input_line_pointer
;
6239 input_line_pointer
= scale
;
6240 val
= get_absolute_expression ();
6245 i
.log2_scale_factor
= 0;
6248 i
.log2_scale_factor
= 1;
6251 i
.log2_scale_factor
= 2;
6254 i
.log2_scale_factor
= 3;
6258 char sep
= *input_line_pointer
;
6260 *input_line_pointer
= '\0';
6261 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6263 *input_line_pointer
= sep
;
6264 input_line_pointer
= save
;
6268 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6270 as_warn (_("scale factor of %d without an index register"),
6271 1 << i
.log2_scale_factor
);
6272 i
.log2_scale_factor
= 0;
6274 scale
= input_line_pointer
;
6275 input_line_pointer
= save
;
6280 i386_displacement (char *disp_start
, char *disp_end
)
6284 char *save_input_line_pointer
;
6285 char *gotfree_input_line
;
6287 i386_operand_type bigdisp
, types
= anydisp
;
6290 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6292 as_bad (_("at most %d displacement operands are allowed"),
6293 MAX_MEMORY_OPERANDS
);
6297 operand_type_set (&bigdisp
, 0);
6298 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6299 || (!current_templates
->start
->opcode_modifier
.jump
6300 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6302 bigdisp
.bitfield
.disp32
= 1;
6303 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6304 if (flag_code
== CODE_64BIT
)
6308 bigdisp
.bitfield
.disp32s
= 1;
6309 bigdisp
.bitfield
.disp64
= 1;
6312 else if ((flag_code
== CODE_16BIT
) ^ override
)
6314 bigdisp
.bitfield
.disp32
= 0;
6315 bigdisp
.bitfield
.disp16
= 1;
6320 /* For PC-relative branches, the width of the displacement
6321 is dependent upon data size, not address size. */
6322 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6323 if (flag_code
== CODE_64BIT
)
6325 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6326 bigdisp
.bitfield
.disp16
= 1;
6329 bigdisp
.bitfield
.disp32
= 1;
6330 bigdisp
.bitfield
.disp32s
= 1;
6336 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6338 : LONG_MNEM_SUFFIX
));
6339 bigdisp
.bitfield
.disp32
= 1;
6340 if ((flag_code
== CODE_16BIT
) ^ override
)
6342 bigdisp
.bitfield
.disp32
= 0;
6343 bigdisp
.bitfield
.disp16
= 1;
6347 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6350 exp
= &disp_expressions
[i
.disp_operands
];
6351 i
.op
[this_operand
].disps
= exp
;
6353 save_input_line_pointer
= input_line_pointer
;
6354 input_line_pointer
= disp_start
;
6355 END_STRING_AND_SAVE (disp_end
);
6357 #ifndef GCC_ASM_O_HACK
6358 #define GCC_ASM_O_HACK 0
6361 END_STRING_AND_SAVE (disp_end
+ 1);
6362 if (i
.types
[this_operand
].bitfield
.baseIndex
6363 && displacement_string_end
[-1] == '+')
6365 /* This hack is to avoid a warning when using the "o"
6366 constraint within gcc asm statements.
6369 #define _set_tssldt_desc(n,addr,limit,type) \
6370 __asm__ __volatile__ ( \
6372 "movw %w1,2+%0\n\t" \
6374 "movb %b1,4+%0\n\t" \
6375 "movb %4,5+%0\n\t" \
6376 "movb $0,6+%0\n\t" \
6377 "movb %h1,7+%0\n\t" \
6379 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6381 This works great except that the output assembler ends
6382 up looking a bit weird if it turns out that there is
6383 no offset. You end up producing code that looks like:
6396 So here we provide the missing zero. */
6398 *displacement_string_end
= '0';
6401 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6402 if (gotfree_input_line
)
6403 input_line_pointer
= gotfree_input_line
;
6405 exp_seg
= expression (exp
);
6408 if (*input_line_pointer
)
6409 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6411 RESTORE_END_STRING (disp_end
+ 1);
6413 input_line_pointer
= save_input_line_pointer
;
6414 if (gotfree_input_line
)
6416 free (gotfree_input_line
);
6418 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6419 exp
->X_op
= O_illegal
;
6422 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6424 RESTORE_END_STRING (disp_end
);
6430 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6431 i386_operand_type types
, const char *disp_start
)
6433 i386_operand_type bigdisp
;
6436 /* We do this to make sure that the section symbol is in
6437 the symbol table. We will ultimately change the relocation
6438 to be relative to the beginning of the section. */
6439 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6440 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6441 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6443 if (exp
->X_op
!= O_symbol
)
6446 if (S_IS_LOCAL (exp
->X_add_symbol
)
6447 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6448 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6449 exp
->X_op
= O_subtract
;
6450 exp
->X_op_symbol
= GOT_symbol
;
6451 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6452 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6453 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6454 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6456 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6459 else if (exp
->X_op
== O_absent
6460 || exp
->X_op
== O_illegal
6461 || exp
->X_op
== O_big
)
6464 as_bad (_("missing or invalid displacement expression `%s'"),
6469 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6470 else if (exp
->X_op
!= O_constant
6471 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6472 && exp_seg
!= absolute_section
6473 && exp_seg
!= text_section
6474 && exp_seg
!= data_section
6475 && exp_seg
!= bss_section
6476 && exp_seg
!= undefined_section
6477 && !bfd_is_com_section (exp_seg
))
6479 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6484 /* Check if this is a displacement only operand. */
6485 bigdisp
= i
.types
[this_operand
];
6486 bigdisp
.bitfield
.disp8
= 0;
6487 bigdisp
.bitfield
.disp16
= 0;
6488 bigdisp
.bitfield
.disp32
= 0;
6489 bigdisp
.bitfield
.disp32s
= 0;
6490 bigdisp
.bitfield
.disp64
= 0;
6491 if (operand_type_all_zero (&bigdisp
))
6492 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6498 /* Make sure the memory operand we've been dealt is valid.
6499 Return 1 on success, 0 on a failure. */
6502 i386_index_check (const char *operand_string
)
6505 const char *kind
= "base/index";
6506 #if INFER_ADDR_PREFIX
6512 if (current_templates
->start
->opcode_modifier
.isstring
6513 && !current_templates
->start
->opcode_modifier
.immext
6514 && (current_templates
->end
[-1].opcode_modifier
.isstring
6517 /* Memory operands of string insns are special in that they only allow
6518 a single register (rDI, rSI, or rBX) as their memory address. */
6519 unsigned int expected
;
6521 kind
= "string address";
6523 if (current_templates
->start
->opcode_modifier
.w
)
6525 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6527 if (!type
.bitfield
.baseindex
6528 || ((!i
.mem_operands
!= !intel_syntax
)
6529 && current_templates
->end
[-1].operand_types
[1]
6530 .bitfield
.baseindex
))
6531 type
= current_templates
->end
[-1].operand_types
[1];
6532 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6535 expected
= 3 /* rBX */;
6537 if (!i
.base_reg
|| i
.index_reg
6538 || operand_type_check (i
.types
[this_operand
], disp
))
6540 else if (!(flag_code
== CODE_64BIT
6541 ? i
.prefix
[ADDR_PREFIX
]
6542 ? i
.base_reg
->reg_type
.bitfield
.reg32
6543 : i
.base_reg
->reg_type
.bitfield
.reg64
6544 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6545 ? i
.base_reg
->reg_type
.bitfield
.reg32
6546 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6548 else if (i
.base_reg
->reg_num
!= expected
)
6555 for (j
= 0; j
< i386_regtab_size
; ++j
)
6556 if ((flag_code
== CODE_64BIT
6557 ? i
.prefix
[ADDR_PREFIX
]
6558 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6559 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6560 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6561 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6562 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6563 && i386_regtab
[j
].reg_num
== expected
)
6565 gas_assert (j
< i386_regtab_size
);
6566 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6568 intel_syntax
? '[' : '(',
6570 i386_regtab
[j
].reg_name
,
6571 intel_syntax
? ']' : ')');
6575 else if (flag_code
== CODE_64BIT
)
6578 && ((i
.prefix
[ADDR_PREFIX
] == 0
6579 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6580 || (i
.prefix
[ADDR_PREFIX
]
6581 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6583 || i
.base_reg
->reg_num
!=
6584 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6586 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6587 || (i
.prefix
[ADDR_PREFIX
] == 0
6588 && i
.index_reg
->reg_num
!= RegRiz
6589 && !i
.index_reg
->reg_type
.bitfield
.reg64
6591 || (i
.prefix
[ADDR_PREFIX
]
6592 && i
.index_reg
->reg_num
!= RegEiz
6593 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6598 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6602 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6603 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6605 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6606 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6608 && i
.base_reg
->reg_num
< 6
6609 && i
.index_reg
->reg_num
>= 6
6610 && i
.log2_scale_factor
== 0))))
6617 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6619 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6620 && i
.index_reg
->reg_num
!= RegEiz
)
6621 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6627 #if INFER_ADDR_PREFIX
6628 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6630 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6632 /* Change the size of any displacement too. At most one of
6633 Disp16 or Disp32 is set.
6634 FIXME. There doesn't seem to be any real need for separate
6635 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6636 Removing them would probably clean up the code quite a lot. */
6637 if (flag_code
!= CODE_64BIT
6638 && (i
.types
[this_operand
].bitfield
.disp16
6639 || i
.types
[this_operand
].bitfield
.disp32
))
6640 i
.types
[this_operand
]
6641 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6646 as_bad (_("`%s' is not a valid %s expression"),
6651 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6653 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6654 ? flag_code
== CODE_32BIT
6663 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6667 i386_att_operand (char *operand_string
)
6671 char *op_string
= operand_string
;
6673 if (is_space_char (*op_string
))
6676 /* We check for an absolute prefix (differentiating,
6677 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6678 if (*op_string
== ABSOLUTE_PREFIX
)
6681 if (is_space_char (*op_string
))
6683 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6686 /* Check if operand is a register. */
6687 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6689 i386_operand_type temp
;
6691 /* Check for a segment override by searching for ':' after a
6692 segment register. */
6694 if (is_space_char (*op_string
))
6696 if (*op_string
== ':'
6697 && (r
->reg_type
.bitfield
.sreg2
6698 || r
->reg_type
.bitfield
.sreg3
))
6703 i
.seg
[i
.mem_operands
] = &es
;
6706 i
.seg
[i
.mem_operands
] = &cs
;
6709 i
.seg
[i
.mem_operands
] = &ss
;
6712 i
.seg
[i
.mem_operands
] = &ds
;
6715 i
.seg
[i
.mem_operands
] = &fs
;
6718 i
.seg
[i
.mem_operands
] = &gs
;
6722 /* Skip the ':' and whitespace. */
6724 if (is_space_char (*op_string
))
6727 if (!is_digit_char (*op_string
)
6728 && !is_identifier_char (*op_string
)
6729 && *op_string
!= '('
6730 && *op_string
!= ABSOLUTE_PREFIX
)
6732 as_bad (_("bad memory operand `%s'"), op_string
);
6735 /* Handle case of %es:*foo. */
6736 if (*op_string
== ABSOLUTE_PREFIX
)
6739 if (is_space_char (*op_string
))
6741 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6743 goto do_memory_reference
;
6747 as_bad (_("junk `%s' after register"), op_string
);
6751 temp
.bitfield
.baseindex
= 0;
6752 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6754 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6755 i
.op
[this_operand
].regs
= r
;
6758 else if (*op_string
== REGISTER_PREFIX
)
6760 as_bad (_("bad register name `%s'"), op_string
);
6763 else if (*op_string
== IMMEDIATE_PREFIX
)
6766 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6768 as_bad (_("immediate operand illegal with absolute jump"));
6771 if (!i386_immediate (op_string
))
6774 else if (is_digit_char (*op_string
)
6775 || is_identifier_char (*op_string
)
6776 || *op_string
== '(')
6778 /* This is a memory reference of some sort. */
6781 /* Start and end of displacement string expression (if found). */
6782 char *displacement_string_start
;
6783 char *displacement_string_end
;
6785 do_memory_reference
:
6786 if ((i
.mem_operands
== 1
6787 && !current_templates
->start
->opcode_modifier
.isstring
)
6788 || i
.mem_operands
== 2)
6790 as_bad (_("too many memory references for `%s'"),
6791 current_templates
->start
->name
);
6795 /* Check for base index form. We detect the base index form by
6796 looking for an ')' at the end of the operand, searching
6797 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6799 base_string
= op_string
+ strlen (op_string
);
6802 if (is_space_char (*base_string
))
6805 /* If we only have a displacement, set-up for it to be parsed later. */
6806 displacement_string_start
= op_string
;
6807 displacement_string_end
= base_string
+ 1;
6809 if (*base_string
== ')')
6812 unsigned int parens_balanced
= 1;
6813 /* We've already checked that the number of left & right ()'s are
6814 equal, so this loop will not be infinite. */
6818 if (*base_string
== ')')
6820 if (*base_string
== '(')
6823 while (parens_balanced
);
6825 temp_string
= base_string
;
6827 /* Skip past '(' and whitespace. */
6829 if (is_space_char (*base_string
))
6832 if (*base_string
== ','
6833 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6836 displacement_string_end
= temp_string
;
6838 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6842 base_string
= end_op
;
6843 if (is_space_char (*base_string
))
6847 /* There may be an index reg or scale factor here. */
6848 if (*base_string
== ',')
6851 if (is_space_char (*base_string
))
6854 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6857 base_string
= end_op
;
6858 if (is_space_char (*base_string
))
6860 if (*base_string
== ',')
6863 if (is_space_char (*base_string
))
6866 else if (*base_string
!= ')')
6868 as_bad (_("expecting `,' or `)' "
6869 "after index register in `%s'"),
6874 else if (*base_string
== REGISTER_PREFIX
)
6876 as_bad (_("bad register name `%s'"), base_string
);
6880 /* Check for scale factor. */
6881 if (*base_string
!= ')')
6883 char *end_scale
= i386_scale (base_string
);
6888 base_string
= end_scale
;
6889 if (is_space_char (*base_string
))
6891 if (*base_string
!= ')')
6893 as_bad (_("expecting `)' "
6894 "after scale factor in `%s'"),
6899 else if (!i
.index_reg
)
6901 as_bad (_("expecting index register or scale factor "
6902 "after `,'; got '%c'"),
6907 else if (*base_string
!= ')')
6909 as_bad (_("expecting `,' or `)' "
6910 "after base register in `%s'"),
6915 else if (*base_string
== REGISTER_PREFIX
)
6917 as_bad (_("bad register name `%s'"), base_string
);
6922 /* If there's an expression beginning the operand, parse it,
6923 assuming displacement_string_start and
6924 displacement_string_end are meaningful. */
6925 if (displacement_string_start
!= displacement_string_end
)
6927 if (!i386_displacement (displacement_string_start
,
6928 displacement_string_end
))
6932 /* Special case for (%dx) while doing input/output op. */
6934 && operand_type_equal (&i
.base_reg
->reg_type
,
6935 ®16_inoutportreg
)
6937 && i
.log2_scale_factor
== 0
6938 && i
.seg
[i
.mem_operands
] == 0
6939 && !operand_type_check (i
.types
[this_operand
], disp
))
6941 i
.types
[this_operand
] = inoutportreg
;
6945 if (i386_index_check (operand_string
) == 0)
6947 i
.types
[this_operand
].bitfield
.mem
= 1;
6952 /* It's not a memory operand; argh! */
6953 as_bad (_("invalid char %s beginning operand %d `%s'"),
6954 output_invalid (*op_string
),
6959 return 1; /* Normal return. */
6962 /* md_estimate_size_before_relax()
6964 Called just before relax() for rs_machine_dependent frags. The x86
6965 assembler uses these frags to handle variable size jump
6968 Any symbol that is now undefined will not become defined.
6969 Return the correct fr_subtype in the frag.
6970 Return the initial "guess for variable size of frag" to caller.
6971 The guess is actually the growth beyond the fixed part. Whatever
6972 we do to grow the fixed or variable part contributes to our
6976 md_estimate_size_before_relax (fragP
, segment
)
6980 /* We've already got fragP->fr_subtype right; all we have to do is
6981 check for un-relaxable symbols. On an ELF system, we can't relax
6982 an externally visible symbol, because it may be overridden by a
6984 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
6985 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6987 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
6988 || S_IS_WEAK (fragP
->fr_symbol
)
6989 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
6990 & BSF_GNU_INDIRECT_FUNCTION
))))
6992 #if defined (OBJ_COFF) && defined (TE_PE)
6993 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
6994 && S_IS_WEAK (fragP
->fr_symbol
))
6998 /* Symbol is undefined in this segment, or we need to keep a
6999 reloc so that weak symbols can be overridden. */
7000 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7001 enum bfd_reloc_code_real reloc_type
;
7002 unsigned char *opcode
;
7005 if (fragP
->fr_var
!= NO_RELOC
)
7006 reloc_type
= fragP
->fr_var
;
7008 reloc_type
= BFD_RELOC_16_PCREL
;
7010 reloc_type
= BFD_RELOC_32_PCREL
;
7012 old_fr_fix
= fragP
->fr_fix
;
7013 opcode
= (unsigned char *) fragP
->fr_opcode
;
7015 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7018 /* Make jmp (0xeb) a (d)word displacement jump. */
7020 fragP
->fr_fix
+= size
;
7021 fix_new (fragP
, old_fr_fix
, size
,
7023 fragP
->fr_offset
, 1,
7029 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7031 /* Negate the condition, and branch past an
7032 unconditional jump. */
7035 /* Insert an unconditional jump. */
7037 /* We added two extra opcode bytes, and have a two byte
7039 fragP
->fr_fix
+= 2 + 2;
7040 fix_new (fragP
, old_fr_fix
+ 2, 2,
7042 fragP
->fr_offset
, 1,
7049 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7054 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7056 fragP
->fr_offset
, 1,
7058 fixP
->fx_signed
= 1;
7062 /* This changes the byte-displacement jump 0x7N
7063 to the (d)word-displacement jump 0x0f,0x8N. */
7064 opcode
[1] = opcode
[0] + 0x10;
7065 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7066 /* We've added an opcode byte. */
7067 fragP
->fr_fix
+= 1 + size
;
7068 fix_new (fragP
, old_fr_fix
+ 1, size
,
7070 fragP
->fr_offset
, 1,
7075 BAD_CASE (fragP
->fr_subtype
);
7079 return fragP
->fr_fix
- old_fr_fix
;
7082 /* Guess size depending on current relax state. Initially the relax
7083 state will correspond to a short jump and we return 1, because
7084 the variable part of the frag (the branch offset) is one byte
7085 long. However, we can relax a section more than once and in that
7086 case we must either set fr_subtype back to the unrelaxed state,
7087 or return the value for the appropriate branch. */
7088 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7091 /* Called after relax() is finished.
7093 In: Address of frag.
7094 fr_type == rs_machine_dependent.
7095 fr_subtype is what the address relaxed to.
7097 Out: Any fixSs and constants are set up.
7098 Caller will turn frag into a ".space 0". */
7101 md_convert_frag (abfd
, sec
, fragP
)
7102 bfd
*abfd ATTRIBUTE_UNUSED
;
7103 segT sec ATTRIBUTE_UNUSED
;
7106 unsigned char *opcode
;
7107 unsigned char *where_to_put_displacement
= NULL
;
7108 offsetT target_address
;
7109 offsetT opcode_address
;
7110 unsigned int extension
= 0;
7111 offsetT displacement_from_opcode_start
;
7113 opcode
= (unsigned char *) fragP
->fr_opcode
;
7115 /* Address we want to reach in file space. */
7116 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7118 /* Address opcode resides at in file space. */
7119 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7121 /* Displacement from opcode start to fill into instruction. */
7122 displacement_from_opcode_start
= target_address
- opcode_address
;
7124 if ((fragP
->fr_subtype
& BIG
) == 0)
7126 /* Don't have to change opcode. */
7127 extension
= 1; /* 1 opcode + 1 displacement */
7128 where_to_put_displacement
= &opcode
[1];
7132 if (no_cond_jump_promotion
7133 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7134 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7135 _("long jump required"));
7137 switch (fragP
->fr_subtype
)
7139 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7140 extension
= 4; /* 1 opcode + 4 displacement */
7142 where_to_put_displacement
= &opcode
[1];
7145 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7146 extension
= 2; /* 1 opcode + 2 displacement */
7148 where_to_put_displacement
= &opcode
[1];
7151 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7152 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7153 extension
= 5; /* 2 opcode + 4 displacement */
7154 opcode
[1] = opcode
[0] + 0x10;
7155 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7156 where_to_put_displacement
= &opcode
[2];
7159 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7160 extension
= 3; /* 2 opcode + 2 displacement */
7161 opcode
[1] = opcode
[0] + 0x10;
7162 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7163 where_to_put_displacement
= &opcode
[2];
7166 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7171 where_to_put_displacement
= &opcode
[3];
7175 BAD_CASE (fragP
->fr_subtype
);
7180 /* If size if less then four we are sure that the operand fits,
7181 but if it's 4, then it could be that the displacement is larger
7183 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7185 && ((addressT
) (displacement_from_opcode_start
- extension
7186 + ((addressT
) 1 << 31))
7187 > (((addressT
) 2 << 31) - 1)))
7189 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7190 _("jump target out of range"));
7191 /* Make us emit 0. */
7192 displacement_from_opcode_start
= extension
;
7194 /* Now put displacement after opcode. */
7195 md_number_to_chars ((char *) where_to_put_displacement
,
7196 (valueT
) (displacement_from_opcode_start
- extension
),
7197 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7198 fragP
->fr_fix
+= extension
;
7201 /* Apply a fixup (fixS) to segment data, once it has been determined
7202 by our caller that we have all the info we need to fix it up.
7204 On the 386, immediates, displacements, and data pointers are all in
7205 the same (little-endian) format, so we don't need to care about which
7209 md_apply_fix (fixP
, valP
, seg
)
7210 /* The fix we're to put in. */
7212 /* Pointer to the value of the bits. */
7214 /* Segment fix is from. */
7215 segT seg ATTRIBUTE_UNUSED
;
7217 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7218 valueT value
= *valP
;
7220 #if !defined (TE_Mach)
7223 switch (fixP
->fx_r_type
)
7229 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7232 case BFD_RELOC_X86_64_32S
:
7233 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7236 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7239 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7244 if (fixP
->fx_addsy
!= NULL
7245 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7246 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7247 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7248 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7249 && !use_rela_relocations
)
7251 /* This is a hack. There should be a better way to handle this.
7252 This covers for the fact that bfd_install_relocation will
7253 subtract the current location (for partial_inplace, PC relative
7254 relocations); see more below. */
7258 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7261 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7263 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7266 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7269 || (symbol_section_p (fixP
->fx_addsy
)
7270 && sym_seg
!= absolute_section
))
7271 && !TC_FORCE_RELOCATION (fixP
))
7273 /* Yes, we add the values in twice. This is because
7274 bfd_install_relocation subtracts them out again. I think
7275 bfd_install_relocation is broken, but I don't dare change
7277 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7281 #if defined (OBJ_COFF) && defined (TE_PE)
7282 /* For some reason, the PE format does not store a
7283 section address offset for a PC relative symbol. */
7284 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7285 || S_IS_WEAK (fixP
->fx_addsy
))
7286 value
+= md_pcrel_from (fixP
);
7289 #if defined (OBJ_COFF) && defined (TE_PE)
7290 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7292 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7296 /* Fix a few things - the dynamic linker expects certain values here,
7297 and we must not disappoint it. */
7298 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7299 if (IS_ELF
&& fixP
->fx_addsy
)
7300 switch (fixP
->fx_r_type
)
7302 case BFD_RELOC_386_PLT32
:
7303 case BFD_RELOC_X86_64_PLT32
:
7304 /* Make the jump instruction point to the address of the operand. At
7305 runtime we merely add the offset to the actual PLT entry. */
7309 case BFD_RELOC_386_TLS_GD
:
7310 case BFD_RELOC_386_TLS_LDM
:
7311 case BFD_RELOC_386_TLS_IE_32
:
7312 case BFD_RELOC_386_TLS_IE
:
7313 case BFD_RELOC_386_TLS_GOTIE
:
7314 case BFD_RELOC_386_TLS_GOTDESC
:
7315 case BFD_RELOC_X86_64_TLSGD
:
7316 case BFD_RELOC_X86_64_TLSLD
:
7317 case BFD_RELOC_X86_64_GOTTPOFF
:
7318 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7319 value
= 0; /* Fully resolved at runtime. No addend. */
7321 case BFD_RELOC_386_TLS_LE
:
7322 case BFD_RELOC_386_TLS_LDO_32
:
7323 case BFD_RELOC_386_TLS_LE_32
:
7324 case BFD_RELOC_X86_64_DTPOFF32
:
7325 case BFD_RELOC_X86_64_DTPOFF64
:
7326 case BFD_RELOC_X86_64_TPOFF32
:
7327 case BFD_RELOC_X86_64_TPOFF64
:
7328 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7331 case BFD_RELOC_386_TLS_DESC_CALL
:
7332 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7333 value
= 0; /* Fully resolved at runtime. No addend. */
7334 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7338 case BFD_RELOC_386_GOT32
:
7339 case BFD_RELOC_X86_64_GOT32
:
7340 value
= 0; /* Fully resolved at runtime. No addend. */
7343 case BFD_RELOC_VTABLE_INHERIT
:
7344 case BFD_RELOC_VTABLE_ENTRY
:
7351 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7353 #endif /* !defined (TE_Mach) */
7355 /* Are we finished with this relocation now? */
7356 if (fixP
->fx_addsy
== NULL
)
7358 #if defined (OBJ_COFF) && defined (TE_PE)
7359 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7362 /* Remember value for tc_gen_reloc. */
7363 fixP
->fx_addnumber
= value
;
7364 /* Clear out the frag for now. */
7368 else if (use_rela_relocations
)
7370 fixP
->fx_no_overflow
= 1;
7371 /* Remember value for tc_gen_reloc. */
7372 fixP
->fx_addnumber
= value
;
7376 md_number_to_chars (p
, value
, fixP
->fx_size
);
7380 md_atof (int type
, char *litP
, int *sizeP
)
7382 /* This outputs the LITTLENUMs in REVERSE order;
7383 in accord with the bigendian 386. */
7384 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7387 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7390 output_invalid (int c
)
7393 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7396 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7397 "(0x%x)", (unsigned char) c
);
7398 return output_invalid_buf
;
7401 /* REG_STRING starts *before* REGISTER_PREFIX. */
7403 static const reg_entry
*
7404 parse_real_register (char *reg_string
, char **end_op
)
7406 char *s
= reg_string
;
7408 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7411 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7412 if (*s
== REGISTER_PREFIX
)
7415 if (is_space_char (*s
))
7419 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7421 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7422 return (const reg_entry
*) NULL
;
7426 /* For naked regs, make sure that we are not dealing with an identifier.
7427 This prevents confusing an identifier like `eax_var' with register
7429 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7430 return (const reg_entry
*) NULL
;
7434 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7436 /* Handle floating point regs, allowing spaces in the (i) part. */
7437 if (r
== i386_regtab
/* %st is first entry of table */)
7439 if (is_space_char (*s
))
7444 if (is_space_char (*s
))
7446 if (*s
>= '0' && *s
<= '7')
7450 if (is_space_char (*s
))
7455 r
= hash_find (reg_hash
, "st(0)");
7460 /* We have "%st(" then garbage. */
7461 return (const reg_entry
*) NULL
;
7465 if (r
== NULL
|| allow_pseudo_reg
)
7468 if (operand_type_all_zero (&r
->reg_type
))
7469 return (const reg_entry
*) NULL
;
7471 if ((r
->reg_type
.bitfield
.reg32
7472 || r
->reg_type
.bitfield
.sreg3
7473 || r
->reg_type
.bitfield
.control
7474 || r
->reg_type
.bitfield
.debug
7475 || r
->reg_type
.bitfield
.test
)
7476 && !cpu_arch_flags
.bitfield
.cpui386
)
7477 return (const reg_entry
*) NULL
;
7479 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7480 return (const reg_entry
*) NULL
;
7482 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7483 return (const reg_entry
*) NULL
;
7485 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7486 return (const reg_entry
*) NULL
;
7488 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7489 if (!allow_index_reg
7490 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7491 return (const reg_entry
*) NULL
;
7493 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7494 || r
->reg_type
.bitfield
.reg64
)
7495 && (!cpu_arch_flags
.bitfield
.cpulm
7496 || !operand_type_equal (&r
->reg_type
, &control
))
7497 && flag_code
!= CODE_64BIT
)
7498 return (const reg_entry
*) NULL
;
7500 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7501 return (const reg_entry
*) NULL
;
7506 /* REG_STRING starts *before* REGISTER_PREFIX. */
7508 static const reg_entry
*
7509 parse_register (char *reg_string
, char **end_op
)
7513 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7514 r
= parse_real_register (reg_string
, end_op
);
7519 char *save
= input_line_pointer
;
7523 input_line_pointer
= reg_string
;
7524 c
= get_symbol_end ();
7525 symbolP
= symbol_find (reg_string
);
7526 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7528 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7530 know (e
->X_op
== O_register
);
7531 know (e
->X_add_number
>= 0
7532 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7533 r
= i386_regtab
+ e
->X_add_number
;
7534 *end_op
= input_line_pointer
;
7536 *input_line_pointer
= c
;
7537 input_line_pointer
= save
;
7543 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7546 char *end
= input_line_pointer
;
7549 r
= parse_register (name
, &input_line_pointer
);
7550 if (r
&& end
<= input_line_pointer
)
7552 *nextcharP
= *input_line_pointer
;
7553 *input_line_pointer
= 0;
7554 e
->X_op
= O_register
;
7555 e
->X_add_number
= r
- i386_regtab
;
7558 input_line_pointer
= end
;
7560 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7564 md_operand (expressionS
*e
)
7569 switch (*input_line_pointer
)
7571 case REGISTER_PREFIX
:
7572 r
= parse_real_register (input_line_pointer
, &end
);
7575 e
->X_op
= O_register
;
7576 e
->X_add_number
= r
- i386_regtab
;
7577 input_line_pointer
= end
;
7582 gas_assert (intel_syntax
);
7583 end
= input_line_pointer
++;
7585 if (*input_line_pointer
== ']')
7587 ++input_line_pointer
;
7588 e
->X_op_symbol
= make_expr_symbol (e
);
7589 e
->X_add_symbol
= NULL
;
7590 e
->X_add_number
= 0;
7596 input_line_pointer
= end
;
7603 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7604 const char *md_shortopts
= "kVQ:sqn";
7606 const char *md_shortopts
= "qn";
7609 #define OPTION_32 (OPTION_MD_BASE + 0)
7610 #define OPTION_64 (OPTION_MD_BASE + 1)
7611 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7612 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7613 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7614 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7615 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7616 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7617 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7618 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7619 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7620 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7622 struct option md_longopts
[] =
7624 {"32", no_argument
, NULL
, OPTION_32
},
7625 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7626 || defined (TE_PE) || defined (TE_PEP))
7627 {"64", no_argument
, NULL
, OPTION_64
},
7629 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7630 {"march", required_argument
, NULL
, OPTION_MARCH
},
7631 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7632 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7633 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7634 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7635 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7636 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7637 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7638 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7639 {NULL
, no_argument
, NULL
, 0}
7641 size_t md_longopts_size
= sizeof (md_longopts
);
7644 md_parse_option (int c
, char *arg
)
7652 optimize_align_code
= 0;
7659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7660 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7661 should be emitted or not. FIXME: Not implemented. */
7665 /* -V: SVR4 argument to print version ID. */
7667 print_version_id ();
7670 /* -k: Ignore for FreeBSD compatibility. */
7675 /* -s: On i386 Solaris, this tells the native assembler to use
7676 .stab instead of .stab.excl. We always use .stab anyhow. */
7679 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7680 || defined (TE_PE) || defined (TE_PEP))
7683 const char **list
, **l
;
7685 list
= bfd_target_list ();
7686 for (l
= list
; *l
!= NULL
; l
++)
7687 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7688 || strcmp (*l
, "coff-x86-64") == 0
7689 || strcmp (*l
, "pe-x86-64") == 0
7690 || strcmp (*l
, "pei-x86-64") == 0)
7692 default_arch
= "x86_64";
7696 as_fatal (_("No compiled in support for x86_64"));
7703 default_arch
= "i386";
7707 #ifdef SVR4_COMMENT_CHARS
7712 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7714 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7718 i386_comment_chars
= n
;
7724 arch
= xstrdup (arg
);
7728 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7729 next
= strchr (arch
, '+');
7732 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7734 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7737 cpu_arch_name
= cpu_arch
[i
].name
;
7738 cpu_sub_arch_name
= NULL
;
7739 cpu_arch_flags
= cpu_arch
[i
].flags
;
7740 cpu_arch_isa
= cpu_arch
[i
].type
;
7741 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7742 if (!cpu_arch_tune_set
)
7744 cpu_arch_tune
= cpu_arch_isa
;
7745 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7749 else if (*cpu_arch
[i
].name
== '.'
7750 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7752 /* ISA entension. */
7753 i386_cpu_flags flags
;
7754 flags
= cpu_flags_or (cpu_arch_flags
,
7756 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7758 if (cpu_sub_arch_name
)
7760 char *name
= cpu_sub_arch_name
;
7761 cpu_sub_arch_name
= concat (name
,
7763 (const char *) NULL
);
7767 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7768 cpu_arch_flags
= flags
;
7774 if (i
>= ARRAY_SIZE (cpu_arch
))
7775 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7779 while (next
!= NULL
);
7784 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7785 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7787 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7789 cpu_arch_tune_set
= 1;
7790 cpu_arch_tune
= cpu_arch
[i
].type
;
7791 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7795 if (i
>= ARRAY_SIZE (cpu_arch
))
7796 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7799 case OPTION_MMNEMONIC
:
7800 if (strcasecmp (arg
, "att") == 0)
7802 else if (strcasecmp (arg
, "intel") == 0)
7805 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7808 case OPTION_MSYNTAX
:
7809 if (strcasecmp (arg
, "att") == 0)
7811 else if (strcasecmp (arg
, "intel") == 0)
7814 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7817 case OPTION_MINDEX_REG
:
7818 allow_index_reg
= 1;
7821 case OPTION_MNAKED_REG
:
7822 allow_naked_reg
= 1;
7825 case OPTION_MOLD_GCC
:
7829 case OPTION_MSSE2AVX
:
7833 case OPTION_MSSE_CHECK
:
7834 if (strcasecmp (arg
, "error") == 0)
7835 sse_check
= sse_check_error
;
7836 else if (strcasecmp (arg
, "warning") == 0)
7837 sse_check
= sse_check_warning
;
7838 else if (strcasecmp (arg
, "none") == 0)
7839 sse_check
= sse_check_none
;
7841 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7851 md_show_usage (stream
)
7854 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7855 fprintf (stream
, _("\
7857 -V print assembler version number\n\
7860 fprintf (stream
, _("\
7861 -n Do not optimize code alignment\n\
7862 -q quieten some warnings\n"));
7863 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7864 fprintf (stream
, _("\
7867 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7868 || defined (TE_PE) || defined (TE_PEP))
7869 fprintf (stream
, _("\
7870 --32/--64 generate 32bit/64bit code\n"));
7872 #ifdef SVR4_COMMENT_CHARS
7873 fprintf (stream
, _("\
7874 --divide do not treat `/' as a comment character\n"));
7876 fprintf (stream
, _("\
7877 --divide ignored\n"));
7879 fprintf (stream
, _("\
7880 -march=CPU[,+EXTENSION...]\n\
7881 generate code for CPU and EXTENSION, CPU is one of:\n\
7882 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7883 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7884 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7885 generic32, generic64\n\
7886 EXTENSION is combination of:\n\
7887 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7888 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
7889 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
7890 svme, abm, padlock, fma4\n"));
7891 fprintf (stream
, _("\
7892 -mtune=CPU optimize for CPU, CPU is one of:\n\
7893 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7894 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7895 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7896 generic32, generic64\n"));
7897 fprintf (stream
, _("\
7898 -msse2avx encode SSE instructions with VEX prefix\n"));
7899 fprintf (stream
, _("\
7900 -msse-check=[none|error|warning]\n\
7901 check SSE instructions\n"));
7902 fprintf (stream
, _("\
7903 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7904 fprintf (stream
, _("\
7905 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7906 fprintf (stream
, _("\
7907 -mindex-reg support pseudo index registers\n"));
7908 fprintf (stream
, _("\
7909 -mnaked-reg don't require `%%' prefix for registers\n"));
7910 fprintf (stream
, _("\
7911 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7914 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7915 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7916 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
7918 /* Pick the target format to use. */
7921 i386_target_format (void)
7923 if (!strcmp (default_arch
, "x86_64"))
7925 set_code_flag (CODE_64BIT
);
7926 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
7928 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7929 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7930 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7931 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
7932 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
7933 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
7934 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
7935 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
7936 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
7937 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
7939 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
7941 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7942 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7943 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7944 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
7945 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
7946 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
7947 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
7948 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
7949 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
7950 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
7953 else if (!strcmp (default_arch
, "i386"))
7955 set_code_flag (CODE_32BIT
);
7956 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
7958 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7959 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7960 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7962 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
7964 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7965 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7966 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7970 as_fatal (_("Unknown architecture"));
7971 switch (OUTPUT_FLAVOR
)
7973 #if defined (TE_PE) || defined (TE_PEP)
7974 case bfd_target_coff_flavour
:
7975 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
7977 #ifdef OBJ_MAYBE_AOUT
7978 case bfd_target_aout_flavour
:
7979 return AOUT_TARGET_FORMAT
;
7981 #ifdef OBJ_MAYBE_COFF
7982 case bfd_target_coff_flavour
:
7985 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7986 case bfd_target_elf_flavour
:
7988 if (flag_code
== CODE_64BIT
)
7991 use_rela_relocations
= 1;
7993 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
7996 #if defined (OBJ_MACH_O)
7997 case bfd_target_mach_o_flavour
:
7998 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8006 #endif /* OBJ_MAYBE_ more than one */
8008 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8010 i386_elf_emit_arch_note (void)
8012 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8015 asection
*seg
= now_seg
;
8016 subsegT subseg
= now_subseg
;
8017 Elf_Internal_Note i_note
;
8018 Elf_External_Note e_note
;
8019 asection
*note_secp
;
8022 /* Create the .note section. */
8023 note_secp
= subseg_new (".note", 0);
8024 bfd_set_section_flags (stdoutput
,
8026 SEC_HAS_CONTENTS
| SEC_READONLY
);
8028 /* Process the arch string. */
8029 len
= strlen (cpu_arch_name
);
8031 i_note
.namesz
= len
+ 1;
8033 i_note
.type
= NT_ARCH
;
8034 p
= frag_more (sizeof (e_note
.namesz
));
8035 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8036 p
= frag_more (sizeof (e_note
.descsz
));
8037 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8038 p
= frag_more (sizeof (e_note
.type
));
8039 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8040 p
= frag_more (len
+ 1);
8041 strcpy (p
, cpu_arch_name
);
8043 frag_align (2, 0, 0);
8045 subseg_set (seg
, subseg
);
8051 md_undefined_symbol (name
)
8054 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8055 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8056 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8057 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8061 if (symbol_find (name
))
8062 as_bad (_("GOT already in symbol table"));
8063 GOT_symbol
= symbol_new (name
, undefined_section
,
8064 (valueT
) 0, &zero_address_frag
);
8071 /* Round up a section size to the appropriate boundary. */
8074 md_section_align (segment
, size
)
8075 segT segment ATTRIBUTE_UNUSED
;
8078 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8079 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8081 /* For a.out, force the section size to be aligned. If we don't do
8082 this, BFD will align it for us, but it will not write out the
8083 final bytes of the section. This may be a bug in BFD, but it is
8084 easier to fix it here since that is how the other a.out targets
8088 align
= bfd_get_section_alignment (stdoutput
, segment
);
8089 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8096 /* On the i386, PC-relative offsets are relative to the start of the
8097 next instruction. That is, the address of the offset, plus its
8098 size, since the offset is always the last part of the insn. */
8101 md_pcrel_from (fixS
*fixP
)
8103 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8109 s_bss (int ignore ATTRIBUTE_UNUSED
)
8113 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8115 obj_elf_section_change_hook ();
8117 temp
= get_absolute_expression ();
8118 subseg_set (bss_section
, (subsegT
) temp
);
8119 demand_empty_rest_of_line ();
8125 i386_validate_fix (fixS
*fixp
)
8127 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8129 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8133 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8138 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8140 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8147 tc_gen_reloc (section
, fixp
)
8148 asection
*section ATTRIBUTE_UNUSED
;
8152 bfd_reloc_code_real_type code
;
8154 switch (fixp
->fx_r_type
)
8156 case BFD_RELOC_X86_64_PLT32
:
8157 case BFD_RELOC_X86_64_GOT32
:
8158 case BFD_RELOC_X86_64_GOTPCREL
:
8159 case BFD_RELOC_386_PLT32
:
8160 case BFD_RELOC_386_GOT32
:
8161 case BFD_RELOC_386_GOTOFF
:
8162 case BFD_RELOC_386_GOTPC
:
8163 case BFD_RELOC_386_TLS_GD
:
8164 case BFD_RELOC_386_TLS_LDM
:
8165 case BFD_RELOC_386_TLS_LDO_32
:
8166 case BFD_RELOC_386_TLS_IE_32
:
8167 case BFD_RELOC_386_TLS_IE
:
8168 case BFD_RELOC_386_TLS_GOTIE
:
8169 case BFD_RELOC_386_TLS_LE_32
:
8170 case BFD_RELOC_386_TLS_LE
:
8171 case BFD_RELOC_386_TLS_GOTDESC
:
8172 case BFD_RELOC_386_TLS_DESC_CALL
:
8173 case BFD_RELOC_X86_64_TLSGD
:
8174 case BFD_RELOC_X86_64_TLSLD
:
8175 case BFD_RELOC_X86_64_DTPOFF32
:
8176 case BFD_RELOC_X86_64_DTPOFF64
:
8177 case BFD_RELOC_X86_64_GOTTPOFF
:
8178 case BFD_RELOC_X86_64_TPOFF32
:
8179 case BFD_RELOC_X86_64_TPOFF64
:
8180 case BFD_RELOC_X86_64_GOTOFF64
:
8181 case BFD_RELOC_X86_64_GOTPC32
:
8182 case BFD_RELOC_X86_64_GOT64
:
8183 case BFD_RELOC_X86_64_GOTPCREL64
:
8184 case BFD_RELOC_X86_64_GOTPC64
:
8185 case BFD_RELOC_X86_64_GOTPLT64
:
8186 case BFD_RELOC_X86_64_PLTOFF64
:
8187 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8188 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8190 case BFD_RELOC_VTABLE_ENTRY
:
8191 case BFD_RELOC_VTABLE_INHERIT
:
8193 case BFD_RELOC_32_SECREL
:
8195 code
= fixp
->fx_r_type
;
8197 case BFD_RELOC_X86_64_32S
:
8198 if (!fixp
->fx_pcrel
)
8200 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8201 code
= fixp
->fx_r_type
;
8207 switch (fixp
->fx_size
)
8210 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8211 _("can not do %d byte pc-relative relocation"),
8213 code
= BFD_RELOC_32_PCREL
;
8215 case 1: code
= BFD_RELOC_8_PCREL
; break;
8216 case 2: code
= BFD_RELOC_16_PCREL
; break;
8217 case 4: code
= BFD_RELOC_32_PCREL
; break;
8219 case 8: code
= BFD_RELOC_64_PCREL
; break;
8225 switch (fixp
->fx_size
)
8228 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8229 _("can not do %d byte relocation"),
8231 code
= BFD_RELOC_32
;
8233 case 1: code
= BFD_RELOC_8
; break;
8234 case 2: code
= BFD_RELOC_16
; break;
8235 case 4: code
= BFD_RELOC_32
; break;
8237 case 8: code
= BFD_RELOC_64
; break;
8244 if ((code
== BFD_RELOC_32
8245 || code
== BFD_RELOC_32_PCREL
8246 || code
== BFD_RELOC_X86_64_32S
)
8248 && fixp
->fx_addsy
== GOT_symbol
)
8251 code
= BFD_RELOC_386_GOTPC
;
8253 code
= BFD_RELOC_X86_64_GOTPC32
;
8255 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8257 && fixp
->fx_addsy
== GOT_symbol
)
8259 code
= BFD_RELOC_X86_64_GOTPC64
;
8262 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8263 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8264 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8266 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8268 if (!use_rela_relocations
)
8270 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8271 vtable entry to be used in the relocation's section offset. */
8272 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8273 rel
->address
= fixp
->fx_offset
;
8274 #if defined (OBJ_COFF) && defined (TE_PE)
8275 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8276 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8281 /* Use the rela in 64bit mode. */
8284 if (!fixp
->fx_pcrel
)
8285 rel
->addend
= fixp
->fx_offset
;
8289 case BFD_RELOC_X86_64_PLT32
:
8290 case BFD_RELOC_X86_64_GOT32
:
8291 case BFD_RELOC_X86_64_GOTPCREL
:
8292 case BFD_RELOC_X86_64_TLSGD
:
8293 case BFD_RELOC_X86_64_TLSLD
:
8294 case BFD_RELOC_X86_64_GOTTPOFF
:
8295 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8296 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8297 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8300 rel
->addend
= (section
->vma
8302 + fixp
->fx_addnumber
8303 + md_pcrel_from (fixp
));
8308 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8309 if (rel
->howto
== NULL
)
8311 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8312 _("cannot represent relocation type %s"),
8313 bfd_get_reloc_code_name (code
));
8314 /* Set howto to a garbage value so that we can keep going. */
8315 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8316 gas_assert (rel
->howto
!= NULL
);
8322 #include "tc-i386-intel.c"
8325 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8327 int saved_naked_reg
;
8328 char saved_register_dot
;
8330 saved_naked_reg
= allow_naked_reg
;
8331 allow_naked_reg
= 1;
8332 saved_register_dot
= register_chars
['.'];
8333 register_chars
['.'] = '.';
8334 allow_pseudo_reg
= 1;
8335 expression_and_evaluate (exp
);
8336 allow_pseudo_reg
= 0;
8337 register_chars
['.'] = saved_register_dot
;
8338 allow_naked_reg
= saved_naked_reg
;
8340 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8342 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8344 exp
->X_op
= O_constant
;
8345 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8346 .dw2_regnum
[flag_code
>> 1];
8349 exp
->X_op
= O_illegal
;
8354 tc_x86_frame_initial_instructions (void)
8356 static unsigned int sp_regno
[2];
8358 if (!sp_regno
[flag_code
>> 1])
8360 char *saved_input
= input_line_pointer
;
8361 char sp
[][4] = {"esp", "rsp"};
8364 input_line_pointer
= sp
[flag_code
>> 1];
8365 tc_x86_parse_to_dw2regnum (&exp
);
8366 gas_assert (exp
.X_op
== O_constant
);
8367 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8368 input_line_pointer
= saved_input
;
8371 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8372 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8376 i386_elf_section_type (const char *str
, size_t len
)
8378 if (flag_code
== CODE_64BIT
8379 && len
== sizeof ("unwind") - 1
8380 && strncmp (str
, "unwind", 6) == 0)
8381 return SHT_X86_64_UNWIND
;
8388 i386_solaris_fix_up_eh_frame (segT sec
)
8390 if (flag_code
== CODE_64BIT
)
8391 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8397 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8401 expr
.X_op
= O_secrel
;
8402 expr
.X_add_symbol
= symbol
;
8403 expr
.X_add_number
= 0;
8404 emit_expr (&expr
, size
);
8408 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8409 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8412 x86_64_section_letter (int letter
, char **ptr_msg
)
8414 if (flag_code
== CODE_64BIT
)
8417 return SHF_X86_64_LARGE
;
8419 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8422 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8427 x86_64_section_word (char *str
, size_t len
)
8429 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8430 return SHF_X86_64_LARGE
;
8436 handle_large_common (int small ATTRIBUTE_UNUSED
)
8438 if (flag_code
!= CODE_64BIT
)
8440 s_comm_internal (0, elf_common_parse
);
8441 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8445 static segT lbss_section
;
8446 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8447 asection
*saved_bss_section
= bss_section
;
8449 if (lbss_section
== NULL
)
8451 flagword applicable
;
8453 subsegT subseg
= now_subseg
;
8455 /* The .lbss section is for local .largecomm symbols. */
8456 lbss_section
= subseg_new (".lbss", 0);
8457 applicable
= bfd_applicable_section_flags (stdoutput
);
8458 bfd_set_section_flags (stdoutput
, lbss_section
,
8459 applicable
& SEC_ALLOC
);
8460 seg_info (lbss_section
)->bss
= 1;
8462 subseg_set (seg
, subseg
);
8465 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8466 bss_section
= lbss_section
;
8468 s_comm_internal (0, elf_common_parse
);
8470 elf_com_section_ptr
= saved_com_section_ptr
;
8471 bss_section
= saved_bss_section
;
8474 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */