1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const insn_template
*start
;
101 const insn_template
*end
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const insn_template
*match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "l1om", PROCESSOR_L1OM
,
582 { "k6", PROCESSOR_K6
,
584 { "k6_2", PROCESSOR_K6
,
586 { "athlon", PROCESSOR_ATHLON
,
588 { "sledgehammer", PROCESSOR_K8
,
590 { "opteron", PROCESSOR_K8
,
592 { "k8", PROCESSOR_K8
,
594 { "amdfam10", PROCESSOR_AMDFAM10
,
595 CPU_AMDFAM10_FLAGS
},
596 { ".8087", PROCESSOR_UNKNOWN
,
598 { ".287", PROCESSOR_UNKNOWN
,
600 { ".387", PROCESSOR_UNKNOWN
,
602 { ".no87", PROCESSOR_UNKNOWN
,
604 { ".mmx", PROCESSOR_UNKNOWN
,
606 { ".nommx", PROCESSOR_UNKNOWN
,
608 { ".sse", PROCESSOR_UNKNOWN
,
610 { ".sse2", PROCESSOR_UNKNOWN
,
612 { ".sse3", PROCESSOR_UNKNOWN
,
614 { ".ssse3", PROCESSOR_UNKNOWN
,
616 { ".sse4.1", PROCESSOR_UNKNOWN
,
618 { ".sse4.2", PROCESSOR_UNKNOWN
,
620 { ".sse4", PROCESSOR_UNKNOWN
,
622 { ".nosse", PROCESSOR_UNKNOWN
,
624 { ".avx", PROCESSOR_UNKNOWN
,
626 { ".noavx", PROCESSOR_UNKNOWN
,
628 { ".vmx", PROCESSOR_UNKNOWN
,
630 { ".smx", PROCESSOR_UNKNOWN
,
632 { ".xsave", PROCESSOR_UNKNOWN
,
634 { ".aes", PROCESSOR_UNKNOWN
,
636 { ".pclmul", PROCESSOR_UNKNOWN
,
638 { ".clmul", PROCESSOR_UNKNOWN
,
640 { ".fma", PROCESSOR_UNKNOWN
,
642 { ".fma4", PROCESSOR_UNKNOWN
,
644 { ".movbe", PROCESSOR_UNKNOWN
,
646 { ".ept", PROCESSOR_UNKNOWN
,
648 { ".clflush", PROCESSOR_UNKNOWN
,
650 { ".syscall", PROCESSOR_UNKNOWN
,
652 { ".rdtscp", PROCESSOR_UNKNOWN
,
654 { ".3dnow", PROCESSOR_UNKNOWN
,
656 { ".3dnowa", PROCESSOR_UNKNOWN
,
658 { ".padlock", PROCESSOR_UNKNOWN
,
660 { ".pacifica", PROCESSOR_UNKNOWN
,
662 { ".svme", PROCESSOR_UNKNOWN
,
664 { ".sse4a", PROCESSOR_UNKNOWN
,
666 { ".abm", PROCESSOR_UNKNOWN
,
671 /* Like s_lcomm_internal in gas/read.c but the alignment string
672 is allowed to be optional. */
675 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
682 && *input_line_pointer
== ',')
684 align
= parse_align (needs_align
- 1);
686 if (align
== (addressT
) -1)
701 bss_alloc (symbolP
, size
, align
);
706 pe_lcomm (int needs_align
)
708 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
712 const pseudo_typeS md_pseudo_table
[] =
714 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
715 {"align", s_align_bytes
, 0},
717 {"align", s_align_ptwo
, 0},
719 {"arch", set_cpu_arch
, 0},
723 {"lcomm", pe_lcomm
, 1},
725 {"ffloat", float_cons
, 'f'},
726 {"dfloat", float_cons
, 'd'},
727 {"tfloat", float_cons
, 'x'},
729 {"slong", signed_cons
, 4},
730 {"noopt", s_ignore
, 0},
731 {"optim", s_ignore
, 0},
732 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
733 {"code16", set_code_flag
, CODE_16BIT
},
734 {"code32", set_code_flag
, CODE_32BIT
},
735 {"code64", set_code_flag
, CODE_64BIT
},
736 {"intel_syntax", set_intel_syntax
, 1},
737 {"att_syntax", set_intel_syntax
, 0},
738 {"intel_mnemonic", set_intel_mnemonic
, 1},
739 {"att_mnemonic", set_intel_mnemonic
, 0},
740 {"allow_index_reg", set_allow_index_reg
, 1},
741 {"disallow_index_reg", set_allow_index_reg
, 0},
742 {"sse_check", set_sse_check
, 0},
743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
744 {"largecomm", handle_large_common
, 0},
746 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
747 {"loc", dwarf2_directive_loc
, 0},
748 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
751 {"secrel32", pe_directive_secrel
, 0},
756 /* For interface with expression (). */
757 extern char *input_line_pointer
;
759 /* Hash table for instruction mnemonic lookup. */
760 static struct hash_control
*op_hash
;
762 /* Hash table for register lookup. */
763 static struct hash_control
*reg_hash
;
766 i386_align_code (fragS
*fragP
, int count
)
768 /* Various efficient no-op patterns for aligning code labels.
769 Note: Don't try to assemble the instructions in the comments.
770 0L and 0w are not legal. */
771 static const char f32_1
[] =
773 static const char f32_2
[] =
774 {0x66,0x90}; /* xchg %ax,%ax */
775 static const char f32_3
[] =
776 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
777 static const char f32_4
[] =
778 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
779 static const char f32_5
[] =
781 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_6
[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
784 static const char f32_7
[] =
785 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
786 static const char f32_8
[] =
788 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_9
[] =
790 {0x89,0xf6, /* movl %esi,%esi */
791 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
792 static const char f32_10
[] =
793 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_11
[] =
796 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_12
[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
800 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
801 static const char f32_13
[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_14
[] =
805 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f16_3
[] =
808 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
809 static const char f16_4
[] =
810 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
811 static const char f16_5
[] =
813 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_6
[] =
815 {0x89,0xf6, /* mov %si,%si */
816 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
817 static const char f16_7
[] =
818 {0x8d,0x74,0x00, /* lea 0(%si),%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_8
[] =
821 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
823 static const char jump_31
[] =
824 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
828 static const char *const f32_patt
[] = {
829 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
830 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
832 static const char *const f16_patt
[] = {
833 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
836 static const char alt_3
[] =
838 /* nopl 0(%[re]ax) */
839 static const char alt_4
[] =
840 {0x0f,0x1f,0x40,0x00};
841 /* nopl 0(%[re]ax,%[re]ax,1) */
842 static const char alt_5
[] =
843 {0x0f,0x1f,0x44,0x00,0x00};
844 /* nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_6
[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00};
847 /* nopl 0L(%[re]ax) */
848 static const char alt_7
[] =
849 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 /* nopl 0L(%[re]ax,%[re]ax,1) */
851 static const char alt_8
[] =
852 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* nopw 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_9
[] =
855 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_10
[] =
858 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 nopw %cs:0L(%[re]ax,%[re]ax,1) */
861 static const char alt_long_11
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_12
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
874 nopw %cs:0L(%[re]ax,%[re]ax,1) */
875 static const char alt_long_13
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
884 nopw %cs:0L(%[re]ax,%[re]ax,1) */
885 static const char alt_long_14
[] =
890 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_15
[] =
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 /* nopl 0(%[re]ax,%[re]ax,1)
905 nopw 0(%[re]ax,%[re]ax,1) */
906 static const char alt_short_11
[] =
907 {0x0f,0x1f,0x44,0x00,0x00,
908 0x66,0x0f,0x1f,0x44,0x00,0x00};
909 /* nopw 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_12
[] =
912 {0x66,0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
916 static const char alt_short_13
[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 static const char alt_short_14
[] =
922 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
925 nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_short_15
[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 static const char *const alt_short_patt
[] = {
930 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
931 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
932 alt_short_14
, alt_short_15
934 static const char *const alt_long_patt
[] = {
935 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
936 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
937 alt_long_14
, alt_long_15
940 /* Only align for at least a positive non-zero boundary. */
941 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
944 /* We need to decide which NOP sequence to use for 32bit and
945 64bit. When -mtune= is used:
947 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
948 PROCESSOR_GENERIC32, f32_patt will be used.
949 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
950 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
951 PROCESSOR_GENERIC64, alt_long_patt will be used.
952 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
953 PROCESSOR_AMDFAM10, alt_short_patt will be used.
955 When -mtune= isn't used, alt_long_patt will be used if
956 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
959 When -march= or .arch is used, we can't use anything beyond
960 cpu_arch_isa_flags. */
962 if (flag_code
== CODE_16BIT
)
966 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
968 /* Adjust jump offset. */
969 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
972 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
973 f16_patt
[count
- 1], count
);
977 const char *const *patt
= NULL
;
979 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
981 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
982 switch (cpu_arch_tune
)
984 case PROCESSOR_UNKNOWN
:
985 /* We use cpu_arch_isa_flags to check if we SHOULD
986 optimize for Cpu686. */
987 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
988 patt
= alt_long_patt
;
992 case PROCESSOR_PENTIUMPRO
:
993 case PROCESSOR_PENTIUM4
:
994 case PROCESSOR_NOCONA
:
996 case PROCESSOR_CORE2
:
997 case PROCESSOR_COREI7
:
999 case PROCESSOR_GENERIC64
:
1000 patt
= alt_long_patt
;
1003 case PROCESSOR_ATHLON
:
1005 case PROCESSOR_AMDFAM10
:
1006 patt
= alt_short_patt
;
1008 case PROCESSOR_I386
:
1009 case PROCESSOR_I486
:
1010 case PROCESSOR_PENTIUM
:
1011 case PROCESSOR_GENERIC32
:
1018 switch (fragP
->tc_frag_data
.tune
)
1020 case PROCESSOR_UNKNOWN
:
1021 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1022 PROCESSOR_UNKNOWN. */
1026 case PROCESSOR_I386
:
1027 case PROCESSOR_I486
:
1028 case PROCESSOR_PENTIUM
:
1030 case PROCESSOR_ATHLON
:
1032 case PROCESSOR_AMDFAM10
:
1033 case PROCESSOR_GENERIC32
:
1034 /* We use cpu_arch_isa_flags to check if we CAN optimize
1036 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1037 patt
= alt_short_patt
;
1041 case PROCESSOR_PENTIUMPRO
:
1042 case PROCESSOR_PENTIUM4
:
1043 case PROCESSOR_NOCONA
:
1044 case PROCESSOR_CORE
:
1045 case PROCESSOR_CORE2
:
1046 case PROCESSOR_COREI7
:
1047 case PROCESSOR_L1OM
:
1048 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1049 patt
= alt_long_patt
;
1053 case PROCESSOR_GENERIC64
:
1054 patt
= alt_long_patt
;
1059 if (patt
== f32_patt
)
1061 /* If the padding is less than 15 bytes, we use the normal
1062 ones. Otherwise, we use a jump instruction and adjust
1066 /* For 64bit, the limit is 3 bytes. */
1067 if (flag_code
== CODE_64BIT
1068 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1073 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1074 patt
[count
- 1], count
);
1077 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1079 /* Adjust jump offset. */
1080 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1085 /* Maximum length of an instruction is 15 byte. If the
1086 padding is greater than 15 bytes and we don't use jump,
1087 we have to break it into smaller pieces. */
1088 int padding
= count
;
1089 while (padding
> 15)
1092 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1097 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1098 patt
[padding
- 1], padding
);
1101 fragP
->fr_var
= count
;
1105 operand_type_all_zero (const union i386_operand_type
*x
)
1107 switch (ARRAY_SIZE(x
->array
))
1116 return !x
->array
[0];
1123 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1125 switch (ARRAY_SIZE(x
->array
))
1140 operand_type_equal (const union i386_operand_type
*x
,
1141 const union i386_operand_type
*y
)
1143 switch (ARRAY_SIZE(x
->array
))
1146 if (x
->array
[2] != y
->array
[2])
1149 if (x
->array
[1] != y
->array
[1])
1152 return x
->array
[0] == y
->array
[0];
1160 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1162 switch (ARRAY_SIZE(x
->array
))
1171 return !x
->array
[0];
1178 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1180 switch (ARRAY_SIZE(x
->array
))
1195 cpu_flags_equal (const union i386_cpu_flags
*x
,
1196 const union i386_cpu_flags
*y
)
1198 switch (ARRAY_SIZE(x
->array
))
1201 if (x
->array
[2] != y
->array
[2])
1204 if (x
->array
[1] != y
->array
[1])
1207 return x
->array
[0] == y
->array
[0];
1215 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1217 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1218 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1221 static INLINE i386_cpu_flags
1222 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1224 switch (ARRAY_SIZE (x
.array
))
1227 x
.array
[2] &= y
.array
[2];
1229 x
.array
[1] &= y
.array
[1];
1231 x
.array
[0] &= y
.array
[0];
1239 static INLINE i386_cpu_flags
1240 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1242 switch (ARRAY_SIZE (x
.array
))
1245 x
.array
[2] |= y
.array
[2];
1247 x
.array
[1] |= y
.array
[1];
1249 x
.array
[0] |= y
.array
[0];
1257 static INLINE i386_cpu_flags
1258 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1260 switch (ARRAY_SIZE (x
.array
))
1263 x
.array
[2] &= ~y
.array
[2];
1265 x
.array
[1] &= ~y
.array
[1];
1267 x
.array
[0] &= ~y
.array
[0];
1275 #define CPU_FLAGS_ARCH_MATCH 0x1
1276 #define CPU_FLAGS_64BIT_MATCH 0x2
1277 #define CPU_FLAGS_AES_MATCH 0x4
1278 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1279 #define CPU_FLAGS_AVX_MATCH 0x10
1281 #define CPU_FLAGS_32BIT_MATCH \
1282 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1283 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1284 #define CPU_FLAGS_PERFECT_MATCH \
1285 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1287 /* Return CPU flags match bits. */
1290 cpu_flags_match (const insn_template
*t
)
1292 i386_cpu_flags x
= t
->cpu_flags
;
1293 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1295 x
.bitfield
.cpu64
= 0;
1296 x
.bitfield
.cpuno64
= 0;
1298 if (cpu_flags_all_zero (&x
))
1300 /* This instruction is available on all archs. */
1301 match
|= CPU_FLAGS_32BIT_MATCH
;
1305 /* This instruction is available only on some archs. */
1306 i386_cpu_flags cpu
= cpu_arch_flags
;
1308 cpu
.bitfield
.cpu64
= 0;
1309 cpu
.bitfield
.cpuno64
= 0;
1310 cpu
= cpu_flags_and (x
, cpu
);
1311 if (!cpu_flags_all_zero (&cpu
))
1313 if (x
.bitfield
.cpuavx
)
1315 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1316 if (cpu
.bitfield
.cpuavx
)
1318 /* Check SSE2AVX. */
1319 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1321 match
|= (CPU_FLAGS_ARCH_MATCH
1322 | CPU_FLAGS_AVX_MATCH
);
1324 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1325 match
|= CPU_FLAGS_AES_MATCH
;
1327 if (!x
.bitfield
.cpupclmul
1328 || cpu
.bitfield
.cpupclmul
)
1329 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1333 match
|= CPU_FLAGS_ARCH_MATCH
;
1336 match
|= CPU_FLAGS_32BIT_MATCH
;
1342 static INLINE i386_operand_type
1343 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1345 switch (ARRAY_SIZE (x
.array
))
1348 x
.array
[2] &= y
.array
[2];
1350 x
.array
[1] &= y
.array
[1];
1352 x
.array
[0] &= y
.array
[0];
1360 static INLINE i386_operand_type
1361 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1363 switch (ARRAY_SIZE (x
.array
))
1366 x
.array
[2] |= y
.array
[2];
1368 x
.array
[1] |= y
.array
[1];
1370 x
.array
[0] |= y
.array
[0];
1378 static INLINE i386_operand_type
1379 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1381 switch (ARRAY_SIZE (x
.array
))
1384 x
.array
[2] ^= y
.array
[2];
1386 x
.array
[1] ^= y
.array
[1];
1388 x
.array
[0] ^= y
.array
[0];
1396 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1397 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1398 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1399 static const i386_operand_type inoutportreg
1400 = OPERAND_TYPE_INOUTPORTREG
;
1401 static const i386_operand_type reg16_inoutportreg
1402 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1403 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1404 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1405 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1406 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1407 static const i386_operand_type anydisp
1408 = OPERAND_TYPE_ANYDISP
;
1409 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1410 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1411 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1412 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1413 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1414 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1415 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1416 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1417 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1418 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1419 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1430 operand_type_check (i386_operand_type t
, enum operand_type c
)
1435 return (t
.bitfield
.reg8
1438 || t
.bitfield
.reg64
);
1441 return (t
.bitfield
.imm8
1445 || t
.bitfield
.imm32s
1446 || t
.bitfield
.imm64
);
1449 return (t
.bitfield
.disp8
1450 || t
.bitfield
.disp16
1451 || t
.bitfield
.disp32
1452 || t
.bitfield
.disp32s
1453 || t
.bitfield
.disp64
);
1456 return (t
.bitfield
.disp8
1457 || t
.bitfield
.disp16
1458 || t
.bitfield
.disp32
1459 || t
.bitfield
.disp32s
1460 || t
.bitfield
.disp64
1461 || t
.bitfield
.baseindex
);
1470 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1471 operand J for instruction template T. */
1474 match_reg_size (const insn_template
*t
, unsigned int j
)
1476 return !((i
.types
[j
].bitfield
.byte
1477 && !t
->operand_types
[j
].bitfield
.byte
)
1478 || (i
.types
[j
].bitfield
.word
1479 && !t
->operand_types
[j
].bitfield
.word
)
1480 || (i
.types
[j
].bitfield
.dword
1481 && !t
->operand_types
[j
].bitfield
.dword
)
1482 || (i
.types
[j
].bitfield
.qword
1483 && !t
->operand_types
[j
].bitfield
.qword
));
1486 /* Return 1 if there is no conflict in any size on operand J for
1487 instruction template T. */
1490 match_mem_size (const insn_template
*t
, unsigned int j
)
1492 return (match_reg_size (t
, j
)
1493 && !((i
.types
[j
].bitfield
.unspecified
1494 && !t
->operand_types
[j
].bitfield
.unspecified
)
1495 || (i
.types
[j
].bitfield
.fword
1496 && !t
->operand_types
[j
].bitfield
.fword
)
1497 || (i
.types
[j
].bitfield
.tbyte
1498 && !t
->operand_types
[j
].bitfield
.tbyte
)
1499 || (i
.types
[j
].bitfield
.xmmword
1500 && !t
->operand_types
[j
].bitfield
.xmmword
)
1501 || (i
.types
[j
].bitfield
.ymmword
1502 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1505 /* Return 1 if there is no size conflict on any operands for
1506 instruction template T. */
1509 operand_size_match (const insn_template
*t
)
1514 /* Don't check jump instructions. */
1515 if (t
->opcode_modifier
.jump
1516 || t
->opcode_modifier
.jumpbyte
1517 || t
->opcode_modifier
.jumpdword
1518 || t
->opcode_modifier
.jumpintersegment
)
1521 /* Check memory and accumulator operand size. */
1522 for (j
= 0; j
< i
.operands
; j
++)
1524 if (t
->operand_types
[j
].bitfield
.anysize
)
1527 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1533 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1541 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1544 /* Check reverse. */
1545 gas_assert (i
.operands
== 2);
1548 for (j
= 0; j
< 2; j
++)
1550 if (t
->operand_types
[j
].bitfield
.acc
1551 && !match_reg_size (t
, j
? 0 : 1))
1557 if (i
.types
[j
].bitfield
.mem
1558 && !match_mem_size (t
, j
? 0 : 1))
1569 operand_type_match (i386_operand_type overlap
,
1570 i386_operand_type given
)
1572 i386_operand_type temp
= overlap
;
1574 temp
.bitfield
.jumpabsolute
= 0;
1575 temp
.bitfield
.unspecified
= 0;
1576 temp
.bitfield
.byte
= 0;
1577 temp
.bitfield
.word
= 0;
1578 temp
.bitfield
.dword
= 0;
1579 temp
.bitfield
.fword
= 0;
1580 temp
.bitfield
.qword
= 0;
1581 temp
.bitfield
.tbyte
= 0;
1582 temp
.bitfield
.xmmword
= 0;
1583 temp
.bitfield
.ymmword
= 0;
1584 if (operand_type_all_zero (&temp
))
1587 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1588 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1591 /* If given types g0 and g1 are registers they must be of the same type
1592 unless the expected operand type register overlap is null.
1593 Note that Acc in a template matches every size of reg. */
1596 operand_type_register_match (i386_operand_type m0
,
1597 i386_operand_type g0
,
1598 i386_operand_type t0
,
1599 i386_operand_type m1
,
1600 i386_operand_type g1
,
1601 i386_operand_type t1
)
1603 if (!operand_type_check (g0
, reg
))
1606 if (!operand_type_check (g1
, reg
))
1609 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1610 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1611 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1612 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1615 if (m0
.bitfield
.acc
)
1617 t0
.bitfield
.reg8
= 1;
1618 t0
.bitfield
.reg16
= 1;
1619 t0
.bitfield
.reg32
= 1;
1620 t0
.bitfield
.reg64
= 1;
1623 if (m1
.bitfield
.acc
)
1625 t1
.bitfield
.reg8
= 1;
1626 t1
.bitfield
.reg16
= 1;
1627 t1
.bitfield
.reg32
= 1;
1628 t1
.bitfield
.reg64
= 1;
1631 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1632 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1633 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1634 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1637 static INLINE
unsigned int
1638 mode_from_disp_size (i386_operand_type t
)
1640 if (t
.bitfield
.disp8
)
1642 else if (t
.bitfield
.disp16
1643 || t
.bitfield
.disp32
1644 || t
.bitfield
.disp32s
)
1651 fits_in_signed_byte (offsetT num
)
1653 return (num
>= -128) && (num
<= 127);
1657 fits_in_unsigned_byte (offsetT num
)
1659 return (num
& 0xff) == num
;
1663 fits_in_unsigned_word (offsetT num
)
1665 return (num
& 0xffff) == num
;
1669 fits_in_signed_word (offsetT num
)
1671 return (-32768 <= num
) && (num
<= 32767);
1675 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1680 return (!(((offsetT
) -1 << 31) & num
)
1681 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1683 } /* fits_in_signed_long() */
1686 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1691 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1693 } /* fits_in_unsigned_long() */
1695 static i386_operand_type
1696 smallest_imm_type (offsetT num
)
1698 i386_operand_type t
;
1700 operand_type_set (&t
, 0);
1701 t
.bitfield
.imm64
= 1;
1703 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1705 /* This code is disabled on the 486 because all the Imm1 forms
1706 in the opcode table are slower on the i486. They're the
1707 versions with the implicitly specified single-position
1708 displacement, which has another syntax if you really want to
1710 t
.bitfield
.imm1
= 1;
1711 t
.bitfield
.imm8
= 1;
1712 t
.bitfield
.imm8s
= 1;
1713 t
.bitfield
.imm16
= 1;
1714 t
.bitfield
.imm32
= 1;
1715 t
.bitfield
.imm32s
= 1;
1717 else if (fits_in_signed_byte (num
))
1719 t
.bitfield
.imm8
= 1;
1720 t
.bitfield
.imm8s
= 1;
1721 t
.bitfield
.imm16
= 1;
1722 t
.bitfield
.imm32
= 1;
1723 t
.bitfield
.imm32s
= 1;
1725 else if (fits_in_unsigned_byte (num
))
1727 t
.bitfield
.imm8
= 1;
1728 t
.bitfield
.imm16
= 1;
1729 t
.bitfield
.imm32
= 1;
1730 t
.bitfield
.imm32s
= 1;
1732 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1734 t
.bitfield
.imm16
= 1;
1735 t
.bitfield
.imm32
= 1;
1736 t
.bitfield
.imm32s
= 1;
1738 else if (fits_in_signed_long (num
))
1740 t
.bitfield
.imm32
= 1;
1741 t
.bitfield
.imm32s
= 1;
1743 else if (fits_in_unsigned_long (num
))
1744 t
.bitfield
.imm32
= 1;
1750 offset_in_range (offsetT val
, int size
)
1756 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1757 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1758 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1760 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1766 /* If BFD64, sign extend val for 32bit address mode. */
1767 if (flag_code
!= CODE_64BIT
1768 || i
.prefix
[ADDR_PREFIX
])
1769 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1770 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1773 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1775 char buf1
[40], buf2
[40];
1777 sprint_value (buf1
, val
);
1778 sprint_value (buf2
, val
& mask
);
1779 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1784 /* Returns 0 if attempting to add a prefix where one from the same
1785 class already exists, 1 if non rep/repne added, 2 if rep/repne
1788 add_prefix (unsigned int prefix
)
1793 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1794 && flag_code
== CODE_64BIT
)
1796 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1797 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1798 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1809 case CS_PREFIX_OPCODE
:
1810 case DS_PREFIX_OPCODE
:
1811 case ES_PREFIX_OPCODE
:
1812 case FS_PREFIX_OPCODE
:
1813 case GS_PREFIX_OPCODE
:
1814 case SS_PREFIX_OPCODE
:
1818 case REPNE_PREFIX_OPCODE
:
1819 case REPE_PREFIX_OPCODE
:
1822 case LOCK_PREFIX_OPCODE
:
1830 case ADDR_PREFIX_OPCODE
:
1834 case DATA_PREFIX_OPCODE
:
1838 if (i
.prefix
[q
] != 0)
1846 i
.prefix
[q
] |= prefix
;
1849 as_bad (_("same type of prefix used twice"));
1855 set_code_flag (int value
)
1857 flag_code
= (enum flag_code
) value
;
1858 if (flag_code
== CODE_64BIT
)
1860 cpu_arch_flags
.bitfield
.cpu64
= 1;
1861 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1865 cpu_arch_flags
.bitfield
.cpu64
= 0;
1866 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1868 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1870 as_bad (_("64bit mode not supported on this CPU."));
1872 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1874 as_bad (_("32bit mode not supported on this CPU."));
1876 stackop_size
= '\0';
1880 set_16bit_gcc_code_flag (int new_code_flag
)
1882 flag_code
= (enum flag_code
) new_code_flag
;
1883 if (flag_code
!= CODE_16BIT
)
1885 cpu_arch_flags
.bitfield
.cpu64
= 0;
1886 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1887 stackop_size
= LONG_MNEM_SUFFIX
;
1891 set_intel_syntax (int syntax_flag
)
1893 /* Find out if register prefixing is specified. */
1894 int ask_naked_reg
= 0;
1897 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1899 char *string
= input_line_pointer
;
1900 int e
= get_symbol_end ();
1902 if (strcmp (string
, "prefix") == 0)
1904 else if (strcmp (string
, "noprefix") == 0)
1907 as_bad (_("bad argument to syntax directive."));
1908 *input_line_pointer
= e
;
1910 demand_empty_rest_of_line ();
1912 intel_syntax
= syntax_flag
;
1914 if (ask_naked_reg
== 0)
1915 allow_naked_reg
= (intel_syntax
1916 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1918 allow_naked_reg
= (ask_naked_reg
< 0);
1920 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1922 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1923 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1924 register_prefix
= allow_naked_reg
? "" : "%";
1928 set_intel_mnemonic (int mnemonic_flag
)
1930 intel_mnemonic
= mnemonic_flag
;
1934 set_allow_index_reg (int flag
)
1936 allow_index_reg
= flag
;
1940 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1944 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1946 char *string
= input_line_pointer
;
1947 int e
= get_symbol_end ();
1949 if (strcmp (string
, "none") == 0)
1950 sse_check
= sse_check_none
;
1951 else if (strcmp (string
, "warning") == 0)
1952 sse_check
= sse_check_warning
;
1953 else if (strcmp (string
, "error") == 0)
1954 sse_check
= sse_check_error
;
1956 as_bad (_("bad argument to sse_check directive."));
1957 *input_line_pointer
= e
;
1960 as_bad (_("missing argument for sse_check directive"));
1962 demand_empty_rest_of_line ();
1966 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1967 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1970 static const char *arch
;
1972 /* Intel LIOM is only supported on ELF. */
1978 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1979 use default_arch. */
1980 arch
= cpu_arch_name
;
1982 arch
= default_arch
;
1985 /* If we are targeting Intel L1OM, we must enable it. */
1986 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
1987 || new_flag
.bitfield
.cpul1om
)
1990 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
1995 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1999 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2001 char *string
= input_line_pointer
;
2002 int e
= get_symbol_end ();
2004 i386_cpu_flags flags
;
2006 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2008 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2010 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2014 cpu_arch_name
= cpu_arch
[i
].name
;
2015 cpu_sub_arch_name
= NULL
;
2016 cpu_arch_flags
= cpu_arch
[i
].flags
;
2017 if (flag_code
== CODE_64BIT
)
2019 cpu_arch_flags
.bitfield
.cpu64
= 1;
2020 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2024 cpu_arch_flags
.bitfield
.cpu64
= 0;
2025 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2027 cpu_arch_isa
= cpu_arch
[i
].type
;
2028 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2029 if (!cpu_arch_tune_set
)
2031 cpu_arch_tune
= cpu_arch_isa
;
2032 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2037 if (strncmp (string
+ 1, "no", 2))
2038 flags
= cpu_flags_or (cpu_arch_flags
,
2041 flags
= cpu_flags_and_not (cpu_arch_flags
,
2043 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2045 if (cpu_sub_arch_name
)
2047 char *name
= cpu_sub_arch_name
;
2048 cpu_sub_arch_name
= concat (name
,
2050 (const char *) NULL
);
2054 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2055 cpu_arch_flags
= flags
;
2057 *input_line_pointer
= e
;
2058 demand_empty_rest_of_line ();
2062 if (i
>= ARRAY_SIZE (cpu_arch
))
2063 as_bad (_("no such architecture: `%s'"), string
);
2065 *input_line_pointer
= e
;
2068 as_bad (_("missing cpu architecture"));
2070 no_cond_jump_promotion
= 0;
2071 if (*input_line_pointer
== ','
2072 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2074 char *string
= ++input_line_pointer
;
2075 int e
= get_symbol_end ();
2077 if (strcmp (string
, "nojumps") == 0)
2078 no_cond_jump_promotion
= 1;
2079 else if (strcmp (string
, "jumps") == 0)
2082 as_bad (_("no such architecture modifier: `%s'"), string
);
2084 *input_line_pointer
= e
;
2087 demand_empty_rest_of_line ();
2090 enum bfd_architecture
2093 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2095 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2096 || flag_code
!= CODE_64BIT
)
2097 as_fatal (_("Intel L1OM is 64bit ELF only"));
2098 return bfd_arch_l1om
;
2101 return bfd_arch_i386
;
2107 if (!strcmp (default_arch
, "x86_64"))
2109 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2111 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2112 as_fatal (_("Intel L1OM is 64bit ELF only"));
2113 return bfd_mach_l1om
;
2116 return bfd_mach_x86_64
;
2118 else if (!strcmp (default_arch
, "i386"))
2119 return bfd_mach_i386_i386
;
2121 as_fatal (_("Unknown architecture"));
2127 const char *hash_err
;
2129 /* Initialize op_hash hash table. */
2130 op_hash
= hash_new ();
2133 const insn_template
*optab
;
2134 templates
*core_optab
;
2136 /* Setup for loop. */
2138 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2139 core_optab
->start
= optab
;
2144 if (optab
->name
== NULL
2145 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2147 /* different name --> ship out current template list;
2148 add to hash table; & begin anew. */
2149 core_optab
->end
= optab
;
2150 hash_err
= hash_insert (op_hash
,
2152 (void *) core_optab
);
2155 as_fatal (_("Internal Error: Can't hash %s: %s"),
2159 if (optab
->name
== NULL
)
2161 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2162 core_optab
->start
= optab
;
2167 /* Initialize reg_hash hash table. */
2168 reg_hash
= hash_new ();
2170 const reg_entry
*regtab
;
2171 unsigned int regtab_size
= i386_regtab_size
;
2173 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2175 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2177 as_fatal (_("Internal Error: Can't hash %s: %s"),
2183 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2188 for (c
= 0; c
< 256; c
++)
2193 mnemonic_chars
[c
] = c
;
2194 register_chars
[c
] = c
;
2195 operand_chars
[c
] = c
;
2197 else if (ISLOWER (c
))
2199 mnemonic_chars
[c
] = c
;
2200 register_chars
[c
] = c
;
2201 operand_chars
[c
] = c
;
2203 else if (ISUPPER (c
))
2205 mnemonic_chars
[c
] = TOLOWER (c
);
2206 register_chars
[c
] = mnemonic_chars
[c
];
2207 operand_chars
[c
] = c
;
2210 if (ISALPHA (c
) || ISDIGIT (c
))
2211 identifier_chars
[c
] = c
;
2214 identifier_chars
[c
] = c
;
2215 operand_chars
[c
] = c
;
2220 identifier_chars
['@'] = '@';
2223 identifier_chars
['?'] = '?';
2224 operand_chars
['?'] = '?';
2226 digit_chars
['-'] = '-';
2227 mnemonic_chars
['_'] = '_';
2228 mnemonic_chars
['-'] = '-';
2229 mnemonic_chars
['.'] = '.';
2230 identifier_chars
['_'] = '_';
2231 identifier_chars
['.'] = '.';
2233 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2234 operand_chars
[(unsigned char) *p
] = *p
;
2237 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2240 record_alignment (text_section
, 2);
2241 record_alignment (data_section
, 2);
2242 record_alignment (bss_section
, 2);
2246 if (flag_code
== CODE_64BIT
)
2248 x86_dwarf2_return_column
= 16;
2249 x86_cie_data_alignment
= -8;
2253 x86_dwarf2_return_column
= 8;
2254 x86_cie_data_alignment
= -4;
2259 i386_print_statistics (FILE *file
)
2261 hash_print_statistics (file
, "i386 opcode", op_hash
);
2262 hash_print_statistics (file
, "i386 register", reg_hash
);
2267 /* Debugging routines for md_assemble. */
2268 static void pte (insn_template
*);
2269 static void pt (i386_operand_type
);
2270 static void pe (expressionS
*);
2271 static void ps (symbolS
*);
2274 pi (char *line
, i386_insn
*x
)
2278 fprintf (stdout
, "%s: template ", line
);
2280 fprintf (stdout
, " address: base %s index %s scale %x\n",
2281 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2282 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2283 x
->log2_scale_factor
);
2284 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2285 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2286 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2287 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2288 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2289 (x
->rex
& REX_W
) != 0,
2290 (x
->rex
& REX_R
) != 0,
2291 (x
->rex
& REX_X
) != 0,
2292 (x
->rex
& REX_B
) != 0);
2293 for (i
= 0; i
< x
->operands
; i
++)
2295 fprintf (stdout
, " #%d: ", i
+ 1);
2297 fprintf (stdout
, "\n");
2298 if (x
->types
[i
].bitfield
.reg8
2299 || x
->types
[i
].bitfield
.reg16
2300 || x
->types
[i
].bitfield
.reg32
2301 || x
->types
[i
].bitfield
.reg64
2302 || x
->types
[i
].bitfield
.regmmx
2303 || x
->types
[i
].bitfield
.regxmm
2304 || x
->types
[i
].bitfield
.regymm
2305 || x
->types
[i
].bitfield
.sreg2
2306 || x
->types
[i
].bitfield
.sreg3
2307 || x
->types
[i
].bitfield
.control
2308 || x
->types
[i
].bitfield
.debug
2309 || x
->types
[i
].bitfield
.test
)
2310 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2311 if (operand_type_check (x
->types
[i
], imm
))
2313 if (operand_type_check (x
->types
[i
], disp
))
2314 pe (x
->op
[i
].disps
);
2319 pte (insn_template
*t
)
2322 fprintf (stdout
, " %d operands ", t
->operands
);
2323 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2324 if (t
->extension_opcode
!= None
)
2325 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2326 if (t
->opcode_modifier
.d
)
2327 fprintf (stdout
, "D");
2328 if (t
->opcode_modifier
.w
)
2329 fprintf (stdout
, "W");
2330 fprintf (stdout
, "\n");
2331 for (i
= 0; i
< t
->operands
; i
++)
2333 fprintf (stdout
, " #%d type ", i
+ 1);
2334 pt (t
->operand_types
[i
]);
2335 fprintf (stdout
, "\n");
2342 fprintf (stdout
, " operation %d\n", e
->X_op
);
2343 fprintf (stdout
, " add_number %ld (%lx)\n",
2344 (long) e
->X_add_number
, (long) e
->X_add_number
);
2345 if (e
->X_add_symbol
)
2347 fprintf (stdout
, " add_symbol ");
2348 ps (e
->X_add_symbol
);
2349 fprintf (stdout
, "\n");
2353 fprintf (stdout
, " op_symbol ");
2354 ps (e
->X_op_symbol
);
2355 fprintf (stdout
, "\n");
2362 fprintf (stdout
, "%s type %s%s",
2364 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2365 segment_name (S_GET_SEGMENT (s
)));
2368 static struct type_name
2370 i386_operand_type mask
;
2373 const type_names
[] =
2375 { OPERAND_TYPE_REG8
, "r8" },
2376 { OPERAND_TYPE_REG16
, "r16" },
2377 { OPERAND_TYPE_REG32
, "r32" },
2378 { OPERAND_TYPE_REG64
, "r64" },
2379 { OPERAND_TYPE_IMM8
, "i8" },
2380 { OPERAND_TYPE_IMM8
, "i8s" },
2381 { OPERAND_TYPE_IMM16
, "i16" },
2382 { OPERAND_TYPE_IMM32
, "i32" },
2383 { OPERAND_TYPE_IMM32S
, "i32s" },
2384 { OPERAND_TYPE_IMM64
, "i64" },
2385 { OPERAND_TYPE_IMM1
, "i1" },
2386 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2387 { OPERAND_TYPE_DISP8
, "d8" },
2388 { OPERAND_TYPE_DISP16
, "d16" },
2389 { OPERAND_TYPE_DISP32
, "d32" },
2390 { OPERAND_TYPE_DISP32S
, "d32s" },
2391 { OPERAND_TYPE_DISP64
, "d64" },
2392 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2393 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2394 { OPERAND_TYPE_CONTROL
, "control reg" },
2395 { OPERAND_TYPE_TEST
, "test reg" },
2396 { OPERAND_TYPE_DEBUG
, "debug reg" },
2397 { OPERAND_TYPE_FLOATREG
, "FReg" },
2398 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2399 { OPERAND_TYPE_SREG2
, "SReg2" },
2400 { OPERAND_TYPE_SREG3
, "SReg3" },
2401 { OPERAND_TYPE_ACC
, "Acc" },
2402 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2403 { OPERAND_TYPE_REGMMX
, "rMMX" },
2404 { OPERAND_TYPE_REGXMM
, "rXMM" },
2405 { OPERAND_TYPE_REGYMM
, "rYMM" },
2406 { OPERAND_TYPE_ESSEG
, "es" },
2410 pt (i386_operand_type t
)
2413 i386_operand_type a
;
2415 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2417 a
= operand_type_and (t
, type_names
[j
].mask
);
2418 if (!operand_type_all_zero (&a
))
2419 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2424 #endif /* DEBUG386 */
2426 static bfd_reloc_code_real_type
2427 reloc (unsigned int size
,
2430 bfd_reloc_code_real_type other
)
2432 if (other
!= NO_RELOC
)
2434 reloc_howto_type
*reloc
;
2439 case BFD_RELOC_X86_64_GOT32
:
2440 return BFD_RELOC_X86_64_GOT64
;
2442 case BFD_RELOC_X86_64_PLTOFF64
:
2443 return BFD_RELOC_X86_64_PLTOFF64
;
2445 case BFD_RELOC_X86_64_GOTPC32
:
2446 other
= BFD_RELOC_X86_64_GOTPC64
;
2448 case BFD_RELOC_X86_64_GOTPCREL
:
2449 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2451 case BFD_RELOC_X86_64_TPOFF32
:
2452 other
= BFD_RELOC_X86_64_TPOFF64
;
2454 case BFD_RELOC_X86_64_DTPOFF32
:
2455 other
= BFD_RELOC_X86_64_DTPOFF64
;
2461 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2462 if (size
== 4 && flag_code
!= CODE_64BIT
)
2465 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2467 as_bad (_("unknown relocation (%u)"), other
);
2468 else if (size
!= bfd_get_reloc_size (reloc
))
2469 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2470 bfd_get_reloc_size (reloc
),
2472 else if (pcrel
&& !reloc
->pc_relative
)
2473 as_bad (_("non-pc-relative relocation for pc-relative field"));
2474 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2476 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2478 as_bad (_("relocated field and relocation type differ in signedness"));
2487 as_bad (_("there are no unsigned pc-relative relocations"));
2490 case 1: return BFD_RELOC_8_PCREL
;
2491 case 2: return BFD_RELOC_16_PCREL
;
2492 case 4: return BFD_RELOC_32_PCREL
;
2493 case 8: return BFD_RELOC_64_PCREL
;
2495 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2502 case 4: return BFD_RELOC_X86_64_32S
;
2507 case 1: return BFD_RELOC_8
;
2508 case 2: return BFD_RELOC_16
;
2509 case 4: return BFD_RELOC_32
;
2510 case 8: return BFD_RELOC_64
;
2512 as_bad (_("cannot do %s %u byte relocation"),
2513 sign
> 0 ? "signed" : "unsigned", size
);
2519 /* Here we decide which fixups can be adjusted to make them relative to
2520 the beginning of the section instead of the symbol. Basically we need
2521 to make sure that the dynamic relocations are done correctly, so in
2522 some cases we force the original symbol to be used. */
2525 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2531 /* Don't adjust pc-relative references to merge sections in 64-bit
2533 if (use_rela_relocations
2534 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2538 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2539 and changed later by validate_fix. */
2540 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2541 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2544 /* adjust_reloc_syms doesn't know about the GOT. */
2545 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2546 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2547 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2548 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2549 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2550 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2551 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2552 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2553 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2554 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2555 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2556 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2557 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2558 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2559 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2560 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2561 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2562 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2563 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2564 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2565 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2566 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2567 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2568 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2569 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2570 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2571 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2572 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2579 intel_float_operand (const char *mnemonic
)
2581 /* Note that the value returned is meaningful only for opcodes with (memory)
2582 operands, hence the code here is free to improperly handle opcodes that
2583 have no operands (for better performance and smaller code). */
2585 if (mnemonic
[0] != 'f')
2586 return 0; /* non-math */
2588 switch (mnemonic
[1])
2590 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2591 the fs segment override prefix not currently handled because no
2592 call path can make opcodes without operands get here */
2594 return 2 /* integer op */;
2596 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2597 return 3; /* fldcw/fldenv */
2600 if (mnemonic
[2] != 'o' /* fnop */)
2601 return 3; /* non-waiting control op */
2604 if (mnemonic
[2] == 's')
2605 return 3; /* frstor/frstpm */
2608 if (mnemonic
[2] == 'a')
2609 return 3; /* fsave */
2610 if (mnemonic
[2] == 't')
2612 switch (mnemonic
[3])
2614 case 'c': /* fstcw */
2615 case 'd': /* fstdw */
2616 case 'e': /* fstenv */
2617 case 's': /* fsts[gw] */
2623 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2624 return 0; /* fxsave/fxrstor are not really math ops */
2631 /* Build the VEX prefix. */
2634 build_vex_prefix (const insn_template
*t
)
2636 unsigned int register_specifier
;
2637 unsigned int implied_prefix
;
2638 unsigned int vector_length
;
2640 /* Check register specifier. */
2641 if (i
.vex
.register_specifier
)
2643 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2644 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2645 register_specifier
+= 8;
2646 register_specifier
= ~register_specifier
& 0xf;
2649 register_specifier
= 0xf;
2651 /* Use 2-byte VEX prefix by swappping destination and source
2654 && i
.operands
== i
.reg_operands
2655 && i
.tm
.opcode_modifier
.vex0f
2656 && i
.tm
.opcode_modifier
.s
2659 unsigned int xchg
= i
.operands
- 1;
2660 union i386_op temp_op
;
2661 i386_operand_type temp_type
;
2663 temp_type
= i
.types
[xchg
];
2664 i
.types
[xchg
] = i
.types
[0];
2665 i
.types
[0] = temp_type
;
2666 temp_op
= i
.op
[xchg
];
2667 i
.op
[xchg
] = i
.op
[0];
2670 gas_assert (i
.rm
.mode
== 3);
2674 i
.rm
.regmem
= i
.rm
.reg
;
2677 /* Use the next insn. */
2681 vector_length
= i
.tm
.opcode_modifier
.vex
== 2 ? 1 : 0;
2683 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2688 case DATA_PREFIX_OPCODE
:
2691 case REPE_PREFIX_OPCODE
:
2694 case REPNE_PREFIX_OPCODE
:
2701 /* Use 2-byte VEX prefix if possible. */
2702 if (i
.tm
.opcode_modifier
.vex0f
2703 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2705 /* 2-byte VEX prefix. */
2709 i
.vex
.bytes
[0] = 0xc5;
2711 /* Check the REX.R bit. */
2712 r
= (i
.rex
& REX_R
) ? 0 : 1;
2713 i
.vex
.bytes
[1] = (r
<< 7
2714 | register_specifier
<< 3
2715 | vector_length
<< 2
2720 /* 3-byte VEX prefix. */
2723 if (i
.tm
.opcode_modifier
.vex0f
)
2725 else if (i
.tm
.opcode_modifier
.vex0f38
)
2727 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2733 i
.vex
.bytes
[0] = 0xc4;
2735 /* The high 3 bits of the second VEX byte are 1's compliment
2736 of RXB bits from REX. */
2737 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2739 /* Check the REX.W bit. */
2740 w
= (i
.rex
& REX_W
) ? 1 : 0;
2741 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2746 if (i
.tm
.opcode_modifier
.vexw1
)
2750 i
.vex
.bytes
[2] = (w
<< 7
2751 | register_specifier
<< 3
2752 | vector_length
<< 2
2758 process_immext (void)
2762 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2764 /* SSE3 Instructions have the fixed operands with an opcode
2765 suffix which is coded in the same place as an 8-bit immediate
2766 field would be. Here we check those operands and remove them
2770 for (x
= 0; x
< i
.operands
; x
++)
2771 if (i
.op
[x
].regs
->reg_num
!= x
)
2772 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2773 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2779 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2780 which is coded in the same place as an 8-bit immediate field
2781 would be. Here we fake an 8-bit immediate operand from the
2782 opcode suffix stored in tm.extension_opcode.
2784 AVX instructions also use this encoding, for some of
2785 3 argument instructions. */
2787 gas_assert (i
.imm_operands
== 0
2789 || (i
.tm
.opcode_modifier
.vex
2790 && i
.operands
<= 4)));
2792 exp
= &im_expressions
[i
.imm_operands
++];
2793 i
.op
[i
.operands
].imms
= exp
;
2794 i
.types
[i
.operands
] = imm8
;
2796 exp
->X_op
= O_constant
;
2797 exp
->X_add_number
= i
.tm
.extension_opcode
;
2798 i
.tm
.extension_opcode
= None
;
2801 /* This is the guts of the machine-dependent assembler. LINE points to a
2802 machine dependent instruction. This function is supposed to emit
2803 the frags/bytes it assembles to. */
2806 md_assemble (char *line
)
2809 char mnemonic
[MAX_MNEM_SIZE
];
2810 const insn_template
*t
;
2812 /* Initialize globals. */
2813 memset (&i
, '\0', sizeof (i
));
2814 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2815 i
.reloc
[j
] = NO_RELOC
;
2816 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2817 memset (im_expressions
, '\0', sizeof (im_expressions
));
2818 save_stack_p
= save_stack
;
2820 /* First parse an instruction mnemonic & call i386_operand for the operands.
2821 We assume that the scrubber has arranged it so that line[0] is the valid
2822 start of a (possibly prefixed) mnemonic. */
2824 line
= parse_insn (line
, mnemonic
);
2828 line
= parse_operands (line
, mnemonic
);
2833 /* Now we've parsed the mnemonic into a set of templates, and have the
2834 operands at hand. */
2836 /* All intel opcodes have reversed operands except for "bound" and
2837 "enter". We also don't reverse intersegment "jmp" and "call"
2838 instructions with 2 immediate operands so that the immediate segment
2839 precedes the offset, as it does when in AT&T mode. */
2842 && (strcmp (mnemonic
, "bound") != 0)
2843 && (strcmp (mnemonic
, "invlpga") != 0)
2844 && !(operand_type_check (i
.types
[0], imm
)
2845 && operand_type_check (i
.types
[1], imm
)))
2848 /* The order of the immediates should be reversed
2849 for 2 immediates extrq and insertq instructions */
2850 if (i
.imm_operands
== 2
2851 && (strcmp (mnemonic
, "extrq") == 0
2852 || strcmp (mnemonic
, "insertq") == 0))
2853 swap_2_operands (0, 1);
2858 /* Don't optimize displacement for movabs since it only takes 64bit
2861 && (flag_code
!= CODE_64BIT
2862 || strcmp (mnemonic
, "movabs") != 0))
2865 /* Next, we find a template that matches the given insn,
2866 making sure the overlap of the given operands types is consistent
2867 with the template operand types. */
2869 if (!(t
= match_template ()))
2872 if (sse_check
!= sse_check_none
2873 && !i
.tm
.opcode_modifier
.noavx
2874 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2875 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2876 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2877 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2878 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2879 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2881 (sse_check
== sse_check_warning
2883 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2886 /* Zap movzx and movsx suffix. The suffix has been set from
2887 "word ptr" or "byte ptr" on the source operand in Intel syntax
2888 or extracted from mnemonic in AT&T syntax. But we'll use
2889 the destination register to choose the suffix for encoding. */
2890 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2892 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2893 there is no suffix, the default will be byte extension. */
2894 if (i
.reg_operands
!= 2
2897 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2902 if (i
.tm
.opcode_modifier
.fwait
)
2903 if (!add_prefix (FWAIT_OPCODE
))
2906 /* Check string instruction segment overrides. */
2907 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2909 if (!check_string ())
2911 i
.disp_operands
= 0;
2914 if (!process_suffix ())
2917 /* Update operand types. */
2918 for (j
= 0; j
< i
.operands
; j
++)
2919 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2921 /* Make still unresolved immediate matches conform to size of immediate
2922 given in i.suffix. */
2923 if (!finalize_imm ())
2926 if (i
.types
[0].bitfield
.imm1
)
2927 i
.imm_operands
= 0; /* kludge for shift insns. */
2929 /* We only need to check those implicit registers for instructions
2930 with 3 operands or less. */
2931 if (i
.operands
<= 3)
2932 for (j
= 0; j
< i
.operands
; j
++)
2933 if (i
.types
[j
].bitfield
.inoutportreg
2934 || i
.types
[j
].bitfield
.shiftcount
2935 || i
.types
[j
].bitfield
.acc
2936 || i
.types
[j
].bitfield
.floatacc
)
2939 /* ImmExt should be processed after SSE2AVX. */
2940 if (!i
.tm
.opcode_modifier
.sse2avx
2941 && i
.tm
.opcode_modifier
.immext
)
2944 /* For insns with operands there are more diddles to do to the opcode. */
2947 if (!process_operands ())
2950 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2952 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2953 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2956 if (i
.tm
.opcode_modifier
.vex
)
2957 build_vex_prefix (t
);
2959 /* Handle conversion of 'int $3' --> special int3 insn. */
2960 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2962 i
.tm
.base_opcode
= INT3_OPCODE
;
2966 if ((i
.tm
.opcode_modifier
.jump
2967 || i
.tm
.opcode_modifier
.jumpbyte
2968 || i
.tm
.opcode_modifier
.jumpdword
)
2969 && i
.op
[0].disps
->X_op
== O_constant
)
2971 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2972 the absolute address given by the constant. Since ix86 jumps and
2973 calls are pc relative, we need to generate a reloc. */
2974 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2975 i
.op
[0].disps
->X_op
= O_symbol
;
2978 if (i
.tm
.opcode_modifier
.rex64
)
2981 /* For 8 bit registers we need an empty rex prefix. Also if the
2982 instruction already has a prefix, we need to convert old
2983 registers to new ones. */
2985 if ((i
.types
[0].bitfield
.reg8
2986 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2987 || (i
.types
[1].bitfield
.reg8
2988 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2989 || ((i
.types
[0].bitfield
.reg8
2990 || i
.types
[1].bitfield
.reg8
)
2995 i
.rex
|= REX_OPCODE
;
2996 for (x
= 0; x
< 2; x
++)
2998 /* Look for 8 bit operand that uses old registers. */
2999 if (i
.types
[x
].bitfield
.reg8
3000 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3002 /* In case it is "hi" register, give up. */
3003 if (i
.op
[x
].regs
->reg_num
> 3)
3004 as_bad (_("can't encode register '%s%s' in an "
3005 "instruction requiring REX prefix."),
3006 register_prefix
, i
.op
[x
].regs
->reg_name
);
3008 /* Otherwise it is equivalent to the extended register.
3009 Since the encoding doesn't change this is merely
3010 cosmetic cleanup for debug output. */
3012 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3018 add_prefix (REX_OPCODE
| i
.rex
);
3020 /* We are ready to output the insn. */
3025 parse_insn (char *line
, char *mnemonic
)
3028 char *token_start
= l
;
3031 const insn_template
*t
;
3034 /* Non-zero if we found a prefix only acceptable with string insns. */
3035 const char *expecting_string_instruction
= NULL
;
3040 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3045 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3047 as_bad (_("no such instruction: `%s'"), token_start
);
3052 if (!is_space_char (*l
)
3053 && *l
!= END_OF_INSN
3055 || (*l
!= PREFIX_SEPARATOR
3058 as_bad (_("invalid character %s in mnemonic"),
3059 output_invalid (*l
));
3062 if (token_start
== l
)
3064 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3065 as_bad (_("expecting prefix; got nothing"));
3067 as_bad (_("expecting mnemonic; got nothing"));
3071 /* Look up instruction (or prefix) via hash table. */
3072 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3074 if (*l
!= END_OF_INSN
3075 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3076 && current_templates
3077 && current_templates
->start
->opcode_modifier
.isprefix
)
3079 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3081 as_bad ((flag_code
!= CODE_64BIT
3082 ? _("`%s' is only supported in 64-bit mode")
3083 : _("`%s' is not supported in 64-bit mode")),
3084 current_templates
->start
->name
);
3087 /* If we are in 16-bit mode, do not allow addr16 or data16.
3088 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3089 if ((current_templates
->start
->opcode_modifier
.size16
3090 || current_templates
->start
->opcode_modifier
.size32
)
3091 && flag_code
!= CODE_64BIT
3092 && (current_templates
->start
->opcode_modifier
.size32
3093 ^ (flag_code
== CODE_16BIT
)))
3095 as_bad (_("redundant %s prefix"),
3096 current_templates
->start
->name
);
3099 /* Add prefix, checking for repeated prefixes. */
3100 switch (add_prefix (current_templates
->start
->base_opcode
))
3105 expecting_string_instruction
= current_templates
->start
->name
;
3108 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3115 if (!current_templates
)
3117 /* Check if we should swap operand in encoding. */
3118 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3124 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3127 if (!current_templates
)
3130 /* See if we can get a match by trimming off a suffix. */
3133 case WORD_MNEM_SUFFIX
:
3134 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3135 i
.suffix
= SHORT_MNEM_SUFFIX
;
3137 case BYTE_MNEM_SUFFIX
:
3138 case QWORD_MNEM_SUFFIX
:
3139 i
.suffix
= mnem_p
[-1];
3141 current_templates
= (const templates
*) hash_find (op_hash
,
3144 case SHORT_MNEM_SUFFIX
:
3145 case LONG_MNEM_SUFFIX
:
3148 i
.suffix
= mnem_p
[-1];
3150 current_templates
= (const templates
*) hash_find (op_hash
,
3159 if (intel_float_operand (mnemonic
) == 1)
3160 i
.suffix
= SHORT_MNEM_SUFFIX
;
3162 i
.suffix
= LONG_MNEM_SUFFIX
;
3164 current_templates
= (const templates
*) hash_find (op_hash
,
3169 if (!current_templates
)
3171 as_bad (_("no such instruction: `%s'"), token_start
);
3176 if (current_templates
->start
->opcode_modifier
.jump
3177 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3179 /* Check for a branch hint. We allow ",pt" and ",pn" for
3180 predict taken and predict not taken respectively.
3181 I'm not sure that branch hints actually do anything on loop
3182 and jcxz insns (JumpByte) for current Pentium4 chips. They
3183 may work in the future and it doesn't hurt to accept them
3185 if (l
[0] == ',' && l
[1] == 'p')
3189 if (!add_prefix (DS_PREFIX_OPCODE
))
3193 else if (l
[2] == 'n')
3195 if (!add_prefix (CS_PREFIX_OPCODE
))
3201 /* Any other comma loses. */
3204 as_bad (_("invalid character %s in mnemonic"),
3205 output_invalid (*l
));
3209 /* Check if instruction is supported on specified architecture. */
3211 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3213 supported
|= cpu_flags_match (t
);
3214 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3218 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3220 as_bad (flag_code
== CODE_64BIT
3221 ? _("`%s' is not supported in 64-bit mode")
3222 : _("`%s' is only supported in 64-bit mode"),
3223 current_templates
->start
->name
);
3226 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3228 as_bad (_("`%s' is not supported on `%s%s'"),
3229 current_templates
->start
->name
,
3230 cpu_arch_name
? cpu_arch_name
: default_arch
,
3231 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3236 if (!cpu_arch_flags
.bitfield
.cpui386
3237 && (flag_code
!= CODE_16BIT
))
3239 as_warn (_("use .code16 to ensure correct addressing mode"));
3242 /* Check for rep/repne without a string instruction. */
3243 if (expecting_string_instruction
)
3245 static templates override
;
3247 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3248 if (t
->opcode_modifier
.isstring
)
3250 if (t
>= current_templates
->end
)
3252 as_bad (_("expecting string instruction after `%s'"),
3253 expecting_string_instruction
);
3256 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3257 if (!t
->opcode_modifier
.isstring
)
3260 current_templates
= &override
;
3267 parse_operands (char *l
, const char *mnemonic
)
3271 /* 1 if operand is pending after ','. */
3272 unsigned int expecting_operand
= 0;
3274 /* Non-zero if operand parens not balanced. */
3275 unsigned int paren_not_balanced
;
3277 while (*l
!= END_OF_INSN
)
3279 /* Skip optional white space before operand. */
3280 if (is_space_char (*l
))
3282 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3284 as_bad (_("invalid character %s before operand %d"),
3285 output_invalid (*l
),
3289 token_start
= l
; /* after white space */
3290 paren_not_balanced
= 0;
3291 while (paren_not_balanced
|| *l
!= ',')
3293 if (*l
== END_OF_INSN
)
3295 if (paren_not_balanced
)
3298 as_bad (_("unbalanced parenthesis in operand %d."),
3301 as_bad (_("unbalanced brackets in operand %d."),
3306 break; /* we are done */
3308 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3310 as_bad (_("invalid character %s in operand %d"),
3311 output_invalid (*l
),
3318 ++paren_not_balanced
;
3320 --paren_not_balanced
;
3325 ++paren_not_balanced
;
3327 --paren_not_balanced
;
3331 if (l
!= token_start
)
3332 { /* Yes, we've read in another operand. */
3333 unsigned int operand_ok
;
3334 this_operand
= i
.operands
++;
3335 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3336 if (i
.operands
> MAX_OPERANDS
)
3338 as_bad (_("spurious operands; (%d operands/instruction max)"),
3342 /* Now parse operand adding info to 'i' as we go along. */
3343 END_STRING_AND_SAVE (l
);
3347 i386_intel_operand (token_start
,
3348 intel_float_operand (mnemonic
));
3350 operand_ok
= i386_att_operand (token_start
);
3352 RESTORE_END_STRING (l
);
3358 if (expecting_operand
)
3360 expecting_operand_after_comma
:
3361 as_bad (_("expecting operand after ','; got nothing"));
3366 as_bad (_("expecting operand before ','; got nothing"));
3371 /* Now *l must be either ',' or END_OF_INSN. */
3374 if (*++l
== END_OF_INSN
)
3376 /* Just skip it, if it's \n complain. */
3377 goto expecting_operand_after_comma
;
3379 expecting_operand
= 1;
3386 swap_2_operands (int xchg1
, int xchg2
)
3388 union i386_op temp_op
;
3389 i386_operand_type temp_type
;
3390 enum bfd_reloc_code_real temp_reloc
;
3392 temp_type
= i
.types
[xchg2
];
3393 i
.types
[xchg2
] = i
.types
[xchg1
];
3394 i
.types
[xchg1
] = temp_type
;
3395 temp_op
= i
.op
[xchg2
];
3396 i
.op
[xchg2
] = i
.op
[xchg1
];
3397 i
.op
[xchg1
] = temp_op
;
3398 temp_reloc
= i
.reloc
[xchg2
];
3399 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3400 i
.reloc
[xchg1
] = temp_reloc
;
3404 swap_operands (void)
3410 swap_2_operands (1, i
.operands
- 2);
3413 swap_2_operands (0, i
.operands
- 1);
3419 if (i
.mem_operands
== 2)
3421 const seg_entry
*temp_seg
;
3422 temp_seg
= i
.seg
[0];
3423 i
.seg
[0] = i
.seg
[1];
3424 i
.seg
[1] = temp_seg
;
3428 /* Try to ensure constant immediates are represented in the smallest
3433 char guess_suffix
= 0;
3437 guess_suffix
= i
.suffix
;
3438 else if (i
.reg_operands
)
3440 /* Figure out a suffix from the last register operand specified.
3441 We can't do this properly yet, ie. excluding InOutPortReg,
3442 but the following works for instructions with immediates.
3443 In any case, we can't set i.suffix yet. */
3444 for (op
= i
.operands
; --op
>= 0;)
3445 if (i
.types
[op
].bitfield
.reg8
)
3447 guess_suffix
= BYTE_MNEM_SUFFIX
;
3450 else if (i
.types
[op
].bitfield
.reg16
)
3452 guess_suffix
= WORD_MNEM_SUFFIX
;
3455 else if (i
.types
[op
].bitfield
.reg32
)
3457 guess_suffix
= LONG_MNEM_SUFFIX
;
3460 else if (i
.types
[op
].bitfield
.reg64
)
3462 guess_suffix
= QWORD_MNEM_SUFFIX
;
3466 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3467 guess_suffix
= WORD_MNEM_SUFFIX
;
3469 for (op
= i
.operands
; --op
>= 0;)
3470 if (operand_type_check (i
.types
[op
], imm
))
3472 switch (i
.op
[op
].imms
->X_op
)
3475 /* If a suffix is given, this operand may be shortened. */
3476 switch (guess_suffix
)
3478 case LONG_MNEM_SUFFIX
:
3479 i
.types
[op
].bitfield
.imm32
= 1;
3480 i
.types
[op
].bitfield
.imm64
= 1;
3482 case WORD_MNEM_SUFFIX
:
3483 i
.types
[op
].bitfield
.imm16
= 1;
3484 i
.types
[op
].bitfield
.imm32
= 1;
3485 i
.types
[op
].bitfield
.imm32s
= 1;
3486 i
.types
[op
].bitfield
.imm64
= 1;
3488 case BYTE_MNEM_SUFFIX
:
3489 i
.types
[op
].bitfield
.imm8
= 1;
3490 i
.types
[op
].bitfield
.imm8s
= 1;
3491 i
.types
[op
].bitfield
.imm16
= 1;
3492 i
.types
[op
].bitfield
.imm32
= 1;
3493 i
.types
[op
].bitfield
.imm32s
= 1;
3494 i
.types
[op
].bitfield
.imm64
= 1;
3498 /* If this operand is at most 16 bits, convert it
3499 to a signed 16 bit number before trying to see
3500 whether it will fit in an even smaller size.
3501 This allows a 16-bit operand such as $0xffe0 to
3502 be recognised as within Imm8S range. */
3503 if ((i
.types
[op
].bitfield
.imm16
)
3504 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3506 i
.op
[op
].imms
->X_add_number
=
3507 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3509 if ((i
.types
[op
].bitfield
.imm32
)
3510 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3513 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3514 ^ ((offsetT
) 1 << 31))
3515 - ((offsetT
) 1 << 31));
3518 = operand_type_or (i
.types
[op
],
3519 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3521 /* We must avoid matching of Imm32 templates when 64bit
3522 only immediate is available. */
3523 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3524 i
.types
[op
].bitfield
.imm32
= 0;
3531 /* Symbols and expressions. */
3533 /* Convert symbolic operand to proper sizes for matching, but don't
3534 prevent matching a set of insns that only supports sizes other
3535 than those matching the insn suffix. */
3537 i386_operand_type mask
, allowed
;
3538 const insn_template
*t
;
3540 operand_type_set (&mask
, 0);
3541 operand_type_set (&allowed
, 0);
3543 for (t
= current_templates
->start
;
3544 t
< current_templates
->end
;
3546 allowed
= operand_type_or (allowed
,
3547 t
->operand_types
[op
]);
3548 switch (guess_suffix
)
3550 case QWORD_MNEM_SUFFIX
:
3551 mask
.bitfield
.imm64
= 1;
3552 mask
.bitfield
.imm32s
= 1;
3554 case LONG_MNEM_SUFFIX
:
3555 mask
.bitfield
.imm32
= 1;
3557 case WORD_MNEM_SUFFIX
:
3558 mask
.bitfield
.imm16
= 1;
3560 case BYTE_MNEM_SUFFIX
:
3561 mask
.bitfield
.imm8
= 1;
3566 allowed
= operand_type_and (mask
, allowed
);
3567 if (!operand_type_all_zero (&allowed
))
3568 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3575 /* Try to use the smallest displacement type too. */
3577 optimize_disp (void)
3581 for (op
= i
.operands
; --op
>= 0;)
3582 if (operand_type_check (i
.types
[op
], disp
))
3584 if (i
.op
[op
].disps
->X_op
== O_constant
)
3586 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3588 if (i
.types
[op
].bitfield
.disp16
3589 && (disp
& ~(offsetT
) 0xffff) == 0)
3591 /* If this operand is at most 16 bits, convert
3592 to a signed 16 bit number and don't use 64bit
3594 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3595 i
.types
[op
].bitfield
.disp64
= 0;
3597 if (i
.types
[op
].bitfield
.disp32
3598 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3600 /* If this operand is at most 32 bits, convert
3601 to a signed 32 bit number and don't use 64bit
3603 disp
&= (((offsetT
) 2 << 31) - 1);
3604 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3605 i
.types
[op
].bitfield
.disp64
= 0;
3607 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3609 i
.types
[op
].bitfield
.disp8
= 0;
3610 i
.types
[op
].bitfield
.disp16
= 0;
3611 i
.types
[op
].bitfield
.disp32
= 0;
3612 i
.types
[op
].bitfield
.disp32s
= 0;
3613 i
.types
[op
].bitfield
.disp64
= 0;
3617 else if (flag_code
== CODE_64BIT
)
3619 if (fits_in_signed_long (disp
))
3621 i
.types
[op
].bitfield
.disp64
= 0;
3622 i
.types
[op
].bitfield
.disp32s
= 1;
3624 if (i
.prefix
[ADDR_PREFIX
]
3625 && fits_in_unsigned_long (disp
))
3626 i
.types
[op
].bitfield
.disp32
= 1;
3628 if ((i
.types
[op
].bitfield
.disp32
3629 || i
.types
[op
].bitfield
.disp32s
3630 || i
.types
[op
].bitfield
.disp16
)
3631 && fits_in_signed_byte (disp
))
3632 i
.types
[op
].bitfield
.disp8
= 1;
3634 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3635 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3637 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3638 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3639 i
.types
[op
].bitfield
.disp8
= 0;
3640 i
.types
[op
].bitfield
.disp16
= 0;
3641 i
.types
[op
].bitfield
.disp32
= 0;
3642 i
.types
[op
].bitfield
.disp32s
= 0;
3643 i
.types
[op
].bitfield
.disp64
= 0;
3646 /* We only support 64bit displacement on constants. */
3647 i
.types
[op
].bitfield
.disp64
= 0;
3651 static const insn_template
*
3652 match_template (void)
3654 /* Points to template once we've found it. */
3655 const insn_template
*t
;
3656 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3657 i386_operand_type overlap4
;
3658 unsigned int found_reverse_match
;
3659 i386_opcode_modifier suffix_check
;
3660 i386_operand_type operand_types
[MAX_OPERANDS
];
3661 int addr_prefix_disp
;
3663 unsigned int found_cpu_match
;
3664 unsigned int check_register
;
3666 #if MAX_OPERANDS != 5
3667 # error "MAX_OPERANDS must be 5."
3670 found_reverse_match
= 0;
3671 addr_prefix_disp
= -1;
3673 memset (&suffix_check
, 0, sizeof (suffix_check
));
3674 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3675 suffix_check
.no_bsuf
= 1;
3676 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3677 suffix_check
.no_wsuf
= 1;
3678 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3679 suffix_check
.no_ssuf
= 1;
3680 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3681 suffix_check
.no_lsuf
= 1;
3682 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3683 suffix_check
.no_qsuf
= 1;
3684 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3685 suffix_check
.no_ldsuf
= 1;
3687 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3689 addr_prefix_disp
= -1;
3691 /* Must have right number of operands. */
3692 if (i
.operands
!= t
->operands
)
3695 /* Check processor support. */
3696 found_cpu_match
= (cpu_flags_match (t
)
3697 == CPU_FLAGS_PERFECT_MATCH
);
3698 if (!found_cpu_match
)
3701 /* Check old gcc support. */
3702 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3705 /* Check AT&T mnemonic. */
3706 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3709 /* Check AT&T syntax Intel syntax. */
3710 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3711 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3714 /* Check the suffix, except for some instructions in intel mode. */
3715 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3716 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3717 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3718 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3719 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3720 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3721 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3724 if (!operand_size_match (t
))
3727 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3728 operand_types
[j
] = t
->operand_types
[j
];
3730 /* In general, don't allow 64-bit operands in 32-bit mode. */
3731 if (i
.suffix
== QWORD_MNEM_SUFFIX
3732 && flag_code
!= CODE_64BIT
3734 ? (!t
->opcode_modifier
.ignoresize
3735 && !intel_float_operand (t
->name
))
3736 : intel_float_operand (t
->name
) != 2)
3737 && ((!operand_types
[0].bitfield
.regmmx
3738 && !operand_types
[0].bitfield
.regxmm
3739 && !operand_types
[0].bitfield
.regymm
)
3740 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3741 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3742 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3743 && (t
->base_opcode
!= 0x0fc7
3744 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3747 /* In general, don't allow 32-bit operands on pre-386. */
3748 else if (i
.suffix
== LONG_MNEM_SUFFIX
3749 && !cpu_arch_flags
.bitfield
.cpui386
3751 ? (!t
->opcode_modifier
.ignoresize
3752 && !intel_float_operand (t
->name
))
3753 : intel_float_operand (t
->name
) != 2)
3754 && ((!operand_types
[0].bitfield
.regmmx
3755 && !operand_types
[0].bitfield
.regxmm
)
3756 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3757 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3760 /* Do not verify operands when there are none. */
3764 /* We've found a match; break out of loop. */
3768 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3769 into Disp32/Disp16/Disp32 operand. */
3770 if (i
.prefix
[ADDR_PREFIX
] != 0)
3772 /* There should be only one Disp operand. */
3776 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3778 if (operand_types
[j
].bitfield
.disp16
)
3780 addr_prefix_disp
= j
;
3781 operand_types
[j
].bitfield
.disp32
= 1;
3782 operand_types
[j
].bitfield
.disp16
= 0;
3788 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3790 if (operand_types
[j
].bitfield
.disp32
)
3792 addr_prefix_disp
= j
;
3793 operand_types
[j
].bitfield
.disp32
= 0;
3794 operand_types
[j
].bitfield
.disp16
= 1;
3800 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3802 if (operand_types
[j
].bitfield
.disp64
)
3804 addr_prefix_disp
= j
;
3805 operand_types
[j
].bitfield
.disp64
= 0;
3806 operand_types
[j
].bitfield
.disp32
= 1;
3814 /* We check register size only if size of operands can be
3815 encoded the canonical way. */
3816 check_register
= t
->opcode_modifier
.w
;
3817 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3818 switch (t
->operands
)
3821 if (!operand_type_match (overlap0
, i
.types
[0]))
3825 /* xchg %eax, %eax is a special case. It is an aliase for nop
3826 only in 32bit mode and we can use opcode 0x90. In 64bit
3827 mode, we can't use 0x90 for xchg %eax, %eax since it should
3828 zero-extend %eax to %rax. */
3829 if (flag_code
== CODE_64BIT
3830 && t
->base_opcode
== 0x90
3831 && operand_type_equal (&i
.types
[0], &acc32
)
3832 && operand_type_equal (&i
.types
[1], &acc32
))
3836 /* If we swap operand in encoding, we either match
3837 the next one or reverse direction of operands. */
3838 if (t
->opcode_modifier
.s
)
3840 else if (t
->opcode_modifier
.d
)
3845 /* If we swap operand in encoding, we match the next one. */
3846 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3850 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3851 if (!operand_type_match (overlap0
, i
.types
[0])
3852 || !operand_type_match (overlap1
, i
.types
[1])
3854 && !operand_type_register_match (overlap0
, i
.types
[0],
3856 overlap1
, i
.types
[1],
3859 /* Check if other direction is valid ... */
3860 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3864 /* Try reversing direction of operands. */
3865 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3866 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3867 if (!operand_type_match (overlap0
, i
.types
[0])
3868 || !operand_type_match (overlap1
, i
.types
[1])
3870 && !operand_type_register_match (overlap0
,
3877 /* Does not match either direction. */
3880 /* found_reverse_match holds which of D or FloatDR
3882 if (t
->opcode_modifier
.d
)
3883 found_reverse_match
= Opcode_D
;
3884 else if (t
->opcode_modifier
.floatd
)
3885 found_reverse_match
= Opcode_FloatD
;
3887 found_reverse_match
= 0;
3888 if (t
->opcode_modifier
.floatr
)
3889 found_reverse_match
|= Opcode_FloatR
;
3893 /* Found a forward 2 operand match here. */
3894 switch (t
->operands
)
3897 overlap4
= operand_type_and (i
.types
[4],
3900 overlap3
= operand_type_and (i
.types
[3],
3903 overlap2
= operand_type_and (i
.types
[2],
3908 switch (t
->operands
)
3911 if (!operand_type_match (overlap4
, i
.types
[4])
3912 || !operand_type_register_match (overlap3
,
3920 if (!operand_type_match (overlap3
, i
.types
[3])
3922 && !operand_type_register_match (overlap2
,
3930 /* Here we make use of the fact that there are no
3931 reverse match 3 operand instructions, and all 3
3932 operand instructions only need to be checked for
3933 register consistency between operands 2 and 3. */
3934 if (!operand_type_match (overlap2
, i
.types
[2])
3936 && !operand_type_register_match (overlap1
,
3946 /* Found either forward/reverse 2, 3 or 4 operand match here:
3947 slip through to break. */
3949 if (!found_cpu_match
)
3951 found_reverse_match
= 0;
3955 /* We've found a match; break out of loop. */
3959 if (t
== current_templates
->end
)
3961 /* We found no match. */
3963 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3964 current_templates
->start
->name
);
3966 as_bad (_("suffix or operands invalid for `%s'"),
3967 current_templates
->start
->name
);
3971 if (!quiet_warnings
)
3974 && (i
.types
[0].bitfield
.jumpabsolute
3975 != operand_types
[0].bitfield
.jumpabsolute
))
3977 as_warn (_("indirect %s without `*'"), t
->name
);
3980 if (t
->opcode_modifier
.isprefix
3981 && t
->opcode_modifier
.ignoresize
)
3983 /* Warn them that a data or address size prefix doesn't
3984 affect assembly of the next line of code. */
3985 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3989 /* Copy the template we found. */
3992 if (addr_prefix_disp
!= -1)
3993 i
.tm
.operand_types
[addr_prefix_disp
]
3994 = operand_types
[addr_prefix_disp
];
3996 if (found_reverse_match
)
3998 /* If we found a reverse match we must alter the opcode
3999 direction bit. found_reverse_match holds bits to change
4000 (different for int & float insns). */
4002 i
.tm
.base_opcode
^= found_reverse_match
;
4004 i
.tm
.operand_types
[0] = operand_types
[1];
4005 i
.tm
.operand_types
[1] = operand_types
[0];
4014 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4015 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4017 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4019 as_bad (_("`%s' operand %d must use `%ses' segment"),
4025 /* There's only ever one segment override allowed per instruction.
4026 This instruction possibly has a legal segment override on the
4027 second operand, so copy the segment to where non-string
4028 instructions store it, allowing common code. */
4029 i
.seg
[0] = i
.seg
[1];
4031 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4033 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4035 as_bad (_("`%s' operand %d must use `%ses' segment"),
4046 process_suffix (void)
4048 /* If matched instruction specifies an explicit instruction mnemonic
4050 if (i
.tm
.opcode_modifier
.size16
)
4051 i
.suffix
= WORD_MNEM_SUFFIX
;
4052 else if (i
.tm
.opcode_modifier
.size32
)
4053 i
.suffix
= LONG_MNEM_SUFFIX
;
4054 else if (i
.tm
.opcode_modifier
.size64
)
4055 i
.suffix
= QWORD_MNEM_SUFFIX
;
4056 else if (i
.reg_operands
)
4058 /* If there's no instruction mnemonic suffix we try to invent one
4059 based on register operands. */
4062 /* We take i.suffix from the last register operand specified,
4063 Destination register type is more significant than source
4064 register type. crc32 in SSE4.2 prefers source register
4066 if (i
.tm
.base_opcode
== 0xf20f38f1)
4068 if (i
.types
[0].bitfield
.reg16
)
4069 i
.suffix
= WORD_MNEM_SUFFIX
;
4070 else if (i
.types
[0].bitfield
.reg32
)
4071 i
.suffix
= LONG_MNEM_SUFFIX
;
4072 else if (i
.types
[0].bitfield
.reg64
)
4073 i
.suffix
= QWORD_MNEM_SUFFIX
;
4075 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4077 if (i
.types
[0].bitfield
.reg8
)
4078 i
.suffix
= BYTE_MNEM_SUFFIX
;
4085 if (i
.tm
.base_opcode
== 0xf20f38f1
4086 || i
.tm
.base_opcode
== 0xf20f38f0)
4088 /* We have to know the operand size for crc32. */
4089 as_bad (_("ambiguous memory operand size for `%s`"),
4094 for (op
= i
.operands
; --op
>= 0;)
4095 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4097 if (i
.types
[op
].bitfield
.reg8
)
4099 i
.suffix
= BYTE_MNEM_SUFFIX
;
4102 else if (i
.types
[op
].bitfield
.reg16
)
4104 i
.suffix
= WORD_MNEM_SUFFIX
;
4107 else if (i
.types
[op
].bitfield
.reg32
)
4109 i
.suffix
= LONG_MNEM_SUFFIX
;
4112 else if (i
.types
[op
].bitfield
.reg64
)
4114 i
.suffix
= QWORD_MNEM_SUFFIX
;
4120 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4122 if (!check_byte_reg ())
4125 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4127 if (!check_long_reg ())
4130 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4133 && i
.tm
.opcode_modifier
.ignoresize
4134 && i
.tm
.opcode_modifier
.no_qsuf
)
4136 else if (!check_qword_reg ())
4139 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4141 if (!check_word_reg ())
4144 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4145 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4147 /* Skip if the instruction has x/y suffix. match_template
4148 should check if it is a valid suffix. */
4150 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4151 /* Do nothing if the instruction is going to ignore the prefix. */
4156 else if (i
.tm
.opcode_modifier
.defaultsize
4158 /* exclude fldenv/frstor/fsave/fstenv */
4159 && i
.tm
.opcode_modifier
.no_ssuf
)
4161 i
.suffix
= stackop_size
;
4163 else if (intel_syntax
4165 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4166 || i
.tm
.opcode_modifier
.jumpbyte
4167 || i
.tm
.opcode_modifier
.jumpintersegment
4168 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4169 && i
.tm
.extension_opcode
<= 3)))
4174 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4176 i
.suffix
= QWORD_MNEM_SUFFIX
;
4180 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4181 i
.suffix
= LONG_MNEM_SUFFIX
;
4184 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4185 i
.suffix
= WORD_MNEM_SUFFIX
;
4194 if (i
.tm
.opcode_modifier
.w
)
4196 as_bad (_("no instruction mnemonic suffix given and "
4197 "no register operands; can't size instruction"));
4203 unsigned int suffixes
;
4205 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4206 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4208 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4210 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4212 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4214 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4217 /* There are more than suffix matches. */
4218 if (i
.tm
.opcode_modifier
.w
4219 || ((suffixes
& (suffixes
- 1))
4220 && !i
.tm
.opcode_modifier
.defaultsize
4221 && !i
.tm
.opcode_modifier
.ignoresize
))
4223 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4229 /* Change the opcode based on the operand size given by i.suffix;
4230 We don't need to change things for byte insns. */
4233 && i
.suffix
!= BYTE_MNEM_SUFFIX
4234 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4235 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4237 /* It's not a byte, select word/dword operation. */
4238 if (i
.tm
.opcode_modifier
.w
)
4240 if (i
.tm
.opcode_modifier
.shortform
)
4241 i
.tm
.base_opcode
|= 8;
4243 i
.tm
.base_opcode
|= 1;
4246 /* Now select between word & dword operations via the operand
4247 size prefix, except for instructions that will ignore this
4249 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4251 /* The address size override prefix changes the size of the
4253 if ((flag_code
== CODE_32BIT
4254 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4255 || (flag_code
!= CODE_32BIT
4256 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4257 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4260 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4261 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4262 && !i
.tm
.opcode_modifier
.ignoresize
4263 && !i
.tm
.opcode_modifier
.floatmf
4264 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4265 || (flag_code
== CODE_64BIT
4266 && i
.tm
.opcode_modifier
.jumpbyte
)))
4268 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4270 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4271 prefix
= ADDR_PREFIX_OPCODE
;
4273 if (!add_prefix (prefix
))
4277 /* Set mode64 for an operand. */
4278 if (i
.suffix
== QWORD_MNEM_SUFFIX
4279 && flag_code
== CODE_64BIT
4280 && !i
.tm
.opcode_modifier
.norex64
)
4282 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4283 need rex64. cmpxchg8b is also a special case. */
4284 if (! (i
.operands
== 2
4285 && i
.tm
.base_opcode
== 0x90
4286 && i
.tm
.extension_opcode
== None
4287 && operand_type_equal (&i
.types
[0], &acc64
)
4288 && operand_type_equal (&i
.types
[1], &acc64
))
4289 && ! (i
.operands
== 1
4290 && i
.tm
.base_opcode
== 0xfc7
4291 && i
.tm
.extension_opcode
== 1
4292 && !operand_type_check (i
.types
[0], reg
)
4293 && operand_type_check (i
.types
[0], anymem
)))
4297 /* Size floating point instruction. */
4298 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4299 if (i
.tm
.opcode_modifier
.floatmf
)
4300 i
.tm
.base_opcode
^= 4;
4307 check_byte_reg (void)
4311 for (op
= i
.operands
; --op
>= 0;)
4313 /* If this is an eight bit register, it's OK. If it's the 16 or
4314 32 bit version of an eight bit register, we will just use the
4315 low portion, and that's OK too. */
4316 if (i
.types
[op
].bitfield
.reg8
)
4319 /* Don't generate this warning if not needed. */
4320 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4323 /* crc32 doesn't generate this warning. */
4324 if (i
.tm
.base_opcode
== 0xf20f38f0)
4327 if ((i
.types
[op
].bitfield
.reg16
4328 || i
.types
[op
].bitfield
.reg32
4329 || i
.types
[op
].bitfield
.reg64
)
4330 && i
.op
[op
].regs
->reg_num
< 4)
4332 /* Prohibit these changes in the 64bit mode, since the
4333 lowering is more complicated. */
4334 if (flag_code
== CODE_64BIT
4335 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4337 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4338 register_prefix
, i
.op
[op
].regs
->reg_name
,
4342 #if REGISTER_WARNINGS
4344 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4345 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4347 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4348 ? REGNAM_AL
- REGNAM_AX
4349 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4351 i
.op
[op
].regs
->reg_name
,
4356 /* Any other register is bad. */
4357 if (i
.types
[op
].bitfield
.reg16
4358 || i
.types
[op
].bitfield
.reg32
4359 || i
.types
[op
].bitfield
.reg64
4360 || i
.types
[op
].bitfield
.regmmx
4361 || i
.types
[op
].bitfield
.regxmm
4362 || i
.types
[op
].bitfield
.regymm
4363 || i
.types
[op
].bitfield
.sreg2
4364 || i
.types
[op
].bitfield
.sreg3
4365 || i
.types
[op
].bitfield
.control
4366 || i
.types
[op
].bitfield
.debug
4367 || i
.types
[op
].bitfield
.test
4368 || i
.types
[op
].bitfield
.floatreg
4369 || i
.types
[op
].bitfield
.floatacc
)
4371 as_bad (_("`%s%s' not allowed with `%s%c'"),
4373 i
.op
[op
].regs
->reg_name
,
4383 check_long_reg (void)
4387 for (op
= i
.operands
; --op
>= 0;)
4388 /* Reject eight bit registers, except where the template requires
4389 them. (eg. movzb) */
4390 if (i
.types
[op
].bitfield
.reg8
4391 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4392 || i
.tm
.operand_types
[op
].bitfield
.reg32
4393 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4395 as_bad (_("`%s%s' not allowed with `%s%c'"),
4397 i
.op
[op
].regs
->reg_name
,
4402 /* Warn if the e prefix on a general reg is missing. */
4403 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4404 && i
.types
[op
].bitfield
.reg16
4405 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4406 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4408 /* Prohibit these changes in the 64bit mode, since the
4409 lowering is more complicated. */
4410 if (flag_code
== CODE_64BIT
)
4412 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4413 register_prefix
, i
.op
[op
].regs
->reg_name
,
4417 #if REGISTER_WARNINGS
4419 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4421 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4423 i
.op
[op
].regs
->reg_name
,
4427 /* Warn if the r prefix on a general reg is missing. */
4428 else if (i
.types
[op
].bitfield
.reg64
4429 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4430 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4433 && i
.tm
.opcode_modifier
.toqword
4434 && !i
.types
[0].bitfield
.regxmm
)
4436 /* Convert to QWORD. We want REX byte. */
4437 i
.suffix
= QWORD_MNEM_SUFFIX
;
4441 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4442 register_prefix
, i
.op
[op
].regs
->reg_name
,
4451 check_qword_reg (void)
4455 for (op
= i
.operands
; --op
>= 0; )
4456 /* Reject eight bit registers, except where the template requires
4457 them. (eg. movzb) */
4458 if (i
.types
[op
].bitfield
.reg8
4459 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4460 || i
.tm
.operand_types
[op
].bitfield
.reg32
4461 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4463 as_bad (_("`%s%s' not allowed with `%s%c'"),
4465 i
.op
[op
].regs
->reg_name
,
4470 /* Warn if the e prefix on a general reg is missing. */
4471 else if ((i
.types
[op
].bitfield
.reg16
4472 || i
.types
[op
].bitfield
.reg32
)
4473 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4474 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4476 /* Prohibit these changes in the 64bit mode, since the
4477 lowering is more complicated. */
4479 && i
.tm
.opcode_modifier
.todword
4480 && !i
.types
[0].bitfield
.regxmm
)
4482 /* Convert to DWORD. We don't want REX byte. */
4483 i
.suffix
= LONG_MNEM_SUFFIX
;
4487 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4488 register_prefix
, i
.op
[op
].regs
->reg_name
,
4497 check_word_reg (void)
4500 for (op
= i
.operands
; --op
>= 0;)
4501 /* Reject eight bit registers, except where the template requires
4502 them. (eg. movzb) */
4503 if (i
.types
[op
].bitfield
.reg8
4504 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4505 || i
.tm
.operand_types
[op
].bitfield
.reg32
4506 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4508 as_bad (_("`%s%s' not allowed with `%s%c'"),
4510 i
.op
[op
].regs
->reg_name
,
4515 /* Warn if the e prefix on a general reg is present. */
4516 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4517 && i
.types
[op
].bitfield
.reg32
4518 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4519 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4521 /* Prohibit these changes in the 64bit mode, since the
4522 lowering is more complicated. */
4523 if (flag_code
== CODE_64BIT
)
4525 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4526 register_prefix
, i
.op
[op
].regs
->reg_name
,
4531 #if REGISTER_WARNINGS
4532 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4534 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4536 i
.op
[op
].regs
->reg_name
,
4544 update_imm (unsigned int j
)
4546 i386_operand_type overlap
= i
.types
[j
];
4547 if ((overlap
.bitfield
.imm8
4548 || overlap
.bitfield
.imm8s
4549 || overlap
.bitfield
.imm16
4550 || overlap
.bitfield
.imm32
4551 || overlap
.bitfield
.imm32s
4552 || overlap
.bitfield
.imm64
)
4553 && !operand_type_equal (&overlap
, &imm8
)
4554 && !operand_type_equal (&overlap
, &imm8s
)
4555 && !operand_type_equal (&overlap
, &imm16
)
4556 && !operand_type_equal (&overlap
, &imm32
)
4557 && !operand_type_equal (&overlap
, &imm32s
)
4558 && !operand_type_equal (&overlap
, &imm64
))
4562 i386_operand_type temp
;
4564 operand_type_set (&temp
, 0);
4565 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4567 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4568 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4570 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4571 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4572 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4574 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4575 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4578 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4581 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4582 || operand_type_equal (&overlap
, &imm16_32
)
4583 || operand_type_equal (&overlap
, &imm16_32s
))
4585 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4590 if (!operand_type_equal (&overlap
, &imm8
)
4591 && !operand_type_equal (&overlap
, &imm8s
)
4592 && !operand_type_equal (&overlap
, &imm16
)
4593 && !operand_type_equal (&overlap
, &imm32
)
4594 && !operand_type_equal (&overlap
, &imm32s
)
4595 && !operand_type_equal (&overlap
, &imm64
))
4597 as_bad (_("no instruction mnemonic suffix given; "
4598 "can't determine immediate size"));
4602 i
.types
[j
] = overlap
;
4612 /* Update the first 2 immediate operands. */
4613 n
= i
.operands
> 2 ? 2 : i
.operands
;
4616 for (j
= 0; j
< n
; j
++)
4617 if (update_imm (j
) == 0)
4620 /* The 3rd operand can't be immediate operand. */
4621 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4628 bad_implicit_operand (int xmm
)
4630 const char *reg
= xmm
? "xmm0" : "ymm0";
4632 as_bad (_("the last operand of `%s' must be `%s%s'"),
4633 i
.tm
.name
, register_prefix
, reg
);
4635 as_bad (_("the first operand of `%s' must be `%s%s'"),
4636 i
.tm
.name
, register_prefix
, reg
);
4641 process_operands (void)
4643 /* Default segment register this instruction will use for memory
4644 accesses. 0 means unknown. This is only for optimizing out
4645 unnecessary segment overrides. */
4646 const seg_entry
*default_seg
= 0;
4648 if (i
.tm
.opcode_modifier
.sse2avx
4649 && (i
.tm
.opcode_modifier
.vexnds
4650 || i
.tm
.opcode_modifier
.vexndd
))
4652 unsigned int dup
= i
.operands
;
4653 unsigned int dest
= dup
- 1;
4656 /* The destination must be an xmm register. */
4657 gas_assert (i
.reg_operands
4658 && MAX_OPERANDS
> dup
4659 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4661 if (i
.tm
.opcode_modifier
.firstxmm0
)
4663 /* The first operand is implicit and must be xmm0. */
4664 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4665 if (i
.op
[0].regs
->reg_num
!= 0)
4666 return bad_implicit_operand (1);
4668 if (i
.tm
.opcode_modifier
.vex3sources
)
4670 /* Keep xmm0 for instructions with VEX prefix and 3
4676 /* We remove the first xmm0 and keep the number of
4677 operands unchanged, which in fact duplicates the
4679 for (j
= 1; j
< i
.operands
; j
++)
4681 i
.op
[j
- 1] = i
.op
[j
];
4682 i
.types
[j
- 1] = i
.types
[j
];
4683 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4687 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4689 gas_assert ((MAX_OPERANDS
- 1) > dup
4690 && i
.tm
.opcode_modifier
.vex3sources
);
4692 /* Add the implicit xmm0 for instructions with VEX prefix
4694 for (j
= i
.operands
; j
> 0; j
--)
4696 i
.op
[j
] = i
.op
[j
- 1];
4697 i
.types
[j
] = i
.types
[j
- 1];
4698 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4701 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4702 i
.types
[0] = regxmm
;
4703 i
.tm
.operand_types
[0] = regxmm
;
4706 i
.reg_operands
+= 2;
4711 i
.op
[dup
] = i
.op
[dest
];
4712 i
.types
[dup
] = i
.types
[dest
];
4713 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4722 i
.op
[dup
] = i
.op
[dest
];
4723 i
.types
[dup
] = i
.types
[dest
];
4724 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4727 if (i
.tm
.opcode_modifier
.immext
)
4730 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4734 /* The first operand is implicit and must be xmm0/ymm0. */
4735 gas_assert (i
.reg_operands
4736 && (operand_type_equal (&i
.types
[0], ®xmm
)
4737 || operand_type_equal (&i
.types
[0], ®ymm
)));
4738 if (i
.op
[0].regs
->reg_num
!= 0)
4739 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4741 for (j
= 1; j
< i
.operands
; j
++)
4743 i
.op
[j
- 1] = i
.op
[j
];
4744 i
.types
[j
- 1] = i
.types
[j
];
4746 /* We need to adjust fields in i.tm since they are used by
4747 build_modrm_byte. */
4748 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4755 else if (i
.tm
.opcode_modifier
.regkludge
)
4757 /* The imul $imm, %reg instruction is converted into
4758 imul $imm, %reg, %reg, and the clr %reg instruction
4759 is converted into xor %reg, %reg. */
4761 unsigned int first_reg_op
;
4763 if (operand_type_check (i
.types
[0], reg
))
4767 /* Pretend we saw the extra register operand. */
4768 gas_assert (i
.reg_operands
== 1
4769 && i
.op
[first_reg_op
+ 1].regs
== 0);
4770 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4771 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4776 if (i
.tm
.opcode_modifier
.shortform
)
4778 if (i
.types
[0].bitfield
.sreg2
4779 || i
.types
[0].bitfield
.sreg3
)
4781 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4782 && i
.op
[0].regs
->reg_num
== 1)
4784 as_bad (_("you can't `pop %scs'"), register_prefix
);
4787 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4788 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4793 /* The register or float register operand is in operand
4797 if (i
.types
[0].bitfield
.floatreg
4798 || operand_type_check (i
.types
[0], reg
))
4802 /* Register goes in low 3 bits of opcode. */
4803 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4804 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4806 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4808 /* Warn about some common errors, but press on regardless.
4809 The first case can be generated by gcc (<= 2.8.1). */
4810 if (i
.operands
== 2)
4812 /* Reversed arguments on faddp, fsubp, etc. */
4813 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4814 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4815 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4819 /* Extraneous `l' suffix on fp insn. */
4820 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4821 register_prefix
, i
.op
[0].regs
->reg_name
);
4826 else if (i
.tm
.opcode_modifier
.modrm
)
4828 /* The opcode is completed (modulo i.tm.extension_opcode which
4829 must be put into the modrm byte). Now, we make the modrm and
4830 index base bytes based on all the info we've collected. */
4832 default_seg
= build_modrm_byte ();
4834 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4838 else if (i
.tm
.opcode_modifier
.isstring
)
4840 /* For the string instructions that allow a segment override
4841 on one of their operands, the default segment is ds. */
4845 if (i
.tm
.base_opcode
== 0x8d /* lea */
4848 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4850 /* If a segment was explicitly specified, and the specified segment
4851 is not the default, use an opcode prefix to select it. If we
4852 never figured out what the default segment is, then default_seg
4853 will be zero at this point, and the specified segment prefix will
4855 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4857 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4863 static const seg_entry
*
4864 build_modrm_byte (void)
4866 const seg_entry
*default_seg
= 0;
4867 unsigned int source
, dest
;
4870 /* The first operand of instructions with VEX prefix and 3 sources
4871 must be VEX_Imm4. */
4872 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4875 unsigned int nds
, reg
;
4878 if (i
.tm
.opcode_modifier
.veximmext
4879 && i
.tm
.opcode_modifier
.immext
)
4881 dest
= i
.operands
- 2;
4882 gas_assert (dest
== 3);
4885 dest
= i
.operands
- 1;
4888 /* This instruction must have 4 register operands
4889 or 3 register operands plus 1 memory operand.
4890 It must have VexNDS and VexImmExt. */
4891 gas_assert ((i
.reg_operands
== 4
4892 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4893 && i
.tm
.opcode_modifier
.vexnds
4894 && i
.tm
.opcode_modifier
.veximmext
4895 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4896 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4898 /* Generate an 8bit immediate operand to encode the register
4900 exp
= &im_expressions
[i
.imm_operands
++];
4901 i
.op
[i
.operands
].imms
= exp
;
4902 i
.types
[i
.operands
] = imm8
;
4904 /* If VexW1 is set, the first operand is the source and
4905 the second operand is encoded in the immediate operand. */
4906 if (i
.tm
.opcode_modifier
.vexw1
)
4916 /* FMA4 swaps REG and NDS. */
4917 if (i
.tm
.cpu_flags
.bitfield
.cpufma4
)
4924 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4925 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4927 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4928 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4930 exp
->X_op
= O_constant
;
4932 = ((i
.op
[reg
].regs
->reg_num
4933 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4934 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4939 /* i.reg_operands MUST be the number of real register operands;
4940 implicit registers do not count. If there are 3 register
4941 operands, it must be a instruction with VexNDS. For a
4942 instruction with VexNDD, the destination register is encoded
4943 in VEX prefix. If there are 4 register operands, it must be
4944 a instruction with VEX prefix and 3 sources. */
4945 if (i
.mem_operands
== 0
4946 && ((i
.reg_operands
== 2
4947 && !i
.tm
.opcode_modifier
.vexndd
)
4948 || (i
.reg_operands
== 3
4949 && i
.tm
.opcode_modifier
.vexnds
)
4950 || (i
.reg_operands
== 4 && vex_3_sources
)))
4958 /* When there are 3 operands, one of them may be immediate,
4959 which may be the first or the last operand. Otherwise,
4960 the first operand must be shift count register (cl) or it
4961 is an instruction with VexNDS. */
4962 gas_assert (i
.imm_operands
== 1
4963 || (i
.imm_operands
== 0
4964 && (i
.tm
.opcode_modifier
.vexnds
4965 || i
.types
[0].bitfield
.shiftcount
)));
4966 if (operand_type_check (i
.types
[0], imm
)
4967 || i
.types
[0].bitfield
.shiftcount
)
4973 /* When there are 4 operands, the first two must be 8bit
4974 immediate operands. The source operand will be the 3rd
4977 For instructions with VexNDS, if the first operand
4978 an imm8, the source operand is the 2nd one. If the last
4979 operand is imm8, the source operand is the first one. */
4980 gas_assert ((i
.imm_operands
== 2
4981 && i
.types
[0].bitfield
.imm8
4982 && i
.types
[1].bitfield
.imm8
)
4983 || (i
.tm
.opcode_modifier
.vexnds
4984 && i
.imm_operands
== 1
4985 && (i
.types
[0].bitfield
.imm8
4986 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4987 if (i
.tm
.opcode_modifier
.vexnds
)
4989 if (i
.types
[0].bitfield
.imm8
)
5007 if (i
.tm
.opcode_modifier
.vexnds
)
5009 /* For instructions with VexNDS, the register-only
5010 source operand must be XMM or YMM register. It is
5011 encoded in VEX prefix. We need to clear RegMem bit
5012 before calling operand_type_equal. */
5013 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5014 op
.bitfield
.regmem
= 0;
5015 if ((dest
+ 1) >= i
.operands
5016 || (!operand_type_equal (&op
, ®xmm
)
5017 && !operand_type_equal (&op
, ®ymm
)))
5019 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5025 /* One of the register operands will be encoded in the i.tm.reg
5026 field, the other in the combined i.tm.mode and i.tm.regmem
5027 fields. If no form of this instruction supports a memory
5028 destination operand, then we assume the source operand may
5029 sometimes be a memory operand and so we need to store the
5030 destination in the i.rm.reg field. */
5031 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5032 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5034 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5035 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5036 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5038 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5043 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5044 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5045 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5047 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5050 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5052 if (!i
.types
[0].bitfield
.control
5053 && !i
.types
[1].bitfield
.control
)
5055 i
.rex
&= ~(REX_R
| REX_B
);
5056 add_prefix (LOCK_PREFIX_OPCODE
);
5060 { /* If it's not 2 reg operands... */
5065 unsigned int fake_zero_displacement
= 0;
5068 for (op
= 0; op
< i
.operands
; op
++)
5069 if (operand_type_check (i
.types
[op
], anymem
))
5071 gas_assert (op
< i
.operands
);
5075 if (i
.base_reg
== 0)
5078 if (!i
.disp_operands
)
5079 fake_zero_displacement
= 1;
5080 if (i
.index_reg
== 0)
5082 /* Operand is just <disp> */
5083 if (flag_code
== CODE_64BIT
)
5085 /* 64bit mode overwrites the 32bit absolute
5086 addressing by RIP relative addressing and
5087 absolute addressing is encoded by one of the
5088 redundant SIB forms. */
5089 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5090 i
.sib
.base
= NO_BASE_REGISTER
;
5091 i
.sib
.index
= NO_INDEX_REGISTER
;
5092 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5093 ? disp32s
: disp32
);
5095 else if ((flag_code
== CODE_16BIT
)
5096 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5098 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5099 i
.types
[op
] = disp16
;
5103 i
.rm
.regmem
= NO_BASE_REGISTER
;
5104 i
.types
[op
] = disp32
;
5107 else /* !i.base_reg && i.index_reg */
5109 if (i
.index_reg
->reg_num
== RegEiz
5110 || i
.index_reg
->reg_num
== RegRiz
)
5111 i
.sib
.index
= NO_INDEX_REGISTER
;
5113 i
.sib
.index
= i
.index_reg
->reg_num
;
5114 i
.sib
.base
= NO_BASE_REGISTER
;
5115 i
.sib
.scale
= i
.log2_scale_factor
;
5116 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5117 i
.types
[op
].bitfield
.disp8
= 0;
5118 i
.types
[op
].bitfield
.disp16
= 0;
5119 i
.types
[op
].bitfield
.disp64
= 0;
5120 if (flag_code
!= CODE_64BIT
)
5122 /* Must be 32 bit */
5123 i
.types
[op
].bitfield
.disp32
= 1;
5124 i
.types
[op
].bitfield
.disp32s
= 0;
5128 i
.types
[op
].bitfield
.disp32
= 0;
5129 i
.types
[op
].bitfield
.disp32s
= 1;
5131 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5135 /* RIP addressing for 64bit mode. */
5136 else if (i
.base_reg
->reg_num
== RegRip
||
5137 i
.base_reg
->reg_num
== RegEip
)
5139 i
.rm
.regmem
= NO_BASE_REGISTER
;
5140 i
.types
[op
].bitfield
.disp8
= 0;
5141 i
.types
[op
].bitfield
.disp16
= 0;
5142 i
.types
[op
].bitfield
.disp32
= 0;
5143 i
.types
[op
].bitfield
.disp32s
= 1;
5144 i
.types
[op
].bitfield
.disp64
= 0;
5145 i
.flags
[op
] |= Operand_PCrel
;
5146 if (! i
.disp_operands
)
5147 fake_zero_displacement
= 1;
5149 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5151 switch (i
.base_reg
->reg_num
)
5154 if (i
.index_reg
== 0)
5156 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5157 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5161 if (i
.index_reg
== 0)
5164 if (operand_type_check (i
.types
[op
], disp
) == 0)
5166 /* fake (%bp) into 0(%bp) */
5167 i
.types
[op
].bitfield
.disp8
= 1;
5168 fake_zero_displacement
= 1;
5171 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5172 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5174 default: /* (%si) -> 4 or (%di) -> 5 */
5175 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5177 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5179 else /* i.base_reg and 32/64 bit mode */
5181 if (flag_code
== CODE_64BIT
5182 && operand_type_check (i
.types
[op
], disp
))
5184 i386_operand_type temp
;
5185 operand_type_set (&temp
, 0);
5186 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5188 if (i
.prefix
[ADDR_PREFIX
] == 0)
5189 i
.types
[op
].bitfield
.disp32s
= 1;
5191 i
.types
[op
].bitfield
.disp32
= 1;
5194 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5195 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5197 i
.sib
.base
= i
.base_reg
->reg_num
;
5198 /* x86-64 ignores REX prefix bit here to avoid decoder
5200 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5203 if (i
.disp_operands
== 0)
5205 fake_zero_displacement
= 1;
5206 i
.types
[op
].bitfield
.disp8
= 1;
5209 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5213 i
.sib
.scale
= i
.log2_scale_factor
;
5214 if (i
.index_reg
== 0)
5216 /* <disp>(%esp) becomes two byte modrm with no index
5217 register. We've already stored the code for esp
5218 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5219 Any base register besides %esp will not use the
5220 extra modrm byte. */
5221 i
.sib
.index
= NO_INDEX_REGISTER
;
5225 if (i
.index_reg
->reg_num
== RegEiz
5226 || i
.index_reg
->reg_num
== RegRiz
)
5227 i
.sib
.index
= NO_INDEX_REGISTER
;
5229 i
.sib
.index
= i
.index_reg
->reg_num
;
5230 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5231 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5236 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5237 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5240 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5243 if (fake_zero_displacement
)
5245 /* Fakes a zero displacement assuming that i.types[op]
5246 holds the correct displacement size. */
5249 gas_assert (i
.op
[op
].disps
== 0);
5250 exp
= &disp_expressions
[i
.disp_operands
++];
5251 i
.op
[op
].disps
= exp
;
5252 exp
->X_op
= O_constant
;
5253 exp
->X_add_number
= 0;
5254 exp
->X_add_symbol
= (symbolS
*) 0;
5255 exp
->X_op_symbol
= (symbolS
*) 0;
5263 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5264 (if any) based on i.tm.extension_opcode. Again, we must be
5265 careful to make sure that segment/control/debug/test/MMX
5266 registers are coded into the i.rm.reg field. */
5270 unsigned int vex_reg
= ~0;
5272 for (op
= 0; op
< i
.operands
; op
++)
5273 if (i
.types
[op
].bitfield
.reg8
5274 || i
.types
[op
].bitfield
.reg16
5275 || i
.types
[op
].bitfield
.reg32
5276 || i
.types
[op
].bitfield
.reg64
5277 || i
.types
[op
].bitfield
.regmmx
5278 || i
.types
[op
].bitfield
.regxmm
5279 || i
.types
[op
].bitfield
.regymm
5280 || i
.types
[op
].bitfield
.sreg2
5281 || i
.types
[op
].bitfield
.sreg3
5282 || i
.types
[op
].bitfield
.control
5283 || i
.types
[op
].bitfield
.debug
5284 || i
.types
[op
].bitfield
.test
)
5289 else if (i
.tm
.opcode_modifier
.vexnds
)
5291 /* For instructions with VexNDS, the register-only
5292 source operand is encoded in VEX prefix. */
5293 gas_assert (mem
!= (unsigned int) ~0);
5298 gas_assert (op
< i
.operands
);
5303 gas_assert (vex_reg
< i
.operands
);
5306 else if (i
.tm
.opcode_modifier
.vexndd
)
5308 /* For instructions with VexNDD, there should be
5309 no memory operand and the register destination
5310 is encoded in VEX prefix. */
5311 gas_assert (i
.mem_operands
== 0
5312 && (op
+ 2) == i
.operands
);
5316 gas_assert (op
< i
.operands
);
5318 if (vex_reg
!= (unsigned int) ~0)
5320 gas_assert (i
.reg_operands
== 2);
5322 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5324 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5327 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5330 /* If there is an extension opcode to put here, the
5331 register number must be put into the regmem field. */
5332 if (i
.tm
.extension_opcode
!= None
)
5334 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5335 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5340 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5341 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5345 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5346 must set it to 3 to indicate this is a register operand
5347 in the regmem field. */
5348 if (!i
.mem_operands
)
5352 /* Fill in i.rm.reg field with extension opcode (if any). */
5353 if (i
.tm
.extension_opcode
!= None
)
5354 i
.rm
.reg
= i
.tm
.extension_opcode
;
5360 output_branch (void)
5365 relax_substateT subtype
;
5370 if (flag_code
== CODE_16BIT
)
5374 if (i
.prefix
[DATA_PREFIX
] != 0)
5380 /* Pentium4 branch hints. */
5381 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5382 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5387 if (i
.prefix
[REX_PREFIX
] != 0)
5393 if (i
.prefixes
!= 0 && !intel_syntax
)
5394 as_warn (_("skipping prefixes on this instruction"));
5396 /* It's always a symbol; End frag & setup for relax.
5397 Make sure there is enough room in this frag for the largest
5398 instruction we may generate in md_convert_frag. This is 2
5399 bytes for the opcode and room for the prefix and largest
5401 frag_grow (prefix
+ 2 + 4);
5402 /* Prefix and 1 opcode byte go in fr_fix. */
5403 p
= frag_more (prefix
+ 1);
5404 if (i
.prefix
[DATA_PREFIX
] != 0)
5405 *p
++ = DATA_PREFIX_OPCODE
;
5406 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5407 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5408 *p
++ = i
.prefix
[SEG_PREFIX
];
5409 if (i
.prefix
[REX_PREFIX
] != 0)
5410 *p
++ = i
.prefix
[REX_PREFIX
];
5411 *p
= i
.tm
.base_opcode
;
5413 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5414 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5415 else if (cpu_arch_flags
.bitfield
.cpui386
)
5416 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5418 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5421 sym
= i
.op
[0].disps
->X_add_symbol
;
5422 off
= i
.op
[0].disps
->X_add_number
;
5424 if (i
.op
[0].disps
->X_op
!= O_constant
5425 && i
.op
[0].disps
->X_op
!= O_symbol
)
5427 /* Handle complex expressions. */
5428 sym
= make_expr_symbol (i
.op
[0].disps
);
5432 /* 1 possible extra opcode + 4 byte displacement go in var part.
5433 Pass reloc in fr_var. */
5434 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5444 if (i
.tm
.opcode_modifier
.jumpbyte
)
5446 /* This is a loop or jecxz type instruction. */
5448 if (i
.prefix
[ADDR_PREFIX
] != 0)
5450 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5453 /* Pentium4 branch hints. */
5454 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5455 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5457 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5466 if (flag_code
== CODE_16BIT
)
5469 if (i
.prefix
[DATA_PREFIX
] != 0)
5471 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5481 if (i
.prefix
[REX_PREFIX
] != 0)
5483 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5487 if (i
.prefixes
!= 0 && !intel_syntax
)
5488 as_warn (_("skipping prefixes on this instruction"));
5490 p
= frag_more (1 + size
);
5491 *p
++ = i
.tm
.base_opcode
;
5493 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5494 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5496 /* All jumps handled here are signed, but don't use a signed limit
5497 check for 32 and 16 bit jumps as we want to allow wrap around at
5498 4G and 64k respectively. */
5500 fixP
->fx_signed
= 1;
5504 output_interseg_jump (void)
5512 if (flag_code
== CODE_16BIT
)
5516 if (i
.prefix
[DATA_PREFIX
] != 0)
5522 if (i
.prefix
[REX_PREFIX
] != 0)
5532 if (i
.prefixes
!= 0 && !intel_syntax
)
5533 as_warn (_("skipping prefixes on this instruction"));
5535 /* 1 opcode; 2 segment; offset */
5536 p
= frag_more (prefix
+ 1 + 2 + size
);
5538 if (i
.prefix
[DATA_PREFIX
] != 0)
5539 *p
++ = DATA_PREFIX_OPCODE
;
5541 if (i
.prefix
[REX_PREFIX
] != 0)
5542 *p
++ = i
.prefix
[REX_PREFIX
];
5544 *p
++ = i
.tm
.base_opcode
;
5545 if (i
.op
[1].imms
->X_op
== O_constant
)
5547 offsetT n
= i
.op
[1].imms
->X_add_number
;
5550 && !fits_in_unsigned_word (n
)
5551 && !fits_in_signed_word (n
))
5553 as_bad (_("16-bit jump out of range"));
5556 md_number_to_chars (p
, n
, size
);
5559 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5560 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5561 if (i
.op
[0].imms
->X_op
!= O_constant
)
5562 as_bad (_("can't handle non absolute segment in `%s'"),
5564 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5570 fragS
*insn_start_frag
;
5571 offsetT insn_start_off
;
5573 /* Tie dwarf2 debug info to the address at the start of the insn.
5574 We can't do this after the insn has been output as the current
5575 frag may have been closed off. eg. by frag_var. */
5576 dwarf2_emit_insn (0);
5578 insn_start_frag
= frag_now
;
5579 insn_start_off
= frag_now_fix ();
5582 if (i
.tm
.opcode_modifier
.jump
)
5584 else if (i
.tm
.opcode_modifier
.jumpbyte
5585 || i
.tm
.opcode_modifier
.jumpdword
)
5587 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5588 output_interseg_jump ();
5591 /* Output normal instructions here. */
5595 unsigned int prefix
;
5597 /* Since the VEX prefix contains the implicit prefix, we don't
5598 need the explicit prefix. */
5599 if (!i
.tm
.opcode_modifier
.vex
)
5601 switch (i
.tm
.opcode_length
)
5604 if (i
.tm
.base_opcode
& 0xff000000)
5606 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5611 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5613 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5614 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5617 if (prefix
!= REPE_PREFIX_OPCODE
5618 || (i
.prefix
[LOCKREP_PREFIX
]
5619 != REPE_PREFIX_OPCODE
))
5620 add_prefix (prefix
);
5623 add_prefix (prefix
);
5632 /* The prefix bytes. */
5633 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5635 FRAG_APPEND_1_CHAR (*q
);
5638 if (i
.tm
.opcode_modifier
.vex
)
5640 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5645 /* REX byte is encoded in VEX prefix. */
5649 FRAG_APPEND_1_CHAR (*q
);
5652 /* There should be no other prefixes for instructions
5657 /* Now the VEX prefix. */
5658 p
= frag_more (i
.vex
.length
);
5659 for (j
= 0; j
< i
.vex
.length
; j
++)
5660 p
[j
] = i
.vex
.bytes
[j
];
5663 /* Now the opcode; be careful about word order here! */
5664 if (i
.tm
.opcode_length
== 1)
5666 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5670 switch (i
.tm
.opcode_length
)
5674 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5684 /* Put out high byte first: can't use md_number_to_chars! */
5685 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5686 *p
= i
.tm
.base_opcode
& 0xff;
5689 /* Now the modrm byte and sib byte (if present). */
5690 if (i
.tm
.opcode_modifier
.modrm
)
5692 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5695 /* If i.rm.regmem == ESP (4)
5696 && i.rm.mode != (Register mode)
5698 ==> need second modrm byte. */
5699 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5701 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5702 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5704 | i
.sib
.scale
<< 6));
5707 if (i
.disp_operands
)
5708 output_disp (insn_start_frag
, insn_start_off
);
5711 output_imm (insn_start_frag
, insn_start_off
);
5717 pi ("" /*line*/, &i
);
5719 #endif /* DEBUG386 */
5722 /* Return the size of the displacement operand N. */
5725 disp_size (unsigned int n
)
5728 if (i
.types
[n
].bitfield
.disp64
)
5730 else if (i
.types
[n
].bitfield
.disp8
)
5732 else if (i
.types
[n
].bitfield
.disp16
)
5737 /* Return the size of the immediate operand N. */
5740 imm_size (unsigned int n
)
5743 if (i
.types
[n
].bitfield
.imm64
)
5745 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5747 else if (i
.types
[n
].bitfield
.imm16
)
5753 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5758 for (n
= 0; n
< i
.operands
; n
++)
5760 if (operand_type_check (i
.types
[n
], disp
))
5762 if (i
.op
[n
].disps
->X_op
== O_constant
)
5764 int size
= disp_size (n
);
5767 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5769 p
= frag_more (size
);
5770 md_number_to_chars (p
, val
, size
);
5774 enum bfd_reloc_code_real reloc_type
;
5775 int size
= disp_size (n
);
5776 int sign
= i
.types
[n
].bitfield
.disp32s
;
5777 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5779 /* We can't have 8 bit displacement here. */
5780 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5782 /* The PC relative address is computed relative
5783 to the instruction boundary, so in case immediate
5784 fields follows, we need to adjust the value. */
5785 if (pcrel
&& i
.imm_operands
)
5790 for (n1
= 0; n1
< i
.operands
; n1
++)
5791 if (operand_type_check (i
.types
[n1
], imm
))
5793 /* Only one immediate is allowed for PC
5794 relative address. */
5795 gas_assert (sz
== 0);
5797 i
.op
[n
].disps
->X_add_number
-= sz
;
5799 /* We should find the immediate. */
5800 gas_assert (sz
!= 0);
5803 p
= frag_more (size
);
5804 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5806 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5807 && (((reloc_type
== BFD_RELOC_32
5808 || reloc_type
== BFD_RELOC_X86_64_32S
5809 || (reloc_type
== BFD_RELOC_64
5811 && (i
.op
[n
].disps
->X_op
== O_symbol
5812 || (i
.op
[n
].disps
->X_op
== O_add
5813 && ((symbol_get_value_expression
5814 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5816 || reloc_type
== BFD_RELOC_32_PCREL
))
5820 if (insn_start_frag
== frag_now
)
5821 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5826 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5827 for (fr
= insn_start_frag
->fr_next
;
5828 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5830 add
+= p
- frag_now
->fr_literal
;
5835 reloc_type
= BFD_RELOC_386_GOTPC
;
5836 i
.op
[n
].imms
->X_add_number
+= add
;
5838 else if (reloc_type
== BFD_RELOC_64
)
5839 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5841 /* Don't do the adjustment for x86-64, as there
5842 the pcrel addressing is relative to the _next_
5843 insn, and that is taken care of in other code. */
5844 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5846 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5847 i
.op
[n
].disps
, pcrel
, reloc_type
);
5854 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5859 for (n
= 0; n
< i
.operands
; n
++)
5861 if (operand_type_check (i
.types
[n
], imm
))
5863 if (i
.op
[n
].imms
->X_op
== O_constant
)
5865 int size
= imm_size (n
);
5868 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5870 p
= frag_more (size
);
5871 md_number_to_chars (p
, val
, size
);
5875 /* Not absolute_section.
5876 Need a 32-bit fixup (don't support 8bit
5877 non-absolute imms). Try to support other
5879 enum bfd_reloc_code_real reloc_type
;
5880 int size
= imm_size (n
);
5883 if (i
.types
[n
].bitfield
.imm32s
5884 && (i
.suffix
== QWORD_MNEM_SUFFIX
5885 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5890 p
= frag_more (size
);
5891 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5893 /* This is tough to explain. We end up with this one if we
5894 * have operands that look like
5895 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5896 * obtain the absolute address of the GOT, and it is strongly
5897 * preferable from a performance point of view to avoid using
5898 * a runtime relocation for this. The actual sequence of
5899 * instructions often look something like:
5904 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5906 * The call and pop essentially return the absolute address
5907 * of the label .L66 and store it in %ebx. The linker itself
5908 * will ultimately change the first operand of the addl so
5909 * that %ebx points to the GOT, but to keep things simple, the
5910 * .o file must have this operand set so that it generates not
5911 * the absolute address of .L66, but the absolute address of
5912 * itself. This allows the linker itself simply treat a GOTPC
5913 * relocation as asking for a pcrel offset to the GOT to be
5914 * added in, and the addend of the relocation is stored in the
5915 * operand field for the instruction itself.
5917 * Our job here is to fix the operand so that it would add
5918 * the correct offset so that %ebx would point to itself. The
5919 * thing that is tricky is that .-.L66 will point to the
5920 * beginning of the instruction, so we need to further modify
5921 * the operand so that it will point to itself. There are
5922 * other cases where you have something like:
5924 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5926 * and here no correction would be required. Internally in
5927 * the assembler we treat operands of this form as not being
5928 * pcrel since the '.' is explicitly mentioned, and I wonder
5929 * whether it would simplify matters to do it this way. Who
5930 * knows. In earlier versions of the PIC patches, the
5931 * pcrel_adjust field was used to store the correction, but
5932 * since the expression is not pcrel, I felt it would be
5933 * confusing to do it this way. */
5935 if ((reloc_type
== BFD_RELOC_32
5936 || reloc_type
== BFD_RELOC_X86_64_32S
5937 || reloc_type
== BFD_RELOC_64
)
5939 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5940 && (i
.op
[n
].imms
->X_op
== O_symbol
5941 || (i
.op
[n
].imms
->X_op
== O_add
5942 && ((symbol_get_value_expression
5943 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5948 if (insn_start_frag
== frag_now
)
5949 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5954 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5955 for (fr
= insn_start_frag
->fr_next
;
5956 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5958 add
+= p
- frag_now
->fr_literal
;
5962 reloc_type
= BFD_RELOC_386_GOTPC
;
5964 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5966 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5967 i
.op
[n
].imms
->X_add_number
+= add
;
5969 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5970 i
.op
[n
].imms
, 0, reloc_type
);
5976 /* x86_cons_fix_new is called via the expression parsing code when a
5977 reloc is needed. We use this hook to get the correct .got reloc. */
5978 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5979 static int cons_sign
= -1;
5982 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5985 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5987 got_reloc
= NO_RELOC
;
5990 if (exp
->X_op
== O_secrel
)
5992 exp
->X_op
= O_symbol
;
5993 r
= BFD_RELOC_32_SECREL
;
5997 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6000 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6001 # define lex_got(reloc, adjust, types) NULL
6003 /* Parse operands of the form
6004 <symbol>@GOTOFF+<nnn>
6005 and similar .plt or .got references.
6007 If we find one, set up the correct relocation in RELOC and copy the
6008 input string, minus the `@GOTOFF' into a malloc'd buffer for
6009 parsing by the calling routine. Return this buffer, and if ADJUST
6010 is non-null set it to the length of the string we removed from the
6011 input line. Otherwise return NULL. */
6013 lex_got (enum bfd_reloc_code_real
*reloc
,
6015 i386_operand_type
*types
)
6017 /* Some of the relocations depend on the size of what field is to
6018 be relocated. But in our callers i386_immediate and i386_displacement
6019 we don't yet know the operand size (this will be set by insn
6020 matching). Hence we record the word32 relocation here,
6021 and adjust the reloc according to the real size in reloc(). */
6022 static const struct {
6024 const enum bfd_reloc_code_real rel
[2];
6025 const i386_operand_type types64
;
6027 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6028 BFD_RELOC_X86_64_PLTOFF64
},
6029 OPERAND_TYPE_IMM64
},
6030 { "PLT", { BFD_RELOC_386_PLT32
,
6031 BFD_RELOC_X86_64_PLT32
},
6032 OPERAND_TYPE_IMM32_32S_DISP32
},
6033 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6034 BFD_RELOC_X86_64_GOTPLT64
},
6035 OPERAND_TYPE_IMM64_DISP64
},
6036 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6037 BFD_RELOC_X86_64_GOTOFF64
},
6038 OPERAND_TYPE_IMM64_DISP64
},
6039 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6040 BFD_RELOC_X86_64_GOTPCREL
},
6041 OPERAND_TYPE_IMM32_32S_DISP32
},
6042 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6043 BFD_RELOC_X86_64_TLSGD
},
6044 OPERAND_TYPE_IMM32_32S_DISP32
},
6045 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6046 _dummy_first_bfd_reloc_code_real
},
6047 OPERAND_TYPE_NONE
},
6048 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6049 BFD_RELOC_X86_64_TLSLD
},
6050 OPERAND_TYPE_IMM32_32S_DISP32
},
6051 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6052 BFD_RELOC_X86_64_GOTTPOFF
},
6053 OPERAND_TYPE_IMM32_32S_DISP32
},
6054 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6055 BFD_RELOC_X86_64_TPOFF32
},
6056 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6057 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6058 _dummy_first_bfd_reloc_code_real
},
6059 OPERAND_TYPE_NONE
},
6060 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6061 BFD_RELOC_X86_64_DTPOFF32
},
6063 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6064 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6065 _dummy_first_bfd_reloc_code_real
},
6066 OPERAND_TYPE_NONE
},
6067 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6068 _dummy_first_bfd_reloc_code_real
},
6069 OPERAND_TYPE_NONE
},
6070 { "GOT", { BFD_RELOC_386_GOT32
,
6071 BFD_RELOC_X86_64_GOT32
},
6072 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6073 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6074 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6075 OPERAND_TYPE_IMM32_32S_DISP32
},
6076 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6077 BFD_RELOC_X86_64_TLSDESC_CALL
},
6078 OPERAND_TYPE_IMM32_32S_DISP32
},
6086 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6087 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6090 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6094 len
= strlen (gotrel
[j
].str
);
6095 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6097 if (gotrel
[j
].rel
[object_64bit
] != 0)
6100 char *tmpbuf
, *past_reloc
;
6102 *reloc
= gotrel
[j
].rel
[object_64bit
];
6108 if (flag_code
!= CODE_64BIT
)
6110 types
->bitfield
.imm32
= 1;
6111 types
->bitfield
.disp32
= 1;
6114 *types
= gotrel
[j
].types64
;
6117 if (GOT_symbol
== NULL
)
6118 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6120 /* The length of the first part of our input line. */
6121 first
= cp
- input_line_pointer
;
6123 /* The second part goes from after the reloc token until
6124 (and including) an end_of_line char or comma. */
6125 past_reloc
= cp
+ 1 + len
;
6127 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6129 second
= cp
+ 1 - past_reloc
;
6131 /* Allocate and copy string. The trailing NUL shouldn't
6132 be necessary, but be safe. */
6133 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6134 memcpy (tmpbuf
, input_line_pointer
, first
);
6135 if (second
!= 0 && *past_reloc
!= ' ')
6136 /* Replace the relocation token with ' ', so that
6137 errors like foo@GOTOFF1 will be detected. */
6138 tmpbuf
[first
++] = ' ';
6139 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6140 tmpbuf
[first
+ second
] = '\0';
6144 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6145 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6150 /* Might be a symbol version string. Don't as_bad here. */
6155 x86_cons (expressionS
*exp
, int size
)
6157 intel_syntax
= -intel_syntax
;
6159 if (size
== 4 || (object_64bit
&& size
== 8))
6161 /* Handle @GOTOFF and the like in an expression. */
6163 char *gotfree_input_line
;
6166 save
= input_line_pointer
;
6167 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6168 if (gotfree_input_line
)
6169 input_line_pointer
= gotfree_input_line
;
6173 if (gotfree_input_line
)
6175 /* expression () has merrily parsed up to the end of line,
6176 or a comma - in the wrong buffer. Transfer how far
6177 input_line_pointer has moved to the right buffer. */
6178 input_line_pointer
= (save
6179 + (input_line_pointer
- gotfree_input_line
)
6181 free (gotfree_input_line
);
6182 if (exp
->X_op
== O_constant
6183 || exp
->X_op
== O_absent
6184 || exp
->X_op
== O_illegal
6185 || exp
->X_op
== O_register
6186 || exp
->X_op
== O_big
)
6188 char c
= *input_line_pointer
;
6189 *input_line_pointer
= 0;
6190 as_bad (_("missing or invalid expression `%s'"), save
);
6191 *input_line_pointer
= c
;
6198 intel_syntax
= -intel_syntax
;
6201 i386_intel_simplify (exp
);
6206 signed_cons (int size
)
6208 if (flag_code
== CODE_64BIT
)
6216 pe_directive_secrel (dummy
)
6217 int dummy ATTRIBUTE_UNUSED
;
6224 if (exp
.X_op
== O_symbol
)
6225 exp
.X_op
= O_secrel
;
6227 emit_expr (&exp
, 4);
6229 while (*input_line_pointer
++ == ',');
6231 input_line_pointer
--;
6232 demand_empty_rest_of_line ();
6237 i386_immediate (char *imm_start
)
6239 char *save_input_line_pointer
;
6240 char *gotfree_input_line
;
6243 i386_operand_type types
;
6245 operand_type_set (&types
, ~0);
6247 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6249 as_bad (_("at most %d immediate operands are allowed"),
6250 MAX_IMMEDIATE_OPERANDS
);
6254 exp
= &im_expressions
[i
.imm_operands
++];
6255 i
.op
[this_operand
].imms
= exp
;
6257 if (is_space_char (*imm_start
))
6260 save_input_line_pointer
= input_line_pointer
;
6261 input_line_pointer
= imm_start
;
6263 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6264 if (gotfree_input_line
)
6265 input_line_pointer
= gotfree_input_line
;
6267 exp_seg
= expression (exp
);
6270 if (*input_line_pointer
)
6271 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6273 input_line_pointer
= save_input_line_pointer
;
6274 if (gotfree_input_line
)
6276 free (gotfree_input_line
);
6278 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6279 exp
->X_op
= O_illegal
;
6282 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6286 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6287 i386_operand_type types
, const char *imm_start
)
6289 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6292 as_bad (_("missing or invalid immediate expression `%s'"),
6296 else if (exp
->X_op
== O_constant
)
6298 /* Size it properly later. */
6299 i
.types
[this_operand
].bitfield
.imm64
= 1;
6300 /* If BFD64, sign extend val. */
6301 if (!use_rela_relocations
6302 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6304 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6306 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6307 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6308 && exp_seg
!= absolute_section
6309 && exp_seg
!= text_section
6310 && exp_seg
!= data_section
6311 && exp_seg
!= bss_section
6312 && exp_seg
!= undefined_section
6313 && !bfd_is_com_section (exp_seg
))
6315 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6319 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6322 as_bad (_("illegal immediate register operand %s"), imm_start
);
6327 /* This is an address. The size of the address will be
6328 determined later, depending on destination register,
6329 suffix, or the default for the section. */
6330 i
.types
[this_operand
].bitfield
.imm8
= 1;
6331 i
.types
[this_operand
].bitfield
.imm16
= 1;
6332 i
.types
[this_operand
].bitfield
.imm32
= 1;
6333 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6334 i
.types
[this_operand
].bitfield
.imm64
= 1;
6335 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6343 i386_scale (char *scale
)
6346 char *save
= input_line_pointer
;
6348 input_line_pointer
= scale
;
6349 val
= get_absolute_expression ();
6354 i
.log2_scale_factor
= 0;
6357 i
.log2_scale_factor
= 1;
6360 i
.log2_scale_factor
= 2;
6363 i
.log2_scale_factor
= 3;
6367 char sep
= *input_line_pointer
;
6369 *input_line_pointer
= '\0';
6370 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6372 *input_line_pointer
= sep
;
6373 input_line_pointer
= save
;
6377 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6379 as_warn (_("scale factor of %d without an index register"),
6380 1 << i
.log2_scale_factor
);
6381 i
.log2_scale_factor
= 0;
6383 scale
= input_line_pointer
;
6384 input_line_pointer
= save
;
6389 i386_displacement (char *disp_start
, char *disp_end
)
6393 char *save_input_line_pointer
;
6394 char *gotfree_input_line
;
6396 i386_operand_type bigdisp
, types
= anydisp
;
6399 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6401 as_bad (_("at most %d displacement operands are allowed"),
6402 MAX_MEMORY_OPERANDS
);
6406 operand_type_set (&bigdisp
, 0);
6407 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6408 || (!current_templates
->start
->opcode_modifier
.jump
6409 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6411 bigdisp
.bitfield
.disp32
= 1;
6412 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6413 if (flag_code
== CODE_64BIT
)
6417 bigdisp
.bitfield
.disp32s
= 1;
6418 bigdisp
.bitfield
.disp64
= 1;
6421 else if ((flag_code
== CODE_16BIT
) ^ override
)
6423 bigdisp
.bitfield
.disp32
= 0;
6424 bigdisp
.bitfield
.disp16
= 1;
6429 /* For PC-relative branches, the width of the displacement
6430 is dependent upon data size, not address size. */
6431 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6432 if (flag_code
== CODE_64BIT
)
6434 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6435 bigdisp
.bitfield
.disp16
= 1;
6438 bigdisp
.bitfield
.disp32
= 1;
6439 bigdisp
.bitfield
.disp32s
= 1;
6445 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6447 : LONG_MNEM_SUFFIX
));
6448 bigdisp
.bitfield
.disp32
= 1;
6449 if ((flag_code
== CODE_16BIT
) ^ override
)
6451 bigdisp
.bitfield
.disp32
= 0;
6452 bigdisp
.bitfield
.disp16
= 1;
6456 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6459 exp
= &disp_expressions
[i
.disp_operands
];
6460 i
.op
[this_operand
].disps
= exp
;
6462 save_input_line_pointer
= input_line_pointer
;
6463 input_line_pointer
= disp_start
;
6464 END_STRING_AND_SAVE (disp_end
);
6466 #ifndef GCC_ASM_O_HACK
6467 #define GCC_ASM_O_HACK 0
6470 END_STRING_AND_SAVE (disp_end
+ 1);
6471 if (i
.types
[this_operand
].bitfield
.baseIndex
6472 && displacement_string_end
[-1] == '+')
6474 /* This hack is to avoid a warning when using the "o"
6475 constraint within gcc asm statements.
6478 #define _set_tssldt_desc(n,addr,limit,type) \
6479 __asm__ __volatile__ ( \
6481 "movw %w1,2+%0\n\t" \
6483 "movb %b1,4+%0\n\t" \
6484 "movb %4,5+%0\n\t" \
6485 "movb $0,6+%0\n\t" \
6486 "movb %h1,7+%0\n\t" \
6488 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6490 This works great except that the output assembler ends
6491 up looking a bit weird if it turns out that there is
6492 no offset. You end up producing code that looks like:
6505 So here we provide the missing zero. */
6507 *displacement_string_end
= '0';
6510 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6511 if (gotfree_input_line
)
6512 input_line_pointer
= gotfree_input_line
;
6514 exp_seg
= expression (exp
);
6517 if (*input_line_pointer
)
6518 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6520 RESTORE_END_STRING (disp_end
+ 1);
6522 input_line_pointer
= save_input_line_pointer
;
6523 if (gotfree_input_line
)
6525 free (gotfree_input_line
);
6527 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6528 exp
->X_op
= O_illegal
;
6531 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6533 RESTORE_END_STRING (disp_end
);
6539 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6540 i386_operand_type types
, const char *disp_start
)
6542 i386_operand_type bigdisp
;
6545 /* We do this to make sure that the section symbol is in
6546 the symbol table. We will ultimately change the relocation
6547 to be relative to the beginning of the section. */
6548 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6549 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6550 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6552 if (exp
->X_op
!= O_symbol
)
6555 if (S_IS_LOCAL (exp
->X_add_symbol
)
6556 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6557 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6558 exp
->X_op
= O_subtract
;
6559 exp
->X_op_symbol
= GOT_symbol
;
6560 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6561 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6562 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6563 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6565 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6568 else if (exp
->X_op
== O_absent
6569 || exp
->X_op
== O_illegal
6570 || exp
->X_op
== O_big
)
6573 as_bad (_("missing or invalid displacement expression `%s'"),
6578 else if (flag_code
== CODE_64BIT
6579 && !i
.prefix
[ADDR_PREFIX
]
6580 && exp
->X_op
== O_constant
)
6582 /* Since displacement is signed extended to 64bit, don't allow
6583 disp32 and turn off disp32s if they are out of range. */
6584 i
.types
[this_operand
].bitfield
.disp32
= 0;
6585 if (!fits_in_signed_long (exp
->X_add_number
))
6587 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6588 if (i
.types
[this_operand
].bitfield
.baseindex
)
6590 as_bad (_("0x%lx out range of signed 32bit displacement"),
6591 (long) exp
->X_add_number
);
6597 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6598 else if (exp
->X_op
!= O_constant
6599 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6600 && exp_seg
!= absolute_section
6601 && exp_seg
!= text_section
6602 && exp_seg
!= data_section
6603 && exp_seg
!= bss_section
6604 && exp_seg
!= undefined_section
6605 && !bfd_is_com_section (exp_seg
))
6607 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6612 /* Check if this is a displacement only operand. */
6613 bigdisp
= i
.types
[this_operand
];
6614 bigdisp
.bitfield
.disp8
= 0;
6615 bigdisp
.bitfield
.disp16
= 0;
6616 bigdisp
.bitfield
.disp32
= 0;
6617 bigdisp
.bitfield
.disp32s
= 0;
6618 bigdisp
.bitfield
.disp64
= 0;
6619 if (operand_type_all_zero (&bigdisp
))
6620 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6626 /* Make sure the memory operand we've been dealt is valid.
6627 Return 1 on success, 0 on a failure. */
6630 i386_index_check (const char *operand_string
)
6633 const char *kind
= "base/index";
6634 #if INFER_ADDR_PREFIX
6640 if (current_templates
->start
->opcode_modifier
.isstring
6641 && !current_templates
->start
->opcode_modifier
.immext
6642 && (current_templates
->end
[-1].opcode_modifier
.isstring
6645 /* Memory operands of string insns are special in that they only allow
6646 a single register (rDI, rSI, or rBX) as their memory address. */
6647 unsigned int expected
;
6649 kind
= "string address";
6651 if (current_templates
->start
->opcode_modifier
.w
)
6653 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6655 if (!type
.bitfield
.baseindex
6656 || ((!i
.mem_operands
!= !intel_syntax
)
6657 && current_templates
->end
[-1].operand_types
[1]
6658 .bitfield
.baseindex
))
6659 type
= current_templates
->end
[-1].operand_types
[1];
6660 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6663 expected
= 3 /* rBX */;
6665 if (!i
.base_reg
|| i
.index_reg
6666 || operand_type_check (i
.types
[this_operand
], disp
))
6668 else if (!(flag_code
== CODE_64BIT
6669 ? i
.prefix
[ADDR_PREFIX
]
6670 ? i
.base_reg
->reg_type
.bitfield
.reg32
6671 : i
.base_reg
->reg_type
.bitfield
.reg64
6672 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6673 ? i
.base_reg
->reg_type
.bitfield
.reg32
6674 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6676 else if (i
.base_reg
->reg_num
!= expected
)
6683 for (j
= 0; j
< i386_regtab_size
; ++j
)
6684 if ((flag_code
== CODE_64BIT
6685 ? i
.prefix
[ADDR_PREFIX
]
6686 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6687 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6688 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6689 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6690 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6691 && i386_regtab
[j
].reg_num
== expected
)
6693 gas_assert (j
< i386_regtab_size
);
6694 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6696 intel_syntax
? '[' : '(',
6698 i386_regtab
[j
].reg_name
,
6699 intel_syntax
? ']' : ')');
6703 else if (flag_code
== CODE_64BIT
)
6706 && ((i
.prefix
[ADDR_PREFIX
] == 0
6707 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6708 || (i
.prefix
[ADDR_PREFIX
]
6709 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6711 || i
.base_reg
->reg_num
!=
6712 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6714 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6715 || (i
.prefix
[ADDR_PREFIX
] == 0
6716 && i
.index_reg
->reg_num
!= RegRiz
6717 && !i
.index_reg
->reg_type
.bitfield
.reg64
6719 || (i
.prefix
[ADDR_PREFIX
]
6720 && i
.index_reg
->reg_num
!= RegEiz
6721 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6726 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6730 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6731 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6733 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6734 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6736 && i
.base_reg
->reg_num
< 6
6737 && i
.index_reg
->reg_num
>= 6
6738 && i
.log2_scale_factor
== 0))))
6745 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6747 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6748 && i
.index_reg
->reg_num
!= RegEiz
)
6749 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6755 #if INFER_ADDR_PREFIX
6756 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6758 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6760 /* Change the size of any displacement too. At most one of
6761 Disp16 or Disp32 is set.
6762 FIXME. There doesn't seem to be any real need for separate
6763 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6764 Removing them would probably clean up the code quite a lot. */
6765 if (flag_code
!= CODE_64BIT
6766 && (i
.types
[this_operand
].bitfield
.disp16
6767 || i
.types
[this_operand
].bitfield
.disp32
))
6768 i
.types
[this_operand
]
6769 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6774 as_bad (_("`%s' is not a valid %s expression"),
6779 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6781 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6782 ? flag_code
== CODE_32BIT
6791 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6795 i386_att_operand (char *operand_string
)
6799 char *op_string
= operand_string
;
6801 if (is_space_char (*op_string
))
6804 /* We check for an absolute prefix (differentiating,
6805 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6806 if (*op_string
== ABSOLUTE_PREFIX
)
6809 if (is_space_char (*op_string
))
6811 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6814 /* Check if operand is a register. */
6815 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6817 i386_operand_type temp
;
6819 /* Check for a segment override by searching for ':' after a
6820 segment register. */
6822 if (is_space_char (*op_string
))
6824 if (*op_string
== ':'
6825 && (r
->reg_type
.bitfield
.sreg2
6826 || r
->reg_type
.bitfield
.sreg3
))
6831 i
.seg
[i
.mem_operands
] = &es
;
6834 i
.seg
[i
.mem_operands
] = &cs
;
6837 i
.seg
[i
.mem_operands
] = &ss
;
6840 i
.seg
[i
.mem_operands
] = &ds
;
6843 i
.seg
[i
.mem_operands
] = &fs
;
6846 i
.seg
[i
.mem_operands
] = &gs
;
6850 /* Skip the ':' and whitespace. */
6852 if (is_space_char (*op_string
))
6855 if (!is_digit_char (*op_string
)
6856 && !is_identifier_char (*op_string
)
6857 && *op_string
!= '('
6858 && *op_string
!= ABSOLUTE_PREFIX
)
6860 as_bad (_("bad memory operand `%s'"), op_string
);
6863 /* Handle case of %es:*foo. */
6864 if (*op_string
== ABSOLUTE_PREFIX
)
6867 if (is_space_char (*op_string
))
6869 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6871 goto do_memory_reference
;
6875 as_bad (_("junk `%s' after register"), op_string
);
6879 temp
.bitfield
.baseindex
= 0;
6880 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6882 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6883 i
.op
[this_operand
].regs
= r
;
6886 else if (*op_string
== REGISTER_PREFIX
)
6888 as_bad (_("bad register name `%s'"), op_string
);
6891 else if (*op_string
== IMMEDIATE_PREFIX
)
6894 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6896 as_bad (_("immediate operand illegal with absolute jump"));
6899 if (!i386_immediate (op_string
))
6902 else if (is_digit_char (*op_string
)
6903 || is_identifier_char (*op_string
)
6904 || *op_string
== '(')
6906 /* This is a memory reference of some sort. */
6909 /* Start and end of displacement string expression (if found). */
6910 char *displacement_string_start
;
6911 char *displacement_string_end
;
6913 do_memory_reference
:
6914 if ((i
.mem_operands
== 1
6915 && !current_templates
->start
->opcode_modifier
.isstring
)
6916 || i
.mem_operands
== 2)
6918 as_bad (_("too many memory references for `%s'"),
6919 current_templates
->start
->name
);
6923 /* Check for base index form. We detect the base index form by
6924 looking for an ')' at the end of the operand, searching
6925 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6927 base_string
= op_string
+ strlen (op_string
);
6930 if (is_space_char (*base_string
))
6933 /* If we only have a displacement, set-up for it to be parsed later. */
6934 displacement_string_start
= op_string
;
6935 displacement_string_end
= base_string
+ 1;
6937 if (*base_string
== ')')
6940 unsigned int parens_balanced
= 1;
6941 /* We've already checked that the number of left & right ()'s are
6942 equal, so this loop will not be infinite. */
6946 if (*base_string
== ')')
6948 if (*base_string
== '(')
6951 while (parens_balanced
);
6953 temp_string
= base_string
;
6955 /* Skip past '(' and whitespace. */
6957 if (is_space_char (*base_string
))
6960 if (*base_string
== ','
6961 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6964 displacement_string_end
= temp_string
;
6966 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6970 base_string
= end_op
;
6971 if (is_space_char (*base_string
))
6975 /* There may be an index reg or scale factor here. */
6976 if (*base_string
== ',')
6979 if (is_space_char (*base_string
))
6982 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6985 base_string
= end_op
;
6986 if (is_space_char (*base_string
))
6988 if (*base_string
== ',')
6991 if (is_space_char (*base_string
))
6994 else if (*base_string
!= ')')
6996 as_bad (_("expecting `,' or `)' "
6997 "after index register in `%s'"),
7002 else if (*base_string
== REGISTER_PREFIX
)
7004 as_bad (_("bad register name `%s'"), base_string
);
7008 /* Check for scale factor. */
7009 if (*base_string
!= ')')
7011 char *end_scale
= i386_scale (base_string
);
7016 base_string
= end_scale
;
7017 if (is_space_char (*base_string
))
7019 if (*base_string
!= ')')
7021 as_bad (_("expecting `)' "
7022 "after scale factor in `%s'"),
7027 else if (!i
.index_reg
)
7029 as_bad (_("expecting index register or scale factor "
7030 "after `,'; got '%c'"),
7035 else if (*base_string
!= ')')
7037 as_bad (_("expecting `,' or `)' "
7038 "after base register in `%s'"),
7043 else if (*base_string
== REGISTER_PREFIX
)
7045 as_bad (_("bad register name `%s'"), base_string
);
7050 /* If there's an expression beginning the operand, parse it,
7051 assuming displacement_string_start and
7052 displacement_string_end are meaningful. */
7053 if (displacement_string_start
!= displacement_string_end
)
7055 if (!i386_displacement (displacement_string_start
,
7056 displacement_string_end
))
7060 /* Special case for (%dx) while doing input/output op. */
7062 && operand_type_equal (&i
.base_reg
->reg_type
,
7063 ®16_inoutportreg
)
7065 && i
.log2_scale_factor
== 0
7066 && i
.seg
[i
.mem_operands
] == 0
7067 && !operand_type_check (i
.types
[this_operand
], disp
))
7069 i
.types
[this_operand
] = inoutportreg
;
7073 if (i386_index_check (operand_string
) == 0)
7075 i
.types
[this_operand
].bitfield
.mem
= 1;
7080 /* It's not a memory operand; argh! */
7081 as_bad (_("invalid char %s beginning operand %d `%s'"),
7082 output_invalid (*op_string
),
7087 return 1; /* Normal return. */
7090 /* md_estimate_size_before_relax()
7092 Called just before relax() for rs_machine_dependent frags. The x86
7093 assembler uses these frags to handle variable size jump
7096 Any symbol that is now undefined will not become defined.
7097 Return the correct fr_subtype in the frag.
7098 Return the initial "guess for variable size of frag" to caller.
7099 The guess is actually the growth beyond the fixed part. Whatever
7100 we do to grow the fixed or variable part contributes to our
7104 md_estimate_size_before_relax (fragP
, segment
)
7108 /* We've already got fragP->fr_subtype right; all we have to do is
7109 check for un-relaxable symbols. On an ELF system, we can't relax
7110 an externally visible symbol, because it may be overridden by a
7112 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7113 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7115 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7116 || S_IS_WEAK (fragP
->fr_symbol
)
7117 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7118 & BSF_GNU_INDIRECT_FUNCTION
))))
7120 #if defined (OBJ_COFF) && defined (TE_PE)
7121 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7122 && S_IS_WEAK (fragP
->fr_symbol
))
7126 /* Symbol is undefined in this segment, or we need to keep a
7127 reloc so that weak symbols can be overridden. */
7128 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7129 enum bfd_reloc_code_real reloc_type
;
7130 unsigned char *opcode
;
7133 if (fragP
->fr_var
!= NO_RELOC
)
7134 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7136 reloc_type
= BFD_RELOC_16_PCREL
;
7138 reloc_type
= BFD_RELOC_32_PCREL
;
7140 old_fr_fix
= fragP
->fr_fix
;
7141 opcode
= (unsigned char *) fragP
->fr_opcode
;
7143 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7146 /* Make jmp (0xeb) a (d)word displacement jump. */
7148 fragP
->fr_fix
+= size
;
7149 fix_new (fragP
, old_fr_fix
, size
,
7151 fragP
->fr_offset
, 1,
7157 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7159 /* Negate the condition, and branch past an
7160 unconditional jump. */
7163 /* Insert an unconditional jump. */
7165 /* We added two extra opcode bytes, and have a two byte
7167 fragP
->fr_fix
+= 2 + 2;
7168 fix_new (fragP
, old_fr_fix
+ 2, 2,
7170 fragP
->fr_offset
, 1,
7177 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7182 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7184 fragP
->fr_offset
, 1,
7186 fixP
->fx_signed
= 1;
7190 /* This changes the byte-displacement jump 0x7N
7191 to the (d)word-displacement jump 0x0f,0x8N. */
7192 opcode
[1] = opcode
[0] + 0x10;
7193 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7194 /* We've added an opcode byte. */
7195 fragP
->fr_fix
+= 1 + size
;
7196 fix_new (fragP
, old_fr_fix
+ 1, size
,
7198 fragP
->fr_offset
, 1,
7203 BAD_CASE (fragP
->fr_subtype
);
7207 return fragP
->fr_fix
- old_fr_fix
;
7210 /* Guess size depending on current relax state. Initially the relax
7211 state will correspond to a short jump and we return 1, because
7212 the variable part of the frag (the branch offset) is one byte
7213 long. However, we can relax a section more than once and in that
7214 case we must either set fr_subtype back to the unrelaxed state,
7215 or return the value for the appropriate branch. */
7216 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7219 /* Called after relax() is finished.
7221 In: Address of frag.
7222 fr_type == rs_machine_dependent.
7223 fr_subtype is what the address relaxed to.
7225 Out: Any fixSs and constants are set up.
7226 Caller will turn frag into a ".space 0". */
7229 md_convert_frag (abfd
, sec
, fragP
)
7230 bfd
*abfd ATTRIBUTE_UNUSED
;
7231 segT sec ATTRIBUTE_UNUSED
;
7234 unsigned char *opcode
;
7235 unsigned char *where_to_put_displacement
= NULL
;
7236 offsetT target_address
;
7237 offsetT opcode_address
;
7238 unsigned int extension
= 0;
7239 offsetT displacement_from_opcode_start
;
7241 opcode
= (unsigned char *) fragP
->fr_opcode
;
7243 /* Address we want to reach in file space. */
7244 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7246 /* Address opcode resides at in file space. */
7247 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7249 /* Displacement from opcode start to fill into instruction. */
7250 displacement_from_opcode_start
= target_address
- opcode_address
;
7252 if ((fragP
->fr_subtype
& BIG
) == 0)
7254 /* Don't have to change opcode. */
7255 extension
= 1; /* 1 opcode + 1 displacement */
7256 where_to_put_displacement
= &opcode
[1];
7260 if (no_cond_jump_promotion
7261 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7262 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7263 _("long jump required"));
7265 switch (fragP
->fr_subtype
)
7267 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7268 extension
= 4; /* 1 opcode + 4 displacement */
7270 where_to_put_displacement
= &opcode
[1];
7273 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7274 extension
= 2; /* 1 opcode + 2 displacement */
7276 where_to_put_displacement
= &opcode
[1];
7279 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7280 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7281 extension
= 5; /* 2 opcode + 4 displacement */
7282 opcode
[1] = opcode
[0] + 0x10;
7283 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7284 where_to_put_displacement
= &opcode
[2];
7287 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7288 extension
= 3; /* 2 opcode + 2 displacement */
7289 opcode
[1] = opcode
[0] + 0x10;
7290 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7291 where_to_put_displacement
= &opcode
[2];
7294 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7299 where_to_put_displacement
= &opcode
[3];
7303 BAD_CASE (fragP
->fr_subtype
);
7308 /* If size if less then four we are sure that the operand fits,
7309 but if it's 4, then it could be that the displacement is larger
7311 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7313 && ((addressT
) (displacement_from_opcode_start
- extension
7314 + ((addressT
) 1 << 31))
7315 > (((addressT
) 2 << 31) - 1)))
7317 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7318 _("jump target out of range"));
7319 /* Make us emit 0. */
7320 displacement_from_opcode_start
= extension
;
7322 /* Now put displacement after opcode. */
7323 md_number_to_chars ((char *) where_to_put_displacement
,
7324 (valueT
) (displacement_from_opcode_start
- extension
),
7325 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7326 fragP
->fr_fix
+= extension
;
7329 /* Apply a fixup (fixS) to segment data, once it has been determined
7330 by our caller that we have all the info we need to fix it up.
7332 On the 386, immediates, displacements, and data pointers are all in
7333 the same (little-endian) format, so we don't need to care about which
7337 md_apply_fix (fixP
, valP
, seg
)
7338 /* The fix we're to put in. */
7340 /* Pointer to the value of the bits. */
7342 /* Segment fix is from. */
7343 segT seg ATTRIBUTE_UNUSED
;
7345 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7346 valueT value
= *valP
;
7348 #if !defined (TE_Mach)
7351 switch (fixP
->fx_r_type
)
7357 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7360 case BFD_RELOC_X86_64_32S
:
7361 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7364 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7367 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7372 if (fixP
->fx_addsy
!= NULL
7373 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7374 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7375 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7376 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7377 && !use_rela_relocations
)
7379 /* This is a hack. There should be a better way to handle this.
7380 This covers for the fact that bfd_install_relocation will
7381 subtract the current location (for partial_inplace, PC relative
7382 relocations); see more below. */
7386 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7389 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7391 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7394 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7397 || (symbol_section_p (fixP
->fx_addsy
)
7398 && sym_seg
!= absolute_section
))
7399 && !generic_force_reloc (fixP
))
7401 /* Yes, we add the values in twice. This is because
7402 bfd_install_relocation subtracts them out again. I think
7403 bfd_install_relocation is broken, but I don't dare change
7405 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7409 #if defined (OBJ_COFF) && defined (TE_PE)
7410 /* For some reason, the PE format does not store a
7411 section address offset for a PC relative symbol. */
7412 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7413 || S_IS_WEAK (fixP
->fx_addsy
))
7414 value
+= md_pcrel_from (fixP
);
7417 #if defined (OBJ_COFF) && defined (TE_PE)
7418 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7420 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7424 /* Fix a few things - the dynamic linker expects certain values here,
7425 and we must not disappoint it. */
7426 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7427 if (IS_ELF
&& fixP
->fx_addsy
)
7428 switch (fixP
->fx_r_type
)
7430 case BFD_RELOC_386_PLT32
:
7431 case BFD_RELOC_X86_64_PLT32
:
7432 /* Make the jump instruction point to the address of the operand. At
7433 runtime we merely add the offset to the actual PLT entry. */
7437 case BFD_RELOC_386_TLS_GD
:
7438 case BFD_RELOC_386_TLS_LDM
:
7439 case BFD_RELOC_386_TLS_IE_32
:
7440 case BFD_RELOC_386_TLS_IE
:
7441 case BFD_RELOC_386_TLS_GOTIE
:
7442 case BFD_RELOC_386_TLS_GOTDESC
:
7443 case BFD_RELOC_X86_64_TLSGD
:
7444 case BFD_RELOC_X86_64_TLSLD
:
7445 case BFD_RELOC_X86_64_GOTTPOFF
:
7446 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7447 value
= 0; /* Fully resolved at runtime. No addend. */
7449 case BFD_RELOC_386_TLS_LE
:
7450 case BFD_RELOC_386_TLS_LDO_32
:
7451 case BFD_RELOC_386_TLS_LE_32
:
7452 case BFD_RELOC_X86_64_DTPOFF32
:
7453 case BFD_RELOC_X86_64_DTPOFF64
:
7454 case BFD_RELOC_X86_64_TPOFF32
:
7455 case BFD_RELOC_X86_64_TPOFF64
:
7456 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7459 case BFD_RELOC_386_TLS_DESC_CALL
:
7460 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7461 value
= 0; /* Fully resolved at runtime. No addend. */
7462 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7466 case BFD_RELOC_386_GOT32
:
7467 case BFD_RELOC_X86_64_GOT32
:
7468 value
= 0; /* Fully resolved at runtime. No addend. */
7471 case BFD_RELOC_VTABLE_INHERIT
:
7472 case BFD_RELOC_VTABLE_ENTRY
:
7479 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7481 #endif /* !defined (TE_Mach) */
7483 /* Are we finished with this relocation now? */
7484 if (fixP
->fx_addsy
== NULL
)
7486 #if defined (OBJ_COFF) && defined (TE_PE)
7487 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7490 /* Remember value for tc_gen_reloc. */
7491 fixP
->fx_addnumber
= value
;
7492 /* Clear out the frag for now. */
7496 else if (use_rela_relocations
)
7498 fixP
->fx_no_overflow
= 1;
7499 /* Remember value for tc_gen_reloc. */
7500 fixP
->fx_addnumber
= value
;
7504 md_number_to_chars (p
, value
, fixP
->fx_size
);
7508 md_atof (int type
, char *litP
, int *sizeP
)
7510 /* This outputs the LITTLENUMs in REVERSE order;
7511 in accord with the bigendian 386. */
7512 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7515 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7518 output_invalid (int c
)
7521 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7524 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7525 "(0x%x)", (unsigned char) c
);
7526 return output_invalid_buf
;
7529 /* REG_STRING starts *before* REGISTER_PREFIX. */
7531 static const reg_entry
*
7532 parse_real_register (char *reg_string
, char **end_op
)
7534 char *s
= reg_string
;
7536 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7539 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7540 if (*s
== REGISTER_PREFIX
)
7543 if (is_space_char (*s
))
7547 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7549 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7550 return (const reg_entry
*) NULL
;
7554 /* For naked regs, make sure that we are not dealing with an identifier.
7555 This prevents confusing an identifier like `eax_var' with register
7557 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7558 return (const reg_entry
*) NULL
;
7562 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7564 /* Handle floating point regs, allowing spaces in the (i) part. */
7565 if (r
== i386_regtab
/* %st is first entry of table */)
7567 if (is_space_char (*s
))
7572 if (is_space_char (*s
))
7574 if (*s
>= '0' && *s
<= '7')
7578 if (is_space_char (*s
))
7583 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7588 /* We have "%st(" then garbage. */
7589 return (const reg_entry
*) NULL
;
7593 if (r
== NULL
|| allow_pseudo_reg
)
7596 if (operand_type_all_zero (&r
->reg_type
))
7597 return (const reg_entry
*) NULL
;
7599 if ((r
->reg_type
.bitfield
.reg32
7600 || r
->reg_type
.bitfield
.sreg3
7601 || r
->reg_type
.bitfield
.control
7602 || r
->reg_type
.bitfield
.debug
7603 || r
->reg_type
.bitfield
.test
)
7604 && !cpu_arch_flags
.bitfield
.cpui386
)
7605 return (const reg_entry
*) NULL
;
7607 if (r
->reg_type
.bitfield
.floatreg
7608 && !cpu_arch_flags
.bitfield
.cpu8087
7609 && !cpu_arch_flags
.bitfield
.cpu287
7610 && !cpu_arch_flags
.bitfield
.cpu387
)
7611 return (const reg_entry
*) NULL
;
7613 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7614 return (const reg_entry
*) NULL
;
7616 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7617 return (const reg_entry
*) NULL
;
7619 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7620 return (const reg_entry
*) NULL
;
7622 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7623 if (!allow_index_reg
7624 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7625 return (const reg_entry
*) NULL
;
7627 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7628 || r
->reg_type
.bitfield
.reg64
)
7629 && (!cpu_arch_flags
.bitfield
.cpulm
7630 || !operand_type_equal (&r
->reg_type
, &control
))
7631 && flag_code
!= CODE_64BIT
)
7632 return (const reg_entry
*) NULL
;
7634 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7635 return (const reg_entry
*) NULL
;
7640 /* REG_STRING starts *before* REGISTER_PREFIX. */
7642 static const reg_entry
*
7643 parse_register (char *reg_string
, char **end_op
)
7647 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7648 r
= parse_real_register (reg_string
, end_op
);
7653 char *save
= input_line_pointer
;
7657 input_line_pointer
= reg_string
;
7658 c
= get_symbol_end ();
7659 symbolP
= symbol_find (reg_string
);
7660 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7662 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7664 know (e
->X_op
== O_register
);
7665 know (e
->X_add_number
>= 0
7666 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7667 r
= i386_regtab
+ e
->X_add_number
;
7668 *end_op
= input_line_pointer
;
7670 *input_line_pointer
= c
;
7671 input_line_pointer
= save
;
7677 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7680 char *end
= input_line_pointer
;
7683 r
= parse_register (name
, &input_line_pointer
);
7684 if (r
&& end
<= input_line_pointer
)
7686 *nextcharP
= *input_line_pointer
;
7687 *input_line_pointer
= 0;
7688 e
->X_op
= O_register
;
7689 e
->X_add_number
= r
- i386_regtab
;
7692 input_line_pointer
= end
;
7694 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7698 md_operand (expressionS
*e
)
7703 switch (*input_line_pointer
)
7705 case REGISTER_PREFIX
:
7706 r
= parse_real_register (input_line_pointer
, &end
);
7709 e
->X_op
= O_register
;
7710 e
->X_add_number
= r
- i386_regtab
;
7711 input_line_pointer
= end
;
7716 gas_assert (intel_syntax
);
7717 end
= input_line_pointer
++;
7719 if (*input_line_pointer
== ']')
7721 ++input_line_pointer
;
7722 e
->X_op_symbol
= make_expr_symbol (e
);
7723 e
->X_add_symbol
= NULL
;
7724 e
->X_add_number
= 0;
7730 input_line_pointer
= end
;
7737 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7738 const char *md_shortopts
= "kVQ:sqn";
7740 const char *md_shortopts
= "qn";
7743 #define OPTION_32 (OPTION_MD_BASE + 0)
7744 #define OPTION_64 (OPTION_MD_BASE + 1)
7745 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7746 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7747 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7748 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7749 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7750 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7751 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7752 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7753 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7754 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7756 struct option md_longopts
[] =
7758 {"32", no_argument
, NULL
, OPTION_32
},
7759 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7760 || defined (TE_PE) || defined (TE_PEP))
7761 {"64", no_argument
, NULL
, OPTION_64
},
7763 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7764 {"march", required_argument
, NULL
, OPTION_MARCH
},
7765 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7766 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7767 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7768 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7769 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7770 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7771 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7772 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7773 {NULL
, no_argument
, NULL
, 0}
7775 size_t md_longopts_size
= sizeof (md_longopts
);
7778 md_parse_option (int c
, char *arg
)
7786 optimize_align_code
= 0;
7793 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7794 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7795 should be emitted or not. FIXME: Not implemented. */
7799 /* -V: SVR4 argument to print version ID. */
7801 print_version_id ();
7804 /* -k: Ignore for FreeBSD compatibility. */
7809 /* -s: On i386 Solaris, this tells the native assembler to use
7810 .stab instead of .stab.excl. We always use .stab anyhow. */
7813 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7814 || defined (TE_PE) || defined (TE_PEP))
7817 const char **list
, **l
;
7819 list
= bfd_target_list ();
7820 for (l
= list
; *l
!= NULL
; l
++)
7821 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7822 || strcmp (*l
, "coff-x86-64") == 0
7823 || strcmp (*l
, "pe-x86-64") == 0
7824 || strcmp (*l
, "pei-x86-64") == 0)
7826 default_arch
= "x86_64";
7830 as_fatal (_("No compiled in support for x86_64"));
7837 default_arch
= "i386";
7841 #ifdef SVR4_COMMENT_CHARS
7846 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7848 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7852 i386_comment_chars
= n
;
7858 arch
= xstrdup (arg
);
7862 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7863 next
= strchr (arch
, '+');
7866 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7868 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7871 cpu_arch_name
= cpu_arch
[i
].name
;
7872 cpu_sub_arch_name
= NULL
;
7873 cpu_arch_flags
= cpu_arch
[i
].flags
;
7874 cpu_arch_isa
= cpu_arch
[i
].type
;
7875 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7876 if (!cpu_arch_tune_set
)
7878 cpu_arch_tune
= cpu_arch_isa
;
7879 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7883 else if (*cpu_arch
[i
].name
== '.'
7884 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7886 /* ISA entension. */
7887 i386_cpu_flags flags
;
7889 if (strncmp (arch
, "no", 2))
7890 flags
= cpu_flags_or (cpu_arch_flags
,
7893 flags
= cpu_flags_and_not (cpu_arch_flags
,
7895 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7897 if (cpu_sub_arch_name
)
7899 char *name
= cpu_sub_arch_name
;
7900 cpu_sub_arch_name
= concat (name
,
7902 (const char *) NULL
);
7906 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7907 cpu_arch_flags
= flags
;
7913 if (i
>= ARRAY_SIZE (cpu_arch
))
7914 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7918 while (next
!= NULL
);
7923 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7924 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7926 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7928 cpu_arch_tune_set
= 1;
7929 cpu_arch_tune
= cpu_arch
[i
].type
;
7930 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7934 if (i
>= ARRAY_SIZE (cpu_arch
))
7935 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7938 case OPTION_MMNEMONIC
:
7939 if (strcasecmp (arg
, "att") == 0)
7941 else if (strcasecmp (arg
, "intel") == 0)
7944 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7947 case OPTION_MSYNTAX
:
7948 if (strcasecmp (arg
, "att") == 0)
7950 else if (strcasecmp (arg
, "intel") == 0)
7953 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7956 case OPTION_MINDEX_REG
:
7957 allow_index_reg
= 1;
7960 case OPTION_MNAKED_REG
:
7961 allow_naked_reg
= 1;
7964 case OPTION_MOLD_GCC
:
7968 case OPTION_MSSE2AVX
:
7972 case OPTION_MSSE_CHECK
:
7973 if (strcasecmp (arg
, "error") == 0)
7974 sse_check
= sse_check_error
;
7975 else if (strcasecmp (arg
, "warning") == 0)
7976 sse_check
= sse_check_warning
;
7977 else if (strcasecmp (arg
, "none") == 0)
7978 sse_check
= sse_check_none
;
7980 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7990 md_show_usage (stream
)
7993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7994 fprintf (stream
, _("\
7996 -V print assembler version number\n\
7999 fprintf (stream
, _("\
8000 -n Do not optimize code alignment\n\
8001 -q quieten some warnings\n"));
8002 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8003 fprintf (stream
, _("\
8006 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8007 || defined (TE_PE) || defined (TE_PEP))
8008 fprintf (stream
, _("\
8009 --32/--64 generate 32bit/64bit code\n"));
8011 #ifdef SVR4_COMMENT_CHARS
8012 fprintf (stream
, _("\
8013 --divide do not treat `/' as a comment character\n"));
8015 fprintf (stream
, _("\
8016 --divide ignored\n"));
8018 fprintf (stream
, _("\
8019 -march=CPU[,+EXTENSION...]\n\
8020 generate code for CPU and EXTENSION, CPU is one of:\n\
8021 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8022 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8023 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8024 amdfam10, generic32, generic64\n\
8025 EXTENSION is combination of:\n\
8026 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8027 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8028 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8029 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8030 svme, abm, padlock, fma4\n"));
8031 fprintf (stream
, _("\
8032 -mtune=CPU optimize for CPU, CPU is one of:\n\
8033 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8034 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8035 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8036 amdfam10, generic32, generic64\n"));
8037 fprintf (stream
, _("\
8038 -msse2avx encode SSE instructions with VEX prefix\n"));
8039 fprintf (stream
, _("\
8040 -msse-check=[none|error|warning]\n\
8041 check SSE instructions\n"));
8042 fprintf (stream
, _("\
8043 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8044 fprintf (stream
, _("\
8045 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8046 fprintf (stream
, _("\
8047 -mindex-reg support pseudo index registers\n"));
8048 fprintf (stream
, _("\
8049 -mnaked-reg don't require `%%' prefix for registers\n"));
8050 fprintf (stream
, _("\
8051 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8054 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8055 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8056 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8058 /* Pick the target format to use. */
8061 i386_target_format (void)
8063 if (!strcmp (default_arch
, "x86_64"))
8065 set_code_flag (CODE_64BIT
);
8066 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8068 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8069 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8070 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8071 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8072 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8073 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8074 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8075 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8076 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8077 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8078 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8080 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8082 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8083 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8084 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8085 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8086 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8087 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8088 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8089 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8090 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8091 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8094 else if (!strcmp (default_arch
, "i386"))
8096 set_code_flag (CODE_32BIT
);
8097 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8099 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8100 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8101 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8103 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8105 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8106 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8107 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8111 as_fatal (_("Unknown architecture"));
8112 switch (OUTPUT_FLAVOR
)
8114 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8115 case bfd_target_aout_flavour
:
8116 return AOUT_TARGET_FORMAT
;
8118 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8119 # if defined (TE_PE) || defined (TE_PEP)
8120 case bfd_target_coff_flavour
:
8121 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8122 # elif defined (TE_GO32)
8123 case bfd_target_coff_flavour
:
8126 case bfd_target_coff_flavour
:
8130 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8131 case bfd_target_elf_flavour
:
8133 if (flag_code
== CODE_64BIT
)
8136 use_rela_relocations
= 1;
8138 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8140 if (flag_code
!= CODE_64BIT
)
8141 as_fatal (_("Intel L1OM is 64bit only"));
8142 return ELF_TARGET_L1OM_FORMAT
;
8145 return (flag_code
== CODE_64BIT
8146 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8149 #if defined (OBJ_MACH_O)
8150 case bfd_target_mach_o_flavour
:
8151 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8159 #endif /* OBJ_MAYBE_ more than one */
8161 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8163 i386_elf_emit_arch_note (void)
8165 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8168 asection
*seg
= now_seg
;
8169 subsegT subseg
= now_subseg
;
8170 Elf_Internal_Note i_note
;
8171 Elf_External_Note e_note
;
8172 asection
*note_secp
;
8175 /* Create the .note section. */
8176 note_secp
= subseg_new (".note", 0);
8177 bfd_set_section_flags (stdoutput
,
8179 SEC_HAS_CONTENTS
| SEC_READONLY
);
8181 /* Process the arch string. */
8182 len
= strlen (cpu_arch_name
);
8184 i_note
.namesz
= len
+ 1;
8186 i_note
.type
= NT_ARCH
;
8187 p
= frag_more (sizeof (e_note
.namesz
));
8188 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8189 p
= frag_more (sizeof (e_note
.descsz
));
8190 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8191 p
= frag_more (sizeof (e_note
.type
));
8192 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8193 p
= frag_more (len
+ 1);
8194 strcpy (p
, cpu_arch_name
);
8196 frag_align (2, 0, 0);
8198 subseg_set (seg
, subseg
);
8204 md_undefined_symbol (name
)
8207 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8208 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8209 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8210 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8214 if (symbol_find (name
))
8215 as_bad (_("GOT already in symbol table"));
8216 GOT_symbol
= symbol_new (name
, undefined_section
,
8217 (valueT
) 0, &zero_address_frag
);
8224 /* Round up a section size to the appropriate boundary. */
8227 md_section_align (segment
, size
)
8228 segT segment ATTRIBUTE_UNUSED
;
8231 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8232 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8234 /* For a.out, force the section size to be aligned. If we don't do
8235 this, BFD will align it for us, but it will not write out the
8236 final bytes of the section. This may be a bug in BFD, but it is
8237 easier to fix it here since that is how the other a.out targets
8241 align
= bfd_get_section_alignment (stdoutput
, segment
);
8242 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8249 /* On the i386, PC-relative offsets are relative to the start of the
8250 next instruction. That is, the address of the offset, plus its
8251 size, since the offset is always the last part of the insn. */
8254 md_pcrel_from (fixS
*fixP
)
8256 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8262 s_bss (int ignore ATTRIBUTE_UNUSED
)
8266 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8268 obj_elf_section_change_hook ();
8270 temp
= get_absolute_expression ();
8271 subseg_set (bss_section
, (subsegT
) temp
);
8272 demand_empty_rest_of_line ();
8278 i386_validate_fix (fixS
*fixp
)
8280 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8282 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8286 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8291 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8293 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8300 tc_gen_reloc (section
, fixp
)
8301 asection
*section ATTRIBUTE_UNUSED
;
8305 bfd_reloc_code_real_type code
;
8307 switch (fixp
->fx_r_type
)
8309 case BFD_RELOC_X86_64_PLT32
:
8310 case BFD_RELOC_X86_64_GOT32
:
8311 case BFD_RELOC_X86_64_GOTPCREL
:
8312 case BFD_RELOC_386_PLT32
:
8313 case BFD_RELOC_386_GOT32
:
8314 case BFD_RELOC_386_GOTOFF
:
8315 case BFD_RELOC_386_GOTPC
:
8316 case BFD_RELOC_386_TLS_GD
:
8317 case BFD_RELOC_386_TLS_LDM
:
8318 case BFD_RELOC_386_TLS_LDO_32
:
8319 case BFD_RELOC_386_TLS_IE_32
:
8320 case BFD_RELOC_386_TLS_IE
:
8321 case BFD_RELOC_386_TLS_GOTIE
:
8322 case BFD_RELOC_386_TLS_LE_32
:
8323 case BFD_RELOC_386_TLS_LE
:
8324 case BFD_RELOC_386_TLS_GOTDESC
:
8325 case BFD_RELOC_386_TLS_DESC_CALL
:
8326 case BFD_RELOC_X86_64_TLSGD
:
8327 case BFD_RELOC_X86_64_TLSLD
:
8328 case BFD_RELOC_X86_64_DTPOFF32
:
8329 case BFD_RELOC_X86_64_DTPOFF64
:
8330 case BFD_RELOC_X86_64_GOTTPOFF
:
8331 case BFD_RELOC_X86_64_TPOFF32
:
8332 case BFD_RELOC_X86_64_TPOFF64
:
8333 case BFD_RELOC_X86_64_GOTOFF64
:
8334 case BFD_RELOC_X86_64_GOTPC32
:
8335 case BFD_RELOC_X86_64_GOT64
:
8336 case BFD_RELOC_X86_64_GOTPCREL64
:
8337 case BFD_RELOC_X86_64_GOTPC64
:
8338 case BFD_RELOC_X86_64_GOTPLT64
:
8339 case BFD_RELOC_X86_64_PLTOFF64
:
8340 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8341 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8343 case BFD_RELOC_VTABLE_ENTRY
:
8344 case BFD_RELOC_VTABLE_INHERIT
:
8346 case BFD_RELOC_32_SECREL
:
8348 code
= fixp
->fx_r_type
;
8350 case BFD_RELOC_X86_64_32S
:
8351 if (!fixp
->fx_pcrel
)
8353 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8354 code
= fixp
->fx_r_type
;
8360 switch (fixp
->fx_size
)
8363 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8364 _("can not do %d byte pc-relative relocation"),
8366 code
= BFD_RELOC_32_PCREL
;
8368 case 1: code
= BFD_RELOC_8_PCREL
; break;
8369 case 2: code
= BFD_RELOC_16_PCREL
; break;
8370 case 4: code
= BFD_RELOC_32_PCREL
; break;
8372 case 8: code
= BFD_RELOC_64_PCREL
; break;
8378 switch (fixp
->fx_size
)
8381 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8382 _("can not do %d byte relocation"),
8384 code
= BFD_RELOC_32
;
8386 case 1: code
= BFD_RELOC_8
; break;
8387 case 2: code
= BFD_RELOC_16
; break;
8388 case 4: code
= BFD_RELOC_32
; break;
8390 case 8: code
= BFD_RELOC_64
; break;
8397 if ((code
== BFD_RELOC_32
8398 || code
== BFD_RELOC_32_PCREL
8399 || code
== BFD_RELOC_X86_64_32S
)
8401 && fixp
->fx_addsy
== GOT_symbol
)
8404 code
= BFD_RELOC_386_GOTPC
;
8406 code
= BFD_RELOC_X86_64_GOTPC32
;
8408 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8410 && fixp
->fx_addsy
== GOT_symbol
)
8412 code
= BFD_RELOC_X86_64_GOTPC64
;
8415 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8416 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8417 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8419 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8421 if (!use_rela_relocations
)
8423 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8424 vtable entry to be used in the relocation's section offset. */
8425 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8426 rel
->address
= fixp
->fx_offset
;
8427 #if defined (OBJ_COFF) && defined (TE_PE)
8428 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8429 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8434 /* Use the rela in 64bit mode. */
8437 if (!fixp
->fx_pcrel
)
8438 rel
->addend
= fixp
->fx_offset
;
8442 case BFD_RELOC_X86_64_PLT32
:
8443 case BFD_RELOC_X86_64_GOT32
:
8444 case BFD_RELOC_X86_64_GOTPCREL
:
8445 case BFD_RELOC_X86_64_TLSGD
:
8446 case BFD_RELOC_X86_64_TLSLD
:
8447 case BFD_RELOC_X86_64_GOTTPOFF
:
8448 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8449 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8450 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8453 rel
->addend
= (section
->vma
8455 + fixp
->fx_addnumber
8456 + md_pcrel_from (fixp
));
8461 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8462 if (rel
->howto
== NULL
)
8464 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8465 _("cannot represent relocation type %s"),
8466 bfd_get_reloc_code_name (code
));
8467 /* Set howto to a garbage value so that we can keep going. */
8468 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8469 gas_assert (rel
->howto
!= NULL
);
8475 #include "tc-i386-intel.c"
8478 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8480 int saved_naked_reg
;
8481 char saved_register_dot
;
8483 saved_naked_reg
= allow_naked_reg
;
8484 allow_naked_reg
= 1;
8485 saved_register_dot
= register_chars
['.'];
8486 register_chars
['.'] = '.';
8487 allow_pseudo_reg
= 1;
8488 expression_and_evaluate (exp
);
8489 allow_pseudo_reg
= 0;
8490 register_chars
['.'] = saved_register_dot
;
8491 allow_naked_reg
= saved_naked_reg
;
8493 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8495 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8497 exp
->X_op
= O_constant
;
8498 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8499 .dw2_regnum
[flag_code
>> 1];
8502 exp
->X_op
= O_illegal
;
8507 tc_x86_frame_initial_instructions (void)
8509 static unsigned int sp_regno
[2];
8511 if (!sp_regno
[flag_code
>> 1])
8513 char *saved_input
= input_line_pointer
;
8514 char sp
[][4] = {"esp", "rsp"};
8517 input_line_pointer
= sp
[flag_code
>> 1];
8518 tc_x86_parse_to_dw2regnum (&exp
);
8519 gas_assert (exp
.X_op
== O_constant
);
8520 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8521 input_line_pointer
= saved_input
;
8524 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8525 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8529 i386_elf_section_type (const char *str
, size_t len
)
8531 if (flag_code
== CODE_64BIT
8532 && len
== sizeof ("unwind") - 1
8533 && strncmp (str
, "unwind", 6) == 0)
8534 return SHT_X86_64_UNWIND
;
8541 i386_solaris_fix_up_eh_frame (segT sec
)
8543 if (flag_code
== CODE_64BIT
)
8544 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8550 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8554 expr
.X_op
= O_secrel
;
8555 expr
.X_add_symbol
= symbol
;
8556 expr
.X_add_number
= 0;
8557 emit_expr (&expr
, size
);
8561 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8562 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8565 x86_64_section_letter (int letter
, char **ptr_msg
)
8567 if (flag_code
== CODE_64BIT
)
8570 return SHF_X86_64_LARGE
;
8572 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8575 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8580 x86_64_section_word (char *str
, size_t len
)
8582 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8583 return SHF_X86_64_LARGE
;
8589 handle_large_common (int small ATTRIBUTE_UNUSED
)
8591 if (flag_code
!= CODE_64BIT
)
8593 s_comm_internal (0, elf_common_parse
);
8594 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8598 static segT lbss_section
;
8599 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8600 asection
*saved_bss_section
= bss_section
;
8602 if (lbss_section
== NULL
)
8604 flagword applicable
;
8606 subsegT subseg
= now_subseg
;
8608 /* The .lbss section is for local .largecomm symbols. */
8609 lbss_section
= subseg_new (".lbss", 0);
8610 applicable
= bfd_applicable_section_flags (stdoutput
);
8611 bfd_set_section_flags (stdoutput
, lbss_section
,
8612 applicable
& SEC_ALLOC
);
8613 seg_info (lbss_section
)->bss
= 1;
8615 subseg_set (seg
, subseg
);
8618 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8619 bss_section
= lbss_section
;
8621 s_comm_internal (0, elf_common_parse
);
8623 elf_com_section_ptr
= saved_com_section_ptr
;
8624 bss_section
= saved_bss_section
;
8627 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */