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opcodes: blackfin: fix decoding of many invalid insns
[binutils.git] / opcodes / bfin-dis.c
blobc77a5dad90578523576e01594b966c3ecd21a244
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3
4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include <stdio.h>
22 #include <stdlib.h>
23 #include <string.h>
24
25 #include "opcode/bfin.h"
26
27 #define M_S2RND 1
28 #define M_T 2
29 #define M_W32 3
30 #define M_FU 4
31 #define M_TFU 6
32 #define M_IS 8
33 #define M_ISS2 9
34 #define M_IH 11
35 #define M_IU 12
36
37 #ifndef PRINTF
38 #define PRINTF printf
39 #endif
40
41 #ifndef EXIT
42 #define EXIT exit
43 #endif
44
45 typedef long TIword;
46
47 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
51
52 #include "dis-asm.h"
53
54 typedef unsigned int bu32;
55
56 static char comment = 0;
57 static char parallel = 0;
58
59 typedef enum
60 {
61 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
62 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
63 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
64 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
65 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
66 } const_forms_t;
67
68 static const struct
69 {
70 const char *name;
71 const int nbits;
72 const char reloc;
73 const char issigned;
74 const char pcrel;
75 const char scale;
76 const char offset;
77 const char negative;
78 const char positive;
79 const char decimal;
80 const char leading;
81 const char exact;
82 } constant_formats[] =
83 {
84 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
92 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
94 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
95 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
97 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
98 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
100 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
101 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
104 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
108 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
109 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
110 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
113 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
119 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
121 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
123 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
124 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
125 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
127 };
128
129 static const char *
130 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
131 {
132 static char buf[60];
133
134 if (constant_formats[cf].reloc)
135 {
136 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
137 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
138 if (constant_formats[cf].pcrel)
139 ea += pc;
140
141 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
142 {
143 outf->print_address_func (ea, outf);
144 return "";
145 }
146 else
147 {
148 sprintf (buf, "%lx", (unsigned long) x);
149 return buf;
150 }
151 }
152
153 /* Negative constants have an implied sign bit. */
154 if (constant_formats[cf].negative)
155 {
156 int nb = constant_formats[cf].nbits + 1;
157
158 x = x | (1 << constant_formats[cf].nbits);
159 x = SIGNEXTEND (x, nb);
160 }
161 else
162 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
163
164 if (constant_formats[cf].offset)
165 x += constant_formats[cf].offset;
166
167 if (constant_formats[cf].scale)
168 x <<= constant_formats[cf].scale;
169
170 if (constant_formats[cf].decimal)
171 {
172 if (constant_formats[cf].leading)
173 {
174 char ps[10];
175 sprintf (ps, "%%%ii", constant_formats[cf].leading);
176 sprintf (buf, ps, x);
177 }
178 else
179 sprintf (buf, "%li", x);
180 }
181 else
182 {
183 if (constant_formats[cf].issigned && x < 0)
184 sprintf (buf, "-0x%x", abs (x));
185 else
186 sprintf (buf, "0x%lx", (unsigned long) x);
187 }
188
189 return buf;
190 }
191
192 static bu32
193 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
194 {
195 if (0 && constant_formats[cf].reloc)
196 {
197 bu32 ea = (((constant_formats[cf].pcrel
198 ? SIGNEXTEND (x, constant_formats[cf].nbits)
199 : x) + constant_formats[cf].offset)
200 << constant_formats[cf].scale);
201 if (constant_formats[cf].pcrel)
202 ea += pc;
203
204 return ea;
205 }
206
207 /* Negative constants have an implied sign bit. */
208 if (constant_formats[cf].negative)
209 {
210 int nb = constant_formats[cf].nbits + 1;
211 x = x | (1 << constant_formats[cf].nbits);
212 x = SIGNEXTEND (x, nb);
213 }
214 else if (constant_formats[cf].issigned)
215 x = SIGNEXTEND (x, constant_formats[cf].nbits);
216
217 x += constant_formats[cf].offset;
218 x <<= constant_formats[cf].scale;
219
220 return x;
221 }
222
223 enum machine_registers
224 {
225 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
226 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
227 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
228 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
229 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
230 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
231 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
232 REG_L2, REG_L3,
233 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
234 REG_AQ, REG_V, REG_VS,
235 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
236 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
237 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
238 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
239 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
240 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
241 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
242 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
243 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
244 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
245 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
246 REG_LASTREG,
247 };
248
249 enum reg_class
250 {
251 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
252 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
253 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
254 rc_sysregs3, rc_allregs,
255 LIM_REG_CLASSES
256 };
257
258 static const char *reg_names[] =
259 {
260 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
261 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
262 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
263 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
264 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
265 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
266 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
267 "L2", "L3",
268 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
269 "AQ", "V", "VS",
270 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
271 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
272 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
273 "RETE", "EMUDAT",
274 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
275 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
276 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
277 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
278 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
279 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
280 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
281 "AC0_COPY", "V_COPY", "RND_MOD",
282 "LASTREG",
283 0
284 };
285
286 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
287
288 /* RL(0..7). */
289 static enum machine_registers decode_dregs_lo[] =
290 {
291 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
292 };
293
294 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
295
296 /* RH(0..7). */
297 static enum machine_registers decode_dregs_hi[] =
298 {
299 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
300 };
301
302 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
303
304 /* R(0..7). */
305 static enum machine_registers decode_dregs[] =
306 {
307 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
308 };
309
310 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
311
312 /* R BYTE(0..7). */
313 static enum machine_registers decode_dregs_byte[] =
314 {
315 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
316 };
317
318 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
319
320 /* P(0..5) SP FP. */
321 static enum machine_registers decode_pregs[] =
322 {
323 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
324 };
325
326 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
327 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
328 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
329 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
330 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
331 #define accum(x) REGNAME (decode_accum[(x) & 1])
332
333 /* I(0..3). */
334 static enum machine_registers decode_iregs[] =
335 {
336 REG_I0, REG_I1, REG_I2, REG_I3,
337 };
338
339 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
340
341 /* M(0..3). */
342 static enum machine_registers decode_mregs[] =
343 {
344 REG_M0, REG_M1, REG_M2, REG_M3,
345 };
346
347 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
348 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
349 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
350
351 /* dregs pregs. */
352 static enum machine_registers decode_dpregs[] =
353 {
354 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
355 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
356 };
357
358 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
359
360 /* [dregs pregs]. */
361 static enum machine_registers decode_gregs[] =
362 {
363 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
364 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
365 };
366
367 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
368
369 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
370 static enum machine_registers decode_regs[] =
371 {
372 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
373 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
374 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
375 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
376 };
377
378 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
379
380 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
381 static enum machine_registers decode_regs_lo[] =
382 {
383 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
384 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
385 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
386 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
387 };
388
389 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
390 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
391 static enum machine_registers decode_regs_hi[] =
392 {
393 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
394 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
395 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
396 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
397 };
398
399 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
400
401 static enum machine_registers decode_statbits[] =
402 {
403 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
404 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
405 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
406 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
407 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
408 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
409 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
410 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
411 };
412
413 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
414
415 /* LC0 LC1. */
416 static enum machine_registers decode_counters[] =
417 {
418 REG_LC0, REG_LC1,
419 };
420
421 #define counters(x) REGNAME (decode_counters[(x) & 1])
422 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
423
424 /* [dregs pregs (iregs mregs) (bregs lregs)
425 dregs2_sysregs1 open sysregs2 sysregs3]. */
426 static enum machine_registers decode_allregs[] =
427 {
428 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
429 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
430 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
431 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
432 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
433 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
434 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
435 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
436 REG_LASTREG,
437 };
438
439 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
440 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
441 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
442 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
443 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
444 #define IS_SYSREG(g,r) \
445 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
446 #define IS_RESERVEDREG(g,r) \
447 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
448
449 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
450 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
451
452 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
453 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
454 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
455 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
456 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
457 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
458 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
459 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
460 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
461 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
462 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
463 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
464 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
465 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
466 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
467 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
468 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
469 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
470 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
471 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
472 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
473 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
474 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
475 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
476 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
477 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
478 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
479 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
480 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
481 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
482 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
483 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
484 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
485 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
486 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
487 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
488 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
489 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
490 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
491 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
492 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
493 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
494 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
495
496 /* (arch.pm)arch_disassembler_functions. */
497 #ifndef OUTS
498 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
499 #endif
500
501 static void
502 amod0 (int s0, int x0, disassemble_info *outf)
503 {
504 if (s0 == 1 && x0 == 0)
505 OUTS (outf, " (S)");
506 else if (s0 == 0 && x0 == 1)
507 OUTS (outf, " (CO)");
508 else if (s0 == 1 && x0 == 1)
509 OUTS (outf, " (SCO)");
510 }
511
512 static void
513 amod1 (int s0, int x0, disassemble_info *outf)
514 {
515 if (s0 == 0 && x0 == 0)
516 OUTS (outf, " (NS)");
517 else if (s0 == 1 && x0 == 0)
518 OUTS (outf, " (S)");
519 }
520
521 static void
522 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
523 {
524 if (s0 == 1 && x0 == 0 && aop0 == 0)
525 OUTS (outf, " (S)");
526 else if (s0 == 0 && x0 == 1 && aop0 == 0)
527 OUTS (outf, " (CO)");
528 else if (s0 == 1 && x0 == 1 && aop0 == 0)
529 OUTS (outf, " (SCO)");
530 else if (s0 == 0 && x0 == 0 && aop0 == 2)
531 OUTS (outf, " (ASR)");
532 else if (s0 == 1 && x0 == 0 && aop0 == 2)
533 OUTS (outf, " (S, ASR)");
534 else if (s0 == 0 && x0 == 1 && aop0 == 2)
535 OUTS (outf, " (CO, ASR)");
536 else if (s0 == 1 && x0 == 1 && aop0 == 2)
537 OUTS (outf, " (SCO, ASR)");
538 else if (s0 == 0 && x0 == 0 && aop0 == 3)
539 OUTS (outf, " (ASL)");
540 else if (s0 == 1 && x0 == 0 && aop0 == 3)
541 OUTS (outf, " (S, ASL)");
542 else if (s0 == 0 && x0 == 1 && aop0 == 3)
543 OUTS (outf, " (CO, ASL)");
544 else if (s0 == 1 && x0 == 1 && aop0 == 3)
545 OUTS (outf, " (SCO, ASL)");
546 }
547
548 static void
549 searchmod (int r0, disassemble_info *outf)
550 {
551 if (r0 == 0)
552 OUTS (outf, "GT");
553 else if (r0 == 1)
554 OUTS (outf, "GE");
555 else if (r0 == 2)
556 OUTS (outf, "LT");
557 else if (r0 == 3)
558 OUTS (outf, "LE");
559 }
560
561 static void
562 aligndir (int r0, disassemble_info *outf)
563 {
564 if (r0 == 1)
565 OUTS (outf, " (R)");
566 }
567
568 static int
569 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
570 {
571 const char *s0, *s1;
572
573 if (h0)
574 s0 = dregs_hi (src0);
575 else
576 s0 = dregs_lo (src0);
577
578 if (h1)
579 s1 = dregs_hi (src1);
580 else
581 s1 = dregs_lo (src1);
582
583 OUTS (outf, s0);
584 OUTS (outf, " * ");
585 OUTS (outf, s1);
586 return 0;
587 }
588
589 static int
590 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
591 {
592 const char *a;
593 const char *sop = "<unknown op>";
594
595 if (which)
596 a = "A1";
597 else
598 a = "A0";
599
600 if (op == 3)
601 {
602 OUTS (outf, a);
603 return 0;
604 }
605
606 switch (op)
607 {
608 case 0: sop = " = "; break;
609 case 1: sop = " += "; break;
610 case 2: sop = " -= "; break;
611 default: break;
612 }
613
614 OUTS (outf, a);
615 OUTS (outf, sop);
616 decode_multfunc (h0, h1, src0, src1, outf);
617
618 return 0;
619 }
620
621 static void
622 decode_optmode (int mod, int MM, disassemble_info *outf)
623 {
624 if (mod == 0 && MM == 0)
625 return;
626
627 OUTS (outf, " (");
628
629 if (MM && !mod)
630 {
631 OUTS (outf, "M)");
632 return;
633 }
634
635 if (MM)
636 OUTS (outf, "M, ");
637
638 if (mod == M_S2RND)
639 OUTS (outf, "S2RND");
640 else if (mod == M_T)
641 OUTS (outf, "T");
642 else if (mod == M_W32)
643 OUTS (outf, "W32");
644 else if (mod == M_FU)
645 OUTS (outf, "FU");
646 else if (mod == M_TFU)
647 OUTS (outf, "TFU");
648 else if (mod == M_IS)
649 OUTS (outf, "IS");
650 else if (mod == M_ISS2)
651 OUTS (outf, "ISS2");
652 else if (mod == M_IH)
653 OUTS (outf, "IH");
654 else if (mod == M_IU)
655 OUTS (outf, "IU");
656 else
657 abort ();
658
659 OUTS (outf, ")");
660 }
661
662 struct saved_state
663 {
664 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
665 bu32 a0x, a0w, a1x, a1w;
666 bu32 lt[2], lc[2], lb[2];
667 int ac0, ac0_copy, ac1, an, aq;
668 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
669 int rnd_mod;
670 int v_internal;
671 bu32 pc, rets;
672
673 int ticks;
674 int insts;
675
676 int exception;
677
678 int end_of_registers;
679
680 int msize;
681 unsigned char *memory;
682 unsigned long bfd_mach;
683 } saved_state;
684
685 #define DREG(x) (saved_state.dpregs[x])
686 #define GREG(x,i) DPREG ((x) | (i << 3))
687 #define DPREG(x) (saved_state.dpregs[x])
688 #define DREG(x) (saved_state.dpregs[x])
689 #define PREG(x) (saved_state.dpregs[x + 8])
690 #define SPREG PREG (6)
691 #define FPREG PREG (7)
692 #define IREG(x) (saved_state.iregs[x])
693 #define MREG(x) (saved_state.mregs[x])
694 #define BREG(x) (saved_state.bregs[x])
695 #define LREG(x) (saved_state.lregs[x])
696 #define A0XREG (saved_state.a0x)
697 #define A0WREG (saved_state.a0w)
698 #define A1XREG (saved_state.a1x)
699 #define A1WREG (saved_state.a1w)
700 #define CCREG (saved_state.cc)
701 #define LC0REG (saved_state.lc[0])
702 #define LT0REG (saved_state.lt[0])
703 #define LB0REG (saved_state.lb[0])
704 #define LC1REG (saved_state.lc[1])
705 #define LT1REG (saved_state.lt[1])
706 #define LB1REG (saved_state.lb[1])
707 #define RETSREG (saved_state.rets)
708 #define PCREG (saved_state.pc)
709
710 static bu32 *
711 get_allreg (int grp, int reg)
712 {
713 int fullreg = (grp << 3) | reg;
714 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
715 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
716 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
717 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
718 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
719 , , , , , , , ,
720 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
721 REG_CYCLES2,
722 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
723 REG_LASTREG */
724 switch (fullreg >> 2)
725 {
726 case 0: case 1: return &DREG (reg); break;
727 case 2: case 3: return &PREG (reg); break;
728 case 4: return &IREG (reg & 3); break;
729 case 5: return &MREG (reg & 3); break;
730 case 6: return &BREG (reg & 3); break;
731 case 7: return &LREG (reg & 3); break;
732 default:
733 switch (fullreg)
734 {
735 case 32: return &saved_state.a0x;
736 case 33: return &saved_state.a0w;
737 case 34: return &saved_state.a1x;
738 case 35: return &saved_state.a1w;
739 case 39: return &saved_state.rets;
740 case 48: return &LC0REG;
741 case 49: return &LT0REG;
742 case 50: return &LB0REG;
743 case 51: return &LC1REG;
744 case 52: return &LT1REG;
745 case 53: return &LB1REG;
746 }
747 return 0;
748 }
749 }
750
751 static int
752 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
753 {
754 /* ProgCtrl
755 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
756 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
757 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
758 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
759 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
760
761 if (prgfunc == 0 && poprnd == 0)
762 OUTS (outf, "NOP");
763 else if (parallel)
764 return 0;
765 else if (prgfunc == 1 && poprnd == 0)
766 OUTS (outf, "RTS");
767 else if (prgfunc == 1 && poprnd == 1)
768 OUTS (outf, "RTI");
769 else if (prgfunc == 1 && poprnd == 2)
770 OUTS (outf, "RTX");
771 else if (prgfunc == 1 && poprnd == 3)
772 OUTS (outf, "RTN");
773 else if (prgfunc == 1 && poprnd == 4)
774 OUTS (outf, "RTE");
775 else if (prgfunc == 2 && poprnd == 0)
776 OUTS (outf, "IDLE");
777 else if (prgfunc == 2 && poprnd == 3)
778 OUTS (outf, "CSYNC");
779 else if (prgfunc == 2 && poprnd == 4)
780 OUTS (outf, "SSYNC");
781 else if (prgfunc == 2 && poprnd == 5)
782 OUTS (outf, "EMUEXCPT");
783 else if (prgfunc == 3 && IS_DREG (0, poprnd))
784 {
785 OUTS (outf, "CLI ");
786 OUTS (outf, dregs (poprnd));
787 }
788 else if (prgfunc == 4 && IS_DREG (0, poprnd))
789 {
790 OUTS (outf, "STI ");
791 OUTS (outf, dregs (poprnd));
792 }
793 else if (prgfunc == 5 && IS_PREG (1, poprnd))
794 {
795 OUTS (outf, "JUMP (");
796 OUTS (outf, pregs (poprnd));
797 OUTS (outf, ")");
798 }
799 else if (prgfunc == 6 && IS_PREG (1, poprnd))
800 {
801 OUTS (outf, "CALL (");
802 OUTS (outf, pregs (poprnd));
803 OUTS (outf, ")");
804 }
805 else if (prgfunc == 7 && IS_PREG (1, poprnd))
806 {
807 OUTS (outf, "CALL (PC + ");
808 OUTS (outf, pregs (poprnd));
809 OUTS (outf, ")");
810 }
811 else if (prgfunc == 8 && IS_PREG (1, poprnd))
812 {
813 OUTS (outf, "JUMP (PC + ");
814 OUTS (outf, pregs (poprnd));
815 OUTS (outf, ")");
816 }
817 else if (prgfunc == 9)
818 {
819 OUTS (outf, "RAISE ");
820 OUTS (outf, uimm4 (poprnd));
821 }
822 else if (prgfunc == 10)
823 {
824 OUTS (outf, "EXCPT ");
825 OUTS (outf, uimm4 (poprnd));
826 }
827 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
828 {
829 OUTS (outf, "TESTSET (");
830 OUTS (outf, pregs (poprnd));
831 OUTS (outf, ")");
832 }
833 else
834 return 0;
835 return 2;
836 }
837
838 static int
839 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
840 {
841 /* CaCTRL
842 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
843 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
844 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
845 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
846 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
847 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
848
849 if (parallel)
850 return 0;
851
852 if (a == 0 && op == 0)
853 {
854 OUTS (outf, "PREFETCH[");
855 OUTS (outf, pregs (reg));
856 OUTS (outf, "]");
857 }
858 else if (a == 0 && op == 1)
859 {
860 OUTS (outf, "FLUSHINV[");
861 OUTS (outf, pregs (reg));
862 OUTS (outf, "]");
863 }
864 else if (a == 0 && op == 2)
865 {
866 OUTS (outf, "FLUSH[");
867 OUTS (outf, pregs (reg));
868 OUTS (outf, "]");
869 }
870 else if (a == 0 && op == 3)
871 {
872 OUTS (outf, "IFLUSH[");
873 OUTS (outf, pregs (reg));
874 OUTS (outf, "]");
875 }
876 else if (a == 1 && op == 0)
877 {
878 OUTS (outf, "PREFETCH[");
879 OUTS (outf, pregs (reg));
880 OUTS (outf, "++]");
881 }
882 else if (a == 1 && op == 1)
883 {
884 OUTS (outf, "FLUSHINV[");
885 OUTS (outf, pregs (reg));
886 OUTS (outf, "++]");
887 }
888 else if (a == 1 && op == 2)
889 {
890 OUTS (outf, "FLUSH[");
891 OUTS (outf, pregs (reg));
892 OUTS (outf, "++]");
893 }
894 else if (a == 1 && op == 3)
895 {
896 OUTS (outf, "IFLUSH[");
897 OUTS (outf, pregs (reg));
898 OUTS (outf, "++]");
899 }
900 else
901 return 0;
902 return 2;
903 }
904
905 static int
906 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
907 {
908 /* PushPopReg
909 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
910 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
911 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
912 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
913 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
914 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
915
916 if (parallel)
917 return 0;
918
919 if (W == 0 && mostreg (reg, grp))
920 {
921 OUTS (outf, allregs (reg, grp));
922 OUTS (outf, " = [SP++]");
923 }
924 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
925 {
926 OUTS (outf, "[--SP] = ");
927 OUTS (outf, allregs (reg, grp));
928 }
929 else
930 return 0;
931 return 2;
932 }
933
934 static int
935 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
936 {
937 /* PushPopMultiple
938 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
939 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
940 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
941 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
942 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
943 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
944 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
945 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
946
947 if (parallel)
948 return 0;
949
950 if (pr > 5)
951 return 0;
952
953 if (W == 1 && d == 1 && p == 1)
954 {
955 OUTS (outf, "[--SP] = (R7:");
956 OUTS (outf, imm5d (dr));
957 OUTS (outf, ", P5:");
958 OUTS (outf, imm5d (pr));
959 OUTS (outf, ")");
960 }
961 else if (W == 1 && d == 1 && p == 0 && pr == 0)
962 {
963 OUTS (outf, "[--SP] = (R7:");
964 OUTS (outf, imm5d (dr));
965 OUTS (outf, ")");
966 }
967 else if (W == 1 && d == 0 && p == 1 && dr == 0)
968 {
969 OUTS (outf, "[--SP] = (P5:");
970 OUTS (outf, imm5d (pr));
971 OUTS (outf, ")");
972 }
973 else if (W == 0 && d == 1 && p == 1)
974 {
975 OUTS (outf, "(R7:");
976 OUTS (outf, imm5d (dr));
977 OUTS (outf, ", P5:");
978 OUTS (outf, imm5d (pr));
979 OUTS (outf, ") = [SP++]");
980 }
981 else if (W == 0 && d == 1 && p == 0 && pr == 0)
982 {
983 OUTS (outf, "(R7:");
984 OUTS (outf, imm5d (dr));
985 OUTS (outf, ") = [SP++]");
986 }
987 else if (W == 0 && d == 0 && p == 1 && dr == 0)
988 {
989 OUTS (outf, "(P5:");
990 OUTS (outf, imm5d (pr));
991 OUTS (outf, ") = [SP++]");
992 }
993 else
994 return 0;
995 return 2;
996 }
997
998 static int
999 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
1000 {
1001 /* ccMV
1002 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1003 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1004 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1005 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
1006 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
1007 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
1008 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
1009 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
1010
1011 if (parallel)
1012 return 0;
1013
1014 if (T == 1)
1015 {
1016 OUTS (outf, "IF CC ");
1017 OUTS (outf, gregs (dst, d));
1018 OUTS (outf, " = ");
1019 OUTS (outf, gregs (src, s));
1020 }
1021 else if (T == 0)
1022 {
1023 OUTS (outf, "IF !CC ");
1024 OUTS (outf, gregs (dst, d));
1025 OUTS (outf, " = ");
1026 OUTS (outf, gregs (src, s));
1027 }
1028 else
1029 return 0;
1030 return 2;
1031 }
1032
1033 static int
1034 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1035 {
1036 /* CCflag
1037 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1038 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1039 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1040 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1041 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1042 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1043 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1044 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1045
1046 if (parallel)
1047 return 0;
1048
1049 if (opc == 0 && I == 0 && G == 0)
1050 {
1051 OUTS (outf, "CC = ");
1052 OUTS (outf, dregs (x));
1053 OUTS (outf, " == ");
1054 OUTS (outf, dregs (y));
1055 }
1056 else if (opc == 1 && I == 0 && G == 0)
1057 {
1058 OUTS (outf, "CC = ");
1059 OUTS (outf, dregs (x));
1060 OUTS (outf, " < ");
1061 OUTS (outf, dregs (y));
1062 }
1063 else if (opc == 2 && I == 0 && G == 0)
1064 {
1065 OUTS (outf, "CC = ");
1066 OUTS (outf, dregs (x));
1067 OUTS (outf, " <= ");
1068 OUTS (outf, dregs (y));
1069 }
1070 else if (opc == 3 && I == 0 && G == 0)
1071 {
1072 OUTS (outf, "CC = ");
1073 OUTS (outf, dregs (x));
1074 OUTS (outf, " < ");
1075 OUTS (outf, dregs (y));
1076 OUTS (outf, " (IU)");
1077 }
1078 else if (opc == 4 && I == 0 && G == 0)
1079 {
1080 OUTS (outf, "CC = ");
1081 OUTS (outf, dregs (x));
1082 OUTS (outf, " <= ");
1083 OUTS (outf, dregs (y));
1084 OUTS (outf, " (IU)");
1085 }
1086 else if (opc == 0 && I == 1 && G == 0)
1087 {
1088 OUTS (outf, "CC = ");
1089 OUTS (outf, dregs (x));
1090 OUTS (outf, " == ");
1091 OUTS (outf, imm3 (y));
1092 }
1093 else if (opc == 1 && I == 1 && G == 0)
1094 {
1095 OUTS (outf, "CC = ");
1096 OUTS (outf, dregs (x));
1097 OUTS (outf, " < ");
1098 OUTS (outf, imm3 (y));
1099 }
1100 else if (opc == 2 && I == 1 && G == 0)
1101 {
1102 OUTS (outf, "CC = ");
1103 OUTS (outf, dregs (x));
1104 OUTS (outf, " <= ");
1105 OUTS (outf, imm3 (y));
1106 }
1107 else if (opc == 3 && I == 1 && G == 0)
1108 {
1109 OUTS (outf, "CC = ");
1110 OUTS (outf, dregs (x));
1111 OUTS (outf, " < ");
1112 OUTS (outf, uimm3 (y));
1113 OUTS (outf, " (IU)");
1114 }
1115 else if (opc == 4 && I == 1 && G == 0)
1116 {
1117 OUTS (outf, "CC = ");
1118 OUTS (outf, dregs (x));
1119 OUTS (outf, " <= ");
1120 OUTS (outf, uimm3 (y));
1121 OUTS (outf, " (IU)");
1122 }
1123 else if (opc == 0 && I == 0 && G == 1)
1124 {
1125 OUTS (outf, "CC = ");
1126 OUTS (outf, pregs (x));
1127 OUTS (outf, " == ");
1128 OUTS (outf, pregs (y));
1129 }
1130 else if (opc == 1 && I == 0 && G == 1)
1131 {
1132 OUTS (outf, "CC = ");
1133 OUTS (outf, pregs (x));
1134 OUTS (outf, " < ");
1135 OUTS (outf, pregs (y));
1136 }
1137 else if (opc == 2 && I == 0 && G == 1)
1138 {
1139 OUTS (outf, "CC = ");
1140 OUTS (outf, pregs (x));
1141 OUTS (outf, " <= ");
1142 OUTS (outf, pregs (y));
1143 }
1144 else if (opc == 3 && I == 0 && G == 1)
1145 {
1146 OUTS (outf, "CC = ");
1147 OUTS (outf, pregs (x));
1148 OUTS (outf, " < ");
1149 OUTS (outf, pregs (y));
1150 OUTS (outf, " (IU)");
1151 }
1152 else if (opc == 4 && I == 0 && G == 1)
1153 {
1154 OUTS (outf, "CC = ");
1155 OUTS (outf, pregs (x));
1156 OUTS (outf, " <= ");
1157 OUTS (outf, pregs (y));
1158 OUTS (outf, " (IU)");
1159 }
1160 else if (opc == 0 && I == 1 && G == 1)
1161 {
1162 OUTS (outf, "CC = ");
1163 OUTS (outf, pregs (x));
1164 OUTS (outf, " == ");
1165 OUTS (outf, imm3 (y));
1166 }
1167 else if (opc == 1 && I == 1 && G == 1)
1168 {
1169 OUTS (outf, "CC = ");
1170 OUTS (outf, pregs (x));
1171 OUTS (outf, " < ");
1172 OUTS (outf, imm3 (y));
1173 }
1174 else if (opc == 2 && I == 1 && G == 1)
1175 {
1176 OUTS (outf, "CC = ");
1177 OUTS (outf, pregs (x));
1178 OUTS (outf, " <= ");
1179 OUTS (outf, imm3 (y));
1180 }
1181 else if (opc == 3 && I == 1 && G == 1)
1182 {
1183 OUTS (outf, "CC = ");
1184 OUTS (outf, pregs (x));
1185 OUTS (outf, " < ");
1186 OUTS (outf, uimm3 (y));
1187 OUTS (outf, " (IU)");
1188 }
1189 else if (opc == 4 && I == 1 && G == 1)
1190 {
1191 OUTS (outf, "CC = ");
1192 OUTS (outf, pregs (x));
1193 OUTS (outf, " <= ");
1194 OUTS (outf, uimm3 (y));
1195 OUTS (outf, " (IU)");
1196 }
1197 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1198 OUTS (outf, "CC = A0 == A1");
1199
1200 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1201 OUTS (outf, "CC = A0 < A1");
1202
1203 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1204 OUTS (outf, "CC = A0 <= A1");
1205
1206 else
1207 return 0;
1208 return 2;
1209 }
1210
1211 static int
1212 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1213 {
1214 /* CC2dreg
1215 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1216 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1217 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1218 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1219 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1220
1221 if (parallel)
1222 return 0;
1223
1224 if (op == 0)
1225 {
1226 OUTS (outf, dregs (reg));
1227 OUTS (outf, " = CC");
1228 }
1229 else if (op == 1)
1230 {
1231 OUTS (outf, "CC = ");
1232 OUTS (outf, dregs (reg));
1233 }
1234 else if (op == 3 && reg == 0)
1235 OUTS (outf, "CC = !CC");
1236 else
1237 return 0;
1238
1239 return 2;
1240 }
1241
1242 static int
1243 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1244 {
1245 /* CC2stat
1246 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1247 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1248 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1249 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1250 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1251 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1252
1253 const char *bitname = statbits (cbit);
1254
1255 if (parallel)
1256 return 0;
1257
1258 if (decode_statbits[cbit] == REG_LASTREG)
1259 {
1260 /* All ASTAT bits except CC may be operated on in hardware, but may
1261 not have a dedicated insn, so still decode "valid" insns. */
1262 static char bitnames[64];
1263 if (cbit != 5)
1264 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1265 else
1266 return 0;
1267
1268 bitname = bitnames;
1269 }
1270
1271 if (op == 0 && D == 0)
1272 {
1273 OUTS (outf, "CC = ");
1274 OUTS (outf, bitname);
1275 }
1276 else if (op == 1 && D == 0)
1277 {
1278 OUTS (outf, "CC |= ");
1279 OUTS (outf, bitname);
1280 }
1281 else if (op == 2 && D == 0)
1282 {
1283 OUTS (outf, "CC &= ");
1284 OUTS (outf, bitname);
1285 }
1286 else if (op == 3 && D == 0)
1287 {
1288 OUTS (outf, "CC ^= ");
1289 OUTS (outf, bitname);
1290 }
1291 else if (op == 0 && D == 1)
1292 {
1293 OUTS (outf, bitname);
1294 OUTS (outf, " = CC");
1295 }
1296 else if (op == 1 && D == 1)
1297 {
1298 OUTS (outf, bitname);
1299 OUTS (outf, " |= CC");
1300 }
1301 else if (op == 2 && D == 1)
1302 {
1303 OUTS (outf, bitname);
1304 OUTS (outf, " &= CC");
1305 }
1306 else if (op == 3 && D == 1)
1307 {
1308 OUTS (outf, bitname);
1309 OUTS (outf, " ^= CC");
1310 }
1311 else
1312 return 0;
1313
1314 return 2;
1315 }
1316
1317 static int
1318 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1319 {
1320 /* BRCC
1321 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1322 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1323 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1324 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1325 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1326 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1327
1328 if (parallel)
1329 return 0;
1330
1331 if (T == 1 && B == 1)
1332 {
1333 OUTS (outf, "IF CC JUMP 0x");
1334 OUTS (outf, pcrel10 (offset));
1335 OUTS (outf, " (BP)");
1336 }
1337 else if (T == 0 && B == 1)
1338 {
1339 OUTS (outf, "IF !CC JUMP 0x");
1340 OUTS (outf, pcrel10 (offset));
1341 OUTS (outf, " (BP)");
1342 }
1343 else if (T == 1)
1344 {
1345 OUTS (outf, "IF CC JUMP 0x");
1346 OUTS (outf, pcrel10 (offset));
1347 }
1348 else if (T == 0)
1349 {
1350 OUTS (outf, "IF !CC JUMP 0x");
1351 OUTS (outf, pcrel10 (offset));
1352 }
1353 else
1354 return 0;
1355
1356 return 2;
1357 }
1358
1359 static int
1360 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1361 {
1362 /* UJUMP
1363 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1364 | 0 | 0 | 1 | 0 |.offset........................................|
1365 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1366 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1367
1368 if (parallel)
1369 return 0;
1370
1371 OUTS (outf, "JUMP.S 0x");
1372 OUTS (outf, pcrel12 (offset));
1373 return 2;
1374 }
1375
1376 static int
1377 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1378 {
1379 /* REGMV
1380 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1381 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1382 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1383 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1384 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1385 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1386 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1387
1388 if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src))
1389 || (IS_GENREG (gd, dst) && IS_DAGREG (gs, src))
1390 || (IS_DAGREG (gd, dst) && IS_GENREG (gs, src))
1391 || (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src))
1392 || (IS_GENREG (gd, dst) && gs == 7 && src == 0)
1393 || (gd == 7 && dst == 0 && IS_GENREG (gs, src))
1394 || (IS_DREG (gd, dst) && IS_SYSREG (gs, src))
1395 || (IS_PREG (gd, dst) && IS_SYSREG (gs, src))
1396 || (IS_SYSREG (gd, dst) && IS_DREG (gs, src))
1397 || (IS_SYSREG (gd, dst) && IS_PREG (gs, src))
1398 || (IS_SYSREG (gd, dst) && gs == 7 && src == 0)))
1399 return 0;
1400
1401 OUTS (outf, allregs (dst, gd));
1402 OUTS (outf, " = ");
1403 OUTS (outf, allregs (src, gs));
1404 return 2;
1405 }
1406
1407 static int
1408 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1409 {
1410 /* ALU2op
1411 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1412 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1413 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1414 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1415 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1416 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1417
1418 if (opc == 0)
1419 {
1420 OUTS (outf, dregs (dst));
1421 OUTS (outf, " >>>= ");
1422 OUTS (outf, dregs (src));
1423 }
1424 else if (opc == 1)
1425 {
1426 OUTS (outf, dregs (dst));
1427 OUTS (outf, " >>= ");
1428 OUTS (outf, dregs (src));
1429 }
1430 else if (opc == 2)
1431 {
1432 OUTS (outf, dregs (dst));
1433 OUTS (outf, " <<= ");
1434 OUTS (outf, dregs (src));
1435 }
1436 else if (opc == 3)
1437 {
1438 OUTS (outf, dregs (dst));
1439 OUTS (outf, " *= ");
1440 OUTS (outf, dregs (src));
1441 }
1442 else if (opc == 4)
1443 {
1444 OUTS (outf, dregs (dst));
1445 OUTS (outf, " = (");
1446 OUTS (outf, dregs (dst));
1447 OUTS (outf, " + ");
1448 OUTS (outf, dregs (src));
1449 OUTS (outf, ") << 0x1");
1450 }
1451 else if (opc == 5)
1452 {
1453 OUTS (outf, dregs (dst));
1454 OUTS (outf, " = (");
1455 OUTS (outf, dregs (dst));
1456 OUTS (outf, " + ");
1457 OUTS (outf, dregs (src));
1458 OUTS (outf, ") << 0x2");
1459 }
1460 else if (opc == 8)
1461 {
1462 OUTS (outf, "DIVQ (");
1463 OUTS (outf, dregs (dst));
1464 OUTS (outf, ", ");
1465 OUTS (outf, dregs (src));
1466 OUTS (outf, ")");
1467 }
1468 else if (opc == 9)
1469 {
1470 OUTS (outf, "DIVS (");
1471 OUTS (outf, dregs (dst));
1472 OUTS (outf, ", ");
1473 OUTS (outf, dregs (src));
1474 OUTS (outf, ")");
1475 }
1476 else if (opc == 10)
1477 {
1478 OUTS (outf, dregs (dst));
1479 OUTS (outf, " = ");
1480 OUTS (outf, dregs_lo (src));
1481 OUTS (outf, " (X)");
1482 }
1483 else if (opc == 11)
1484 {
1485 OUTS (outf, dregs (dst));
1486 OUTS (outf, " = ");
1487 OUTS (outf, dregs_lo (src));
1488 OUTS (outf, " (Z)");
1489 }
1490 else if (opc == 12)
1491 {
1492 OUTS (outf, dregs (dst));
1493 OUTS (outf, " = ");
1494 OUTS (outf, dregs_byte (src));
1495 OUTS (outf, " (X)");
1496 }
1497 else if (opc == 13)
1498 {
1499 OUTS (outf, dregs (dst));
1500 OUTS (outf, " = ");
1501 OUTS (outf, dregs_byte (src));
1502 OUTS (outf, " (Z)");
1503 }
1504 else if (opc == 14)
1505 {
1506 OUTS (outf, dregs (dst));
1507 OUTS (outf, " = -");
1508 OUTS (outf, dregs (src));
1509 }
1510 else if (opc == 15)
1511 {
1512 OUTS (outf, dregs (dst));
1513 OUTS (outf, " =~ ");
1514 OUTS (outf, dregs (src));
1515 }
1516 else
1517 return 0;
1518
1519 return 2;
1520 }
1521
1522 static int
1523 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1524 {
1525 /* PTR2op
1526 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1527 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1528 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1529 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1530 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1531 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1532
1533 if (opc == 0)
1534 {
1535 OUTS (outf, pregs (dst));
1536 OUTS (outf, " -= ");
1537 OUTS (outf, pregs (src));
1538 }
1539 else if (opc == 1)
1540 {
1541 OUTS (outf, pregs (dst));
1542 OUTS (outf, " = ");
1543 OUTS (outf, pregs (src));
1544 OUTS (outf, " << 0x2");
1545 }
1546 else if (opc == 3)
1547 {
1548 OUTS (outf, pregs (dst));
1549 OUTS (outf, " = ");
1550 OUTS (outf, pregs (src));
1551 OUTS (outf, " >> 0x2");
1552 }
1553 else if (opc == 4)
1554 {
1555 OUTS (outf, pregs (dst));
1556 OUTS (outf, " = ");
1557 OUTS (outf, pregs (src));
1558 OUTS (outf, " >> 0x1");
1559 }
1560 else if (opc == 5)
1561 {
1562 OUTS (outf, pregs (dst));
1563 OUTS (outf, " += ");
1564 OUTS (outf, pregs (src));
1565 OUTS (outf, " (BREV)");
1566 }
1567 else if (opc == 6)
1568 {
1569 OUTS (outf, pregs (dst));
1570 OUTS (outf, " = (");
1571 OUTS (outf, pregs (dst));
1572 OUTS (outf, " + ");
1573 OUTS (outf, pregs (src));
1574 OUTS (outf, ") << 0x1");
1575 }
1576 else if (opc == 7)
1577 {
1578 OUTS (outf, pregs (dst));
1579 OUTS (outf, " = (");
1580 OUTS (outf, pregs (dst));
1581 OUTS (outf, " + ");
1582 OUTS (outf, pregs (src));
1583 OUTS (outf, ") << 0x2");
1584 }
1585 else
1586 return 0;
1587
1588 return 2;
1589 }
1590
1591 static int
1592 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1593 {
1594 /* LOGI2op
1595 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1596 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1597 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1598 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1599 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1600 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1601
1602 if (parallel)
1603 return 0;
1604
1605 if (opc == 0)
1606 {
1607 OUTS (outf, "CC = !BITTST (");
1608 OUTS (outf, dregs (dst));
1609 OUTS (outf, ", ");
1610 OUTS (outf, uimm5 (src));
1611 OUTS (outf, ");\t\t/* bit");
1612 OUTS (outf, imm7d (src));
1613 OUTS (outf, " */");
1614 comment = 1;
1615 }
1616 else if (opc == 1)
1617 {
1618 OUTS (outf, "CC = BITTST (");
1619 OUTS (outf, dregs (dst));
1620 OUTS (outf, ", ");
1621 OUTS (outf, uimm5 (src));
1622 OUTS (outf, ");\t\t/* bit");
1623 OUTS (outf, imm7d (src));
1624 OUTS (outf, " */");
1625 comment = 1;
1626 }
1627 else if (opc == 2)
1628 {
1629 OUTS (outf, "BITSET (");
1630 OUTS (outf, dregs (dst));
1631 OUTS (outf, ", ");
1632 OUTS (outf, uimm5 (src));
1633 OUTS (outf, ");\t\t/* bit");
1634 OUTS (outf, imm7d (src));
1635 OUTS (outf, " */");
1636 comment = 1;
1637 }
1638 else if (opc == 3)
1639 {
1640 OUTS (outf, "BITTGL (");
1641 OUTS (outf, dregs (dst));
1642 OUTS (outf, ", ");
1643 OUTS (outf, uimm5 (src));
1644 OUTS (outf, ");\t\t/* bit");
1645 OUTS (outf, imm7d (src));
1646 OUTS (outf, " */");
1647 comment = 1;
1648 }
1649 else if (opc == 4)
1650 {
1651 OUTS (outf, "BITCLR (");
1652 OUTS (outf, dregs (dst));
1653 OUTS (outf, ", ");
1654 OUTS (outf, uimm5 (src));
1655 OUTS (outf, ");\t\t/* bit");
1656 OUTS (outf, imm7d (src));
1657 OUTS (outf, " */");
1658 comment = 1;
1659 }
1660 else if (opc == 5)
1661 {
1662 OUTS (outf, dregs (dst));
1663 OUTS (outf, " >>>= ");
1664 OUTS (outf, uimm5 (src));
1665 }
1666 else if (opc == 6)
1667 {
1668 OUTS (outf, dregs (dst));
1669 OUTS (outf, " >>= ");
1670 OUTS (outf, uimm5 (src));
1671 }
1672 else if (opc == 7)
1673 {
1674 OUTS (outf, dregs (dst));
1675 OUTS (outf, " <<= ");
1676 OUTS (outf, uimm5 (src));
1677 }
1678 else
1679 return 0;
1680
1681 return 2;
1682 }
1683
1684 static int
1685 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1686 {
1687 /* COMP3op
1688 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1689 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1690 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1691 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1692 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1693 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1694 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1695
1696 if (opc == 5 && src1 == src0)
1697 {
1698 OUTS (outf, pregs (dst));
1699 OUTS (outf, " = ");
1700 OUTS (outf, pregs (src0));
1701 OUTS (outf, " << 0x1");
1702 }
1703 else if (opc == 1)
1704 {
1705 OUTS (outf, dregs (dst));
1706 OUTS (outf, " = ");
1707 OUTS (outf, dregs (src0));
1708 OUTS (outf, " - ");
1709 OUTS (outf, dregs (src1));
1710 }
1711 else if (opc == 2)
1712 {
1713 OUTS (outf, dregs (dst));
1714 OUTS (outf, " = ");
1715 OUTS (outf, dregs (src0));
1716 OUTS (outf, " & ");
1717 OUTS (outf, dregs (src1));
1718 }
1719 else if (opc == 3)
1720 {
1721 OUTS (outf, dregs (dst));
1722 OUTS (outf, " = ");
1723 OUTS (outf, dregs (src0));
1724 OUTS (outf, " | ");
1725 OUTS (outf, dregs (src1));
1726 }
1727 else if (opc == 4)
1728 {
1729 OUTS (outf, dregs (dst));
1730 OUTS (outf, " = ");
1731 OUTS (outf, dregs (src0));
1732 OUTS (outf, " ^ ");
1733 OUTS (outf, dregs (src1));
1734 }
1735 else if (opc == 5)
1736 {
1737 OUTS (outf, pregs (dst));
1738 OUTS (outf, " = ");
1739 OUTS (outf, pregs (src0));
1740 OUTS (outf, " + ");
1741 OUTS (outf, pregs (src1));
1742 }
1743 else if (opc == 6)
1744 {
1745 OUTS (outf, pregs (dst));
1746 OUTS (outf, " = ");
1747 OUTS (outf, pregs (src0));
1748 OUTS (outf, " + (");
1749 OUTS (outf, pregs (src1));
1750 OUTS (outf, " << 0x1)");
1751 }
1752 else if (opc == 7)
1753 {
1754 OUTS (outf, pregs (dst));
1755 OUTS (outf, " = ");
1756 OUTS (outf, pregs (src0));
1757 OUTS (outf, " + (");
1758 OUTS (outf, pregs (src1));
1759 OUTS (outf, " << 0x2)");
1760 }
1761 else if (opc == 0)
1762 {
1763 OUTS (outf, dregs (dst));
1764 OUTS (outf, " = ");
1765 OUTS (outf, dregs (src0));
1766 OUTS (outf, " + ");
1767 OUTS (outf, dregs (src1));
1768 }
1769 else
1770 return 0;
1771
1772 return 2;
1773 }
1774
1775 static int
1776 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1777 {
1778 /* COMPI2opD
1779 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1780 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1781 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1782 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1783 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1784 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1785
1786 bu32 *pval = get_allreg (0, dst);
1787
1788 if (parallel)
1789 return 0;
1790
1791 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1792 to combine them, so it prints out the right values.
1793 Here we keep track of the registers. */
1794 if (op == 0)
1795 {
1796 *pval = imm7_val (src);
1797 if (src & 0x40)
1798 *pval |= 0xFFFFFF80;
1799 else
1800 *pval &= 0x7F;
1801 }
1802
1803 if (op == 0)
1804 {
1805 OUTS (outf, dregs (dst));
1806 OUTS (outf, " = ");
1807 OUTS (outf, imm7 (src));
1808 OUTS (outf, " (X);\t\t/*\t\t");
1809 OUTS (outf, dregs (dst));
1810 OUTS (outf, "=");
1811 OUTS (outf, uimm32 (*pval));
1812 OUTS (outf, "(");
1813 OUTS (outf, imm32 (*pval));
1814 OUTS (outf, ") */");
1815 comment = 1;
1816 }
1817 else if (op == 1)
1818 {
1819 OUTS (outf, dregs (dst));
1820 OUTS (outf, " += ");
1821 OUTS (outf, imm7 (src));
1822 OUTS (outf, ";\t\t/* (");
1823 OUTS (outf, imm7d (src));
1824 OUTS (outf, ") */");
1825 comment = 1;
1826 }
1827 else
1828 return 0;
1829
1830 return 2;
1831 }
1832
1833 static int
1834 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1835 {
1836 /* COMPI2opP
1837 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1838 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1839 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1840 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1841 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1842 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1843
1844 bu32 *pval = get_allreg (1, dst);
1845
1846 if (parallel)
1847 return 0;
1848
1849 if (op == 0)
1850 {
1851 *pval = imm7_val (src);
1852 if (src & 0x40)
1853 *pval |= 0xFFFFFF80;
1854 else
1855 *pval &= 0x7F;
1856 }
1857
1858 if (op == 0)
1859 {
1860 OUTS (outf, pregs (dst));
1861 OUTS (outf, " = ");
1862 OUTS (outf, imm7 (src));
1863 OUTS (outf, " (X);\t\t/*\t\t");
1864 OUTS (outf, pregs (dst));
1865 OUTS (outf, "=");
1866 OUTS (outf, uimm32 (*pval));
1867 OUTS (outf, "(");
1868 OUTS (outf, imm32 (*pval));
1869 OUTS (outf, ") */");
1870 comment = 1;
1871 }
1872 else if (op == 1)
1873 {
1874 OUTS (outf, pregs (dst));
1875 OUTS (outf, " += ");
1876 OUTS (outf, imm7 (src));
1877 OUTS (outf, ";\t\t/* (");
1878 OUTS (outf, imm7d (src));
1879 OUTS (outf, ") */");
1880 comment = 1;
1881 }
1882 else
1883 return 0;
1884
1885 return 2;
1886 }
1887
1888 static int
1889 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1890 {
1891 /* LDSTpmod
1892 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1893 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1894 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1895 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1896 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1897 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1898 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1899 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1900
1901 if (aop == 1 && W == 0 && idx == ptr)
1902 {
1903 OUTS (outf, dregs_lo (reg));
1904 OUTS (outf, " = W[");
1905 OUTS (outf, pregs (ptr));
1906 OUTS (outf, "]");
1907 }
1908 else if (aop == 2 && W == 0 && idx == ptr)
1909 {
1910 OUTS (outf, dregs_hi (reg));
1911 OUTS (outf, " = W[");
1912 OUTS (outf, pregs (ptr));
1913 OUTS (outf, "]");
1914 }
1915 else if (aop == 1 && W == 1 && idx == ptr)
1916 {
1917 OUTS (outf, "W[");
1918 OUTS (outf, pregs (ptr));
1919 OUTS (outf, "] = ");
1920 OUTS (outf, dregs_lo (reg));
1921 }
1922 else if (aop == 2 && W == 1 && idx == ptr)
1923 {
1924 OUTS (outf, "W[");
1925 OUTS (outf, pregs (ptr));
1926 OUTS (outf, "] = ");
1927 OUTS (outf, dregs_hi (reg));
1928 }
1929 else if (aop == 0 && W == 0)
1930 {
1931 OUTS (outf, dregs (reg));
1932 OUTS (outf, " = [");
1933 OUTS (outf, pregs (ptr));
1934 OUTS (outf, " ++ ");
1935 OUTS (outf, pregs (idx));
1936 OUTS (outf, "]");
1937 }
1938 else if (aop == 1 && W == 0)
1939 {
1940 OUTS (outf, dregs_lo (reg));
1941 OUTS (outf, " = W[");
1942 OUTS (outf, pregs (ptr));
1943 OUTS (outf, " ++ ");
1944 OUTS (outf, pregs (idx));
1945 OUTS (outf, "]");
1946 }
1947 else if (aop == 2 && W == 0)
1948 {
1949 OUTS (outf, dregs_hi (reg));
1950 OUTS (outf, " = W[");
1951 OUTS (outf, pregs (ptr));
1952 OUTS (outf, " ++ ");
1953 OUTS (outf, pregs (idx));
1954 OUTS (outf, "]");
1955 }
1956 else if (aop == 3 && W == 0)
1957 {
1958 OUTS (outf, dregs (reg));
1959 OUTS (outf, " = W[");
1960 OUTS (outf, pregs (ptr));
1961 OUTS (outf, " ++ ");
1962 OUTS (outf, pregs (idx));
1963 OUTS (outf, "] (Z)");
1964 }
1965 else if (aop == 3 && W == 1)
1966 {
1967 OUTS (outf, dregs (reg));
1968 OUTS (outf, " = W[");
1969 OUTS (outf, pregs (ptr));
1970 OUTS (outf, " ++ ");
1971 OUTS (outf, pregs (idx));
1972 OUTS (outf, "] (X)");
1973 }
1974 else if (aop == 0 && W == 1)
1975 {
1976 OUTS (outf, "[");
1977 OUTS (outf, pregs (ptr));
1978 OUTS (outf, " ++ ");
1979 OUTS (outf, pregs (idx));
1980 OUTS (outf, "] = ");
1981 OUTS (outf, dregs (reg));
1982 }
1983 else if (aop == 1 && W == 1)
1984 {
1985 OUTS (outf, "W[");
1986 OUTS (outf, pregs (ptr));
1987 OUTS (outf, " ++ ");
1988 OUTS (outf, pregs (idx));
1989 OUTS (outf, "] = ");
1990 OUTS (outf, dregs_lo (reg));
1991 }
1992 else if (aop == 2 && W == 1)
1993 {
1994 OUTS (outf, "W[");
1995 OUTS (outf, pregs (ptr));
1996 OUTS (outf, " ++ ");
1997 OUTS (outf, pregs (idx));
1998 OUTS (outf, "] = ");
1999 OUTS (outf, dregs_hi (reg));
2000 }
2001 else
2002 return 0;
2003
2004 return 2;
2005 }
2006
2007 static int
2008 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2009 {
2010 /* dagMODim
2011 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2012 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2013 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2014 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2015 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2016 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2017 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2018
2019 if (op == 0 && br == 1)
2020 {
2021 OUTS (outf, iregs (i));
2022 OUTS (outf, " += ");
2023 OUTS (outf, mregs (m));
2024 OUTS (outf, " (BREV)");
2025 }
2026 else if (op == 0)
2027 {
2028 OUTS (outf, iregs (i));
2029 OUTS (outf, " += ");
2030 OUTS (outf, mregs (m));
2031 }
2032 else if (op == 1 && br == 0)
2033 {
2034 OUTS (outf, iregs (i));
2035 OUTS (outf, " -= ");
2036 OUTS (outf, mregs (m));
2037 }
2038 else
2039 return 0;
2040
2041 return 2;
2042 }
2043
2044 static int
2045 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2046 {
2047 /* dagMODik
2048 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2049 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2050 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2051 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2052 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2053
2054 if (op == 0)
2055 {
2056 OUTS (outf, iregs (i));
2057 OUTS (outf, " += 0x2");
2058 }
2059 else if (op == 1)
2060 {
2061 OUTS (outf, iregs (i));
2062 OUTS (outf, " -= 0x2");
2063 }
2064 else if (op == 2)
2065 {
2066 OUTS (outf, iregs (i));
2067 OUTS (outf, " += 0x4");
2068 }
2069 else if (op == 3)
2070 {
2071 OUTS (outf, iregs (i));
2072 OUTS (outf, " -= 0x4");
2073 }
2074 else
2075 return 0;
2076
2077 if (! parallel )
2078 {
2079 OUTS (outf, ";\t\t/* ( ");
2080 if (op == 0 || op == 1)
2081 OUTS (outf, "2");
2082 else if (op == 2 || op == 3)
2083 OUTS (outf, "4");
2084 OUTS (outf, ") */");
2085 comment = 1;
2086 }
2087
2088 return 2;
2089 }
2090
2091 static int
2092 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2093 {
2094 /* dspLDST
2095 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2096 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2097 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2098 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2099 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2100 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2101 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2102 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2103
2104 if (aop == 0 && W == 0 && m == 0)
2105 {
2106 OUTS (outf, dregs (reg));
2107 OUTS (outf, " = [");
2108 OUTS (outf, iregs (i));
2109 OUTS (outf, "++]");
2110 }
2111 else if (aop == 0 && W == 0 && m == 1)
2112 {
2113 OUTS (outf, dregs_lo (reg));
2114 OUTS (outf, " = W[");
2115 OUTS (outf, iregs (i));
2116 OUTS (outf, "++]");
2117 }
2118 else if (aop == 0 && W == 0 && m == 2)
2119 {
2120 OUTS (outf, dregs_hi (reg));
2121 OUTS (outf, " = W[");
2122 OUTS (outf, iregs (i));
2123 OUTS (outf, "++]");
2124 }
2125 else if (aop == 1 && W == 0 && m == 0)
2126 {
2127 OUTS (outf, dregs (reg));
2128 OUTS (outf, " = [");
2129 OUTS (outf, iregs (i));
2130 OUTS (outf, "--]");
2131 }
2132 else if (aop == 1 && W == 0 && m == 1)
2133 {
2134 OUTS (outf, dregs_lo (reg));
2135 OUTS (outf, " = W[");
2136 OUTS (outf, iregs (i));
2137 OUTS (outf, "--]");
2138 }
2139 else if (aop == 1 && W == 0 && m == 2)
2140 {
2141 OUTS (outf, dregs_hi (reg));
2142 OUTS (outf, " = W[");
2143 OUTS (outf, iregs (i));
2144 OUTS (outf, "--]");
2145 }
2146 else if (aop == 2 && W == 0 && m == 0)
2147 {
2148 OUTS (outf, dregs (reg));
2149 OUTS (outf, " = [");
2150 OUTS (outf, iregs (i));
2151 OUTS (outf, "]");
2152 }
2153 else if (aop == 2 && W == 0 && m == 1)
2154 {
2155 OUTS (outf, dregs_lo (reg));
2156 OUTS (outf, " = W[");
2157 OUTS (outf, iregs (i));
2158 OUTS (outf, "]");
2159 }
2160 else if (aop == 2 && W == 0 && m == 2)
2161 {
2162 OUTS (outf, dregs_hi (reg));
2163 OUTS (outf, " = W[");
2164 OUTS (outf, iregs (i));
2165 OUTS (outf, "]");
2166 }
2167 else if (aop == 0 && W == 1 && m == 0)
2168 {
2169 OUTS (outf, "[");
2170 OUTS (outf, iregs (i));
2171 OUTS (outf, "++] = ");
2172 OUTS (outf, dregs (reg));
2173 }
2174 else if (aop == 0 && W == 1 && m == 1)
2175 {
2176 OUTS (outf, "W[");
2177 OUTS (outf, iregs (i));
2178 OUTS (outf, "++] = ");
2179 OUTS (outf, dregs_lo (reg));
2180 }
2181 else if (aop == 0 && W == 1 && m == 2)
2182 {
2183 OUTS (outf, "W[");
2184 OUTS (outf, iregs (i));
2185 OUTS (outf, "++] = ");
2186 OUTS (outf, dregs_hi (reg));
2187 }
2188 else if (aop == 1 && W == 1 && m == 0)
2189 {
2190 OUTS (outf, "[");
2191 OUTS (outf, iregs (i));
2192 OUTS (outf, "--] = ");
2193 OUTS (outf, dregs (reg));
2194 }
2195 else if (aop == 1 && W == 1 && m == 1)
2196 {
2197 OUTS (outf, "W[");
2198 OUTS (outf, iregs (i));
2199 OUTS (outf, "--] = ");
2200 OUTS (outf, dregs_lo (reg));
2201 }
2202 else if (aop == 1 && W == 1 && m == 2)
2203 {
2204 OUTS (outf, "W[");
2205 OUTS (outf, iregs (i));
2206 OUTS (outf, "--] = ");
2207 OUTS (outf, dregs_hi (reg));
2208 }
2209 else if (aop == 2 && W == 1 && m == 0)
2210 {
2211 OUTS (outf, "[");
2212 OUTS (outf, iregs (i));
2213 OUTS (outf, "] = ");
2214 OUTS (outf, dregs (reg));
2215 }
2216 else if (aop == 2 && W == 1 && m == 1)
2217 {
2218 OUTS (outf, "W[");
2219 OUTS (outf, iregs (i));
2220 OUTS (outf, "] = ");
2221 OUTS (outf, dregs_lo (reg));
2222 }
2223 else if (aop == 2 && W == 1 && m == 2)
2224 {
2225 OUTS (outf, "W[");
2226 OUTS (outf, iregs (i));
2227 OUTS (outf, "] = ");
2228 OUTS (outf, dregs_hi (reg));
2229 }
2230 else if (aop == 3 && W == 0)
2231 {
2232 OUTS (outf, dregs (reg));
2233 OUTS (outf, " = [");
2234 OUTS (outf, iregs (i));
2235 OUTS (outf, " ++ ");
2236 OUTS (outf, mregs (m));
2237 OUTS (outf, "]");
2238 }
2239 else if (aop == 3 && W == 1)
2240 {
2241 OUTS (outf, "[");
2242 OUTS (outf, iregs (i));
2243 OUTS (outf, " ++ ");
2244 OUTS (outf, mregs (m));
2245 OUTS (outf, "] = ");
2246 OUTS (outf, dregs (reg));
2247 }
2248 else
2249 return 0;
2250
2251 return 2;
2252 }
2253
2254 static int
2255 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2256 {
2257 /* LDST
2258 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2259 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2260 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2261 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2262 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2263 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2264 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2265 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2266 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2267
2268 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2269 {
2270 OUTS (outf, dregs (reg));
2271 OUTS (outf, " = [");
2272 OUTS (outf, pregs (ptr));
2273 OUTS (outf, "++]");
2274 }
2275 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2276 {
2277 OUTS (outf, pregs (reg));
2278 OUTS (outf, " = [");
2279 OUTS (outf, pregs (ptr));
2280 OUTS (outf, "++]");
2281 }
2282 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2283 {
2284 OUTS (outf, dregs (reg));
2285 OUTS (outf, " = W[");
2286 OUTS (outf, pregs (ptr));
2287 OUTS (outf, "++] (Z)");
2288 }
2289 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2290 {
2291 OUTS (outf, dregs (reg));
2292 OUTS (outf, " = W[");
2293 OUTS (outf, pregs (ptr));
2294 OUTS (outf, "++] (X)");
2295 }
2296 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2297 {
2298 OUTS (outf, dregs (reg));
2299 OUTS (outf, " = B[");
2300 OUTS (outf, pregs (ptr));
2301 OUTS (outf, "++] (Z)");
2302 }
2303 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2304 {
2305 OUTS (outf, dregs (reg));
2306 OUTS (outf, " = B[");
2307 OUTS (outf, pregs (ptr));
2308 OUTS (outf, "++] (X)");
2309 }
2310 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2311 {
2312 OUTS (outf, dregs (reg));
2313 OUTS (outf, " = [");
2314 OUTS (outf, pregs (ptr));
2315 OUTS (outf, "--]");
2316 }
2317 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2318 {
2319 OUTS (outf, pregs (reg));
2320 OUTS (outf, " = [");
2321 OUTS (outf, pregs (ptr));
2322 OUTS (outf, "--]");
2323 }
2324 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2325 {
2326 OUTS (outf, dregs (reg));
2327 OUTS (outf, " = W[");
2328 OUTS (outf, pregs (ptr));
2329 OUTS (outf, "--] (Z)");
2330 }
2331 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2332 {
2333 OUTS (outf, dregs (reg));
2334 OUTS (outf, " = W[");
2335 OUTS (outf, pregs (ptr));
2336 OUTS (outf, "--] (X)");
2337 }
2338 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2339 {
2340 OUTS (outf, dregs (reg));
2341 OUTS (outf, " = B[");
2342 OUTS (outf, pregs (ptr));
2343 OUTS (outf, "--] (Z)");
2344 }
2345 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2346 {
2347 OUTS (outf, dregs (reg));
2348 OUTS (outf, " = B[");
2349 OUTS (outf, pregs (ptr));
2350 OUTS (outf, "--] (X)");
2351 }
2352 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2353 {
2354 OUTS (outf, dregs (reg));
2355 OUTS (outf, " = [");
2356 OUTS (outf, pregs (ptr));
2357 OUTS (outf, "]");
2358 }
2359 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2360 {
2361 OUTS (outf, pregs (reg));
2362 OUTS (outf, " = [");
2363 OUTS (outf, pregs (ptr));
2364 OUTS (outf, "]");
2365 }
2366 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2367 {
2368 OUTS (outf, dregs (reg));
2369 OUTS (outf, " = W[");
2370 OUTS (outf, pregs (ptr));
2371 OUTS (outf, "] (Z)");
2372 }
2373 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2374 {
2375 OUTS (outf, dregs (reg));
2376 OUTS (outf, " = W[");
2377 OUTS (outf, pregs (ptr));
2378 OUTS (outf, "] (X)");
2379 }
2380 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2381 {
2382 OUTS (outf, dregs (reg));
2383 OUTS (outf, " = B[");
2384 OUTS (outf, pregs (ptr));
2385 OUTS (outf, "] (Z)");
2386 }
2387 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2388 {
2389 OUTS (outf, dregs (reg));
2390 OUTS (outf, " = B[");
2391 OUTS (outf, pregs (ptr));
2392 OUTS (outf, "] (X)");
2393 }
2394 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2395 {
2396 OUTS (outf, "[");
2397 OUTS (outf, pregs (ptr));
2398 OUTS (outf, "++] = ");
2399 OUTS (outf, dregs (reg));
2400 }
2401 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2402 {
2403 OUTS (outf, "[");
2404 OUTS (outf, pregs (ptr));
2405 OUTS (outf, "++] = ");
2406 OUTS (outf, pregs (reg));
2407 }
2408 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2409 {
2410 OUTS (outf, "W[");
2411 OUTS (outf, pregs (ptr));
2412 OUTS (outf, "++] = ");
2413 OUTS (outf, dregs (reg));
2414 }
2415 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2416 {
2417 OUTS (outf, "B[");
2418 OUTS (outf, pregs (ptr));
2419 OUTS (outf, "++] = ");
2420 OUTS (outf, dregs (reg));
2421 }
2422 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2423 {
2424 OUTS (outf, "[");
2425 OUTS (outf, pregs (ptr));
2426 OUTS (outf, "--] = ");
2427 OUTS (outf, dregs (reg));
2428 }
2429 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2430 {
2431 OUTS (outf, "[");
2432 OUTS (outf, pregs (ptr));
2433 OUTS (outf, "--] = ");
2434 OUTS (outf, pregs (reg));
2435 }
2436 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2437 {
2438 OUTS (outf, "W[");
2439 OUTS (outf, pregs (ptr));
2440 OUTS (outf, "--] = ");
2441 OUTS (outf, dregs (reg));
2442 }
2443 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2444 {
2445 OUTS (outf, "B[");
2446 OUTS (outf, pregs (ptr));
2447 OUTS (outf, "--] = ");
2448 OUTS (outf, dregs (reg));
2449 }
2450 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2451 {
2452 OUTS (outf, "[");
2453 OUTS (outf, pregs (ptr));
2454 OUTS (outf, "] = ");
2455 OUTS (outf, dregs (reg));
2456 }
2457 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2458 {
2459 OUTS (outf, "[");
2460 OUTS (outf, pregs (ptr));
2461 OUTS (outf, "] = ");
2462 OUTS (outf, pregs (reg));
2463 }
2464 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2465 {
2466 OUTS (outf, "W[");
2467 OUTS (outf, pregs (ptr));
2468 OUTS (outf, "] = ");
2469 OUTS (outf, dregs (reg));
2470 }
2471 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2472 {
2473 OUTS (outf, "B[");
2474 OUTS (outf, pregs (ptr));
2475 OUTS (outf, "] = ");
2476 OUTS (outf, dregs (reg));
2477 }
2478 else
2479 return 0;
2480
2481 return 2;
2482 }
2483
2484 static int
2485 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2486 {
2487 /* LDSTiiFP
2488 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2489 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2490 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2491 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2492 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2493 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2494
2495 if (W == 0)
2496 {
2497 OUTS (outf, dpregs (reg));
2498 OUTS (outf, " = [FP ");
2499 OUTS (outf, negimm5s4 (offset));
2500 OUTS (outf, "]");
2501 }
2502 else if (W == 1)
2503 {
2504 OUTS (outf, "[FP ");
2505 OUTS (outf, negimm5s4 (offset));
2506 OUTS (outf, "] = ");
2507 OUTS (outf, dpregs (reg));
2508 }
2509 else
2510 return 0;
2511
2512 return 2;
2513 }
2514
2515 static int
2516 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2517 {
2518 /* LDSTii
2519 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2520 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2521 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2522 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2523 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2524 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2525 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2526 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2527
2528 if (W == 0 && op == 0)
2529 {
2530 OUTS (outf, dregs (reg));
2531 OUTS (outf, " = [");
2532 OUTS (outf, pregs (ptr));
2533 OUTS (outf, " + ");
2534 OUTS (outf, uimm4s4 (offset));
2535 OUTS (outf, "]");
2536 }
2537 else if (W == 0 && op == 1)
2538 {
2539 OUTS (outf, dregs (reg));
2540 OUTS (outf, " = W[");
2541 OUTS (outf, pregs (ptr));
2542 OUTS (outf, " + ");
2543 OUTS (outf, uimm4s2 (offset));
2544 OUTS (outf, "] (Z)");
2545 }
2546 else if (W == 0 && op == 2)
2547 {
2548 OUTS (outf, dregs (reg));
2549 OUTS (outf, " = W[");
2550 OUTS (outf, pregs (ptr));
2551 OUTS (outf, " + ");
2552 OUTS (outf, uimm4s2 (offset));
2553 OUTS (outf, "] (X)");
2554 }
2555 else if (W == 0 && op == 3)
2556 {
2557 OUTS (outf, pregs (reg));
2558 OUTS (outf, " = [");
2559 OUTS (outf, pregs (ptr));
2560 OUTS (outf, " + ");
2561 OUTS (outf, uimm4s4 (offset));
2562 OUTS (outf, "]");
2563 }
2564 else if (W == 1 && op == 0)
2565 {
2566 OUTS (outf, "[");
2567 OUTS (outf, pregs (ptr));
2568 OUTS (outf, " + ");
2569 OUTS (outf, uimm4s4 (offset));
2570 OUTS (outf, "] = ");
2571 OUTS (outf, dregs (reg));
2572 }
2573 else if (W == 1 && op == 1)
2574 {
2575 OUTS (outf, "W[");
2576 OUTS (outf, pregs (ptr));
2577 OUTS (outf, " + ");
2578 OUTS (outf, uimm4s2 (offset));
2579 OUTS (outf, "] = ");
2580 OUTS (outf, dregs (reg));
2581 }
2582 else if (W == 1 && op == 3)
2583 {
2584 OUTS (outf, "[");
2585 OUTS (outf, pregs (ptr));
2586 OUTS (outf, " + ");
2587 OUTS (outf, uimm4s4 (offset));
2588 OUTS (outf, "] = ");
2589 OUTS (outf, pregs (reg));
2590 }
2591 else
2592 return 0;
2593
2594 return 2;
2595 }
2596
2597 static int
2598 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2599 {
2600 /* LoopSetup
2601 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2602 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2603 |.reg...........| - | - |.eoffset...............................|
2604 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2605 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2606 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2607 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2608 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2609 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2610
2611 if (parallel)
2612 return 0;
2613
2614 if (rop == 0)
2615 {
2616 OUTS (outf, "LSETUP");
2617 OUTS (outf, "(0x");
2618 OUTS (outf, pcrel4 (soffset));
2619 OUTS (outf, ", 0x");
2620 OUTS (outf, lppcrel10 (eoffset));
2621 OUTS (outf, ") ");
2622 OUTS (outf, counters (c));
2623 }
2624 else if (rop == 1)
2625 {
2626 OUTS (outf, "LSETUP");
2627 OUTS (outf, "(0x");
2628 OUTS (outf, pcrel4 (soffset));
2629 OUTS (outf, ", 0x");
2630 OUTS (outf, lppcrel10 (eoffset));
2631 OUTS (outf, ") ");
2632 OUTS (outf, counters (c));
2633 OUTS (outf, " = ");
2634 OUTS (outf, pregs (reg));
2635 }
2636 else if (rop == 3)
2637 {
2638 OUTS (outf, "LSETUP");
2639 OUTS (outf, "(0x");
2640 OUTS (outf, pcrel4 (soffset));
2641 OUTS (outf, ", 0x");
2642 OUTS (outf, lppcrel10 (eoffset));
2643 OUTS (outf, ") ");
2644 OUTS (outf, counters (c));
2645 OUTS (outf, " = ");
2646 OUTS (outf, pregs (reg));
2647 OUTS (outf, " >> 0x1");
2648 }
2649 else
2650 return 0;
2651
2652 return 4;
2653 }
2654
2655 static int
2656 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2657 {
2658 /* LDIMMhalf
2659 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2660 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2661 |.hword.........................................................|
2662 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2663 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2664 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2665 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2666 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2667 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2668 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2669
2670 bu32 *pval = get_allreg (grp, reg);
2671
2672 if (parallel)
2673 return 0;
2674
2675 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2676 to combine them, so it prints out the right values.
2677 Here we keep track of the registers. */
2678 if (H == 0 && S == 1 && Z == 0)
2679 {
2680 /* regs = imm16 (x) */
2681 *pval = imm16_val (hword);
2682 if (hword & 0x8000)
2683 *pval |= 0xFFFF0000;
2684 else
2685 *pval &= 0xFFFF;
2686 }
2687 else if (H == 0 && S == 0 && Z == 1)
2688 {
2689 /* regs = luimm16 (Z) */
2690 *pval = luimm16_val (hword);
2691 *pval &= 0xFFFF;
2692 }
2693 else if (H == 0 && S == 0 && Z == 0)
2694 {
2695 /* regs_lo = luimm16 */
2696 *pval &= 0xFFFF0000;
2697 *pval |= luimm16_val (hword);
2698 }
2699 else if (H == 1 && S == 0 && Z == 0)
2700 {
2701 /* regs_hi = huimm16 */
2702 *pval &= 0xFFFF;
2703 *pval |= luimm16_val (hword) << 16;
2704 }
2705
2706 /* Here we do the disassembly */
2707 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2708 {
2709 OUTS (outf, dregs_lo (reg));
2710 OUTS (outf, " = ");
2711 OUTS (outf, uimm16 (hword));
2712 }
2713 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2714 {
2715 OUTS (outf, dregs_hi (reg));
2716 OUTS (outf, " = ");
2717 OUTS (outf, uimm16 (hword));
2718 }
2719 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2720 {
2721 OUTS (outf, dregs (reg));
2722 OUTS (outf, " = ");
2723 OUTS (outf, imm16 (hword));
2724 OUTS (outf, " (X)");
2725 }
2726 else if (H == 0 && S == 1 && Z == 0)
2727 {
2728 OUTS (outf, regs (reg, grp));
2729 OUTS (outf, " = ");
2730 OUTS (outf, imm16 (hword));
2731 OUTS (outf, " (X)");
2732 }
2733 else if (H == 0 && S == 0 && Z == 1)
2734 {
2735 OUTS (outf, regs (reg, grp));
2736 OUTS (outf, " = ");
2737 OUTS (outf, uimm16 (hword));
2738 OUTS (outf, " (Z)");
2739 }
2740 else if (H == 0 && S == 0 && Z == 0)
2741 {
2742 OUTS (outf, regs_lo (reg, grp));
2743 OUTS (outf, " = ");
2744 OUTS (outf, uimm16 (hword));
2745 }
2746 else if (H == 1 && S == 0 && Z == 0)
2747 {
2748 OUTS (outf, regs_hi (reg, grp));
2749 OUTS (outf, " = ");
2750 OUTS (outf, uimm16 (hword));
2751 }
2752 else
2753 return 0;
2754
2755 /* And we print out the 32-bit value if it is a pointer. */
2756 if (S == 0 && Z == 0)
2757 {
2758 OUTS (outf, ";\t\t/* (");
2759 OUTS (outf, imm16d (hword));
2760 OUTS (outf, ")\t");
2761
2762 /* If it is an MMR, don't print the symbol. */
2763 if (*pval < 0xFFC00000 && grp == 1)
2764 {
2765 OUTS (outf, regs (reg, grp));
2766 OUTS (outf, "=0x");
2767 OUTS (outf, huimm32e (*pval));
2768 }
2769 else
2770 {
2771 OUTS (outf, regs (reg, grp));
2772 OUTS (outf, "=0x");
2773 OUTS (outf, huimm32e (*pval));
2774 OUTS (outf, "(");
2775 OUTS (outf, imm32 (*pval));
2776 OUTS (outf, ")");
2777 }
2778
2779 OUTS (outf, " */");
2780 comment = 1;
2781 }
2782 if (S == 1 || Z == 1)
2783 {
2784 OUTS (outf, ";\t\t/*\t\t");
2785 OUTS (outf, regs (reg, grp));
2786 OUTS (outf, "=0x");
2787 OUTS (outf, huimm32e (*pval));
2788 OUTS (outf, "(");
2789 OUTS (outf, imm32 (*pval));
2790 OUTS (outf, ") */");
2791 comment = 1;
2792 }
2793 return 4;
2794 }
2795
2796 static int
2797 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2798 {
2799 /* CALLa
2800 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2801 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2802 |.lsw...........................................................|
2803 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2804 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2805 int lsw = ((iw1 >> 0) & 0xffff);
2806 int msw = ((iw0 >> 0) & 0xff);
2807
2808 if (parallel)
2809 return 0;
2810
2811 if (S == 1)
2812 OUTS (outf, "CALL 0x");
2813 else if (S == 0)
2814 OUTS (outf, "JUMP.L 0x");
2815 else
2816 return 0;
2817
2818 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2819 return 4;
2820 }
2821
2822 static int
2823 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2824 {
2825 /* LDSTidxI
2826 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2827 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2828 |.offset........................................................|
2829 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2830 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2831 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2832 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2833 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2834 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2835 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2836
2837 if (W == 0 && sz == 0 && Z == 0)
2838 {
2839 OUTS (outf, dregs (reg));
2840 OUTS (outf, " = [");
2841 OUTS (outf, pregs (ptr));
2842 OUTS (outf, " + ");
2843 OUTS (outf, imm16s4 (offset));
2844 OUTS (outf, "]");
2845 }
2846 else if (W == 0 && sz == 0 && Z == 1)
2847 {
2848 OUTS (outf, pregs (reg));
2849 OUTS (outf, " = [");
2850 OUTS (outf, pregs (ptr));
2851 OUTS (outf, " + ");
2852 OUTS (outf, imm16s4 (offset));
2853 OUTS (outf, "]");
2854 }
2855 else if (W == 0 && sz == 1 && Z == 0)
2856 {
2857 OUTS (outf, dregs (reg));
2858 OUTS (outf, " = W[");
2859 OUTS (outf, pregs (ptr));
2860 OUTS (outf, " + ");
2861 OUTS (outf, imm16s2 (offset));
2862 OUTS (outf, "] (Z)");
2863 }
2864 else if (W == 0 && sz == 1 && Z == 1)
2865 {
2866 OUTS (outf, dregs (reg));
2867 OUTS (outf, " = W[");
2868 OUTS (outf, pregs (ptr));
2869 OUTS (outf, " + ");
2870 OUTS (outf, imm16s2 (offset));
2871 OUTS (outf, "] (X)");
2872 }
2873 else if (W == 0 && sz == 2 && Z == 0)
2874 {
2875 OUTS (outf, dregs (reg));
2876 OUTS (outf, " = B[");
2877 OUTS (outf, pregs (ptr));
2878 OUTS (outf, " + ");
2879 OUTS (outf, imm16 (offset));
2880 OUTS (outf, "] (Z)");
2881 }
2882 else if (W == 0 && sz == 2 && Z == 1)
2883 {
2884 OUTS (outf, dregs (reg));
2885 OUTS (outf, " = B[");
2886 OUTS (outf, pregs (ptr));
2887 OUTS (outf, " + ");
2888 OUTS (outf, imm16 (offset));
2889 OUTS (outf, "] (X)");
2890 }
2891 else if (W == 1 && sz == 0 && Z == 0)
2892 {
2893 OUTS (outf, "[");
2894 OUTS (outf, pregs (ptr));
2895 OUTS (outf, " + ");
2896 OUTS (outf, imm16s4 (offset));
2897 OUTS (outf, "] = ");
2898 OUTS (outf, dregs (reg));
2899 }
2900 else if (W == 1 && sz == 0 && Z == 1)
2901 {
2902 OUTS (outf, "[");
2903 OUTS (outf, pregs (ptr));
2904 OUTS (outf, " + ");
2905 OUTS (outf, imm16s4 (offset));
2906 OUTS (outf, "] = ");
2907 OUTS (outf, pregs (reg));
2908 }
2909 else if (W == 1 && sz == 1 && Z == 0)
2910 {
2911 OUTS (outf, "W[");
2912 OUTS (outf, pregs (ptr));
2913 OUTS (outf, " + ");
2914 OUTS (outf, imm16s2 (offset));
2915 OUTS (outf, "] = ");
2916 OUTS (outf, dregs (reg));
2917 }
2918 else if (W == 1 && sz == 2 && Z == 0)
2919 {
2920 OUTS (outf, "B[");
2921 OUTS (outf, pregs (ptr));
2922 OUTS (outf, " + ");
2923 OUTS (outf, imm16 (offset));
2924 OUTS (outf, "] = ");
2925 OUTS (outf, dregs (reg));
2926 }
2927 else
2928 return 0;
2929
2930 return 4;
2931 }
2932
2933 static int
2934 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2935 {
2936 /* linkage
2937 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2938 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2939 |.framesize.....................................................|
2940 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2941 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2942 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2943
2944 if (parallel)
2945 return 0;
2946
2947 if (R == 0)
2948 {
2949 OUTS (outf, "LINK ");
2950 OUTS (outf, uimm16s4 (framesize));
2951 OUTS (outf, ";\t\t/* (");
2952 OUTS (outf, uimm16s4d (framesize));
2953 OUTS (outf, ") */");
2954 comment = 1;
2955 }
2956 else if (R == 1)
2957 OUTS (outf, "UNLINK");
2958 else
2959 return 0;
2960
2961 return 4;
2962 }
2963
2964 static int
2965 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2966 {
2967 /* dsp32mac
2968 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2969 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2970 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2971 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2972 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2973 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2974 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2975 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2976 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2977 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2978 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2979 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2980 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2981 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2982 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2983 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2984 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2985 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2986
2987 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2988 return 0;
2989
2990 if (op1 == 3 && MM)
2991 return 0;
2992
2993 if ((w1 || w0) && mmod == M_W32)
2994 return 0;
2995
2996 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2997 return 0;
2998
2999 if (w1 == 1 || op1 != 3)
3000 {
3001 if (w1)
3002 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3003
3004 if (op1 == 3)
3005 OUTS (outf, " = A1");
3006 else
3007 {
3008 if (w1)
3009 OUTS (outf, " = (");
3010 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3011 if (w1)
3012 OUTS (outf, ")");
3013 }
3014
3015 if (w0 == 1 || op0 != 3)
3016 {
3017 if (MM)
3018 OUTS (outf, " (M)");
3019 MM = 0;
3020 OUTS (outf, ", ");
3021 }
3022 }
3023
3024 if (w0 == 1 || op0 != 3)
3025 {
3026 if (w0)
3027 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3028
3029 if (op0 == 3)
3030 OUTS (outf, " = A0");
3031 else
3032 {
3033 if (w0)
3034 OUTS (outf, " = (");
3035 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3036 if (w0)
3037 OUTS (outf, ")");
3038 }
3039 }
3040
3041 decode_optmode (mmod, MM, outf);
3042
3043 return 4;
3044 }
3045
3046 static int
3047 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3048 {
3049 /* dsp32mult
3050 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3051 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3052 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3053 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3054 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3055 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3056 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3057 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3058 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3059 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3060 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3061 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3062 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3063 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3064 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3065 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3066
3067 if (w1 == 0 && w0 == 0)
3068 return 0;
3069
3070 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3071 return 0;
3072
3073 if (w1)
3074 {
3075 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3076 OUTS (outf, " = ");
3077 decode_multfunc (h01, h11, src0, src1, outf);
3078
3079 if (w0)
3080 {
3081 if (MM)
3082 OUTS (outf, " (M)");
3083 MM = 0;
3084 OUTS (outf, ", ");
3085 }
3086 }
3087
3088 if (w0)
3089 {
3090 OUTS (outf, dregs (dst));
3091 OUTS (outf, " = ");
3092 decode_multfunc (h00, h10, src0, src1, outf);
3093 }
3094
3095 decode_optmode (mmod, MM, outf);
3096 return 4;
3097 }
3098
3099 static int
3100 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3101 {
3102 /* dsp32alu
3103 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3104 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3105 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3106 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3107 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3108 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3109 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3110 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3111 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3112 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3113 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3114 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3115 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3116
3117 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3118 {
3119 OUTS (outf, "A0.L = ");
3120 OUTS (outf, dregs_lo (src0));
3121 }
3122 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3123 {
3124 OUTS (outf, "A1.H = ");
3125 OUTS (outf, dregs_hi (src0));
3126 }
3127 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3128 {
3129 OUTS (outf, "A1.L = ");
3130 OUTS (outf, dregs_lo (src0));
3131 }
3132 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3133 {
3134 OUTS (outf, "A0.H = ");
3135 OUTS (outf, dregs_hi (src0));
3136 }
3137 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3138 {
3139 OUTS (outf, dregs_hi (dst0));
3140 OUTS (outf, " = ");
3141 OUTS (outf, dregs (src0));
3142 OUTS (outf, " - ");
3143 OUTS (outf, dregs (src1));
3144 OUTS (outf, " (RND20)");
3145 }
3146 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3147 {
3148 OUTS (outf, dregs_hi (dst0));
3149 OUTS (outf, " = ");
3150 OUTS (outf, dregs (src0));
3151 OUTS (outf, " + ");
3152 OUTS (outf, dregs (src1));
3153 OUTS (outf, " (RND20)");
3154 }
3155 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3156 {
3157 OUTS (outf, dregs_lo (dst0));
3158 OUTS (outf, " = ");
3159 OUTS (outf, dregs (src0));
3160 OUTS (outf, " - ");
3161 OUTS (outf, dregs (src1));
3162 OUTS (outf, " (RND12)");
3163 }
3164 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3165 {
3166 OUTS (outf, dregs_lo (dst0));
3167 OUTS (outf, " = ");
3168 OUTS (outf, dregs (src0));
3169 OUTS (outf, " + ");
3170 OUTS (outf, dregs (src1));
3171 OUTS (outf, " (RND12)");
3172 }
3173 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3174 {
3175 OUTS (outf, dregs_lo (dst0));
3176 OUTS (outf, " = ");
3177 OUTS (outf, dregs (src0));
3178 OUTS (outf, " - ");
3179 OUTS (outf, dregs (src1));
3180 OUTS (outf, " (RND20)");
3181 }
3182 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3183 {
3184 OUTS (outf, dregs_hi (dst0));
3185 OUTS (outf, " = ");
3186 OUTS (outf, dregs (src0));
3187 OUTS (outf, " + ");
3188 OUTS (outf, dregs (src1));
3189 OUTS (outf, " (RND12)");
3190 }
3191 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3192 {
3193 OUTS (outf, dregs_lo (dst0));
3194 OUTS (outf, " = ");
3195 OUTS (outf, dregs (src0));
3196 OUTS (outf, " + ");
3197 OUTS (outf, dregs (src1));
3198 OUTS (outf, " (RND20)");
3199 }
3200 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3201 {
3202 OUTS (outf, dregs_hi (dst0));
3203 OUTS (outf, " = ");
3204 OUTS (outf, dregs (src0));
3205 OUTS (outf, " - ");
3206 OUTS (outf, dregs (src1));
3207 OUTS (outf, " (RND12)");
3208 }
3209 else if (HL == 1 && aop == 0 && aopcde == 2)
3210 {
3211 OUTS (outf, dregs_hi (dst0));
3212 OUTS (outf, " = ");
3213 OUTS (outf, dregs_lo (src0));
3214 OUTS (outf, " + ");
3215 OUTS (outf, dregs_lo (src1));
3216 amod1 (s, x, outf);
3217 }
3218 else if (HL == 1 && aop == 1 && aopcde == 2)
3219 {
3220 OUTS (outf, dregs_hi (dst0));
3221 OUTS (outf, " = ");
3222 OUTS (outf, dregs_lo (src0));
3223 OUTS (outf, " + ");
3224 OUTS (outf, dregs_hi (src1));
3225 amod1 (s, x, outf);
3226 }
3227 else if (HL == 1 && aop == 2 && aopcde == 2)
3228 {
3229 OUTS (outf, dregs_hi (dst0));
3230 OUTS (outf, " = ");
3231 OUTS (outf, dregs_hi (src0));
3232 OUTS (outf, " + ");
3233 OUTS (outf, dregs_lo (src1));
3234 amod1 (s, x, outf);
3235 }
3236 else if (HL == 1 && aop == 3 && aopcde == 2)
3237 {
3238 OUTS (outf, dregs_hi (dst0));
3239 OUTS (outf, " = ");
3240 OUTS (outf, dregs_hi (src0));
3241 OUTS (outf, " + ");
3242 OUTS (outf, dregs_hi (src1));
3243 amod1 (s, x, outf);
3244 }
3245 else if (HL == 0 && aop == 0 && aopcde == 3)
3246 {
3247 OUTS (outf, dregs_lo (dst0));
3248 OUTS (outf, " = ");
3249 OUTS (outf, dregs_lo (src0));
3250 OUTS (outf, " - ");
3251 OUTS (outf, dregs_lo (src1));
3252 amod1 (s, x, outf);
3253 }
3254 else if (HL == 0 && aop == 1 && aopcde == 3)
3255 {
3256 OUTS (outf, dregs_lo (dst0));
3257 OUTS (outf, " = ");
3258 OUTS (outf, dregs_lo (src0));
3259 OUTS (outf, " - ");
3260 OUTS (outf, dregs_hi (src1));
3261 amod1 (s, x, outf);
3262 }
3263 else if (HL == 0 && aop == 3 && aopcde == 2)
3264 {
3265 OUTS (outf, dregs_lo (dst0));
3266 OUTS (outf, " = ");
3267 OUTS (outf, dregs_hi (src0));
3268 OUTS (outf, " + ");
3269 OUTS (outf, dregs_hi (src1));
3270 amod1 (s, x, outf);
3271 }
3272 else if (HL == 1 && aop == 0 && aopcde == 3)
3273 {
3274 OUTS (outf, dregs_hi (dst0));
3275 OUTS (outf, " = ");
3276 OUTS (outf, dregs_lo (src0));
3277 OUTS (outf, " - ");
3278 OUTS (outf, dregs_lo (src1));
3279 amod1 (s, x, outf);
3280 }
3281 else if (HL == 1 && aop == 1 && aopcde == 3)
3282 {
3283 OUTS (outf, dregs_hi (dst0));
3284 OUTS (outf, " = ");
3285 OUTS (outf, dregs_lo (src0));
3286 OUTS (outf, " - ");
3287 OUTS (outf, dregs_hi (src1));
3288 amod1 (s, x, outf);
3289 }
3290 else if (HL == 1 && aop == 2 && aopcde == 3)
3291 {
3292 OUTS (outf, dregs_hi (dst0));
3293 OUTS (outf, " = ");
3294 OUTS (outf, dregs_hi (src0));
3295 OUTS (outf, " - ");
3296 OUTS (outf, dregs_lo (src1));
3297 amod1 (s, x, outf);
3298 }
3299 else if (HL == 1 && aop == 3 && aopcde == 3)
3300 {
3301 OUTS (outf, dregs_hi (dst0));
3302 OUTS (outf, " = ");
3303 OUTS (outf, dregs_hi (src0));
3304 OUTS (outf, " - ");
3305 OUTS (outf, dregs_hi (src1));
3306 amod1 (s, x, outf);
3307 }
3308 else if (HL == 0 && aop == 2 && aopcde == 2)
3309 {
3310 OUTS (outf, dregs_lo (dst0));
3311 OUTS (outf, " = ");
3312 OUTS (outf, dregs_hi (src0));
3313 OUTS (outf, " + ");
3314 OUTS (outf, dregs_lo (src1));
3315 amod1 (s, x, outf);
3316 }
3317 else if (HL == 0 && aop == 1 && aopcde == 2)
3318 {
3319 OUTS (outf, dregs_lo (dst0));
3320 OUTS (outf, " = ");
3321 OUTS (outf, dregs_lo (src0));
3322 OUTS (outf, " + ");
3323 OUTS (outf, dregs_hi (src1));
3324 amod1 (s, x, outf);
3325 }
3326 else if (HL == 0 && aop == 2 && aopcde == 3)
3327 {
3328 OUTS (outf, dregs_lo (dst0));
3329 OUTS (outf, " = ");
3330 OUTS (outf, dregs_hi (src0));
3331 OUTS (outf, " - ");
3332 OUTS (outf, dregs_lo (src1));
3333 amod1 (s, x, outf);
3334 }
3335 else if (HL == 0 && aop == 3 && aopcde == 3)
3336 {
3337 OUTS (outf, dregs_lo (dst0));
3338 OUTS (outf, " = ");
3339 OUTS (outf, dregs_hi (src0));
3340 OUTS (outf, " - ");
3341 OUTS (outf, dregs_hi (src1));
3342 amod1 (s, x, outf);
3343 }
3344 else if (HL == 0 && aop == 0 && aopcde == 2)
3345 {
3346 OUTS (outf, dregs_lo (dst0));
3347 OUTS (outf, " = ");
3348 OUTS (outf, dregs_lo (src0));
3349 OUTS (outf, " + ");
3350 OUTS (outf, dregs_lo (src1));
3351 amod1 (s, x, outf);
3352 }
3353 else if (aop == 0 && aopcde == 9 && s == 1)
3354 {
3355 OUTS (outf, "A0 = ");
3356 OUTS (outf, dregs (src0));
3357 }
3358 else if (aop == 3 && aopcde == 11 && s == 0)
3359 OUTS (outf, "A0 -= A1");
3360
3361 else if (aop == 3 && aopcde == 11 && s == 1)
3362 OUTS (outf, "A0 -= A1 (W32)");
3363
3364 else if (aop == 3 && aopcde == 22 && HL == 1)
3365 {
3366 OUTS (outf, dregs (dst0));
3367 OUTS (outf, " = BYTEOP2M (");
3368 OUTS (outf, dregs (src0 + 1));
3369 OUTS (outf, ":");
3370 OUTS (outf, imm5 (src0));
3371 OUTS (outf, ", ");
3372 OUTS (outf, dregs (src1 + 1));
3373 OUTS (outf, ":");
3374 OUTS (outf, imm5 (src1));
3375 OUTS (outf, ") (TH");
3376 if (s == 1)
3377 OUTS (outf, ", R)");
3378 else
3379 OUTS (outf, ")");
3380 }
3381 else if (aop == 3 && aopcde == 22 && HL == 0)
3382 {
3383 OUTS (outf, dregs (dst0));
3384 OUTS (outf, " = BYTEOP2M (");
3385 OUTS (outf, dregs (src0 + 1));
3386 OUTS (outf, ":");
3387 OUTS (outf, imm5 (src0));
3388 OUTS (outf, ", ");
3389 OUTS (outf, dregs (src1 + 1));
3390 OUTS (outf, ":");
3391 OUTS (outf, imm5 (src1));
3392 OUTS (outf, ") (TL");
3393 if (s == 1)
3394 OUTS (outf, ", R)");
3395 else
3396 OUTS (outf, ")");
3397 }
3398 else if (aop == 2 && aopcde == 22 && HL == 1)
3399 {
3400 OUTS (outf, dregs (dst0));
3401 OUTS (outf, " = BYTEOP2M (");
3402 OUTS (outf, dregs (src0 + 1));
3403 OUTS (outf, ":");
3404 OUTS (outf, imm5 (src0));
3405 OUTS (outf, ", ");
3406 OUTS (outf, dregs (src1 + 1));
3407 OUTS (outf, ":");
3408 OUTS (outf, imm5 (src1));
3409 OUTS (outf, ") (RNDH");
3410 if (s == 1)
3411 OUTS (outf, ", R)");
3412 else
3413 OUTS (outf, ")");
3414 }
3415 else if (aop == 2 && aopcde == 22 && HL == 0)
3416 {
3417 OUTS (outf, dregs (dst0));
3418 OUTS (outf, " = BYTEOP2M (");
3419 OUTS (outf, dregs (src0 + 1));
3420 OUTS (outf, ":");
3421 OUTS (outf, imm5 (src0));
3422 OUTS (outf, ", ");
3423 OUTS (outf, dregs (src1 + 1));
3424 OUTS (outf, ":");
3425 OUTS (outf, imm5 (src1));
3426 OUTS (outf, ") (RNDL");
3427 if (s == 1)
3428 OUTS (outf, ", R)");
3429 else
3430 OUTS (outf, ")");
3431 }
3432 else if (aop == 1 && aopcde == 22 && HL == 1)
3433 {
3434 OUTS (outf, dregs (dst0));
3435 OUTS (outf, " = BYTEOP2P (");
3436 OUTS (outf, dregs (src0 + 1));
3437 OUTS (outf, ":");
3438 OUTS (outf, imm5d (src0));
3439 OUTS (outf, ", ");
3440 OUTS (outf, dregs (src1 + 1));
3441 OUTS (outf, ":");
3442 OUTS (outf, imm5d (src1));
3443 OUTS (outf, ") (TH");
3444 if (s == 1)
3445 OUTS (outf, ", R)");
3446 else
3447 OUTS (outf, ")");
3448 }
3449 else if (aop == 1 && aopcde == 22 && HL == 0)
3450 {
3451 OUTS (outf, dregs (dst0));
3452 OUTS (outf, " = BYTEOP2P (");
3453 OUTS (outf, dregs (src0 + 1));
3454 OUTS (outf, ":");
3455 OUTS (outf, imm5d (src0));
3456 OUTS (outf, ", ");
3457 OUTS (outf, dregs (src1 + 1));
3458 OUTS (outf, ":");
3459 OUTS (outf, imm5d (src1));
3460 OUTS (outf, ") (TL");
3461 if (s == 1)
3462 OUTS (outf, ", R)");
3463 else
3464 OUTS (outf, ")");
3465 }
3466 else if (aop == 0 && aopcde == 22 && HL == 1)
3467 {
3468 OUTS (outf, dregs (dst0));
3469 OUTS (outf, " = BYTEOP2P (");
3470 OUTS (outf, dregs (src0 + 1));
3471 OUTS (outf, ":");
3472 OUTS (outf, imm5d (src0));
3473 OUTS (outf, ", ");
3474 OUTS (outf, dregs (src1 + 1));
3475 OUTS (outf, ":");
3476 OUTS (outf, imm5d (src1));
3477 OUTS (outf, ") (RNDH");
3478 if (s == 1)
3479 OUTS (outf, ", R)");
3480 else
3481 OUTS (outf, ")");
3482 }
3483 else if (aop == 0 && aopcde == 22 && HL == 0)
3484 {
3485 OUTS (outf, dregs (dst0));
3486 OUTS (outf, " = BYTEOP2P (");
3487 OUTS (outf, dregs (src0 + 1));
3488 OUTS (outf, ":");
3489 OUTS (outf, imm5d (src0));
3490 OUTS (outf, ", ");
3491 OUTS (outf, dregs (src1 + 1));
3492 OUTS (outf, ":");
3493 OUTS (outf, imm5d (src1));
3494 OUTS (outf, ") (RNDL");
3495 if (s == 1)
3496 OUTS (outf, ", R)");
3497 else
3498 OUTS (outf, ")");
3499 }
3500 else if (aop == 0 && s == 0 && aopcde == 8)
3501 OUTS (outf, "A0 = 0");
3502
3503 else if (aop == 0 && s == 1 && aopcde == 8)
3504 OUTS (outf, "A0 = A0 (S)");
3505
3506 else if (aop == 1 && s == 0 && aopcde == 8)
3507 OUTS (outf, "A1 = 0");
3508
3509 else if (aop == 1 && s == 1 && aopcde == 8)
3510 OUTS (outf, "A1 = A1 (S)");
3511
3512 else if (aop == 2 && s == 0 && aopcde == 8)
3513 OUTS (outf, "A1 = A0 = 0");
3514
3515 else if (aop == 2 && s == 1 && aopcde == 8)
3516 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3517
3518 else if (aop == 3 && s == 0 && aopcde == 8)
3519 OUTS (outf, "A0 = A1");
3520
3521 else if (aop == 3 && s == 1 && aopcde == 8)
3522 OUTS (outf, "A1 = A0");
3523
3524 else if (aop == 1 && aopcde == 9 && s == 0)
3525 {
3526 OUTS (outf, "A0.X = ");
3527 OUTS (outf, dregs_lo (src0));
3528 }
3529 else if (aop == 1 && HL == 0 && aopcde == 11)
3530 {
3531 OUTS (outf, dregs_lo (dst0));
3532 OUTS (outf, " = (A0 += A1)");
3533 }
3534 else if (aop == 3 && HL == 0 && aopcde == 16)
3535 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3536
3537 else if (aop == 0 && aopcde == 23 && HL == 1)
3538 {
3539 OUTS (outf, dregs (dst0));
3540 OUTS (outf, " = BYTEOP3P (");
3541 OUTS (outf, dregs (src0 + 1));
3542 OUTS (outf, ":");
3543 OUTS (outf, imm5d (src0));
3544 OUTS (outf, ", ");
3545 OUTS (outf, dregs (src1 + 1));
3546 OUTS (outf, ":");
3547 OUTS (outf, imm5d (src1));
3548 OUTS (outf, ") (HI");
3549 if (s == 1)
3550 OUTS (outf, ", R)");
3551 else
3552 OUTS (outf, ")");
3553 }
3554 else if (aop == 3 && aopcde == 9 && s == 0)
3555 {
3556 OUTS (outf, "A1.X = ");
3557 OUTS (outf, dregs_lo (src0));
3558 }
3559 else if (aop == 1 && HL == 1 && aopcde == 16)
3560 OUTS (outf, "A1 = ABS A1");
3561
3562 else if (aop == 0 && HL == 1 && aopcde == 16)
3563 OUTS (outf, "A1 = ABS A0");
3564
3565 else if (aop == 2 && aopcde == 9 && s == 1)
3566 {
3567 OUTS (outf, "A1 = ");
3568 OUTS (outf, dregs (src0));
3569 }
3570 else if (HL == 0 && aop == 3 && aopcde == 12)
3571 {
3572 OUTS (outf, dregs_lo (dst0));
3573 OUTS (outf, " = ");
3574 OUTS (outf, dregs (src0));
3575 OUTS (outf, " (RND)");
3576 }
3577 else if (aop == 1 && HL == 0 && aopcde == 16)
3578 OUTS (outf, "A0 = ABS A1");
3579
3580 else if (aop == 0 && HL == 0 && aopcde == 16)
3581 OUTS (outf, "A0 = ABS A0");
3582
3583 else if (aop == 3 && HL == 0 && aopcde == 15)
3584 {
3585 OUTS (outf, dregs (dst0));
3586 OUTS (outf, " = -");
3587 OUTS (outf, dregs (src0));
3588 OUTS (outf, " (V)");
3589 }
3590 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3591 {
3592 OUTS (outf, dregs (dst0));
3593 OUTS (outf, " = -");
3594 OUTS (outf, dregs (src0));
3595 OUTS (outf, " (S)");
3596 }
3597 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3598 {
3599 OUTS (outf, dregs (dst0));
3600 OUTS (outf, " = -");
3601 OUTS (outf, dregs (src0));
3602 OUTS (outf, " (NS)");
3603 }
3604 else if (aop == 1 && HL == 1 && aopcde == 11)
3605 {
3606 OUTS (outf, dregs_hi (dst0));
3607 OUTS (outf, " = (A0 += A1)");
3608 }
3609 else if (aop == 2 && aopcde == 11 && s == 0)
3610 OUTS (outf, "A0 += A1");
3611
3612 else if (aop == 2 && aopcde == 11 && s == 1)
3613 OUTS (outf, "A0 += A1 (W32)");
3614
3615 else if (aop == 3 && HL == 0 && aopcde == 14)
3616 OUTS (outf, "A1 = -A1, A0 = -A0");
3617
3618 else if (HL == 1 && aop == 3 && aopcde == 12)
3619 {
3620 OUTS (outf, dregs_hi (dst0));
3621 OUTS (outf, " = ");
3622 OUTS (outf, dregs (src0));
3623 OUTS (outf, " (RND)");
3624 }
3625 else if (aop == 0 && aopcde == 23 && HL == 0)
3626 {
3627 OUTS (outf, dregs (dst0));
3628 OUTS (outf, " = BYTEOP3P (");
3629 OUTS (outf, dregs (src0 + 1));
3630 OUTS (outf, ":");
3631 OUTS (outf, imm5d (src0));
3632 OUTS (outf, ", ");
3633 OUTS (outf, dregs (src1 + 1));
3634 OUTS (outf, ":");
3635 OUTS (outf, imm5d (src1));
3636 OUTS (outf, ") (LO");
3637 if (s == 1)
3638 OUTS (outf, ", R)");
3639 else
3640 OUTS (outf, ")");
3641 }
3642 else if (aop == 0 && HL == 0 && aopcde == 14)
3643 OUTS (outf, "A0 = -A0");
3644
3645 else if (aop == 1 && HL == 0 && aopcde == 14)
3646 OUTS (outf, "A0 = -A1");
3647
3648 else if (aop == 0 && HL == 1 && aopcde == 14)
3649 OUTS (outf, "A1 = -A0");
3650
3651 else if (aop == 1 && HL == 1 && aopcde == 14)
3652 OUTS (outf, "A1 = -A1");
3653
3654 else if (aop == 0 && aopcde == 12)
3655 {
3656 OUTS (outf, dregs_hi (dst0));
3657 OUTS (outf, " = ");
3658 OUTS (outf, dregs_lo (dst0));
3659 OUTS (outf, " = SIGN (");
3660 OUTS (outf, dregs_hi (src0));
3661 OUTS (outf, ") * ");
3662 OUTS (outf, dregs_hi (src1));
3663 OUTS (outf, " + SIGN (");
3664 OUTS (outf, dregs_lo (src0));
3665 OUTS (outf, ") * ");
3666 OUTS (outf, dregs_lo (src1));
3667 }
3668 else if (aop == 2 && aopcde == 0)
3669 {
3670 OUTS (outf, dregs (dst0));
3671 OUTS (outf, " = ");
3672 OUTS (outf, dregs (src0));
3673 OUTS (outf, " -|+ ");
3674 OUTS (outf, dregs (src1));
3675 amod0 (s, x, outf);
3676 }
3677 else if (aop == 1 && aopcde == 12)
3678 {
3679 OUTS (outf, dregs (dst1));
3680 OUTS (outf, " = A1.L + A1.H, ");
3681 OUTS (outf, dregs (dst0));
3682 OUTS (outf, " = A0.L + A0.H");
3683 }
3684 else if (aop == 2 && aopcde == 4)
3685 {
3686 OUTS (outf, dregs (dst1));
3687 OUTS (outf, " = ");
3688 OUTS (outf, dregs (src0));
3689 OUTS (outf, " + ");
3690 OUTS (outf, dregs (src1));
3691 OUTS (outf, ", ");
3692 OUTS (outf, dregs (dst0));
3693 OUTS (outf, " = ");
3694 OUTS (outf, dregs (src0));
3695 OUTS (outf, " - ");
3696 OUTS (outf, dregs (src1));
3697 amod1 (s, x, outf);
3698 }
3699 else if (HL == 0 && aopcde == 1)
3700 {
3701 OUTS (outf, dregs (dst1));
3702 OUTS (outf, " = ");
3703 OUTS (outf, dregs (src0));
3704 OUTS (outf, " +|+ ");
3705 OUTS (outf, dregs (src1));
3706 OUTS (outf, ", ");
3707 OUTS (outf, dregs (dst0));
3708 OUTS (outf, " = ");
3709 OUTS (outf, dregs (src0));
3710 OUTS (outf, " -|- ");
3711 OUTS (outf, dregs (src1));
3712 amod0amod2 (s, x, aop, outf);
3713 }
3714 else if (aop == 0 && aopcde == 11)
3715 {
3716 OUTS (outf, dregs (dst0));
3717 OUTS (outf, " = (A0 += A1)");
3718 }
3719 else if (aop == 0 && aopcde == 10)
3720 {
3721 OUTS (outf, dregs_lo (dst0));
3722 OUTS (outf, " = A0.X");
3723 }
3724 else if (aop == 1 && aopcde == 10)
3725 {
3726 OUTS (outf, dregs_lo (dst0));
3727 OUTS (outf, " = A1.X");
3728 }
3729 else if (aop == 1 && aopcde == 0)
3730 {
3731 OUTS (outf, dregs (dst0));
3732 OUTS (outf, " = ");
3733 OUTS (outf, dregs (src0));
3734 OUTS (outf, " +|- ");
3735 OUTS (outf, dregs (src1));
3736 amod0 (s, x, outf);
3737 }
3738 else if (aop == 3 && aopcde == 0)
3739 {
3740 OUTS (outf, dregs (dst0));
3741 OUTS (outf, " = ");
3742 OUTS (outf, dregs (src0));
3743 OUTS (outf, " -|- ");
3744 OUTS (outf, dregs (src1));
3745 amod0 (s, x, outf);
3746 }
3747 else if (aop == 1 && aopcde == 4)
3748 {
3749 OUTS (outf, dregs (dst0));
3750 OUTS (outf, " = ");
3751 OUTS (outf, dregs (src0));
3752 OUTS (outf, " - ");
3753 OUTS (outf, dregs (src1));
3754 amod1 (s, x, outf);
3755 }
3756 else if (aop == 0 && aopcde == 17)
3757 {
3758 OUTS (outf, dregs (dst1));
3759 OUTS (outf, " = A1 + A0, ");
3760 OUTS (outf, dregs (dst0));
3761 OUTS (outf, " = A1 - A0");
3762 amod1 (s, x, outf);
3763 }
3764 else if (aop == 1 && aopcde == 17)
3765 {
3766 OUTS (outf, dregs (dst1));
3767 OUTS (outf, " = A0 + A1, ");
3768 OUTS (outf, dregs (dst0));
3769 OUTS (outf, " = A0 - A1");
3770 amod1 (s, x, outf);
3771 }
3772 else if (aop == 0 && aopcde == 18)
3773 {
3774 OUTS (outf, "SAA (");
3775 OUTS (outf, dregs (src0 + 1));
3776 OUTS (outf, ":");
3777 OUTS (outf, imm5d (src0));
3778 OUTS (outf, ", ");
3779 OUTS (outf, dregs (src1 + 1));
3780 OUTS (outf, ":");
3781 OUTS (outf, imm5d (src1));
3782 OUTS (outf, ")");
3783 aligndir (s, outf);
3784 }
3785 else if (aop == 3 && aopcde == 18)
3786 OUTS (outf, "DISALGNEXCPT");
3787
3788 else if (aop == 0 && aopcde == 20)
3789 {
3790 OUTS (outf, dregs (dst0));
3791 OUTS (outf, " = BYTEOP1P (");
3792 OUTS (outf, dregs (src0 + 1));
3793 OUTS (outf, ":");
3794 OUTS (outf, imm5d (src0));
3795 OUTS (outf, ", ");
3796 OUTS (outf, dregs (src1 + 1));
3797 OUTS (outf, ":");
3798 OUTS (outf, imm5d (src1));
3799 OUTS (outf, ")");
3800 aligndir (s, outf);
3801 }
3802 else if (aop == 1 && aopcde == 20)
3803 {
3804 OUTS (outf, dregs (dst0));
3805 OUTS (outf, " = BYTEOP1P (");
3806 OUTS (outf, dregs (src0 + 1));
3807 OUTS (outf, ":");
3808 OUTS (outf, imm5d (src0));
3809 OUTS (outf, ", ");
3810 OUTS (outf, dregs (src1 + 1));
3811 OUTS (outf, ":");
3812 OUTS (outf, imm5d (src1));
3813 OUTS (outf, ") (T");
3814 if (s == 1)
3815 OUTS (outf, ", R)");
3816 else
3817 OUTS (outf, ")");
3818 }
3819 else if (aop == 0 && aopcde == 21)
3820 {
3821 OUTS (outf, "(");
3822 OUTS (outf, dregs (dst1));
3823 OUTS (outf, ", ");
3824 OUTS (outf, dregs (dst0));
3825 OUTS (outf, ") = BYTEOP16P (");
3826 OUTS (outf, dregs (src0 + 1));
3827 OUTS (outf, ":");
3828 OUTS (outf, imm5d (src0));
3829 OUTS (outf, ", ");
3830 OUTS (outf, dregs (src1 + 1));
3831 OUTS (outf, ":");
3832 OUTS (outf, imm5d (src1));
3833 OUTS (outf, ")");
3834 aligndir (s, outf);
3835 }
3836 else if (aop == 1 && aopcde == 21)
3837 {
3838 OUTS (outf, "(");
3839 OUTS (outf, dregs (dst1));
3840 OUTS (outf, ", ");
3841 OUTS (outf, dregs (dst0));
3842 OUTS (outf, ") = BYTEOP16M (");
3843 OUTS (outf, dregs (src0 + 1));
3844 OUTS (outf, ":");
3845 OUTS (outf, imm5d (src0));
3846 OUTS (outf, ", ");
3847 OUTS (outf, dregs (src1 + 1));
3848 OUTS (outf, ":");
3849 OUTS (outf, imm5d (src1));
3850 OUTS (outf, ")");
3851 aligndir (s, outf);
3852 }
3853 else if (aop == 2 && aopcde == 7)
3854 {
3855 OUTS (outf, dregs (dst0));
3856 OUTS (outf, " = ABS ");
3857 OUTS (outf, dregs (src0));
3858 }
3859 else if (aop == 1 && aopcde == 7)
3860 {
3861 OUTS (outf, dregs (dst0));
3862 OUTS (outf, " = MIN (");
3863 OUTS (outf, dregs (src0));
3864 OUTS (outf, ", ");
3865 OUTS (outf, dregs (src1));
3866 OUTS (outf, ")");
3867 }
3868 else if (aop == 0 && aopcde == 7)
3869 {
3870 OUTS (outf, dregs (dst0));
3871 OUTS (outf, " = MAX (");
3872 OUTS (outf, dregs (src0));
3873 OUTS (outf, ", ");
3874 OUTS (outf, dregs (src1));
3875 OUTS (outf, ")");
3876 }
3877 else if (aop == 2 && aopcde == 6)
3878 {
3879 OUTS (outf, dregs (dst0));
3880 OUTS (outf, " = ABS ");
3881 OUTS (outf, dregs (src0));
3882 OUTS (outf, " (V)");
3883 }
3884 else if (aop == 1 && aopcde == 6)
3885 {
3886 OUTS (outf, dregs (dst0));
3887 OUTS (outf, " = MIN (");
3888 OUTS (outf, dregs (src0));
3889 OUTS (outf, ", ");
3890 OUTS (outf, dregs (src1));
3891 OUTS (outf, ") (V)");
3892 }
3893 else if (aop == 0 && aopcde == 6)
3894 {
3895 OUTS (outf, dregs (dst0));
3896 OUTS (outf, " = MAX (");
3897 OUTS (outf, dregs (src0));
3898 OUTS (outf, ", ");
3899 OUTS (outf, dregs (src1));
3900 OUTS (outf, ") (V)");
3901 }
3902 else if (HL == 1 && aopcde == 1)
3903 {
3904 OUTS (outf, dregs (dst1));
3905 OUTS (outf, " = ");
3906 OUTS (outf, dregs (src0));
3907 OUTS (outf, " +|- ");
3908 OUTS (outf, dregs (src1));
3909 OUTS (outf, ", ");
3910 OUTS (outf, dregs (dst0));
3911 OUTS (outf, " = ");
3912 OUTS (outf, dregs (src0));
3913 OUTS (outf, " -|+ ");
3914 OUTS (outf, dregs (src1));
3915 amod0amod2 (s, x, aop, outf);
3916 }
3917 else if (aop == 0 && aopcde == 4)
3918 {
3919 OUTS (outf, dregs (dst0));
3920 OUTS (outf, " = ");
3921 OUTS (outf, dregs (src0));
3922 OUTS (outf, " + ");
3923 OUTS (outf, dregs (src1));
3924 amod1 (s, x, outf);
3925 }
3926 else if (aop == 0 && aopcde == 0)
3927 {
3928 OUTS (outf, dregs (dst0));
3929 OUTS (outf, " = ");
3930 OUTS (outf, dregs (src0));
3931 OUTS (outf, " +|+ ");
3932 OUTS (outf, dregs (src1));
3933 amod0 (s, x, outf);
3934 }
3935 else if (aop == 0 && aopcde == 24)
3936 {
3937 OUTS (outf, dregs (dst0));
3938 OUTS (outf, " = BYTEPACK (");
3939 OUTS (outf, dregs (src0));
3940 OUTS (outf, ", ");
3941 OUTS (outf, dregs (src1));
3942 OUTS (outf, ")");
3943 }
3944 else if (aop == 1 && aopcde == 24)
3945 {
3946 OUTS (outf, "(");
3947 OUTS (outf, dregs (dst1));
3948 OUTS (outf, ", ");
3949 OUTS (outf, dregs (dst0));
3950 OUTS (outf, ") = BYTEUNPACK ");
3951 OUTS (outf, dregs (src0 + 1));
3952 OUTS (outf, ":");
3953 OUTS (outf, imm5d (src0));
3954 aligndir (s, outf);
3955 }
3956 else if (aopcde == 13)
3957 {
3958 OUTS (outf, "(");
3959 OUTS (outf, dregs (dst1));
3960 OUTS (outf, ", ");
3961 OUTS (outf, dregs (dst0));
3962 OUTS (outf, ") = SEARCH ");
3963 OUTS (outf, dregs (src0));
3964 OUTS (outf, " (");
3965 searchmod (aop, outf);
3966 OUTS (outf, ")");
3967 }
3968 else
3969 return 0;
3970
3971 return 4;
3972 }
3973
3974 static int
3975 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3976 {
3977 /* dsp32shift
3978 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3979 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3980 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3981 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3982 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3983 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3984 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3985 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3986 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3987 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3988 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3989
3990 if (HLs == 0 && sop == 0 && sopcde == 0)
3991 {
3992 OUTS (outf, dregs_lo (dst0));
3993 OUTS (outf, " = ASHIFT ");
3994 OUTS (outf, dregs_lo (src1));
3995 OUTS (outf, " BY ");
3996 OUTS (outf, dregs_lo (src0));
3997 }
3998 else if (HLs == 1 && sop == 0 && sopcde == 0)
3999 {
4000 OUTS (outf, dregs_lo (dst0));
4001 OUTS (outf, " = ASHIFT ");
4002 OUTS (outf, dregs_hi (src1));
4003 OUTS (outf, " BY ");
4004 OUTS (outf, dregs_lo (src0));
4005 }
4006 else if (HLs == 2 && sop == 0 && sopcde == 0)
4007 {
4008 OUTS (outf, dregs_hi (dst0));
4009 OUTS (outf, " = ASHIFT ");
4010 OUTS (outf, dregs_lo (src1));
4011 OUTS (outf, " BY ");
4012 OUTS (outf, dregs_lo (src0));
4013 }
4014 else if (HLs == 3 && sop == 0 && sopcde == 0)
4015 {
4016 OUTS (outf, dregs_hi (dst0));
4017 OUTS (outf, " = ASHIFT ");
4018 OUTS (outf, dregs_hi (src1));
4019 OUTS (outf, " BY ");
4020 OUTS (outf, dregs_lo (src0));
4021 }
4022 else if (HLs == 0 && sop == 1 && sopcde == 0)
4023 {
4024 OUTS (outf, dregs_lo (dst0));
4025 OUTS (outf, " = ASHIFT ");
4026 OUTS (outf, dregs_lo (src1));
4027 OUTS (outf, " BY ");
4028 OUTS (outf, dregs_lo (src0));
4029 OUTS (outf, " (S)");
4030 }
4031 else if (HLs == 1 && sop == 1 && sopcde == 0)
4032 {
4033 OUTS (outf, dregs_lo (dst0));
4034 OUTS (outf, " = ASHIFT ");
4035 OUTS (outf, dregs_hi (src1));
4036 OUTS (outf, " BY ");
4037 OUTS (outf, dregs_lo (src0));
4038 OUTS (outf, " (S)");
4039 }
4040 else if (HLs == 2 && sop == 1 && sopcde == 0)
4041 {
4042 OUTS (outf, dregs_hi (dst0));
4043 OUTS (outf, " = ASHIFT ");
4044 OUTS (outf, dregs_lo (src1));
4045 OUTS (outf, " BY ");
4046 OUTS (outf, dregs_lo (src0));
4047 OUTS (outf, " (S)");
4048 }
4049 else if (HLs == 3 && sop == 1 && sopcde == 0)
4050 {
4051 OUTS (outf, dregs_hi (dst0));
4052 OUTS (outf, " = ASHIFT ");
4053 OUTS (outf, dregs_hi (src1));
4054 OUTS (outf, " BY ");
4055 OUTS (outf, dregs_lo (src0));
4056 OUTS (outf, " (S)");
4057 }
4058 else if (sop == 2 && sopcde == 0)
4059 {
4060 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
4061 OUTS (outf, " = LSHIFT ");
4062 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4063 OUTS (outf, " BY ");
4064 OUTS (outf, dregs_lo (src0));
4065 }
4066 else if (sop == 0 && sopcde == 3)
4067 {
4068 OUTS (outf, acc01);
4069 OUTS (outf, " = ASHIFT ");
4070 OUTS (outf, acc01);
4071 OUTS (outf, " BY ");
4072 OUTS (outf, dregs_lo (src0));
4073 }
4074 else if (sop == 1 && sopcde == 3)
4075 {
4076 OUTS (outf, acc01);
4077 OUTS (outf, " = LSHIFT ");
4078 OUTS (outf, acc01);
4079 OUTS (outf, " BY ");
4080 OUTS (outf, dregs_lo (src0));
4081 }
4082 else if (sop == 2 && sopcde == 3)
4083 {
4084 OUTS (outf, acc01);
4085 OUTS (outf, " = ROT ");
4086 OUTS (outf, acc01);
4087 OUTS (outf, " BY ");
4088 OUTS (outf, dregs_lo (src0));
4089 }
4090 else if (sop == 3 && sopcde == 3)
4091 {
4092 OUTS (outf, dregs (dst0));
4093 OUTS (outf, " = ROT ");
4094 OUTS (outf, dregs (src1));
4095 OUTS (outf, " BY ");
4096 OUTS (outf, dregs_lo (src0));
4097 }
4098 else if (sop == 1 && sopcde == 1)
4099 {
4100 OUTS (outf, dregs (dst0));
4101 OUTS (outf, " = ASHIFT ");
4102 OUTS (outf, dregs (src1));
4103 OUTS (outf, " BY ");
4104 OUTS (outf, dregs_lo (src0));
4105 OUTS (outf, " (V, S)");
4106 }
4107 else if (sop == 0 && sopcde == 1)
4108 {
4109 OUTS (outf, dregs (dst0));
4110 OUTS (outf, " = ASHIFT ");
4111 OUTS (outf, dregs (src1));
4112 OUTS (outf, " BY ");
4113 OUTS (outf, dregs_lo (src0));
4114 OUTS (outf, " (V)");
4115 }
4116 else if (sop == 0 && sopcde == 2)
4117 {
4118 OUTS (outf, dregs (dst0));
4119 OUTS (outf, " = ASHIFT ");
4120 OUTS (outf, dregs (src1));
4121 OUTS (outf, " BY ");
4122 OUTS (outf, dregs_lo (src0));
4123 }
4124 else if (sop == 1 && sopcde == 2)
4125 {
4126 OUTS (outf, dregs (dst0));
4127 OUTS (outf, " = ASHIFT ");
4128 OUTS (outf, dregs (src1));
4129 OUTS (outf, " BY ");
4130 OUTS (outf, dregs_lo (src0));
4131 OUTS (outf, " (S)");
4132 }
4133 else if (sop == 2 && sopcde == 2)
4134 {
4135 OUTS (outf, dregs (dst0));
4136 OUTS (outf, " = LSHIFT ");
4137 OUTS (outf, dregs (src1));
4138 OUTS (outf, " BY ");
4139 OUTS (outf, dregs_lo (src0));
4140 }
4141 else if (sop == 3 && sopcde == 2)
4142 {
4143 OUTS (outf, dregs (dst0));
4144 OUTS (outf, " = ROT ");
4145 OUTS (outf, dregs (src1));
4146 OUTS (outf, " BY ");
4147 OUTS (outf, dregs_lo (src0));
4148 }
4149 else if (sop == 2 && sopcde == 1)
4150 {
4151 OUTS (outf, dregs (dst0));
4152 OUTS (outf, " = LSHIFT ");
4153 OUTS (outf, dregs (src1));
4154 OUTS (outf, " BY ");
4155 OUTS (outf, dregs_lo (src0));
4156 OUTS (outf, " (V)");
4157 }
4158 else if (sop == 0 && sopcde == 4)
4159 {
4160 OUTS (outf, dregs (dst0));
4161 OUTS (outf, " = PACK (");
4162 OUTS (outf, dregs_lo (src1));
4163 OUTS (outf, ", ");
4164 OUTS (outf, dregs_lo (src0));
4165 OUTS (outf, ")");
4166 }
4167 else if (sop == 1 && sopcde == 4)
4168 {
4169 OUTS (outf, dregs (dst0));
4170 OUTS (outf, " = PACK (");
4171 OUTS (outf, dregs_lo (src1));
4172 OUTS (outf, ", ");
4173 OUTS (outf, dregs_hi (src0));
4174 OUTS (outf, ")");
4175 }
4176 else if (sop == 2 && sopcde == 4)
4177 {
4178 OUTS (outf, dregs (dst0));
4179 OUTS (outf, " = PACK (");
4180 OUTS (outf, dregs_hi (src1));
4181 OUTS (outf, ", ");
4182 OUTS (outf, dregs_lo (src0));
4183 OUTS (outf, ")");
4184 }
4185 else if (sop == 3 && sopcde == 4)
4186 {
4187 OUTS (outf, dregs (dst0));
4188 OUTS (outf, " = PACK (");
4189 OUTS (outf, dregs_hi (src1));
4190 OUTS (outf, ", ");
4191 OUTS (outf, dregs_hi (src0));
4192 OUTS (outf, ")");
4193 }
4194 else if (sop == 0 && sopcde == 5)
4195 {
4196 OUTS (outf, dregs_lo (dst0));
4197 OUTS (outf, " = SIGNBITS ");
4198 OUTS (outf, dregs (src1));
4199 }
4200 else if (sop == 1 && sopcde == 5)
4201 {
4202 OUTS (outf, dregs_lo (dst0));
4203 OUTS (outf, " = SIGNBITS ");
4204 OUTS (outf, dregs_lo (src1));
4205 }
4206 else if (sop == 2 && sopcde == 5)
4207 {
4208 OUTS (outf, dregs_lo (dst0));
4209 OUTS (outf, " = SIGNBITS ");
4210 OUTS (outf, dregs_hi (src1));
4211 }
4212 else if (sop == 0 && sopcde == 6)
4213 {
4214 OUTS (outf, dregs_lo (dst0));
4215 OUTS (outf, " = SIGNBITS A0");
4216 }
4217 else if (sop == 1 && sopcde == 6)
4218 {
4219 OUTS (outf, dregs_lo (dst0));
4220 OUTS (outf, " = SIGNBITS A1");
4221 }
4222 else if (sop == 3 && sopcde == 6)
4223 {
4224 OUTS (outf, dregs_lo (dst0));
4225 OUTS (outf, " = ONES ");
4226 OUTS (outf, dregs (src1));
4227 }
4228 else if (sop == 0 && sopcde == 7)
4229 {
4230 OUTS (outf, dregs_lo (dst0));
4231 OUTS (outf, " = EXPADJ (");
4232 OUTS (outf, dregs (src1));
4233 OUTS (outf, ", ");
4234 OUTS (outf, dregs_lo (src0));
4235 OUTS (outf, ")");
4236 }
4237 else if (sop == 1 && sopcde == 7)
4238 {
4239 OUTS (outf, dregs_lo (dst0));
4240 OUTS (outf, " = EXPADJ (");
4241 OUTS (outf, dregs (src1));
4242 OUTS (outf, ", ");
4243 OUTS (outf, dregs_lo (src0));
4244 OUTS (outf, ") (V)");
4245 }
4246 else if (sop == 2 && sopcde == 7)
4247 {
4248 OUTS (outf, dregs_lo (dst0));
4249 OUTS (outf, " = EXPADJ (");
4250 OUTS (outf, dregs_lo (src1));
4251 OUTS (outf, ", ");
4252 OUTS (outf, dregs_lo (src0));
4253 OUTS (outf, ")");
4254 }
4255 else if (sop == 3 && sopcde == 7)
4256 {
4257 OUTS (outf, dregs_lo (dst0));
4258 OUTS (outf, " = EXPADJ (");
4259 OUTS (outf, dregs_hi (src1));
4260 OUTS (outf, ", ");
4261 OUTS (outf, dregs_lo (src0));
4262 OUTS (outf, ")");
4263 }
4264 else if (sop == 0 && sopcde == 8)
4265 {
4266 OUTS (outf, "BITMUX (");
4267 OUTS (outf, dregs (src0));
4268 OUTS (outf, ", ");
4269 OUTS (outf, dregs (src1));
4270 OUTS (outf, ", A0) (ASR)");
4271 }
4272 else if (sop == 1 && sopcde == 8)
4273 {
4274 OUTS (outf, "BITMUX (");
4275 OUTS (outf, dregs (src0));
4276 OUTS (outf, ", ");
4277 OUTS (outf, dregs (src1));
4278 OUTS (outf, ", A0) (ASL)");
4279 }
4280 else if (sop == 0 && sopcde == 9)
4281 {
4282 OUTS (outf, dregs_lo (dst0));
4283 OUTS (outf, " = VIT_MAX (");
4284 OUTS (outf, dregs (src1));
4285 OUTS (outf, ") (ASL)");
4286 }
4287 else if (sop == 1 && sopcde == 9)
4288 {
4289 OUTS (outf, dregs_lo (dst0));
4290 OUTS (outf, " = VIT_MAX (");
4291 OUTS (outf, dregs (src1));
4292 OUTS (outf, ") (ASR)");
4293 }
4294 else if (sop == 2 && sopcde == 9)
4295 {
4296 OUTS (outf, dregs (dst0));
4297 OUTS (outf, " = VIT_MAX (");
4298 OUTS (outf, dregs (src1));
4299 OUTS (outf, ", ");
4300 OUTS (outf, dregs (src0));
4301 OUTS (outf, ") (ASL)");
4302 }
4303 else if (sop == 3 && sopcde == 9)
4304 {
4305 OUTS (outf, dregs (dst0));
4306 OUTS (outf, " = VIT_MAX (");
4307 OUTS (outf, dregs (src1));
4308 OUTS (outf, ", ");
4309 OUTS (outf, dregs (src0));
4310 OUTS (outf, ") (ASR)");
4311 }
4312 else if (sop == 0 && sopcde == 10)
4313 {
4314 OUTS (outf, dregs (dst0));
4315 OUTS (outf, " = EXTRACT (");
4316 OUTS (outf, dregs (src1));
4317 OUTS (outf, ", ");
4318 OUTS (outf, dregs_lo (src0));
4319 OUTS (outf, ") (Z)");
4320 }
4321 else if (sop == 1 && sopcde == 10)
4322 {
4323 OUTS (outf, dregs (dst0));
4324 OUTS (outf, " = EXTRACT (");
4325 OUTS (outf, dregs (src1));
4326 OUTS (outf, ", ");
4327 OUTS (outf, dregs_lo (src0));
4328 OUTS (outf, ") (X)");
4329 }
4330 else if (sop == 2 && sopcde == 10)
4331 {
4332 OUTS (outf, dregs (dst0));
4333 OUTS (outf, " = DEPOSIT (");
4334 OUTS (outf, dregs (src1));
4335 OUTS (outf, ", ");
4336 OUTS (outf, dregs (src0));
4337 OUTS (outf, ")");
4338 }
4339 else if (sop == 3 && sopcde == 10)
4340 {
4341 OUTS (outf, dregs (dst0));
4342 OUTS (outf, " = DEPOSIT (");
4343 OUTS (outf, dregs (src1));
4344 OUTS (outf, ", ");
4345 OUTS (outf, dregs (src0));
4346 OUTS (outf, ") (X)");
4347 }
4348 else if (sop == 0 && sopcde == 11)
4349 {
4350 OUTS (outf, dregs_lo (dst0));
4351 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4352 OUTS (outf, dregs (src0));
4353 OUTS (outf, ")");
4354 }
4355 else if (sop == 1 && sopcde == 11)
4356 {
4357 OUTS (outf, dregs_lo (dst0));
4358 OUTS (outf, " = CC = BXOR (A0, ");
4359 OUTS (outf, dregs (src0));
4360 OUTS (outf, ")");
4361 }
4362 else if (sop == 0 && sopcde == 12)
4363 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4364
4365 else if (sop == 1 && sopcde == 12)
4366 {
4367 OUTS (outf, dregs_lo (dst0));
4368 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4369 }
4370 else if (sop == 0 && sopcde == 13)
4371 {
4372 OUTS (outf, dregs (dst0));
4373 OUTS (outf, " = ALIGN8 (");
4374 OUTS (outf, dregs (src1));
4375 OUTS (outf, ", ");
4376 OUTS (outf, dregs (src0));
4377 OUTS (outf, ")");
4378 }
4379 else if (sop == 1 && sopcde == 13)
4380 {
4381 OUTS (outf, dregs (dst0));
4382 OUTS (outf, " = ALIGN16 (");
4383 OUTS (outf, dregs (src1));
4384 OUTS (outf, ", ");
4385 OUTS (outf, dregs (src0));
4386 OUTS (outf, ")");
4387 }
4388 else if (sop == 2 && sopcde == 13)
4389 {
4390 OUTS (outf, dregs (dst0));
4391 OUTS (outf, " = ALIGN24 (");
4392 OUTS (outf, dregs (src1));
4393 OUTS (outf, ", ");
4394 OUTS (outf, dregs (src0));
4395 OUTS (outf, ")");
4396 }
4397 else
4398 return 0;
4399
4400 return 4;
4401 }
4402
4403 static int
4404 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4405 {
4406 /* dsp32shiftimm
4407 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4408 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4409 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4410 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4411 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4412 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4413 int bit8 = ((iw1 >> 8) & 0x1);
4414 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4415 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4416 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4417 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4418 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4419
4420
4421 if (sop == 0 && sopcde == 0)
4422 {
4423 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4424 OUTS (outf, " = ");
4425 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4426 OUTS (outf, " >>> ");
4427 OUTS (outf, uimm4 (newimmag));
4428 }
4429 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4430 {
4431 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4432 OUTS (outf, " = ");
4433 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4434 OUTS (outf, " << ");
4435 OUTS (outf, uimm4 (immag));
4436 OUTS (outf, " (S)");
4437 }
4438 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4439 {
4440 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4441 OUTS (outf, " = ");
4442 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4443 OUTS (outf, " >>> ");
4444 OUTS (outf, uimm4 (newimmag));
4445 OUTS (outf, " (S)");
4446 }
4447 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4448 {
4449 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4450 OUTS (outf, " = ");
4451 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4452 OUTS (outf, " << ");
4453 OUTS (outf, uimm4 (immag));
4454 }
4455 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4456 {
4457 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4458 OUTS (outf, " = ");
4459 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4460 OUTS (outf, " >> ");
4461 OUTS (outf, uimm4 (newimmag));
4462 }
4463 else if (sop == 2 && sopcde == 3 && HLs == 1)
4464 {
4465 OUTS (outf, "A1 = ROT A1 BY ");
4466 OUTS (outf, imm6 (immag));
4467 }
4468 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4469 {
4470 OUTS (outf, "A0 = A0 << ");
4471 OUTS (outf, uimm5 (immag));
4472 }
4473 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4474 {
4475 OUTS (outf, "A0 = A0 >>> ");
4476 OUTS (outf, uimm5 (newimmag));
4477 }
4478 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4479 {
4480 OUTS (outf, "A1 = A1 << ");
4481 OUTS (outf, uimm5 (immag));
4482 }
4483 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4484 {
4485 OUTS (outf, "A1 = A1 >>> ");
4486 OUTS (outf, uimm5 (newimmag));
4487 }
4488 else if (sop == 1 && sopcde == 3 && HLs == 0)
4489 {
4490 OUTS (outf, "A0 = A0 >> ");
4491 OUTS (outf, uimm5 (newimmag));
4492 }
4493 else if (sop == 1 && sopcde == 3 && HLs == 1)
4494 {
4495 OUTS (outf, "A1 = A1 >> ");
4496 OUTS (outf, uimm5 (newimmag));
4497 }
4498 else if (sop == 2 && sopcde == 3 && HLs == 0)
4499 {
4500 OUTS (outf, "A0 = ROT A0 BY ");
4501 OUTS (outf, imm6 (immag));
4502 }
4503 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4504 {
4505 OUTS (outf, dregs (dst0));
4506 OUTS (outf, " = ");
4507 OUTS (outf, dregs (src1));
4508 OUTS (outf, " << ");
4509 OUTS (outf, uimm5 (immag));
4510 OUTS (outf, " (V, S)");
4511 }
4512 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4513 {
4514 OUTS (outf, dregs (dst0));
4515 OUTS (outf, " = ");
4516 OUTS (outf, dregs (src1));
4517 OUTS (outf, " >>> ");
4518 OUTS (outf, imm5 (-immag));
4519 OUTS (outf, " (V, S)");
4520 }
4521 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4522 {
4523 OUTS (outf, dregs (dst0));
4524 OUTS (outf, " = ");
4525 OUTS (outf, dregs (src1));
4526 OUTS (outf, " >> ");
4527 OUTS (outf, uimm5 (newimmag));
4528 OUTS (outf, " (V)");
4529 }
4530 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4531 {
4532 OUTS (outf, dregs (dst0));
4533 OUTS (outf, " = ");
4534 OUTS (outf, dregs (src1));
4535 OUTS (outf, " << ");
4536 OUTS (outf, imm5 (immag));
4537 OUTS (outf, " (V)");
4538 }
4539 else if (sop == 0 && sopcde == 1)
4540 {
4541 OUTS (outf, dregs (dst0));
4542 OUTS (outf, " = ");
4543 OUTS (outf, dregs (src1));
4544 OUTS (outf, " >>> ");
4545 OUTS (outf, uimm5 (newimmag));
4546 OUTS (outf, " (V)");
4547 }
4548 else if (sop == 1 && sopcde == 2)
4549 {
4550 OUTS (outf, dregs (dst0));
4551 OUTS (outf, " = ");
4552 OUTS (outf, dregs (src1));
4553 OUTS (outf, " << ");
4554 OUTS (outf, uimm5 (immag));
4555 OUTS (outf, " (S)");
4556 }
4557 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4558 {
4559 OUTS (outf, dregs (dst0));
4560 OUTS (outf, " = ");
4561 OUTS (outf, dregs (src1));
4562 OUTS (outf, " >> ");
4563 OUTS (outf, uimm5 (newimmag));
4564 }
4565 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4566 {
4567 OUTS (outf, dregs (dst0));
4568 OUTS (outf, " = ");
4569 OUTS (outf, dregs (src1));
4570 OUTS (outf, " << ");
4571 OUTS (outf, uimm5 (immag));
4572 }
4573 else if (sop == 3 && sopcde == 2)
4574 {
4575 OUTS (outf, dregs (dst0));
4576 OUTS (outf, " = ROT ");
4577 OUTS (outf, dregs (src1));
4578 OUTS (outf, " BY ");
4579 OUTS (outf, imm6 (immag));
4580 }
4581 else if (sop == 0 && sopcde == 2)
4582 {
4583 OUTS (outf, dregs (dst0));
4584 OUTS (outf, " = ");
4585 OUTS (outf, dregs (src1));
4586 OUTS (outf, " >>> ");
4587 OUTS (outf, uimm5 (newimmag));
4588 }
4589 else
4590 return 0;
4591
4592 return 4;
4593 }
4594
4595 static int
4596 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4597 {
4598 /* pseudoDEBUG
4599 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4600 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4601 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4602 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4603 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4604 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4605
4606 if (parallel)
4607 return 0;
4608
4609 if (reg == 0 && fn == 3)
4610 OUTS (outf, "DBG A0");
4611
4612 else if (reg == 1 && fn == 3)
4613 OUTS (outf, "DBG A1");
4614
4615 else if (reg == 3 && fn == 3)
4616 OUTS (outf, "ABORT");
4617
4618 else if (reg == 4 && fn == 3)
4619 OUTS (outf, "HLT");
4620
4621 else if (reg == 5 && fn == 3)
4622 OUTS (outf, "DBGHALT");
4623
4624 else if (reg == 6 && fn == 3)
4625 {
4626 OUTS (outf, "DBGCMPLX (");
4627 OUTS (outf, dregs (grp));
4628 OUTS (outf, ")");
4629 }
4630 else if (reg == 7 && fn == 3)
4631 OUTS (outf, "DBG");
4632
4633 else if (grp == 0 && fn == 2)
4634 {
4635 OUTS (outf, "OUTC ");
4636 OUTS (outf, dregs (reg));
4637 }
4638 else if (fn == 0)
4639 {
4640 OUTS (outf, "DBG ");
4641 OUTS (outf, allregs (reg, grp));
4642 }
4643 else if (fn == 1)
4644 {
4645 OUTS (outf, "PRNT");
4646 OUTS (outf, allregs (reg, grp));
4647 }
4648 else
4649 return 0;
4650
4651 return 2;
4652 }
4653
4654 static int
4655 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4656 {
4657 /* psedoOChar
4658 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4659 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4660 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4661 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4662
4663 if (parallel)
4664 return 0;
4665
4666 OUTS (outf, "OUTC ");
4667 OUTS (outf, uimm8 (ch));
4668
4669 return 2;
4670 }
4671
4672 static int
4673 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4674 {
4675 /* pseudodbg_assert
4676 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4677 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4678 |.expected......................................................|
4679 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4680 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4681 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4682 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4683 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4684
4685 if (parallel)
4686 return 0;
4687
4688 if (dbgop == 0)
4689 {
4690 OUTS (outf, "DBGA (");
4691 OUTS (outf, regs_lo (regtest, grp));
4692 OUTS (outf, ", ");
4693 OUTS (outf, uimm16 (expected));
4694 OUTS (outf, ")");
4695 }
4696 else if (dbgop == 1)
4697 {
4698 OUTS (outf, "DBGA (");
4699 OUTS (outf, regs_hi (regtest, grp));
4700 OUTS (outf, ", ");
4701 OUTS (outf, uimm16 (expected));
4702 OUTS (outf, ")");
4703 }
4704 else if (dbgop == 2)
4705 {
4706 OUTS (outf, "DBGAL (");
4707 OUTS (outf, allregs (regtest, grp));
4708 OUTS (outf, ", ");
4709 OUTS (outf, uimm16 (expected));
4710 OUTS (outf, ")");
4711 }
4712 else if (dbgop == 3)
4713 {
4714 OUTS (outf, "DBGAH (");
4715 OUTS (outf, allregs (regtest, grp));
4716 OUTS (outf, ", ");
4717 OUTS (outf, uimm16 (expected));
4718 OUTS (outf, ")");
4719 }
4720 else
4721 return 0;
4722 return 4;
4723 }
4724
4725 static int
4726 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4727 {
4728 bfd_byte buf[4];
4729 TIword iw0;
4730 TIword iw1;
4731 int status;
4732 int rv = 0;
4733
4734 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4735 /* FIXME */
4736 (void) status;
4737 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4738 /* FIXME */
4739 (void) status;
4740
4741 iw0 = bfd_getl16 (buf);
4742 iw1 = bfd_getl16 (buf + 2);
4743
4744 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4745 {
4746 if (parallel)
4747 {
4748 OUTS (outf, "ILLEGAL");
4749 return 0;
4750 }
4751 OUTS (outf, "MNOP");
4752 return 4;
4753 }
4754 else if ((iw0 & 0xff00) == 0x0000)
4755 rv = decode_ProgCtrl_0 (iw0, outf);
4756 else if ((iw0 & 0xffc0) == 0x0240)
4757 rv = decode_CaCTRL_0 (iw0, outf);
4758 else if ((iw0 & 0xff80) == 0x0100)
4759 rv = decode_PushPopReg_0 (iw0, outf);
4760 else if ((iw0 & 0xfe00) == 0x0400)
4761 rv = decode_PushPopMultiple_0 (iw0, outf);
4762 else if ((iw0 & 0xfe00) == 0x0600)
4763 rv = decode_ccMV_0 (iw0, outf);
4764 else if ((iw0 & 0xf800) == 0x0800)
4765 rv = decode_CCflag_0 (iw0, outf);
4766 else if ((iw0 & 0xffe0) == 0x0200)
4767 rv = decode_CC2dreg_0 (iw0, outf);
4768 else if ((iw0 & 0xff00) == 0x0300)
4769 rv = decode_CC2stat_0 (iw0, outf);
4770 else if ((iw0 & 0xf000) == 0x1000)
4771 rv = decode_BRCC_0 (iw0, pc, outf);
4772 else if ((iw0 & 0xf000) == 0x2000)
4773 rv = decode_UJUMP_0 (iw0, pc, outf);
4774 else if ((iw0 & 0xf000) == 0x3000)
4775 rv = decode_REGMV_0 (iw0, outf);
4776 else if ((iw0 & 0xfc00) == 0x4000)
4777 rv = decode_ALU2op_0 (iw0, outf);
4778 else if ((iw0 & 0xfe00) == 0x4400)
4779 rv = decode_PTR2op_0 (iw0, outf);
4780 else if ((iw0 & 0xf800) == 0x4800)
4781 rv = decode_LOGI2op_0 (iw0, outf);
4782 else if ((iw0 & 0xf000) == 0x5000)
4783 rv = decode_COMP3op_0 (iw0, outf);
4784 else if ((iw0 & 0xf800) == 0x6000)
4785 rv = decode_COMPI2opD_0 (iw0, outf);
4786 else if ((iw0 & 0xf800) == 0x6800)
4787 rv = decode_COMPI2opP_0 (iw0, outf);
4788 else if ((iw0 & 0xf000) == 0x8000)
4789 rv = decode_LDSTpmod_0 (iw0, outf);
4790 else if ((iw0 & 0xff60) == 0x9e60)
4791 rv = decode_dagMODim_0 (iw0, outf);
4792 else if ((iw0 & 0xfff0) == 0x9f60)
4793 rv = decode_dagMODik_0 (iw0, outf);
4794 else if ((iw0 & 0xfc00) == 0x9c00)
4795 rv = decode_dspLDST_0 (iw0, outf);
4796 else if ((iw0 & 0xf000) == 0x9000)
4797 rv = decode_LDST_0 (iw0, outf);
4798 else if ((iw0 & 0xfc00) == 0xb800)
4799 rv = decode_LDSTiiFP_0 (iw0, outf);
4800 else if ((iw0 & 0xe000) == 0xA000)
4801 rv = decode_LDSTii_0 (iw0, outf);
4802 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4803 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4804 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4805 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4806 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4807 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4808 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4809 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4810 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4811 rv = decode_linkage_0 (iw0, iw1, outf);
4812 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4813 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4814 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4815 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4816 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4817 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4818 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4819 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4820 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4821 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4822 else if ((iw0 & 0xff00) == 0xf800)
4823 rv = decode_pseudoDEBUG_0 (iw0, outf);
4824 else if ((iw0 & 0xFF00) == 0xF900)
4825 rv = decode_pseudoOChar_0 (iw0, outf);
4826 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4827 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4828
4829 if (rv == 0)
4830 OUTS (outf, "ILLEGAL");
4831
4832 return rv;
4833 }
4834
4835
4836 int
4837 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4838 {
4839 bfd_byte buf[2];
4840 unsigned short iw0;
4841 int status;
4842 int count = 0;
4843
4844 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4845 /* FIXME */
4846 (void) status;
4847 iw0 = bfd_getl16 (buf);
4848
4849 count += _print_insn_bfin (pc, outf);
4850
4851 /* Proper display of multiple issue instructions. */
4852
4853 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4854 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4855 {
4856 int legal = 1;
4857 int len;
4858
4859 parallel = 1;
4860 outf->fprintf_func (outf->stream, " || ");
4861 len = _print_insn_bfin (pc + 4, outf);
4862 outf->fprintf_func (outf->stream, " || ");
4863 if (len != 2)
4864 legal = 0;
4865 len = _print_insn_bfin (pc + 6, outf);
4866 if (len != 2)
4867 legal = 0;
4868
4869 if (legal)
4870 count = 8;
4871 else
4872 {
4873 outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4874 comment = 1;
4875 count = 0;
4876 }
4877 parallel = 0;
4878 }
4879
4880 if (!comment)
4881 outf->fprintf_func (outf->stream, ";");
4882
4883 if (count == 0)
4884 return 2;
4885
4886 comment = 0;
4887
4888 return count;
4889 }
git-cvsimport of binutils cvsroot