opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_EX_VexImmW (int, int);
  95 static void OP_XMM_Vex (int, int);
  96 static void OP_XMM_VexW (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VEXI4_Fixup (int, int);
 100 static void VZERO_Fixup (int, int);
 101 static void VCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void CMPXCHG8B_Fixup (int, int);
 112 static void XMM_Fixup (int, int);
 113 static void CRC32_Fixup (int, int);
 114 static void FXSAVE_Fixup (int, int);
 115 static void OP_LWPCB_E (int, int);
 116 static void OP_LWP_E (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define Iq { OP_I, q_mode }
 257 #define Iv64 { OP_I64, v_mode }
 258 #define Iw { OP_I, w_mode }
 259 #define I1 { OP_I, const_1_mode }
 260 #define Jb { OP_J, b_mode }
 261 #define Jv { OP_J, v_mode }
 262 #define Cm { OP_C, m_mode }
 263 #define Dm { OP_D, m_mode }
 264 #define Td { OP_T, d_mode }
 265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 266
 267 #define RMeAX { OP_REG, eAX_reg }
 268 #define RMeBX { OP_REG, eBX_reg }
 269 #define RMeCX { OP_REG, eCX_reg }
 270 #define RMeDX { OP_REG, eDX_reg }
 271 #define RMeSP { OP_REG, eSP_reg }
 272 #define RMeBP { OP_REG, eBP_reg }
 273 #define RMeSI { OP_REG, eSI_reg }
 274 #define RMeDI { OP_REG, eDI_reg }
 275 #define RMrAX { OP_REG, rAX_reg }
 276 #define RMrBX { OP_REG, rBX_reg }
 277 #define RMrCX { OP_REG, rCX_reg }
 278 #define RMrDX { OP_REG, rDX_reg }
 279 #define RMrSP { OP_REG, rSP_reg }
 280 #define RMrBP { OP_REG, rBP_reg }
 281 #define RMrSI { OP_REG, rSI_reg }
 282 #define RMrDI { OP_REG, rDI_reg }
 283 #define RMAL { OP_REG, al_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMCL { OP_REG, cl_reg }
 286 #define RMDL { OP_REG, dl_reg }
 287 #define RMBL { OP_REG, bl_reg }
 288 #define RMAH { OP_REG, ah_reg }
 289 #define RMCH { OP_REG, ch_reg }
 290 #define RMDH { OP_REG, dh_reg }
 291 #define RMBH { OP_REG, bh_reg }
 292 #define RMAX { OP_REG, ax_reg }
 293 #define RMDX { OP_REG, dx_reg }
 294
 295 #define eAX { OP_IMREG, eAX_reg }
 296 #define eBX { OP_IMREG, eBX_reg }
 297 #define eCX { OP_IMREG, eCX_reg }
 298 #define eDX { OP_IMREG, eDX_reg }
 299 #define eSP { OP_IMREG, eSP_reg }
 300 #define eBP { OP_IMREG, eBP_reg }
 301 #define eSI { OP_IMREG, eSI_reg }
 302 #define eDI { OP_IMREG, eDI_reg }
 303 #define AL { OP_IMREG, al_reg }
 304 #define CL { OP_IMREG, cl_reg }
 305 #define DL { OP_IMREG, dl_reg }
 306 #define BL { OP_IMREG, bl_reg }
 307 #define AH { OP_IMREG, ah_reg }
 308 #define CH { OP_IMREG, ch_reg }
 309 #define DH { OP_IMREG, dh_reg }
 310 #define BH { OP_IMREG, bh_reg }
 311 #define AX { OP_IMREG, ax_reg }
 312 #define DX { OP_IMREG, dx_reg }
 313 #define zAX { OP_IMREG, z_mode_ax_reg }
 314 #define indirDX { OP_IMREG, indir_dx_reg }
 315
 316 #define Sw { OP_SEG, w_mode }
 317 #define Sv { OP_SEG, v_mode }
 318 #define Ap { OP_DIR, 0 }
 319 #define Ob { OP_OFF64, b_mode }
 320 #define Ov { OP_OFF64, v_mode }
 321 #define Xb { OP_DSreg, eSI_reg }
 322 #define Xv { OP_DSreg, eSI_reg }
 323 #define Xz { OP_DSreg, eSI_reg }
 324 #define Yb { OP_ESreg, eDI_reg }
 325 #define Yv { OP_ESreg, eDI_reg }
 326 #define DSBX { OP_DSreg, eBX_reg }
 327
 328 #define es { OP_REG, es_reg }
 329 #define ss { OP_REG, ss_reg }
 330 #define cs { OP_REG, cs_reg }
 331 #define ds { OP_REG, ds_reg }
 332 #define fs { OP_REG, fs_reg }
 333 #define gs { OP_REG, gs_reg }
 334
 335 #define MX { OP_MMX, 0 }
 336 #define XM { OP_XMM, 0 }
 337 #define XMScalar { OP_XMM, scalar_mode }
 338 #define XMM { OP_XMM, xmm_mode }
 339 #define EM { OP_EM, v_mode }
 340 #define EMS { OP_EM, v_swap_mode }
 341 #define EMd { OP_EM, d_mode }
 342 #define EMx { OP_EM, x_mode }
 343 #define EXw { OP_EX, w_mode }
 344 #define EXd { OP_EX, d_mode }
 345 #define EXdScalar { OP_EX, d_scalar_mode }
 346 #define EXdS { OP_EX, d_swap_mode }
 347 #define EXq { OP_EX, q_mode }
 348 #define EXqScalar { OP_EX, q_scalar_mode }
 349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 350 #define EXqS { OP_EX, q_swap_mode }
 351 #define EXx { OP_EX, x_mode }
 352 #define EXxS { OP_EX, x_swap_mode }
 353 #define EXxmm { OP_EX, xmm_mode }
 354 #define EXxmmq { OP_EX, xmmq_mode }
 355 #define EXymmq { OP_EX, ymmq_mode }
 356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 358 #define MS { OP_MS, v_mode }
 359 #define XS { OP_XS, v_mode }
 360 #define EMCq { OP_EMC, q_mode }
 361 #define MXC { OP_MXC, 0 }
 362 #define OPSUF { OP_3DNowSuffix, 0 }
 363 #define CMP { CMP_Fixup, 0 }
 364 #define XMM0 { XMM_Fixup, 0 }
 365 #define FXSAVE { FXSAVE_Fixup, 0 }
 366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 368
 369 #define Vex { OP_VEX, vex_mode }
 370 #define VexScalar { OP_VEX, vex_scalar_mode }
 371 #define Vex128 { OP_VEX, vex128_mode }
 372 #define Vex256 { OP_VEX, vex256_mode }
 373 #define VexI4 { VEXI4_Fixup, 0}
 374 #define EXdVex { OP_EX_Vex, d_mode }
 375 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 376 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 377 #define EXqVex { OP_EX_Vex, q_mode }
 378 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 379 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 380 #define EXVexW { OP_EX_VexW, x_mode }
 381 #define EXdVexW { OP_EX_VexW, d_mode }
 382 #define EXqVexW { OP_EX_VexW, q_mode }
 383 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 384 #define XMVex { OP_XMM_Vex, 0 }
 385 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 386 #define XMVexW { OP_XMM_VexW, 0 }
 387 #define XMVexI4 { OP_REG_VexI4, x_mode }
 388 #define PCLMUL { PCLMUL_Fixup, 0 }
 389 #define VZERO { VZERO_Fixup, 0 }
 390 #define VCMP { VCMP_Fixup, 0 }
 391
 392 /* Used handle "rep" prefix for string instructions.  */
 393 #define Xbr { REP_Fixup, eSI_reg }
 394 #define Xvr { REP_Fixup, eSI_reg }
 395 #define Ybr { REP_Fixup, eDI_reg }
 396 #define Yvr { REP_Fixup, eDI_reg }
 397 #define Yzr { REP_Fixup, eDI_reg }
 398 #define indirDXr { REP_Fixup, indir_dx_reg }
 399 #define ALr { REP_Fixup, al_reg }
 400 #define eAXr { REP_Fixup, eAX_reg }
 401
 402 #define cond_jump_flag { NULL, cond_jump_mode }
 403 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 404
 405 /* bits in sizeflag */
 406 #define SUFFIX_ALWAYS 4
 407 #define AFLAG 2
 408 #define DFLAG 1
 409
 410 enum
 411 {
 412   /* byte operand */
 413   b_mode = 1,
 414   /* byte operand with operand swapped */
 415   b_swap_mode,
 416   /* operand size depends on prefixes */
 417   v_mode,
 418   /* operand size depends on prefixes with operand swapped */
 419   v_swap_mode,
 420   /* word operand */
 421   w_mode,
 422   /* double word operand  */
 423   d_mode,
 424   /* double word operand with operand swapped */
 425   d_swap_mode,
 426   /* quad word operand */
 427   q_mode,
 428   /* quad word operand with operand swapped */
 429   q_swap_mode,
 430   /* ten-byte operand */
 431   t_mode,
 432   /* 16-byte XMM or 32-byte YMM operand */
 433   x_mode,
 434   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 435   x_swap_mode,
 436   /* 16-byte XMM operand */
 437   xmm_mode,
 438   /* 16-byte XMM or quad word operand */
 439   xmmq_mode,
 440   /* 32-byte YMM or quad word operand */
 441   ymmq_mode,
 442   /* d_mode in 32bit, q_mode in 64bit mode.  */
 443   m_mode,
 444   /* pair of v_mode operands */
 445   a_mode,
 446   cond_jump_mode,
 447   loop_jcxz_mode,
 448   /* operand size depends on REX prefixes.  */
 449   dq_mode,
 450   /* registers like dq_mode, memory like w_mode.  */
 451   dqw_mode,
 452   /* 4- or 6-byte pointer operand */
 453   f_mode,
 454   const_1_mode,
 455   /* v_mode for stack-related opcodes.  */
 456   stack_v_mode,
 457   /* non-quad operand size depends on prefixes */
 458   z_mode,
 459   /* 16-byte operand */
 460   o_mode,
 461   /* registers like dq_mode, memory like b_mode.  */
 462   dqb_mode,
 463   /* registers like dq_mode, memory like d_mode.  */
 464   dqd_mode,
 465   /* normal vex mode */
 466   vex_mode,
 467   /* 128bit vex mode */
 468   vex128_mode,
 469   /* 256bit vex mode */
 470   vex256_mode,
 471   /* operand size depends on the VEX.W bit.  */
 472   vex_w_dq_mode,
 473
 474   /* scalar, ignore vector length.  */
 475   scalar_mode,
 476   /* like d_mode, ignore vector length.  */
 477   d_scalar_mode,
 478   /* like d_swap_mode, ignore vector length.  */
 479   d_scalar_swap_mode,
 480   /* like q_mode, ignore vector length.  */
 481   q_scalar_mode,
 482   /* like q_swap_mode, ignore vector length.  */
 483   q_scalar_swap_mode,
 484   /* like vex_mode, ignore vector length.  */
 485   vex_scalar_mode,
 486   /* like vex_w_dq_mode, ignore vector length.  */
 487   vex_scalar_w_dq_mode,
 488
 489   es_reg,
 490   cs_reg,
 491   ss_reg,
 492   ds_reg,
 493   fs_reg,
 494   gs_reg,
 495
 496   eAX_reg,
 497   eCX_reg,
 498   eDX_reg,
 499   eBX_reg,
 500   eSP_reg,
 501   eBP_reg,
 502   eSI_reg,
 503   eDI_reg,
 504
 505   al_reg,
 506   cl_reg,
 507   dl_reg,
 508   bl_reg,
 509   ah_reg,
 510   ch_reg,
 511   dh_reg,
 512   bh_reg,
 513
 514   ax_reg,
 515   cx_reg,
 516   dx_reg,
 517   bx_reg,
 518   sp_reg,
 519   bp_reg,
 520   si_reg,
 521   di_reg,
 522
 523   rAX_reg,
 524   rCX_reg,
 525   rDX_reg,
 526   rBX_reg,
 527   rSP_reg,
 528   rBP_reg,
 529   rSI_reg,
 530   rDI_reg,
 531
 532   z_mode_ax_reg,
 533   indir_dx_reg
 534 };
 535
 536 enum
 537 {
 538   FLOATCODE = 1,
 539   USE_REG_TABLE,
 540   USE_MOD_TABLE,
 541   USE_RM_TABLE,
 542   USE_PREFIX_TABLE,
 543   USE_X86_64_TABLE,
 544   USE_3BYTE_TABLE,
 545   USE_XOP_8F_TABLE,
 546   USE_VEX_C4_TABLE,
 547   USE_VEX_C5_TABLE,
 548   USE_VEX_LEN_TABLE,
 549   USE_VEX_W_TABLE
 550 };
 551
 552 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 553
 554 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 555 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 556 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 557 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 558 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 559 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 560 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 561 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 562 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 563 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 564 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 565 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 566
 567 enum
 568 {
 569   REG_80 = 0,
 570   REG_81,
 571   REG_82,
 572   REG_8F,
 573   REG_C0,
 574   REG_C1,
 575   REG_C6,
 576   REG_C7,
 577   REG_D0,
 578   REG_D1,
 579   REG_D2,
 580   REG_D3,
 581   REG_F6,
 582   REG_F7,
 583   REG_FE,
 584   REG_FF,
 585   REG_0F00,
 586   REG_0F01,
 587   REG_0F0D,
 588   REG_0F18,
 589   REG_0F71,
 590   REG_0F72,
 591   REG_0F73,
 592   REG_0FA6,
 593   REG_0FA7,
 594   REG_0FAE,
 595   REG_0FBA,
 596   REG_0FC7,
 597   REG_VEX_71,
 598   REG_VEX_72,
 599   REG_VEX_73,
 600   REG_VEX_AE,
 601   REG_XOP_LWPCB,
 602   REG_XOP_LWP
 603 };
 604
 605 enum
 606 {
 607   MOD_8D = 0,
 608   MOD_0F01_REG_0,
 609   MOD_0F01_REG_1,
 610   MOD_0F01_REG_2,
 611   MOD_0F01_REG_3,
 612   MOD_0F01_REG_7,
 613   MOD_0F12_PREFIX_0,
 614   MOD_0F13,
 615   MOD_0F16_PREFIX_0,
 616   MOD_0F17,
 617   MOD_0F18_REG_0,
 618   MOD_0F18_REG_1,
 619   MOD_0F18_REG_2,
 620   MOD_0F18_REG_3,
 621   MOD_0F20,
 622   MOD_0F21,
 623   MOD_0F22,
 624   MOD_0F23,
 625   MOD_0F24,
 626   MOD_0F26,
 627   MOD_0F2B_PREFIX_0,
 628   MOD_0F2B_PREFIX_1,
 629   MOD_0F2B_PREFIX_2,
 630   MOD_0F2B_PREFIX_3,
 631   MOD_0F51,
 632   MOD_0F71_REG_2,
 633   MOD_0F71_REG_4,
 634   MOD_0F71_REG_6,
 635   MOD_0F72_REG_2,
 636   MOD_0F72_REG_4,
 637   MOD_0F72_REG_6,
 638   MOD_0F73_REG_2,
 639   MOD_0F73_REG_3,
 640   MOD_0F73_REG_6,
 641   MOD_0F73_REG_7,
 642   MOD_0FAE_REG_0,
 643   MOD_0FAE_REG_1,
 644   MOD_0FAE_REG_2,
 645   MOD_0FAE_REG_3,
 646   MOD_0FAE_REG_4,
 647   MOD_0FAE_REG_5,
 648   MOD_0FAE_REG_6,
 649   MOD_0FAE_REG_7,
 650   MOD_0FB2,
 651   MOD_0FB4,
 652   MOD_0FB5,
 653   MOD_0FC7_REG_6,
 654   MOD_0FC7_REG_7,
 655   MOD_0FD7,
 656   MOD_0FE7_PREFIX_2,
 657   MOD_0FF0_PREFIX_3,
 658   MOD_0F382A_PREFIX_2,
 659   MOD_62_32BIT,
 660   MOD_C4_32BIT,
 661   MOD_C5_32BIT,
 662   MOD_VEX_12_PREFIX_0,
 663   MOD_VEX_13,
 664   MOD_VEX_16_PREFIX_0,
 665   MOD_VEX_17,
 666   MOD_VEX_2B,
 667   MOD_VEX_50,
 668   MOD_VEX_71_REG_2,
 669   MOD_VEX_71_REG_4,
 670   MOD_VEX_71_REG_6,
 671   MOD_VEX_72_REG_2,
 672   MOD_VEX_72_REG_4,
 673   MOD_VEX_72_REG_6,
 674   MOD_VEX_73_REG_2,
 675   MOD_VEX_73_REG_3,
 676   MOD_VEX_73_REG_6,
 677   MOD_VEX_73_REG_7,
 678   MOD_VEX_AE_REG_2,
 679   MOD_VEX_AE_REG_3,
 680   MOD_VEX_D7_PREFIX_2,
 681   MOD_VEX_E7_PREFIX_2,
 682   MOD_VEX_F0_PREFIX_3,
 683   MOD_VEX_3818_PREFIX_2,
 684   MOD_VEX_3819_PREFIX_2,
 685   MOD_VEX_381A_PREFIX_2,
 686   MOD_VEX_382A_PREFIX_2,
 687   MOD_VEX_382C_PREFIX_2,
 688   MOD_VEX_382D_PREFIX_2,
 689   MOD_VEX_382E_PREFIX_2,
 690   MOD_VEX_382F_PREFIX_2
 691 };
 692
 693 enum
 694 {
 695   RM_0F01_REG_0 = 0,
 696   RM_0F01_REG_1,
 697   RM_0F01_REG_2,
 698   RM_0F01_REG_3,
 699   RM_0F01_REG_7,
 700   RM_0FAE_REG_5,
 701   RM_0FAE_REG_6,
 702   RM_0FAE_REG_7
 703 };
 704
 705 enum
 706 {
 707   PREFIX_90 = 0,
 708   PREFIX_0F10,
 709   PREFIX_0F11,
 710   PREFIX_0F12,
 711   PREFIX_0F16,
 712   PREFIX_0F2A,
 713   PREFIX_0F2B,
 714   PREFIX_0F2C,
 715   PREFIX_0F2D,
 716   PREFIX_0F2E,
 717   PREFIX_0F2F,
 718   PREFIX_0F51,
 719   PREFIX_0F52,
 720   PREFIX_0F53,
 721   PREFIX_0F58,
 722   PREFIX_0F59,
 723   PREFIX_0F5A,
 724   PREFIX_0F5B,
 725   PREFIX_0F5C,
 726   PREFIX_0F5D,
 727   PREFIX_0F5E,
 728   PREFIX_0F5F,
 729   PREFIX_0F60,
 730   PREFIX_0F61,
 731   PREFIX_0F62,
 732   PREFIX_0F6C,
 733   PREFIX_0F6D,
 734   PREFIX_0F6F,
 735   PREFIX_0F70,
 736   PREFIX_0F73_REG_3,
 737   PREFIX_0F73_REG_7,
 738   PREFIX_0F78,
 739   PREFIX_0F79,
 740   PREFIX_0F7C,
 741   PREFIX_0F7D,
 742   PREFIX_0F7E,
 743   PREFIX_0F7F,
 744   PREFIX_0FB8,
 745   PREFIX_0FBD,
 746   PREFIX_0FC2,
 747   PREFIX_0FC3,
 748   PREFIX_0FC7_REG_6,
 749   PREFIX_0FD0,
 750   PREFIX_0FD6,
 751   PREFIX_0FE6,
 752   PREFIX_0FE7,
 753   PREFIX_0FF0,
 754   PREFIX_0FF7,
 755   PREFIX_0F3810,
 756   PREFIX_0F3814,
 757   PREFIX_0F3815,
 758   PREFIX_0F3817,
 759   PREFIX_0F3820,
 760   PREFIX_0F3821,
 761   PREFIX_0F3822,
 762   PREFIX_0F3823,
 763   PREFIX_0F3824,
 764   PREFIX_0F3825,
 765   PREFIX_0F3828,
 766   PREFIX_0F3829,
 767   PREFIX_0F382A,
 768   PREFIX_0F382B,
 769   PREFIX_0F3830,
 770   PREFIX_0F3831,
 771   PREFIX_0F3832,
 772   PREFIX_0F3833,
 773   PREFIX_0F3834,
 774   PREFIX_0F3835,
 775   PREFIX_0F3837,
 776   PREFIX_0F3838,
 777   PREFIX_0F3839,
 778   PREFIX_0F383A,
 779   PREFIX_0F383B,
 780   PREFIX_0F383C,
 781   PREFIX_0F383D,
 782   PREFIX_0F383E,
 783   PREFIX_0F383F,
 784   PREFIX_0F3840,
 785   PREFIX_0F3841,
 786   PREFIX_0F3880,
 787   PREFIX_0F3881,
 788   PREFIX_0F38DB,
 789   PREFIX_0F38DC,
 790   PREFIX_0F38DD,
 791   PREFIX_0F38DE,
 792   PREFIX_0F38DF,
 793   PREFIX_0F38F0,
 794   PREFIX_0F38F1,
 795   PREFIX_0F3A08,
 796   PREFIX_0F3A09,
 797   PREFIX_0F3A0A,
 798   PREFIX_0F3A0B,
 799   PREFIX_0F3A0C,
 800   PREFIX_0F3A0D,
 801   PREFIX_0F3A0E,
 802   PREFIX_0F3A14,
 803   PREFIX_0F3A15,
 804   PREFIX_0F3A16,
 805   PREFIX_0F3A17,
 806   PREFIX_0F3A20,
 807   PREFIX_0F3A21,
 808   PREFIX_0F3A22,
 809   PREFIX_0F3A40,
 810   PREFIX_0F3A41,
 811   PREFIX_0F3A42,
 812   PREFIX_0F3A44,
 813   PREFIX_0F3A60,
 814   PREFIX_0F3A61,
 815   PREFIX_0F3A62,
 816   PREFIX_0F3A63,
 817   PREFIX_0F3ADF,
 818   PREFIX_VEX_10,
 819   PREFIX_VEX_11,
 820   PREFIX_VEX_12,
 821   PREFIX_VEX_16,
 822   PREFIX_VEX_2A,
 823   PREFIX_VEX_2C,
 824   PREFIX_VEX_2D,
 825   PREFIX_VEX_2E,
 826   PREFIX_VEX_2F,
 827   PREFIX_VEX_51,
 828   PREFIX_VEX_52,
 829   PREFIX_VEX_53,
 830   PREFIX_VEX_58,
 831   PREFIX_VEX_59,
 832   PREFIX_VEX_5A,
 833   PREFIX_VEX_5B,
 834   PREFIX_VEX_5C,
 835   PREFIX_VEX_5D,
 836   PREFIX_VEX_5E,
 837   PREFIX_VEX_5F,
 838   PREFIX_VEX_60,
 839   PREFIX_VEX_61,
 840   PREFIX_VEX_62,
 841   PREFIX_VEX_63,
 842   PREFIX_VEX_64,
 843   PREFIX_VEX_65,
 844   PREFIX_VEX_66,
 845   PREFIX_VEX_67,
 846   PREFIX_VEX_68,
 847   PREFIX_VEX_69,
 848   PREFIX_VEX_6A,
 849   PREFIX_VEX_6B,
 850   PREFIX_VEX_6C,
 851   PREFIX_VEX_6D,
 852   PREFIX_VEX_6E,
 853   PREFIX_VEX_6F,
 854   PREFIX_VEX_70,
 855   PREFIX_VEX_71_REG_2,
 856   PREFIX_VEX_71_REG_4,
 857   PREFIX_VEX_71_REG_6,
 858   PREFIX_VEX_72_REG_2,
 859   PREFIX_VEX_72_REG_4,
 860   PREFIX_VEX_72_REG_6,
 861   PREFIX_VEX_73_REG_2,
 862   PREFIX_VEX_73_REG_3,
 863   PREFIX_VEX_73_REG_6,
 864   PREFIX_VEX_73_REG_7,
 865   PREFIX_VEX_74,
 866   PREFIX_VEX_75,
 867   PREFIX_VEX_76,
 868   PREFIX_VEX_77,
 869   PREFIX_VEX_7C,
 870   PREFIX_VEX_7D,
 871   PREFIX_VEX_7E,
 872   PREFIX_VEX_7F,
 873   PREFIX_VEX_C2,
 874   PREFIX_VEX_C4,
 875   PREFIX_VEX_C5,
 876   PREFIX_VEX_D0,
 877   PREFIX_VEX_D1,
 878   PREFIX_VEX_D2,
 879   PREFIX_VEX_D3,
 880   PREFIX_VEX_D4,
 881   PREFIX_VEX_D5,
 882   PREFIX_VEX_D6,
 883   PREFIX_VEX_D7,
 884   PREFIX_VEX_D8,
 885   PREFIX_VEX_D9,
 886   PREFIX_VEX_DA,
 887   PREFIX_VEX_DB,
 888   PREFIX_VEX_DC,
 889   PREFIX_VEX_DD,
 890   PREFIX_VEX_DE,
 891   PREFIX_VEX_DF,
 892   PREFIX_VEX_E0,
 893   PREFIX_VEX_E1,
 894   PREFIX_VEX_E2,
 895   PREFIX_VEX_E3,
 896   PREFIX_VEX_E4,
 897   PREFIX_VEX_E5,
 898   PREFIX_VEX_E6,
 899   PREFIX_VEX_E7,
 900   PREFIX_VEX_E8,
 901   PREFIX_VEX_E9,
 902   PREFIX_VEX_EA,
 903   PREFIX_VEX_EB,
 904   PREFIX_VEX_EC,
 905   PREFIX_VEX_ED,
 906   PREFIX_VEX_EE,
 907   PREFIX_VEX_EF,
 908   PREFIX_VEX_F0,
 909   PREFIX_VEX_F1,
 910   PREFIX_VEX_F2,
 911   PREFIX_VEX_F3,
 912   PREFIX_VEX_F4,
 913   PREFIX_VEX_F5,
 914   PREFIX_VEX_F6,
 915   PREFIX_VEX_F7,
 916   PREFIX_VEX_F8,
 917   PREFIX_VEX_F9,
 918   PREFIX_VEX_FA,
 919   PREFIX_VEX_FB,
 920   PREFIX_VEX_FC,
 921   PREFIX_VEX_FD,
 922   PREFIX_VEX_FE,
 923   PREFIX_VEX_3800,
 924   PREFIX_VEX_3801,
 925   PREFIX_VEX_3802,
 926   PREFIX_VEX_3803,
 927   PREFIX_VEX_3804,
 928   PREFIX_VEX_3805,
 929   PREFIX_VEX_3806,
 930   PREFIX_VEX_3807,
 931   PREFIX_VEX_3808,
 932   PREFIX_VEX_3809,
 933   PREFIX_VEX_380A,
 934   PREFIX_VEX_380B,
 935   PREFIX_VEX_380C,
 936   PREFIX_VEX_380D,
 937   PREFIX_VEX_380E,
 938   PREFIX_VEX_380F,
 939   PREFIX_VEX_3817,
 940   PREFIX_VEX_3818,
 941   PREFIX_VEX_3819,
 942   PREFIX_VEX_381A,
 943   PREFIX_VEX_381C,
 944   PREFIX_VEX_381D,
 945   PREFIX_VEX_381E,
 946   PREFIX_VEX_3820,
 947   PREFIX_VEX_3821,
 948   PREFIX_VEX_3822,
 949   PREFIX_VEX_3823,
 950   PREFIX_VEX_3824,
 951   PREFIX_VEX_3825,
 952   PREFIX_VEX_3828,
 953   PREFIX_VEX_3829,
 954   PREFIX_VEX_382A,
 955   PREFIX_VEX_382B,
 956   PREFIX_VEX_382C,
 957   PREFIX_VEX_382D,
 958   PREFIX_VEX_382E,
 959   PREFIX_VEX_382F,
 960   PREFIX_VEX_3830,
 961   PREFIX_VEX_3831,
 962   PREFIX_VEX_3832,
 963   PREFIX_VEX_3833,
 964   PREFIX_VEX_3834,
 965   PREFIX_VEX_3835,
 966   PREFIX_VEX_3837,
 967   PREFIX_VEX_3838,
 968   PREFIX_VEX_3839,
 969   PREFIX_VEX_383A,
 970   PREFIX_VEX_383B,
 971   PREFIX_VEX_383C,
 972   PREFIX_VEX_383D,
 973   PREFIX_VEX_383E,
 974   PREFIX_VEX_383F,
 975   PREFIX_VEX_3840,
 976   PREFIX_VEX_3841,
 977   PREFIX_VEX_3896,
 978   PREFIX_VEX_3897,
 979   PREFIX_VEX_3898,
 980   PREFIX_VEX_3899,
 981   PREFIX_VEX_389A,
 982   PREFIX_VEX_389B,
 983   PREFIX_VEX_389C,
 984   PREFIX_VEX_389D,
 985   PREFIX_VEX_389E,
 986   PREFIX_VEX_389F,
 987   PREFIX_VEX_38A6,
 988   PREFIX_VEX_38A7,
 989   PREFIX_VEX_38A8,
 990   PREFIX_VEX_38A9,
 991   PREFIX_VEX_38AA,
 992   PREFIX_VEX_38AB,
 993   PREFIX_VEX_38AC,
 994   PREFIX_VEX_38AD,
 995   PREFIX_VEX_38AE,
 996   PREFIX_VEX_38AF,
 997   PREFIX_VEX_38B6,
 998   PREFIX_VEX_38B7,
 999   PREFIX_VEX_38B8,
1000   PREFIX_VEX_38B9,
1001   PREFIX_VEX_38BA,
1002   PREFIX_VEX_38BB,
1003   PREFIX_VEX_38BC,
1004   PREFIX_VEX_38BD,
1005   PREFIX_VEX_38BE,
1006   PREFIX_VEX_38BF,
1007   PREFIX_VEX_38DB,
1008   PREFIX_VEX_38DC,
1009   PREFIX_VEX_38DD,
1010   PREFIX_VEX_38DE,
1011   PREFIX_VEX_38DF,
1012   PREFIX_VEX_3A04,
1013   PREFIX_VEX_3A05,
1014   PREFIX_VEX_3A06,
1015   PREFIX_VEX_3A08,
1016   PREFIX_VEX_3A09,
1017   PREFIX_VEX_3A0A,
1018   PREFIX_VEX_3A0B,
1019   PREFIX_VEX_3A0C,
1020   PREFIX_VEX_3A0D,
1021   PREFIX_VEX_3A0E,
1022   PREFIX_VEX_3A0F,
1023   PREFIX_VEX_3A14,
1024   PREFIX_VEX_3A15,
1025   PREFIX_VEX_3A16,
1026   PREFIX_VEX_3A17,
1027   PREFIX_VEX_3A18,
1028   PREFIX_VEX_3A19,
1029   PREFIX_VEX_3A20,
1030   PREFIX_VEX_3A21,
1031   PREFIX_VEX_3A22,
1032   PREFIX_VEX_3A40,
1033   PREFIX_VEX_3A41,
1034   PREFIX_VEX_3A42,
1035   PREFIX_VEX_3A44,
1036   PREFIX_VEX_3A48,
1037   PREFIX_VEX_3A49,
1038   PREFIX_VEX_3A4A,
1039   PREFIX_VEX_3A4B,
1040   PREFIX_VEX_3A4C,
1041   PREFIX_VEX_3A5C,
1042   PREFIX_VEX_3A5D,
1043   PREFIX_VEX_3A5E,
1044   PREFIX_VEX_3A5F,
1045   PREFIX_VEX_3A60,
1046   PREFIX_VEX_3A61,
1047   PREFIX_VEX_3A62,
1048   PREFIX_VEX_3A63,
1049   PREFIX_VEX_3A68,
1050   PREFIX_VEX_3A69,
1051   PREFIX_VEX_3A6A,
1052   PREFIX_VEX_3A6B,
1053   PREFIX_VEX_3A6C,
1054   PREFIX_VEX_3A6D,
1055   PREFIX_VEX_3A6E,
1056   PREFIX_VEX_3A6F,
1057   PREFIX_VEX_3A78,
1058   PREFIX_VEX_3A79,
1059   PREFIX_VEX_3A7A,
1060   PREFIX_VEX_3A7B,
1061   PREFIX_VEX_3A7C,
1062   PREFIX_VEX_3A7D,
1063   PREFIX_VEX_3A7E,
1064   PREFIX_VEX_3A7F,
1065   PREFIX_VEX_3ADF
1066 };
1067
1068 enum
1069 {
1070   X86_64_06 = 0,
1071   X86_64_07,
1072   X86_64_0D,
1073   X86_64_16,
1074   X86_64_17,
1075   X86_64_1E,
1076   X86_64_1F,
1077   X86_64_27,
1078   X86_64_2F,
1079   X86_64_37,
1080   X86_64_3F,
1081   X86_64_60,
1082   X86_64_61,
1083   X86_64_62,
1084   X86_64_63,
1085   X86_64_6D,
1086   X86_64_6F,
1087   X86_64_9A,
1088   X86_64_C4,
1089   X86_64_C5,
1090   X86_64_CE,
1091   X86_64_D4,
1092   X86_64_D5,
1093   X86_64_EA,
1094   X86_64_0F01_REG_0,
1095   X86_64_0F01_REG_1,
1096   X86_64_0F01_REG_2,
1097   X86_64_0F01_REG_3
1098 };
1099
1100 enum
1101 {
1102   THREE_BYTE_0F38 = 0,
1103   THREE_BYTE_0F3A,
1104   THREE_BYTE_0F7A
1105 };
1106
1107 enum
1108 {
1109   XOP_08 = 0,
1110   XOP_09,
1111   XOP_0A
1112 };
1113
1114 enum
1115 {
1116   VEX_0F = 0,
1117   VEX_0F38,
1118   VEX_0F3A
1119 };
1120
1121 enum
1122 {
1123   VEX_LEN_10_P_1 = 0,
1124   VEX_LEN_10_P_3,
1125   VEX_LEN_11_P_1,
1126   VEX_LEN_11_P_3,
1127   VEX_LEN_12_P_0_M_0,
1128   VEX_LEN_12_P_0_M_1,
1129   VEX_LEN_12_P_2,
1130   VEX_LEN_13_M_0,
1131   VEX_LEN_16_P_0_M_0,
1132   VEX_LEN_16_P_0_M_1,
1133   VEX_LEN_16_P_2,
1134   VEX_LEN_17_M_0,
1135   VEX_LEN_2A_P_1,
1136   VEX_LEN_2A_P_3,
1137   VEX_LEN_2C_P_1,
1138   VEX_LEN_2C_P_3,
1139   VEX_LEN_2D_P_1,
1140   VEX_LEN_2D_P_3,
1141   VEX_LEN_2E_P_0,
1142   VEX_LEN_2E_P_2,
1143   VEX_LEN_2F_P_0,
1144   VEX_LEN_2F_P_2,
1145   VEX_LEN_51_P_1,
1146   VEX_LEN_51_P_3,
1147   VEX_LEN_52_P_1,
1148   VEX_LEN_53_P_1,
1149   VEX_LEN_58_P_1,
1150   VEX_LEN_58_P_3,
1151   VEX_LEN_59_P_1,
1152   VEX_LEN_59_P_3,
1153   VEX_LEN_5A_P_1,
1154   VEX_LEN_5A_P_3,
1155   VEX_LEN_5C_P_1,
1156   VEX_LEN_5C_P_3,
1157   VEX_LEN_5D_P_1,
1158   VEX_LEN_5D_P_3,
1159   VEX_LEN_5E_P_1,
1160   VEX_LEN_5E_P_3,
1161   VEX_LEN_5F_P_1,
1162   VEX_LEN_5F_P_3,
1163   VEX_LEN_60_P_2,
1164   VEX_LEN_61_P_2,
1165   VEX_LEN_62_P_2,
1166   VEX_LEN_63_P_2,
1167   VEX_LEN_64_P_2,
1168   VEX_LEN_65_P_2,
1169   VEX_LEN_66_P_2,
1170   VEX_LEN_67_P_2,
1171   VEX_LEN_68_P_2,
1172   VEX_LEN_69_P_2,
1173   VEX_LEN_6A_P_2,
1174   VEX_LEN_6B_P_2,
1175   VEX_LEN_6C_P_2,
1176   VEX_LEN_6D_P_2,
1177   VEX_LEN_6E_P_2,
1178   VEX_LEN_70_P_1,
1179   VEX_LEN_70_P_2,
1180   VEX_LEN_70_P_3,
1181   VEX_LEN_71_R_2_P_2,
1182   VEX_LEN_71_R_4_P_2,
1183   VEX_LEN_71_R_6_P_2,
1184   VEX_LEN_72_R_2_P_2,
1185   VEX_LEN_72_R_4_P_2,
1186   VEX_LEN_72_R_6_P_2,
1187   VEX_LEN_73_R_2_P_2,
1188   VEX_LEN_73_R_3_P_2,
1189   VEX_LEN_73_R_6_P_2,
1190   VEX_LEN_73_R_7_P_2,
1191   VEX_LEN_74_P_2,
1192   VEX_LEN_75_P_2,
1193   VEX_LEN_76_P_2,
1194   VEX_LEN_7E_P_1,
1195   VEX_LEN_7E_P_2,
1196   VEX_LEN_AE_R_2_M_0,
1197   VEX_LEN_AE_R_3_M_0,
1198   VEX_LEN_C2_P_1,
1199   VEX_LEN_C2_P_3,
1200   VEX_LEN_C4_P_2,
1201   VEX_LEN_C5_P_2,
1202   VEX_LEN_D1_P_2,
1203   VEX_LEN_D2_P_2,
1204   VEX_LEN_D3_P_2,
1205   VEX_LEN_D4_P_2,
1206   VEX_LEN_D5_P_2,
1207   VEX_LEN_D6_P_2,
1208   VEX_LEN_D7_P_2_M_1,
1209   VEX_LEN_D8_P_2,
1210   VEX_LEN_D9_P_2,
1211   VEX_LEN_DA_P_2,
1212   VEX_LEN_DB_P_2,
1213   VEX_LEN_DC_P_2,
1214   VEX_LEN_DD_P_2,
1215   VEX_LEN_DE_P_2,
1216   VEX_LEN_DF_P_2,
1217   VEX_LEN_E0_P_2,
1218   VEX_LEN_E1_P_2,
1219   VEX_LEN_E2_P_2,
1220   VEX_LEN_E3_P_2,
1221   VEX_LEN_E4_P_2,
1222   VEX_LEN_E5_P_2,
1223   VEX_LEN_E8_P_2,
1224   VEX_LEN_E9_P_2,
1225   VEX_LEN_EA_P_2,
1226   VEX_LEN_EB_P_2,
1227   VEX_LEN_EC_P_2,
1228   VEX_LEN_ED_P_2,
1229   VEX_LEN_EE_P_2,
1230   VEX_LEN_EF_P_2,
1231   VEX_LEN_F1_P_2,
1232   VEX_LEN_F2_P_2,
1233   VEX_LEN_F3_P_2,
1234   VEX_LEN_F4_P_2,
1235   VEX_LEN_F5_P_2,
1236   VEX_LEN_F6_P_2,
1237   VEX_LEN_F7_P_2,
1238   VEX_LEN_F8_P_2,
1239   VEX_LEN_F9_P_2,
1240   VEX_LEN_FA_P_2,
1241   VEX_LEN_FB_P_2,
1242   VEX_LEN_FC_P_2,
1243   VEX_LEN_FD_P_2,
1244   VEX_LEN_FE_P_2,
1245   VEX_LEN_3800_P_2,
1246   VEX_LEN_3801_P_2,
1247   VEX_LEN_3802_P_2,
1248   VEX_LEN_3803_P_2,
1249   VEX_LEN_3804_P_2,
1250   VEX_LEN_3805_P_2,
1251   VEX_LEN_3806_P_2,
1252   VEX_LEN_3807_P_2,
1253   VEX_LEN_3808_P_2,
1254   VEX_LEN_3809_P_2,
1255   VEX_LEN_380A_P_2,
1256   VEX_LEN_380B_P_2,
1257   VEX_LEN_3819_P_2_M_0,
1258   VEX_LEN_381A_P_2_M_0,
1259   VEX_LEN_381C_P_2,
1260   VEX_LEN_381D_P_2,
1261   VEX_LEN_381E_P_2,
1262   VEX_LEN_3820_P_2,
1263   VEX_LEN_3821_P_2,
1264   VEX_LEN_3822_P_2,
1265   VEX_LEN_3823_P_2,
1266   VEX_LEN_3824_P_2,
1267   VEX_LEN_3825_P_2,
1268   VEX_LEN_3828_P_2,
1269   VEX_LEN_3829_P_2,
1270   VEX_LEN_382A_P_2_M_0,
1271   VEX_LEN_382B_P_2,
1272   VEX_LEN_3830_P_2,
1273   VEX_LEN_3831_P_2,
1274   VEX_LEN_3832_P_2,
1275   VEX_LEN_3833_P_2,
1276   VEX_LEN_3834_P_2,
1277   VEX_LEN_3835_P_2,
1278   VEX_LEN_3837_P_2,
1279   VEX_LEN_3838_P_2,
1280   VEX_LEN_3839_P_2,
1281   VEX_LEN_383A_P_2,
1282   VEX_LEN_383B_P_2,
1283   VEX_LEN_383C_P_2,
1284   VEX_LEN_383D_P_2,
1285   VEX_LEN_383E_P_2,
1286   VEX_LEN_383F_P_2,
1287   VEX_LEN_3840_P_2,
1288   VEX_LEN_3841_P_2,
1289   VEX_LEN_38DB_P_2,
1290   VEX_LEN_38DC_P_2,
1291   VEX_LEN_38DD_P_2,
1292   VEX_LEN_38DE_P_2,
1293   VEX_LEN_38DF_P_2,
1294   VEX_LEN_3A06_P_2,
1295   VEX_LEN_3A0A_P_2,
1296   VEX_LEN_3A0B_P_2,
1297   VEX_LEN_3A0E_P_2,
1298   VEX_LEN_3A0F_P_2,
1299   VEX_LEN_3A14_P_2,
1300   VEX_LEN_3A15_P_2,
1301   VEX_LEN_3A16_P_2,
1302   VEX_LEN_3A17_P_2,
1303   VEX_LEN_3A18_P_2,
1304   VEX_LEN_3A19_P_2,
1305   VEX_LEN_3A20_P_2,
1306   VEX_LEN_3A21_P_2,
1307   VEX_LEN_3A22_P_2,
1308   VEX_LEN_3A41_P_2,
1309   VEX_LEN_3A42_P_2,
1310   VEX_LEN_3A44_P_2,
1311   VEX_LEN_3A4C_P_2,
1312   VEX_LEN_3A60_P_2,
1313   VEX_LEN_3A61_P_2,
1314   VEX_LEN_3A62_P_2,
1315   VEX_LEN_3A63_P_2,
1316   VEX_LEN_3A6A_P_2,
1317   VEX_LEN_3A6B_P_2,
1318   VEX_LEN_3A6E_P_2,
1319   VEX_LEN_3A6F_P_2,
1320   VEX_LEN_3A7A_P_2,
1321   VEX_LEN_3A7B_P_2,
1322   VEX_LEN_3A7E_P_2,
1323   VEX_LEN_3A7F_P_2,
1324   VEX_LEN_3ADF_P_2,
1325   VEX_LEN_XOP_09_80,
1326   VEX_LEN_XOP_09_81
1327 };
1328
1329 enum
1330 {
1331   VEX_W_10_P_0 = 0,
1332   VEX_W_10_P_1,
1333   VEX_W_10_P_2,
1334   VEX_W_10_P_3,
1335   VEX_W_11_P_0,
1336   VEX_W_11_P_1,
1337   VEX_W_11_P_2,
1338   VEX_W_11_P_3,
1339   VEX_W_12_P_0_M_0,
1340   VEX_W_12_P_0_M_1,
1341   VEX_W_12_P_1,
1342   VEX_W_12_P_2,
1343   VEX_W_12_P_3,
1344   VEX_W_13_M_0,
1345   VEX_W_14,
1346   VEX_W_15,
1347   VEX_W_16_P_0_M_0,
1348   VEX_W_16_P_0_M_1,
1349   VEX_W_16_P_1,
1350   VEX_W_16_P_2,
1351   VEX_W_17_M_0,
1352   VEX_W_28,
1353   VEX_W_29,
1354   VEX_W_2B_M_0,
1355   VEX_W_2E_P_0,
1356   VEX_W_2E_P_2,
1357   VEX_W_2F_P_0,
1358   VEX_W_2F_P_2,
1359   VEX_W_50_M_0,
1360   VEX_W_51_P_0,
1361   VEX_W_51_P_1,
1362   VEX_W_51_P_2,
1363   VEX_W_51_P_3,
1364   VEX_W_52_P_0,
1365   VEX_W_52_P_1,
1366   VEX_W_53_P_0,
1367   VEX_W_53_P_1,
1368   VEX_W_58_P_0,
1369   VEX_W_58_P_1,
1370   VEX_W_58_P_2,
1371   VEX_W_58_P_3,
1372   VEX_W_59_P_0,
1373   VEX_W_59_P_1,
1374   VEX_W_59_P_2,
1375   VEX_W_59_P_3,
1376   VEX_W_5A_P_0,
1377   VEX_W_5A_P_1,
1378   VEX_W_5A_P_3,
1379   VEX_W_5B_P_0,
1380   VEX_W_5B_P_1,
1381   VEX_W_5B_P_2,
1382   VEX_W_5C_P_0,
1383   VEX_W_5C_P_1,
1384   VEX_W_5C_P_2,
1385   VEX_W_5C_P_3,
1386   VEX_W_5D_P_0,
1387   VEX_W_5D_P_1,
1388   VEX_W_5D_P_2,
1389   VEX_W_5D_P_3,
1390   VEX_W_5E_P_0,
1391   VEX_W_5E_P_1,
1392   VEX_W_5E_P_2,
1393   VEX_W_5E_P_3,
1394   VEX_W_5F_P_0,
1395   VEX_W_5F_P_1,
1396   VEX_W_5F_P_2,
1397   VEX_W_5F_P_3,
1398   VEX_W_60_P_2,
1399   VEX_W_61_P_2,
1400   VEX_W_62_P_2,
1401   VEX_W_63_P_2,
1402   VEX_W_64_P_2,
1403   VEX_W_65_P_2,
1404   VEX_W_66_P_2,
1405   VEX_W_67_P_2,
1406   VEX_W_68_P_2,
1407   VEX_W_69_P_2,
1408   VEX_W_6A_P_2,
1409   VEX_W_6B_P_2,
1410   VEX_W_6C_P_2,
1411   VEX_W_6D_P_2,
1412   VEX_W_6F_P_1,
1413   VEX_W_6F_P_2,
1414   VEX_W_70_P_1,
1415   VEX_W_70_P_2,
1416   VEX_W_70_P_3,
1417   VEX_W_71_R_2_P_2,
1418   VEX_W_71_R_4_P_2,
1419   VEX_W_71_R_6_P_2,
1420   VEX_W_72_R_2_P_2,
1421   VEX_W_72_R_4_P_2,
1422   VEX_W_72_R_6_P_2,
1423   VEX_W_73_R_2_P_2,
1424   VEX_W_73_R_3_P_2,
1425   VEX_W_73_R_6_P_2,
1426   VEX_W_73_R_7_P_2,
1427   VEX_W_74_P_2,
1428   VEX_W_75_P_2,
1429   VEX_W_76_P_2,
1430   VEX_W_77_P_0,
1431   VEX_W_7C_P_2,
1432   VEX_W_7C_P_3,
1433   VEX_W_7D_P_2,
1434   VEX_W_7D_P_3,
1435   VEX_W_7E_P_1,
1436   VEX_W_7F_P_1,
1437   VEX_W_7F_P_2,
1438   VEX_W_AE_R_2_M_0,
1439   VEX_W_AE_R_3_M_0,
1440   VEX_W_C2_P_0,
1441   VEX_W_C2_P_1,
1442   VEX_W_C2_P_2,
1443   VEX_W_C2_P_3,
1444   VEX_W_C4_P_2,
1445   VEX_W_C5_P_2,
1446   VEX_W_D0_P_2,
1447   VEX_W_D0_P_3,
1448   VEX_W_D1_P_2,
1449   VEX_W_D2_P_2,
1450   VEX_W_D3_P_2,
1451   VEX_W_D4_P_2,
1452   VEX_W_D5_P_2,
1453   VEX_W_D6_P_2,
1454   VEX_W_D7_P_2_M_1,
1455   VEX_W_D8_P_2,
1456   VEX_W_D9_P_2,
1457   VEX_W_DA_P_2,
1458   VEX_W_DB_P_2,
1459   VEX_W_DC_P_2,
1460   VEX_W_DD_P_2,
1461   VEX_W_DE_P_2,
1462   VEX_W_DF_P_2,
1463   VEX_W_E0_P_2,
1464   VEX_W_E1_P_2,
1465   VEX_W_E2_P_2,
1466   VEX_W_E3_P_2,
1467   VEX_W_E4_P_2,
1468   VEX_W_E5_P_2,
1469   VEX_W_E6_P_1,
1470   VEX_W_E6_P_2,
1471   VEX_W_E6_P_3,
1472   VEX_W_E7_P_2_M_0,
1473   VEX_W_E8_P_2,
1474   VEX_W_E9_P_2,
1475   VEX_W_EA_P_2,
1476   VEX_W_EB_P_2,
1477   VEX_W_EC_P_2,
1478   VEX_W_ED_P_2,
1479   VEX_W_EE_P_2,
1480   VEX_W_EF_P_2,
1481   VEX_W_F0_P_3_M_0,
1482   VEX_W_F1_P_2,
1483   VEX_W_F2_P_2,
1484   VEX_W_F3_P_2,
1485   VEX_W_F4_P_2,
1486   VEX_W_F5_P_2,
1487   VEX_W_F6_P_2,
1488   VEX_W_F7_P_2,
1489   VEX_W_F8_P_2,
1490   VEX_W_F9_P_2,
1491   VEX_W_FA_P_2,
1492   VEX_W_FB_P_2,
1493   VEX_W_FC_P_2,
1494   VEX_W_FD_P_2,
1495   VEX_W_FE_P_2,
1496   VEX_W_3800_P_2,
1497   VEX_W_3801_P_2,
1498   VEX_W_3802_P_2,
1499   VEX_W_3803_P_2,
1500   VEX_W_3804_P_2,
1501   VEX_W_3805_P_2,
1502   VEX_W_3806_P_2,
1503   VEX_W_3807_P_2,
1504   VEX_W_3808_P_2,
1505   VEX_W_3809_P_2,
1506   VEX_W_380A_P_2,
1507   VEX_W_380B_P_2,
1508   VEX_W_380C_P_2,
1509   VEX_W_380D_P_2,
1510   VEX_W_380E_P_2,
1511   VEX_W_380F_P_2,
1512   VEX_W_3817_P_2,
1513   VEX_W_3818_P_2_M_0,
1514   VEX_W_3819_P_2_M_0,
1515   VEX_W_381A_P_2_M_0,
1516   VEX_W_381C_P_2,
1517   VEX_W_381D_P_2,
1518   VEX_W_381E_P_2,
1519   VEX_W_3820_P_2,
1520   VEX_W_3821_P_2,
1521   VEX_W_3822_P_2,
1522   VEX_W_3823_P_2,
1523   VEX_W_3824_P_2,
1524   VEX_W_3825_P_2,
1525   VEX_W_3828_P_2,
1526   VEX_W_3829_P_2,
1527   VEX_W_382A_P_2_M_0,
1528   VEX_W_382B_P_2,
1529   VEX_W_382C_P_2_M_0,
1530   VEX_W_382D_P_2_M_0,
1531   VEX_W_382E_P_2_M_0,
1532   VEX_W_382F_P_2_M_0,
1533   VEX_W_3830_P_2,
1534   VEX_W_3831_P_2,
1535   VEX_W_3832_P_2,
1536   VEX_W_3833_P_2,
1537   VEX_W_3834_P_2,
1538   VEX_W_3835_P_2,
1539   VEX_W_3837_P_2,
1540   VEX_W_3838_P_2,
1541   VEX_W_3839_P_2,
1542   VEX_W_383A_P_2,
1543   VEX_W_383B_P_2,
1544   VEX_W_383C_P_2,
1545   VEX_W_383D_P_2,
1546   VEX_W_383E_P_2,
1547   VEX_W_383F_P_2,
1548   VEX_W_3840_P_2,
1549   VEX_W_3841_P_2,
1550   VEX_W_38DB_P_2,
1551   VEX_W_38DC_P_2,
1552   VEX_W_38DD_P_2,
1553   VEX_W_38DE_P_2,
1554   VEX_W_38DF_P_2,
1555   VEX_W_3A04_P_2,
1556   VEX_W_3A05_P_2,
1557   VEX_W_3A06_P_2,
1558   VEX_W_3A08_P_2,
1559   VEX_W_3A09_P_2,
1560   VEX_W_3A0A_P_2,
1561   VEX_W_3A0B_P_2,
1562   VEX_W_3A0C_P_2,
1563   VEX_W_3A0D_P_2,
1564   VEX_W_3A0E_P_2,
1565   VEX_W_3A0F_P_2,
1566   VEX_W_3A14_P_2,
1567   VEX_W_3A15_P_2,
1568   VEX_W_3A18_P_2,
1569   VEX_W_3A19_P_2,
1570   VEX_W_3A20_P_2,
1571   VEX_W_3A21_P_2,
1572   VEX_W_3A40_P_2,
1573   VEX_W_3A41_P_2,
1574   VEX_W_3A42_P_2,
1575   VEX_W_3A44_P_2,
1576   VEX_W_3A48_P_2,
1577   VEX_W_3A49_P_2,
1578   VEX_W_3A4A_P_2,
1579   VEX_W_3A4B_P_2,
1580   VEX_W_3A4C_P_2,
1581   VEX_W_3A60_P_2,
1582   VEX_W_3A61_P_2,
1583   VEX_W_3A62_P_2,
1584   VEX_W_3A63_P_2,
1585   VEX_W_3ADF_P_2
1586 };
1587
1588 typedef void (*op_rtn) (int bytemode, int sizeflag);
1589
1590 struct dis386 {
1591   const char *name;
1592   struct
1593     {
1594       op_rtn rtn;
1595       int bytemode;
1596     } op[MAX_OPERANDS];
1597 };
1598
1599 /* Upper case letters in the instruction names here are macros.
1600    'A' => print 'b' if no register operands or suffix_always is true
1601    'B' => print 'b' if suffix_always is true
1602    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1603           size prefix
1604    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1605           suffix_always is true
1606    'E' => print 'e' if 32-bit form of jcxz
1607    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1608    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1609    'H' => print ",pt" or ",pn" branch hint
1610    'I' => honor following macro letter even in Intel mode (implemented only
1611           for some of the macro letters)
1612    'J' => print 'l'
1613    'K' => print 'd' or 'q' if rex prefix is present.
1614    'L' => print 'l' if suffix_always is true
1615    'M' => print 'r' if intel_mnemonic is false.
1616    'N' => print 'n' if instruction has no wait "prefix"
1617    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1618    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1619           or suffix_always is true.  print 'q' if rex prefix is present.
1620    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1621           is true
1622    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1623    'S' => print 'w', 'l' or 'q' if suffix_always is true
1624    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1625    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1626    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1627    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1628    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1629    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1630           suffix_always is true.
1631    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1632    '!' => change condition from true to false or from false to true.
1633    '%' => add 1 upper case letter to the macro.
1634
1635    2 upper case letter macros:
1636    "XY" => print 'x' or 'y' if no register operands or suffix_always
1637            is true.
1638    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1639    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1640            or suffix_always is true
1641    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1642    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1643    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1644
1645    Many of the above letters print nothing in Intel mode.  See "putop"
1646    for the details.
1647
1648    Braces '{' and '}', and vertical bars '|', indicate alternative
1649    mnemonic strings for AT&T and Intel.  */
1650
1651 static const struct dis386 dis386[] = {
1652   /* 00 */
1653   { "addB",             { Eb, Gb } },
1654   { "addS",             { Ev, Gv } },
1655   { "addB",             { Gb, EbS } },
1656   { "addS",             { Gv, EvS } },
1657   { "addB",             { AL, Ib } },
1658   { "addS",             { eAX, Iv } },
1659   { X86_64_TABLE (X86_64_06) },
1660   { X86_64_TABLE (X86_64_07) },
1661   /* 08 */
1662   { "orB",              { Eb, Gb } },
1663   { "orS",              { Ev, Gv } },
1664   { "orB",              { Gb, EbS } },
1665   { "orS",              { Gv, EvS } },
1666   { "orB",              { AL, Ib } },
1667   { "orS",              { eAX, Iv } },
1668   { X86_64_TABLE (X86_64_0D) },
1669   { Bad_Opcode },       /* 0x0f extended opcode escape */
1670   /* 10 */
1671   { "adcB",             { Eb, Gb } },
1672   { "adcS",             { Ev, Gv } },
1673   { "adcB",             { Gb, EbS } },
1674   { "adcS",             { Gv, EvS } },
1675   { "adcB",             { AL, Ib } },
1676   { "adcS",             { eAX, Iv } },
1677   { X86_64_TABLE (X86_64_16) },
1678   { X86_64_TABLE (X86_64_17) },
1679   /* 18 */
1680   { "sbbB",             { Eb, Gb } },
1681   { "sbbS",             { Ev, Gv } },
1682   { "sbbB",             { Gb, EbS } },
1683   { "sbbS",             { Gv, EvS } },
1684   { "sbbB",             { AL, Ib } },
1685   { "sbbS",             { eAX, Iv } },
1686   { X86_64_TABLE (X86_64_1E) },
1687   { X86_64_TABLE (X86_64_1F) },
1688   /* 20 */
1689   { "andB",             { Eb, Gb } },
1690   { "andS",             { Ev, Gv } },
1691   { "andB",             { Gb, EbS } },
1692   { "andS",             { Gv, EvS } },
1693   { "andB",             { AL, Ib } },
1694   { "andS",             { eAX, Iv } },
1695   { Bad_Opcode },       /* SEG ES prefix */
1696   { X86_64_TABLE (X86_64_27) },
1697   /* 28 */
1698   { "subB",             { Eb, Gb } },
1699   { "subS",             { Ev, Gv } },
1700   { "subB",             { Gb, EbS } },
1701   { "subS",             { Gv, EvS } },
1702   { "subB",             { AL, Ib } },
1703   { "subS",             { eAX, Iv } },
1704   { Bad_Opcode },       /* SEG CS prefix */
1705   { X86_64_TABLE (X86_64_2F) },
1706   /* 30 */
1707   { "xorB",             { Eb, Gb } },
1708   { "xorS",             { Ev, Gv } },
1709   { "xorB",             { Gb, EbS } },
1710   { "xorS",             { Gv, EvS } },
1711   { "xorB",             { AL, Ib } },
1712   { "xorS",             { eAX, Iv } },
1713   { Bad_Opcode },       /* SEG SS prefix */
1714   { X86_64_TABLE (X86_64_37) },
1715   /* 38 */
1716   { "cmpB",             { Eb, Gb } },
1717   { "cmpS",             { Ev, Gv } },
1718   { "cmpB",             { Gb, EbS } },
1719   { "cmpS",             { Gv, EvS } },
1720   { "cmpB",             { AL, Ib } },
1721   { "cmpS",             { eAX, Iv } },
1722   { Bad_Opcode },       /* SEG DS prefix */
1723   { X86_64_TABLE (X86_64_3F) },
1724   /* 40 */
1725   { "inc{S|}",          { RMeAX } },
1726   { "inc{S|}",          { RMeCX } },
1727   { "inc{S|}",          { RMeDX } },
1728   { "inc{S|}",          { RMeBX } },
1729   { "inc{S|}",          { RMeSP } },
1730   { "inc{S|}",          { RMeBP } },
1731   { "inc{S|}",          { RMeSI } },
1732   { "inc{S|}",          { RMeDI } },
1733   /* 48 */
1734   { "dec{S|}",          { RMeAX } },
1735   { "dec{S|}",          { RMeCX } },
1736   { "dec{S|}",          { RMeDX } },
1737   { "dec{S|}",          { RMeBX } },
1738   { "dec{S|}",          { RMeSP } },
1739   { "dec{S|}",          { RMeBP } },
1740   { "dec{S|}",          { RMeSI } },
1741   { "dec{S|}",          { RMeDI } },
1742   /* 50 */
1743   { "pushV",            { RMrAX } },
1744   { "pushV",            { RMrCX } },
1745   { "pushV",            { RMrDX } },
1746   { "pushV",            { RMrBX } },
1747   { "pushV",            { RMrSP } },
1748   { "pushV",            { RMrBP } },
1749   { "pushV",            { RMrSI } },
1750   { "pushV",            { RMrDI } },
1751   /* 58 */
1752   { "popV",             { RMrAX } },
1753   { "popV",             { RMrCX } },
1754   { "popV",             { RMrDX } },
1755   { "popV",             { RMrBX } },
1756   { "popV",             { RMrSP } },
1757   { "popV",             { RMrBP } },
1758   { "popV",             { RMrSI } },
1759   { "popV",             { RMrDI } },
1760   /* 60 */
1761   { X86_64_TABLE (X86_64_60) },
1762   { X86_64_TABLE (X86_64_61) },
1763   { X86_64_TABLE (X86_64_62) },
1764   { X86_64_TABLE (X86_64_63) },
1765   { Bad_Opcode },       /* seg fs */
1766   { Bad_Opcode },       /* seg gs */
1767   { Bad_Opcode },       /* op size prefix */
1768   { Bad_Opcode },       /* adr size prefix */
1769   /* 68 */
1770   { "pushT",            { Iq } },
1771   { "imulS",            { Gv, Ev, Iv } },
1772   { "pushT",            { sIb } },
1773   { "imulS",            { Gv, Ev, sIb } },
1774   { "ins{b|}",          { Ybr, indirDX } },
1775   { X86_64_TABLE (X86_64_6D) },
1776   { "outs{b|}",         { indirDXr, Xb } },
1777   { X86_64_TABLE (X86_64_6F) },
1778   /* 70 */
1779   { "joH",              { Jb, XX, cond_jump_flag } },
1780   { "jnoH",             { Jb, XX, cond_jump_flag } },
1781   { "jbH",              { Jb, XX, cond_jump_flag } },
1782   { "jaeH",             { Jb, XX, cond_jump_flag } },
1783   { "jeH",              { Jb, XX, cond_jump_flag } },
1784   { "jneH",             { Jb, XX, cond_jump_flag } },
1785   { "jbeH",             { Jb, XX, cond_jump_flag } },
1786   { "jaH",              { Jb, XX, cond_jump_flag } },
1787   /* 78 */
1788   { "jsH",              { Jb, XX, cond_jump_flag } },
1789   { "jnsH",             { Jb, XX, cond_jump_flag } },
1790   { "jpH",              { Jb, XX, cond_jump_flag } },
1791   { "jnpH",             { Jb, XX, cond_jump_flag } },
1792   { "jlH",              { Jb, XX, cond_jump_flag } },
1793   { "jgeH",             { Jb, XX, cond_jump_flag } },
1794   { "jleH",             { Jb, XX, cond_jump_flag } },
1795   { "jgH",              { Jb, XX, cond_jump_flag } },
1796   /* 80 */
1797   { REG_TABLE (REG_80) },
1798   { REG_TABLE (REG_81) },
1799   { Bad_Opcode },
1800   { REG_TABLE (REG_82) },
1801   { "testB",            { Eb, Gb } },
1802   { "testS",            { Ev, Gv } },
1803   { "xchgB",            { Eb, Gb } },
1804   { "xchgS",            { Ev, Gv } },
1805   /* 88 */
1806   { "movB",             { Eb, Gb } },
1807   { "movS",             { Ev, Gv } },
1808   { "movB",             { Gb, EbS } },
1809   { "movS",             { Gv, EvS } },
1810   { "movD",             { Sv, Sw } },
1811   { MOD_TABLE (MOD_8D) },
1812   { "movD",             { Sw, Sv } },
1813   { REG_TABLE (REG_8F) },
1814   /* 90 */
1815   { PREFIX_TABLE (PREFIX_90) },
1816   { "xchgS",            { RMeCX, eAX } },
1817   { "xchgS",            { RMeDX, eAX } },
1818   { "xchgS",            { RMeBX, eAX } },
1819   { "xchgS",            { RMeSP, eAX } },
1820   { "xchgS",            { RMeBP, eAX } },
1821   { "xchgS",            { RMeSI, eAX } },
1822   { "xchgS",            { RMeDI, eAX } },
1823   /* 98 */
1824   { "cW{t|}R",          { XX } },
1825   { "cR{t|}O",          { XX } },
1826   { X86_64_TABLE (X86_64_9A) },
1827   { Bad_Opcode },       /* fwait */
1828   { "pushfT",           { XX } },
1829   { "popfT",            { XX } },
1830   { "sahf",             { XX } },
1831   { "lahf",             { XX } },
1832   /* a0 */
1833   { "mov%LB",           { AL, Ob } },
1834   { "mov%LS",           { eAX, Ov } },
1835   { "mov%LB",           { Ob, AL } },
1836   { "mov%LS",           { Ov, eAX } },
1837   { "movs{b|}",         { Ybr, Xb } },
1838   { "movs{R|}",         { Yvr, Xv } },
1839   { "cmps{b|}",         { Xb, Yb } },
1840   { "cmps{R|}",         { Xv, Yv } },
1841   /* a8 */
1842   { "testB",            { AL, Ib } },
1843   { "testS",            { eAX, Iv } },
1844   { "stosB",            { Ybr, AL } },
1845   { "stosS",            { Yvr, eAX } },
1846   { "lodsB",            { ALr, Xb } },
1847   { "lodsS",            { eAXr, Xv } },
1848   { "scasB",            { AL, Yb } },
1849   { "scasS",            { eAX, Yv } },
1850   /* b0 */
1851   { "movB",             { RMAL, Ib } },
1852   { "movB",             { RMCL, Ib } },
1853   { "movB",             { RMDL, Ib } },
1854   { "movB",             { RMBL, Ib } },
1855   { "movB",             { RMAH, Ib } },
1856   { "movB",             { RMCH, Ib } },
1857   { "movB",             { RMDH, Ib } },
1858   { "movB",             { RMBH, Ib } },
1859   /* b8 */
1860   { "mov%LV",           { RMeAX, Iv64 } },
1861   { "mov%LV",           { RMeCX, Iv64 } },
1862   { "mov%LV",           { RMeDX, Iv64 } },
1863   { "mov%LV",           { RMeBX, Iv64 } },
1864   { "mov%LV",           { RMeSP, Iv64 } },
1865   { "mov%LV",           { RMeBP, Iv64 } },
1866   { "mov%LV",           { RMeSI, Iv64 } },
1867   { "mov%LV",           { RMeDI, Iv64 } },
1868   /* c0 */
1869   { REG_TABLE (REG_C0) },
1870   { REG_TABLE (REG_C1) },
1871   { "retT",             { Iw } },
1872   { "retT",             { XX } },
1873   { X86_64_TABLE (X86_64_C4) },
1874   { X86_64_TABLE (X86_64_C5) },
1875   { REG_TABLE (REG_C6) },
1876   { REG_TABLE (REG_C7) },
1877   /* c8 */
1878   { "enterT",           { Iw, Ib } },
1879   { "leaveT",           { XX } },
1880   { "Jret{|f}P",        { Iw } },
1881   { "Jret{|f}P",        { XX } },
1882   { "int3",             { XX } },
1883   { "int",              { Ib } },
1884   { X86_64_TABLE (X86_64_CE) },
1885   { "iretP",            { XX } },
1886   /* d0 */
1887   { REG_TABLE (REG_D0) },
1888   { REG_TABLE (REG_D1) },
1889   { REG_TABLE (REG_D2) },
1890   { REG_TABLE (REG_D3) },
1891   { X86_64_TABLE (X86_64_D4) },
1892   { X86_64_TABLE (X86_64_D5) },
1893   { Bad_Opcode },
1894   { "xlat",             { DSBX } },
1895   /* d8 */
1896   { FLOAT },
1897   { FLOAT },
1898   { FLOAT },
1899   { FLOAT },
1900   { FLOAT },
1901   { FLOAT },
1902   { FLOAT },
1903   { FLOAT },
1904   /* e0 */
1905   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1906   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1907   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1908   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1909   { "inB",              { AL, Ib } },
1910   { "inG",              { zAX, Ib } },
1911   { "outB",             { Ib, AL } },
1912   { "outG",             { Ib, zAX } },
1913   /* e8 */
1914   { "callT",            { Jv } },
1915   { "jmpT",             { Jv } },
1916   { X86_64_TABLE (X86_64_EA) },
1917   { "jmp",              { Jb } },
1918   { "inB",              { AL, indirDX } },
1919   { "inG",              { zAX, indirDX } },
1920   { "outB",             { indirDX, AL } },
1921   { "outG",             { indirDX, zAX } },
1922   /* f0 */
1923   { Bad_Opcode },       /* lock prefix */
1924   { "icebp",            { XX } },
1925   { Bad_Opcode },       /* repne */
1926   { Bad_Opcode },       /* repz */
1927   { "hlt",              { XX } },
1928   { "cmc",              { XX } },
1929   { REG_TABLE (REG_F6) },
1930   { REG_TABLE (REG_F7) },
1931   /* f8 */
1932   { "clc",              { XX } },
1933   { "stc",              { XX } },
1934   { "cli",              { XX } },
1935   { "sti",              { XX } },
1936   { "cld",              { XX } },
1937   { "std",              { XX } },
1938   { REG_TABLE (REG_FE) },
1939   { REG_TABLE (REG_FF) },
1940 };
1941
1942 static const struct dis386 dis386_twobyte[] = {
1943   /* 00 */
1944   { REG_TABLE (REG_0F00 ) },
1945   { REG_TABLE (REG_0F01 ) },
1946   { "larS",             { Gv, Ew } },
1947   { "lslS",             { Gv, Ew } },
1948   { Bad_Opcode },
1949   { "syscall",          { XX } },
1950   { "clts",             { XX } },
1951   { "sysretP",          { XX } },
1952   /* 08 */
1953   { "invd",             { XX } },
1954   { "wbinvd",           { XX } },
1955   { Bad_Opcode },
1956   { "ud2a",             { XX } },
1957   { Bad_Opcode },
1958   { REG_TABLE (REG_0F0D) },
1959   { "femms",            { XX } },
1960   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1961   /* 10 */
1962   { PREFIX_TABLE (PREFIX_0F10) },
1963   { PREFIX_TABLE (PREFIX_0F11) },
1964   { PREFIX_TABLE (PREFIX_0F12) },
1965   { MOD_TABLE (MOD_0F13) },
1966   { "unpcklpX",         { XM, EXx } },
1967   { "unpckhpX",         { XM, EXx } },
1968   { PREFIX_TABLE (PREFIX_0F16) },
1969   { MOD_TABLE (MOD_0F17) },
1970   /* 18 */
1971   { REG_TABLE (REG_0F18) },
1972   { "nopQ",             { Ev } },
1973   { "nopQ",             { Ev } },
1974   { "nopQ",             { Ev } },
1975   { "nopQ",             { Ev } },
1976   { "nopQ",             { Ev } },
1977   { "nopQ",             { Ev } },
1978   { "nopQ",             { Ev } },
1979   /* 20 */
1980   { MOD_TABLE (MOD_0F20) },
1981   { MOD_TABLE (MOD_0F21) },
1982   { MOD_TABLE (MOD_0F22) },
1983   { MOD_TABLE (MOD_0F23) },
1984   { MOD_TABLE (MOD_0F24) },
1985   { Bad_Opcode },
1986   { MOD_TABLE (MOD_0F26) },
1987   { Bad_Opcode },
1988   /* 28 */
1989   { "movapX",           { XM, EXx } },
1990   { "movapX",           { EXxS, XM } },
1991   { PREFIX_TABLE (PREFIX_0F2A) },
1992   { PREFIX_TABLE (PREFIX_0F2B) },
1993   { PREFIX_TABLE (PREFIX_0F2C) },
1994   { PREFIX_TABLE (PREFIX_0F2D) },
1995   { PREFIX_TABLE (PREFIX_0F2E) },
1996   { PREFIX_TABLE (PREFIX_0F2F) },
1997   /* 30 */
1998   { "wrmsr",            { XX } },
1999   { "rdtsc",            { XX } },
2000   { "rdmsr",            { XX } },
2001   { "rdpmc",            { XX } },
2002   { "sysenter",         { XX } },
2003   { "sysexit",          { XX } },
2004   { Bad_Opcode },
2005   { "getsec",           { XX } },
2006   /* 38 */
2007   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2008   { Bad_Opcode },
2009   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2010   { Bad_Opcode },
2011   { Bad_Opcode },
2012   { Bad_Opcode },
2013   { Bad_Opcode },
2014   { Bad_Opcode },
2015   /* 40 */
2016   { "cmovoS",           { Gv, Ev } },
2017   { "cmovnoS",          { Gv, Ev } },
2018   { "cmovbS",           { Gv, Ev } },
2019   { "cmovaeS",          { Gv, Ev } },
2020   { "cmoveS",           { Gv, Ev } },
2021   { "cmovneS",          { Gv, Ev } },
2022   { "cmovbeS",          { Gv, Ev } },
2023   { "cmovaS",           { Gv, Ev } },
2024   /* 48 */
2025   { "cmovsS",           { Gv, Ev } },
2026   { "cmovnsS",          { Gv, Ev } },
2027   { "cmovpS",           { Gv, Ev } },
2028   { "cmovnpS",          { Gv, Ev } },
2029   { "cmovlS",           { Gv, Ev } },
2030   { "cmovgeS",          { Gv, Ev } },
2031   { "cmovleS",          { Gv, Ev } },
2032   { "cmovgS",           { Gv, Ev } },
2033   /* 50 */
2034   { MOD_TABLE (MOD_0F51) },
2035   { PREFIX_TABLE (PREFIX_0F51) },
2036   { PREFIX_TABLE (PREFIX_0F52) },
2037   { PREFIX_TABLE (PREFIX_0F53) },
2038   { "andpX",            { XM, EXx } },
2039   { "andnpX",           { XM, EXx } },
2040   { "orpX",             { XM, EXx } },
2041   { "xorpX",            { XM, EXx } },
2042   /* 58 */
2043   { PREFIX_TABLE (PREFIX_0F58) },
2044   { PREFIX_TABLE (PREFIX_0F59) },
2045   { PREFIX_TABLE (PREFIX_0F5A) },
2046   { PREFIX_TABLE (PREFIX_0F5B) },
2047   { PREFIX_TABLE (PREFIX_0F5C) },
2048   { PREFIX_TABLE (PREFIX_0F5D) },
2049   { PREFIX_TABLE (PREFIX_0F5E) },
2050   { PREFIX_TABLE (PREFIX_0F5F) },
2051   /* 60 */
2052   { PREFIX_TABLE (PREFIX_0F60) },
2053   { PREFIX_TABLE (PREFIX_0F61) },
2054   { PREFIX_TABLE (PREFIX_0F62) },
2055   { "packsswb",         { MX, EM } },
2056   { "pcmpgtb",          { MX, EM } },
2057   { "pcmpgtw",          { MX, EM } },
2058   { "pcmpgtd",          { MX, EM } },
2059   { "packuswb",         { MX, EM } },
2060   /* 68 */
2061   { "punpckhbw",        { MX, EM } },
2062   { "punpckhwd",        { MX, EM } },
2063   { "punpckhdq",        { MX, EM } },
2064   { "packssdw",         { MX, EM } },
2065   { PREFIX_TABLE (PREFIX_0F6C) },
2066   { PREFIX_TABLE (PREFIX_0F6D) },
2067   { "movK",             { MX, Edq } },
2068   { PREFIX_TABLE (PREFIX_0F6F) },
2069   /* 70 */
2070   { PREFIX_TABLE (PREFIX_0F70) },
2071   { REG_TABLE (REG_0F71) },
2072   { REG_TABLE (REG_0F72) },
2073   { REG_TABLE (REG_0F73) },
2074   { "pcmpeqb",          { MX, EM } },
2075   { "pcmpeqw",          { MX, EM } },
2076   { "pcmpeqd",          { MX, EM } },
2077   { "emms",             { XX } },
2078   /* 78 */
2079   { PREFIX_TABLE (PREFIX_0F78) },
2080   { PREFIX_TABLE (PREFIX_0F79) },
2081   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2082   { Bad_Opcode },
2083   { PREFIX_TABLE (PREFIX_0F7C) },
2084   { PREFIX_TABLE (PREFIX_0F7D) },
2085   { PREFIX_TABLE (PREFIX_0F7E) },
2086   { PREFIX_TABLE (PREFIX_0F7F) },
2087   /* 80 */
2088   { "joH",              { Jv, XX, cond_jump_flag } },
2089   { "jnoH",             { Jv, XX, cond_jump_flag } },
2090   { "jbH",              { Jv, XX, cond_jump_flag } },
2091   { "jaeH",             { Jv, XX, cond_jump_flag } },
2092   { "jeH",              { Jv, XX, cond_jump_flag } },
2093   { "jneH",             { Jv, XX, cond_jump_flag } },
2094   { "jbeH",             { Jv, XX, cond_jump_flag } },
2095   { "jaH",              { Jv, XX, cond_jump_flag } },
2096   /* 88 */
2097   { "jsH",              { Jv, XX, cond_jump_flag } },
2098   { "jnsH",             { Jv, XX, cond_jump_flag } },
2099   { "jpH",              { Jv, XX, cond_jump_flag } },
2100   { "jnpH",             { Jv, XX, cond_jump_flag } },
2101   { "jlH",              { Jv, XX, cond_jump_flag } },
2102   { "jgeH",             { Jv, XX, cond_jump_flag } },
2103   { "jleH",             { Jv, XX, cond_jump_flag } },
2104   { "jgH",              { Jv, XX, cond_jump_flag } },
2105   /* 90 */
2106   { "seto",             { Eb } },
2107   { "setno",            { Eb } },
2108   { "setb",             { Eb } },
2109   { "setae",            { Eb } },
2110   { "sete",             { Eb } },
2111   { "setne",            { Eb } },
2112   { "setbe",            { Eb } },
2113   { "seta",             { Eb } },
2114   /* 98 */
2115   { "sets",             { Eb } },
2116   { "setns",            { Eb } },
2117   { "setp",             { Eb } },
2118   { "setnp",            { Eb } },
2119   { "setl",             { Eb } },
2120   { "setge",            { Eb } },
2121   { "setle",            { Eb } },
2122   { "setg",             { Eb } },
2123   /* a0 */
2124   { "pushT",            { fs } },
2125   { "popT",             { fs } },
2126   { "cpuid",            { XX } },
2127   { "btS",              { Ev, Gv } },
2128   { "shldS",            { Ev, Gv, Ib } },
2129   { "shldS",            { Ev, Gv, CL } },
2130   { REG_TABLE (REG_0FA6) },
2131   { REG_TABLE (REG_0FA7) },
2132   /* a8 */
2133   { "pushT",            { gs } },
2134   { "popT",             { gs } },
2135   { "rsm",              { XX } },
2136   { "btsS",             { Ev, Gv } },
2137   { "shrdS",            { Ev, Gv, Ib } },
2138   { "shrdS",            { Ev, Gv, CL } },
2139   { REG_TABLE (REG_0FAE) },
2140   { "imulS",            { Gv, Ev } },
2141   /* b0 */
2142   { "cmpxchgB",         { Eb, Gb } },
2143   { "cmpxchgS",         { Ev, Gv } },
2144   { MOD_TABLE (MOD_0FB2) },
2145   { "btrS",             { Ev, Gv } },
2146   { MOD_TABLE (MOD_0FB4) },
2147   { MOD_TABLE (MOD_0FB5) },
2148   { "movz{bR|x}",       { Gv, Eb } },
2149   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2150   /* b8 */
2151   { PREFIX_TABLE (PREFIX_0FB8) },
2152   { "ud2b",             { XX } },
2153   { REG_TABLE (REG_0FBA) },
2154   { "btcS",             { Ev, Gv } },
2155   { "bsfS",             { Gv, Ev } },
2156   { PREFIX_TABLE (PREFIX_0FBD) },
2157   { "movs{bR|x}",       { Gv, Eb } },
2158   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2159   /* c0 */
2160   { "xaddB",            { Eb, Gb } },
2161   { "xaddS",            { Ev, Gv } },
2162   { PREFIX_TABLE (PREFIX_0FC2) },
2163   { PREFIX_TABLE (PREFIX_0FC3) },
2164   { "pinsrw",           { MX, Edqw, Ib } },
2165   { "pextrw",           { Gdq, MS, Ib } },
2166   { "shufpX",           { XM, EXx, Ib } },
2167   { REG_TABLE (REG_0FC7) },
2168   /* c8 */
2169   { "bswap",            { RMeAX } },
2170   { "bswap",            { RMeCX } },
2171   { "bswap",            { RMeDX } },
2172   { "bswap",            { RMeBX } },
2173   { "bswap",            { RMeSP } },
2174   { "bswap",            { RMeBP } },
2175   { "bswap",            { RMeSI } },
2176   { "bswap",            { RMeDI } },
2177   /* d0 */
2178   { PREFIX_TABLE (PREFIX_0FD0) },
2179   { "psrlw",            { MX, EM } },
2180   { "psrld",            { MX, EM } },
2181   { "psrlq",            { MX, EM } },
2182   { "paddq",            { MX, EM } },
2183   { "pmullw",           { MX, EM } },
2184   { PREFIX_TABLE (PREFIX_0FD6) },
2185   { MOD_TABLE (MOD_0FD7) },
2186   /* d8 */
2187   { "psubusb",          { MX, EM } },
2188   { "psubusw",          { MX, EM } },
2189   { "pminub",           { MX, EM } },
2190   { "pand",             { MX, EM } },
2191   { "paddusb",          { MX, EM } },
2192   { "paddusw",          { MX, EM } },
2193   { "pmaxub",           { MX, EM } },
2194   { "pandn",            { MX, EM } },
2195   /* e0 */
2196   { "pavgb",            { MX, EM } },
2197   { "psraw",            { MX, EM } },
2198   { "psrad",            { MX, EM } },
2199   { "pavgw",            { MX, EM } },
2200   { "pmulhuw",          { MX, EM } },
2201   { "pmulhw",           { MX, EM } },
2202   { PREFIX_TABLE (PREFIX_0FE6) },
2203   { PREFIX_TABLE (PREFIX_0FE7) },
2204   /* e8 */
2205   { "psubsb",           { MX, EM } },
2206   { "psubsw",           { MX, EM } },
2207   { "pminsw",           { MX, EM } },
2208   { "por",              { MX, EM } },
2209   { "paddsb",           { MX, EM } },
2210   { "paddsw",           { MX, EM } },
2211   { "pmaxsw",           { MX, EM } },
2212   { "pxor",             { MX, EM } },
2213   /* f0 */
2214   { PREFIX_TABLE (PREFIX_0FF0) },
2215   { "psllw",            { MX, EM } },
2216   { "pslld",            { MX, EM } },
2217   { "psllq",            { MX, EM } },
2218   { "pmuludq",          { MX, EM } },
2219   { "pmaddwd",          { MX, EM } },
2220   { "psadbw",           { MX, EM } },
2221   { PREFIX_TABLE (PREFIX_0FF7) },
2222   /* f8 */
2223   { "psubb",            { MX, EM } },
2224   { "psubw",            { MX, EM } },
2225   { "psubd",            { MX, EM } },
2226   { "psubq",            { MX, EM } },
2227   { "paddb",            { MX, EM } },
2228   { "paddw",            { MX, EM } },
2229   { "paddd",            { MX, EM } },
2230   { Bad_Opcode },
2231 };
2232
2233 static const unsigned char onebyte_has_modrm[256] = {
2234   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2235   /*       -------------------------------        */
2236   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2237   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2238   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2239   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2240   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2241   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2242   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2243   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2244   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2245   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2246   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2247   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2248   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2249   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2250   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2251   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2252   /*       -------------------------------        */
2253   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2254 };
2255
2256 static const unsigned char twobyte_has_modrm[256] = {
2257   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2258   /*       -------------------------------        */
2259   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2260   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2261   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2262   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2263   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2264   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2265   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2266   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2267   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2268   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2269   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2270   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2271   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2272   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2273   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2274   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2275   /*       -------------------------------        */
2276   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2277 };
2278
2279 static char obuf[100];
2280 static char *obufp;
2281 static char *mnemonicendp;
2282 static char scratchbuf[100];
2283 static unsigned char *start_codep;
2284 static unsigned char *insn_codep;
2285 static unsigned char *codep;
2286 static int last_lock_prefix;
2287 static int last_repz_prefix;
2288 static int last_repnz_prefix;
2289 static int last_data_prefix;
2290 static int last_addr_prefix;
2291 static int last_rex_prefix;
2292 static int last_seg_prefix;
2293 #define MAX_CODE_LENGTH 15
2294 /* We can up to 14 prefixes since the maximum instruction length is
2295    15bytes.  */
2296 static int all_prefixes[MAX_CODE_LENGTH - 1];
2297 static disassemble_info *the_info;
2298 static struct
2299   {
2300     int mod;
2301     int reg;
2302     int rm;
2303   }
2304 modrm;
2305 static unsigned char need_modrm;
2306 static struct
2307   {
2308     int register_specifier;
2309     int length;
2310     int prefix;
2311     int w;
2312   }
2313 vex;
2314 static unsigned char need_vex;
2315 static unsigned char need_vex_reg;
2316 static unsigned char vex_w_done;
2317
2318 struct op
2319   {
2320     const char *name;
2321     unsigned int len;
2322   };
2323
2324 /* If we are accessing mod/rm/reg without need_modrm set, then the
2325    values are stale.  Hitting this abort likely indicates that you
2326    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2327 #define MODRM_CHECK  if (!need_modrm) abort ()
2328
2329 static const char **names64;
2330 static const char **names32;
2331 static const char **names16;
2332 static const char **names8;
2333 static const char **names8rex;
2334 static const char **names_seg;
2335 static const char *index64;
2336 static const char *index32;
2337 static const char **index16;
2338
2339 static const char *intel_names64[] = {
2340   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2341   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2342 };
2343 static const char *intel_names32[] = {
2344   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2345   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2346 };
2347 static const char *intel_names16[] = {
2348   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2349   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2350 };
2351 static const char *intel_names8[] = {
2352   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2353 };
2354 static const char *intel_names8rex[] = {
2355   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2356   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2357 };
2358 static const char *intel_names_seg[] = {
2359   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2360 };
2361 static const char *intel_index64 = "riz";
2362 static const char *intel_index32 = "eiz";
2363 static const char *intel_index16[] = {
2364   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2365 };
2366
2367 static const char *att_names64[] = {
2368   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2369   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2370 };
2371 static const char *att_names32[] = {
2372   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2373   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2374 };
2375 static const char *att_names16[] = {
2376   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2377   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2378 };
2379 static const char *att_names8[] = {
2380   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2381 };
2382 static const char *att_names8rex[] = {
2383   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2384   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2385 };
2386 static const char *att_names_seg[] = {
2387   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2388 };
2389 static const char *att_index64 = "%riz";
2390 static const char *att_index32 = "%eiz";
2391 static const char *att_index16[] = {
2392   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2393 };
2394
2395 static const char **names_mm;
2396 static const char *intel_names_mm[] = {
2397   "mm0", "mm1", "mm2", "mm3",
2398   "mm4", "mm5", "mm6", "mm7"
2399 };
2400 static const char *att_names_mm[] = {
2401   "%mm0", "%mm1", "%mm2", "%mm3",
2402   "%mm4", "%mm5", "%mm6", "%mm7"
2403 };
2404
2405 static const char **names_xmm;
2406 static const char *intel_names_xmm[] = {
2407   "xmm0", "xmm1", "xmm2", "xmm3",
2408   "xmm4", "xmm5", "xmm6", "xmm7",
2409   "xmm8", "xmm9", "xmm10", "xmm11",
2410   "xmm12", "xmm13", "xmm14", "xmm15"
2411 };
2412 static const char *att_names_xmm[] = {
2413   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2414   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2415   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2416   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2417 };
2418
2419 static const char **names_ymm;
2420 static const char *intel_names_ymm[] = {
2421   "ymm0", "ymm1", "ymm2", "ymm3",
2422   "ymm4", "ymm5", "ymm6", "ymm7",
2423   "ymm8", "ymm9", "ymm10", "ymm11",
2424   "ymm12", "ymm13", "ymm14", "ymm15"
2425 };
2426 static const char *att_names_ymm[] = {
2427   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2428   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2429   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2430   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2431 };
2432
2433 static const struct dis386 reg_table[][8] = {
2434   /* REG_80 */
2435   {
2436     { "addA",   { Eb, Ib } },
2437     { "orA",    { Eb, Ib } },
2438     { "adcA",   { Eb, Ib } },
2439     { "sbbA",   { Eb, Ib } },
2440     { "andA",   { Eb, Ib } },
2441     { "subA",   { Eb, Ib } },
2442     { "xorA",   { Eb, Ib } },
2443     { "cmpA",   { Eb, Ib } },
2444   },
2445   /* REG_81 */
2446   {
2447     { "addQ",   { Ev, Iv } },
2448     { "orQ",    { Ev, Iv } },
2449     { "adcQ",   { Ev, Iv } },
2450     { "sbbQ",   { Ev, Iv } },
2451     { "andQ",   { Ev, Iv } },
2452     { "subQ",   { Ev, Iv } },
2453     { "xorQ",   { Ev, Iv } },
2454     { "cmpQ",   { Ev, Iv } },
2455   },
2456   /* REG_82 */
2457   {
2458     { "addQ",   { Ev, sIb } },
2459     { "orQ",    { Ev, sIb } },
2460     { "adcQ",   { Ev, sIb } },
2461     { "sbbQ",   { Ev, sIb } },
2462     { "andQ",   { Ev, sIb } },
2463     { "subQ",   { Ev, sIb } },
2464     { "xorQ",   { Ev, sIb } },
2465     { "cmpQ",   { Ev, sIb } },
2466   },
2467   /* REG_8F */
2468   {
2469     { "popU",   { stackEv } },
2470     { XOP_8F_TABLE (XOP_09) },
2471     { Bad_Opcode },
2472     { Bad_Opcode },
2473     { Bad_Opcode },
2474     { XOP_8F_TABLE (XOP_09) },
2475   },
2476   /* REG_C0 */
2477   {
2478     { "rolA",   { Eb, Ib } },
2479     { "rorA",   { Eb, Ib } },
2480     { "rclA",   { Eb, Ib } },
2481     { "rcrA",   { Eb, Ib } },
2482     { "shlA",   { Eb, Ib } },
2483     { "shrA",   { Eb, Ib } },
2484     { Bad_Opcode },
2485     { "sarA",   { Eb, Ib } },
2486   },
2487   /* REG_C1 */
2488   {
2489     { "rolQ",   { Ev, Ib } },
2490     { "rorQ",   { Ev, Ib } },
2491     { "rclQ",   { Ev, Ib } },
2492     { "rcrQ",   { Ev, Ib } },
2493     { "shlQ",   { Ev, Ib } },
2494     { "shrQ",   { Ev, Ib } },
2495     { Bad_Opcode },
2496     { "sarQ",   { Ev, Ib } },
2497   },
2498   /* REG_C6 */
2499   {
2500     { "movA",   { Eb, Ib } },
2501   },
2502   /* REG_C7 */
2503   {
2504     { "movQ",   { Ev, Iv } },
2505   },
2506   /* REG_D0 */
2507   {
2508     { "rolA",   { Eb, I1 } },
2509     { "rorA",   { Eb, I1 } },
2510     { "rclA",   { Eb, I1 } },
2511     { "rcrA",   { Eb, I1 } },
2512     { "shlA",   { Eb, I1 } },
2513     { "shrA",   { Eb, I1 } },
2514     { Bad_Opcode },
2515     { "sarA",   { Eb, I1 } },
2516   },
2517   /* REG_D1 */
2518   {
2519     { "rolQ",   { Ev, I1 } },
2520     { "rorQ",   { Ev, I1 } },
2521     { "rclQ",   { Ev, I1 } },
2522     { "rcrQ",   { Ev, I1 } },
2523     { "shlQ",   { Ev, I1 } },
2524     { "shrQ",   { Ev, I1 } },
2525     { Bad_Opcode },
2526     { "sarQ",   { Ev, I1 } },
2527   },
2528   /* REG_D2 */
2529   {
2530     { "rolA",   { Eb, CL } },
2531     { "rorA",   { Eb, CL } },
2532     { "rclA",   { Eb, CL } },
2533     { "rcrA",   { Eb, CL } },
2534     { "shlA",   { Eb, CL } },
2535     { "shrA",   { Eb, CL } },
2536     { Bad_Opcode },
2537     { "sarA",   { Eb, CL } },
2538   },
2539   /* REG_D3 */
2540   {
2541     { "rolQ",   { Ev, CL } },
2542     { "rorQ",   { Ev, CL } },
2543     { "rclQ",   { Ev, CL } },
2544     { "rcrQ",   { Ev, CL } },
2545     { "shlQ",   { Ev, CL } },
2546     { "shrQ",   { Ev, CL } },
2547     { Bad_Opcode },
2548     { "sarQ",   { Ev, CL } },
2549   },
2550   /* REG_F6 */
2551   {
2552     { "testA",  { Eb, Ib } },
2553     { Bad_Opcode },
2554     { "notA",   { Eb } },
2555     { "negA",   { Eb } },
2556     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2557     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2558     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2559     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2560   },
2561   /* REG_F7 */
2562   {
2563     { "testQ",  { Ev, Iv } },
2564     { Bad_Opcode },
2565     { "notQ",   { Ev } },
2566     { "negQ",   { Ev } },
2567     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2568     { "imulQ",  { Ev } },
2569     { "divQ",   { Ev } },
2570     { "idivQ",  { Ev } },
2571   },
2572   /* REG_FE */
2573   {
2574     { "incA",   { Eb } },
2575     { "decA",   { Eb } },
2576   },
2577   /* REG_FF */
2578   {
2579     { "incQ",   { Ev } },
2580     { "decQ",   { Ev } },
2581     { "callT",  { indirEv } },
2582     { "JcallT", { indirEp } },
2583     { "jmpT",   { indirEv } },
2584     { "JjmpT",  { indirEp } },
2585     { "pushU",  { stackEv } },
2586     { Bad_Opcode },
2587   },
2588   /* REG_0F00 */
2589   {
2590     { "sldtD",  { Sv } },
2591     { "strD",   { Sv } },
2592     { "lldt",   { Ew } },
2593     { "ltr",    { Ew } },
2594     { "verr",   { Ew } },
2595     { "verw",   { Ew } },
2596     { Bad_Opcode },
2597     { Bad_Opcode },
2598   },
2599   /* REG_0F01 */
2600   {
2601     { MOD_TABLE (MOD_0F01_REG_0) },
2602     { MOD_TABLE (MOD_0F01_REG_1) },
2603     { MOD_TABLE (MOD_0F01_REG_2) },
2604     { MOD_TABLE (MOD_0F01_REG_3) },
2605     { "smswD",  { Sv } },
2606     { Bad_Opcode },
2607     { "lmsw",   { Ew } },
2608     { MOD_TABLE (MOD_0F01_REG_7) },
2609   },
2610   /* REG_0F0D */
2611   {
2612     { "prefetch",       { Eb } },
2613     { "prefetchw",      { Eb } },
2614   },
2615   /* REG_0F18 */
2616   {
2617     { MOD_TABLE (MOD_0F18_REG_0) },
2618     { MOD_TABLE (MOD_0F18_REG_1) },
2619     { MOD_TABLE (MOD_0F18_REG_2) },
2620     { MOD_TABLE (MOD_0F18_REG_3) },
2621   },
2622   /* REG_0F71 */
2623   {
2624     { Bad_Opcode },
2625     { Bad_Opcode },
2626     { MOD_TABLE (MOD_0F71_REG_2) },
2627     { Bad_Opcode },
2628     { MOD_TABLE (MOD_0F71_REG_4) },
2629     { Bad_Opcode },
2630     { MOD_TABLE (MOD_0F71_REG_6) },
2631   },
2632   /* REG_0F72 */
2633   {
2634     { Bad_Opcode },
2635     { Bad_Opcode },
2636     { MOD_TABLE (MOD_0F72_REG_2) },
2637     { Bad_Opcode },
2638     { MOD_TABLE (MOD_0F72_REG_4) },
2639     { Bad_Opcode },
2640     { MOD_TABLE (MOD_0F72_REG_6) },
2641   },
2642   /* REG_0F73 */
2643   {
2644     { Bad_Opcode },
2645     { Bad_Opcode },
2646     { MOD_TABLE (MOD_0F73_REG_2) },
2647     { MOD_TABLE (MOD_0F73_REG_3) },
2648     { Bad_Opcode },
2649     { Bad_Opcode },
2650     { MOD_TABLE (MOD_0F73_REG_6) },
2651     { MOD_TABLE (MOD_0F73_REG_7) },
2652   },
2653   /* REG_0FA6 */
2654   {
2655     { "montmul",        { { OP_0f07, 0 } } },
2656     { "xsha1",          { { OP_0f07, 0 } } },
2657     { "xsha256",        { { OP_0f07, 0 } } },
2658   },
2659   /* REG_0FA7 */
2660   {
2661     { "xstore-rng",     { { OP_0f07, 0 } } },
2662     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2663     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2664     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2665     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2666     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2667   },
2668   /* REG_0FAE */
2669   {
2670     { MOD_TABLE (MOD_0FAE_REG_0) },
2671     { MOD_TABLE (MOD_0FAE_REG_1) },
2672     { MOD_TABLE (MOD_0FAE_REG_2) },
2673     { MOD_TABLE (MOD_0FAE_REG_3) },
2674     { MOD_TABLE (MOD_0FAE_REG_4) },
2675     { MOD_TABLE (MOD_0FAE_REG_5) },
2676     { MOD_TABLE (MOD_0FAE_REG_6) },
2677     { MOD_TABLE (MOD_0FAE_REG_7) },
2678   },
2679   /* REG_0FBA */
2680   {
2681     { Bad_Opcode },
2682     { Bad_Opcode },
2683     { Bad_Opcode },
2684     { Bad_Opcode },
2685     { "btQ",    { Ev, Ib } },
2686     { "btsQ",   { Ev, Ib } },
2687     { "btrQ",   { Ev, Ib } },
2688     { "btcQ",   { Ev, Ib } },
2689   },
2690   /* REG_0FC7 */
2691   {
2692     { Bad_Opcode },
2693     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2694     { Bad_Opcode },
2695     { Bad_Opcode },
2696     { Bad_Opcode },
2697     { Bad_Opcode },
2698     { MOD_TABLE (MOD_0FC7_REG_6) },
2699     { MOD_TABLE (MOD_0FC7_REG_7) },
2700   },
2701   /* REG_VEX_71 */
2702   {
2703     { Bad_Opcode },
2704     { Bad_Opcode },
2705     { MOD_TABLE (MOD_VEX_71_REG_2) },
2706     { Bad_Opcode },
2707     { MOD_TABLE (MOD_VEX_71_REG_4) },
2708     { Bad_Opcode },
2709     { MOD_TABLE (MOD_VEX_71_REG_6) },
2710   },
2711   /* REG_VEX_72 */
2712   {
2713     { Bad_Opcode },
2714     { Bad_Opcode },
2715     { MOD_TABLE (MOD_VEX_72_REG_2) },
2716     { Bad_Opcode },
2717     { MOD_TABLE (MOD_VEX_72_REG_4) },
2718     { Bad_Opcode },
2719     { MOD_TABLE (MOD_VEX_72_REG_6) },
2720   },
2721   /* REG_VEX_73 */
2722   {
2723     { Bad_Opcode },
2724     { Bad_Opcode },
2725     { MOD_TABLE (MOD_VEX_73_REG_2) },
2726     { MOD_TABLE (MOD_VEX_73_REG_3) },
2727     { Bad_Opcode },
2728     { Bad_Opcode },
2729     { MOD_TABLE (MOD_VEX_73_REG_6) },
2730     { MOD_TABLE (MOD_VEX_73_REG_7) },
2731   },
2732   /* REG_VEX_AE */
2733   {
2734     { Bad_Opcode },
2735     { Bad_Opcode },
2736     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2737     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2738   },
2739   /* REG_XOP_LWPCB */
2740   {
2741     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2742     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2743   },
2744   /* REG_XOP_LWP */
2745   {
2746     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2747     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2748   },
2749 };
2750
2751 static const struct dis386 prefix_table[][4] = {
2752   /* PREFIX_90 */
2753   {
2754     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2755     { "pause", { XX } },
2756     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2757   },
2758
2759   /* PREFIX_0F10 */
2760   {
2761     { "movups", { XM, EXx } },
2762     { "movss",  { XM, EXd } },
2763     { "movupd", { XM, EXx } },
2764     { "movsd",  { XM, EXq } },
2765   },
2766
2767   /* PREFIX_0F11 */
2768   {
2769     { "movups", { EXxS, XM } },
2770     { "movss",  { EXdS, XM } },
2771     { "movupd", { EXxS, XM } },
2772     { "movsd",  { EXqS, XM } },
2773   },
2774
2775   /* PREFIX_0F12 */
2776   {
2777     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2778     { "movsldup", { XM, EXx } },
2779     { "movlpd", { XM, EXq } },
2780     { "movddup", { XM, EXq } },
2781   },
2782
2783   /* PREFIX_0F16 */
2784   {
2785     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2786     { "movshdup", { XM, EXx } },
2787     { "movhpd", { XM, EXq } },
2788   },
2789
2790   /* PREFIX_0F2A */
2791   {
2792     { "cvtpi2ps", { XM, EMCq } },
2793     { "cvtsi2ss%LQ", { XM, Ev } },
2794     { "cvtpi2pd", { XM, EMCq } },
2795     { "cvtsi2sd%LQ", { XM, Ev } },
2796   },
2797
2798   /* PREFIX_0F2B */
2799   {
2800     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2801     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2802     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2803     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2804   },
2805
2806   /* PREFIX_0F2C */
2807   {
2808     { "cvttps2pi", { MXC, EXq } },
2809     { "cvttss2siY", { Gv, EXd } },
2810     { "cvttpd2pi", { MXC, EXx } },
2811     { "cvttsd2siY", { Gv, EXq } },
2812   },
2813
2814   /* PREFIX_0F2D */
2815   {
2816     { "cvtps2pi", { MXC, EXq } },
2817     { "cvtss2siY", { Gv, EXd } },
2818     { "cvtpd2pi", { MXC, EXx } },
2819     { "cvtsd2siY", { Gv, EXq } },
2820   },
2821
2822   /* PREFIX_0F2E */
2823   {
2824     { "ucomiss",{ XM, EXd } },
2825     { Bad_Opcode },
2826     { "ucomisd",{ XM, EXq } },
2827   },
2828
2829   /* PREFIX_0F2F */
2830   {
2831     { "comiss", { XM, EXd } },
2832     { Bad_Opcode },
2833     { "comisd", { XM, EXq } },
2834   },
2835
2836   /* PREFIX_0F51 */
2837   {
2838     { "sqrtps", { XM, EXx } },
2839     { "sqrtss", { XM, EXd } },
2840     { "sqrtpd", { XM, EXx } },
2841     { "sqrtsd", { XM, EXq } },
2842   },
2843
2844   /* PREFIX_0F52 */
2845   {
2846     { "rsqrtps",{ XM, EXx } },
2847     { "rsqrtss",{ XM, EXd } },
2848   },
2849
2850   /* PREFIX_0F53 */
2851   {
2852     { "rcpps",  { XM, EXx } },
2853     { "rcpss",  { XM, EXd } },
2854   },
2855
2856   /* PREFIX_0F58 */
2857   {
2858     { "addps", { XM, EXx } },
2859     { "addss", { XM, EXd } },
2860     { "addpd", { XM, EXx } },
2861     { "addsd", { XM, EXq } },
2862   },
2863
2864   /* PREFIX_0F59 */
2865   {
2866     { "mulps",  { XM, EXx } },
2867     { "mulss",  { XM, EXd } },
2868     { "mulpd",  { XM, EXx } },
2869     { "mulsd",  { XM, EXq } },
2870   },
2871
2872   /* PREFIX_0F5A */
2873   {
2874     { "cvtps2pd", { XM, EXq } },
2875     { "cvtss2sd", { XM, EXd } },
2876     { "cvtpd2ps", { XM, EXx } },
2877     { "cvtsd2ss", { XM, EXq } },
2878   },
2879
2880   /* PREFIX_0F5B */
2881   {
2882     { "cvtdq2ps", { XM, EXx } },
2883     { "cvttps2dq", { XM, EXx } },
2884     { "cvtps2dq", { XM, EXx } },
2885   },
2886
2887   /* PREFIX_0F5C */
2888   {
2889     { "subps",  { XM, EXx } },
2890     { "subss",  { XM, EXd } },
2891     { "subpd",  { XM, EXx } },
2892     { "subsd",  { XM, EXq } },
2893   },
2894
2895   /* PREFIX_0F5D */
2896   {
2897     { "minps",  { XM, EXx } },
2898     { "minss",  { XM, EXd } },
2899     { "minpd",  { XM, EXx } },
2900     { "minsd",  { XM, EXq } },
2901   },
2902
2903   /* PREFIX_0F5E */
2904   {
2905     { "divps",  { XM, EXx } },
2906     { "divss",  { XM, EXd } },
2907     { "divpd",  { XM, EXx } },
2908     { "divsd",  { XM, EXq } },
2909   },
2910
2911   /* PREFIX_0F5F */
2912   {
2913     { "maxps",  { XM, EXx } },
2914     { "maxss",  { XM, EXd } },
2915     { "maxpd",  { XM, EXx } },
2916     { "maxsd",  { XM, EXq } },
2917   },
2918
2919   /* PREFIX_0F60 */
2920   {
2921     { "punpcklbw",{ MX, EMd } },
2922     { Bad_Opcode },
2923     { "punpcklbw",{ MX, EMx } },
2924   },
2925
2926   /* PREFIX_0F61 */
2927   {
2928     { "punpcklwd",{ MX, EMd } },
2929     { Bad_Opcode },
2930     { "punpcklwd",{ MX, EMx } },
2931   },
2932
2933   /* PREFIX_0F62 */
2934   {
2935     { "punpckldq",{ MX, EMd } },
2936     { Bad_Opcode },
2937     { "punpckldq",{ MX, EMx } },
2938   },
2939
2940   /* PREFIX_0F6C */
2941   {
2942     { Bad_Opcode },
2943     { Bad_Opcode },
2944     { "punpcklqdq", { XM, EXx } },
2945   },
2946
2947   /* PREFIX_0F6D */
2948   {
2949     { Bad_Opcode },
2950     { Bad_Opcode },
2951     { "punpckhqdq", { XM, EXx } },
2952   },
2953
2954   /* PREFIX_0F6F */
2955   {
2956     { "movq",   { MX, EM } },
2957     { "movdqu", { XM, EXx } },
2958     { "movdqa", { XM, EXx } },
2959   },
2960
2961   /* PREFIX_0F70 */
2962   {
2963     { "pshufw", { MX, EM, Ib } },
2964     { "pshufhw",{ XM, EXx, Ib } },
2965     { "pshufd", { XM, EXx, Ib } },
2966     { "pshuflw",{ XM, EXx, Ib } },
2967   },
2968
2969   /* PREFIX_0F73_REG_3 */
2970   {
2971     { Bad_Opcode },
2972     { Bad_Opcode },
2973     { "psrldq", { XS, Ib } },
2974   },
2975
2976   /* PREFIX_0F73_REG_7 */
2977   {
2978     { Bad_Opcode },
2979     { Bad_Opcode },
2980     { "pslldq", { XS, Ib } },
2981   },
2982
2983   /* PREFIX_0F78 */
2984   {
2985     {"vmread",  { Em, Gm } },
2986     { Bad_Opcode },
2987     {"extrq",   { XS, Ib, Ib } },
2988     {"insertq", { XM, XS, Ib, Ib } },
2989   },
2990
2991   /* PREFIX_0F79 */
2992   {
2993     {"vmwrite", { Gm, Em } },
2994     { Bad_Opcode },
2995     {"extrq",   { XM, XS } },
2996     {"insertq", { XM, XS } },
2997   },
2998
2999   /* PREFIX_0F7C */
3000   {
3001     { Bad_Opcode },
3002     { Bad_Opcode },
3003     { "haddpd", { XM, EXx } },
3004     { "haddps", { XM, EXx } },
3005   },
3006
3007   /* PREFIX_0F7D */
3008   {
3009     { Bad_Opcode },
3010     { Bad_Opcode },
3011     { "hsubpd", { XM, EXx } },
3012     { "hsubps", { XM, EXx } },
3013   },
3014
3015   /* PREFIX_0F7E */
3016   {
3017     { "movK",   { Edq, MX } },
3018     { "movq",   { XM, EXq } },
3019     { "movK",   { Edq, XM } },
3020   },
3021
3022   /* PREFIX_0F7F */
3023   {
3024     { "movq",   { EMS, MX } },
3025     { "movdqu", { EXxS, XM } },
3026     { "movdqa", { EXxS, XM } },
3027   },
3028
3029   /* PREFIX_0FB8 */
3030   {
3031     { Bad_Opcode },
3032     { "popcntS", { Gv, Ev } },
3033   },
3034
3035   /* PREFIX_0FBD */
3036   {
3037     { "bsrS",   { Gv, Ev } },
3038     { "lzcntS", { Gv, Ev } },
3039     { "bsrS",   { Gv, Ev } },
3040   },
3041
3042   /* PREFIX_0FC2 */
3043   {
3044     { "cmpps",  { XM, EXx, CMP } },
3045     { "cmpss",  { XM, EXd, CMP } },
3046     { "cmppd",  { XM, EXx, CMP } },
3047     { "cmpsd",  { XM, EXq, CMP } },
3048   },
3049
3050   /* PREFIX_0FC3 */
3051   {
3052     { "movntiS", { Ma, Gv } },
3053   },
3054
3055   /* PREFIX_0FC7_REG_6 */
3056   {
3057     { "vmptrld",{ Mq } },
3058     { "vmxon",  { Mq } },
3059     { "vmclear",{ Mq } },
3060   },
3061
3062   /* PREFIX_0FD0 */
3063   {
3064     { Bad_Opcode },
3065     { Bad_Opcode },
3066     { "addsubpd", { XM, EXx } },
3067     { "addsubps", { XM, EXx } },
3068   },
3069
3070   /* PREFIX_0FD6 */
3071   {
3072     { Bad_Opcode },
3073     { "movq2dq",{ XM, MS } },
3074     { "movq",   { EXqS, XM } },
3075     { "movdq2q",{ MX, XS } },
3076   },
3077
3078   /* PREFIX_0FE6 */
3079   {
3080     { Bad_Opcode },
3081     { "cvtdq2pd", { XM, EXq } },
3082     { "cvttpd2dq", { XM, EXx } },
3083     { "cvtpd2dq", { XM, EXx } },
3084   },
3085
3086   /* PREFIX_0FE7 */
3087   {
3088     { "movntq", { Mq, MX } },
3089     { Bad_Opcode },
3090     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3091   },
3092
3093   /* PREFIX_0FF0 */
3094   {
3095     { Bad_Opcode },
3096     { Bad_Opcode },
3097     { Bad_Opcode },
3098     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3099   },
3100
3101   /* PREFIX_0FF7 */
3102   {
3103     { "maskmovq", { MX, MS } },
3104     { Bad_Opcode },
3105     { "maskmovdqu", { XM, XS } },
3106   },
3107
3108   /* PREFIX_0F3810 */
3109   {
3110     { Bad_Opcode },
3111     { Bad_Opcode },
3112     { "pblendvb", { XM, EXx, XMM0 } },
3113   },
3114
3115   /* PREFIX_0F3814 */
3116   {
3117     { Bad_Opcode },
3118     { Bad_Opcode },
3119     { "blendvps", { XM, EXx, XMM0 } },
3120   },
3121
3122   /* PREFIX_0F3815 */
3123   {
3124     { Bad_Opcode },
3125     { Bad_Opcode },
3126     { "blendvpd", { XM, EXx, XMM0 } },
3127   },
3128
3129   /* PREFIX_0F3817 */
3130   {
3131     { Bad_Opcode },
3132     { Bad_Opcode },
3133     { "ptest",  { XM, EXx } },
3134   },
3135
3136   /* PREFIX_0F3820 */
3137   {
3138     { Bad_Opcode },
3139     { Bad_Opcode },
3140     { "pmovsxbw", { XM, EXq } },
3141   },
3142
3143   /* PREFIX_0F3821 */
3144   {
3145     { Bad_Opcode },
3146     { Bad_Opcode },
3147     { "pmovsxbd", { XM, EXd } },
3148   },
3149
3150   /* PREFIX_0F3822 */
3151   {
3152     { Bad_Opcode },
3153     { Bad_Opcode },
3154     { "pmovsxbq", { XM, EXw } },
3155   },
3156
3157   /* PREFIX_0F3823 */
3158   {
3159     { Bad_Opcode },
3160     { Bad_Opcode },
3161     { "pmovsxwd", { XM, EXq } },
3162   },
3163
3164   /* PREFIX_0F3824 */
3165   {
3166     { Bad_Opcode },
3167     { Bad_Opcode },
3168     { "pmovsxwq", { XM, EXd } },
3169   },
3170
3171   /* PREFIX_0F3825 */
3172   {
3173     { Bad_Opcode },
3174     { Bad_Opcode },
3175     { "pmovsxdq", { XM, EXq } },
3176   },
3177
3178   /* PREFIX_0F3828 */
3179   {
3180     { Bad_Opcode },
3181     { Bad_Opcode },
3182     { "pmuldq", { XM, EXx } },
3183   },
3184
3185   /* PREFIX_0F3829 */
3186   {
3187     { Bad_Opcode },
3188     { Bad_Opcode },
3189     { "pcmpeqq", { XM, EXx } },
3190   },
3191
3192   /* PREFIX_0F382A */
3193   {
3194     { Bad_Opcode },
3195     { Bad_Opcode },
3196     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3197   },
3198
3199   /* PREFIX_0F382B */
3200   {
3201     { Bad_Opcode },
3202     { Bad_Opcode },
3203     { "packusdw", { XM, EXx } },
3204   },
3205
3206   /* PREFIX_0F3830 */
3207   {
3208     { Bad_Opcode },
3209     { Bad_Opcode },
3210     { "pmovzxbw", { XM, EXq } },
3211   },
3212
3213   /* PREFIX_0F3831 */
3214   {
3215     { Bad_Opcode },
3216     { Bad_Opcode },
3217     { "pmovzxbd", { XM, EXd } },
3218   },
3219
3220   /* PREFIX_0F3832 */
3221   {
3222     { Bad_Opcode },
3223     { Bad_Opcode },
3224     { "pmovzxbq", { XM, EXw } },
3225   },
3226
3227   /* PREFIX_0F3833 */
3228   {
3229     { Bad_Opcode },
3230     { Bad_Opcode },
3231     { "pmovzxwd", { XM, EXq } },
3232   },
3233
3234   /* PREFIX_0F3834 */
3235   {
3236     { Bad_Opcode },
3237     { Bad_Opcode },
3238     { "pmovzxwq", { XM, EXd } },
3239   },
3240
3241   /* PREFIX_0F3835 */
3242   {
3243     { Bad_Opcode },
3244     { Bad_Opcode },
3245     { "pmovzxdq", { XM, EXq } },
3246   },
3247
3248   /* PREFIX_0F3837 */
3249   {
3250     { Bad_Opcode },
3251     { Bad_Opcode },
3252     { "pcmpgtq", { XM, EXx } },
3253   },
3254
3255   /* PREFIX_0F3838 */
3256   {
3257     { Bad_Opcode },
3258     { Bad_Opcode },
3259     { "pminsb", { XM, EXx } },
3260   },
3261
3262   /* PREFIX_0F3839 */
3263   {
3264     { Bad_Opcode },
3265     { Bad_Opcode },
3266     { "pminsd", { XM, EXx } },
3267   },
3268
3269   /* PREFIX_0F383A */
3270   {
3271     { Bad_Opcode },
3272     { Bad_Opcode },
3273     { "pminuw", { XM, EXx } },
3274   },
3275
3276   /* PREFIX_0F383B */
3277   {
3278     { Bad_Opcode },
3279     { Bad_Opcode },
3280     { "pminud", { XM, EXx } },
3281   },
3282
3283   /* PREFIX_0F383C */
3284   {
3285     { Bad_Opcode },
3286     { Bad_Opcode },
3287     { "pmaxsb", { XM, EXx } },
3288   },
3289
3290   /* PREFIX_0F383D */
3291   {
3292     { Bad_Opcode },
3293     { Bad_Opcode },
3294     { "pmaxsd", { XM, EXx } },
3295   },
3296
3297   /* PREFIX_0F383E */
3298   {
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { "pmaxuw", { XM, EXx } },
3302   },
3303
3304   /* PREFIX_0F383F */
3305   {
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { "pmaxud", { XM, EXx } },
3309   },
3310
3311   /* PREFIX_0F3840 */
3312   {
3313     { Bad_Opcode },
3314     { Bad_Opcode },
3315     { "pmulld", { XM, EXx } },
3316   },
3317
3318   /* PREFIX_0F3841 */
3319   {
3320     { Bad_Opcode },
3321     { Bad_Opcode },
3322     { "phminposuw", { XM, EXx } },
3323   },
3324
3325   /* PREFIX_0F3880 */
3326   {
3327     { Bad_Opcode },
3328     { Bad_Opcode },
3329     { "invept", { Gm, Mo } },
3330   },
3331
3332   /* PREFIX_0F3881 */
3333   {
3334     { Bad_Opcode },
3335     { Bad_Opcode },
3336     { "invvpid", { Gm, Mo } },
3337   },
3338
3339   /* PREFIX_0F38DB */
3340   {
3341     { Bad_Opcode },
3342     { Bad_Opcode },
3343     { "aesimc", { XM, EXx } },
3344   },
3345
3346   /* PREFIX_0F38DC */
3347   {
3348     { Bad_Opcode },
3349     { Bad_Opcode },
3350     { "aesenc", { XM, EXx } },
3351   },
3352
3353   /* PREFIX_0F38DD */
3354   {
3355     { Bad_Opcode },
3356     { Bad_Opcode },
3357     { "aesenclast", { XM, EXx } },
3358   },
3359
3360   /* PREFIX_0F38DE */
3361   {
3362     { Bad_Opcode },
3363     { Bad_Opcode },
3364     { "aesdec", { XM, EXx } },
3365   },
3366
3367   /* PREFIX_0F38DF */
3368   {
3369     { Bad_Opcode },
3370     { Bad_Opcode },
3371     { "aesdeclast", { XM, EXx } },
3372   },
3373
3374   /* PREFIX_0F38F0 */
3375   {
3376     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3377     { Bad_Opcode },
3378     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3379     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3380   },
3381
3382   /* PREFIX_0F38F1 */
3383   {
3384     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3385     { Bad_Opcode },
3386     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3387     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3388   },
3389
3390   /* PREFIX_0F3A08 */
3391   {
3392     { Bad_Opcode },
3393     { Bad_Opcode },
3394     { "roundps", { XM, EXx, Ib } },
3395   },
3396
3397   /* PREFIX_0F3A09 */
3398   {
3399     { Bad_Opcode },
3400     { Bad_Opcode },
3401     { "roundpd", { XM, EXx, Ib } },
3402   },
3403
3404   /* PREFIX_0F3A0A */
3405   {
3406     { Bad_Opcode },
3407     { Bad_Opcode },
3408     { "roundss", { XM, EXd, Ib } },
3409   },
3410
3411   /* PREFIX_0F3A0B */
3412   {
3413     { Bad_Opcode },
3414     { Bad_Opcode },
3415     { "roundsd", { XM, EXq, Ib } },
3416   },
3417
3418   /* PREFIX_0F3A0C */
3419   {
3420     { Bad_Opcode },
3421     { Bad_Opcode },
3422     { "blendps", { XM, EXx, Ib } },
3423   },
3424
3425   /* PREFIX_0F3A0D */
3426   {
3427     { Bad_Opcode },
3428     { Bad_Opcode },
3429     { "blendpd", { XM, EXx, Ib } },
3430   },
3431
3432   /* PREFIX_0F3A0E */
3433   {
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436     { "pblendw", { XM, EXx, Ib } },
3437   },
3438
3439   /* PREFIX_0F3A14 */
3440   {
3441     { Bad_Opcode },
3442     { Bad_Opcode },
3443     { "pextrb", { Edqb, XM, Ib } },
3444   },
3445
3446   /* PREFIX_0F3A15 */
3447   {
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { "pextrw", { Edqw, XM, Ib } },
3451   },
3452
3453   /* PREFIX_0F3A16 */
3454   {
3455     { Bad_Opcode },
3456     { Bad_Opcode },
3457     { "pextrK", { Edq, XM, Ib } },
3458   },
3459
3460   /* PREFIX_0F3A17 */
3461   {
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { "extractps", { Edqd, XM, Ib } },
3465   },
3466
3467   /* PREFIX_0F3A20 */
3468   {
3469     { Bad_Opcode },
3470     { Bad_Opcode },
3471     { "pinsrb", { XM, Edqb, Ib } },
3472   },
3473
3474   /* PREFIX_0F3A21 */
3475   {
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { "insertps", { XM, EXd, Ib } },
3479   },
3480
3481   /* PREFIX_0F3A22 */
3482   {
3483     { Bad_Opcode },
3484     { Bad_Opcode },
3485     { "pinsrK", { XM, Edq, Ib } },
3486   },
3487
3488   /* PREFIX_0F3A40 */
3489   {
3490     { Bad_Opcode },
3491     { Bad_Opcode },
3492     { "dpps",   { XM, EXx, Ib } },
3493   },
3494
3495   /* PREFIX_0F3A41 */
3496   {
3497     { Bad_Opcode },
3498     { Bad_Opcode },
3499     { "dppd",   { XM, EXx, Ib } },
3500   },
3501
3502   /* PREFIX_0F3A42 */
3503   {
3504     { Bad_Opcode },
3505     { Bad_Opcode },
3506     { "mpsadbw", { XM, EXx, Ib } },
3507   },
3508
3509   /* PREFIX_0F3A44 */
3510   {
3511     { Bad_Opcode },
3512     { Bad_Opcode },
3513     { "pclmulqdq", { XM, EXx, PCLMUL } },
3514   },
3515
3516   /* PREFIX_0F3A60 */
3517   {
3518     { Bad_Opcode },
3519     { Bad_Opcode },
3520     { "pcmpestrm", { XM, EXx, Ib } },
3521   },
3522
3523   /* PREFIX_0F3A61 */
3524   {
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { "pcmpestri", { XM, EXx, Ib } },
3528   },
3529
3530   /* PREFIX_0F3A62 */
3531   {
3532     { Bad_Opcode },
3533     { Bad_Opcode },
3534     { "pcmpistrm", { XM, EXx, Ib } },
3535   },
3536
3537   /* PREFIX_0F3A63 */
3538   {
3539     { Bad_Opcode },
3540     { Bad_Opcode },
3541     { "pcmpistri", { XM, EXx, Ib } },
3542   },
3543
3544   /* PREFIX_0F3ADF */
3545   {
3546     { Bad_Opcode },
3547     { Bad_Opcode },
3548     { "aeskeygenassist", { XM, EXx, Ib } },
3549   },
3550
3551   /* PREFIX_VEX_10 */
3552   {
3553     { VEX_W_TABLE (VEX_W_10_P_0) },
3554     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3555     { VEX_W_TABLE (VEX_W_10_P_2) },
3556     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3557   },
3558
3559   /* PREFIX_VEX_11 */
3560   {
3561     { VEX_W_TABLE (VEX_W_11_P_0) },
3562     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3563     { VEX_W_TABLE (VEX_W_11_P_2) },
3564     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3565   },
3566
3567   /* PREFIX_VEX_12 */
3568   {
3569     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3570     { VEX_W_TABLE (VEX_W_12_P_1) },
3571     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3572     { VEX_W_TABLE (VEX_W_12_P_3) },
3573   },
3574
3575   /* PREFIX_VEX_16 */
3576   {
3577     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3578     { VEX_W_TABLE (VEX_W_16_P_1) },
3579     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3580   },
3581
3582   /* PREFIX_VEX_2A */
3583   {
3584     { Bad_Opcode },
3585     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3586     { Bad_Opcode },
3587     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3588   },
3589
3590   /* PREFIX_VEX_2C */
3591   {
3592     { Bad_Opcode },
3593     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3594     { Bad_Opcode },
3595     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3596   },
3597
3598   /* PREFIX_VEX_2D */
3599   {
3600     { Bad_Opcode },
3601     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3602     { Bad_Opcode },
3603     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3604   },
3605
3606   /* PREFIX_VEX_2E */
3607   {
3608     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3609     { Bad_Opcode },
3610     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3611   },
3612
3613   /* PREFIX_VEX_2F */
3614   {
3615     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3616     { Bad_Opcode },
3617     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3618   },
3619
3620   /* PREFIX_VEX_51 */
3621   {
3622     { VEX_W_TABLE (VEX_W_51_P_0) },
3623     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3624     { VEX_W_TABLE (VEX_W_51_P_2) },
3625     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3626   },
3627
3628   /* PREFIX_VEX_52 */
3629   {
3630     { VEX_W_TABLE (VEX_W_52_P_0) },
3631     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3632   },
3633
3634   /* PREFIX_VEX_53 */
3635   {
3636     { VEX_W_TABLE (VEX_W_53_P_0) },
3637     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3638   },
3639
3640   /* PREFIX_VEX_58 */
3641   {
3642     { VEX_W_TABLE (VEX_W_58_P_0) },
3643     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3644     { VEX_W_TABLE (VEX_W_58_P_2) },
3645     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3646   },
3647
3648   /* PREFIX_VEX_59 */
3649   {
3650     { VEX_W_TABLE (VEX_W_59_P_0) },
3651     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3652     { VEX_W_TABLE (VEX_W_59_P_2) },
3653     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3654   },
3655
3656   /* PREFIX_VEX_5A */
3657   {
3658     { VEX_W_TABLE (VEX_W_5A_P_0) },
3659     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3660     { "vcvtpd2ps%XY", { XMM, EXx } },
3661     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3662   },
3663
3664   /* PREFIX_VEX_5B */
3665   {
3666     { VEX_W_TABLE (VEX_W_5B_P_0) },
3667     { VEX_W_TABLE (VEX_W_5B_P_1) },
3668     { VEX_W_TABLE (VEX_W_5B_P_2) },
3669   },
3670
3671   /* PREFIX_VEX_5C */
3672   {
3673     { VEX_W_TABLE (VEX_W_5C_P_0) },
3674     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3675     { VEX_W_TABLE (VEX_W_5C_P_2) },
3676     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3677   },
3678
3679   /* PREFIX_VEX_5D */
3680   {
3681     { VEX_W_TABLE (VEX_W_5D_P_0) },
3682     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3683     { VEX_W_TABLE (VEX_W_5D_P_2) },
3684     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3685   },
3686
3687   /* PREFIX_VEX_5E */
3688   {
3689     { VEX_W_TABLE (VEX_W_5E_P_0) },
3690     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3691     { VEX_W_TABLE (VEX_W_5E_P_2) },
3692     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3693   },
3694
3695   /* PREFIX_VEX_5F */
3696   {
3697     { VEX_W_TABLE (VEX_W_5F_P_0) },
3698     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3699     { VEX_W_TABLE (VEX_W_5F_P_2) },
3700     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3701   },
3702
3703   /* PREFIX_VEX_60 */
3704   {
3705     { Bad_Opcode },
3706     { Bad_Opcode },
3707     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3708   },
3709
3710   /* PREFIX_VEX_61 */
3711   {
3712     { Bad_Opcode },
3713     { Bad_Opcode },
3714     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3715   },
3716
3717   /* PREFIX_VEX_62 */
3718   {
3719     { Bad_Opcode },
3720     { Bad_Opcode },
3721     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3722   },
3723
3724   /* PREFIX_VEX_63 */
3725   {
3726     { Bad_Opcode },
3727     { Bad_Opcode },
3728     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3729   },
3730
3731   /* PREFIX_VEX_64 */
3732   {
3733     { Bad_Opcode },
3734     { Bad_Opcode },
3735     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3736   },
3737
3738   /* PREFIX_VEX_65 */
3739   {
3740     { Bad_Opcode },
3741     { Bad_Opcode },
3742     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3743   },
3744
3745   /* PREFIX_VEX_66 */
3746   {
3747     { Bad_Opcode },
3748     { Bad_Opcode },
3749     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3750   },
3751
3752   /* PREFIX_VEX_67 */
3753   {
3754     { Bad_Opcode },
3755     { Bad_Opcode },
3756     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3757   },
3758
3759   /* PREFIX_VEX_68 */
3760   {
3761     { Bad_Opcode },
3762     { Bad_Opcode },
3763     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3764   },
3765
3766   /* PREFIX_VEX_69 */
3767   {
3768     { Bad_Opcode },
3769     { Bad_Opcode },
3770     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3771   },
3772
3773   /* PREFIX_VEX_6A */
3774   {
3775     { Bad_Opcode },
3776     { Bad_Opcode },
3777     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3778   },
3779
3780   /* PREFIX_VEX_6B */
3781   {
3782     { Bad_Opcode },
3783     { Bad_Opcode },
3784     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3785   },
3786
3787   /* PREFIX_VEX_6C */
3788   {
3789     { Bad_Opcode },
3790     { Bad_Opcode },
3791     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3792   },
3793
3794   /* PREFIX_VEX_6D */
3795   {
3796     { Bad_Opcode },
3797     { Bad_Opcode },
3798     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3799   },
3800
3801   /* PREFIX_VEX_6E */
3802   {
3803     { Bad_Opcode },
3804     { Bad_Opcode },
3805     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3806   },
3807
3808   /* PREFIX_VEX_6F */
3809   {
3810     { Bad_Opcode },
3811     { VEX_W_TABLE (VEX_W_6F_P_1) },
3812     { VEX_W_TABLE (VEX_W_6F_P_2) },
3813   },
3814
3815   /* PREFIX_VEX_70 */
3816   {
3817     { Bad_Opcode },
3818     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3819     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3820     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3821   },
3822
3823   /* PREFIX_VEX_71_REG_2 */
3824   {
3825     { Bad_Opcode },
3826     { Bad_Opcode },
3827     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3828   },
3829
3830   /* PREFIX_VEX_71_REG_4 */
3831   {
3832     { Bad_Opcode },
3833     { Bad_Opcode },
3834     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3835   },
3836
3837   /* PREFIX_VEX_71_REG_6 */
3838   {
3839     { Bad_Opcode },
3840     { Bad_Opcode },
3841     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3842   },
3843
3844   /* PREFIX_VEX_72_REG_2 */
3845   {
3846     { Bad_Opcode },
3847     { Bad_Opcode },
3848     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3849   },
3850
3851   /* PREFIX_VEX_72_REG_4 */
3852   {
3853     { Bad_Opcode },
3854     { Bad_Opcode },
3855     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3856   },
3857
3858   /* PREFIX_VEX_72_REG_6 */
3859   {
3860     { Bad_Opcode },
3861     { Bad_Opcode },
3862     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3863   },
3864
3865   /* PREFIX_VEX_73_REG_2 */
3866   {
3867     { Bad_Opcode },
3868     { Bad_Opcode },
3869     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3870   },
3871
3872   /* PREFIX_VEX_73_REG_3 */
3873   {
3874     { Bad_Opcode },
3875     { Bad_Opcode },
3876     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3877   },
3878
3879   /* PREFIX_VEX_73_REG_6 */
3880   {
3881     { Bad_Opcode },
3882     { Bad_Opcode },
3883     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3884   },
3885
3886   /* PREFIX_VEX_73_REG_7 */
3887   {
3888     { Bad_Opcode },
3889     { Bad_Opcode },
3890     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3891   },
3892
3893   /* PREFIX_VEX_74 */
3894   {
3895     { Bad_Opcode },
3896     { Bad_Opcode },
3897     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3898   },
3899
3900   /* PREFIX_VEX_75 */
3901   {
3902     { Bad_Opcode },
3903     { Bad_Opcode },
3904     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3905   },
3906
3907   /* PREFIX_VEX_76 */
3908   {
3909     { Bad_Opcode },
3910     { Bad_Opcode },
3911     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3912   },
3913
3914   /* PREFIX_VEX_77 */
3915   {
3916     { VEX_W_TABLE (VEX_W_77_P_0) },
3917   },
3918
3919   /* PREFIX_VEX_7C */
3920   {
3921     { Bad_Opcode },
3922     { Bad_Opcode },
3923     { VEX_W_TABLE (VEX_W_7C_P_2) },
3924     { VEX_W_TABLE (VEX_W_7C_P_3) },
3925   },
3926
3927   /* PREFIX_VEX_7D */
3928   {
3929     { Bad_Opcode },
3930     { Bad_Opcode },
3931     { VEX_W_TABLE (VEX_W_7D_P_2) },
3932     { VEX_W_TABLE (VEX_W_7D_P_3) },
3933   },
3934
3935   /* PREFIX_VEX_7E */
3936   {
3937     { Bad_Opcode },
3938     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3939     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3940   },
3941
3942   /* PREFIX_VEX_7F */
3943   {
3944     { Bad_Opcode },
3945     { VEX_W_TABLE (VEX_W_7F_P_1) },
3946     { VEX_W_TABLE (VEX_W_7F_P_2) },
3947   },
3948
3949   /* PREFIX_VEX_C2 */
3950   {
3951     { VEX_W_TABLE (VEX_W_C2_P_0) },
3952     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3953     { VEX_W_TABLE (VEX_W_C2_P_2) },
3954     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3955   },
3956
3957   /* PREFIX_VEX_C4 */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3962   },
3963
3964   /* PREFIX_VEX_C5 */
3965   {
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3969   },
3970
3971   /* PREFIX_VEX_D0 */
3972   {
3973     { Bad_Opcode },
3974     { Bad_Opcode },
3975     { VEX_W_TABLE (VEX_W_D0_P_2) },
3976     { VEX_W_TABLE (VEX_W_D0_P_3) },
3977   },
3978
3979   /* PREFIX_VEX_D1 */
3980   {
3981     { Bad_Opcode },
3982     { Bad_Opcode },
3983     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3984   },
3985
3986   /* PREFIX_VEX_D2 */
3987   {
3988     { Bad_Opcode },
3989     { Bad_Opcode },
3990     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3991   },
3992
3993   /* PREFIX_VEX_D3 */
3994   {
3995     { Bad_Opcode },
3996     { Bad_Opcode },
3997     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3998   },
3999
4000   /* PREFIX_VEX_D4 */
4001   {
4002     { Bad_Opcode },
4003     { Bad_Opcode },
4004     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
4005   },
4006
4007   /* PREFIX_VEX_D5 */
4008   {
4009     { Bad_Opcode },
4010     { Bad_Opcode },
4011     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
4012   },
4013
4014   /* PREFIX_VEX_D6 */
4015   {
4016     { Bad_Opcode },
4017     { Bad_Opcode },
4018     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
4019   },
4020
4021   /* PREFIX_VEX_D7 */
4022   {
4023     { Bad_Opcode },
4024     { Bad_Opcode },
4025     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
4026   },
4027
4028   /* PREFIX_VEX_D8 */
4029   {
4030     { Bad_Opcode },
4031     { Bad_Opcode },
4032     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4033   },
4034
4035   /* PREFIX_VEX_D9 */
4036   {
4037     { Bad_Opcode },
4038     { Bad_Opcode },
4039     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4040   },
4041
4042   /* PREFIX_VEX_DA */
4043   {
4044     { Bad_Opcode },
4045     { Bad_Opcode },
4046     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4047   },
4048
4049   /* PREFIX_VEX_DB */
4050   {
4051     { Bad_Opcode },
4052     { Bad_Opcode },
4053     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4054   },
4055
4056   /* PREFIX_VEX_DC */
4057   {
4058     { Bad_Opcode },
4059     { Bad_Opcode },
4060     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4061   },
4062
4063   /* PREFIX_VEX_DD */
4064   {
4065     { Bad_Opcode },
4066     { Bad_Opcode },
4067     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4068   },
4069
4070   /* PREFIX_VEX_DE */
4071   {
4072     { Bad_Opcode },
4073     { Bad_Opcode },
4074     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4075   },
4076
4077   /* PREFIX_VEX_DF */
4078   {
4079     { Bad_Opcode },
4080     { Bad_Opcode },
4081     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4082   },
4083
4084   /* PREFIX_VEX_E0 */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4089   },
4090
4091   /* PREFIX_VEX_E1 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4096   },
4097
4098   /* PREFIX_VEX_E2 */
4099   {
4100     { Bad_Opcode },
4101     { Bad_Opcode },
4102     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4103   },
4104
4105   /* PREFIX_VEX_E3 */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4110   },
4111
4112   /* PREFIX_VEX_E4 */
4113   {
4114     { Bad_Opcode },
4115     { Bad_Opcode },
4116     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4117   },
4118
4119   /* PREFIX_VEX_E5 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4124   },
4125
4126   /* PREFIX_VEX_E6 */
4127   {
4128     { Bad_Opcode },
4129     { VEX_W_TABLE (VEX_W_E6_P_1) },
4130     { VEX_W_TABLE (VEX_W_E6_P_2) },
4131     { VEX_W_TABLE (VEX_W_E6_P_3) },
4132   },
4133
4134   /* PREFIX_VEX_E7 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4139   },
4140
4141   /* PREFIX_VEX_E8 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4146   },
4147
4148   /* PREFIX_VEX_E9 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4153   },
4154
4155   /* PREFIX_VEX_EA */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4160   },
4161
4162   /* PREFIX_VEX_EB */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4167   },
4168
4169   /* PREFIX_VEX_EC */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4174   },
4175
4176   /* PREFIX_VEX_ED */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4181   },
4182
4183   /* PREFIX_VEX_EE */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4188   },
4189
4190   /* PREFIX_VEX_EF */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4195   },
4196
4197   /* PREFIX_VEX_F0 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4203   },
4204
4205   /* PREFIX_VEX_F1 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4210   },
4211
4212   /* PREFIX_VEX_F2 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4217   },
4218
4219   /* PREFIX_VEX_F3 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4224   },
4225
4226   /* PREFIX_VEX_F4 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4231   },
4232
4233   /* PREFIX_VEX_F5 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4238   },
4239
4240   /* PREFIX_VEX_F6 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4245   },
4246
4247   /* PREFIX_VEX_F7 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4252   },
4253
4254   /* PREFIX_VEX_F8 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4259   },
4260
4261   /* PREFIX_VEX_F9 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4266   },
4267
4268   /* PREFIX_VEX_FA */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4273   },
4274
4275   /* PREFIX_VEX_FB */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4280   },
4281
4282   /* PREFIX_VEX_FC */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4287   },
4288
4289   /* PREFIX_VEX_FD */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4294   },
4295
4296   /* PREFIX_VEX_FE */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4301   },
4302
4303   /* PREFIX_VEX_3800 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4308   },
4309
4310   /* PREFIX_VEX_3801 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4315   },
4316
4317   /* PREFIX_VEX_3802 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4322   },
4323
4324   /* PREFIX_VEX_3803 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4329   },
4330
4331   /* PREFIX_VEX_3804 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4336   },
4337
4338   /* PREFIX_VEX_3805 */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4343   },
4344
4345   /* PREFIX_VEX_3806 */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4350   },
4351
4352   /* PREFIX_VEX_3807 */
4353   {
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4357   },
4358
4359   /* PREFIX_VEX_3808 */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4364   },
4365
4366   /* PREFIX_VEX_3809 */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4371   },
4372
4373   /* PREFIX_VEX_380A */
4374   {
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4378   },
4379
4380   /* PREFIX_VEX_380B */
4381   {
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4385   },
4386
4387   /* PREFIX_VEX_380C */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { VEX_W_TABLE (VEX_W_380C_P_2) },
4392   },
4393
4394   /* PREFIX_VEX_380D */
4395   {
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { VEX_W_TABLE (VEX_W_380D_P_2) },
4399   },
4400
4401   /* PREFIX_VEX_380E */
4402   {
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     { VEX_W_TABLE (VEX_W_380E_P_2) },
4406   },
4407
4408   /* PREFIX_VEX_380F */
4409   {
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { VEX_W_TABLE (VEX_W_380F_P_2) },
4413   },
4414
4415   /* PREFIX_VEX_3817 */
4416   {
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { VEX_W_TABLE (VEX_W_3817_P_2) },
4420   },
4421
4422   /* PREFIX_VEX_3818 */
4423   {
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4427   },
4428
4429   /* PREFIX_VEX_3819 */
4430   {
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4434   },
4435
4436   /* PREFIX_VEX_381A */
4437   {
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4441   },
4442
4443   /* PREFIX_VEX_381C */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4448   },
4449
4450   /* PREFIX_VEX_381D */
4451   {
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4455   },
4456
4457   /* PREFIX_VEX_381E */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4462   },
4463
4464   /* PREFIX_VEX_3820 */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4469   },
4470
4471   /* PREFIX_VEX_3821 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4476   },
4477
4478   /* PREFIX_VEX_3822 */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4483   },
4484
4485   /* PREFIX_VEX_3823 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4490   },
4491
4492   /* PREFIX_VEX_3824 */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4497   },
4498
4499   /* PREFIX_VEX_3825 */
4500   {
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4504   },
4505
4506   /* PREFIX_VEX_3828 */
4507   {
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4511   },
4512
4513   /* PREFIX_VEX_3829 */
4514   {
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4518   },
4519
4520   /* PREFIX_VEX_382A */
4521   {
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4525   },
4526
4527   /* PREFIX_VEX_382B */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4532   },
4533
4534   /* PREFIX_VEX_382C */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4539   },
4540
4541   /* PREFIX_VEX_382D */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4546   },
4547
4548   /* PREFIX_VEX_382E */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4553   },
4554
4555   /* PREFIX_VEX_382F */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4560   },
4561
4562   /* PREFIX_VEX_3830 */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4567   },
4568
4569   /* PREFIX_VEX_3831 */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4574   },
4575
4576   /* PREFIX_VEX_3832 */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4581   },
4582
4583   /* PREFIX_VEX_3833 */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4588   },
4589
4590   /* PREFIX_VEX_3834 */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4595   },
4596
4597   /* PREFIX_VEX_3835 */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4602   },
4603
4604   /* PREFIX_VEX_3837 */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4609   },
4610
4611   /* PREFIX_VEX_3838 */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_3839 */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4623   },
4624
4625   /* PREFIX_VEX_383A */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4630   },
4631
4632   /* PREFIX_VEX_383B */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4637   },
4638
4639   /* PREFIX_VEX_383C */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4644   },
4645
4646   /* PREFIX_VEX_383D */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4651   },
4652
4653   /* PREFIX_VEX_383E */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4658   },
4659
4660   /* PREFIX_VEX_383F */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4665   },
4666
4667   /* PREFIX_VEX_3840 */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4672   },
4673
4674   /* PREFIX_VEX_3841 */
4675   {
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4679   },
4680
4681   /* PREFIX_VEX_3896 */
4682   {
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4686   },
4687
4688   /* PREFIX_VEX_3897 */
4689   {
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4693   },
4694
4695   /* PREFIX_VEX_3898 */
4696   {
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { "vfmadd132p%XW", { XM, Vex, EXx } },
4700   },
4701
4702   /* PREFIX_VEX_3899 */
4703   {
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4707   },
4708
4709   /* PREFIX_VEX_389A */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "vfmsub132p%XW", { XM, Vex, EXx } },
4714   },
4715
4716   /* PREFIX_VEX_389B */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4721   },
4722
4723   /* PREFIX_VEX_389C */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4728   },
4729
4730   /* PREFIX_VEX_389D */
4731   {
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4735   },
4736
4737   /* PREFIX_VEX_389E */
4738   {
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4742   },
4743
4744   /* PREFIX_VEX_389F */
4745   {
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4749   },
4750
4751   /* PREFIX_VEX_38A6 */
4752   {
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4756     { Bad_Opcode },
4757   },
4758
4759   /* PREFIX_VEX_38A7 */
4760   {
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4764   },
4765
4766   /* PREFIX_VEX_38A8 */
4767   {
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { "vfmadd213p%XW", { XM, Vex, EXx } },
4771   },
4772
4773   /* PREFIX_VEX_38A9 */
4774   {
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4778   },
4779
4780   /* PREFIX_VEX_38AA */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { "vfmsub213p%XW", { XM, Vex, EXx } },
4785   },
4786
4787   /* PREFIX_VEX_38AB */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4792   },
4793
4794   /* PREFIX_VEX_38AC */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4799   },
4800
4801   /* PREFIX_VEX_38AD */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4806   },
4807
4808   /* PREFIX_VEX_38AE */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4813   },
4814
4815   /* PREFIX_VEX_38AF */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4820   },
4821
4822   /* PREFIX_VEX_38B6 */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4827   },
4828
4829   /* PREFIX_VEX_38B7 */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4834   },
4835
4836   /* PREFIX_VEX_38B8 */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { "vfmadd231p%XW", { XM, Vex, EXx } },
4841   },
4842
4843   /* PREFIX_VEX_38B9 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4848   },
4849
4850   /* PREFIX_VEX_38BA */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "vfmsub231p%XW", { XM, Vex, EXx } },
4855   },
4856
4857   /* PREFIX_VEX_38BB */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4862   },
4863
4864   /* PREFIX_VEX_38BC */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4869   },
4870
4871   /* PREFIX_VEX_38BD */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4876   },
4877
4878   /* PREFIX_VEX_38BE */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4883   },
4884
4885   /* PREFIX_VEX_38BF */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4890   },
4891
4892   /* PREFIX_VEX_38DB */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4897   },
4898
4899   /* PREFIX_VEX_38DC */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4904   },
4905
4906   /* PREFIX_VEX_38DD */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4911   },
4912
4913   /* PREFIX_VEX_38DE */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_38DF */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_3A04 */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { VEX_W_TABLE (VEX_W_3A04_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_3A05 */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_W_TABLE (VEX_W_3A05_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_3A06 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_3A08 */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_W_TABLE (VEX_W_3A08_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_3A09 */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_3A09_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_3A0A */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_3A0B */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_3A0C */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_W_TABLE (VEX_W_3A0C_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_3A0D */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_W_TABLE (VEX_W_3A0D_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_3A0E */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_3A0F */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_3A14 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_3A15 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_3A16 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_3A17 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_3A18 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_3A19 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_3A20 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_3A21 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_3A22 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_3A40 */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_W_TABLE (VEX_W_3A40_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_3A41 */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_3A42 */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_3A44 */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_3A48 */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { VEX_W_TABLE (VEX_W_3A48_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_3A49 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_W_TABLE (VEX_W_3A49_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_3A4A */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_3A4B */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5121   },
5122
5123   /* PREFIX_VEX_3A4C */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5128   },
5129
5130   /* PREFIX_VEX_3A5C */
5131   {
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5135   },
5136
5137   /* PREFIX_VEX_3A5D */
5138   {
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5142   },
5143
5144   /* PREFIX_VEX_3A5E */
5145   {
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5149   },
5150
5151   /* PREFIX_VEX_3A5F */
5152   {
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5156   },
5157
5158   /* PREFIX_VEX_3A60 */
5159   {
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5163     { Bad_Opcode },
5164   },
5165
5166   /* PREFIX_VEX_3A61 */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_3A62 */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5178   },
5179
5180   /* PREFIX_VEX_3A63 */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5185   },
5186
5187   /* PREFIX_VEX_3A68 */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5192   },
5193
5194   /* PREFIX_VEX_3A69 */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5199   },
5200
5201   /* PREFIX_VEX_3A6A */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5206   },
5207
5208   /* PREFIX_VEX_3A6B */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5213   },
5214
5215   /* PREFIX_VEX_3A6C */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5220   },
5221
5222   /* PREFIX_VEX_3A6D */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5227   },
5228
5229   /* PREFIX_VEX_3A6E */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5234   },
5235
5236   /* PREFIX_VEX_3A6F */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5241   },
5242
5243   /* PREFIX_VEX_3A78 */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5248   },
5249
5250   /* PREFIX_VEX_3A79 */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5255   },
5256
5257   /* PREFIX_VEX_3A7A */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5262   },
5263
5264   /* PREFIX_VEX_3A7B */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5269   },
5270
5271   /* PREFIX_VEX_3A7C */
5272   {
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5276     { Bad_Opcode },
5277   },
5278
5279   /* PREFIX_VEX_3A7D */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5284   },
5285
5286   /* PREFIX_VEX_3A7E */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5291   },
5292
5293   /* PREFIX_VEX_3A7F */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5298   },
5299
5300   /* PREFIX_VEX_3ADF */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5305   },
5306 };
5307
5308 static const struct dis386 x86_64_table[][2] = {
5309   /* X86_64_06 */
5310   {
5311     { "push{T|}", { es } },
5312   },
5313
5314   /* X86_64_07 */
5315   {
5316     { "pop{T|}", { es } },
5317   },
5318
5319   /* X86_64_0D */
5320   {
5321     { "push{T|}", { cs } },
5322   },
5323
5324   /* X86_64_16 */
5325   {
5326     { "push{T|}", { ss } },
5327   },
5328
5329   /* X86_64_17 */
5330   {
5331     { "pop{T|}", { ss } },
5332   },
5333
5334   /* X86_64_1E */
5335   {
5336     { "push{T|}", { ds } },
5337   },
5338
5339   /* X86_64_1F */
5340   {
5341     { "pop{T|}", { ds } },
5342   },
5343
5344   /* X86_64_27 */
5345   {
5346     { "daa", { XX } },
5347   },
5348
5349   /* X86_64_2F */
5350   {
5351     { "das", { XX } },
5352   },
5353
5354   /* X86_64_37 */
5355   {
5356     { "aaa", { XX } },
5357   },
5358
5359   /* X86_64_3F */
5360   {
5361     { "aas", { XX } },
5362   },
5363
5364   /* X86_64_60 */
5365   {
5366     { "pusha{P|}", { XX } },
5367   },
5368
5369   /* X86_64_61 */
5370   {
5371     { "popa{P|}", { XX } },
5372   },
5373
5374   /* X86_64_62 */
5375   {
5376     { MOD_TABLE (MOD_62_32BIT) },
5377   },
5378
5379   /* X86_64_63 */
5380   {
5381     { "arpl", { Ew, Gw } },
5382     { "movs{lq|xd}", { Gv, Ed } },
5383   },
5384
5385   /* X86_64_6D */
5386   {
5387     { "ins{R|}", { Yzr, indirDX } },
5388     { "ins{G|}", { Yzr, indirDX } },
5389   },
5390
5391   /* X86_64_6F */
5392   {
5393     { "outs{R|}", { indirDXr, Xz } },
5394     { "outs{G|}", { indirDXr, Xz } },
5395   },
5396
5397   /* X86_64_9A */
5398   {
5399     { "Jcall{T|}", { Ap } },
5400   },
5401
5402   /* X86_64_C4 */
5403   {
5404     { MOD_TABLE (MOD_C4_32BIT) },
5405     { VEX_C4_TABLE (VEX_0F) },
5406   },
5407
5408   /* X86_64_C5 */
5409   {
5410     { MOD_TABLE (MOD_C5_32BIT) },
5411     { VEX_C5_TABLE (VEX_0F) },
5412   },
5413
5414   /* X86_64_CE */
5415   {
5416     { "into", { XX } },
5417   },
5418
5419   /* X86_64_D4 */
5420   {
5421     { "aam", { sIb } },
5422   },
5423
5424   /* X86_64_D5 */
5425   {
5426     { "aad", { sIb } },
5427   },
5428
5429   /* X86_64_EA */
5430   {
5431     { "Jjmp{T|}", { Ap } },
5432   },
5433
5434   /* X86_64_0F01_REG_0 */
5435   {
5436     { "sgdt{Q|IQ}", { M } },
5437     { "sgdt", { M } },
5438   },
5439
5440   /* X86_64_0F01_REG_1 */
5441   {
5442     { "sidt{Q|IQ}", { M } },
5443     { "sidt", { M } },
5444   },
5445
5446   /* X86_64_0F01_REG_2 */
5447   {
5448     { "lgdt{Q|Q}", { M } },
5449     { "lgdt", { M } },
5450   },
5451
5452   /* X86_64_0F01_REG_3 */
5453   {
5454     { "lidt{Q|Q}", { M } },
5455     { "lidt", { M } },
5456   },
5457 };
5458
5459 static const struct dis386 three_byte_table[][256] = {
5460
5461   /* THREE_BYTE_0F38 */
5462   {
5463     /* 00 */
5464     { "pshufb",         { MX, EM } },
5465     { "phaddw",         { MX, EM } },
5466     { "phaddd",         { MX, EM } },
5467     { "phaddsw",        { MX, EM } },
5468     { "pmaddubsw",      { MX, EM } },
5469     { "phsubw",         { MX, EM } },
5470     { "phsubd",         { MX, EM } },
5471     { "phsubsw",        { MX, EM } },
5472     /* 08 */
5473     { "psignb",         { MX, EM } },
5474     { "psignw",         { MX, EM } },
5475     { "psignd",         { MX, EM } },
5476     { "pmulhrsw",       { MX, EM } },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     /* 10 */
5482     { PREFIX_TABLE (PREFIX_0F3810) },
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { PREFIX_TABLE (PREFIX_0F3814) },
5487     { PREFIX_TABLE (PREFIX_0F3815) },
5488     { Bad_Opcode },
5489     { PREFIX_TABLE (PREFIX_0F3817) },
5490     /* 18 */
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { "pabsb",          { MX, EM } },
5496     { "pabsw",          { MX, EM } },
5497     { "pabsd",          { MX, EM } },
5498     { Bad_Opcode },
5499     /* 20 */
5500     { PREFIX_TABLE (PREFIX_0F3820) },
5501     { PREFIX_TABLE (PREFIX_0F3821) },
5502     { PREFIX_TABLE (PREFIX_0F3822) },
5503     { PREFIX_TABLE (PREFIX_0F3823) },
5504     { PREFIX_TABLE (PREFIX_0F3824) },
5505     { PREFIX_TABLE (PREFIX_0F3825) },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     /* 28 */
5509     { PREFIX_TABLE (PREFIX_0F3828) },
5510     { PREFIX_TABLE (PREFIX_0F3829) },
5511     { PREFIX_TABLE (PREFIX_0F382A) },
5512     { PREFIX_TABLE (PREFIX_0F382B) },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     /* 30 */
5518     { PREFIX_TABLE (PREFIX_0F3830) },
5519     { PREFIX_TABLE (PREFIX_0F3831) },
5520     { PREFIX_TABLE (PREFIX_0F3832) },
5521     { PREFIX_TABLE (PREFIX_0F3833) },
5522     { PREFIX_TABLE (PREFIX_0F3834) },
5523     { PREFIX_TABLE (PREFIX_0F3835) },
5524     { Bad_Opcode },
5525     { PREFIX_TABLE (PREFIX_0F3837) },
5526     /* 38 */
5527     { PREFIX_TABLE (PREFIX_0F3838) },
5528     { PREFIX_TABLE (PREFIX_0F3839) },
5529     { PREFIX_TABLE (PREFIX_0F383A) },
5530     { PREFIX_TABLE (PREFIX_0F383B) },
5531     { PREFIX_TABLE (PREFIX_0F383C) },
5532     { PREFIX_TABLE (PREFIX_0F383D) },
5533     { PREFIX_TABLE (PREFIX_0F383E) },
5534     { PREFIX_TABLE (PREFIX_0F383F) },
5535     /* 40 */
5536     { PREFIX_TABLE (PREFIX_0F3840) },
5537     { PREFIX_TABLE (PREFIX_0F3841) },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     /* 48 */
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     /* 50 */
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     /* 58 */
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     /* 60 */
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     /* 68 */
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     /* 70 */
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     /* 78 */
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     /* 80 */
5608     { PREFIX_TABLE (PREFIX_0F3880) },
5609     { PREFIX_TABLE (PREFIX_0F3881) },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     /* 88 */
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     /* 90 */
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     /* 98 */
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     /* a0 */
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     /* a8 */
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     /* b0 */
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     /* b8 */
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     /* c0 */
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     /* c8 */
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     /* d0 */
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     /* d8 */
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { PREFIX_TABLE (PREFIX_0F38DB) },
5711     { PREFIX_TABLE (PREFIX_0F38DC) },
5712     { PREFIX_TABLE (PREFIX_0F38DD) },
5713     { PREFIX_TABLE (PREFIX_0F38DE) },
5714     { PREFIX_TABLE (PREFIX_0F38DF) },
5715     /* e0 */
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     /* e8 */
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     /* f0 */
5734     { PREFIX_TABLE (PREFIX_0F38F0) },
5735     { PREFIX_TABLE (PREFIX_0F38F1) },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     /* f8 */
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751   },
5752   /* THREE_BYTE_0F3A */
5753   {
5754     /* 00 */
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     /* 08 */
5764     { PREFIX_TABLE (PREFIX_0F3A08) },
5765     { PREFIX_TABLE (PREFIX_0F3A09) },
5766     { PREFIX_TABLE (PREFIX_0F3A0A) },
5767     { PREFIX_TABLE (PREFIX_0F3A0B) },
5768     { PREFIX_TABLE (PREFIX_0F3A0C) },
5769     { PREFIX_TABLE (PREFIX_0F3A0D) },
5770     { PREFIX_TABLE (PREFIX_0F3A0E) },
5771     { "palignr",        { MX, EM, Ib } },
5772     /* 10 */
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { PREFIX_TABLE (PREFIX_0F3A14) },
5778     { PREFIX_TABLE (PREFIX_0F3A15) },
5779     { PREFIX_TABLE (PREFIX_0F3A16) },
5780     { PREFIX_TABLE (PREFIX_0F3A17) },
5781     /* 18 */
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     /* 20 */
5791     { PREFIX_TABLE (PREFIX_0F3A20) },
5792     { PREFIX_TABLE (PREFIX_0F3A21) },
5793     { PREFIX_TABLE (PREFIX_0F3A22) },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     /* 28 */
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     /* 30 */
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     /* 38 */
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     /* 40 */
5827     { PREFIX_TABLE (PREFIX_0F3A40) },
5828     { PREFIX_TABLE (PREFIX_0F3A41) },
5829     { PREFIX_TABLE (PREFIX_0F3A42) },
5830     { Bad_Opcode },
5831     { PREFIX_TABLE (PREFIX_0F3A44) },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     /* 48 */
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     /* 50 */
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     /* 58 */
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     /* 60 */
5863     { PREFIX_TABLE (PREFIX_0F3A60) },
5864     { PREFIX_TABLE (PREFIX_0F3A61) },
5865     { PREFIX_TABLE (PREFIX_0F3A62) },
5866     { PREFIX_TABLE (PREFIX_0F3A63) },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     /* 68 */
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     /* 70 */
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     /* 78 */
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     /* 80 */
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     /* 88 */
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     /* 90 */
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     /* 98 */
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     /* a0 */
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     /* a8 */
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     /* b0 */
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     /* b8 */
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     /* c0 */
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     /* c8 */
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     /* d0 */
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     /* d8 */
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { PREFIX_TABLE (PREFIX_0F3ADF) },
6006     /* e0 */
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     /* e8 */
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     /* f0 */
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     /* f8 */
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042   },
6043
6044   /* THREE_BYTE_0F7A */
6045   {
6046     /* 00 */
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     /* 08 */
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     /* 10 */
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     /* 18 */
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     /* 20 */
6083     { "ptest",          { XX } },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     /* 28 */
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     /* 30 */
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     /* 38 */
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     /* 40 */
6119     { Bad_Opcode },
6120     { "phaddbw",        { XM, EXq } },
6121     { "phaddbd",        { XM, EXq } },
6122     { "phaddbq",        { XM, EXq } },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "phaddwd",        { XM, EXq } },
6126     { "phaddwq",        { XM, EXq } },
6127     /* 48 */
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { "phadddq",        { XM, EXq } },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     /* 50 */
6137     { Bad_Opcode },
6138     { "phaddubw",       { XM, EXq } },
6139     { "phaddubd",       { XM, EXq } },
6140     { "phaddubq",       { XM, EXq } },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "phadduwd",       { XM, EXq } },
6144     { "phadduwq",       { XM, EXq } },
6145     /* 58 */
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "phaddudq",       { XM, EXq } },
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     /* 60 */
6155     { Bad_Opcode },
6156     { "phsubbw",        { XM, EXq } },
6157     { "phsubbd",        { XM, EXq } },
6158     { "phsubbq",        { XM, EXq } },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     /* 68 */
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     /* 70 */
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     /* 78 */
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     /* 80 */
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     /* 88 */
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     /* 90 */
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     /* 98 */
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     /* a0 */
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     /* a8 */
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     /* b0 */
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     /* b8 */
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     /* c0 */
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     /* c8 */
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     /* d0 */
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     /* d8 */
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     /* e0 */
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     /* e8 */
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     /* f0 */
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     /* f8 */
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334   },
6335 };
6336
6337 static const struct dis386 xop_table[][256] = {
6338   /* XOP_08 */
6339   {
6340     /* 00 */
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     /* 08 */
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     /* 10 */
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     /* 18 */
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     /* 20 */
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     /* 28 */
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     /* 30 */
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     /* 38 */
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     /* 40 */
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     /* 48 */
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     /* 50 */
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     /* 58 */
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     /* 60 */
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     /* 68 */
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     /* 70 */
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     /* 78 */
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     /* 80 */
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6491     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6492     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6493     /* 88 */
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6501     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6502     /* 90 */
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6509     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6510     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6511     /* 98 */
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6519     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6520     /* a0 */
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6524     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6528     { Bad_Opcode },
6529     /* a8 */
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     /* b0 */
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6546     { Bad_Opcode },
6547     /* b8 */
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     /* c0 */
6557     { "vprotb",         { XM, Vex_2src_1, Ib } },
6558     { "vprotw",         { XM, Vex_2src_1, Ib } },
6559     { "vprotd",         { XM, Vex_2src_1, Ib } },
6560     { "vprotq",         { XM, Vex_2src_1, Ib } },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     /* c8 */
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6571     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6572     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6573     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6574     /* d0 */
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     /* d8 */
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     /* e0 */
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     /* e8 */
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6607     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6608     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6609     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6610     /* f0 */
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     /* f8 */
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628   },
6629   /* XOP_09 */
6630   {
6631     /* 00 */
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     /* 08 */
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     /* 10 */
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { REG_TABLE (REG_XOP_LWPCB) },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     /* 18 */
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     /* 20 */
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     /* 28 */
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     /* 30 */
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     /* 38 */
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     /* 40 */
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     /* 48 */
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     /* 50 */
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     /* 58 */
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     /* 60 */
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     /* 68 */
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     /* 70 */
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     /* 78 */
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     /* 80 */
6776     { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6777     { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6778     { "vfrczss",        { XM, EXd } },
6779     { "vfrczsd",        { XM, EXq } },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     /* 88 */
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     /* 90 */
6794     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6795     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6796     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6797     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6798     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6799     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6800     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6801     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6802     /* 98 */
6803     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6804     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6805     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6806     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     /* a0 */
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     /* a8 */
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     /* b0 */
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     /* b8 */
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     /* c0 */
6848     { Bad_Opcode },
6849     { "vphaddbw",       { XM, EXxmm } },
6850     { "vphaddbd",       { XM, EXxmm } },
6851     { "vphaddbq",       { XM, EXxmm } },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { "vphaddwd",       { XM, EXxmm } },
6855     { "vphaddwq",       { XM, EXxmm } },
6856     /* c8 */
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { "vphadddq",       { XM, EXxmm } },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     /* d0 */
6866     { Bad_Opcode },
6867     { "vphaddubw",      { XM, EXxmm } },
6868     { "vphaddubd",      { XM, EXxmm } },
6869     { "vphaddubq",      { XM, EXxmm } },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { "vphadduwd",      { XM, EXxmm } },
6873     { "vphadduwq",      { XM, EXxmm } },
6874     /* d8 */
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { "vphaddudq",      { XM, EXxmm } },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     /* e0 */
6884     { Bad_Opcode },
6885     { "vphsubbw",       { XM, EXxmm } },
6886     { "vphsubwd",       { XM, EXxmm } },
6887     { "vphsubdq",       { XM, EXxmm } },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     /* e8 */
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     /* f0 */
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     /* f8 */
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919   },
6920   /* XOP_0A */
6921   {
6922     /* 00 */
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     /* 08 */
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     /* 10 */
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { REG_TABLE (REG_XOP_LWP) },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     /* 18 */
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     /* 20 */
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     /* 28 */
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     /* 30 */
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     /* 38 */
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     /* 40 */
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     /* 48 */
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     /* 50 */
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     /* 58 */
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     /* 60 */
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     /* 68 */
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     /* 70 */
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     /* 78 */
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     /* 80 */
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     /* 88 */
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     /* 90 */
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     /* 98 */
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     /* a0 */
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     /* a8 */
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     /* b0 */
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     /* b8 */
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     /* c0 */
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     /* c8 */
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     /* d0 */
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     /* d8 */
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     /* e0 */
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     /* e8 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     /* f0 */
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     /* f8 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210   },
7211 };
7212
7213 static const struct dis386 vex_table[][256] = {
7214   /* VEX_0F */
7215   {
7216     /* 00 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 08 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* 10 */
7235     { PREFIX_TABLE (PREFIX_VEX_10) },
7236     { PREFIX_TABLE (PREFIX_VEX_11) },
7237     { PREFIX_TABLE (PREFIX_VEX_12) },
7238     { MOD_TABLE (MOD_VEX_13) },
7239     { VEX_W_TABLE (VEX_W_14) },
7240     { VEX_W_TABLE (VEX_W_15) },
7241     { PREFIX_TABLE (PREFIX_VEX_16) },
7242     { MOD_TABLE (MOD_VEX_17) },
7243     /* 18 */
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 20 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 28 */
7262     { VEX_W_TABLE (VEX_W_28) },
7263     { VEX_W_TABLE (VEX_W_29) },
7264     { PREFIX_TABLE (PREFIX_VEX_2A) },
7265     { MOD_TABLE (MOD_VEX_2B) },
7266     { PREFIX_TABLE (PREFIX_VEX_2C) },
7267     { PREFIX_TABLE (PREFIX_VEX_2D) },
7268     { PREFIX_TABLE (PREFIX_VEX_2E) },
7269     { PREFIX_TABLE (PREFIX_VEX_2F) },
7270     /* 30 */
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* 38 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 40 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 48 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 50 */
7307     { MOD_TABLE (MOD_VEX_50) },
7308     { PREFIX_TABLE (PREFIX_VEX_51) },
7309     { PREFIX_TABLE (PREFIX_VEX_52) },
7310     { PREFIX_TABLE (PREFIX_VEX_53) },
7311     { "vandpX",         { XM, Vex, EXx } },
7312     { "vandnpX",        { XM, Vex, EXx } },
7313     { "vorpX",          { XM, Vex, EXx } },
7314     { "vxorpX",         { XM, Vex, EXx } },
7315     /* 58 */
7316     { PREFIX_TABLE (PREFIX_VEX_58) },
7317     { PREFIX_TABLE (PREFIX_VEX_59) },
7318     { PREFIX_TABLE (PREFIX_VEX_5A) },
7319     { PREFIX_TABLE (PREFIX_VEX_5B) },
7320     { PREFIX_TABLE (PREFIX_VEX_5C) },
7321     { PREFIX_TABLE (PREFIX_VEX_5D) },
7322     { PREFIX_TABLE (PREFIX_VEX_5E) },
7323     { PREFIX_TABLE (PREFIX_VEX_5F) },
7324     /* 60 */
7325     { PREFIX_TABLE (PREFIX_VEX_60) },
7326     { PREFIX_TABLE (PREFIX_VEX_61) },
7327     { PREFIX_TABLE (PREFIX_VEX_62) },
7328     { PREFIX_TABLE (PREFIX_VEX_63) },
7329     { PREFIX_TABLE (PREFIX_VEX_64) },
7330     { PREFIX_TABLE (PREFIX_VEX_65) },
7331     { PREFIX_TABLE (PREFIX_VEX_66) },
7332     { PREFIX_TABLE (PREFIX_VEX_67) },
7333     /* 68 */
7334     { PREFIX_TABLE (PREFIX_VEX_68) },
7335     { PREFIX_TABLE (PREFIX_VEX_69) },
7336     { PREFIX_TABLE (PREFIX_VEX_6A) },
7337     { PREFIX_TABLE (PREFIX_VEX_6B) },
7338     { PREFIX_TABLE (PREFIX_VEX_6C) },
7339     { PREFIX_TABLE (PREFIX_VEX_6D) },
7340     { PREFIX_TABLE (PREFIX_VEX_6E) },
7341     { PREFIX_TABLE (PREFIX_VEX_6F) },
7342     /* 70 */
7343     { PREFIX_TABLE (PREFIX_VEX_70) },
7344     { REG_TABLE (REG_VEX_71) },
7345     { REG_TABLE (REG_VEX_72) },
7346     { REG_TABLE (REG_VEX_73) },
7347     { PREFIX_TABLE (PREFIX_VEX_74) },
7348     { PREFIX_TABLE (PREFIX_VEX_75) },
7349     { PREFIX_TABLE (PREFIX_VEX_76) },
7350     { PREFIX_TABLE (PREFIX_VEX_77) },
7351     /* 78 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { PREFIX_TABLE (PREFIX_VEX_7C) },
7357     { PREFIX_TABLE (PREFIX_VEX_7D) },
7358     { PREFIX_TABLE (PREFIX_VEX_7E) },
7359     { PREFIX_TABLE (PREFIX_VEX_7F) },
7360     /* 80 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* 88 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* 90 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* 98 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* a0 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* a8 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { REG_TABLE (REG_VEX_AE) },
7413     { Bad_Opcode },
7414     /* b0 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* b8 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* c0 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { PREFIX_TABLE (PREFIX_VEX_C2) },
7436     { Bad_Opcode },
7437     { PREFIX_TABLE (PREFIX_VEX_C4) },
7438     { PREFIX_TABLE (PREFIX_VEX_C5) },
7439     { "vshufpX",        { XM, Vex, EXx, Ib } },
7440     { Bad_Opcode },
7441     /* c8 */
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     /* d0 */
7451     { PREFIX_TABLE (PREFIX_VEX_D0) },
7452     { PREFIX_TABLE (PREFIX_VEX_D1) },
7453     { PREFIX_TABLE (PREFIX_VEX_D2) },
7454     { PREFIX_TABLE (PREFIX_VEX_D3) },
7455     { PREFIX_TABLE (PREFIX_VEX_D4) },
7456     { PREFIX_TABLE (PREFIX_VEX_D5) },
7457     { PREFIX_TABLE (PREFIX_VEX_D6) },
7458     { PREFIX_TABLE (PREFIX_VEX_D7) },
7459     /* d8 */
7460     { PREFIX_TABLE (PREFIX_VEX_D8) },
7461     { PREFIX_TABLE (PREFIX_VEX_D9) },
7462     { PREFIX_TABLE (PREFIX_VEX_DA) },
7463     { PREFIX_TABLE (PREFIX_VEX_DB) },
7464     { PREFIX_TABLE (PREFIX_VEX_DC) },
7465     { PREFIX_TABLE (PREFIX_VEX_DD) },
7466     { PREFIX_TABLE (PREFIX_VEX_DE) },
7467     { PREFIX_TABLE (PREFIX_VEX_DF) },
7468     /* e0 */
7469     { PREFIX_TABLE (PREFIX_VEX_E0) },
7470     { PREFIX_TABLE (PREFIX_VEX_E1) },
7471     { PREFIX_TABLE (PREFIX_VEX_E2) },
7472     { PREFIX_TABLE (PREFIX_VEX_E3) },
7473     { PREFIX_TABLE (PREFIX_VEX_E4) },
7474     { PREFIX_TABLE (PREFIX_VEX_E5) },
7475     { PREFIX_TABLE (PREFIX_VEX_E6) },
7476     { PREFIX_TABLE (PREFIX_VEX_E7) },
7477     /* e8 */
7478     { PREFIX_TABLE (PREFIX_VEX_E8) },
7479     { PREFIX_TABLE (PREFIX_VEX_E9) },
7480     { PREFIX_TABLE (PREFIX_VEX_EA) },
7481     { PREFIX_TABLE (PREFIX_VEX_EB) },
7482     { PREFIX_TABLE (PREFIX_VEX_EC) },
7483     { PREFIX_TABLE (PREFIX_VEX_ED) },
7484     { PREFIX_TABLE (PREFIX_VEX_EE) },
7485     { PREFIX_TABLE (PREFIX_VEX_EF) },
7486     /* f0 */
7487     { PREFIX_TABLE (PREFIX_VEX_F0) },
7488     { PREFIX_TABLE (PREFIX_VEX_F1) },
7489     { PREFIX_TABLE (PREFIX_VEX_F2) },
7490     { PREFIX_TABLE (PREFIX_VEX_F3) },
7491     { PREFIX_TABLE (PREFIX_VEX_F4) },
7492     { PREFIX_TABLE (PREFIX_VEX_F5) },
7493     { PREFIX_TABLE (PREFIX_VEX_F6) },
7494     { PREFIX_TABLE (PREFIX_VEX_F7) },
7495     /* f8 */
7496     { PREFIX_TABLE (PREFIX_VEX_F8) },
7497     { PREFIX_TABLE (PREFIX_VEX_F9) },
7498     { PREFIX_TABLE (PREFIX_VEX_FA) },
7499     { PREFIX_TABLE (PREFIX_VEX_FB) },
7500     { PREFIX_TABLE (PREFIX_VEX_FC) },
7501     { PREFIX_TABLE (PREFIX_VEX_FD) },
7502     { PREFIX_TABLE (PREFIX_VEX_FE) },
7503     { Bad_Opcode },
7504   },
7505   /* VEX_0F38 */
7506   {
7507     /* 00 */
7508     { PREFIX_TABLE (PREFIX_VEX_3800) },
7509     { PREFIX_TABLE (PREFIX_VEX_3801) },
7510     { PREFIX_TABLE (PREFIX_VEX_3802) },
7511     { PREFIX_TABLE (PREFIX_VEX_3803) },
7512     { PREFIX_TABLE (PREFIX_VEX_3804) },
7513     { PREFIX_TABLE (PREFIX_VEX_3805) },
7514     { PREFIX_TABLE (PREFIX_VEX_3806) },
7515     { PREFIX_TABLE (PREFIX_VEX_3807) },
7516     /* 08 */
7517     { PREFIX_TABLE (PREFIX_VEX_3808) },
7518     { PREFIX_TABLE (PREFIX_VEX_3809) },
7519     { PREFIX_TABLE (PREFIX_VEX_380A) },
7520     { PREFIX_TABLE (PREFIX_VEX_380B) },
7521     { PREFIX_TABLE (PREFIX_VEX_380C) },
7522     { PREFIX_TABLE (PREFIX_VEX_380D) },
7523     { PREFIX_TABLE (PREFIX_VEX_380E) },
7524     { PREFIX_TABLE (PREFIX_VEX_380F) },
7525     /* 10 */
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { PREFIX_TABLE (PREFIX_VEX_3817) },
7534     /* 18 */
7535     { PREFIX_TABLE (PREFIX_VEX_3818) },
7536     { PREFIX_TABLE (PREFIX_VEX_3819) },
7537     { PREFIX_TABLE (PREFIX_VEX_381A) },
7538     { Bad_Opcode },
7539     { PREFIX_TABLE (PREFIX_VEX_381C) },
7540     { PREFIX_TABLE (PREFIX_VEX_381D) },
7541     { PREFIX_TABLE (PREFIX_VEX_381E) },
7542     { Bad_Opcode },
7543     /* 20 */
7544     { PREFIX_TABLE (PREFIX_VEX_3820) },
7545     { PREFIX_TABLE (PREFIX_VEX_3821) },
7546     { PREFIX_TABLE (PREFIX_VEX_3822) },
7547     { PREFIX_TABLE (PREFIX_VEX_3823) },
7548     { PREFIX_TABLE (PREFIX_VEX_3824) },
7549     { PREFIX_TABLE (PREFIX_VEX_3825) },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     /* 28 */
7553     { PREFIX_TABLE (PREFIX_VEX_3828) },
7554     { PREFIX_TABLE (PREFIX_VEX_3829) },
7555     { PREFIX_TABLE (PREFIX_VEX_382A) },
7556     { PREFIX_TABLE (PREFIX_VEX_382B) },
7557     { PREFIX_TABLE (PREFIX_VEX_382C) },
7558     { PREFIX_TABLE (PREFIX_VEX_382D) },
7559     { PREFIX_TABLE (PREFIX_VEX_382E) },
7560     { PREFIX_TABLE (PREFIX_VEX_382F) },
7561     /* 30 */
7562     { PREFIX_TABLE (PREFIX_VEX_3830) },
7563     { PREFIX_TABLE (PREFIX_VEX_3831) },
7564     { PREFIX_TABLE (PREFIX_VEX_3832) },
7565     { PREFIX_TABLE (PREFIX_VEX_3833) },
7566     { PREFIX_TABLE (PREFIX_VEX_3834) },
7567     { PREFIX_TABLE (PREFIX_VEX_3835) },
7568     { Bad_Opcode },
7569     { PREFIX_TABLE (PREFIX_VEX_3837) },
7570     /* 38 */
7571     { PREFIX_TABLE (PREFIX_VEX_3838) },
7572     { PREFIX_TABLE (PREFIX_VEX_3839) },
7573     { PREFIX_TABLE (PREFIX_VEX_383A) },
7574     { PREFIX_TABLE (PREFIX_VEX_383B) },
7575     { PREFIX_TABLE (PREFIX_VEX_383C) },
7576     { PREFIX_TABLE (PREFIX_VEX_383D) },
7577     { PREFIX_TABLE (PREFIX_VEX_383E) },
7578     { PREFIX_TABLE (PREFIX_VEX_383F) },
7579     /* 40 */
7580     { PREFIX_TABLE (PREFIX_VEX_3840) },
7581     { PREFIX_TABLE (PREFIX_VEX_3841) },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     /* 48 */
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     /* 50 */
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     /* 58 */
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     /* 60 */
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     /* 68 */
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     /* 70 */
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     /* 78 */
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     /* 80 */
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     /* 88 */
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     /* 90 */
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { PREFIX_TABLE (PREFIX_VEX_3896) },
7677     { PREFIX_TABLE (PREFIX_VEX_3897) },
7678     /* 98 */
7679     { PREFIX_TABLE (PREFIX_VEX_3898) },
7680     { PREFIX_TABLE (PREFIX_VEX_3899) },
7681     { PREFIX_TABLE (PREFIX_VEX_389A) },
7682     { PREFIX_TABLE (PREFIX_VEX_389B) },
7683     { PREFIX_TABLE (PREFIX_VEX_389C) },
7684     { PREFIX_TABLE (PREFIX_VEX_389D) },
7685     { PREFIX_TABLE (PREFIX_VEX_389E) },
7686     { PREFIX_TABLE (PREFIX_VEX_389F) },
7687     /* a0 */
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7695     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7696     /* a8 */
7697     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7698     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7699     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7700     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7701     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7702     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7703     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7704     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7705     /* b0 */
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7713     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7714     /* b8 */
7715     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7716     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7717     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7718     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7719     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7720     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7721     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7722     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7723     /* c0 */
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     /* c8 */
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     /* d0 */
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     /* d8 */
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7755     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7756     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7757     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7758     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7759     /* e0 */
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     /* e8 */
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     /* f0 */
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     /* f8 */
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795   },
7796   /* VEX_0F3A */
7797   {
7798     /* 00 */
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7804     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7805     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7806     { Bad_Opcode },
7807     /* 08 */
7808     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7809     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7810     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7811     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7812     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7813     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7814     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7815     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7816     /* 10 */
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7822     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7823     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7824     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7825     /* 18 */
7826     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7827     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     /* 20 */
7835     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7836     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7837     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     /* 28 */
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     /* 30 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     /* 38 */
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     /* 40 */
7871     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7872     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7873     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7874     { Bad_Opcode },
7875     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* 48 */
7880     { PREFIX_TABLE (PREFIX_VEX_3A48) },
7881     { PREFIX_TABLE (PREFIX_VEX_3A49) },
7882     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7883     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7884     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     /* 50 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     /* 58 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7903     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7904     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7905     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7906     /* 60 */
7907     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7908     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7909     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7910     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     /* 68 */
7916     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7917     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7918     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7919     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7920     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7921     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7922     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7923     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7924     /* 70 */
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     /* 78 */
7934     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7935     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7936     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7937     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7938     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7939     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7940     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7941     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7942     /* 80 */
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     /* 88 */
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     /* 90 */
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     /* 98 */
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     /* a0 */
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     /* a8 */
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     /* b0 */
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     /* b8 */
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     /* c0 */
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     /* c8 */
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     /* d0 */
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     /* d8 */
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8050     /* e0 */
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     /* e8 */
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     /* f0 */
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     /* f8 */
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086   },
8087 };
8088
8089 static const struct dis386 vex_len_table[][2] = {
8090   /* VEX_LEN_10_P_1 */
8091   {
8092     { VEX_W_TABLE (VEX_W_10_P_1) },
8093     { VEX_W_TABLE (VEX_W_10_P_1) },
8094   },
8095
8096   /* VEX_LEN_10_P_3 */
8097   {
8098     { VEX_W_TABLE (VEX_W_10_P_3) },
8099     { VEX_W_TABLE (VEX_W_10_P_3) },
8100   },
8101
8102   /* VEX_LEN_11_P_1 */
8103   {
8104     { VEX_W_TABLE (VEX_W_11_P_1) },
8105     { VEX_W_TABLE (VEX_W_11_P_1) },
8106   },
8107
8108   /* VEX_LEN_11_P_3 */
8109   {
8110     { VEX_W_TABLE (VEX_W_11_P_3) },
8111     { VEX_W_TABLE (VEX_W_11_P_3) },
8112   },
8113
8114   /* VEX_LEN_12_P_0_M_0 */
8115   {
8116     { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8117   },
8118
8119   /* VEX_LEN_12_P_0_M_1 */
8120   {
8121     { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8122   },
8123
8124   /* VEX_LEN_12_P_2 */
8125   {
8126     { VEX_W_TABLE (VEX_W_12_P_2) },
8127   },
8128
8129   /* VEX_LEN_13_M_0 */
8130   {
8131     { VEX_W_TABLE (VEX_W_13_M_0) },
8132   },
8133
8134   /* VEX_LEN_16_P_0_M_0 */
8135   {
8136     { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8137   },
8138
8139   /* VEX_LEN_16_P_0_M_1 */
8140   {
8141     { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8142   },
8143
8144   /* VEX_LEN_16_P_2 */
8145   {
8146     { VEX_W_TABLE (VEX_W_16_P_2) },
8147   },
8148
8149   /* VEX_LEN_17_M_0 */
8150   {
8151     { VEX_W_TABLE (VEX_W_17_M_0) },
8152   },
8153
8154   /* VEX_LEN_2A_P_1 */
8155   {
8156     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8157     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
8158   },
8159
8160   /* VEX_LEN_2A_P_3 */
8161   {
8162     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8163     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
8164   },
8165
8166   /* VEX_LEN_2C_P_1 */
8167   {
8168     { "vcvttss2siY",    { Gv, EXdScalar } },
8169     { "vcvttss2siY",    { Gv, EXdScalar } },
8170   },
8171
8172   /* VEX_LEN_2C_P_3 */
8173   {
8174     { "vcvttsd2siY",    { Gv, EXqScalar } },
8175     { "vcvttsd2siY",    { Gv, EXqScalar } },
8176   },
8177
8178   /* VEX_LEN_2D_P_1 */
8179   {
8180     { "vcvtss2siY",     { Gv, EXdScalar } },
8181     { "vcvtss2siY",     { Gv, EXdScalar } },
8182   },
8183
8184   /* VEX_LEN_2D_P_3 */
8185   {
8186     { "vcvtsd2siY",     { Gv, EXqScalar } },
8187     { "vcvtsd2siY",     { Gv, EXqScalar } },
8188   },
8189
8190   /* VEX_LEN_2E_P_0 */
8191   {
8192     { VEX_W_TABLE (VEX_W_2E_P_0) },
8193     { VEX_W_TABLE (VEX_W_2E_P_0) },
8194   },
8195
8196   /* VEX_LEN_2E_P_2 */
8197   {
8198     { VEX_W_TABLE (VEX_W_2E_P_2) },
8199     { VEX_W_TABLE (VEX_W_2E_P_2) },
8200   },
8201
8202   /* VEX_LEN_2F_P_0 */
8203   {
8204     { VEX_W_TABLE (VEX_W_2F_P_0) },
8205     { VEX_W_TABLE (VEX_W_2F_P_0) },
8206   },
8207
8208   /* VEX_LEN_2F_P_2 */
8209   {
8210     { VEX_W_TABLE (VEX_W_2F_P_2) },
8211     { VEX_W_TABLE (VEX_W_2F_P_2) },
8212   },
8213
8214   /* VEX_LEN_51_P_1 */
8215   {
8216     { VEX_W_TABLE (VEX_W_51_P_1) },
8217     { VEX_W_TABLE (VEX_W_51_P_1) },
8218   },
8219
8220   /* VEX_LEN_51_P_3 */
8221   {
8222     { VEX_W_TABLE (VEX_W_51_P_3) },
8223     { VEX_W_TABLE (VEX_W_51_P_3) },
8224   },
8225
8226   /* VEX_LEN_52_P_1 */
8227   {
8228     { VEX_W_TABLE (VEX_W_52_P_1) },
8229     { VEX_W_TABLE (VEX_W_52_P_1) },
8230   },
8231
8232   /* VEX_LEN_53_P_1 */
8233   {
8234     { VEX_W_TABLE (VEX_W_53_P_1) },
8235     { VEX_W_TABLE (VEX_W_53_P_1) },
8236   },
8237
8238   /* VEX_LEN_58_P_1 */
8239   {
8240     { VEX_W_TABLE (VEX_W_58_P_1) },
8241     { VEX_W_TABLE (VEX_W_58_P_1) },
8242   },
8243
8244   /* VEX_LEN_58_P_3 */
8245   {
8246     { VEX_W_TABLE (VEX_W_58_P_3) },
8247     { VEX_W_TABLE (VEX_W_58_P_3) },
8248   },
8249
8250   /* VEX_LEN_59_P_1 */
8251   {
8252     { VEX_W_TABLE (VEX_W_59_P_1) },
8253     { VEX_W_TABLE (VEX_W_59_P_1) },
8254   },
8255
8256   /* VEX_LEN_59_P_3 */
8257   {
8258     { VEX_W_TABLE (VEX_W_59_P_3) },
8259     { VEX_W_TABLE (VEX_W_59_P_3) },
8260   },
8261
8262   /* VEX_LEN_5A_P_1 */
8263   {
8264     { VEX_W_TABLE (VEX_W_5A_P_1) },
8265     { VEX_W_TABLE (VEX_W_5A_P_1) },
8266   },
8267
8268   /* VEX_LEN_5A_P_3 */
8269   {
8270     { VEX_W_TABLE (VEX_W_5A_P_3) },
8271     { VEX_W_TABLE (VEX_W_5A_P_3) },
8272   },
8273
8274   /* VEX_LEN_5C_P_1 */
8275   {
8276     { VEX_W_TABLE (VEX_W_5C_P_1) },
8277     { VEX_W_TABLE (VEX_W_5C_P_1) },
8278   },
8279
8280   /* VEX_LEN_5C_P_3 */
8281   {
8282     { VEX_W_TABLE (VEX_W_5C_P_3) },
8283     { VEX_W_TABLE (VEX_W_5C_P_3) },
8284   },
8285
8286   /* VEX_LEN_5D_P_1 */
8287   {
8288     { VEX_W_TABLE (VEX_W_5D_P_1) },
8289     { VEX_W_TABLE (VEX_W_5D_P_1) },
8290   },
8291
8292   /* VEX_LEN_5D_P_3 */
8293   {
8294     { VEX_W_TABLE (VEX_W_5D_P_3) },
8295     { VEX_W_TABLE (VEX_W_5D_P_3) },
8296   },
8297
8298   /* VEX_LEN_5E_P_1 */
8299   {
8300     { VEX_W_TABLE (VEX_W_5E_P_1) },
8301     { VEX_W_TABLE (VEX_W_5E_P_1) },
8302   },
8303
8304   /* VEX_LEN_5E_P_3 */
8305   {
8306     { VEX_W_TABLE (VEX_W_5E_P_3) },
8307     { VEX_W_TABLE (VEX_W_5E_P_3) },
8308   },
8309
8310   /* VEX_LEN_5F_P_1 */
8311   {
8312     { VEX_W_TABLE (VEX_W_5F_P_1) },
8313     { VEX_W_TABLE (VEX_W_5F_P_1) },
8314   },
8315
8316   /* VEX_LEN_5F_P_3 */
8317   {
8318     { VEX_W_TABLE (VEX_W_5F_P_3) },
8319     { VEX_W_TABLE (VEX_W_5F_P_3) },
8320   },
8321
8322   /* VEX_LEN_60_P_2 */
8323   {
8324     { VEX_W_TABLE (VEX_W_60_P_2) },
8325   },
8326
8327   /* VEX_LEN_61_P_2 */
8328   {
8329     { VEX_W_TABLE (VEX_W_61_P_2) },
8330   },
8331
8332   /* VEX_LEN_62_P_2 */
8333   {
8334     { VEX_W_TABLE (VEX_W_62_P_2) },
8335   },
8336
8337   /* VEX_LEN_63_P_2 */
8338   {
8339     { VEX_W_TABLE (VEX_W_63_P_2) },
8340   },
8341
8342   /* VEX_LEN_64_P_2 */
8343   {
8344     { VEX_W_TABLE (VEX_W_64_P_2) },
8345   },
8346
8347   /* VEX_LEN_65_P_2 */
8348   {
8349     { VEX_W_TABLE (VEX_W_65_P_2) },
8350   },
8351
8352   /* VEX_LEN_66_P_2 */
8353   {
8354     { VEX_W_TABLE (VEX_W_66_P_2) },
8355   },
8356
8357   /* VEX_LEN_67_P_2 */
8358   {
8359     { VEX_W_TABLE (VEX_W_67_P_2) },
8360   },
8361
8362   /* VEX_LEN_68_P_2 */
8363   {
8364     { VEX_W_TABLE (VEX_W_68_P_2) },
8365   },
8366
8367   /* VEX_LEN_69_P_2 */
8368   {
8369     { VEX_W_TABLE (VEX_W_69_P_2) },
8370   },
8371
8372   /* VEX_LEN_6A_P_2 */
8373   {
8374     { VEX_W_TABLE (VEX_W_6A_P_2) },
8375   },
8376
8377   /* VEX_LEN_6B_P_2 */
8378   {
8379     { VEX_W_TABLE (VEX_W_6B_P_2) },
8380   },
8381
8382   /* VEX_LEN_6C_P_2 */
8383   {
8384     { VEX_W_TABLE (VEX_W_6C_P_2) },
8385   },
8386
8387   /* VEX_LEN_6D_P_2 */
8388   {
8389     { VEX_W_TABLE (VEX_W_6D_P_2) },
8390   },
8391
8392   /* VEX_LEN_6E_P_2 */
8393   {
8394     { "vmovK",          { XMScalar, Edq } },
8395     { "vmovK",          { XMScalar, Edq } },
8396   },
8397
8398   /* VEX_LEN_70_P_1 */
8399   {
8400     { VEX_W_TABLE (VEX_W_70_P_1) },
8401   },
8402
8403   /* VEX_LEN_70_P_2 */
8404   {
8405     { VEX_W_TABLE (VEX_W_70_P_2) },
8406   },
8407
8408   /* VEX_LEN_70_P_3 */
8409   {
8410     { VEX_W_TABLE (VEX_W_70_P_3) },
8411   },
8412
8413   /* VEX_LEN_71_R_2_P_2 */
8414   {
8415     { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8416   },
8417
8418   /* VEX_LEN_71_R_4_P_2 */
8419   {
8420     { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8421   },
8422
8423   /* VEX_LEN_71_R_6_P_2 */
8424   {
8425     { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8426   },
8427
8428   /* VEX_LEN_72_R_2_P_2 */
8429   {
8430     { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8431   },
8432
8433   /* VEX_LEN_72_R_4_P_2 */
8434   {
8435     { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8436   },
8437
8438   /* VEX_LEN_72_R_6_P_2 */
8439   {
8440     { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8441   },
8442
8443   /* VEX_LEN_73_R_2_P_2 */
8444   {
8445     { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8446   },
8447
8448   /* VEX_LEN_73_R_3_P_2 */
8449   {
8450     { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8451   },
8452
8453   /* VEX_LEN_73_R_6_P_2 */
8454   {
8455     { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8456   },
8457
8458   /* VEX_LEN_73_R_7_P_2 */
8459   {
8460     { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8461   },
8462
8463   /* VEX_LEN_74_P_2 */
8464   {
8465     { VEX_W_TABLE (VEX_W_74_P_2) },
8466   },
8467
8468   /* VEX_LEN_75_P_2 */
8469   {
8470     { VEX_W_TABLE (VEX_W_75_P_2) },
8471   },
8472
8473   /* VEX_LEN_76_P_2 */
8474   {
8475     { VEX_W_TABLE (VEX_W_76_P_2) },
8476   },
8477
8478   /* VEX_LEN_7E_P_1 */
8479   {
8480     { VEX_W_TABLE (VEX_W_7E_P_1) },
8481     { VEX_W_TABLE (VEX_W_7E_P_1) },
8482   },
8483
8484   /* VEX_LEN_7E_P_2 */
8485   {
8486     { "vmovK",          { Edq, XMScalar } },
8487     { "vmovK",          { Edq, XMScalar } },
8488   },
8489
8490   /* VEX_LEN_AE_R_2_M_0 */
8491   {
8492     { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8493   },
8494
8495   /* VEX_LEN_AE_R_3_M_0 */
8496   {
8497     { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8498   },
8499
8500   /* VEX_LEN_C2_P_1 */
8501   {
8502     { VEX_W_TABLE (VEX_W_C2_P_1) },
8503     { VEX_W_TABLE (VEX_W_C2_P_1) },
8504   },
8505
8506   /* VEX_LEN_C2_P_3 */
8507   {
8508     { VEX_W_TABLE (VEX_W_C2_P_3) },
8509     { VEX_W_TABLE (VEX_W_C2_P_3) },
8510   },
8511
8512   /* VEX_LEN_C4_P_2 */
8513   {
8514     { VEX_W_TABLE (VEX_W_C4_P_2) },
8515   },
8516
8517   /* VEX_LEN_C5_P_2 */
8518   {
8519     { VEX_W_TABLE (VEX_W_C5_P_2) },
8520   },
8521
8522   /* VEX_LEN_D1_P_2 */
8523   {
8524     { VEX_W_TABLE (VEX_W_D1_P_2) },
8525   },
8526
8527   /* VEX_LEN_D2_P_2 */
8528   {
8529     { VEX_W_TABLE (VEX_W_D2_P_2) },
8530   },
8531
8532   /* VEX_LEN_D3_P_2 */
8533   {
8534     { VEX_W_TABLE (VEX_W_D3_P_2) },
8535   },
8536
8537   /* VEX_LEN_D4_P_2 */
8538   {
8539     { VEX_W_TABLE (VEX_W_D4_P_2) },
8540   },
8541
8542   /* VEX_LEN_D5_P_2 */
8543   {
8544     { VEX_W_TABLE (VEX_W_D5_P_2) },
8545   },
8546
8547   /* VEX_LEN_D6_P_2 */
8548   {
8549     { VEX_W_TABLE (VEX_W_D6_P_2) },
8550     { VEX_W_TABLE (VEX_W_D6_P_2) },
8551   },
8552
8553   /* VEX_LEN_D7_P_2_M_1 */
8554   {
8555     { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8556   },
8557
8558   /* VEX_LEN_D8_P_2 */
8559   {
8560     { VEX_W_TABLE (VEX_W_D8_P_2) },
8561   },
8562
8563   /* VEX_LEN_D9_P_2 */
8564   {
8565     { VEX_W_TABLE (VEX_W_D9_P_2) },
8566   },
8567
8568   /* VEX_LEN_DA_P_2 */
8569   {
8570     { VEX_W_TABLE (VEX_W_DA_P_2) },
8571   },
8572
8573   /* VEX_LEN_DB_P_2 */
8574   {
8575     { VEX_W_TABLE (VEX_W_DB_P_2) },
8576   },
8577
8578   /* VEX_LEN_DC_P_2 */
8579   {
8580     { VEX_W_TABLE (VEX_W_DC_P_2) },
8581   },
8582
8583   /* VEX_LEN_DD_P_2 */
8584   {
8585     { VEX_W_TABLE (VEX_W_DD_P_2) },
8586   },
8587
8588   /* VEX_LEN_DE_P_2 */
8589   {
8590     { VEX_W_TABLE (VEX_W_DE_P_2) },
8591   },
8592
8593   /* VEX_LEN_DF_P_2 */
8594   {
8595     { VEX_W_TABLE (VEX_W_DF_P_2) },
8596   },
8597
8598   /* VEX_LEN_E0_P_2 */
8599   {
8600     { VEX_W_TABLE (VEX_W_E0_P_2) },
8601   },
8602
8603   /* VEX_LEN_E1_P_2 */
8604   {
8605     { VEX_W_TABLE (VEX_W_E1_P_2) },
8606   },
8607
8608   /* VEX_LEN_E2_P_2 */
8609   {
8610     { VEX_W_TABLE (VEX_W_E2_P_2) },
8611   },
8612
8613   /* VEX_LEN_E3_P_2 */
8614   {
8615     { VEX_W_TABLE (VEX_W_E3_P_2) },
8616   },
8617
8618   /* VEX_LEN_E4_P_2 */
8619   {
8620     { VEX_W_TABLE (VEX_W_E4_P_2) },
8621   },
8622
8623   /* VEX_LEN_E5_P_2 */
8624   {
8625     { VEX_W_TABLE (VEX_W_E5_P_2) },
8626   },
8627
8628   /* VEX_LEN_E8_P_2 */
8629   {
8630     { VEX_W_TABLE (VEX_W_E8_P_2) },
8631   },
8632
8633   /* VEX_LEN_E9_P_2 */
8634   {
8635     { VEX_W_TABLE (VEX_W_E9_P_2) },
8636   },
8637
8638   /* VEX_LEN_EA_P_2 */
8639   {
8640     { VEX_W_TABLE (VEX_W_EA_P_2) },
8641   },
8642
8643   /* VEX_LEN_EB_P_2 */
8644   {
8645     { VEX_W_TABLE (VEX_W_EB_P_2) },
8646   },
8647
8648   /* VEX_LEN_EC_P_2 */
8649   {
8650     { VEX_W_TABLE (VEX_W_EC_P_2) },
8651   },
8652
8653   /* VEX_LEN_ED_P_2 */
8654   {
8655     { VEX_W_TABLE (VEX_W_ED_P_2) },
8656   },
8657
8658   /* VEX_LEN_EE_P_2 */
8659   {
8660     { VEX_W_TABLE (VEX_W_EE_P_2) },
8661   },
8662
8663   /* VEX_LEN_EF_P_2 */
8664   {
8665     { VEX_W_TABLE (VEX_W_EF_P_2) },
8666   },
8667
8668   /* VEX_LEN_F1_P_2 */
8669   {
8670     { VEX_W_TABLE (VEX_W_F1_P_2) },
8671   },
8672
8673   /* VEX_LEN_F2_P_2 */
8674   {
8675     { VEX_W_TABLE (VEX_W_F2_P_2) },
8676   },
8677
8678   /* VEX_LEN_F3_P_2 */
8679   {
8680     { VEX_W_TABLE (VEX_W_F3_P_2) },
8681   },
8682
8683   /* VEX_LEN_F4_P_2 */
8684   {
8685     { VEX_W_TABLE (VEX_W_F4_P_2) },
8686   },
8687
8688   /* VEX_LEN_F5_P_2 */
8689   {
8690     { VEX_W_TABLE (VEX_W_F5_P_2) },
8691   },
8692
8693   /* VEX_LEN_F6_P_2 */
8694   {
8695     { VEX_W_TABLE (VEX_W_F6_P_2) },
8696   },
8697
8698   /* VEX_LEN_F7_P_2 */
8699   {
8700     { VEX_W_TABLE (VEX_W_F7_P_2) },
8701   },
8702
8703   /* VEX_LEN_F8_P_2 */
8704   {
8705     { VEX_W_TABLE (VEX_W_F8_P_2) },
8706   },
8707
8708   /* VEX_LEN_F9_P_2 */
8709   {
8710     { VEX_W_TABLE (VEX_W_F9_P_2) },
8711   },
8712
8713   /* VEX_LEN_FA_P_2 */
8714   {
8715     { VEX_W_TABLE (VEX_W_FA_P_2) },
8716   },
8717
8718   /* VEX_LEN_FB_P_2 */
8719   {
8720     { VEX_W_TABLE (VEX_W_FB_P_2) },
8721   },
8722
8723   /* VEX_LEN_FC_P_2 */
8724   {
8725     { VEX_W_TABLE (VEX_W_FC_P_2) },
8726   },
8727
8728   /* VEX_LEN_FD_P_2 */
8729   {
8730     { VEX_W_TABLE (VEX_W_FD_P_2) },
8731   },
8732
8733   /* VEX_LEN_FE_P_2 */
8734   {
8735     { VEX_W_TABLE (VEX_W_FE_P_2) },
8736   },
8737
8738   /* VEX_LEN_3800_P_2 */
8739   {
8740     { VEX_W_TABLE (VEX_W_3800_P_2) },
8741   },
8742
8743   /* VEX_LEN_3801_P_2 */
8744   {
8745     { VEX_W_TABLE (VEX_W_3801_P_2) },
8746   },
8747
8748   /* VEX_LEN_3802_P_2 */
8749   {
8750     { VEX_W_TABLE (VEX_W_3802_P_2) },
8751   },
8752
8753   /* VEX_LEN_3803_P_2 */
8754   {
8755     { VEX_W_TABLE (VEX_W_3803_P_2) },
8756   },
8757
8758   /* VEX_LEN_3804_P_2 */
8759   {
8760     { VEX_W_TABLE (VEX_W_3804_P_2) },
8761   },
8762
8763   /* VEX_LEN_3805_P_2 */
8764   {
8765     { VEX_W_TABLE (VEX_W_3805_P_2) },
8766   },
8767
8768   /* VEX_LEN_3806_P_2 */
8769   {
8770     { VEX_W_TABLE (VEX_W_3806_P_2) },
8771   },
8772
8773   /* VEX_LEN_3807_P_2 */
8774   {
8775     { VEX_W_TABLE (VEX_W_3807_P_2) },
8776   },
8777
8778   /* VEX_LEN_3808_P_2 */
8779   {
8780     { VEX_W_TABLE (VEX_W_3808_P_2) },
8781   },
8782
8783   /* VEX_LEN_3809_P_2 */
8784   {
8785     { VEX_W_TABLE (VEX_W_3809_P_2) },
8786   },
8787
8788   /* VEX_LEN_380A_P_2 */
8789   {
8790     { VEX_W_TABLE (VEX_W_380A_P_2) },
8791   },
8792
8793   /* VEX_LEN_380B_P_2 */
8794   {
8795     { VEX_W_TABLE (VEX_W_380B_P_2) },
8796   },
8797
8798   /* VEX_LEN_3819_P_2_M_0 */
8799   {
8800     { Bad_Opcode },
8801     { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8802   },
8803
8804   /* VEX_LEN_381A_P_2_M_0 */
8805   {
8806     { Bad_Opcode },
8807     { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8808   },
8809
8810   /* VEX_LEN_381C_P_2 */
8811   {
8812     { VEX_W_TABLE (VEX_W_381C_P_2) },
8813   },
8814
8815   /* VEX_LEN_381D_P_2 */
8816   {
8817     { VEX_W_TABLE (VEX_W_381D_P_2) },
8818   },
8819
8820   /* VEX_LEN_381E_P_2 */
8821   {
8822     { VEX_W_TABLE (VEX_W_381E_P_2) },
8823   },
8824
8825   /* VEX_LEN_3820_P_2 */
8826   {
8827     { VEX_W_TABLE (VEX_W_3820_P_2) },
8828   },
8829
8830   /* VEX_LEN_3821_P_2 */
8831   {
8832     { VEX_W_TABLE (VEX_W_3821_P_2) },
8833   },
8834
8835   /* VEX_LEN_3822_P_2 */
8836   {
8837     { VEX_W_TABLE (VEX_W_3822_P_2) },
8838   },
8839
8840   /* VEX_LEN_3823_P_2 */
8841   {
8842     { VEX_W_TABLE (VEX_W_3823_P_2) },
8843   },
8844
8845   /* VEX_LEN_3824_P_2 */
8846   {
8847     { VEX_W_TABLE (VEX_W_3824_P_2) },
8848   },
8849
8850   /* VEX_LEN_3825_P_2 */
8851   {
8852     { VEX_W_TABLE (VEX_W_3825_P_2) },
8853   },
8854
8855   /* VEX_LEN_3828_P_2 */
8856   {
8857     { VEX_W_TABLE (VEX_W_3828_P_2) },
8858   },
8859
8860   /* VEX_LEN_3829_P_2 */
8861   {
8862     { VEX_W_TABLE (VEX_W_3829_P_2) },
8863   },
8864
8865   /* VEX_LEN_382A_P_2_M_0 */
8866   {
8867     { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8868   },
8869
8870   /* VEX_LEN_382B_P_2 */
8871   {
8872     { VEX_W_TABLE (VEX_W_382B_P_2) },
8873   },
8874
8875   /* VEX_LEN_3830_P_2 */
8876   {
8877     { VEX_W_TABLE (VEX_W_3830_P_2) },
8878   },
8879
8880   /* VEX_LEN_3831_P_2 */
8881   {
8882     { VEX_W_TABLE (VEX_W_3831_P_2) },
8883   },
8884
8885   /* VEX_LEN_3832_P_2 */
8886   {
8887     { VEX_W_TABLE (VEX_W_3832_P_2) },
8888   },
8889
8890   /* VEX_LEN_3833_P_2 */
8891   {
8892     { VEX_W_TABLE (VEX_W_3833_P_2) },
8893   },
8894
8895   /* VEX_LEN_3834_P_2 */
8896   {
8897     { VEX_W_TABLE (VEX_W_3834_P_2) },
8898   },
8899
8900   /* VEX_LEN_3835_P_2 */
8901   {
8902     { VEX_W_TABLE (VEX_W_3835_P_2) },
8903   },
8904
8905   /* VEX_LEN_3837_P_2 */
8906   {
8907     { VEX_W_TABLE (VEX_W_3837_P_2) },
8908   },
8909
8910   /* VEX_LEN_3838_P_2 */
8911   {
8912     { VEX_W_TABLE (VEX_W_3838_P_2) },
8913   },
8914
8915   /* VEX_LEN_3839_P_2 */
8916   {
8917     { VEX_W_TABLE (VEX_W_3839_P_2) },
8918   },
8919
8920   /* VEX_LEN_383A_P_2 */
8921   {
8922     { VEX_W_TABLE (VEX_W_383A_P_2) },
8923   },
8924
8925   /* VEX_LEN_383B_P_2 */
8926   {
8927     { VEX_W_TABLE (VEX_W_383B_P_2) },
8928   },
8929
8930   /* VEX_LEN_383C_P_2 */
8931   {
8932     { VEX_W_TABLE (VEX_W_383C_P_2) },
8933   },
8934
8935   /* VEX_LEN_383D_P_2 */
8936   {
8937     { VEX_W_TABLE (VEX_W_383D_P_2) },
8938   },
8939
8940   /* VEX_LEN_383E_P_2 */
8941   {
8942     { VEX_W_TABLE (VEX_W_383E_P_2) },
8943   },
8944
8945   /* VEX_LEN_383F_P_2 */
8946   {
8947     { VEX_W_TABLE (VEX_W_383F_P_2) },
8948   },
8949
8950   /* VEX_LEN_3840_P_2 */
8951   {
8952     { VEX_W_TABLE (VEX_W_3840_P_2) },
8953   },
8954
8955   /* VEX_LEN_3841_P_2 */
8956   {
8957     { VEX_W_TABLE (VEX_W_3841_P_2) },
8958   },
8959
8960   /* VEX_LEN_38DB_P_2 */
8961   {
8962     { VEX_W_TABLE (VEX_W_38DB_P_2) },
8963   },
8964
8965   /* VEX_LEN_38DC_P_2 */
8966   {
8967     { VEX_W_TABLE (VEX_W_38DC_P_2) },
8968   },
8969
8970   /* VEX_LEN_38DD_P_2 */
8971   {
8972     { VEX_W_TABLE (VEX_W_38DD_P_2) },
8973   },
8974
8975   /* VEX_LEN_38DE_P_2 */
8976   {
8977     { VEX_W_TABLE (VEX_W_38DE_P_2) },
8978   },
8979
8980   /* VEX_LEN_38DF_P_2 */
8981   {
8982     { VEX_W_TABLE (VEX_W_38DF_P_2) },
8983   },
8984
8985   /* VEX_LEN_3A06_P_2 */
8986   {
8987     { Bad_Opcode },
8988     { VEX_W_TABLE (VEX_W_3A06_P_2) },
8989   },
8990
8991   /* VEX_LEN_3A0A_P_2 */
8992   {
8993     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8994     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8995   },
8996
8997   /* VEX_LEN_3A0B_P_2 */
8998   {
8999     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9000     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
9001   },
9002
9003   /* VEX_LEN_3A0E_P_2 */
9004   {
9005     { VEX_W_TABLE (VEX_W_3A0E_P_2) },
9006   },
9007
9008   /* VEX_LEN_3A0F_P_2 */
9009   {
9010     { VEX_W_TABLE (VEX_W_3A0F_P_2) },
9011   },
9012
9013   /* VEX_LEN_3A14_P_2 */
9014   {
9015     { VEX_W_TABLE (VEX_W_3A14_P_2) },
9016   },
9017
9018   /* VEX_LEN_3A15_P_2 */
9019   {
9020     { VEX_W_TABLE (VEX_W_3A15_P_2) },
9021   },
9022
9023   /* VEX_LEN_3A16_P_2  */
9024   {
9025     { "vpextrK",        { Edq, XM, Ib } },
9026   },
9027
9028   /* VEX_LEN_3A17_P_2 */
9029   {
9030     { "vextractps",     { Edqd, XM, Ib } },
9031   },
9032
9033   /* VEX_LEN_3A18_P_2 */
9034   {
9035     { Bad_Opcode },
9036     { VEX_W_TABLE (VEX_W_3A18_P_2) },
9037   },
9038
9039   /* VEX_LEN_3A19_P_2 */
9040   {
9041     { Bad_Opcode },
9042     { VEX_W_TABLE (VEX_W_3A19_P_2) },
9043   },
9044
9045   /* VEX_LEN_3A20_P_2 */
9046   {
9047     { VEX_W_TABLE (VEX_W_3A20_P_2) },
9048   },
9049
9050   /* VEX_LEN_3A21_P_2 */
9051   {
9052     { VEX_W_TABLE (VEX_W_3A21_P_2) },
9053   },
9054
9055   /* VEX_LEN_3A22_P_2 */
9056   {
9057     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
9058   },
9059
9060   /* VEX_LEN_3A41_P_2 */
9061   {
9062     { VEX_W_TABLE (VEX_W_3A41_P_2) },
9063   },
9064
9065   /* VEX_LEN_3A42_P_2 */
9066   {
9067     { VEX_W_TABLE (VEX_W_3A42_P_2) },
9068   },
9069
9070   /* VEX_LEN_3A44_P_2 */
9071   {
9072     { VEX_W_TABLE (VEX_W_3A44_P_2) },
9073   },
9074
9075   /* VEX_LEN_3A4C_P_2 */
9076   {
9077     { VEX_W_TABLE (VEX_W_3A4C_P_2) },
9078   },
9079
9080   /* VEX_LEN_3A60_P_2 */
9081   {
9082     { VEX_W_TABLE (VEX_W_3A60_P_2) },
9083   },
9084
9085   /* VEX_LEN_3A61_P_2 */
9086   {
9087     { VEX_W_TABLE (VEX_W_3A61_P_2) },
9088   },
9089
9090   /* VEX_LEN_3A62_P_2 */
9091   {
9092     { VEX_W_TABLE (VEX_W_3A62_P_2) },
9093   },
9094
9095   /* VEX_LEN_3A63_P_2 */
9096   {
9097     { VEX_W_TABLE (VEX_W_3A63_P_2) },
9098   },
9099
9100   /* VEX_LEN_3A6A_P_2 */
9101   {
9102     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9103   },
9104
9105   /* VEX_LEN_3A6B_P_2 */
9106   {
9107     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9108   },
9109
9110   /* VEX_LEN_3A6E_P_2 */
9111   {
9112     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9113   },
9114
9115   /* VEX_LEN_3A6F_P_2 */
9116   {
9117     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9118   },
9119
9120   /* VEX_LEN_3A7A_P_2 */
9121   {
9122     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9123   },
9124
9125   /* VEX_LEN_3A7B_P_2 */
9126   {
9127     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9128   },
9129
9130   /* VEX_LEN_3A7E_P_2 */
9131   {
9132     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9133   },
9134
9135   /* VEX_LEN_3A7F_P_2 */
9136   {
9137     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9138   },
9139
9140   /* VEX_LEN_3ADF_P_2 */
9141   {
9142     { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9143   },
9144
9145   /* VEX_LEN_XOP_09_80 */
9146   {
9147     { "vfrczps",        { XM, EXxmm } },
9148     { "vfrczps",        { XM, EXymmq } },
9149   },
9150
9151   /* VEX_LEN_XOP_09_81 */
9152   {
9153     { "vfrczpd",        { XM, EXxmm } },
9154     { "vfrczpd",        { XM, EXymmq } },
9155   },
9156 };
9157
9158 static const struct dis386 vex_w_table[][2] = {
9159   {
9160     /* VEX_W_10_P_0 */
9161     { "vmovups",        { XM, EXx } },
9162   },
9163   {
9164     /* VEX_W_10_P_1 */
9165     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
9166   },
9167   {
9168     /* VEX_W_10_P_2 */
9169     { "vmovupd",        { XM, EXx } },
9170   },
9171   {
9172     /* VEX_W_10_P_3 */
9173     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
9174   },
9175   {
9176     /* VEX_W_11_P_0 */
9177     { "vmovups",        { EXxS, XM } },
9178   },
9179   {
9180     /* VEX_W_11_P_1 */
9181     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
9182   },
9183   {
9184     /* VEX_W_11_P_2 */
9185     { "vmovupd",        { EXxS, XM } },
9186   },
9187   {
9188     /* VEX_W_11_P_3 */
9189     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
9190   },
9191   {
9192     /* VEX_W_12_P_0_M_0 */
9193     { "vmovlps",        { XM, Vex128, EXq } },
9194   },
9195   {
9196     /* VEX_W_12_P_0_M_1 */
9197     { "vmovhlps",       { XM, Vex128, EXq } },
9198   },
9199   {
9200     /* VEX_W_12_P_1 */
9201     { "vmovsldup",      { XM, EXx } },
9202   },
9203   {
9204     /* VEX_W_12_P_2 */
9205     { "vmovlpd",        { XM, Vex128, EXq } },
9206   },
9207   {
9208     /* VEX_W_12_P_3 */
9209     { "vmovddup",       { XM, EXymmq } },
9210   },
9211   {
9212     /* VEX_W_13_M_0 */
9213     { "vmovlpX",        { EXq, XM } },
9214   },
9215   {
9216     /* VEX_W_14 */
9217     { "vunpcklpX",      { XM, Vex, EXx } },
9218   },
9219   {
9220     /* VEX_W_15 */
9221     { "vunpckhpX",      { XM, Vex, EXx } },
9222   },
9223   {
9224     /* VEX_W_16_P_0_M_0 */
9225     { "vmovhps",        { XM, Vex128, EXq } },
9226   },
9227   {
9228     /* VEX_W_16_P_0_M_1 */
9229     { "vmovlhps",       { XM, Vex128, EXq } },
9230   },
9231   {
9232     /* VEX_W_16_P_1 */
9233     { "vmovshdup",      { XM, EXx } },
9234   },
9235   {
9236     /* VEX_W_16_P_2 */
9237     { "vmovhpd",        { XM, Vex128, EXq } },
9238   },
9239   {
9240     /* VEX_W_17_M_0 */
9241     { "vmovhpX",        { EXq, XM } },
9242   },
9243   {
9244     /* VEX_W_28 */
9245     { "vmovapX",        { XM, EXx } },
9246   },
9247   {
9248     /* VEX_W_29 */
9249     { "vmovapX",        { EXxS, XM } },
9250   },
9251   {
9252     /* VEX_W_2B_M_0 */
9253     { "vmovntpX",       { Mx, XM } },
9254   },
9255   {
9256     /* VEX_W_2E_P_0 */
9257     { "vucomiss",       { XMScalar, EXdScalar } },
9258   },
9259   {
9260     /* VEX_W_2E_P_2 */
9261     { "vucomisd",       { XMScalar, EXqScalar } },
9262   },
9263   {
9264     /* VEX_W_2F_P_0 */
9265     { "vcomiss",        { XMScalar, EXdScalar } },
9266   },
9267   {
9268     /* VEX_W_2F_P_2 */
9269     { "vcomisd",        { XMScalar, EXqScalar } },
9270   },
9271   {
9272     /* VEX_W_50_M_0 */
9273     { "vmovmskpX",      { Gdq, XS } },
9274   },
9275   {
9276     /* VEX_W_51_P_0 */
9277     { "vsqrtps",        { XM, EXx } },
9278   },
9279   {
9280     /* VEX_W_51_P_1 */
9281     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
9282   },
9283   {
9284     /* VEX_W_51_P_2  */
9285     { "vsqrtpd",        { XM, EXx } },
9286   },
9287   {
9288     /* VEX_W_51_P_3 */
9289     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
9290   },
9291   {
9292     /* VEX_W_52_P_0 */
9293     { "vrsqrtps",       { XM, EXx } },
9294   },
9295   {
9296     /* VEX_W_52_P_1 */
9297     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
9298   },
9299   {
9300     /* VEX_W_53_P_0  */
9301     { "vrcpps",         { XM, EXx } },
9302   },
9303   {
9304     /* VEX_W_53_P_1  */
9305     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
9306   },
9307   {
9308     /* VEX_W_58_P_0  */
9309     { "vaddps",         { XM, Vex, EXx } },
9310   },
9311   {
9312     /* VEX_W_58_P_1  */
9313     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
9314   },
9315   {
9316     /* VEX_W_58_P_2  */
9317     { "vaddpd",         { XM, Vex, EXx } },
9318   },
9319   {
9320     /* VEX_W_58_P_3  */
9321     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
9322   },
9323   {
9324     /* VEX_W_59_P_0  */
9325     { "vmulps",         { XM, Vex, EXx } },
9326   },
9327   {
9328     /* VEX_W_59_P_1  */
9329     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
9330   },
9331   {
9332     /* VEX_W_59_P_2  */
9333     { "vmulpd",         { XM, Vex, EXx } },
9334   },
9335   {
9336     /* VEX_W_59_P_3  */
9337     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
9338   },
9339   {
9340     /* VEX_W_5A_P_0  */
9341     { "vcvtps2pd",      { XM, EXxmmq } },
9342   },
9343   {
9344     /* VEX_W_5A_P_1  */
9345     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
9346   },
9347   {
9348     /* VEX_W_5A_P_3  */
9349     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
9350   },
9351   {
9352     /* VEX_W_5B_P_0  */
9353     { "vcvtdq2ps",      { XM, EXx } },
9354   },
9355   {
9356     /* VEX_W_5B_P_1  */
9357     { "vcvttps2dq",     { XM, EXx } },
9358   },
9359   {
9360     /* VEX_W_5B_P_2  */
9361     { "vcvtps2dq",      { XM, EXx } },
9362   },
9363   {
9364     /* VEX_W_5C_P_0  */
9365     { "vsubps",         { XM, Vex, EXx } },
9366   },
9367   {
9368     /* VEX_W_5C_P_1  */
9369     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
9370   },
9371   {
9372     /* VEX_W_5C_P_2  */
9373     { "vsubpd",         { XM, Vex, EXx } },
9374   },
9375   {
9376     /* VEX_W_5C_P_3  */
9377     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
9378   },
9379   {
9380     /* VEX_W_5D_P_0  */
9381     { "vminps",         { XM, Vex, EXx } },
9382   },
9383   {
9384     /* VEX_W_5D_P_1  */
9385     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
9386   },
9387   {
9388     /* VEX_W_5D_P_2  */
9389     { "vminpd",         { XM, Vex, EXx } },
9390   },
9391   {
9392     /* VEX_W_5D_P_3  */
9393     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
9394   },
9395   {
9396     /* VEX_W_5E_P_0  */
9397     { "vdivps",         { XM, Vex, EXx } },
9398   },
9399   {
9400     /* VEX_W_5E_P_1  */
9401     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
9402   },
9403   {
9404     /* VEX_W_5E_P_2  */
9405     { "vdivpd",         { XM, Vex, EXx } },
9406   },
9407   {
9408     /* VEX_W_5E_P_3  */
9409     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
9410   },
9411   {
9412     /* VEX_W_5F_P_0  */
9413     { "vmaxps",         { XM, Vex, EXx } },
9414   },
9415   {
9416     /* VEX_W_5F_P_1  */
9417     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
9418   },
9419   {
9420     /* VEX_W_5F_P_2  */
9421     { "vmaxpd",         { XM, Vex, EXx } },
9422   },
9423   {
9424     /* VEX_W_5F_P_3  */
9425     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
9426   },
9427   {
9428     /* VEX_W_60_P_2  */
9429     { "vpunpcklbw",     { XM, Vex128, EXx } },
9430   },
9431   {
9432     /* VEX_W_61_P_2  */
9433     { "vpunpcklwd",     { XM, Vex128, EXx } },
9434   },
9435   {
9436     /* VEX_W_62_P_2  */
9437     { "vpunpckldq",     { XM, Vex128, EXx } },
9438   },
9439   {
9440     /* VEX_W_63_P_2  */
9441     { "vpacksswb",      { XM, Vex128, EXx } },
9442   },
9443   {
9444     /* VEX_W_64_P_2  */
9445     { "vpcmpgtb",       { XM, Vex128, EXx } },
9446   },
9447   {
9448     /* VEX_W_65_P_2  */
9449     { "vpcmpgtw",       { XM, Vex128, EXx } },
9450   },
9451   {
9452     /* VEX_W_66_P_2  */
9453     { "vpcmpgtd",       { XM, Vex128, EXx } },
9454   },
9455   {
9456     /* VEX_W_67_P_2  */
9457     { "vpackuswb",      { XM, Vex128, EXx } },
9458   },
9459   {
9460     /* VEX_W_68_P_2  */
9461     { "vpunpckhbw",     { XM, Vex128, EXx } },
9462   },
9463   {
9464     /* VEX_W_69_P_2  */
9465     { "vpunpckhwd",     { XM, Vex128, EXx } },
9466   },
9467   {
9468     /* VEX_W_6A_P_2  */
9469     { "vpunpckhdq",     { XM, Vex128, EXx } },
9470   },
9471   {
9472     /* VEX_W_6B_P_2  */
9473     { "vpackssdw",      { XM, Vex128, EXx } },
9474   },
9475   {
9476     /* VEX_W_6C_P_2  */
9477     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9478   },
9479   {
9480     /* VEX_W_6D_P_2  */
9481     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9482   },
9483   {
9484     /* VEX_W_6F_P_1  */
9485     { "vmovdqu",        { XM, EXx } },
9486   },
9487   {
9488     /* VEX_W_6F_P_2  */
9489     { "vmovdqa",        { XM, EXx } },
9490   },
9491   {
9492     /* VEX_W_70_P_1 */
9493     { "vpshufhw",       { XM, EXx, Ib } },
9494   },
9495   {
9496     /* VEX_W_70_P_2 */
9497     { "vpshufd",        { XM, EXx, Ib } },
9498   },
9499   {
9500     /* VEX_W_70_P_3 */
9501     { "vpshuflw",       { XM, EXx, Ib } },
9502   },
9503   {
9504     /* VEX_W_71_R_2_P_2  */
9505     { "vpsrlw",         { Vex128, XS, Ib } },
9506   },
9507   {
9508     /* VEX_W_71_R_4_P_2  */
9509     { "vpsraw",         { Vex128, XS, Ib } },
9510   },
9511   {
9512     /* VEX_W_71_R_6_P_2  */
9513     { "vpsllw",         { Vex128, XS, Ib } },
9514   },
9515   {
9516     /* VEX_W_72_R_2_P_2  */
9517     { "vpsrld",         { Vex128, XS, Ib } },
9518   },
9519   {
9520     /* VEX_W_72_R_4_P_2  */
9521     { "vpsrad",         { Vex128, XS, Ib } },
9522   },
9523   {
9524     /* VEX_W_72_R_6_P_2  */
9525     { "vpslld",         { Vex128, XS, Ib } },
9526   },
9527   {
9528     /* VEX_W_73_R_2_P_2  */
9529     { "vpsrlq",         { Vex128, XS, Ib } },
9530   },
9531   {
9532     /* VEX_W_73_R_3_P_2  */
9533     { "vpsrldq",        { Vex128, XS, Ib } },
9534   },
9535   {
9536     /* VEX_W_73_R_6_P_2  */
9537     { "vpsllq",         { Vex128, XS, Ib } },
9538   },
9539   {
9540     /* VEX_W_73_R_7_P_2  */
9541     { "vpslldq",        { Vex128, XS, Ib } },
9542   },
9543   {
9544     /* VEX_W_74_P_2 */
9545     { "vpcmpeqb",       { XM, Vex128, EXx } },
9546   },
9547   {
9548     /* VEX_W_75_P_2 */
9549     { "vpcmpeqw",       { XM, Vex128, EXx } },
9550   },
9551   {
9552     /* VEX_W_76_P_2 */
9553     { "vpcmpeqd",       { XM, Vex128, EXx } },
9554   },
9555   {
9556     /* VEX_W_77_P_0 */
9557     { "",               { VZERO } },
9558   },
9559   {
9560     /* VEX_W_7C_P_2 */
9561     { "vhaddpd",        { XM, Vex, EXx } },
9562   },
9563   {
9564     /* VEX_W_7C_P_3 */
9565     { "vhaddps",        { XM, Vex, EXx } },
9566   },
9567   {
9568     /* VEX_W_7D_P_2 */
9569     { "vhsubpd",        { XM, Vex, EXx } },
9570   },
9571   {
9572     /* VEX_W_7D_P_3 */
9573     { "vhsubps",        { XM, Vex, EXx } },
9574   },
9575   {
9576     /* VEX_W_7E_P_1 */
9577     { "vmovq",          { XMScalar, EXqScalar } },
9578   },
9579   {
9580     /* VEX_W_7F_P_1 */
9581     { "vmovdqu",        { EXxS, XM } },
9582   },
9583   {
9584     /* VEX_W_7F_P_2 */
9585     { "vmovdqa",        { EXxS, XM } },
9586   },
9587   {
9588     /* VEX_W_AE_R_2_M_0 */
9589     { "vldmxcsr",       { Md } },
9590   },
9591   {
9592     /* VEX_W_AE_R_3_M_0 */
9593     { "vstmxcsr",       { Md } },
9594   },
9595   {
9596     /* VEX_W_C2_P_0 */
9597     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9598   },
9599   {
9600     /* VEX_W_C2_P_1 */
9601     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
9602   },
9603   {
9604     /* VEX_W_C2_P_2 */
9605     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9606   },
9607   {
9608     /* VEX_W_C2_P_3 */
9609     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
9610   },
9611   {
9612     /* VEX_W_C4_P_2 */
9613     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9614   },
9615   {
9616     /* VEX_W_C5_P_2 */
9617     { "vpextrw",        { Gdq, XS, Ib } },
9618   },
9619   {
9620     /* VEX_W_D0_P_2 */
9621     { "vaddsubpd",      { XM, Vex, EXx } },
9622   },
9623   {
9624     /* VEX_W_D0_P_3 */
9625     { "vaddsubps",      { XM, Vex, EXx } },
9626   },
9627   {
9628     /* VEX_W_D1_P_2 */
9629     { "vpsrlw",         { XM, Vex128, EXx } },
9630   },
9631   {
9632     /* VEX_W_D2_P_2 */
9633     { "vpsrld",         { XM, Vex128, EXx } },
9634   },
9635   {
9636     /* VEX_W_D3_P_2 */
9637     { "vpsrlq",         { XM, Vex128, EXx } },
9638   },
9639   {
9640     /* VEX_W_D4_P_2 */
9641     { "vpaddq",         { XM, Vex128, EXx } },
9642   },
9643   {
9644     /* VEX_W_D5_P_2 */
9645     { "vpmullw",        { XM, Vex128, EXx } },
9646   },
9647   {
9648     /* VEX_W_D6_P_2 */
9649     { "vmovq",          { EXqScalarS, XMScalar } },
9650   },
9651   {
9652     /* VEX_W_D7_P_2_M_1 */
9653     { "vpmovmskb",      { Gdq, XS } },
9654   },
9655   {
9656     /* VEX_W_D8_P_2 */
9657     { "vpsubusb",       { XM, Vex128, EXx } },
9658   },
9659   {
9660     /* VEX_W_D9_P_2 */
9661     { "vpsubusw",       { XM, Vex128, EXx } },
9662   },
9663   {
9664     /* VEX_W_DA_P_2 */
9665     { "vpminub",        { XM, Vex128, EXx } },
9666   },
9667   {
9668     /* VEX_W_DB_P_2 */
9669     { "vpand",          { XM, Vex128, EXx } },
9670   },
9671   {
9672     /* VEX_W_DC_P_2 */
9673     { "vpaddusb",       { XM, Vex128, EXx } },
9674   },
9675   {
9676     /* VEX_W_DD_P_2 */
9677     { "vpaddusw",       { XM, Vex128, EXx } },
9678   },
9679   {
9680     /* VEX_W_DE_P_2 */
9681     { "vpmaxub",        { XM, Vex128, EXx } },
9682   },
9683   {
9684     /* VEX_W_DF_P_2 */
9685     { "vpandn",         { XM, Vex128, EXx } },
9686   },
9687   {
9688     /* VEX_W_E0_P_2  */
9689     { "vpavgb",         { XM, Vex128, EXx } },
9690   },
9691   {
9692     /* VEX_W_E1_P_2  */
9693     { "vpsraw",         { XM, Vex128, EXx } },
9694   },
9695   {
9696     /* VEX_W_E2_P_2  */
9697     { "vpsrad",         { XM, Vex128, EXx } },
9698   },
9699   {
9700     /* VEX_W_E3_P_2  */
9701     { "vpavgw",         { XM, Vex128, EXx } },
9702   },
9703   {
9704     /* VEX_W_E4_P_2  */
9705     { "vpmulhuw",       { XM, Vex128, EXx } },
9706   },
9707   {
9708     /* VEX_W_E5_P_2  */
9709     { "vpmulhw",        { XM, Vex128, EXx } },
9710   },
9711   {
9712     /* VEX_W_E6_P_1  */
9713     { "vcvtdq2pd",      { XM, EXxmmq } },
9714   },
9715   {
9716     /* VEX_W_E6_P_2  */
9717     { "vcvttpd2dq%XY",  { XMM, EXx } },
9718   },
9719   {
9720     /* VEX_W_E6_P_3  */
9721     { "vcvtpd2dq%XY",   { XMM, EXx } },
9722   },
9723   {
9724     /* VEX_W_E7_P_2_M_0 */
9725     { "vmovntdq",       { Mx, XM } },
9726   },
9727   {
9728     /* VEX_W_E8_P_2  */
9729     { "vpsubsb",        { XM, Vex128, EXx } },
9730   },
9731   {
9732     /* VEX_W_E9_P_2  */
9733     { "vpsubsw",        { XM, Vex128, EXx } },
9734   },
9735   {
9736     /* VEX_W_EA_P_2  */
9737     { "vpminsw",        { XM, Vex128, EXx } },
9738   },
9739   {
9740     /* VEX_W_EB_P_2  */
9741     { "vpor",           { XM, Vex128, EXx } },
9742   },
9743   {
9744     /* VEX_W_EC_P_2  */
9745     { "vpaddsb",        { XM, Vex128, EXx } },
9746   },
9747   {
9748     /* VEX_W_ED_P_2  */
9749     { "vpaddsw",        { XM, Vex128, EXx } },
9750   },
9751   {
9752     /* VEX_W_EE_P_2  */
9753     { "vpmaxsw",        { XM, Vex128, EXx } },
9754   },
9755   {
9756     /* VEX_W_EF_P_2  */
9757     { "vpxor",          { XM, Vex128, EXx } },
9758   },
9759   {
9760     /* VEX_W_F0_P_3_M_0 */
9761     { "vlddqu",         { XM, M } },
9762   },
9763   {
9764     /* VEX_W_F1_P_2 */
9765     { "vpsllw",         { XM, Vex128, EXx } },
9766   },
9767   {
9768     /* VEX_W_F2_P_2 */
9769     { "vpslld",         { XM, Vex128, EXx } },
9770   },
9771   {
9772     /* VEX_W_F3_P_2 */
9773     { "vpsllq",         { XM, Vex128, EXx } },
9774   },
9775   {
9776     /* VEX_W_F4_P_2 */
9777     { "vpmuludq",       { XM, Vex128, EXx } },
9778   },
9779   {
9780     /* VEX_W_F5_P_2 */
9781     { "vpmaddwd",       { XM, Vex128, EXx } },
9782   },
9783   {
9784     /* VEX_W_F6_P_2 */
9785     { "vpsadbw",        { XM, Vex128, EXx } },
9786   },
9787   {
9788     /* VEX_W_F7_P_2 */
9789     { "vmaskmovdqu",    { XM, XS } },
9790   },
9791   {
9792     /* VEX_W_F8_P_2 */
9793     { "vpsubb",         { XM, Vex128, EXx } },
9794   },
9795   {
9796     /* VEX_W_F9_P_2 */
9797     { "vpsubw",         { XM, Vex128, EXx } },
9798   },
9799   {
9800     /* VEX_W_FA_P_2 */
9801     { "vpsubd",         { XM, Vex128, EXx } },
9802   },
9803   {
9804     /* VEX_W_FB_P_2 */
9805     { "vpsubq",         { XM, Vex128, EXx } },
9806   },
9807   {
9808     /* VEX_W_FC_P_2 */
9809     { "vpaddb",         { XM, Vex128, EXx } },
9810   },
9811   {
9812     /* VEX_W_FD_P_2 */
9813     { "vpaddw",         { XM, Vex128, EXx } },
9814   },
9815   {
9816     /* VEX_W_FE_P_2 */
9817     { "vpaddd",         { XM, Vex128, EXx } },
9818   },
9819   {
9820     /* VEX_W_3800_P_2  */
9821     { "vpshufb",        { XM, Vex128, EXx } },
9822   },
9823   {
9824     /* VEX_W_3801_P_2  */
9825     { "vphaddw",        { XM, Vex128, EXx } },
9826   },
9827   {
9828     /* VEX_W_3802_P_2  */
9829     { "vphaddd",        { XM, Vex128, EXx } },
9830   },
9831   {
9832     /* VEX_W_3803_P_2  */
9833     { "vphaddsw",       { XM, Vex128, EXx } },
9834   },
9835   {
9836     /* VEX_W_3804_P_2  */
9837     { "vpmaddubsw",     { XM, Vex128, EXx } },
9838   },
9839   {
9840     /* VEX_W_3805_P_2  */
9841     { "vphsubw",        { XM, Vex128, EXx } },
9842   },
9843   {
9844     /* VEX_W_3806_P_2  */
9845     { "vphsubd",        { XM, Vex128, EXx } },
9846   },
9847   {
9848     /* VEX_W_3807_P_2  */
9849     { "vphsubsw",       { XM, Vex128, EXx } },
9850   },
9851   {
9852     /* VEX_W_3808_P_2  */
9853     { "vpsignb",        { XM, Vex128, EXx } },
9854   },
9855   {
9856     /* VEX_W_3809_P_2  */
9857     { "vpsignw",        { XM, Vex128, EXx } },
9858   },
9859   {
9860     /* VEX_W_380A_P_2  */
9861     { "vpsignd",        { XM, Vex128, EXx } },
9862   },
9863   {
9864     /* VEX_W_380B_P_2  */
9865     { "vpmulhrsw",      { XM, Vex128, EXx } },
9866   },
9867   {
9868     /* VEX_W_380C_P_2  */
9869     { "vpermilps",      { XM, Vex, EXx } },
9870   },
9871   {
9872     /* VEX_W_380D_P_2  */
9873     { "vpermilpd",      { XM, Vex, EXx } },
9874   },
9875   {
9876     /* VEX_W_380E_P_2  */
9877     { "vtestps",        { XM, EXx } },
9878   },
9879   {
9880     /* VEX_W_380F_P_2  */
9881     { "vtestpd",        { XM, EXx } },
9882   },
9883   {
9884     /* VEX_W_3817_P_2 */
9885     { "vptest",         { XM, EXx } },
9886   },
9887   {
9888     /* VEX_W_3818_P_2_M_0 */
9889     { "vbroadcastss",   { XM, Md } },
9890   },
9891   {
9892     /* VEX_W_3819_P_2_M_0 */
9893     { "vbroadcastsd",   { XM, Mq } },
9894   },
9895   {
9896     /* VEX_W_381A_P_2_M_0 */
9897     { "vbroadcastf128", { XM, Mxmm } },
9898   },
9899   {
9900     /* VEX_W_381C_P_2 */
9901     { "vpabsb",         { XM, EXx } },
9902   },
9903   {
9904     /* VEX_W_381D_P_2 */
9905     { "vpabsw",         { XM, EXx } },
9906   },
9907   {
9908     /* VEX_W_381E_P_2 */
9909     { "vpabsd",         { XM, EXx } },
9910   },
9911   {
9912     /* VEX_W_3820_P_2 */
9913     { "vpmovsxbw",      { XM, EXq } },
9914   },
9915   {
9916     /* VEX_W_3821_P_2 */
9917     { "vpmovsxbd",      { XM, EXd } },
9918   },
9919   {
9920     /* VEX_W_3822_P_2 */
9921     { "vpmovsxbq",      { XM, EXw } },
9922   },
9923   {
9924     /* VEX_W_3823_P_2 */
9925     { "vpmovsxwd",      { XM, EXq } },
9926   },
9927   {
9928     /* VEX_W_3824_P_2 */
9929     { "vpmovsxwq",      { XM, EXd } },
9930   },
9931   {
9932     /* VEX_W_3825_P_2 */
9933     { "vpmovsxdq",      { XM, EXq } },
9934   },
9935   {
9936     /* VEX_W_3828_P_2 */
9937     { "vpmuldq",        { XM, Vex128, EXx } },
9938   },
9939   {
9940     /* VEX_W_3829_P_2 */
9941     { "vpcmpeqq",       { XM, Vex128, EXx } },
9942   },
9943   {
9944     /* VEX_W_382A_P_2_M_0 */
9945     { "vmovntdqa",      { XM, Mx } },
9946   },
9947   {
9948     /* VEX_W_382B_P_2 */
9949     { "vpackusdw",      { XM, Vex128, EXx } },
9950   },
9951   {
9952     /* VEX_W_382C_P_2_M_0 */
9953     { "vmaskmovps",     { XM, Vex, Mx } },
9954   },
9955   {
9956     /* VEX_W_382D_P_2_M_0 */
9957     { "vmaskmovpd",     { XM, Vex, Mx } },
9958   },
9959   {
9960     /* VEX_W_382E_P_2_M_0 */
9961     { "vmaskmovps",     { Mx, Vex, XM } },
9962   },
9963   {
9964     /* VEX_W_382F_P_2_M_0 */
9965     { "vmaskmovpd",     { Mx, Vex, XM } },
9966   },
9967   {
9968     /* VEX_W_3830_P_2 */
9969     { "vpmovzxbw",      { XM, EXq } },
9970   },
9971   {
9972     /* VEX_W_3831_P_2 */
9973     { "vpmovzxbd",      { XM, EXd } },
9974   },
9975   {
9976     /* VEX_W_3832_P_2 */
9977     { "vpmovzxbq",      { XM, EXw } },
9978   },
9979   {
9980     /* VEX_W_3833_P_2 */
9981     { "vpmovzxwd",      { XM, EXq } },
9982   },
9983   {
9984     /* VEX_W_3834_P_2 */
9985     { "vpmovzxwq",      { XM, EXd } },
9986   },
9987   {
9988     /* VEX_W_3835_P_2 */
9989     { "vpmovzxdq",      { XM, EXq } },
9990   },
9991   {
9992     /* VEX_W_3837_P_2 */
9993     { "vpcmpgtq",       { XM, Vex128, EXx } },
9994   },
9995   {
9996     /* VEX_W_3838_P_2 */
9997     { "vpminsb",        { XM, Vex128, EXx } },
9998   },
9999   {
10000     /* VEX_W_3839_P_2 */
10001     { "vpminsd",        { XM, Vex128, EXx } },
10002   },
10003   {
10004     /* VEX_W_383A_P_2 */
10005     { "vpminuw",        { XM, Vex128, EXx } },
10006   },
10007   {
10008     /* VEX_W_383B_P_2 */
10009     { "vpminud",        { XM, Vex128, EXx } },
10010   },
10011   {
10012     /* VEX_W_383C_P_2 */
10013     { "vpmaxsb",        { XM, Vex128, EXx } },
10014   },
10015   {
10016     /* VEX_W_383D_P_2 */
10017     { "vpmaxsd",        { XM, Vex128, EXx } },
10018   },
10019   {
10020     /* VEX_W_383E_P_2 */
10021     { "vpmaxuw",        { XM, Vex128, EXx } },
10022   },
10023   {
10024     /* VEX_W_383F_P_2 */
10025     { "vpmaxud",        { XM, Vex128, EXx } },
10026   },
10027   {
10028     /* VEX_W_3840_P_2 */
10029     { "vpmulld",        { XM, Vex128, EXx } },
10030   },
10031   {
10032     /* VEX_W_3841_P_2 */
10033     { "vphminposuw",    { XM, EXx } },
10034   },
10035   {
10036     /* VEX_W_38DB_P_2 */
10037     { "vaesimc",        { XM, EXx } },
10038   },
10039   {
10040     /* VEX_W_38DC_P_2 */
10041     { "vaesenc",        { XM, Vex128, EXx } },
10042   },
10043   {
10044     /* VEX_W_38DD_P_2 */
10045     { "vaesenclast",    { XM, Vex128, EXx } },
10046   },
10047   {
10048     /* VEX_W_38DE_P_2 */
10049     { "vaesdec",        { XM, Vex128, EXx } },
10050   },
10051   {
10052     /* VEX_W_38DF_P_2 */
10053     { "vaesdeclast",    { XM, Vex128, EXx } },
10054   },
10055   {
10056     /* VEX_W_3A04_P_2 */
10057     { "vpermilps",      { XM, EXx, Ib } },
10058   },
10059   {
10060     /* VEX_W_3A05_P_2 */
10061     { "vpermilpd",      { XM, EXx, Ib } },
10062   },
10063   {
10064     /* VEX_W_3A06_P_2 */
10065     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
10066   },
10067   {
10068     /* VEX_W_3A08_P_2 */
10069     { "vroundps",       { XM, EXx, Ib } },
10070   },
10071   {
10072     /* VEX_W_3A09_P_2 */
10073     { "vroundpd",       { XM, EXx, Ib } },
10074   },
10075   {
10076     /* VEX_W_3A0A_P_2 */
10077     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
10078   },
10079   {
10080     /* VEX_W_3A0B_P_2 */
10081     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
10082   },
10083   {
10084     /* VEX_W_3A0C_P_2 */
10085     { "vblendps",       { XM, Vex, EXx, Ib } },
10086   },
10087   {
10088     /* VEX_W_3A0D_P_2 */
10089     { "vblendpd",       { XM, Vex, EXx, Ib } },
10090   },
10091   {
10092     /* VEX_W_3A0E_P_2 */
10093     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10094   },
10095   {
10096     /* VEX_W_3A0F_P_2 */
10097     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10098   },
10099   {
10100     /* VEX_W_3A14_P_2 */
10101     { "vpextrb",        { Edqb, XM, Ib } },
10102   },
10103   {
10104     /* VEX_W_3A15_P_2 */
10105     { "vpextrw",        { Edqw, XM, Ib } },
10106   },
10107   {
10108     /* VEX_W_3A18_P_2 */
10109     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10110   },
10111   {
10112     /* VEX_W_3A19_P_2 */
10113     { "vextractf128",   { EXxmm, XM, Ib } },
10114   },
10115   {
10116     /* VEX_W_3A20_P_2 */
10117     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10118   },
10119   {
10120     /* VEX_W_3A21_P_2 */
10121     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10122   },
10123   {
10124     /* VEX_W_3A40_P_2 */
10125     { "vdpps",          { XM, Vex, EXx, Ib } },
10126   },
10127   {
10128     /* VEX_W_3A41_P_2 */
10129     { "vdppd",          { XM, Vex128, EXx, Ib } },
10130   },
10131   {
10132     /* VEX_W_3A42_P_2 */
10133     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10134   },
10135   {
10136     /* VEX_W_3A44_P_2 */
10137     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10138   },
10139   {
10140     /* VEX_W_3A48_P_2 */
10141     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10142     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10143   },
10144   {
10145     /* VEX_W_3A49_P_2 */
10146     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10147     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10148   },
10149   {
10150     /* VEX_W_3A4A_P_2 */
10151     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10152   },
10153   {
10154     /* VEX_W_3A4B_P_2 */
10155     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10156   },
10157   {
10158     /* VEX_W_3A4C_P_2 */
10159     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10160   },
10161   {
10162     /* VEX_W_3A60_P_2 */
10163     { "vpcmpestrm",     { XM, EXx, Ib } },
10164   },
10165   {
10166     /* VEX_W_3A61_P_2 */
10167     { "vpcmpestri",     { XM, EXx, Ib } },
10168   },
10169   {
10170     /* VEX_W_3A62_P_2 */
10171     { "vpcmpistrm",     { XM, EXx, Ib } },
10172   },
10173   {
10174     /* VEX_W_3A63_P_2 */
10175     { "vpcmpistri",     { XM, EXx, Ib } },
10176   },
10177   {
10178     /* VEX_W_3ADF_P_2 */
10179     { "vaeskeygenassist", { XM, EXx, Ib } },
10180   },
10181 };
10182
10183 static const struct dis386 mod_table[][2] = {
10184   {
10185     /* MOD_8D */
10186     { "leaS",           { Gv, M } },
10187   },
10188   {
10189     /* MOD_0F01_REG_0 */
10190     { X86_64_TABLE (X86_64_0F01_REG_0) },
10191     { RM_TABLE (RM_0F01_REG_0) },
10192   },
10193   {
10194     /* MOD_0F01_REG_1 */
10195     { X86_64_TABLE (X86_64_0F01_REG_1) },
10196     { RM_TABLE (RM_0F01_REG_1) },
10197   },
10198   {
10199     /* MOD_0F01_REG_2 */
10200     { X86_64_TABLE (X86_64_0F01_REG_2) },
10201     { RM_TABLE (RM_0F01_REG_2) },
10202   },
10203   {
10204     /* MOD_0F01_REG_3 */
10205     { X86_64_TABLE (X86_64_0F01_REG_3) },
10206     { RM_TABLE (RM_0F01_REG_3) },
10207   },
10208   {
10209     /* MOD_0F01_REG_7 */
10210     { "invlpg",         { Mb } },
10211     { RM_TABLE (RM_0F01_REG_7) },
10212   },
10213   {
10214     /* MOD_0F12_PREFIX_0 */
10215     { "movlps",         { XM, EXq } },
10216     { "movhlps",        { XM, EXq } },
10217   },
10218   {
10219     /* MOD_0F13 */
10220     { "movlpX",         { EXq, XM } },
10221   },
10222   {
10223     /* MOD_0F16_PREFIX_0 */
10224     { "movhps",         { XM, EXq } },
10225     { "movlhps",        { XM, EXq } },
10226   },
10227   {
10228     /* MOD_0F17 */
10229     { "movhpX",         { EXq, XM } },
10230   },
10231   {
10232     /* MOD_0F18_REG_0 */
10233     { "prefetchnta",    { Mb } },
10234   },
10235   {
10236     /* MOD_0F18_REG_1 */
10237     { "prefetcht0",     { Mb } },
10238   },
10239   {
10240     /* MOD_0F18_REG_2 */
10241     { "prefetcht1",     { Mb } },
10242   },
10243   {
10244     /* MOD_0F18_REG_3 */
10245     { "prefetcht2",     { Mb } },
10246   },
10247   {
10248     /* MOD_0F20 */
10249     { Bad_Opcode },
10250     { "movZ",           { Rm, Cm } },
10251   },
10252   {
10253     /* MOD_0F21 */
10254     { Bad_Opcode },
10255     { "movZ",           { Rm, Dm } },
10256   },
10257   {
10258     /* MOD_0F22 */
10259     { Bad_Opcode },
10260     { "movZ",           { Cm, Rm } },
10261   },
10262   {
10263     /* MOD_0F23 */
10264     { Bad_Opcode },
10265     { "movZ",           { Dm, Rm } },
10266   },
10267   {
10268     /* MOD_0F24 */
10269     { Bad_Opcode },
10270     { "movL",           { Rd, Td } },
10271   },
10272   {
10273     /* MOD_0F26 */
10274     { Bad_Opcode },
10275     { "movL",           { Td, Rd } },
10276   },
10277   {
10278     /* MOD_0F2B_PREFIX_0 */
10279     {"movntps",         { Mx, XM } },
10280   },
10281   {
10282     /* MOD_0F2B_PREFIX_1 */
10283     {"movntss",         { Md, XM } },
10284   },
10285   {
10286     /* MOD_0F2B_PREFIX_2 */
10287     {"movntpd",         { Mx, XM } },
10288   },
10289   {
10290     /* MOD_0F2B_PREFIX_3 */
10291     {"movntsd",         { Mq, XM } },
10292   },
10293   {
10294     /* MOD_0F51 */
10295     { Bad_Opcode },
10296     { "movmskpX",       { Gdq, XS } },
10297   },
10298   {
10299     /* MOD_0F71_REG_2 */
10300     { Bad_Opcode },
10301     { "psrlw",          { MS, Ib } },
10302   },
10303   {
10304     /* MOD_0F71_REG_4 */
10305     { Bad_Opcode },
10306     { "psraw",          { MS, Ib } },
10307   },
10308   {
10309     /* MOD_0F71_REG_6 */
10310     { Bad_Opcode },
10311     { "psllw",          { MS, Ib } },
10312   },
10313   {
10314     /* MOD_0F72_REG_2 */
10315     { Bad_Opcode },
10316     { "psrld",          { MS, Ib } },
10317   },
10318   {
10319     /* MOD_0F72_REG_4 */
10320     { Bad_Opcode },
10321     { "psrad",          { MS, Ib } },
10322   },
10323   {
10324     /* MOD_0F72_REG_6 */
10325     { Bad_Opcode },
10326     { "pslld",          { MS, Ib } },
10327   },
10328   {
10329     /* MOD_0F73_REG_2 */
10330     { Bad_Opcode },
10331     { "psrlq",          { MS, Ib } },
10332   },
10333   {
10334     /* MOD_0F73_REG_3 */
10335     { Bad_Opcode },
10336     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10337   },
10338   {
10339     /* MOD_0F73_REG_6 */
10340     { Bad_Opcode },
10341     { "psllq",          { MS, Ib } },
10342   },
10343   {
10344     /* MOD_0F73_REG_7 */
10345     { Bad_Opcode },
10346     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10347   },
10348   {
10349     /* MOD_0FAE_REG_0 */
10350     { "fxsave",         { FXSAVE } },
10351   },
10352   {
10353     /* MOD_0FAE_REG_1 */
10354     { "fxrstor",        { FXSAVE } },
10355   },
10356   {
10357     /* MOD_0FAE_REG_2 */
10358     { "ldmxcsr",        { Md } },
10359   },
10360   {
10361     /* MOD_0FAE_REG_3 */
10362     { "stmxcsr",        { Md } },
10363   },
10364   {
10365     /* MOD_0FAE_REG_4 */
10366     { "xsave",          { FXSAVE } },
10367   },
10368   {
10369     /* MOD_0FAE_REG_5 */
10370     { "xrstor",         { FXSAVE } },
10371     { RM_TABLE (RM_0FAE_REG_5) },
10372   },
10373   {
10374     /* MOD_0FAE_REG_6 */
10375     { Bad_Opcode },
10376     { RM_TABLE (RM_0FAE_REG_6) },
10377   },
10378   {
10379     /* MOD_0FAE_REG_7 */
10380     { "clflush",        { Mb } },
10381     { RM_TABLE (RM_0FAE_REG_7) },
10382   },
10383   {
10384     /* MOD_0FB2 */
10385     { "lssS",           { Gv, Mp } },
10386   },
10387   {
10388     /* MOD_0FB4 */
10389     { "lfsS",           { Gv, Mp } },
10390   },
10391   {
10392     /* MOD_0FB5 */
10393     { "lgsS",           { Gv, Mp } },
10394   },
10395   {
10396     /* MOD_0FC7_REG_6 */
10397     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10398   },
10399   {
10400     /* MOD_0FC7_REG_7 */
10401     { "vmptrst",        { Mq } },
10402   },
10403   {
10404     /* MOD_0FD7 */
10405     { Bad_Opcode },
10406     { "pmovmskb",       { Gdq, MS } },
10407   },
10408   {
10409     /* MOD_0FE7_PREFIX_2 */
10410     { "movntdq",        { Mx, XM } },
10411   },
10412   {
10413     /* MOD_0FF0_PREFIX_3 */
10414     { "lddqu",          { XM, M } },
10415   },
10416   {
10417     /* MOD_0F382A_PREFIX_2 */
10418     { "movntdqa",       { XM, Mx } },
10419   },
10420   {
10421     /* MOD_62_32BIT */
10422     { "bound{S|}",      { Gv, Ma } },
10423   },
10424   {
10425     /* MOD_C4_32BIT */
10426     { "lesS",           { Gv, Mp } },
10427     { VEX_C4_TABLE (VEX_0F) },
10428   },
10429   {
10430     /* MOD_C5_32BIT */
10431     { "ldsS",           { Gv, Mp } },
10432     { VEX_C5_TABLE (VEX_0F) },
10433   },
10434   {
10435     /* MOD_VEX_12_PREFIX_0 */
10436     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10437     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10438   },
10439   {
10440     /* MOD_VEX_13 */
10441     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10442   },
10443   {
10444     /* MOD_VEX_16_PREFIX_0 */
10445     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10446     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10447   },
10448   {
10449     /* MOD_VEX_17 */
10450     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10451   },
10452   {
10453     /* MOD_VEX_2B */
10454     { VEX_W_TABLE (VEX_W_2B_M_0) },
10455   },
10456   {
10457     /* MOD_VEX_50 */
10458     { Bad_Opcode },
10459     { VEX_W_TABLE (VEX_W_50_M_0) },
10460   },
10461   {
10462     /* MOD_VEX_71_REG_2 */
10463     { Bad_Opcode },
10464     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10465   },
10466   {
10467     /* MOD_VEX_71_REG_4 */
10468     { Bad_Opcode },
10469     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10470   },
10471   {
10472     /* MOD_VEX_71_REG_6 */
10473     { Bad_Opcode },
10474     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10475   },
10476   {
10477     /* MOD_VEX_72_REG_2 */
10478     { Bad_Opcode },
10479     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10480   },
10481   {
10482     /* MOD_VEX_72_REG_4 */
10483     { Bad_Opcode },
10484     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10485   },
10486   {
10487     /* MOD_VEX_72_REG_6 */
10488     { Bad_Opcode },
10489     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10490   },
10491   {
10492     /* MOD_VEX_73_REG_2 */
10493     { Bad_Opcode },
10494     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10495   },
10496   {
10497     /* MOD_VEX_73_REG_3 */
10498     { Bad_Opcode },
10499     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10500   },
10501   {
10502     /* MOD_VEX_73_REG_6 */
10503     { Bad_Opcode },
10504     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10505   },
10506   {
10507     /* MOD_VEX_73_REG_7 */
10508     { Bad_Opcode },
10509     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10510   },
10511   {
10512     /* MOD_VEX_AE_REG_2 */
10513     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10514   },
10515   {
10516     /* MOD_VEX_AE_REG_3 */
10517     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10518   },
10519   {
10520     /* MOD_VEX_D7_PREFIX_2 */
10521     { Bad_Opcode },
10522     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10523   },
10524   {
10525     /* MOD_VEX_E7_PREFIX_2 */
10526     { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10527   },
10528   {
10529     /* MOD_VEX_F0_PREFIX_3 */
10530     { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10531   },
10532   {
10533     /* MOD_VEX_3818_PREFIX_2 */
10534     { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10535   },
10536   {
10537     /* MOD_VEX_3819_PREFIX_2 */
10538     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10539   },
10540   {
10541     /* MOD_VEX_381A_PREFIX_2 */
10542     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10543   },
10544   {
10545     /* MOD_VEX_382A_PREFIX_2 */
10546     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10547   },
10548   {
10549     /* MOD_VEX_382C_PREFIX_2 */
10550     { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10551   },
10552   {
10553     /* MOD_VEX_382D_PREFIX_2 */
10554     { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10555   },
10556   {
10557     /* MOD_VEX_382E_PREFIX_2 */
10558     { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10559   },
10560   {
10561     /* MOD_VEX_382F_PREFIX_2 */
10562     { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10563   },
10564 };
10565
10566 static const struct dis386 rm_table[][8] = {
10567   {
10568     /* RM_0F01_REG_0 */
10569     { Bad_Opcode },
10570     { "vmcall",         { Skip_MODRM } },
10571     { "vmlaunch",       { Skip_MODRM } },
10572     { "vmresume",       { Skip_MODRM } },
10573     { "vmxoff",         { Skip_MODRM } },
10574   },
10575   {
10576     /* RM_0F01_REG_1 */
10577     { "monitor",        { { OP_Monitor, 0 } } },
10578     { "mwait",          { { OP_Mwait, 0 } } },
10579   },
10580   {
10581     /* RM_0F01_REG_2 */
10582     { "xgetbv",         { Skip_MODRM } },
10583     { "xsetbv",         { Skip_MODRM } },
10584   },
10585   {
10586     /* RM_0F01_REG_3 */
10587     { "vmrun",          { Skip_MODRM } },
10588     { "vmmcall",        { Skip_MODRM } },
10589     { "vmload",         { Skip_MODRM } },
10590     { "vmsave",         { Skip_MODRM } },
10591     { "stgi",           { Skip_MODRM } },
10592     { "clgi",           { Skip_MODRM } },
10593     { "skinit",         { Skip_MODRM } },
10594     { "invlpga",        { Skip_MODRM } },
10595   },
10596   {
10597     /* RM_0F01_REG_7 */
10598     { "swapgs",         { Skip_MODRM } },
10599     { "rdtscp",         { Skip_MODRM } },
10600   },
10601   {
10602     /* RM_0FAE_REG_5 */
10603     { "lfence",         { Skip_MODRM } },
10604   },
10605   {
10606     /* RM_0FAE_REG_6 */
10607     { "mfence",         { Skip_MODRM } },
10608   },
10609   {
10610     /* RM_0FAE_REG_7 */
10611     { "sfence",         { Skip_MODRM } },
10612   },
10613 };
10614
10615 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10616
10617 /* We use the high bit to indicate different name for the same
10618    prefix.  */
10619 #define ADDR16_PREFIX   (0x67 | 0x100)
10620 #define ADDR32_PREFIX   (0x67 | 0x200)
10621 #define DATA16_PREFIX   (0x66 | 0x100)
10622 #define DATA32_PREFIX   (0x66 | 0x200)
10623 #define REP_PREFIX      (0xf3 | 0x100)
10624
10625 static int
10626 ckprefix (void)
10627 {
10628   int newrex, i, length;
10629   rex = 0;
10630   rex_ignored = 0;
10631   prefixes = 0;
10632   used_prefixes = 0;
10633   rex_used = 0;
10634   last_lock_prefix = -1;
10635   last_repz_prefix = -1;
10636   last_repnz_prefix = -1;
10637   last_data_prefix = -1;
10638   last_addr_prefix = -1;
10639   last_rex_prefix = -1;
10640   last_seg_prefix = -1;
10641   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10642     all_prefixes[i] = 0;
10643   i = 0;
10644   length = 0;
10645   /* The maximum instruction length is 15bytes.  */
10646   while (length < MAX_CODE_LENGTH - 1)
10647     {
10648       FETCH_DATA (the_info, codep + 1);
10649       newrex = 0;
10650       switch (*codep)
10651         {
10652         /* REX prefixes family.  */
10653         case 0x40:
10654         case 0x41:
10655         case 0x42:
10656         case 0x43:
10657         case 0x44:
10658         case 0x45:
10659         case 0x46:
10660         case 0x47:
10661         case 0x48:
10662         case 0x49:
10663         case 0x4a:
10664         case 0x4b:
10665         case 0x4c:
10666         case 0x4d:
10667         case 0x4e:
10668         case 0x4f:
10669           if (address_mode == mode_64bit)
10670             newrex = *codep;
10671           else
10672             return 1;
10673           last_rex_prefix = i;
10674           break;
10675         case 0xf3:
10676           prefixes |= PREFIX_REPZ;
10677           last_repz_prefix = i;
10678           break;
10679         case 0xf2:
10680           prefixes |= PREFIX_REPNZ;
10681           last_repnz_prefix = i;
10682           break;
10683         case 0xf0:
10684           prefixes |= PREFIX_LOCK;
10685           last_lock_prefix = i;
10686           break;
10687         case 0x2e:
10688           prefixes |= PREFIX_CS;
10689           last_seg_prefix = i;
10690           break;
10691         case 0x36:
10692           prefixes |= PREFIX_SS;
10693           last_seg_prefix = i;
10694           break;
10695         case 0x3e:
10696           prefixes |= PREFIX_DS;
10697           last_seg_prefix = i;
10698           break;
10699         case 0x26:
10700           prefixes |= PREFIX_ES;
10701           last_seg_prefix = i;
10702           break;
10703         case 0x64:
10704           prefixes |= PREFIX_FS;
10705           last_seg_prefix = i;
10706           break;
10707         case 0x65:
10708           prefixes |= PREFIX_GS;
10709           last_seg_prefix = i;
10710           break;
10711         case 0x66:
10712           prefixes |= PREFIX_DATA;
10713           last_data_prefix = i;
10714           break;
10715         case 0x67:
10716           prefixes |= PREFIX_ADDR;
10717           last_addr_prefix = i;
10718           break;
10719         case FWAIT_OPCODE:
10720           /* fwait is really an instruction.  If there are prefixes
10721              before the fwait, they belong to the fwait, *not* to the
10722              following instruction.  */
10723           if (prefixes || rex)
10724             {
10725               prefixes |= PREFIX_FWAIT;
10726               codep++;
10727               return 1;
10728             }
10729           prefixes = PREFIX_FWAIT;
10730           break;
10731         default:
10732           return 1;
10733         }
10734       /* Rex is ignored when followed by another prefix.  */
10735       if (rex)
10736         {
10737           rex_used = rex;
10738           return 1;
10739         }
10740       if (*codep != FWAIT_OPCODE)
10741         all_prefixes[i++] = *codep;
10742       rex = newrex;
10743       codep++;
10744       length++;
10745     }
10746   return 0;
10747 }
10748
10749 static int
10750 seg_prefix (int pref)
10751 {
10752   switch (pref)
10753     {
10754     case 0x2e:
10755       return PREFIX_CS;
10756     case 0x36:
10757       return PREFIX_SS;
10758     case 0x3e:
10759       return PREFIX_DS;
10760     case 0x26:
10761       return PREFIX_ES;
10762     case 0x64:
10763       return PREFIX_FS;
10764     case 0x65:
10765       return PREFIX_GS;
10766     default:
10767       return 0;
10768     }
10769 }
10770
10771 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10772    prefix byte.  */
10773
10774 static const char *
10775 prefix_name (int pref, int sizeflag)
10776 {
10777   static const char *rexes [16] =
10778     {
10779       "rex",            /* 0x40 */
10780       "rex.B",          /* 0x41 */
10781       "rex.X",          /* 0x42 */
10782       "rex.XB",         /* 0x43 */
10783       "rex.R",          /* 0x44 */
10784       "rex.RB",         /* 0x45 */
10785       "rex.RX",         /* 0x46 */
10786       "rex.RXB",        /* 0x47 */
10787       "rex.W",          /* 0x48 */
10788       "rex.WB",         /* 0x49 */
10789       "rex.WX",         /* 0x4a */
10790       "rex.WXB",        /* 0x4b */
10791       "rex.WR",         /* 0x4c */
10792       "rex.WRB",        /* 0x4d */
10793       "rex.WRX",        /* 0x4e */
10794       "rex.WRXB",       /* 0x4f */
10795     };
10796
10797   switch (pref)
10798     {
10799     /* REX prefixes family.  */
10800     case 0x40:
10801     case 0x41:
10802     case 0x42:
10803     case 0x43:
10804     case 0x44:
10805     case 0x45:
10806     case 0x46:
10807     case 0x47:
10808     case 0x48:
10809     case 0x49:
10810     case 0x4a:
10811     case 0x4b:
10812     case 0x4c:
10813     case 0x4d:
10814     case 0x4e:
10815     case 0x4f:
10816       return rexes [pref - 0x40];
10817     case 0xf3:
10818       return "repz";
10819     case 0xf2:
10820       return "repnz";
10821     case 0xf0:
10822       return "lock";
10823     case 0x2e:
10824       return "cs";
10825     case 0x36:
10826       return "ss";
10827     case 0x3e:
10828       return "ds";
10829     case 0x26:
10830       return "es";
10831     case 0x64:
10832       return "fs";
10833     case 0x65:
10834       return "gs";
10835     case 0x66:
10836       return (sizeflag & DFLAG) ? "data16" : "data32";
10837     case 0x67:
10838       if (address_mode == mode_64bit)
10839         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10840       else
10841         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10842     case FWAIT_OPCODE:
10843       return "fwait";
10844     case ADDR16_PREFIX:
10845       return "addr16";
10846     case ADDR32_PREFIX:
10847       return "addr32";
10848     case DATA16_PREFIX:
10849       return "data16";
10850     case DATA32_PREFIX:
10851       return "data32";
10852     case REP_PREFIX:
10853       return "rep";
10854     default:
10855       return NULL;
10856     }
10857 }
10858
10859 static char op_out[MAX_OPERANDS][100];
10860 static int op_ad, op_index[MAX_OPERANDS];
10861 static int two_source_ops;
10862 static bfd_vma op_address[MAX_OPERANDS];
10863 static bfd_vma op_riprel[MAX_OPERANDS];
10864 static bfd_vma start_pc;
10865
10866 /*
10867  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10868  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10869  *   section of the "Virtual 8086 Mode" chapter.)
10870  * 'pc' should be the address of this instruction, it will
10871  *   be used to print the target address if this is a relative jump or call
10872  * The function returns the length of this instruction in bytes.
10873  */
10874
10875 static char intel_syntax;
10876 static char intel_mnemonic = !SYSV386_COMPAT;
10877 static char open_char;
10878 static char close_char;
10879 static char separator_char;
10880 static char scale_char;
10881
10882 /* Here for backwards compatibility.  When gdb stops using
10883    print_insn_i386_att and print_insn_i386_intel these functions can
10884    disappear, and print_insn_i386 be merged into print_insn.  */
10885 int
10886 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10887 {
10888   intel_syntax = 0;
10889
10890   return print_insn (pc, info);
10891 }
10892
10893 int
10894 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10895 {
10896   intel_syntax = 1;
10897
10898   return print_insn (pc, info);
10899 }
10900
10901 int
10902 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10903 {
10904   intel_syntax = -1;
10905
10906   return print_insn (pc, info);
10907 }
10908
10909 void
10910 print_i386_disassembler_options (FILE *stream)
10911 {
10912   fprintf (stream, _("\n\
10913 The following i386/x86-64 specific disassembler options are supported for use\n\
10914 with the -M switch (multiple options should be separated by commas):\n"));
10915
10916   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10917   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10918   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10919   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10920   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10921   fprintf (stream, _("  att-mnemonic\n"
10922                      "              Display instruction in AT&T mnemonic\n"));
10923   fprintf (stream, _("  intel-mnemonic\n"
10924                      "              Display instruction in Intel mnemonic\n"));
10925   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10926   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10927   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10928   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10929   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10930   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10931 }
10932
10933 /* Bad opcode.  */
10934 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10935
10936 /* Get a pointer to struct dis386 with a valid name.  */
10937
10938 static const struct dis386 *
10939 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10940 {
10941   int vindex, vex_table_index;
10942
10943   if (dp->name != NULL)
10944     return dp;
10945
10946   switch (dp->op[0].bytemode)
10947     {
10948     case USE_REG_TABLE:
10949       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10950       break;
10951
10952     case USE_MOD_TABLE:
10953       vindex = modrm.mod == 0x3 ? 1 : 0;
10954       dp = &mod_table[dp->op[1].bytemode][vindex];
10955       break;
10956
10957     case USE_RM_TABLE:
10958       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10959       break;
10960
10961     case USE_PREFIX_TABLE:
10962       if (need_vex)
10963         {
10964           /* The prefix in VEX is implicit.  */
10965           switch (vex.prefix)
10966             {
10967             case 0:
10968               vindex = 0;
10969               break;
10970             case REPE_PREFIX_OPCODE:
10971               vindex = 1;
10972               break;
10973             case DATA_PREFIX_OPCODE:
10974               vindex = 2;
10975               break;
10976             case REPNE_PREFIX_OPCODE:
10977               vindex = 3;
10978               break;
10979             default:
10980               abort ();
10981               break;
10982             }
10983         }
10984       else
10985         {
10986           vindex = 0;
10987           used_prefixes |= (prefixes & PREFIX_REPZ);
10988           if (prefixes & PREFIX_REPZ)
10989             {
10990               vindex = 1;
10991               all_prefixes[last_repz_prefix] = 0;
10992             }
10993           else
10994             {
10995               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10996                  PREFIX_DATA.  */
10997               used_prefixes |= (prefixes & PREFIX_REPNZ);
10998               if (prefixes & PREFIX_REPNZ)
10999                 {
11000                   vindex = 3;
11001                   all_prefixes[last_repnz_prefix] = 0;
11002                 }
11003               else
11004                 {
11005                   used_prefixes |= (prefixes & PREFIX_DATA);
11006                   if (prefixes & PREFIX_DATA)
11007                     {
11008                       vindex = 2;
11009                       all_prefixes[last_data_prefix] = 0;
11010                     }
11011                 }
11012             }
11013         }
11014       dp = &prefix_table[dp->op[1].bytemode][vindex];
11015       break;
11016
11017     case USE_X86_64_TABLE:
11018       vindex = address_mode == mode_64bit ? 1 : 0;
11019       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11020       break;
11021
11022     case USE_3BYTE_TABLE:
11023       FETCH_DATA (info, codep + 2);
11024       vindex = *codep++;
11025       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11026       modrm.mod = (*codep >> 6) & 3;
11027       modrm.reg = (*codep >> 3) & 7;
11028       modrm.rm = *codep & 7;
11029       break;
11030
11031     case USE_VEX_LEN_TABLE:
11032       if (!need_vex)
11033         abort ();
11034
11035       switch (vex.length)
11036         {
11037         case 128:
11038           vindex = 0;
11039           break;
11040         case 256:
11041           vindex = 1;
11042           break;
11043         default:
11044           abort ();
11045           break;
11046         }
11047
11048       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11049       break;
11050
11051     case USE_XOP_8F_TABLE:
11052       FETCH_DATA (info, codep + 3);
11053       /* All bits in the REX prefix are ignored.  */
11054       rex_ignored = rex;
11055       rex = ~(*codep >> 5) & 0x7;
11056
11057       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11058       switch ((*codep & 0x1f))
11059         {
11060         default:
11061           BadOp ();
11062         case 0x8:
11063           vex_table_index = XOP_08;
11064           break;
11065         case 0x9:
11066           vex_table_index = XOP_09;
11067           break;
11068         case 0xa:
11069           vex_table_index = XOP_0A;
11070           break;
11071         }
11072       codep++;
11073       vex.w = *codep & 0x80;
11074       if (vex.w && address_mode == mode_64bit)
11075         rex |= REX_W;
11076
11077       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11078       if (address_mode != mode_64bit
11079           && vex.register_specifier > 0x7)
11080         BadOp ();
11081
11082       vex.length = (*codep & 0x4) ? 256 : 128;
11083       switch ((*codep & 0x3))
11084         {
11085         case 0:
11086           vex.prefix = 0;
11087           break;
11088         case 1:
11089           vex.prefix = DATA_PREFIX_OPCODE;
11090           break;
11091         case 2:
11092           vex.prefix = REPE_PREFIX_OPCODE;
11093           break;
11094         case 3:
11095           vex.prefix = REPNE_PREFIX_OPCODE;
11096           break;
11097         }
11098       need_vex = 1;
11099       need_vex_reg = 1;
11100       codep++;
11101       vindex = *codep++;
11102       dp = &xop_table[vex_table_index][vindex];
11103
11104       FETCH_DATA (info, codep + 1);
11105       modrm.mod = (*codep >> 6) & 3;
11106       modrm.reg = (*codep >> 3) & 7;
11107       modrm.rm = *codep & 7;
11108       break;
11109
11110     case USE_VEX_C4_TABLE:
11111       FETCH_DATA (info, codep + 3);
11112       /* All bits in the REX prefix are ignored.  */
11113       rex_ignored = rex;
11114       rex = ~(*codep >> 5) & 0x7;
11115       switch ((*codep & 0x1f))
11116         {
11117         default:
11118           BadOp ();
11119         case 0x1:
11120           vex_table_index = VEX_0F;
11121           break;
11122         case 0x2:
11123           vex_table_index = VEX_0F38;
11124           break;
11125         case 0x3:
11126           vex_table_index = VEX_0F3A;
11127           break;
11128         }
11129       codep++;
11130       vex.w = *codep & 0x80;
11131       if (vex.w && address_mode == mode_64bit)
11132         rex |= REX_W;
11133
11134       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11135       if (address_mode != mode_64bit
11136           && vex.register_specifier > 0x7)
11137         BadOp ();
11138
11139       vex.length = (*codep & 0x4) ? 256 : 128;
11140       switch ((*codep & 0x3))
11141         {
11142         case 0:
11143           vex.prefix = 0;
11144           break;
11145         case 1:
11146           vex.prefix = DATA_PREFIX_OPCODE;
11147           break;
11148         case 2:
11149           vex.prefix = REPE_PREFIX_OPCODE;
11150           break;
11151         case 3:
11152           vex.prefix = REPNE_PREFIX_OPCODE;
11153           break;
11154         }
11155       need_vex = 1;
11156       need_vex_reg = 1;
11157       codep++;
11158       vindex = *codep++;
11159       dp = &vex_table[vex_table_index][vindex];
11160       /* There is no MODRM byte for VEX [82|77].  */
11161       if (vindex != 0x77 && vindex != 0x82)
11162         {
11163           FETCH_DATA (info, codep + 1);
11164           modrm.mod = (*codep >> 6) & 3;
11165           modrm.reg = (*codep >> 3) & 7;
11166           modrm.rm = *codep & 7;
11167         }
11168       break;
11169
11170     case USE_VEX_C5_TABLE:
11171       FETCH_DATA (info, codep + 2);
11172       /* All bits in the REX prefix are ignored.  */
11173       rex_ignored = rex;
11174       rex = (*codep & 0x80) ? 0 : REX_R;
11175
11176       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11177       if (address_mode != mode_64bit
11178           && vex.register_specifier > 0x7)
11179         BadOp ();
11180
11181       vex.w = 0;
11182
11183       vex.length = (*codep & 0x4) ? 256 : 128;
11184       switch ((*codep & 0x3))
11185         {
11186         case 0:
11187           vex.prefix = 0;
11188           break;
11189         case 1:
11190           vex.prefix = DATA_PREFIX_OPCODE;
11191           break;
11192         case 2:
11193           vex.prefix = REPE_PREFIX_OPCODE;
11194           break;
11195         case 3:
11196           vex.prefix = REPNE_PREFIX_OPCODE;
11197           break;
11198         }
11199       need_vex = 1;
11200       need_vex_reg = 1;
11201       codep++;
11202       vindex = *codep++;
11203       dp = &vex_table[dp->op[1].bytemode][vindex];
11204       /* There is no MODRM byte for VEX [82|77].  */
11205       if (vindex != 0x77 && vindex != 0x82)
11206         {
11207           FETCH_DATA (info, codep + 1);
11208           modrm.mod = (*codep >> 6) & 3;
11209           modrm.reg = (*codep >> 3) & 7;
11210           modrm.rm = *codep & 7;
11211         }
11212       break;
11213
11214     case USE_VEX_W_TABLE:
11215       if (!need_vex)
11216         abort ();
11217
11218       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11219       break;
11220
11221     case 0:
11222       dp = &bad_opcode;
11223       break;
11224
11225     default:
11226       abort ();
11227     }
11228
11229   if (dp->name != NULL)
11230     return dp;
11231   else
11232     return get_valid_dis386 (dp, info);
11233 }
11234
11235 static int
11236 print_insn (bfd_vma pc, disassemble_info *info)
11237 {
11238   const struct dis386 *dp;
11239   int i;
11240   char *op_txt[MAX_OPERANDS];
11241   int needcomma;
11242   int sizeflag;
11243   const char *p;
11244   struct dis_private priv;
11245   int prefix_length;
11246   int default_prefixes;
11247
11248   if (info->mach == bfd_mach_x86_64_intel_syntax
11249       || info->mach == bfd_mach_x86_64
11250       || info->mach == bfd_mach_l1om
11251       || info->mach == bfd_mach_l1om_intel_syntax)
11252     address_mode = mode_64bit;
11253   else
11254     address_mode = mode_32bit;
11255
11256   if (intel_syntax == (char) -1)
11257     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11258                     || info->mach == bfd_mach_x86_64_intel_syntax
11259                     || info->mach == bfd_mach_l1om_intel_syntax);
11260
11261   if (info->mach == bfd_mach_i386_i386
11262       || info->mach == bfd_mach_x86_64
11263       || info->mach == bfd_mach_l1om
11264       || info->mach == bfd_mach_i386_i386_intel_syntax
11265       || info->mach == bfd_mach_x86_64_intel_syntax
11266       || info->mach == bfd_mach_l1om_intel_syntax)
11267     priv.orig_sizeflag = AFLAG | DFLAG;
11268   else if (info->mach == bfd_mach_i386_i8086)
11269     priv.orig_sizeflag = 0;
11270   else
11271     abort ();
11272
11273   for (p = info->disassembler_options; p != NULL; )
11274     {
11275       if (CONST_STRNEQ (p, "x86-64"))
11276         {
11277           address_mode = mode_64bit;
11278           priv.orig_sizeflag = AFLAG | DFLAG;
11279         }
11280       else if (CONST_STRNEQ (p, "i386"))
11281         {
11282           address_mode = mode_32bit;
11283           priv.orig_sizeflag = AFLAG | DFLAG;
11284         }
11285       else if (CONST_STRNEQ (p, "i8086"))
11286         {
11287           address_mode = mode_16bit;
11288           priv.orig_sizeflag = 0;
11289         }
11290       else if (CONST_STRNEQ (p, "intel"))
11291         {
11292           intel_syntax = 1;
11293           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11294             intel_mnemonic = 1;
11295         }
11296       else if (CONST_STRNEQ (p, "att"))
11297         {
11298           intel_syntax = 0;
11299           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11300             intel_mnemonic = 0;
11301         }
11302       else if (CONST_STRNEQ (p, "addr"))
11303         {
11304           if (address_mode == mode_64bit)
11305             {
11306               if (p[4] == '3' && p[5] == '2')
11307                 priv.orig_sizeflag &= ~AFLAG;
11308               else if (p[4] == '6' && p[5] == '4')
11309                 priv.orig_sizeflag |= AFLAG;
11310             }
11311           else
11312             {
11313               if (p[4] == '1' && p[5] == '6')
11314                 priv.orig_sizeflag &= ~AFLAG;
11315               else if (p[4] == '3' && p[5] == '2')
11316                 priv.orig_sizeflag |= AFLAG;
11317             }
11318         }
11319       else if (CONST_STRNEQ (p, "data"))
11320         {
11321           if (p[4] == '1' && p[5] == '6')
11322             priv.orig_sizeflag &= ~DFLAG;
11323           else if (p[4] == '3' && p[5] == '2')
11324             priv.orig_sizeflag |= DFLAG;
11325         }
11326       else if (CONST_STRNEQ (p, "suffix"))
11327         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11328
11329       p = strchr (p, ',');
11330       if (p != NULL)
11331         p++;
11332     }
11333
11334   if (intel_syntax)
11335     {
11336       names64 = intel_names64;
11337       names32 = intel_names32;
11338       names16 = intel_names16;
11339       names8 = intel_names8;
11340       names8rex = intel_names8rex;
11341       names_seg = intel_names_seg;
11342       names_mm = intel_names_mm;
11343       names_xmm = intel_names_xmm;
11344       names_ymm = intel_names_ymm;
11345       index64 = intel_index64;
11346       index32 = intel_index32;
11347       index16 = intel_index16;
11348       open_char = '[';
11349       close_char = ']';
11350       separator_char = '+';
11351       scale_char = '*';
11352     }
11353   else
11354     {
11355       names64 = att_names64;
11356       names32 = att_names32;
11357       names16 = att_names16;
11358       names8 = att_names8;
11359       names8rex = att_names8rex;
11360       names_seg = att_names_seg;
11361       names_mm = att_names_mm;
11362       names_xmm = att_names_xmm;
11363       names_ymm = att_names_ymm;
11364       index64 = att_index64;
11365       index32 = att_index32;
11366       index16 = att_index16;
11367       open_char = '(';
11368       close_char =  ')';
11369       separator_char = ',';
11370       scale_char = ',';
11371     }
11372
11373   /* The output looks better if we put 7 bytes on a line, since that
11374      puts most long word instructions on a single line.  Use 8 bytes
11375      for Intel L1OM.  */
11376   if (info->mach == bfd_mach_l1om
11377       || info->mach == bfd_mach_l1om_intel_syntax)
11378     info->bytes_per_line = 8;
11379   else
11380     info->bytes_per_line = 7;
11381
11382   info->private_data = &priv;
11383   priv.max_fetched = priv.the_buffer;
11384   priv.insn_start = pc;
11385
11386   obuf[0] = 0;
11387   for (i = 0; i < MAX_OPERANDS; ++i)
11388     {
11389       op_out[i][0] = 0;
11390       op_index[i] = -1;
11391     }
11392
11393   the_info = info;
11394   start_pc = pc;
11395   start_codep = priv.the_buffer;
11396   codep = priv.the_buffer;
11397
11398   if (setjmp (priv.bailout) != 0)
11399     {
11400       const char *name;
11401
11402       /* Getting here means we tried for data but didn't get it.  That
11403          means we have an incomplete instruction of some sort.  Just
11404          print the first byte as a prefix or a .byte pseudo-op.  */
11405       if (codep > priv.the_buffer)
11406         {
11407           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11408           if (name != NULL)
11409             (*info->fprintf_func) (info->stream, "%s", name);
11410           else
11411             {
11412               /* Just print the first byte as a .byte instruction.  */
11413               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11414                                      (unsigned int) priv.the_buffer[0]);
11415             }
11416
11417           return 1;
11418         }
11419
11420       return -1;
11421     }
11422
11423   obufp = obuf;
11424   sizeflag = priv.orig_sizeflag;
11425
11426   if (!ckprefix () || rex_used)
11427     {
11428       /* Too many prefixes or unused REX prefixes.  */
11429       for (i = 0;
11430            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11431            i++)
11432         (*info->fprintf_func) (info->stream, "%s",
11433                                prefix_name (all_prefixes[i], sizeflag));
11434       return 1;
11435     }
11436
11437   insn_codep = codep;
11438
11439   FETCH_DATA (info, codep + 1);
11440   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11441
11442   if (((prefixes & PREFIX_FWAIT)
11443        && ((*codep < 0xd8) || (*codep > 0xdf))))
11444     {
11445       (*info->fprintf_func) (info->stream, "fwait");
11446       return 1;
11447     }
11448
11449   if (*codep == 0x0f)
11450     {
11451       unsigned char threebyte;
11452       FETCH_DATA (info, codep + 2);
11453       threebyte = *++codep;
11454       dp = &dis386_twobyte[threebyte];
11455       need_modrm = twobyte_has_modrm[*codep];
11456       codep++;
11457     }
11458   else
11459     {
11460       dp = &dis386[*codep];
11461       need_modrm = onebyte_has_modrm[*codep];
11462       codep++;
11463     }
11464
11465   if ((prefixes & PREFIX_REPZ))
11466     used_prefixes |= PREFIX_REPZ;
11467   if ((prefixes & PREFIX_REPNZ))
11468     used_prefixes |= PREFIX_REPNZ;
11469   if ((prefixes & PREFIX_LOCK))
11470     used_prefixes |= PREFIX_LOCK;
11471
11472   default_prefixes = 0;
11473   if (prefixes & PREFIX_ADDR)
11474     {
11475       sizeflag ^= AFLAG;
11476       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11477         {
11478           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11479             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11480           else
11481             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11482           default_prefixes |= PREFIX_ADDR;
11483         }
11484     }
11485
11486   if ((prefixes & PREFIX_DATA))
11487     {
11488       sizeflag ^= DFLAG;
11489       if (dp->op[2].bytemode == cond_jump_mode
11490           && dp->op[0].bytemode == v_mode
11491           && !intel_syntax)
11492         {
11493           if (sizeflag & DFLAG)
11494             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11495           else
11496             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11497           default_prefixes |= PREFIX_DATA;
11498         }
11499       else if (rex & REX_W)
11500         {
11501           /* REX_W will override PREFIX_DATA.  */
11502           default_prefixes |= PREFIX_DATA;
11503         }
11504     }
11505
11506   if (need_modrm)
11507     {
11508       FETCH_DATA (info, codep + 1);
11509       modrm.mod = (*codep >> 6) & 3;
11510       modrm.reg = (*codep >> 3) & 7;
11511       modrm.rm = *codep & 7;
11512     }
11513
11514    need_vex = 0;
11515    need_vex_reg = 0;
11516    vex_w_done = 0;
11517
11518   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11519     {
11520       dofloat (sizeflag);
11521     }
11522   else
11523     {
11524       dp = get_valid_dis386 (dp, info);
11525       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11526         {
11527           for (i = 0; i < MAX_OPERANDS; ++i)
11528             {
11529               obufp = op_out[i];
11530               op_ad = MAX_OPERANDS - 1 - i;
11531               if (dp->op[i].rtn)
11532                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11533             }
11534         }
11535     }
11536
11537   /* See if any prefixes were not used.  If so, print the first one
11538      separately.  If we don't do this, we'll wind up printing an
11539      instruction stream which does not precisely correspond to the
11540      bytes we are disassembling.  */
11541   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11542     {
11543       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11544         if (all_prefixes[i])
11545           {
11546             const char *name;
11547             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11548             if (name == NULL)
11549               name = INTERNAL_DISASSEMBLER_ERROR;
11550             (*info->fprintf_func) (info->stream, "%s", name);
11551             return 1;
11552           }
11553     }
11554
11555   /* Check if the REX prefix is used.  */
11556   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11557     all_prefixes[last_rex_prefix] = 0;
11558
11559   /* Check if the SEG prefix is used.  */
11560   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11561                    | PREFIX_FS | PREFIX_GS)) != 0
11562       && (used_prefixes
11563           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11564     all_prefixes[last_seg_prefix] = 0;
11565
11566   /* Check if the ADDR prefix is used.  */
11567   if ((prefixes & PREFIX_ADDR) != 0
11568       && (used_prefixes & PREFIX_ADDR) != 0)
11569     all_prefixes[last_addr_prefix] = 0;
11570
11571   /* Check if the DATA prefix is used.  */
11572   if ((prefixes & PREFIX_DATA) != 0
11573       && (used_prefixes & PREFIX_DATA) != 0)
11574     all_prefixes[last_data_prefix] = 0;
11575
11576   prefix_length = 0;
11577   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11578     if (all_prefixes[i])
11579       {
11580         const char *name;
11581         name = prefix_name (all_prefixes[i], sizeflag);
11582         if (name == NULL)
11583           abort ();
11584         prefix_length += strlen (name) + 1;
11585         (*info->fprintf_func) (info->stream, "%s ", name);
11586       }
11587
11588   /* Check maximum code length.  */
11589   if ((codep - start_codep) > MAX_CODE_LENGTH)
11590     {
11591       (*info->fprintf_func) (info->stream, "(bad)");
11592       return MAX_CODE_LENGTH;
11593     }
11594
11595   obufp = mnemonicendp;
11596   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11597     oappend (" ");
11598   oappend (" ");
11599   (*info->fprintf_func) (info->stream, "%s", obuf);
11600
11601   /* The enter and bound instructions are printed with operands in the same
11602      order as the intel book; everything else is printed in reverse order.  */
11603   if (intel_syntax || two_source_ops)
11604     {
11605       bfd_vma riprel;
11606
11607       for (i = 0; i < MAX_OPERANDS; ++i)
11608         op_txt[i] = op_out[i];
11609
11610       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11611         {
11612           op_ad = op_index[i];
11613           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11614           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11615           riprel = op_riprel[i];
11616           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11617           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11618         }
11619     }
11620   else
11621     {
11622       for (i = 0; i < MAX_OPERANDS; ++i)
11623         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11624     }
11625
11626   needcomma = 0;
11627   for (i = 0; i < MAX_OPERANDS; ++i)
11628     if (*op_txt[i])
11629       {
11630         if (needcomma)
11631           (*info->fprintf_func) (info->stream, ",");
11632         if (op_index[i] != -1 && !op_riprel[i])
11633           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11634         else
11635           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11636         needcomma = 1;
11637       }
11638
11639   for (i = 0; i < MAX_OPERANDS; i++)
11640     if (op_index[i] != -1 && op_riprel[i])
11641       {
11642         (*info->fprintf_func) (info->stream, "        # ");
11643         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11644                                                 + op_address[op_index[i]]), info);
11645         break;
11646       }
11647   return codep - priv.the_buffer;
11648 }
11649
11650 static const char *float_mem[] = {
11651   /* d8 */
11652   "fadd{s|}",
11653   "fmul{s|}",
11654   "fcom{s|}",
11655   "fcomp{s|}",
11656   "fsub{s|}",
11657   "fsubr{s|}",
11658   "fdiv{s|}",
11659   "fdivr{s|}",
11660   /* d9 */
11661   "fld{s|}",
11662   "(bad)",
11663   "fst{s|}",
11664   "fstp{s|}",
11665   "fldenvIC",
11666   "fldcw",
11667   "fNstenvIC",
11668   "fNstcw",
11669   /* da */
11670   "fiadd{l|}",
11671   "fimul{l|}",
11672   "ficom{l|}",
11673   "ficomp{l|}",
11674   "fisub{l|}",
11675   "fisubr{l|}",
11676   "fidiv{l|}",
11677   "fidivr{l|}",
11678   /* db */
11679   "fild{l|}",
11680   "fisttp{l|}",
11681   "fist{l|}",
11682   "fistp{l|}",
11683   "(bad)",
11684   "fld{t||t|}",
11685   "(bad)",
11686   "fstp{t||t|}",
11687   /* dc */
11688   "fadd{l|}",
11689   "fmul{l|}",
11690   "fcom{l|}",
11691   "fcomp{l|}",
11692   "fsub{l|}",
11693   "fsubr{l|}",
11694   "fdiv{l|}",
11695   "fdivr{l|}",
11696   /* dd */
11697   "fld{l|}",
11698   "fisttp{ll|}",
11699   "fst{l||}",
11700   "fstp{l|}",
11701   "frstorIC",
11702   "(bad)",
11703   "fNsaveIC",
11704   "fNstsw",
11705   /* de */
11706   "fiadd",
11707   "fimul",
11708   "ficom",
11709   "ficomp",
11710   "fisub",
11711   "fisubr",
11712   "fidiv",
11713   "fidivr",
11714   /* df */
11715   "fild",
11716   "fisttp",
11717   "fist",
11718   "fistp",
11719   "fbld",
11720   "fild{ll|}",
11721   "fbstp",
11722   "fistp{ll|}",
11723 };
11724
11725 static const unsigned char float_mem_mode[] = {
11726   /* d8 */
11727   d_mode,
11728   d_mode,
11729   d_mode,
11730   d_mode,
11731   d_mode,
11732   d_mode,
11733   d_mode,
11734   d_mode,
11735   /* d9 */
11736   d_mode,
11737   0,
11738   d_mode,
11739   d_mode,
11740   0,
11741   w_mode,
11742   0,
11743   w_mode,
11744   /* da */
11745   d_mode,
11746   d_mode,
11747   d_mode,
11748   d_mode,
11749   d_mode,
11750   d_mode,
11751   d_mode,
11752   d_mode,
11753   /* db */
11754   d_mode,
11755   d_mode,
11756   d_mode,
11757   d_mode,
11758   0,
11759   t_mode,
11760   0,
11761   t_mode,
11762   /* dc */
11763   q_mode,
11764   q_mode,
11765   q_mode,
11766   q_mode,
11767   q_mode,
11768   q_mode,
11769   q_mode,
11770   q_mode,
11771   /* dd */
11772   q_mode,
11773   q_mode,
11774   q_mode,
11775   q_mode,
11776   0,
11777   0,
11778   0,
11779   w_mode,
11780   /* de */
11781   w_mode,
11782   w_mode,
11783   w_mode,
11784   w_mode,
11785   w_mode,
11786   w_mode,
11787   w_mode,
11788   w_mode,
11789   /* df */
11790   w_mode,
11791   w_mode,
11792   w_mode,
11793   w_mode,
11794   t_mode,
11795   q_mode,
11796   t_mode,
11797   q_mode
11798 };
11799
11800 #define ST { OP_ST, 0 }
11801 #define STi { OP_STi, 0 }
11802
11803 #define FGRPd9_2 NULL, { { NULL, 0 } }
11804 #define FGRPd9_4 NULL, { { NULL, 1 } }
11805 #define FGRPd9_5 NULL, { { NULL, 2 } }
11806 #define FGRPd9_6 NULL, { { NULL, 3 } }
11807 #define FGRPd9_7 NULL, { { NULL, 4 } }
11808 #define FGRPda_5 NULL, { { NULL, 5 } }
11809 #define FGRPdb_4 NULL, { { NULL, 6 } }
11810 #define FGRPde_3 NULL, { { NULL, 7 } }
11811 #define FGRPdf_4 NULL, { { NULL, 8 } }
11812
11813 static const struct dis386 float_reg[][8] = {
11814   /* d8 */
11815   {
11816     { "fadd",   { ST, STi } },
11817     { "fmul",   { ST, STi } },
11818     { "fcom",   { STi } },
11819     { "fcomp",  { STi } },
11820     { "fsub",   { ST, STi } },
11821     { "fsubr",  { ST, STi } },
11822     { "fdiv",   { ST, STi } },
11823     { "fdivr",  { ST, STi } },
11824   },
11825   /* d9 */
11826   {
11827     { "fld",    { STi } },
11828     { "fxch",   { STi } },
11829     { FGRPd9_2 },
11830     { Bad_Opcode },
11831     { FGRPd9_4 },
11832     { FGRPd9_5 },
11833     { FGRPd9_6 },
11834     { FGRPd9_7 },
11835   },
11836   /* da */
11837   {
11838     { "fcmovb", { ST, STi } },
11839     { "fcmove", { ST, STi } },
11840     { "fcmovbe",{ ST, STi } },
11841     { "fcmovu", { ST, STi } },
11842     { Bad_Opcode },
11843     { FGRPda_5 },
11844     { Bad_Opcode },
11845     { Bad_Opcode },
11846   },
11847   /* db */
11848   {
11849     { "fcmovnb",{ ST, STi } },
11850     { "fcmovne",{ ST, STi } },
11851     { "fcmovnbe",{ ST, STi } },
11852     { "fcmovnu",{ ST, STi } },
11853     { FGRPdb_4 },
11854     { "fucomi", { ST, STi } },
11855     { "fcomi",  { ST, STi } },
11856     { Bad_Opcode },
11857   },
11858   /* dc */
11859   {
11860     { "fadd",   { STi, ST } },
11861     { "fmul",   { STi, ST } },
11862     { Bad_Opcode },
11863     { Bad_Opcode },
11864     { "fsub!M", { STi, ST } },
11865     { "fsubM",  { STi, ST } },
11866     { "fdiv!M", { STi, ST } },
11867     { "fdivM",  { STi, ST } },
11868   },
11869   /* dd */
11870   {
11871     { "ffree",  { STi } },
11872     { Bad_Opcode },
11873     { "fst",    { STi } },
11874     { "fstp",   { STi } },
11875     { "fucom",  { STi } },
11876     { "fucomp", { STi } },
11877     { Bad_Opcode },
11878     { Bad_Opcode },
11879   },
11880   /* de */
11881   {
11882     { "faddp",  { STi, ST } },
11883     { "fmulp",  { STi, ST } },
11884     { Bad_Opcode },
11885     { FGRPde_3 },
11886     { "fsub!Mp", { STi, ST } },
11887     { "fsubMp", { STi, ST } },
11888     { "fdiv!Mp", { STi, ST } },
11889     { "fdivMp", { STi, ST } },
11890   },
11891   /* df */
11892   {
11893     { "ffreep", { STi } },
11894     { Bad_Opcode },
11895     { Bad_Opcode },
11896     { Bad_Opcode },
11897     { FGRPdf_4 },
11898     { "fucomip", { ST, STi } },
11899     { "fcomip", { ST, STi } },
11900     { Bad_Opcode },
11901   },
11902 };
11903
11904 static char *fgrps[][8] = {
11905   /* d9_2  0 */
11906   {
11907     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11908   },
11909
11910   /* d9_4  1 */
11911   {
11912     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11913   },
11914
11915   /* d9_5  2 */
11916   {
11917     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11918   },
11919
11920   /* d9_6  3 */
11921   {
11922     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11923   },
11924
11925   /* d9_7  4 */
11926   {
11927     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11928   },
11929
11930   /* da_5  5 */
11931   {
11932     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11933   },
11934
11935   /* db_4  6 */
11936   {
11937     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11938     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11939   },
11940
11941   /* de_3  7 */
11942   {
11943     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11944   },
11945
11946   /* df_4  8 */
11947   {
11948     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11949   },
11950 };
11951
11952 static void
11953 swap_operand (void)
11954 {
11955   mnemonicendp[0] = '.';
11956   mnemonicendp[1] = 's';
11957   mnemonicendp += 2;
11958 }
11959
11960 static void
11961 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11962                int sizeflag ATTRIBUTE_UNUSED)
11963 {
11964   /* Skip mod/rm byte.  */
11965   MODRM_CHECK;
11966   codep++;
11967 }
11968
11969 static void
11970 dofloat (int sizeflag)
11971 {
11972   const struct dis386 *dp;
11973   unsigned char floatop;
11974
11975   floatop = codep[-1];
11976
11977   if (modrm.mod != 3)
11978     {
11979       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11980
11981       putop (float_mem[fp_indx], sizeflag);
11982       obufp = op_out[0];
11983       op_ad = 2;
11984       OP_E (float_mem_mode[fp_indx], sizeflag);
11985       return;
11986     }
11987   /* Skip mod/rm byte.  */
11988   MODRM_CHECK;
11989   codep++;
11990
11991   dp = &float_reg[floatop - 0xd8][modrm.reg];
11992   if (dp->name == NULL)
11993     {
11994       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11995
11996       /* Instruction fnstsw is only one with strange arg.  */
11997       if (floatop == 0xdf && codep[-1] == 0xe0)
11998         strcpy (op_out[0], names16[0]);
11999     }
12000   else
12001     {
12002       putop (dp->name, sizeflag);
12003
12004       obufp = op_out[0];
12005       op_ad = 2;
12006       if (dp->op[0].rtn)
12007         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12008
12009       obufp = op_out[1];
12010       op_ad = 1;
12011       if (dp->op[1].rtn)
12012         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12013     }
12014 }
12015
12016 static void
12017 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12018 {
12019   oappend ("%st" + intel_syntax);
12020 }
12021
12022 static void
12023 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12024 {
12025   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12026   oappend (scratchbuf + intel_syntax);
12027 }
12028
12029 /* Capital letters in template are macros.  */
12030 static int
12031 putop (const char *in_template, int sizeflag)
12032 {
12033   const char *p;
12034   int alt = 0;
12035   int cond = 1;
12036   unsigned int l = 0, len = 1;
12037   char last[4];
12038
12039 #define SAVE_LAST(c)                    \
12040   if (l < len && l < sizeof (last))     \
12041     last[l++] = c;                      \
12042   else                                  \
12043     abort ();
12044
12045   for (p = in_template; *p; p++)
12046     {
12047       switch (*p)
12048         {
12049         default:
12050           *obufp++ = *p;
12051           break;
12052         case '%':
12053           len++;
12054           break;
12055         case '!':
12056           cond = 0;
12057           break;
12058         case '{':
12059           alt = 0;
12060           if (intel_syntax)
12061             {
12062               while (*++p != '|')
12063                 if (*p == '}' || *p == '\0')
12064                   abort ();
12065             }
12066           /* Fall through.  */
12067         case 'I':
12068           alt = 1;
12069           continue;
12070         case '|':
12071           while (*++p != '}')
12072             {
12073               if (*p == '\0')
12074                 abort ();
12075             }
12076           break;
12077         case '}':
12078           break;
12079         case 'A':
12080           if (intel_syntax)
12081             break;
12082           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12083             *obufp++ = 'b';
12084           break;
12085         case 'B':
12086           if (l == 0 && len == 1)
12087             {
12088 case_B:
12089               if (intel_syntax)
12090                 break;
12091               if (sizeflag & SUFFIX_ALWAYS)
12092                 *obufp++ = 'b';
12093             }
12094           else
12095             {
12096               if (l != 1
12097                   || len != 2
12098                   || last[0] != 'L')
12099                 {
12100                   SAVE_LAST (*p);
12101                   break;
12102                 }
12103
12104               if (address_mode == mode_64bit
12105                   && !(prefixes & PREFIX_ADDR))
12106                 {
12107                   *obufp++ = 'a';
12108                   *obufp++ = 'b';
12109                   *obufp++ = 's';
12110                 }
12111
12112               goto case_B;
12113             }
12114           break;
12115         case 'C':
12116           if (intel_syntax && !alt)
12117             break;
12118           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12119             {
12120               if (sizeflag & DFLAG)
12121                 *obufp++ = intel_syntax ? 'd' : 'l';
12122               else
12123                 *obufp++ = intel_syntax ? 'w' : 's';
12124               used_prefixes |= (prefixes & PREFIX_DATA);
12125             }
12126           break;
12127         case 'D':
12128           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12129             break;
12130           USED_REX (REX_W);
12131           if (modrm.mod == 3)
12132             {
12133               if (rex & REX_W)
12134                 *obufp++ = 'q';
12135               else
12136                 {
12137                   if (sizeflag & DFLAG)
12138                     *obufp++ = intel_syntax ? 'd' : 'l';
12139                   else
12140                     *obufp++ = 'w';
12141                   used_prefixes |= (prefixes & PREFIX_DATA);
12142                 }
12143             }
12144           else
12145             *obufp++ = 'w';
12146           break;
12147         case 'E':               /* For jcxz/jecxz */
12148           if (address_mode == mode_64bit)
12149             {
12150               if (sizeflag & AFLAG)
12151                 *obufp++ = 'r';
12152               else
12153                 *obufp++ = 'e';
12154             }
12155           else
12156             if (sizeflag & AFLAG)
12157               *obufp++ = 'e';
12158           used_prefixes |= (prefixes & PREFIX_ADDR);
12159           break;
12160         case 'F':
12161           if (intel_syntax)
12162             break;
12163           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12164             {
12165               if (sizeflag & AFLAG)
12166                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12167               else
12168                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12169               used_prefixes |= (prefixes & PREFIX_ADDR);
12170             }
12171           break;
12172         case 'G':
12173           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12174             break;
12175           if ((rex & REX_W) || (sizeflag & DFLAG))
12176             *obufp++ = 'l';
12177           else
12178             *obufp++ = 'w';
12179           if (!(rex & REX_W))
12180             used_prefixes |= (prefixes & PREFIX_DATA);
12181           break;
12182         case 'H':
12183           if (intel_syntax)
12184             break;
12185           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12186               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12187             {
12188               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12189               *obufp++ = ',';
12190               *obufp++ = 'p';
12191               if (prefixes & PREFIX_DS)
12192                 *obufp++ = 't';
12193               else
12194                 *obufp++ = 'n';
12195             }
12196           break;
12197         case 'J':
12198           if (intel_syntax)
12199             break;
12200           *obufp++ = 'l';
12201           break;
12202         case 'K':
12203           USED_REX (REX_W);
12204           if (rex & REX_W)
12205             *obufp++ = 'q';
12206           else
12207             *obufp++ = 'd';
12208           break;
12209         case 'Z':
12210           if (intel_syntax)
12211             break;
12212           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12213             {
12214               *obufp++ = 'q';
12215               break;
12216             }
12217           /* Fall through.  */
12218           goto case_L;
12219         case 'L':
12220           if (l != 0 || len != 1)
12221             {
12222               SAVE_LAST (*p);
12223               break;
12224             }
12225 case_L:
12226           if (intel_syntax)
12227             break;
12228           if (sizeflag & SUFFIX_ALWAYS)
12229             *obufp++ = 'l';
12230           break;
12231         case 'M':
12232           if (intel_mnemonic != cond)
12233             *obufp++ = 'r';
12234           break;
12235         case 'N':
12236           if ((prefixes & PREFIX_FWAIT) == 0)
12237             *obufp++ = 'n';
12238           else
12239             used_prefixes |= PREFIX_FWAIT;
12240           break;
12241         case 'O':
12242           USED_REX (REX_W);
12243           if (rex & REX_W)
12244             *obufp++ = 'o';
12245           else if (intel_syntax && (sizeflag & DFLAG))
12246             *obufp++ = 'q';
12247           else
12248             *obufp++ = 'd';
12249           if (!(rex & REX_W))
12250             used_prefixes |= (prefixes & PREFIX_DATA);
12251           break;
12252         case 'T':
12253           if (intel_syntax)
12254             break;
12255           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12256             {
12257               *obufp++ = 'q';
12258               break;
12259             }
12260           /* Fall through.  */
12261         case 'P':
12262           if (intel_syntax)
12263             break;
12264           if ((prefixes & PREFIX_DATA)
12265               || (rex & REX_W)
12266               || (sizeflag & SUFFIX_ALWAYS))
12267             {
12268               USED_REX (REX_W);
12269               if (rex & REX_W)
12270                 *obufp++ = 'q';
12271               else
12272                 {
12273                    if (sizeflag & DFLAG)
12274                       *obufp++ = 'l';
12275                    else
12276                      *obufp++ = 'w';
12277                    used_prefixes |= (prefixes & PREFIX_DATA);
12278                 }
12279             }
12280           break;
12281         case 'U':
12282           if (intel_syntax)
12283             break;
12284           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12285             {
12286               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12287                 *obufp++ = 'q';
12288               break;
12289             }
12290           /* Fall through.  */
12291           goto case_Q;
12292         case 'Q':
12293           if (l == 0 && len == 1)
12294             {
12295 case_Q:
12296               if (intel_syntax && !alt)
12297                 break;
12298               USED_REX (REX_W);
12299               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12300                 {
12301                   if (rex & REX_W)
12302                     *obufp++ = 'q';
12303                   else
12304                     {
12305                       if (sizeflag & DFLAG)
12306                         *obufp++ = intel_syntax ? 'd' : 'l';
12307                       else
12308                         *obufp++ = 'w';
12309                       used_prefixes |= (prefixes & PREFIX_DATA);
12310                     }
12311                 }
12312             }
12313           else
12314             {
12315               if (l != 1 || len != 2 || last[0] != 'L')
12316                 {
12317                   SAVE_LAST (*p);
12318                   break;
12319                 }
12320               if (intel_syntax
12321                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12322                 break;
12323               if ((rex & REX_W))
12324                 {
12325                   USED_REX (REX_W);
12326                   *obufp++ = 'q';
12327                 }
12328               else
12329                 *obufp++ = 'l';
12330             }
12331           break;
12332         case 'R':
12333           USED_REX (REX_W);
12334           if (rex & REX_W)
12335             *obufp++ = 'q';
12336           else if (sizeflag & DFLAG)
12337             {
12338               if (intel_syntax)
12339                   *obufp++ = 'd';
12340               else
12341                   *obufp++ = 'l';
12342             }
12343           else
12344             *obufp++ = 'w';
12345           if (intel_syntax && !p[1]
12346               && ((rex & REX_W) || (sizeflag & DFLAG)))
12347             *obufp++ = 'e';
12348           if (!(rex & REX_W))
12349             used_prefixes |= (prefixes & PREFIX_DATA);
12350           break;
12351         case 'V':
12352           if (l == 0 && len == 1)
12353             {
12354               if (intel_syntax)
12355                 break;
12356               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12357                 {
12358                   if (sizeflag & SUFFIX_ALWAYS)
12359                     *obufp++ = 'q';
12360                   break;
12361                 }
12362             }
12363           else
12364             {
12365               if (l != 1
12366                   || len != 2
12367                   || last[0] != 'L')
12368                 {
12369                   SAVE_LAST (*p);
12370                   break;
12371                 }
12372
12373               if (rex & REX_W)
12374                 {
12375                   *obufp++ = 'a';
12376                   *obufp++ = 'b';
12377                   *obufp++ = 's';
12378                 }
12379             }
12380           /* Fall through.  */
12381           goto case_S;
12382         case 'S':
12383           if (l == 0 && len == 1)
12384             {
12385 case_S:
12386               if (intel_syntax)
12387                 break;
12388               if (sizeflag & SUFFIX_ALWAYS)
12389                 {
12390                   if (rex & REX_W)
12391                     *obufp++ = 'q';
12392                   else
12393                     {
12394                       if (sizeflag & DFLAG)
12395                         *obufp++ = 'l';
12396                       else
12397                         *obufp++ = 'w';
12398                       used_prefixes |= (prefixes & PREFIX_DATA);
12399                     }
12400                 }
12401             }
12402           else
12403             {
12404               if (l != 1
12405                   || len != 2
12406                   || last[0] != 'L')
12407                 {
12408                   SAVE_LAST (*p);
12409                   break;
12410                 }
12411
12412               if (address_mode == mode_64bit
12413                   && !(prefixes & PREFIX_ADDR))
12414                 {
12415                   *obufp++ = 'a';
12416                   *obufp++ = 'b';
12417                   *obufp++ = 's';
12418                 }
12419
12420               goto case_S;
12421             }
12422           break;
12423         case 'X':
12424           if (l != 0 || len != 1)
12425             {
12426               SAVE_LAST (*p);
12427               break;
12428             }
12429           if (need_vex && vex.prefix)
12430             {
12431               if (vex.prefix == DATA_PREFIX_OPCODE)
12432                 *obufp++ = 'd';
12433               else
12434                 *obufp++ = 's';
12435             }
12436           else
12437             {
12438               if (prefixes & PREFIX_DATA)
12439                 *obufp++ = 'd';
12440               else
12441                 *obufp++ = 's';
12442               used_prefixes |= (prefixes & PREFIX_DATA);
12443             }
12444           break;
12445         case 'Y':
12446           if (l == 0 && len == 1)
12447             {
12448               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12449                 break;
12450               if (rex & REX_W)
12451                 {
12452                   USED_REX (REX_W);
12453                   *obufp++ = 'q';
12454                 }
12455               break;
12456             }
12457           else
12458             {
12459               if (l != 1 || len != 2 || last[0] != 'X')
12460                 {
12461                   SAVE_LAST (*p);
12462                   break;
12463                 }
12464               if (!need_vex)
12465                 abort ();
12466               if (intel_syntax
12467                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12468                 break;
12469               switch (vex.length)
12470                 {
12471                 case 128:
12472                   *obufp++ = 'x';
12473                   break;
12474                 case 256:
12475                   *obufp++ = 'y';
12476                   break;
12477                 default:
12478                   abort ();
12479                 }
12480             }
12481           break;
12482         case 'W':
12483           if (l == 0 && len == 1)
12484             {
12485               /* operand size flag for cwtl, cbtw */
12486               USED_REX (REX_W);
12487               if (rex & REX_W)
12488                 {
12489                   if (intel_syntax)
12490                     *obufp++ = 'd';
12491                   else
12492                     *obufp++ = 'l';
12493                 }
12494               else if (sizeflag & DFLAG)
12495                 *obufp++ = 'w';
12496               else
12497                 *obufp++ = 'b';
12498               if (!(rex & REX_W))
12499                 used_prefixes |= (prefixes & PREFIX_DATA);
12500             }
12501           else
12502             {
12503               if (l != 1 || len != 2 || last[0] != 'X')
12504                 {
12505                   SAVE_LAST (*p);
12506                   break;
12507                 }
12508               if (!need_vex)
12509                 abort ();
12510               *obufp++ = vex.w ? 'd': 's';
12511             }
12512           break;
12513         }
12514       alt = 0;
12515     }
12516   *obufp = 0;
12517   mnemonicendp = obufp;
12518   return 0;
12519 }
12520
12521 static void
12522 oappend (const char *s)
12523 {
12524   obufp = stpcpy (obufp, s);
12525 }
12526
12527 static void
12528 append_seg (void)
12529 {
12530   if (prefixes & PREFIX_CS)
12531     {
12532       used_prefixes |= PREFIX_CS;
12533       oappend ("%cs:" + intel_syntax);
12534     }
12535   if (prefixes & PREFIX_DS)
12536     {
12537       used_prefixes |= PREFIX_DS;
12538       oappend ("%ds:" + intel_syntax);
12539     }
12540   if (prefixes & PREFIX_SS)
12541     {
12542       used_prefixes |= PREFIX_SS;
12543       oappend ("%ss:" + intel_syntax);
12544     }
12545   if (prefixes & PREFIX_ES)
12546     {
12547       used_prefixes |= PREFIX_ES;
12548       oappend ("%es:" + intel_syntax);
12549     }
12550   if (prefixes & PREFIX_FS)
12551     {
12552       used_prefixes |= PREFIX_FS;
12553       oappend ("%fs:" + intel_syntax);
12554     }
12555   if (prefixes & PREFIX_GS)
12556     {
12557       used_prefixes |= PREFIX_GS;
12558       oappend ("%gs:" + intel_syntax);
12559     }
12560 }
12561
12562 static void
12563 OP_indirE (int bytemode, int sizeflag)
12564 {
12565   if (!intel_syntax)
12566     oappend ("*");
12567   OP_E (bytemode, sizeflag);
12568 }
12569
12570 static void
12571 print_operand_value (char *buf, int hex, bfd_vma disp)
12572 {
12573   if (address_mode == mode_64bit)
12574     {
12575       if (hex)
12576         {
12577           char tmp[30];
12578           int i;
12579           buf[0] = '0';
12580           buf[1] = 'x';
12581           sprintf_vma (tmp, disp);
12582           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12583           strcpy (buf + 2, tmp + i);
12584         }
12585       else
12586         {
12587           bfd_signed_vma v = disp;
12588           char tmp[30];
12589           int i;
12590           if (v < 0)
12591             {
12592               *(buf++) = '-';
12593               v = -disp;
12594               /* Check for possible overflow on 0x8000000000000000.  */
12595               if (v < 0)
12596                 {
12597                   strcpy (buf, "9223372036854775808");
12598                   return;
12599                 }
12600             }
12601           if (!v)
12602             {
12603               strcpy (buf, "0");
12604               return;
12605             }
12606
12607           i = 0;
12608           tmp[29] = 0;
12609           while (v)
12610             {
12611               tmp[28 - i] = (v % 10) + '0';
12612               v /= 10;
12613               i++;
12614             }
12615           strcpy (buf, tmp + 29 - i);
12616         }
12617     }
12618   else
12619     {
12620       if (hex)
12621         sprintf (buf, "0x%x", (unsigned int) disp);
12622       else
12623         sprintf (buf, "%d", (int) disp);
12624     }
12625 }
12626
12627 /* Put DISP in BUF as signed hex number.  */
12628
12629 static void
12630 print_displacement (char *buf, bfd_vma disp)
12631 {
12632   bfd_signed_vma val = disp;
12633   char tmp[30];
12634   int i, j = 0;
12635
12636   if (val < 0)
12637     {
12638       buf[j++] = '-';
12639       val = -disp;
12640
12641       /* Check for possible overflow.  */
12642       if (val < 0)
12643         {
12644           switch (address_mode)
12645             {
12646             case mode_64bit:
12647               strcpy (buf + j, "0x8000000000000000");
12648               break;
12649             case mode_32bit:
12650               strcpy (buf + j, "0x80000000");
12651               break;
12652             case mode_16bit:
12653               strcpy (buf + j, "0x8000");
12654               break;
12655             }
12656           return;
12657         }
12658     }
12659
12660   buf[j++] = '0';
12661   buf[j++] = 'x';
12662
12663   sprintf_vma (tmp, (bfd_vma) val);
12664   for (i = 0; tmp[i] == '0'; i++)
12665     continue;
12666   if (tmp[i] == '\0')
12667     i--;
12668   strcpy (buf + j, tmp + i);
12669 }
12670
12671 static void
12672 intel_operand_size (int bytemode, int sizeflag)
12673 {
12674   switch (bytemode)
12675     {
12676     case b_mode:
12677     case b_swap_mode:
12678     case dqb_mode:
12679       oappend ("BYTE PTR ");
12680       break;
12681     case w_mode:
12682     case dqw_mode:
12683       oappend ("WORD PTR ");
12684       break;
12685     case stack_v_mode:
12686       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12687         {
12688           oappend ("QWORD PTR ");
12689           break;
12690         }
12691       /* FALLTHRU */
12692     case v_mode:
12693     case v_swap_mode:
12694     case dq_mode:
12695       USED_REX (REX_W);
12696       if (rex & REX_W)
12697         oappend ("QWORD PTR ");
12698       else
12699         {
12700           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12701             oappend ("DWORD PTR ");
12702           else
12703             oappend ("WORD PTR ");
12704           used_prefixes |= (prefixes & PREFIX_DATA);
12705         }
12706       break;
12707     case z_mode:
12708       if ((rex & REX_W) || (sizeflag & DFLAG))
12709         *obufp++ = 'D';
12710       oappend ("WORD PTR ");
12711       if (!(rex & REX_W))
12712         used_prefixes |= (prefixes & PREFIX_DATA);
12713       break;
12714     case a_mode:
12715       if (sizeflag & DFLAG)
12716         oappend ("QWORD PTR ");
12717       else
12718         oappend ("DWORD PTR ");
12719       used_prefixes |= (prefixes & PREFIX_DATA);
12720       break;
12721     case d_mode:
12722     case d_scalar_mode:
12723     case d_scalar_swap_mode:
12724     case d_swap_mode:
12725     case dqd_mode:
12726       oappend ("DWORD PTR ");
12727       break;
12728     case q_mode:
12729     case q_scalar_mode:
12730     case q_scalar_swap_mode:
12731     case q_swap_mode:
12732       oappend ("QWORD PTR ");
12733       break;
12734     case m_mode:
12735       if (address_mode == mode_64bit)
12736         oappend ("QWORD PTR ");
12737       else
12738         oappend ("DWORD PTR ");
12739       break;
12740     case f_mode:
12741       if (sizeflag & DFLAG)
12742         oappend ("FWORD PTR ");
12743       else
12744         oappend ("DWORD PTR ");
12745       used_prefixes |= (prefixes & PREFIX_DATA);
12746       break;
12747     case t_mode:
12748       oappend ("TBYTE PTR ");
12749       break;
12750     case x_mode:
12751     case x_swap_mode:
12752       if (need_vex)
12753         {
12754           switch (vex.length)
12755             {
12756             case 128:
12757               oappend ("XMMWORD PTR ");
12758               break;
12759             case 256:
12760               oappend ("YMMWORD PTR ");
12761               break;
12762             default:
12763               abort ();
12764             }
12765         }
12766       else
12767         oappend ("XMMWORD PTR ");
12768       break;
12769     case xmm_mode:
12770       oappend ("XMMWORD PTR ");
12771       break;
12772     case xmmq_mode:
12773       if (!need_vex)
12774         abort ();
12775
12776       switch (vex.length)
12777         {
12778         case 128:
12779           oappend ("QWORD PTR ");
12780           break;
12781         case 256:
12782           oappend ("XMMWORD PTR ");
12783           break;
12784         default:
12785           abort ();
12786         }
12787       break;
12788     case ymmq_mode:
12789       if (!need_vex)
12790         abort ();
12791
12792       switch (vex.length)
12793         {
12794         case 128:
12795           oappend ("QWORD PTR ");
12796           break;
12797         case 256:
12798           oappend ("YMMWORD PTR ");
12799           break;
12800         default:
12801           abort ();
12802         }
12803       break;
12804     case o_mode:
12805       oappend ("OWORD PTR ");
12806       break;
12807     case vex_w_dq_mode:
12808     case vex_scalar_w_dq_mode:
12809       if (!need_vex)
12810         abort ();
12811
12812       if (vex.w)
12813         oappend ("QWORD PTR ");
12814       else
12815         oappend ("DWORD PTR ");
12816       break;
12817     default:
12818       break;
12819     }
12820 }
12821
12822 static void
12823 OP_E_register (int bytemode, int sizeflag)
12824 {
12825   int reg = modrm.rm;
12826   const char **names;
12827
12828   USED_REX (REX_B);
12829   if ((rex & REX_B))
12830     reg += 8;
12831
12832   if ((sizeflag & SUFFIX_ALWAYS)
12833       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12834     swap_operand ();
12835
12836   switch (bytemode)
12837     {
12838     case b_mode:
12839     case b_swap_mode:
12840       USED_REX (0);
12841       if (rex)
12842         names = names8rex;
12843       else
12844         names = names8;
12845       break;
12846     case w_mode:
12847       names = names16;
12848       break;
12849     case d_mode:
12850       names = names32;
12851       break;
12852     case q_mode:
12853       names = names64;
12854       break;
12855     case m_mode:
12856       names = address_mode == mode_64bit ? names64 : names32;
12857       break;
12858     case stack_v_mode:
12859       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12860         {
12861           names = names64;
12862           break;
12863         }
12864       bytemode = v_mode;
12865       /* FALLTHRU */
12866     case v_mode:
12867     case v_swap_mode:
12868     case dq_mode:
12869     case dqb_mode:
12870     case dqd_mode:
12871     case dqw_mode:
12872       USED_REX (REX_W);
12873       if (rex & REX_W)
12874         names = names64;
12875       else
12876         {
12877           if ((sizeflag & DFLAG)
12878               || (bytemode != v_mode
12879                   && bytemode != v_swap_mode))
12880             names = names32;
12881           else
12882             names = names16;
12883           used_prefixes |= (prefixes & PREFIX_DATA);
12884         }
12885       break;
12886     case 0:
12887       return;
12888     default:
12889       oappend (INTERNAL_DISASSEMBLER_ERROR);
12890       return;
12891     }
12892   oappend (names[reg]);
12893 }
12894
12895 static void
12896 OP_E_memory (int bytemode, int sizeflag)
12897 {
12898   bfd_vma disp = 0;
12899   int add = (rex & REX_B) ? 8 : 0;
12900   int riprel = 0;
12901
12902   USED_REX (REX_B);
12903   if (intel_syntax)
12904     intel_operand_size (bytemode, sizeflag);
12905   append_seg ();
12906
12907   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12908     {
12909       /* 32/64 bit address mode */
12910       int havedisp;
12911       int havesib;
12912       int havebase;
12913       int haveindex;
12914       int needindex;
12915       int base, rbase;
12916       int vindex = 0;
12917       int scale = 0;
12918
12919       havesib = 0;
12920       havebase = 1;
12921       haveindex = 0;
12922       base = modrm.rm;
12923
12924       if (base == 4)
12925         {
12926           havesib = 1;
12927           FETCH_DATA (the_info, codep + 1);
12928           vindex = (*codep >> 3) & 7;
12929           scale = (*codep >> 6) & 3;
12930           base = *codep & 7;
12931           USED_REX (REX_X);
12932           if (rex & REX_X)
12933             vindex += 8;
12934           haveindex = vindex != 4;
12935           codep++;
12936         }
12937       rbase = base + add;
12938
12939       switch (modrm.mod)
12940         {
12941         case 0:
12942           if (base == 5)
12943             {
12944               havebase = 0;
12945               if (address_mode == mode_64bit && !havesib)
12946                 riprel = 1;
12947               disp = get32s ();
12948             }
12949           break;
12950         case 1:
12951           FETCH_DATA (the_info, codep + 1);
12952           disp = *codep++;
12953           if ((disp & 0x80) != 0)
12954             disp -= 0x100;
12955           break;
12956         case 2:
12957           disp = get32s ();
12958           break;
12959         }
12960
12961       /* In 32bit mode, we need index register to tell [offset] from
12962          [eiz*1 + offset].  */
12963       needindex = (havesib
12964                    && !havebase
12965                    && !haveindex
12966                    && address_mode == mode_32bit);
12967       havedisp = (havebase
12968                   || needindex
12969                   || (havesib && (haveindex || scale != 0)));
12970
12971       if (!intel_syntax)
12972         if (modrm.mod != 0 || base == 5)
12973           {
12974             if (havedisp || riprel)
12975               print_displacement (scratchbuf, disp);
12976             else
12977               print_operand_value (scratchbuf, 1, disp);
12978             oappend (scratchbuf);
12979             if (riprel)
12980               {
12981                 set_op (disp, 1);
12982                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12983               }
12984           }
12985
12986       if (havebase || haveindex || riprel)
12987         used_prefixes |= PREFIX_ADDR;
12988
12989       if (havedisp || (intel_syntax && riprel))
12990         {
12991           *obufp++ = open_char;
12992           if (intel_syntax && riprel)
12993             {
12994               set_op (disp, 1);
12995               oappend (sizeflag & AFLAG ? "rip" : "eip");
12996             }
12997           *obufp = '\0';
12998           if (havebase)
12999             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13000                      ? names64[rbase] : names32[rbase]);
13001           if (havesib)
13002             {
13003               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
13004                  print index to tell base + index from base.  */
13005               if (scale != 0
13006                   || needindex
13007                   || haveindex
13008                   || (havebase && base != ESP_REG_NUM))
13009                 {
13010                   if (!intel_syntax || havebase)
13011                     {
13012                       *obufp++ = separator_char;
13013                       *obufp = '\0';
13014                     }
13015                   if (haveindex)
13016                     oappend (address_mode == mode_64bit
13017                              && (sizeflag & AFLAG)
13018                              ? names64[vindex] : names32[vindex]);
13019                   else
13020                     oappend (address_mode == mode_64bit
13021                              && (sizeflag & AFLAG)
13022                              ? index64 : index32);
13023
13024                   *obufp++ = scale_char;
13025                   *obufp = '\0';
13026                   sprintf (scratchbuf, "%d", 1 << scale);
13027                   oappend (scratchbuf);
13028                 }
13029             }
13030           if (intel_syntax
13031               && (disp || modrm.mod != 0 || base == 5))
13032             {
13033               if (!havedisp || (bfd_signed_vma) disp >= 0)
13034                 {
13035                   *obufp++ = '+';
13036                   *obufp = '\0';
13037                 }
13038               else if (modrm.mod != 1 && disp != -disp)
13039                 {
13040                   *obufp++ = '-';
13041                   *obufp = '\0';
13042                   disp = - (bfd_signed_vma) disp;
13043                 }
13044
13045               if (havedisp)
13046                 print_displacement (scratchbuf, disp);
13047               else
13048                 print_operand_value (scratchbuf, 1, disp);
13049               oappend (scratchbuf);
13050             }
13051
13052           *obufp++ = close_char;
13053           *obufp = '\0';
13054         }
13055       else if (intel_syntax)
13056         {
13057           if (modrm.mod != 0 || base == 5)
13058             {
13059               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13060                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13061                 ;
13062               else
13063                 {
13064                   oappend (names_seg[ds_reg - es_reg]);
13065                   oappend (":");
13066                 }
13067               print_operand_value (scratchbuf, 1, disp);
13068               oappend (scratchbuf);
13069             }
13070         }
13071     }
13072   else
13073     {
13074       /* 16 bit address mode */
13075       used_prefixes |= prefixes & PREFIX_ADDR;
13076       switch (modrm.mod)
13077         {
13078         case 0:
13079           if (modrm.rm == 6)
13080             {
13081               disp = get16 ();
13082               if ((disp & 0x8000) != 0)
13083                 disp -= 0x10000;
13084             }
13085           break;
13086         case 1:
13087           FETCH_DATA (the_info, codep + 1);
13088           disp = *codep++;
13089           if ((disp & 0x80) != 0)
13090             disp -= 0x100;
13091           break;
13092         case 2:
13093           disp = get16 ();
13094           if ((disp & 0x8000) != 0)
13095             disp -= 0x10000;
13096           break;
13097         }
13098
13099       if (!intel_syntax)
13100         if (modrm.mod != 0 || modrm.rm == 6)
13101           {
13102             print_displacement (scratchbuf, disp);
13103             oappend (scratchbuf);
13104           }
13105
13106       if (modrm.mod != 0 || modrm.rm != 6)
13107         {
13108           *obufp++ = open_char;
13109           *obufp = '\0';
13110           oappend (index16[modrm.rm]);
13111           if (intel_syntax
13112               && (disp || modrm.mod != 0 || modrm.rm == 6))
13113             {
13114               if ((bfd_signed_vma) disp >= 0)
13115                 {
13116                   *obufp++ = '+';
13117                   *obufp = '\0';
13118                 }
13119               else if (modrm.mod != 1)
13120                 {
13121                   *obufp++ = '-';
13122                   *obufp = '\0';
13123                   disp = - (bfd_signed_vma) disp;
13124                 }
13125
13126               print_displacement (scratchbuf, disp);
13127               oappend (scratchbuf);
13128             }
13129
13130           *obufp++ = close_char;
13131           *obufp = '\0';
13132         }
13133       else if (intel_syntax)
13134         {
13135           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13136                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13137             ;
13138           else
13139             {
13140               oappend (names_seg[ds_reg - es_reg]);
13141               oappend (":");
13142             }
13143           print_operand_value (scratchbuf, 1, disp & 0xffff);
13144           oappend (scratchbuf);
13145         }
13146     }
13147 }
13148
13149 static void
13150 OP_E (int bytemode, int sizeflag)
13151 {
13152   /* Skip mod/rm byte.  */
13153   MODRM_CHECK;
13154   codep++;
13155
13156   if (modrm.mod == 3)
13157     OP_E_register (bytemode, sizeflag);
13158   else
13159     OP_E_memory (bytemode, sizeflag);
13160 }
13161
13162 static void
13163 OP_G (int bytemode, int sizeflag)
13164 {
13165   int add = 0;
13166   USED_REX (REX_R);
13167   if (rex & REX_R)
13168     add += 8;
13169   switch (bytemode)
13170     {
13171     case b_mode:
13172       USED_REX (0);
13173       if (rex)
13174         oappend (names8rex[modrm.reg + add]);
13175       else
13176         oappend (names8[modrm.reg + add]);
13177       break;
13178     case w_mode:
13179       oappend (names16[modrm.reg + add]);
13180       break;
13181     case d_mode:
13182       oappend (names32[modrm.reg + add]);
13183       break;
13184     case q_mode:
13185       oappend (names64[modrm.reg + add]);
13186       break;
13187     case v_mode:
13188     case dq_mode:
13189     case dqb_mode:
13190     case dqd_mode:
13191     case dqw_mode:
13192       USED_REX (REX_W);
13193       if (rex & REX_W)
13194         oappend (names64[modrm.reg + add]);
13195       else
13196         {
13197           if ((sizeflag & DFLAG) || bytemode != v_mode)
13198             oappend (names32[modrm.reg + add]);
13199           else
13200             oappend (names16[modrm.reg + add]);
13201           used_prefixes |= (prefixes & PREFIX_DATA);
13202         }
13203       break;
13204     case m_mode:
13205       if (address_mode == mode_64bit)
13206         oappend (names64[modrm.reg + add]);
13207       else
13208         oappend (names32[modrm.reg + add]);
13209       break;
13210     default:
13211       oappend (INTERNAL_DISASSEMBLER_ERROR);
13212       break;
13213     }
13214 }
13215
13216 static bfd_vma
13217 get64 (void)
13218 {
13219   bfd_vma x;
13220 #ifdef BFD64
13221   unsigned int a;
13222   unsigned int b;
13223
13224   FETCH_DATA (the_info, codep + 8);
13225   a = *codep++ & 0xff;
13226   a |= (*codep++ & 0xff) << 8;
13227   a |= (*codep++ & 0xff) << 16;
13228   a |= (*codep++ & 0xff) << 24;
13229   b = *codep++ & 0xff;
13230   b |= (*codep++ & 0xff) << 8;
13231   b |= (*codep++ & 0xff) << 16;
13232   b |= (*codep++ & 0xff) << 24;
13233   x = a + ((bfd_vma) b << 32);
13234 #else
13235   abort ();
13236   x = 0;
13237 #endif
13238   return x;
13239 }
13240
13241 static bfd_signed_vma
13242 get32 (void)
13243 {
13244   bfd_signed_vma x = 0;
13245
13246   FETCH_DATA (the_info, codep + 4);
13247   x = *codep++ & (bfd_signed_vma) 0xff;
13248   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13249   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13250   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13251   return x;
13252 }
13253
13254 static bfd_signed_vma
13255 get32s (void)
13256 {
13257   bfd_signed_vma x = 0;
13258
13259   FETCH_DATA (the_info, codep + 4);
13260   x = *codep++ & (bfd_signed_vma) 0xff;
13261   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13262   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13263   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13264
13265   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13266
13267   return x;
13268 }
13269
13270 static int
13271 get16 (void)
13272 {
13273   int x = 0;
13274
13275   FETCH_DATA (the_info, codep + 2);
13276   x = *codep++ & 0xff;
13277   x |= (*codep++ & 0xff) << 8;
13278   return x;
13279 }
13280
13281 static void
13282 set_op (bfd_vma op, int riprel)
13283 {
13284   op_index[op_ad] = op_ad;
13285   if (address_mode == mode_64bit)
13286     {
13287       op_address[op_ad] = op;
13288       op_riprel[op_ad] = riprel;
13289     }
13290   else
13291     {
13292       /* Mask to get a 32-bit address.  */
13293       op_address[op_ad] = op & 0xffffffff;
13294       op_riprel[op_ad] = riprel & 0xffffffff;
13295     }
13296 }
13297
13298 static void
13299 OP_REG (int code, int sizeflag)
13300 {
13301   const char *s;
13302   int add;
13303   USED_REX (REX_B);
13304   if (rex & REX_B)
13305     add = 8;
13306   else
13307     add = 0;
13308
13309   switch (code)
13310     {
13311     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13312     case sp_reg: case bp_reg: case si_reg: case di_reg:
13313       s = names16[code - ax_reg + add];
13314       break;
13315     case es_reg: case ss_reg: case cs_reg:
13316     case ds_reg: case fs_reg: case gs_reg:
13317       s = names_seg[code - es_reg + add];
13318       break;
13319     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13320     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13321       USED_REX (0);
13322       if (rex)
13323         s = names8rex[code - al_reg + add];
13324       else
13325         s = names8[code - al_reg];
13326       break;
13327     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13328     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13329       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13330         {
13331           s = names64[code - rAX_reg + add];
13332           break;
13333         }
13334       code += eAX_reg - rAX_reg;
13335       /* Fall through.  */
13336     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13337     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13338       USED_REX (REX_W);
13339       if (rex & REX_W)
13340         s = names64[code - eAX_reg + add];
13341       else
13342         {
13343           if (sizeflag & DFLAG)
13344             s = names32[code - eAX_reg + add];
13345           else
13346             s = names16[code - eAX_reg + add];
13347           used_prefixes |= (prefixes & PREFIX_DATA);
13348         }
13349       break;
13350     default:
13351       s = INTERNAL_DISASSEMBLER_ERROR;
13352       break;
13353     }
13354   oappend (s);
13355 }
13356
13357 static void
13358 OP_IMREG (int code, int sizeflag)
13359 {
13360   const char *s;
13361
13362   switch (code)
13363     {
13364     case indir_dx_reg:
13365       if (intel_syntax)
13366         s = "dx";
13367       else
13368         s = "(%dx)";
13369       break;
13370     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13371     case sp_reg: case bp_reg: case si_reg: case di_reg:
13372       s = names16[code - ax_reg];
13373       break;
13374     case es_reg: case ss_reg: case cs_reg:
13375     case ds_reg: case fs_reg: case gs_reg:
13376       s = names_seg[code - es_reg];
13377       break;
13378     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13379     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13380       USED_REX (0);
13381       if (rex)
13382         s = names8rex[code - al_reg];
13383       else
13384         s = names8[code - al_reg];
13385       break;
13386     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13387     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13388       USED_REX (REX_W);
13389       if (rex & REX_W)
13390         s = names64[code - eAX_reg];
13391       else
13392         {
13393           if (sizeflag & DFLAG)
13394             s = names32[code - eAX_reg];
13395           else
13396             s = names16[code - eAX_reg];
13397           used_prefixes |= (prefixes & PREFIX_DATA);
13398         }
13399       break;
13400     case z_mode_ax_reg:
13401       if ((rex & REX_W) || (sizeflag & DFLAG))
13402         s = *names32;
13403       else
13404         s = *names16;
13405       if (!(rex & REX_W))
13406         used_prefixes |= (prefixes & PREFIX_DATA);
13407       break;
13408     default:
13409       s = INTERNAL_DISASSEMBLER_ERROR;
13410       break;
13411     }
13412   oappend (s);
13413 }
13414
13415 static void
13416 OP_I (int bytemode, int sizeflag)
13417 {
13418   bfd_signed_vma op;
13419   bfd_signed_vma mask = -1;
13420
13421   switch (bytemode)
13422     {
13423     case b_mode:
13424       FETCH_DATA (the_info, codep + 1);
13425       op = *codep++;
13426       mask = 0xff;
13427       break;
13428     case q_mode:
13429       if (address_mode == mode_64bit)
13430         {
13431           op = get32s ();
13432           break;
13433         }
13434       /* Fall through.  */
13435     case v_mode:
13436       USED_REX (REX_W);
13437       if (rex & REX_W)
13438         op = get32s ();
13439       else
13440         {
13441           if (sizeflag & DFLAG)
13442             {
13443               op = get32 ();
13444               mask = 0xffffffff;
13445             }
13446           else
13447             {
13448               op = get16 ();
13449               mask = 0xfffff;
13450             }
13451           used_prefixes |= (prefixes & PREFIX_DATA);
13452         }
13453       break;
13454     case w_mode:
13455       mask = 0xfffff;
13456       op = get16 ();
13457       break;
13458     case const_1_mode:
13459       if (intel_syntax)
13460         oappend ("1");
13461       return;
13462     default:
13463       oappend (INTERNAL_DISASSEMBLER_ERROR);
13464       return;
13465     }
13466
13467   op &= mask;
13468   scratchbuf[0] = '$';
13469   print_operand_value (scratchbuf + 1, 1, op);
13470   oappend (scratchbuf + intel_syntax);
13471   scratchbuf[0] = '\0';
13472 }
13473
13474 static void
13475 OP_I64 (int bytemode, int sizeflag)
13476 {
13477   bfd_signed_vma op;
13478   bfd_signed_vma mask = -1;
13479
13480   if (address_mode != mode_64bit)
13481     {
13482       OP_I (bytemode, sizeflag);
13483       return;
13484     }
13485
13486   switch (bytemode)
13487     {
13488     case b_mode:
13489       FETCH_DATA (the_info, codep + 1);
13490       op = *codep++;
13491       mask = 0xff;
13492       break;
13493     case v_mode:
13494       USED_REX (REX_W);
13495       if (rex & REX_W)
13496         op = get64 ();
13497       else
13498         {
13499           if (sizeflag & DFLAG)
13500             {
13501               op = get32 ();
13502               mask = 0xffffffff;
13503             }
13504           else
13505             {
13506               op = get16 ();
13507               mask = 0xfffff;
13508             }
13509           used_prefixes |= (prefixes & PREFIX_DATA);
13510         }
13511       break;
13512     case w_mode:
13513       mask = 0xfffff;
13514       op = get16 ();
13515       break;
13516     default:
13517       oappend (INTERNAL_DISASSEMBLER_ERROR);
13518       return;
13519     }
13520
13521   op &= mask;
13522   scratchbuf[0] = '$';
13523   print_operand_value (scratchbuf + 1, 1, op);
13524   oappend (scratchbuf + intel_syntax);
13525   scratchbuf[0] = '\0';
13526 }
13527
13528 static void
13529 OP_sI (int bytemode, int sizeflag)
13530 {
13531   bfd_signed_vma op;
13532
13533   switch (bytemode)
13534     {
13535     case b_mode:
13536       FETCH_DATA (the_info, codep + 1);
13537       op = *codep++;
13538       if ((op & 0x80) != 0)
13539         op -= 0x100;
13540       break;
13541     case v_mode:
13542       USED_REX (REX_W);
13543       if (rex & REX_W)
13544         op = get32s ();
13545       else
13546         {
13547           if (sizeflag & DFLAG)
13548             {
13549               op = get32s ();
13550             }
13551           else
13552             {
13553               op = get16 ();
13554               if ((op & 0x8000) != 0)
13555                 op -= 0x10000;
13556             }
13557           used_prefixes |= (prefixes & PREFIX_DATA);
13558         }
13559       break;
13560     case w_mode:
13561       op = get16 ();
13562       if ((op & 0x8000) != 0)
13563         op -= 0x10000;
13564       break;
13565     default:
13566       oappend (INTERNAL_DISASSEMBLER_ERROR);
13567       return;
13568     }
13569
13570   scratchbuf[0] = '$';
13571   print_operand_value (scratchbuf + 1, 1, op);
13572   oappend (scratchbuf + intel_syntax);
13573 }
13574
13575 static void
13576 OP_J (int bytemode, int sizeflag)
13577 {
13578   bfd_vma disp;
13579   bfd_vma mask = -1;
13580   bfd_vma segment = 0;
13581
13582   switch (bytemode)
13583     {
13584     case b_mode:
13585       FETCH_DATA (the_info, codep + 1);
13586       disp = *codep++;
13587       if ((disp & 0x80) != 0)
13588         disp -= 0x100;
13589       break;
13590     case v_mode:
13591       USED_REX (REX_W);
13592       if ((sizeflag & DFLAG) || (rex & REX_W))
13593         disp = get32s ();
13594       else
13595         {
13596           disp = get16 ();
13597           if ((disp & 0x8000) != 0)
13598             disp -= 0x10000;
13599           /* In 16bit mode, address is wrapped around at 64k within
13600              the same segment.  Otherwise, a data16 prefix on a jump
13601              instruction means that the pc is masked to 16 bits after
13602              the displacement is added!  */
13603           mask = 0xffff;
13604           if ((prefixes & PREFIX_DATA) == 0)
13605             segment = ((start_pc + codep - start_codep)
13606                        & ~((bfd_vma) 0xffff));
13607         }
13608       if (!(rex & REX_W))
13609         used_prefixes |= (prefixes & PREFIX_DATA);
13610       break;
13611     default:
13612       oappend (INTERNAL_DISASSEMBLER_ERROR);
13613       return;
13614     }
13615   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13616   set_op (disp, 0);
13617   print_operand_value (scratchbuf, 1, disp);
13618   oappend (scratchbuf);
13619 }
13620
13621 static void
13622 OP_SEG (int bytemode, int sizeflag)
13623 {
13624   if (bytemode == w_mode)
13625     oappend (names_seg[modrm.reg]);
13626   else
13627     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13628 }
13629
13630 static void
13631 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13632 {
13633   int seg, offset;
13634
13635   if (sizeflag & DFLAG)
13636     {
13637       offset = get32 ();
13638       seg = get16 ();
13639     }
13640   else
13641     {
13642       offset = get16 ();
13643       seg = get16 ();
13644     }
13645   used_prefixes |= (prefixes & PREFIX_DATA);
13646   if (intel_syntax)
13647     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13648   else
13649     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13650   oappend (scratchbuf);
13651 }
13652
13653 static void
13654 OP_OFF (int bytemode, int sizeflag)
13655 {
13656   bfd_vma off;
13657
13658   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13659     intel_operand_size (bytemode, sizeflag);
13660   append_seg ();
13661
13662   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13663     off = get32 ();
13664   else
13665     off = get16 ();
13666
13667   if (intel_syntax)
13668     {
13669       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13670                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13671         {
13672           oappend (names_seg[ds_reg - es_reg]);
13673           oappend (":");
13674         }
13675     }
13676   print_operand_value (scratchbuf, 1, off);
13677   oappend (scratchbuf);
13678 }
13679
13680 static void
13681 OP_OFF64 (int bytemode, int sizeflag)
13682 {
13683   bfd_vma off;
13684
13685   if (address_mode != mode_64bit
13686       || (prefixes & PREFIX_ADDR))
13687     {
13688       OP_OFF (bytemode, sizeflag);
13689       return;
13690     }
13691
13692   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13693     intel_operand_size (bytemode, sizeflag);
13694   append_seg ();
13695
13696   off = get64 ();
13697
13698   if (intel_syntax)
13699     {
13700       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13701                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13702         {
13703           oappend (names_seg[ds_reg - es_reg]);
13704           oappend (":");
13705         }
13706     }
13707   print_operand_value (scratchbuf, 1, off);
13708   oappend (scratchbuf);
13709 }
13710
13711 static void
13712 ptr_reg (int code, int sizeflag)
13713 {
13714   const char *s;
13715
13716   *obufp++ = open_char;
13717   used_prefixes |= (prefixes & PREFIX_ADDR);
13718   if (address_mode == mode_64bit)
13719     {
13720       if (!(sizeflag & AFLAG))
13721         s = names32[code - eAX_reg];
13722       else
13723         s = names64[code - eAX_reg];
13724     }
13725   else if (sizeflag & AFLAG)
13726     s = names32[code - eAX_reg];
13727   else
13728     s = names16[code - eAX_reg];
13729   oappend (s);
13730   *obufp++ = close_char;
13731   *obufp = 0;
13732 }
13733
13734 static void
13735 OP_ESreg (int code, int sizeflag)
13736 {
13737   if (intel_syntax)
13738     {
13739       switch (codep[-1])
13740         {
13741         case 0x6d:      /* insw/insl */
13742           intel_operand_size (z_mode, sizeflag);
13743           break;
13744         case 0xa5:      /* movsw/movsl/movsq */
13745         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13746         case 0xab:      /* stosw/stosl */
13747         case 0xaf:      /* scasw/scasl */
13748           intel_operand_size (v_mode, sizeflag);
13749           break;
13750         default:
13751           intel_operand_size (b_mode, sizeflag);
13752         }
13753     }
13754   oappend ("%es:" + intel_syntax);
13755   ptr_reg (code, sizeflag);
13756 }
13757
13758 static void
13759 OP_DSreg (int code, int sizeflag)
13760 {
13761   if (intel_syntax)
13762     {
13763       switch (codep[-1])
13764         {
13765         case 0x6f:      /* outsw/outsl */
13766           intel_operand_size (z_mode, sizeflag);
13767           break;
13768         case 0xa5:      /* movsw/movsl/movsq */
13769         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13770         case 0xad:      /* lodsw/lodsl/lodsq */
13771           intel_operand_size (v_mode, sizeflag);
13772           break;
13773         default:
13774           intel_operand_size (b_mode, sizeflag);
13775         }
13776     }
13777   if ((prefixes
13778        & (PREFIX_CS
13779           | PREFIX_DS
13780           | PREFIX_SS
13781           | PREFIX_ES
13782           | PREFIX_FS
13783           | PREFIX_GS)) == 0)
13784     prefixes |= PREFIX_DS;
13785   append_seg ();
13786   ptr_reg (code, sizeflag);
13787 }
13788
13789 static void
13790 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13791 {
13792   int add;
13793   if (rex & REX_R)
13794     {
13795       USED_REX (REX_R);
13796       add = 8;
13797     }
13798   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13799     {
13800       all_prefixes[last_lock_prefix] = 0;
13801       used_prefixes |= PREFIX_LOCK;
13802       add = 8;
13803     }
13804   else
13805     add = 0;
13806   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13807   oappend (scratchbuf + intel_syntax);
13808 }
13809
13810 static void
13811 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13812 {
13813   int add;
13814   USED_REX (REX_R);
13815   if (rex & REX_R)
13816     add = 8;
13817   else
13818     add = 0;
13819   if (intel_syntax)
13820     sprintf (scratchbuf, "db%d", modrm.reg + add);
13821   else
13822     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13823   oappend (scratchbuf);
13824 }
13825
13826 static void
13827 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13828 {
13829   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13830   oappend (scratchbuf + intel_syntax);
13831 }
13832
13833 static void
13834 OP_R (int bytemode, int sizeflag)
13835 {
13836   if (modrm.mod == 3)
13837     OP_E (bytemode, sizeflag);
13838   else
13839     BadOp ();
13840 }
13841
13842 static void
13843 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13844 {
13845   int reg = modrm.reg;
13846   const char **names;
13847
13848   used_prefixes |= (prefixes & PREFIX_DATA);
13849   if (prefixes & PREFIX_DATA)
13850     {
13851       names = names_xmm;
13852       USED_REX (REX_R);
13853       if (rex & REX_R)
13854         reg += 8;
13855     }
13856   else
13857     names = names_mm;
13858   oappend (names[reg]);
13859 }
13860
13861 static void
13862 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13863 {
13864   int reg = modrm.reg;
13865   const char **names;
13866
13867   USED_REX (REX_R);
13868   if (rex & REX_R)
13869     reg += 8;
13870   if (need_vex
13871       && bytemode != xmm_mode
13872       && bytemode != scalar_mode)
13873     {
13874       switch (vex.length)
13875         {
13876         case 128:
13877           names = names_xmm;
13878           break;
13879         case 256:
13880           names = names_ymm;
13881           break;
13882         default:
13883           abort ();
13884         }
13885     }
13886   else
13887     names = names_xmm;
13888   oappend (names[reg]);
13889 }
13890
13891 static void
13892 OP_EM (int bytemode, int sizeflag)
13893 {
13894   int reg;
13895   const char **names;
13896
13897   if (modrm.mod != 3)
13898     {
13899       if (intel_syntax
13900           && (bytemode == v_mode || bytemode == v_swap_mode))
13901         {
13902           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13903           used_prefixes |= (prefixes & PREFIX_DATA);
13904         }
13905       OP_E (bytemode, sizeflag);
13906       return;
13907     }
13908
13909   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13910     swap_operand ();
13911
13912   /* Skip mod/rm byte.  */
13913   MODRM_CHECK;
13914   codep++;
13915   used_prefixes |= (prefixes & PREFIX_DATA);
13916   reg = modrm.rm;
13917   if (prefixes & PREFIX_DATA)
13918     {
13919       names = names_xmm;
13920       USED_REX (REX_B);
13921       if (rex & REX_B)
13922         reg += 8;
13923     }
13924   else
13925     names = names_mm;
13926   oappend (names[reg]);
13927 }
13928
13929 /* cvt* are the only instructions in sse2 which have
13930    both SSE and MMX operands and also have 0x66 prefix
13931    in their opcode. 0x66 was originally used to differentiate
13932    between SSE and MMX instruction(operands). So we have to handle the
13933    cvt* separately using OP_EMC and OP_MXC */
13934 static void
13935 OP_EMC (int bytemode, int sizeflag)
13936 {
13937   if (modrm.mod != 3)
13938     {
13939       if (intel_syntax && bytemode == v_mode)
13940         {
13941           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13942           used_prefixes |= (prefixes & PREFIX_DATA);
13943         }
13944       OP_E (bytemode, sizeflag);
13945       return;
13946     }
13947
13948   /* Skip mod/rm byte.  */
13949   MODRM_CHECK;
13950   codep++;
13951   used_prefixes |= (prefixes & PREFIX_DATA);
13952   oappend (names_mm[modrm.rm]);
13953 }
13954
13955 static void
13956 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13957 {
13958   used_prefixes |= (prefixes & PREFIX_DATA);
13959   oappend (names_mm[modrm.reg]);
13960 }
13961
13962 static void
13963 OP_EX (int bytemode, int sizeflag)
13964 {
13965   int reg;
13966   const char **names;
13967
13968   /* Skip mod/rm byte.  */
13969   MODRM_CHECK;
13970   codep++;
13971
13972   if (modrm.mod != 3)
13973     {
13974       OP_E_memory (bytemode, sizeflag);
13975       return;
13976     }
13977
13978   reg = modrm.rm;
13979   USED_REX (REX_B);
13980   if (rex & REX_B)
13981     reg += 8;
13982
13983   if ((sizeflag & SUFFIX_ALWAYS)
13984       && (bytemode == x_swap_mode
13985           || bytemode == d_swap_mode
13986           || bytemode == d_scalar_swap_mode
13987           || bytemode == q_swap_mode
13988           || bytemode == q_scalar_swap_mode))
13989     swap_operand ();
13990
13991   if (need_vex
13992       && bytemode != xmm_mode
13993       && bytemode != xmmq_mode
13994       && bytemode != d_scalar_mode
13995       && bytemode != d_scalar_swap_mode
13996       && bytemode != q_scalar_mode
13997       && bytemode != q_scalar_swap_mode
13998       && bytemode != vex_scalar_w_dq_mode)
13999     {
14000       switch (vex.length)
14001         {
14002         case 128:
14003           names = names_xmm;
14004           break;
14005         case 256:
14006           names = names_ymm;
14007           break;
14008         default:
14009           abort ();
14010         }
14011     }
14012   else
14013     names = names_xmm;
14014   oappend (names[reg]);
14015 }
14016
14017 static void
14018 OP_MS (int bytemode, int sizeflag)
14019 {
14020   if (modrm.mod == 3)
14021     OP_EM (bytemode, sizeflag);
14022   else
14023     BadOp ();
14024 }
14025
14026 static void
14027 OP_XS (int bytemode, int sizeflag)
14028 {
14029   if (modrm.mod == 3)
14030     OP_EX (bytemode, sizeflag);
14031   else
14032     BadOp ();
14033 }
14034
14035 static void
14036 OP_M (int bytemode, int sizeflag)
14037 {
14038   if (modrm.mod == 3)
14039     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14040     BadOp ();
14041   else
14042     OP_E (bytemode, sizeflag);
14043 }
14044
14045 static void
14046 OP_0f07 (int bytemode, int sizeflag)
14047 {
14048   if (modrm.mod != 3 || modrm.rm != 0)
14049     BadOp ();
14050   else
14051     OP_E (bytemode, sizeflag);
14052 }
14053
14054 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14055    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
14056
14057 static void
14058 NOP_Fixup1 (int bytemode, int sizeflag)
14059 {
14060   if ((prefixes & PREFIX_DATA) != 0
14061       || (rex != 0
14062           && rex != 0x48
14063           && address_mode == mode_64bit))
14064     OP_REG (bytemode, sizeflag);
14065   else
14066     strcpy (obuf, "nop");
14067 }
14068
14069 static void
14070 NOP_Fixup2 (int bytemode, int sizeflag)
14071 {
14072   if ((prefixes & PREFIX_DATA) != 0
14073       || (rex != 0
14074           && rex != 0x48
14075           && address_mode == mode_64bit))
14076     OP_IMREG (bytemode, sizeflag);
14077 }
14078
14079 static const char *const Suffix3DNow[] = {
14080 /* 00 */        NULL,           NULL,           NULL,           NULL,
14081 /* 04 */        NULL,           NULL,           NULL,           NULL,
14082 /* 08 */        NULL,           NULL,           NULL,           NULL,
14083 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
14084 /* 10 */        NULL,           NULL,           NULL,           NULL,
14085 /* 14 */        NULL,           NULL,           NULL,           NULL,
14086 /* 18 */        NULL,           NULL,           NULL,           NULL,
14087 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
14088 /* 20 */        NULL,           NULL,           NULL,           NULL,
14089 /* 24 */        NULL,           NULL,           NULL,           NULL,
14090 /* 28 */        NULL,           NULL,           NULL,           NULL,
14091 /* 2C */        NULL,           NULL,           NULL,           NULL,
14092 /* 30 */        NULL,           NULL,           NULL,           NULL,
14093 /* 34 */        NULL,           NULL,           NULL,           NULL,
14094 /* 38 */        NULL,           NULL,           NULL,           NULL,
14095 /* 3C */        NULL,           NULL,           NULL,           NULL,
14096 /* 40 */        NULL,           NULL,           NULL,           NULL,
14097 /* 44 */        NULL,           NULL,           NULL,           NULL,
14098 /* 48 */        NULL,           NULL,           NULL,           NULL,
14099 /* 4C */        NULL,           NULL,           NULL,           NULL,
14100 /* 50 */        NULL,           NULL,           NULL,           NULL,
14101 /* 54 */        NULL,           NULL,           NULL,           NULL,
14102 /* 58 */        NULL,           NULL,           NULL,           NULL,
14103 /* 5C */        NULL,           NULL,           NULL,           NULL,
14104 /* 60 */        NULL,           NULL,           NULL,           NULL,
14105 /* 64 */        NULL,           NULL,           NULL,           NULL,
14106 /* 68 */        NULL,           NULL,           NULL,           NULL,
14107 /* 6C */        NULL,           NULL,           NULL,           NULL,
14108 /* 70 */        NULL,           NULL,           NULL,           NULL,
14109 /* 74 */        NULL,           NULL,           NULL,           NULL,
14110 /* 78 */        NULL,           NULL,           NULL,           NULL,
14111 /* 7C */        NULL,           NULL,           NULL,           NULL,
14112 /* 80 */        NULL,           NULL,           NULL,           NULL,
14113 /* 84 */        NULL,           NULL,           NULL,           NULL,
14114 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14115 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14116 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14117 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14118 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14119 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14120 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14121 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14122 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14123 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14124 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14125 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14126 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14127 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14128 /* C0 */        NULL,           NULL,           NULL,           NULL,
14129 /* C4 */        NULL,           NULL,           NULL,           NULL,
14130 /* C8 */        NULL,           NULL,           NULL,           NULL,
14131 /* CC */        NULL,           NULL,           NULL,           NULL,
14132 /* D0 */        NULL,           NULL,           NULL,           NULL,
14133 /* D4 */        NULL,           NULL,           NULL,           NULL,
14134 /* D8 */        NULL,           NULL,           NULL,           NULL,
14135 /* DC */        NULL,           NULL,           NULL,           NULL,
14136 /* E0 */        NULL,           NULL,           NULL,           NULL,
14137 /* E4 */        NULL,           NULL,           NULL,           NULL,
14138 /* E8 */        NULL,           NULL,           NULL,           NULL,
14139 /* EC */        NULL,           NULL,           NULL,           NULL,
14140 /* F0 */        NULL,           NULL,           NULL,           NULL,
14141 /* F4 */        NULL,           NULL,           NULL,           NULL,
14142 /* F8 */        NULL,           NULL,           NULL,           NULL,
14143 /* FC */        NULL,           NULL,           NULL,           NULL,
14144 };
14145
14146 static void
14147 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14148 {
14149   const char *mnemonic;
14150
14151   FETCH_DATA (the_info, codep + 1);
14152   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14153      place where an 8-bit immediate would normally go.  ie. the last
14154      byte of the instruction.  */
14155   obufp = mnemonicendp;
14156   mnemonic = Suffix3DNow[*codep++ & 0xff];
14157   if (mnemonic)
14158     oappend (mnemonic);
14159   else
14160     {
14161       /* Since a variable sized modrm/sib chunk is between the start
14162          of the opcode (0x0f0f) and the opcode suffix, we need to do
14163          all the modrm processing first, and don't know until now that
14164          we have a bad opcode.  This necessitates some cleaning up.  */
14165       op_out[0][0] = '\0';
14166       op_out[1][0] = '\0';
14167       BadOp ();
14168     }
14169   mnemonicendp = obufp;
14170 }
14171
14172 static struct op simd_cmp_op[] =
14173 {
14174   { STRING_COMMA_LEN ("eq") },
14175   { STRING_COMMA_LEN ("lt") },
14176   { STRING_COMMA_LEN ("le") },
14177   { STRING_COMMA_LEN ("unord") },
14178   { STRING_COMMA_LEN ("neq") },
14179   { STRING_COMMA_LEN ("nlt") },
14180   { STRING_COMMA_LEN ("nle") },
14181   { STRING_COMMA_LEN ("ord") }
14182 };
14183
14184 static void
14185 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14186 {
14187   unsigned int cmp_type;
14188
14189   FETCH_DATA (the_info, codep + 1);
14190   cmp_type = *codep++ & 0xff;
14191   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14192     {
14193       char suffix [3];
14194       char *p = mnemonicendp - 2;
14195       suffix[0] = p[0];
14196       suffix[1] = p[1];
14197       suffix[2] = '\0';
14198       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14199       mnemonicendp += simd_cmp_op[cmp_type].len;
14200     }
14201   else
14202     {
14203       /* We have a reserved extension byte.  Output it directly.  */
14204       scratchbuf[0] = '$';
14205       print_operand_value (scratchbuf + 1, 1, cmp_type);
14206       oappend (scratchbuf + intel_syntax);
14207       scratchbuf[0] = '\0';
14208     }
14209 }
14210
14211 static void
14212 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14213           int sizeflag ATTRIBUTE_UNUSED)
14214 {
14215   /* mwait %eax,%ecx  */
14216   if (!intel_syntax)
14217     {
14218       const char **names = (address_mode == mode_64bit
14219                             ? names64 : names32);
14220       strcpy (op_out[0], names[0]);
14221       strcpy (op_out[1], names[1]);
14222       two_source_ops = 1;
14223     }
14224   /* Skip mod/rm byte.  */
14225   MODRM_CHECK;
14226   codep++;
14227 }
14228
14229 static void
14230 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14231             int sizeflag ATTRIBUTE_UNUSED)
14232 {
14233   /* monitor %eax,%ecx,%edx"  */
14234   if (!intel_syntax)
14235     {
14236       const char **op1_names;
14237       const char **names = (address_mode == mode_64bit
14238                             ? names64 : names32);
14239
14240       if (!(prefixes & PREFIX_ADDR))
14241         op1_names = (address_mode == mode_16bit
14242                      ? names16 : names);
14243       else
14244         {
14245           /* Remove "addr16/addr32".  */
14246           all_prefixes[last_addr_prefix] = 0;
14247           op1_names = (address_mode != mode_32bit
14248                        ? names32 : names16);
14249           used_prefixes |= PREFIX_ADDR;
14250         }
14251       strcpy (op_out[0], op1_names[0]);
14252       strcpy (op_out[1], names[1]);
14253       strcpy (op_out[2], names[2]);
14254       two_source_ops = 1;
14255     }
14256   /* Skip mod/rm byte.  */
14257   MODRM_CHECK;
14258   codep++;
14259 }
14260
14261 static void
14262 BadOp (void)
14263 {
14264   /* Throw away prefixes and 1st. opcode byte.  */
14265   codep = insn_codep + 1;
14266   oappend ("(bad)");
14267 }
14268
14269 static void
14270 REP_Fixup (int bytemode, int sizeflag)
14271 {
14272   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14273      lods and stos.  */
14274   if (prefixes & PREFIX_REPZ)
14275     all_prefixes[last_repz_prefix] = REP_PREFIX;
14276
14277   switch (bytemode)
14278     {
14279     case al_reg:
14280     case eAX_reg:
14281     case indir_dx_reg:
14282       OP_IMREG (bytemode, sizeflag);
14283       break;
14284     case eDI_reg:
14285       OP_ESreg (bytemode, sizeflag);
14286       break;
14287     case eSI_reg:
14288       OP_DSreg (bytemode, sizeflag);
14289       break;
14290     default:
14291       abort ();
14292       break;
14293     }
14294 }
14295
14296 static void
14297 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14298 {
14299   USED_REX (REX_W);
14300   if (rex & REX_W)
14301     {
14302       /* Change cmpxchg8b to cmpxchg16b.  */
14303       char *p = mnemonicendp - 2;
14304       mnemonicendp = stpcpy (p, "16b");
14305       bytemode = o_mode;
14306     }
14307   OP_M (bytemode, sizeflag);
14308 }
14309
14310 static void
14311 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14312 {
14313   const char **names;
14314
14315   if (need_vex)
14316     {
14317       switch (vex.length)
14318         {
14319         case 128:
14320           names = names_xmm;
14321           break;
14322         case 256:
14323           names = names_ymm;
14324           break;
14325         default:
14326           abort ();
14327         }
14328     }
14329   else
14330     names = names_xmm;
14331   oappend (names[reg]);
14332 }
14333
14334 static void
14335 CRC32_Fixup (int bytemode, int sizeflag)
14336 {
14337   /* Add proper suffix to "crc32".  */
14338   char *p = mnemonicendp;
14339
14340   switch (bytemode)
14341     {
14342     case b_mode:
14343       if (intel_syntax)
14344         goto skip;
14345
14346       *p++ = 'b';
14347       break;
14348     case v_mode:
14349       if (intel_syntax)
14350         goto skip;
14351
14352       USED_REX (REX_W);
14353       if (rex & REX_W)
14354         *p++ = 'q';
14355       else
14356         {
14357           if (sizeflag & DFLAG)
14358             *p++ = 'l';
14359           else
14360             *p++ = 'w';
14361           used_prefixes |= (prefixes & PREFIX_DATA);
14362         }
14363       break;
14364     default:
14365       oappend (INTERNAL_DISASSEMBLER_ERROR);
14366       break;
14367     }
14368   mnemonicendp = p;
14369   *p = '\0';
14370
14371 skip:
14372   if (modrm.mod == 3)
14373     {
14374       int add;
14375
14376       /* Skip mod/rm byte.  */
14377       MODRM_CHECK;
14378       codep++;
14379
14380       USED_REX (REX_B);
14381       add = (rex & REX_B) ? 8 : 0;
14382       if (bytemode == b_mode)
14383         {
14384           USED_REX (0);
14385           if (rex)
14386             oappend (names8rex[modrm.rm + add]);
14387           else
14388             oappend (names8[modrm.rm + add]);
14389         }
14390       else
14391         {
14392           USED_REX (REX_W);
14393           if (rex & REX_W)
14394             oappend (names64[modrm.rm + add]);
14395           else if ((prefixes & PREFIX_DATA))
14396             oappend (names16[modrm.rm + add]);
14397           else
14398             oappend (names32[modrm.rm + add]);
14399         }
14400     }
14401   else
14402     OP_E (bytemode, sizeflag);
14403 }
14404
14405 static void
14406 FXSAVE_Fixup (int bytemode, int sizeflag)
14407 {
14408   /* Add proper suffix to "fxsave" and "fxrstor".  */
14409   USED_REX (REX_W);
14410   if (rex & REX_W)
14411     {
14412       char *p = mnemonicendp;
14413       *p++ = '6';
14414       *p++ = '4';
14415       *p = '\0';
14416       mnemonicendp = p;
14417     }
14418   OP_M (bytemode, sizeflag);
14419 }
14420
14421 /* Display the destination register operand for instructions with
14422    VEX. */
14423
14424 static void
14425 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14426 {
14427   int reg;
14428   const char **names;
14429
14430   if (!need_vex)
14431     abort ();
14432
14433   if (!need_vex_reg)
14434     return;
14435
14436   reg = vex.register_specifier;
14437   if (bytemode == vex_scalar_mode)
14438     {
14439       oappend (names_xmm[reg]);
14440       return;
14441     }
14442
14443   switch (vex.length)
14444     {
14445     case 128:
14446       switch (bytemode)
14447         {
14448         case vex_mode:
14449         case vex128_mode:
14450           break;
14451         default:
14452           abort ();
14453           return;
14454         }
14455
14456       names = names_xmm;
14457       break;
14458     case 256:
14459       switch (bytemode)
14460         {
14461         case vex_mode:
14462         case vex256_mode:
14463           break;
14464         default:
14465           abort ();
14466           return;
14467         }
14468
14469       names = names_ymm;
14470       break;
14471     default:
14472       abort ();
14473       break;
14474     }
14475   oappend (names[reg]);
14476 }
14477
14478 /* Get the VEX immediate byte without moving codep.  */
14479
14480 static unsigned char
14481 get_vex_imm8 (int sizeflag, int opnum)
14482 {
14483   int bytes_before_imm = 0;
14484
14485   if (modrm.mod != 3)
14486     {
14487       /* There are SIB/displacement bytes.  */
14488       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14489         {
14490           /* 32/64 bit address mode */
14491           int base = modrm.rm;
14492
14493           /* Check SIB byte.  */
14494           if (base == 4)
14495             {
14496               FETCH_DATA (the_info, codep + 1);
14497               base = *codep & 7;
14498               /* When decoding the third source, don't increase
14499                  bytes_before_imm as this has already been incremented
14500                  by one in OP_E_memory while decoding the second
14501                  source operand.  */
14502               if (opnum == 0)
14503                 bytes_before_imm++;
14504             }
14505
14506           /* Don't increase bytes_before_imm when decoding the third source,
14507              it has already been incremented by OP_E_memory while decoding
14508              the second source operand.  */
14509           if (opnum == 0)
14510             {
14511               switch (modrm.mod)
14512                 {
14513                   case 0:
14514                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14515                        SIB == 5, there is a 4 byte displacement.  */
14516                     if (base != 5)
14517                       /* No displacement. */
14518                       break;
14519                   case 2:
14520                     /* 4 byte displacement.  */
14521                     bytes_before_imm += 4;
14522                     break;
14523                   case 1:
14524                     /* 1 byte displacement.  */
14525                     bytes_before_imm++;
14526                     break;
14527                 }
14528             }
14529         }
14530       else
14531         {
14532           /* 16 bit address mode */
14533           /* Don't increase bytes_before_imm when decoding the third source,
14534              it has already been incremented by OP_E_memory while decoding
14535              the second source operand.  */
14536           if (opnum == 0)
14537             {
14538               switch (modrm.mod)
14539                 {
14540                 case 0:
14541                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14542                   if (modrm.rm != 6)
14543                     /* No displacement. */
14544                     break;
14545                 case 2:
14546                   /* 2 byte displacement.  */
14547                   bytes_before_imm += 2;
14548                   break;
14549                 case 1:
14550                   /* 1 byte displacement: when decoding the third source,
14551                      don't increase bytes_before_imm as this has already
14552                      been incremented by one in OP_E_memory while decoding
14553                      the second source operand.  */
14554                   if (opnum == 0)
14555                     bytes_before_imm++;
14556
14557                   break;
14558                 }
14559             }
14560         }
14561     }
14562
14563   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14564   return codep [bytes_before_imm];
14565 }
14566
14567 static void
14568 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14569 {
14570   const char **names;
14571
14572   if (reg == -1 && modrm.mod != 3)
14573     {
14574       OP_E_memory (bytemode, sizeflag);
14575       return;
14576     }
14577   else
14578     {
14579       if (reg == -1)
14580         {
14581           reg = modrm.rm;
14582           USED_REX (REX_B);
14583           if (rex & REX_B)
14584             reg += 8;
14585         }
14586       else if (reg > 7 && address_mode != mode_64bit)
14587         BadOp ();
14588     }
14589
14590   switch (vex.length)
14591     {
14592     case 128:
14593       names = names_xmm;
14594       break;
14595     case 256:
14596       names = names_ymm;
14597       break;
14598     default:
14599       abort ();
14600     }
14601   oappend (names[reg]);
14602 }
14603
14604 static void
14605 OP_EX_VexImmW (int bytemode, int sizeflag)
14606 {
14607   int reg = -1;
14608   static unsigned char vex_imm8;
14609
14610   if (vex_w_done == 0)
14611     {
14612       vex_w_done = 1;
14613
14614       /* Skip mod/rm byte.  */
14615       MODRM_CHECK;
14616       codep++;
14617
14618       vex_imm8 = get_vex_imm8 (sizeflag, 0);
14619
14620       if (vex.w)
14621           reg = vex_imm8 >> 4;
14622
14623       OP_EX_VexReg (bytemode, sizeflag, reg);
14624     }
14625   else if (vex_w_done == 1)
14626     {
14627       vex_w_done = 2;
14628
14629       if (!vex.w)
14630           reg = vex_imm8 >> 4;
14631
14632       OP_EX_VexReg (bytemode, sizeflag, reg);
14633     }
14634   else
14635     {
14636       /* Output the imm8 directly.  */
14637       scratchbuf[0] = '$';
14638       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14639       oappend (scratchbuf + intel_syntax);
14640       scratchbuf[0] = '\0';
14641       codep++;
14642     }
14643 }
14644
14645 static void
14646 OP_Vex_2src (int bytemode, int sizeflag)
14647 {
14648   if (modrm.mod == 3)
14649     {
14650       int reg = modrm.rm;
14651       USED_REX (REX_B);
14652       if (rex & REX_B)
14653         reg += 8;
14654       oappend (names_xmm[reg]);
14655     }
14656   else
14657     {
14658       if (intel_syntax
14659           && (bytemode == v_mode || bytemode == v_swap_mode))
14660         {
14661           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14662           used_prefixes |= (prefixes & PREFIX_DATA);
14663         }
14664       OP_E (bytemode, sizeflag);
14665     }
14666 }
14667
14668 static void
14669 OP_Vex_2src_1 (int bytemode, int sizeflag)
14670 {
14671   if (modrm.mod == 3)
14672     {
14673       /* Skip mod/rm byte.   */
14674       MODRM_CHECK;
14675       codep++;
14676     }
14677
14678   if (vex.w)
14679     oappend (names_xmm[vex.register_specifier]);
14680   else
14681     OP_Vex_2src (bytemode, sizeflag);
14682 }
14683
14684 static void
14685 OP_Vex_2src_2 (int bytemode, int sizeflag)
14686 {
14687   if (vex.w)
14688     OP_Vex_2src (bytemode, sizeflag);
14689   else
14690     oappend (names_xmm[vex.register_specifier]);
14691 }
14692
14693 static void
14694 OP_EX_VexW (int bytemode, int sizeflag)
14695 {
14696   int reg = -1;
14697
14698   if (!vex_w_done)
14699     {
14700       vex_w_done = 1;
14701
14702       /* Skip mod/rm byte.  */
14703       MODRM_CHECK;
14704       codep++;
14705
14706       if (vex.w)
14707         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14708     }
14709   else
14710     {
14711       if (!vex.w)
14712         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14713     }
14714
14715   OP_EX_VexReg (bytemode, sizeflag, reg);
14716 }
14717
14718 static void
14719 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14720              int sizeflag ATTRIBUTE_UNUSED)
14721 {
14722   /* Skip the immediate byte and check for invalid bits.  */
14723   FETCH_DATA (the_info, codep + 1);
14724   if (*codep++ & 0xf)
14725     BadOp ();
14726 }
14727
14728 static void
14729 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14730 {
14731   int reg;
14732   const char **names;
14733
14734   FETCH_DATA (the_info, codep + 1);
14735   reg = *codep++;
14736
14737   if (bytemode != x_mode)
14738     abort ();
14739
14740   if (reg & 0xf)
14741       BadOp ();
14742
14743   reg >>= 4;
14744   if (reg > 7 && address_mode != mode_64bit)
14745     BadOp ();
14746
14747   switch (vex.length)
14748     {
14749     case 128:
14750       names = names_xmm;
14751       break;
14752     case 256:
14753       names = names_ymm;
14754       break;
14755     default:
14756       abort ();
14757     }
14758   oappend (names[reg]);
14759 }
14760
14761 static void
14762 OP_XMM_VexW (int bytemode, int sizeflag)
14763 {
14764   /* Turn off the REX.W bit since it is used for swapping operands
14765      now.  */
14766   rex &= ~REX_W;
14767   OP_XMM (bytemode, sizeflag);
14768 }
14769
14770 static void
14771 OP_EX_Vex (int bytemode, int sizeflag)
14772 {
14773   if (modrm.mod != 3)
14774     {
14775       if (vex.register_specifier != 0)
14776         BadOp ();
14777       need_vex_reg = 0;
14778     }
14779   OP_EX (bytemode, sizeflag);
14780 }
14781
14782 static void
14783 OP_XMM_Vex (int bytemode, int sizeflag)
14784 {
14785   if (modrm.mod != 3)
14786     {
14787       if (vex.register_specifier != 0)
14788         BadOp ();
14789       need_vex_reg = 0;
14790     }
14791   OP_XMM (bytemode, sizeflag);
14792 }
14793
14794 static void
14795 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14796 {
14797   switch (vex.length)
14798     {
14799     case 128:
14800       mnemonicendp = stpcpy (obuf, "vzeroupper");
14801       break;
14802     case 256:
14803       mnemonicendp = stpcpy (obuf, "vzeroall");
14804       break;
14805     default:
14806       abort ();
14807     }
14808 }
14809
14810 static struct op vex_cmp_op[] =
14811 {
14812   { STRING_COMMA_LEN ("eq") },
14813   { STRING_COMMA_LEN ("lt") },
14814   { STRING_COMMA_LEN ("le") },
14815   { STRING_COMMA_LEN ("unord") },
14816   { STRING_COMMA_LEN ("neq") },
14817   { STRING_COMMA_LEN ("nlt") },
14818   { STRING_COMMA_LEN ("nle") },
14819   { STRING_COMMA_LEN ("ord") },
14820   { STRING_COMMA_LEN ("eq_uq") },
14821   { STRING_COMMA_LEN ("nge") },
14822   { STRING_COMMA_LEN ("ngt") },
14823   { STRING_COMMA_LEN ("false") },
14824   { STRING_COMMA_LEN ("neq_oq") },
14825   { STRING_COMMA_LEN ("ge") },
14826   { STRING_COMMA_LEN ("gt") },
14827   { STRING_COMMA_LEN ("true") },
14828   { STRING_COMMA_LEN ("eq_os") },
14829   { STRING_COMMA_LEN ("lt_oq") },
14830   { STRING_COMMA_LEN ("le_oq") },
14831   { STRING_COMMA_LEN ("unord_s") },
14832   { STRING_COMMA_LEN ("neq_us") },
14833   { STRING_COMMA_LEN ("nlt_uq") },
14834   { STRING_COMMA_LEN ("nle_uq") },
14835   { STRING_COMMA_LEN ("ord_s") },
14836   { STRING_COMMA_LEN ("eq_us") },
14837   { STRING_COMMA_LEN ("nge_uq") },
14838   { STRING_COMMA_LEN ("ngt_uq") },
14839   { STRING_COMMA_LEN ("false_os") },
14840   { STRING_COMMA_LEN ("neq_os") },
14841   { STRING_COMMA_LEN ("ge_oq") },
14842   { STRING_COMMA_LEN ("gt_oq") },
14843   { STRING_COMMA_LEN ("true_us") },
14844 };
14845
14846 static void
14847 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14848 {
14849   unsigned int cmp_type;
14850
14851   FETCH_DATA (the_info, codep + 1);
14852   cmp_type = *codep++ & 0xff;
14853   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14854     {
14855       char suffix [3];
14856       char *p = mnemonicendp - 2;
14857       suffix[0] = p[0];
14858       suffix[1] = p[1];
14859       suffix[2] = '\0';
14860       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14861       mnemonicendp += vex_cmp_op[cmp_type].len;
14862     }
14863   else
14864     {
14865       /* We have a reserved extension byte.  Output it directly.  */
14866       scratchbuf[0] = '$';
14867       print_operand_value (scratchbuf + 1, 1, cmp_type);
14868       oappend (scratchbuf + intel_syntax);
14869       scratchbuf[0] = '\0';
14870     }
14871 }
14872
14873 static const struct op pclmul_op[] =
14874 {
14875   { STRING_COMMA_LEN ("lql") },
14876   { STRING_COMMA_LEN ("hql") },
14877   { STRING_COMMA_LEN ("lqh") },
14878   { STRING_COMMA_LEN ("hqh") }
14879 };
14880
14881 static void
14882 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14883               int sizeflag ATTRIBUTE_UNUSED)
14884 {
14885   unsigned int pclmul_type;
14886
14887   FETCH_DATA (the_info, codep + 1);
14888   pclmul_type = *codep++ & 0xff;
14889   switch (pclmul_type)
14890     {
14891     case 0x10:
14892       pclmul_type = 2;
14893       break;
14894     case 0x11:
14895       pclmul_type = 3;
14896       break;
14897     default:
14898       break;
14899     }
14900   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14901     {
14902       char suffix [4];
14903       char *p = mnemonicendp - 3;
14904       suffix[0] = p[0];
14905       suffix[1] = p[1];
14906       suffix[2] = p[2];
14907       suffix[3] = '\0';
14908       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14909       mnemonicendp += pclmul_op[pclmul_type].len;
14910     }
14911   else
14912     {
14913       /* We have a reserved extension byte.  Output it directly.  */
14914       scratchbuf[0] = '$';
14915       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14916       oappend (scratchbuf + intel_syntax);
14917       scratchbuf[0] = '\0';
14918     }
14919 }
14920
14921 static void
14922 MOVBE_Fixup (int bytemode, int sizeflag)
14923 {
14924   /* Add proper suffix to "movbe".  */
14925   char *p = mnemonicendp;
14926
14927   switch (bytemode)
14928     {
14929     case v_mode:
14930       if (intel_syntax)
14931         goto skip;
14932
14933       USED_REX (REX_W);
14934       if (sizeflag & SUFFIX_ALWAYS)
14935         {
14936           if (rex & REX_W)
14937             *p++ = 'q';
14938           else
14939             {
14940               if (sizeflag & DFLAG)
14941                 *p++ = 'l';
14942               else
14943                 *p++ = 'w';
14944               used_prefixes |= (prefixes & PREFIX_DATA);
14945             }
14946         }
14947       break;
14948     default:
14949       oappend (INTERNAL_DISASSEMBLER_ERROR);
14950       break;
14951     }
14952   mnemonicendp = p;
14953   *p = '\0';
14954
14955 skip:
14956   OP_M (bytemode, sizeflag);
14957 }
14958
14959 static void
14960 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14961 {
14962   int reg;
14963   const char **names;
14964
14965   /* Skip mod/rm byte.  */
14966   MODRM_CHECK;
14967   codep++;
14968
14969   if (vex.w)
14970     names = names64;
14971   else
14972     names = names32;
14973
14974   reg = modrm.rm;
14975   USED_REX (REX_B);
14976   if (rex & REX_B)
14977     reg += 8;
14978
14979   oappend (names[reg]);
14980 }
14981
14982 static void
14983 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14984 {
14985   const char **names;
14986
14987   if (vex.w)
14988     names = names64;
14989   else
14990     names = names32;
14991
14992   oappend (names[vex.register_specifier]);
14993 }
14994