opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instuction support required */
  48   CpuClflush,
  49   /* SYSCALL Instuctions support required */
  50   CpuSYSCALL,
  51   /* Floating point support required */
  52   Cpu8087,
  53   /* i287 support required */
  54   Cpu287,
  55   /* i387 support required */
  56   Cpu387,
  57   /* i686 and floating point support required */
  58   Cpu687,
  59   /* SSE3 and floating point support required */
  60   CpuFISTTP,
  61   /* MMX support required */
  62   CpuMMX,
  63   /* SSE support required */
  64   CpuSSE,
  65   /* SSE2 support required */
  66   CpuSSE2,
  67   /* 3dnow! support required */
  68   Cpu3dnow,
  69   /* 3dnow! Extensions support required */
  70   Cpu3dnowA,
  71   /* SSE3 support required */
  72   CpuSSE3,
  73   /* VIA PadLock required */
  74   CpuPadLock,
  75   /* AMD Secure Virtual Machine Ext-s required */
  76   CpuSVME,
  77   /* VMX Instructions required */
  78   CpuVMX,
  79   /* SMX Instructions required */
  80   CpuSMX,
  81   /* SSSE3 support required */
  82   CpuSSSE3,
  83   /* SSE4a support required */
  84   CpuSSE4a,
  85   /* ABM New Instructions required */
  86   CpuABM,
  87   /* SSE4.1 support required */
  88   CpuSSE4_1,
  89   /* SSE4.2 support required */
  90   CpuSSE4_2,
  91   /* AVX support required */
  92   CpuAVX,
  93   /* Intel L1OM support required */
  94   CpuL1OM,
  95   /* Xsave/xrstor New Instuctions support required */
  96   CpuXsave,
  97   /* AES support required */
  98   CpuAES,
  99   /* PCLMUL support required */
 100   CpuPCLMUL,
 101   /* FMA support required */
 102   CpuFMA,
 103   /* FMA4 support required */
 104   CpuFMA4,
 105   /* XOP support required */
 106   CpuXOP,
 107   /* LWP support required */
 108   CpuLWP,
 109   /* MOVBE Instuction support required */
 110   CpuMovbe,
 111   /* EPT Instructions required */
 112   CpuEPT,
 113   /* RDTSCP Instuction support required */
 114   CpuRdtscp,
 115   /* 64bit support available, used by -march= in assembler.  */
 116   CpuLM,
 117   /* 64bit support required  */
 118   Cpu64,
 119   /* Not supported in the 64bit mode  */
 120   CpuNo64,
 121   /* The last bitfield in i386_cpu_flags.  */
 122   CpuMax = CpuNo64
 123 };
 124
 125 #define CpuNumOfUints \
 126   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 127 #define CpuNumOfBits \
 128   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 129
 130 /* If you get a compiler error for zero width of the unused field,
 131    comment it out.  */
 132 #define CpuUnused       (CpuMax + 1)
 133
 134 /* We can check if an instruction is available with array instead
 135    of bitfield. */
 136 typedef union i386_cpu_flags
 137 {
 138   struct
 139     {
 140       unsigned int cpui186:1;
 141       unsigned int cpui286:1;
 142       unsigned int cpui386:1;
 143       unsigned int cpui486:1;
 144       unsigned int cpui586:1;
 145       unsigned int cpui686:1;
 146       unsigned int cpuclflush:1;
 147       unsigned int cpusyscall:1;
 148       unsigned int cpu8087:1;
 149       unsigned int cpu287:1;
 150       unsigned int cpu387:1;
 151       unsigned int cpu687:1;
 152       unsigned int cpufisttp:1;
 153       unsigned int cpummx:1;
 154       unsigned int cpusse:1;
 155       unsigned int cpusse2:1;
 156       unsigned int cpua3dnow:1;
 157       unsigned int cpua3dnowa:1;
 158       unsigned int cpusse3:1;
 159       unsigned int cpupadlock:1;
 160       unsigned int cpusvme:1;
 161       unsigned int cpuvmx:1;
 162       unsigned int cpusmx:1;
 163       unsigned int cpussse3:1;
 164       unsigned int cpusse4a:1;
 165       unsigned int cpuabm:1;
 166       unsigned int cpusse4_1:1;
 167       unsigned int cpusse4_2:1;
 168       unsigned int cpuavx:1;
 169       unsigned int cpul1om:1;
 170       unsigned int cpuxsave:1;
 171       unsigned int cpuaes:1;
 172       unsigned int cpupclmul:1;
 173       unsigned int cpufma:1;
 174       unsigned int cpufma4:1;
 175       unsigned int cpuxop:1;
 176       unsigned int cpulwp:1;
 177       unsigned int cpumovbe:1;
 178       unsigned int cpuept:1;
 179       unsigned int cpurdtscp:1;
 180       unsigned int cpulm:1;
 181       unsigned int cpu64:1;
 182       unsigned int cpuno64:1;
 183 #ifdef CpuUnused
 184       unsigned int unused:(CpuNumOfBits - CpuUnused);
 185 #endif
 186     } bitfield;
 187   unsigned int array[CpuNumOfUints];
 188 } i386_cpu_flags;
 189
 190 /* Position of opcode_modifier bits.  */
 191
 192 enum
 193 {
 194   /* has direction bit. */
 195   D = 0,
 196   /* set if operands can be words or dwords encoded the canonical way */
 197   W,
 198   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 199      operand in encoding.  */
 200   S,
 201   /* insn has a modrm byte. */
 202   Modrm,
 203   /* register is in low 3 bits of opcode */
 204   ShortForm,
 205   /* special case for jump insns.  */
 206   Jump,
 207   /* call and jump */
 208   JumpDword,
 209   /* loop and jecxz */
 210   JumpByte,
 211   /* special case for intersegment leaps/calls */
 212   JumpInterSegment,
 213   /* FP insn memory format bit, sized by 0x4 */
 214   FloatMF,
 215   /* src/dest swap for floats. */
 216   FloatR,
 217   /* has float insn direction bit. */
 218   FloatD,
 219   /* needs size prefix if in 32-bit mode */
 220   Size16,
 221   /* needs size prefix if in 16-bit mode */
 222   Size32,
 223   /* needs size prefix if in 64-bit mode */
 224   Size64,
 225   /* instruction ignores operand size prefix and in Intel mode ignores
 226      mnemonic size suffix check.  */
 227   IgnoreSize,
 228   /* default insn size depends on mode */
 229   DefaultSize,
 230   /* b suffix on instruction illegal */
 231   No_bSuf,
 232   /* w suffix on instruction illegal */
 233   No_wSuf,
 234   /* l suffix on instruction illegal */
 235   No_lSuf,
 236   /* s suffix on instruction illegal */
 237   No_sSuf,
 238   /* q suffix on instruction illegal */
 239   No_qSuf,
 240   /* long double suffix on instruction illegal */
 241   No_ldSuf,
 242   /* instruction needs FWAIT */
 243   FWait,
 244   /* quick test for string instructions */
 245   IsString,
 246   /* quick test for lockable instructions */
 247   IsLockable,
 248   /* fake an extra reg operand for clr, imul and special register
 249      processing for some instructions.  */
 250   RegKludge,
 251   /* The first operand must be xmm0 */
 252   FirstXmm0,
 253   /* An implicit xmm0 as the first operand */
 254   Implicit1stXmm0,
 255   /* Convert to DWORD */
 256   ToDword,
 257   /* Convert to QWORD */
 258   ToQword,
 259   /* Address prefix changes operand 0 */
 260   AddrPrefixOp0,
 261   /* opcode is a prefix */
 262   IsPrefix,
 263   /* instruction has extension in 8 bit imm */
 264   ImmExt,
 265   /* instruction don't need Rex64 prefix.  */
 266   NoRex64,
 267   /* instruction require Rex64 prefix.  */
 268   Rex64,
 269   /* deprecated fp insn, gets a warning */
 270   Ugh,
 271   /* insn has VEX prefix:
 272         1: 128bit VEX prefix.
 273         2: 256bit VEX prefix.
 274    */
 275 #define VEX128  1
 276 #define VEX256  2
 277   Vex,
 278   /* How to encode VEX.vvvv:
 279      0: VEX.vvvv must be 1111b.
 280      1: VEX.DNS.  Register-only source is encoded in VEX.vvvv where
 281         the content of source registers will be preserved.
 282         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 283         where the content of first source register will be overwritten
 284         by the result.
 285         For assembler, there are no difference between VEX.DNS and
 286         VEX.DDS.
 287      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
 288      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 289         of the operands can access a memory location.
 290    */
 291 #define VEXXDS  1
 292 #define VEXNDD  2
 293 #define VEXLWP  3
 294   VexVVVV,
 295   /* How the VEX.W bit is used:
 296      0: Set by the REX.W bit.
 297      1: VEX.W0.  Should always be 0.
 298      2: VEX.W1.  Should always be 1.
 299    */
 300 #define VEXW0   1
 301 #define VEXW1   2
 302   VexW,
 303   /* VEX opcode prefix:
 304      0: VEX 0x0F opcode prefix.
 305      1: VEX 0x0F38 opcode prefix.
 306      2: VEX 0x0F3A opcode prefix
 307      3: XOP 0x08 opcode prefix.
 308      4: XOP 0x09 opcode prefix
 309      5: XOP 0x0A opcode prefix.
 310    */
 311 #define VEX0F           0
 312 #define VEX0F38         1
 313 #define VEX0F3A         2
 314 #define XOP08           3
 315 #define XOP09           4
 316 #define XOP0A           5
 317   VexOpcode,
 318   /* number of VEX source operands:
 319      0: <= 2 source operands.
 320      1: 2 XOP source operands.
 321      2: 3 source operands.
 322    */
 323 #define XOP2SOURCES     1
 324 #define VEX3SOURCES     2
 325   VexSources,
 326   /* instruction has VEX 8 bit imm */
 327   VexImmExt,
 328   /* SSE to AVX support required */
 329   SSE2AVX,
 330   /* No AVX equivalent */
 331   NoAVX,
 332   /* Compatible with old (<= 2.8.1) versions of gcc  */
 333   OldGcc,
 334   /* AT&T mnemonic.  */
 335   ATTMnemonic,
 336   /* AT&T syntax.  */
 337   ATTSyntax,
 338   /* Intel syntax.  */
 339   IntelSyntax,
 340   /* The last bitfield in i386_opcode_modifier.  */
 341   Opcode_Modifier_Max
 342 };
 343
 344 typedef struct i386_opcode_modifier
 345 {
 346   unsigned int d:1;
 347   unsigned int w:1;
 348   unsigned int s:1;
 349   unsigned int modrm:1;
 350   unsigned int shortform:1;
 351   unsigned int jump:1;
 352   unsigned int jumpdword:1;
 353   unsigned int jumpbyte:1;
 354   unsigned int jumpintersegment:1;
 355   unsigned int floatmf:1;
 356   unsigned int floatr:1;
 357   unsigned int floatd:1;
 358   unsigned int size16:1;
 359   unsigned int size32:1;
 360   unsigned int size64:1;
 361   unsigned int ignoresize:1;
 362   unsigned int defaultsize:1;
 363   unsigned int no_bsuf:1;
 364   unsigned int no_wsuf:1;
 365   unsigned int no_lsuf:1;
 366   unsigned int no_ssuf:1;
 367   unsigned int no_qsuf:1;
 368   unsigned int no_ldsuf:1;
 369   unsigned int fwait:1;
 370   unsigned int isstring:1;
 371   unsigned int islockable:1;
 372   unsigned int regkludge:1;
 373   unsigned int firstxmm0:1;
 374   unsigned int implicit1stxmm0:1;
 375   unsigned int todword:1;
 376   unsigned int toqword:1;
 377   unsigned int addrprefixop0:1;
 378   unsigned int isprefix:1;
 379   unsigned int immext:1;
 380   unsigned int norex64:1;
 381   unsigned int rex64:1;
 382   unsigned int ugh:1;
 383   unsigned int vex:2;
 384   unsigned int vexvvvv:2;
 385   unsigned int vexw:2;
 386   unsigned int vexopcode:3;
 387   unsigned int vexsources:2;
 388   unsigned int veximmext:1;
 389   unsigned int sse2avx:1;
 390   unsigned int noavx:1;
 391   unsigned int oldgcc:1;
 392   unsigned int attmnemonic:1;
 393   unsigned int attsyntax:1;
 394   unsigned int intelsyntax:1;
 395 } i386_opcode_modifier;
 396
 397 /* Position of operand_type bits.  */
 398
 399 enum
 400 {
 401   /* 8bit register */
 402   Reg8 = 0,
 403   /* 16bit register */
 404   Reg16,
 405   /* 32bit register */
 406   Reg32,
 407   /* 64bit register */
 408   Reg64,
 409   /* Floating pointer stack register */
 410   FloatReg,
 411   /* MMX register */
 412   RegMMX,
 413   /* SSE register */
 414   RegXMM,
 415   /* AVX registers */
 416   RegYMM,
 417   /* Control register */
 418   Control,
 419   /* Debug register */
 420   Debug,
 421   /* Test register */
 422   Test,
 423   /* 2 bit segment register */
 424   SReg2,
 425   /* 3 bit segment register */
 426   SReg3,
 427   /* 1 bit immediate */
 428   Imm1,
 429   /* 8 bit immediate */
 430   Imm8,
 431   /* 8 bit immediate sign extended */
 432   Imm8S,
 433   /* 16 bit immediate */
 434   Imm16,
 435   /* 32 bit immediate */
 436   Imm32,
 437   /* 32 bit immediate sign extended */
 438   Imm32S,
 439   /* 64 bit immediate */
 440   Imm64,
 441   /* 8bit/16bit/32bit displacements are used in different ways,
 442      depending on the instruction.  For jumps, they specify the
 443      size of the PC relative displacement, for instructions with
 444      memory operand, they specify the size of the offset relative
 445      to the base register, and for instructions with memory offset
 446      such as `mov 1234,%al' they specify the size of the offset
 447      relative to the segment base.  */
 448   /* 8 bit displacement */
 449   Disp8,
 450   /* 16 bit displacement */
 451   Disp16,
 452   /* 32 bit displacement */
 453   Disp32,
 454   /* 32 bit signed displacement */
 455   Disp32S,
 456   /* 64 bit displacement */
 457   Disp64,
 458   /* Accumulator %al/%ax/%eax/%rax */
 459   Acc,
 460   /* Floating pointer top stack register %st(0) */
 461   FloatAcc,
 462   /* Register which can be used for base or index in memory operand.  */
 463   BaseIndex,
 464   /* Register to hold in/out port addr = dx */
 465   InOutPortReg,
 466   /* Register to hold shift count = cl */
 467   ShiftCount,
 468   /* Absolute address for jump.  */
 469   JumpAbsolute,
 470   /* String insn operand with fixed es segment */
 471   EsSeg,
 472   /* RegMem is for instructions with a modrm byte where the register
 473      destination operand should be encoded in the mod and regmem fields.
 474      Normally, it will be encoded in the reg field. We add a RegMem
 475      flag to the destination register operand to indicate that it should
 476      be encoded in the regmem field.  */
 477   RegMem,
 478   /* Memory.  */
 479   Mem,
 480   /* BYTE memory. */
 481   Byte,
 482   /* WORD memory. 2 byte */
 483   Word,
 484   /* DWORD memory. 4 byte */
 485   Dword,
 486   /* FWORD memory. 6 byte */
 487   Fword,
 488   /* QWORD memory. 8 byte */
 489   Qword,
 490   /* TBYTE memory. 10 byte */
 491   Tbyte,
 492   /* XMMWORD memory. */
 493   Xmmword,
 494   /* YMMWORD memory. */
 495   Ymmword,
 496   /* Unspecified memory size.  */
 497   Unspecified,
 498   /* Any memory size.  */
 499   Anysize,
 500
 501   /* The last bitfield in i386_operand_type.  */
 502   OTMax
 503 };
 504
 505 #define OTNumOfUints \
 506   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 507 #define OTNumOfBits \
 508   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 509
 510 /* If you get a compiler error for zero width of the unused field,
 511    comment it out.  */
 512 #define OTUnused                (OTMax + 1)
 513
 514 typedef union i386_operand_type
 515 {
 516   struct
 517     {
 518       unsigned int reg8:1;
 519       unsigned int reg16:1;
 520       unsigned int reg32:1;
 521       unsigned int reg64:1;
 522       unsigned int floatreg:1;
 523       unsigned int regmmx:1;
 524       unsigned int regxmm:1;
 525       unsigned int regymm:1;
 526       unsigned int control:1;
 527       unsigned int debug:1;
 528       unsigned int test:1;
 529       unsigned int sreg2:1;
 530       unsigned int sreg3:1;
 531       unsigned int imm1:1;
 532       unsigned int imm8:1;
 533       unsigned int imm8s:1;
 534       unsigned int imm16:1;
 535       unsigned int imm32:1;
 536       unsigned int imm32s:1;
 537       unsigned int imm64:1;
 538       unsigned int disp8:1;
 539       unsigned int disp16:1;
 540       unsigned int disp32:1;
 541       unsigned int disp32s:1;
 542       unsigned int disp64:1;
 543       unsigned int acc:1;
 544       unsigned int floatacc:1;
 545       unsigned int baseindex:1;
 546       unsigned int inoutportreg:1;
 547       unsigned int shiftcount:1;
 548       unsigned int jumpabsolute:1;
 549       unsigned int esseg:1;
 550       unsigned int regmem:1;
 551       unsigned int mem:1;
 552       unsigned int byte:1;
 553       unsigned int word:1;
 554       unsigned int dword:1;
 555       unsigned int fword:1;
 556       unsigned int qword:1;
 557       unsigned int tbyte:1;
 558       unsigned int xmmword:1;
 559       unsigned int ymmword:1;
 560       unsigned int unspecified:1;
 561       unsigned int anysize:1;
 562 #ifdef OTUnused
 563       unsigned int unused:(OTNumOfBits - OTUnused);
 564 #endif
 565     } bitfield;
 566   unsigned int array[OTNumOfUints];
 567 } i386_operand_type;
 568
 569 typedef struct insn_template
 570 {
 571   /* instruction name sans width suffix ("mov" for movl insns) */
 572   char *name;
 573
 574   /* how many operands */
 575   unsigned int operands;
 576
 577   /* base_opcode is the fundamental opcode byte without optional
 578      prefix(es).  */
 579   unsigned int base_opcode;
 580 #define Opcode_D        0x2 /* Direction bit:
 581                                set if Reg --> Regmem;
 582                                unset if Regmem --> Reg. */
 583 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 584 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 585
 586   /* extension_opcode is the 3 bit extension for group <n> insns.
 587      This field is also used to store the 8-bit opcode suffix for the
 588      AMD 3DNow! instructions.
 589      If this template has no extension opcode (the usual case) use None
 590      Instructions */
 591   unsigned int extension_opcode;
 592 #define None 0xffff             /* If no extension_opcode is possible.  */
 593
 594   /* Opcode length.  */
 595   unsigned char opcode_length;
 596
 597   /* cpu feature flags */
 598   i386_cpu_flags cpu_flags;
 599
 600   /* the bits in opcode_modifier are used to generate the final opcode from
 601      the base_opcode.  These bits also are used to detect alternate forms of
 602      the same instruction */
 603   i386_opcode_modifier opcode_modifier;
 604
 605   /* operand_types[i] describes the type of operand i.  This is made
 606      by OR'ing together all of the possible type masks.  (e.g.
 607      'operand_types[i] = Reg|Imm' specifies that operand i can be
 608      either a register or an immediate operand.  */
 609   i386_operand_type operand_types[MAX_OPERANDS];
 610 }
 611 insn_template;
 612
 613 extern const insn_template i386_optab[];
 614
 615 /* these are for register name --> number & type hash lookup */
 616 typedef struct
 617 {
 618   char *reg_name;
 619   i386_operand_type reg_type;
 620   unsigned char reg_flags;
 621 #define RegRex      0x1  /* Extended register.  */
 622 #define RegRex64    0x2  /* Extended 8 bit register.  */
 623   unsigned char reg_num;
 624 #define RegRip  ((unsigned char ) ~0)
 625 #define RegEip  (RegRip - 1)
 626 /* EIZ and RIZ are fake index registers.  */
 627 #define RegEiz  (RegEip - 1)
 628 #define RegRiz  (RegEiz - 1)
 629 /* FLAT is a fake segment register (Intel mode).  */
 630 #define RegFlat     ((unsigned char) ~0)
 631   signed char dw2_regnum[2];
 632 #define Dw2Inval (-1)
 633 }
 634 reg_entry;
 635
 636 /* Entries in i386_regtab.  */
 637 #define REGNAM_AL 1
 638 #define REGNAM_AX 25
 639 #define REGNAM_EAX 41
 640
 641 extern const reg_entry i386_regtab[];
 642 extern const unsigned int i386_regtab_size;
 643
 644 typedef struct
 645 {
 646   char *seg_name;
 647   unsigned int seg_prefix;
 648 }
 649 seg_entry;
 650
 651 extern const seg_entry cs;
 652 extern const seg_entry ds;
 653 extern const seg_entry ss;
 654 extern const seg_entry es;
 655 extern const seg_entry fs;
 656 extern const seg_entry gs;