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gas: blackfin: fix DBG/DBGCMPLX insn encoding
[binutils.git] / opcodes / bfin-dis.c
blobe58917b5c536f8aa64f18f568117a7919b8da012
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3
4 This file is part of libopcodes.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include <stdio.h>
22 #include <stdlib.h>
23 #include <string.h>
24
25 #include "opcode/bfin.h"
26
27 #define M_S2RND 1
28 #define M_T 2
29 #define M_W32 3
30 #define M_FU 4
31 #define M_TFU 6
32 #define M_IS 8
33 #define M_ISS2 9
34 #define M_IH 11
35 #define M_IU 12
36
37 #ifndef PRINTF
38 #define PRINTF printf
39 #endif
40
41 #ifndef EXIT
42 #define EXIT exit
43 #endif
44
45 typedef long TIword;
46
47 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
48 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
49 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
50 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
51
52 #include "dis-asm.h"
53
54 typedef unsigned int bu32;
55
56 static char comment = 0;
57 static char parallel = 0;
58
59 typedef enum
60 {
61 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
62 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
63 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
64 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
65 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
66 } const_forms_t;
67
68 static const struct
69 {
70 const char *name;
71 const int nbits;
72 const char reloc;
73 const char issigned;
74 const char pcrel;
75 const char scale;
76 const char offset;
77 const char negative;
78 const char positive;
79 const char decimal;
80 const char leading;
81 const char exact;
82 } constant_formats[] =
83 {
84 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
85 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
86 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
88 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
89 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
91 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
92 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
94 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
95 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
97 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
98 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
99 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
100 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
101 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
102 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
103 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
104 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
107 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
108 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
109 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
110 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
111 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
112 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
113 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
114 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
118 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
119 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
120 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
121 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
123 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
124 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
125 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
127 };
128
129 static const char *
130 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
131 {
132 static char buf[60];
133
134 if (constant_formats[cf].reloc)
135 {
136 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
137 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
138 if (constant_formats[cf].pcrel)
139 ea += pc;
140
141 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
142 {
143 outf->print_address_func (ea, outf);
144 return "";
145 }
146 else
147 {
148 sprintf (buf, "%lx", (unsigned long) x);
149 return buf;
150 }
151 }
152
153 /* Negative constants have an implied sign bit. */
154 if (constant_formats[cf].negative)
155 {
156 int nb = constant_formats[cf].nbits + 1;
157
158 x = x | (1 << constant_formats[cf].nbits);
159 x = SIGNEXTEND (x, nb);
160 }
161 else
162 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
163
164 if (constant_formats[cf].offset)
165 x += constant_formats[cf].offset;
166
167 if (constant_formats[cf].scale)
168 x <<= constant_formats[cf].scale;
169
170 if (constant_formats[cf].decimal)
171 {
172 if (constant_formats[cf].leading)
173 {
174 char ps[10];
175 sprintf (ps, "%%%ii", constant_formats[cf].leading);
176 sprintf (buf, ps, x);
177 }
178 else
179 sprintf (buf, "%li", x);
180 }
181 else
182 {
183 if (constant_formats[cf].issigned && x < 0)
184 sprintf (buf, "-0x%x", abs (x));
185 else
186 sprintf (buf, "0x%lx", (unsigned long) x);
187 }
188
189 return buf;
190 }
191
192 static bu32
193 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
194 {
195 if (0 && constant_formats[cf].reloc)
196 {
197 bu32 ea = (((constant_formats[cf].pcrel
198 ? SIGNEXTEND (x, constant_formats[cf].nbits)
199 : x) + constant_formats[cf].offset)
200 << constant_formats[cf].scale);
201 if (constant_formats[cf].pcrel)
202 ea += pc;
203
204 return ea;
205 }
206
207 /* Negative constants have an implied sign bit. */
208 if (constant_formats[cf].negative)
209 {
210 int nb = constant_formats[cf].nbits + 1;
211 x = x | (1 << constant_formats[cf].nbits);
212 x = SIGNEXTEND (x, nb);
213 }
214 else if (constant_formats[cf].issigned)
215 x = SIGNEXTEND (x, constant_formats[cf].nbits);
216
217 x += constant_formats[cf].offset;
218 x <<= constant_formats[cf].scale;
219
220 return x;
221 }
222
223 enum machine_registers
224 {
225 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
226 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
227 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
228 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
229 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
230 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
231 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
232 REG_L2, REG_L3,
233 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
234 REG_AQ, REG_V, REG_VS,
235 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
236 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
237 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
238 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
239 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
240 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
241 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
242 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
243 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
244 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
245 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
246 REG_LASTREG,
247 };
248
249 enum reg_class
250 {
251 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
252 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
253 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
254 rc_sysregs3, rc_allregs,
255 LIM_REG_CLASSES
256 };
257
258 static const char *reg_names[] =
259 {
260 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
261 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
262 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
263 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
264 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
265 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
266 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
267 "L2", "L3",
268 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
269 "AQ", "V", "VS",
270 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
271 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
272 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
273 "RETE", "EMUDAT",
274 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
275 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
276 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
277 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
278 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
279 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
280 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
281 "AC0_COPY", "V_COPY", "RND_MOD",
282 "LASTREG",
283 0
284 };
285
286 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
287
288 /* RL(0..7). */
289 static enum machine_registers decode_dregs_lo[] =
290 {
291 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
292 };
293
294 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
295
296 /* RH(0..7). */
297 static enum machine_registers decode_dregs_hi[] =
298 {
299 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
300 };
301
302 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
303
304 /* R(0..7). */
305 static enum machine_registers decode_dregs[] =
306 {
307 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
308 };
309
310 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
311
312 /* R BYTE(0..7). */
313 static enum machine_registers decode_dregs_byte[] =
314 {
315 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
316 };
317
318 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
319
320 /* P(0..5) SP FP. */
321 static enum machine_registers decode_pregs[] =
322 {
323 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
324 };
325
326 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
327 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
328 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
329 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
330 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
331 #define accum(x) REGNAME (decode_accum[(x) & 1])
332
333 /* I(0..3). */
334 static enum machine_registers decode_iregs[] =
335 {
336 REG_I0, REG_I1, REG_I2, REG_I3,
337 };
338
339 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
340
341 /* M(0..3). */
342 static enum machine_registers decode_mregs[] =
343 {
344 REG_M0, REG_M1, REG_M2, REG_M3,
345 };
346
347 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
348 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
349 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
350
351 /* dregs pregs. */
352 static enum machine_registers decode_dpregs[] =
353 {
354 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
355 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
356 };
357
358 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
359
360 /* [dregs pregs]. */
361 static enum machine_registers decode_gregs[] =
362 {
363 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
364 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
365 };
366
367 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
368
369 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
370 static enum machine_registers decode_regs[] =
371 {
372 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
373 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
374 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
375 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
376 };
377
378 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
379
380 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
381 static enum machine_registers decode_regs_lo[] =
382 {
383 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
384 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
385 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
386 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
387 };
388
389 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
390 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
391 static enum machine_registers decode_regs_hi[] =
392 {
393 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
394 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
395 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
396 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
397 };
398
399 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
400
401 static enum machine_registers decode_statbits[] =
402 {
403 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
404 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
405 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
406 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
407 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
408 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
409 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
410 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
411 };
412
413 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
414
415 /* LC0 LC1. */
416 static enum machine_registers decode_counters[] =
417 {
418 REG_LC0, REG_LC1,
419 };
420
421 #define counters(x) REGNAME (decode_counters[(x) & 1])
422 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
423
424 /* [dregs pregs (iregs mregs) (bregs lregs)
425 dregs2_sysregs1 open sysregs2 sysregs3]. */
426 static enum machine_registers decode_allregs[] =
427 {
428 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
429 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
430 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
431 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
432 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
433 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
434 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
435 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
436 REG_LASTREG,
437 };
438
439 #define IS_DREG(g,r) ((g) == 0)
440 #define IS_PREG(g,r) ((g) == 1)
441 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
442 #define IS_GENREG(g,r) ((g) == 0 || (g) == 1 || IS_AREG (g, r))
443 #define IS_DAGREG(g,r) ((g) == 2 || (g) == 3)
444 #define IS_SYSREG(g,r) \
445 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
446
447 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
448 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
449 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
450 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
451 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
452 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
453 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
454 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
455 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
456 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
457 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
458 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
459 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
460 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
461 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
462 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
463 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
464 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
465 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
466 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
467 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
468 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
469 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
470 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
471 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
472 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
473 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
474 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
475 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
476 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
477 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
478 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
479 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
480 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
481 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
482 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
483 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
484 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
485 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
486 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
487 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
488 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
489 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
490
491 /* (arch.pm)arch_disassembler_functions. */
492 #ifndef OUTS
493 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
494 #endif
495
496 static void
497 amod0 (int s0, int x0, disassemble_info *outf)
498 {
499 if (s0 == 1 && x0 == 0)
500 OUTS (outf, " (S)");
501 else if (s0 == 0 && x0 == 1)
502 OUTS (outf, " (CO)");
503 else if (s0 == 1 && x0 == 1)
504 OUTS (outf, " (SCO)");
505 }
506
507 static void
508 amod1 (int s0, int x0, disassemble_info *outf)
509 {
510 if (s0 == 0 && x0 == 0)
511 OUTS (outf, " (NS)");
512 else if (s0 == 1 && x0 == 0)
513 OUTS (outf, " (S)");
514 }
515
516 static void
517 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
518 {
519 if (s0 == 1 && x0 == 0 && aop0 == 0)
520 OUTS (outf, " (S)");
521 else if (s0 == 0 && x0 == 1 && aop0 == 0)
522 OUTS (outf, " (CO)");
523 else if (s0 == 1 && x0 == 1 && aop0 == 0)
524 OUTS (outf, " (SCO)");
525 else if (s0 == 0 && x0 == 0 && aop0 == 2)
526 OUTS (outf, " (ASR)");
527 else if (s0 == 1 && x0 == 0 && aop0 == 2)
528 OUTS (outf, " (S, ASR)");
529 else if (s0 == 0 && x0 == 1 && aop0 == 2)
530 OUTS (outf, " (CO, ASR)");
531 else if (s0 == 1 && x0 == 1 && aop0 == 2)
532 OUTS (outf, " (SCO, ASR)");
533 else if (s0 == 0 && x0 == 0 && aop0 == 3)
534 OUTS (outf, " (ASL)");
535 else if (s0 == 1 && x0 == 0 && aop0 == 3)
536 OUTS (outf, " (S, ASL)");
537 else if (s0 == 0 && x0 == 1 && aop0 == 3)
538 OUTS (outf, " (CO, ASL)");
539 else if (s0 == 1 && x0 == 1 && aop0 == 3)
540 OUTS (outf, " (SCO, ASL)");
541 }
542
543 static void
544 searchmod (int r0, disassemble_info *outf)
545 {
546 if (r0 == 0)
547 OUTS (outf, "GT");
548 else if (r0 == 1)
549 OUTS (outf, "GE");
550 else if (r0 == 2)
551 OUTS (outf, "LT");
552 else if (r0 == 3)
553 OUTS (outf, "LE");
554 }
555
556 static void
557 aligndir (int r0, disassemble_info *outf)
558 {
559 if (r0 == 1)
560 OUTS (outf, " (R)");
561 }
562
563 static int
564 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
565 {
566 const char *s0, *s1;
567
568 if (h0)
569 s0 = dregs_hi (src0);
570 else
571 s0 = dregs_lo (src0);
572
573 if (h1)
574 s1 = dregs_hi (src1);
575 else
576 s1 = dregs_lo (src1);
577
578 OUTS (outf, s0);
579 OUTS (outf, " * ");
580 OUTS (outf, s1);
581 return 0;
582 }
583
584 static int
585 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
586 {
587 const char *a;
588 const char *sop = "<unknown op>";
589
590 if (which)
591 a = "A1";
592 else
593 a = "A0";
594
595 if (op == 3)
596 {
597 OUTS (outf, a);
598 return 0;
599 }
600
601 switch (op)
602 {
603 case 0: sop = " = "; break;
604 case 1: sop = " += "; break;
605 case 2: sop = " -= "; break;
606 default: break;
607 }
608
609 OUTS (outf, a);
610 OUTS (outf, sop);
611 decode_multfunc (h0, h1, src0, src1, outf);
612
613 return 0;
614 }
615
616 static void
617 decode_optmode (int mod, int MM, disassemble_info *outf)
618 {
619 if (mod == 0 && MM == 0)
620 return;
621
622 OUTS (outf, " (");
623
624 if (MM && !mod)
625 {
626 OUTS (outf, "M)");
627 return;
628 }
629
630 if (MM)
631 OUTS (outf, "M, ");
632
633 if (mod == M_S2RND)
634 OUTS (outf, "S2RND");
635 else if (mod == M_T)
636 OUTS (outf, "T");
637 else if (mod == M_W32)
638 OUTS (outf, "W32");
639 else if (mod == M_FU)
640 OUTS (outf, "FU");
641 else if (mod == M_TFU)
642 OUTS (outf, "TFU");
643 else if (mod == M_IS)
644 OUTS (outf, "IS");
645 else if (mod == M_ISS2)
646 OUTS (outf, "ISS2");
647 else if (mod == M_IH)
648 OUTS (outf, "IH");
649 else if (mod == M_IU)
650 OUTS (outf, "IU");
651 else
652 abort ();
653
654 OUTS (outf, ")");
655 }
656
657 struct saved_state
658 {
659 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
660 bu32 a0x, a0w, a1x, a1w;
661 bu32 lt[2], lc[2], lb[2];
662 int ac0, ac0_copy, ac1, an, aq;
663 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
664 int rnd_mod;
665 int v_internal;
666 bu32 pc, rets;
667
668 int ticks;
669 int insts;
670
671 int exception;
672
673 int end_of_registers;
674
675 int msize;
676 unsigned char *memory;
677 unsigned long bfd_mach;
678 } saved_state;
679
680 #define DREG(x) (saved_state.dpregs[x])
681 #define GREG(x,i) DPREG ((x) | (i << 3))
682 #define DPREG(x) (saved_state.dpregs[x])
683 #define DREG(x) (saved_state.dpregs[x])
684 #define PREG(x) (saved_state.dpregs[x + 8])
685 #define SPREG PREG (6)
686 #define FPREG PREG (7)
687 #define IREG(x) (saved_state.iregs[x])
688 #define MREG(x) (saved_state.mregs[x])
689 #define BREG(x) (saved_state.bregs[x])
690 #define LREG(x) (saved_state.lregs[x])
691 #define A0XREG (saved_state.a0x)
692 #define A0WREG (saved_state.a0w)
693 #define A1XREG (saved_state.a1x)
694 #define A1WREG (saved_state.a1w)
695 #define CCREG (saved_state.cc)
696 #define LC0REG (saved_state.lc[0])
697 #define LT0REG (saved_state.lt[0])
698 #define LB0REG (saved_state.lb[0])
699 #define LC1REG (saved_state.lc[1])
700 #define LT1REG (saved_state.lt[1])
701 #define LB1REG (saved_state.lb[1])
702 #define RETSREG (saved_state.rets)
703 #define PCREG (saved_state.pc)
704
705 static bu32 *
706 get_allreg (int grp, int reg)
707 {
708 int fullreg = (grp << 3) | reg;
709 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
710 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
711 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
712 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
713 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
714 , , , , , , , ,
715 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
716 REG_CYCLES2,
717 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
718 REG_LASTREG */
719 switch (fullreg >> 2)
720 {
721 case 0: case 1: return &DREG (reg); break;
722 case 2: case 3: return &PREG (reg); break;
723 case 4: return &IREG (reg & 3); break;
724 case 5: return &MREG (reg & 3); break;
725 case 6: return &BREG (reg & 3); break;
726 case 7: return &LREG (reg & 3); break;
727 default:
728 switch (fullreg)
729 {
730 case 32: return &saved_state.a0x;
731 case 33: return &saved_state.a0w;
732 case 34: return &saved_state.a1x;
733 case 35: return &saved_state.a1w;
734 case 39: return &saved_state.rets;
735 case 48: return &LC0REG;
736 case 49: return &LT0REG;
737 case 50: return &LB0REG;
738 case 51: return &LC1REG;
739 case 52: return &LT1REG;
740 case 53: return &LB1REG;
741 }
742 return 0;
743 }
744 }
745
746 static int
747 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
748 {
749 /* ProgCtrl
750 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
751 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
752 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
753 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
754 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
755
756 if (prgfunc == 0 && poprnd == 0)
757 OUTS (outf, "NOP");
758 else if (prgfunc == 1 && poprnd == 0)
759 OUTS (outf, "RTS");
760 else if (prgfunc == 1 && poprnd == 1)
761 OUTS (outf, "RTI");
762 else if (prgfunc == 1 && poprnd == 2)
763 OUTS (outf, "RTX");
764 else if (prgfunc == 1 && poprnd == 3)
765 OUTS (outf, "RTN");
766 else if (prgfunc == 1 && poprnd == 4)
767 OUTS (outf, "RTE");
768 else if (prgfunc == 2 && poprnd == 0)
769 OUTS (outf, "IDLE");
770 else if (prgfunc == 2 && poprnd == 3)
771 OUTS (outf, "CSYNC");
772 else if (prgfunc == 2 && poprnd == 4)
773 OUTS (outf, "SSYNC");
774 else if (prgfunc == 2 && poprnd == 5)
775 OUTS (outf, "EMUEXCPT");
776 else if (prgfunc == 3)
777 {
778 OUTS (outf, "CLI ");
779 OUTS (outf, dregs (poprnd));
780 }
781 else if (prgfunc == 4)
782 {
783 OUTS (outf, "STI ");
784 OUTS (outf, dregs (poprnd));
785 }
786 else if (prgfunc == 5)
787 {
788 OUTS (outf, "JUMP (");
789 OUTS (outf, pregs (poprnd));
790 OUTS (outf, ")");
791 }
792 else if (prgfunc == 6)
793 {
794 OUTS (outf, "CALL (");
795 OUTS (outf, pregs (poprnd));
796 OUTS (outf, ")");
797 }
798 else if (prgfunc == 7)
799 {
800 OUTS (outf, "CALL (PC + ");
801 OUTS (outf, pregs (poprnd));
802 OUTS (outf, ")");
803 }
804 else if (prgfunc == 8)
805 {
806 OUTS (outf, "JUMP (PC + ");
807 OUTS (outf, pregs (poprnd));
808 OUTS (outf, ")");
809 }
810 else if (prgfunc == 9)
811 {
812 OUTS (outf, "RAISE ");
813 OUTS (outf, uimm4 (poprnd));
814 }
815 else if (prgfunc == 10)
816 {
817 OUTS (outf, "EXCPT ");
818 OUTS (outf, uimm4 (poprnd));
819 }
820 else if (prgfunc == 11)
821 {
822 OUTS (outf, "TESTSET (");
823 OUTS (outf, pregs (poprnd));
824 OUTS (outf, ")");
825 }
826 else
827 return 0;
828 return 2;
829 }
830
831 static int
832 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
833 {
834 /* CaCTRL
835 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
836 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
837 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
838 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
839 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
840 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
841
842 if (a == 0 && op == 0)
843 {
844 OUTS (outf, "PREFETCH[");
845 OUTS (outf, pregs (reg));
846 OUTS (outf, "]");
847 }
848 else if (a == 0 && op == 1)
849 {
850 OUTS (outf, "FLUSHINV[");
851 OUTS (outf, pregs (reg));
852 OUTS (outf, "]");
853 }
854 else if (a == 0 && op == 2)
855 {
856 OUTS (outf, "FLUSH[");
857 OUTS (outf, pregs (reg));
858 OUTS (outf, "]");
859 }
860 else if (a == 0 && op == 3)
861 {
862 OUTS (outf, "IFLUSH[");
863 OUTS (outf, pregs (reg));
864 OUTS (outf, "]");
865 }
866 else if (a == 1 && op == 0)
867 {
868 OUTS (outf, "PREFETCH[");
869 OUTS (outf, pregs (reg));
870 OUTS (outf, "++]");
871 }
872 else if (a == 1 && op == 1)
873 {
874 OUTS (outf, "FLUSHINV[");
875 OUTS (outf, pregs (reg));
876 OUTS (outf, "++]");
877 }
878 else if (a == 1 && op == 2)
879 {
880 OUTS (outf, "FLUSH[");
881 OUTS (outf, pregs (reg));
882 OUTS (outf, "++]");
883 }
884 else if (a == 1 && op == 3)
885 {
886 OUTS (outf, "IFLUSH[");
887 OUTS (outf, pregs (reg));
888 OUTS (outf, "++]");
889 }
890 else
891 return 0;
892 return 2;
893 }
894
895 static int
896 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
897 {
898 /* PushPopReg
899 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
901 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
902 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
903 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
904 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
905
906 if (W == 0)
907 {
908 OUTS (outf, allregs (reg, grp));
909 OUTS (outf, " = [SP++]");
910 }
911 else if (W == 1)
912 {
913 OUTS (outf, "[--SP] = ");
914 OUTS (outf, allregs (reg, grp));
915 }
916 else
917 return 0;
918 return 2;
919 }
920
921 static int
922 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
923 {
924 /* PushPopMultiple
925 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
926 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
927 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
928 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
929 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
930 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
931 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
932 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
933
934 if (W == 1 && d == 1 && p == 1)
935 {
936 OUTS (outf, "[--SP] = (R7:");
937 OUTS (outf, imm5d (dr));
938 OUTS (outf, ", P5:");
939 OUTS (outf, imm5d (pr));
940 OUTS (outf, ")");
941 }
942 else if (W == 1 && d == 1 && p == 0)
943 {
944 OUTS (outf, "[--SP] = (R7:");
945 OUTS (outf, imm5d (dr));
946 OUTS (outf, ")");
947 }
948 else if (W == 1 && d == 0 && p == 1)
949 {
950 OUTS (outf, "[--SP] = (P5:");
951 OUTS (outf, imm5d (pr));
952 OUTS (outf, ")");
953 }
954 else if (W == 0 && d == 1 && p == 1)
955 {
956 OUTS (outf, "(R7:");
957 OUTS (outf, imm5d (dr));
958 OUTS (outf, ", P5:");
959 OUTS (outf, imm5d (pr));
960 OUTS (outf, ") = [SP++]");
961 }
962 else if (W == 0 && d == 1 && p == 0)
963 {
964 OUTS (outf, "(R7:");
965 OUTS (outf, imm5d (dr));
966 OUTS (outf, ") = [SP++]");
967 }
968 else if (W == 0 && d == 0 && p == 1)
969 {
970 OUTS (outf, "(P5:");
971 OUTS (outf, imm5d (pr));
972 OUTS (outf, ") = [SP++]");
973 }
974 else
975 return 0;
976 return 2;
977 }
978
979 static int
980 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
981 {
982 /* ccMV
983 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
984 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
985 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
986 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
987 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
988 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
989 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
990 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
991
992 if (T == 1)
993 {
994 OUTS (outf, "IF CC ");
995 OUTS (outf, gregs (dst, d));
996 OUTS (outf, " = ");
997 OUTS (outf, gregs (src, s));
998 }
999 else if (T == 0)
1000 {
1001 OUTS (outf, "IF !CC ");
1002 OUTS (outf, gregs (dst, d));
1003 OUTS (outf, " = ");
1004 OUTS (outf, gregs (src, s));
1005 }
1006 else
1007 return 0;
1008 return 2;
1009 }
1010
1011 static int
1012 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1013 {
1014 /* CCflag
1015 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1016 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1017 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1018 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1019 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1020 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1021 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1022 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1023
1024 if (opc == 0 && I == 0 && G == 0)
1025 {
1026 OUTS (outf, "CC = ");
1027 OUTS (outf, dregs (x));
1028 OUTS (outf, " == ");
1029 OUTS (outf, dregs (y));
1030 }
1031 else if (opc == 1 && I == 0 && G == 0)
1032 {
1033 OUTS (outf, "CC = ");
1034 OUTS (outf, dregs (x));
1035 OUTS (outf, " < ");
1036 OUTS (outf, dregs (y));
1037 }
1038 else if (opc == 2 && I == 0 && G == 0)
1039 {
1040 OUTS (outf, "CC = ");
1041 OUTS (outf, dregs (x));
1042 OUTS (outf, " <= ");
1043 OUTS (outf, dregs (y));
1044 }
1045 else if (opc == 3 && I == 0 && G == 0)
1046 {
1047 OUTS (outf, "CC = ");
1048 OUTS (outf, dregs (x));
1049 OUTS (outf, " < ");
1050 OUTS (outf, dregs (y));
1051 OUTS (outf, " (IU)");
1052 }
1053 else if (opc == 4 && I == 0 && G == 0)
1054 {
1055 OUTS (outf, "CC = ");
1056 OUTS (outf, dregs (x));
1057 OUTS (outf, " <= ");
1058 OUTS (outf, dregs (y));
1059 OUTS (outf, " (IU)");
1060 }
1061 else if (opc == 0 && I == 1 && G == 0)
1062 {
1063 OUTS (outf, "CC = ");
1064 OUTS (outf, dregs (x));
1065 OUTS (outf, " == ");
1066 OUTS (outf, imm3 (y));
1067 }
1068 else if (opc == 1 && I == 1 && G == 0)
1069 {
1070 OUTS (outf, "CC = ");
1071 OUTS (outf, dregs (x));
1072 OUTS (outf, " < ");
1073 OUTS (outf, imm3 (y));
1074 }
1075 else if (opc == 2 && I == 1 && G == 0)
1076 {
1077 OUTS (outf, "CC = ");
1078 OUTS (outf, dregs (x));
1079 OUTS (outf, " <= ");
1080 OUTS (outf, imm3 (y));
1081 }
1082 else if (opc == 3 && I == 1 && G == 0)
1083 {
1084 OUTS (outf, "CC = ");
1085 OUTS (outf, dregs (x));
1086 OUTS (outf, " < ");
1087 OUTS (outf, uimm3 (y));
1088 OUTS (outf, " (IU)");
1089 }
1090 else if (opc == 4 && I == 1 && G == 0)
1091 {
1092 OUTS (outf, "CC = ");
1093 OUTS (outf, dregs (x));
1094 OUTS (outf, " <= ");
1095 OUTS (outf, uimm3 (y));
1096 OUTS (outf, " (IU)");
1097 }
1098 else if (opc == 0 && I == 0 && G == 1)
1099 {
1100 OUTS (outf, "CC = ");
1101 OUTS (outf, pregs (x));
1102 OUTS (outf, " == ");
1103 OUTS (outf, pregs (y));
1104 }
1105 else if (opc == 1 && I == 0 && G == 1)
1106 {
1107 OUTS (outf, "CC = ");
1108 OUTS (outf, pregs (x));
1109 OUTS (outf, " < ");
1110 OUTS (outf, pregs (y));
1111 }
1112 else if (opc == 2 && I == 0 && G == 1)
1113 {
1114 OUTS (outf, "CC = ");
1115 OUTS (outf, pregs (x));
1116 OUTS (outf, " <= ");
1117 OUTS (outf, pregs (y));
1118 }
1119 else if (opc == 3 && I == 0 && G == 1)
1120 {
1121 OUTS (outf, "CC = ");
1122 OUTS (outf, pregs (x));
1123 OUTS (outf, " < ");
1124 OUTS (outf, pregs (y));
1125 OUTS (outf, " (IU)");
1126 }
1127 else if (opc == 4 && I == 0 && G == 1)
1128 {
1129 OUTS (outf, "CC = ");
1130 OUTS (outf, pregs (x));
1131 OUTS (outf, " <= ");
1132 OUTS (outf, pregs (y));
1133 OUTS (outf, " (IU)");
1134 }
1135 else if (opc == 0 && I == 1 && G == 1)
1136 {
1137 OUTS (outf, "CC = ");
1138 OUTS (outf, pregs (x));
1139 OUTS (outf, " == ");
1140 OUTS (outf, imm3 (y));
1141 }
1142 else if (opc == 1 && I == 1 && G == 1)
1143 {
1144 OUTS (outf, "CC = ");
1145 OUTS (outf, pregs (x));
1146 OUTS (outf, " < ");
1147 OUTS (outf, imm3 (y));
1148 }
1149 else if (opc == 2 && I == 1 && G == 1)
1150 {
1151 OUTS (outf, "CC = ");
1152 OUTS (outf, pregs (x));
1153 OUTS (outf, " <= ");
1154 OUTS (outf, imm3 (y));
1155 }
1156 else if (opc == 3 && I == 1 && G == 1)
1157 {
1158 OUTS (outf, "CC = ");
1159 OUTS (outf, pregs (x));
1160 OUTS (outf, " < ");
1161 OUTS (outf, uimm3 (y));
1162 OUTS (outf, " (IU)");
1163 }
1164 else if (opc == 4 && I == 1 && G == 1)
1165 {
1166 OUTS (outf, "CC = ");
1167 OUTS (outf, pregs (x));
1168 OUTS (outf, " <= ");
1169 OUTS (outf, uimm3 (y));
1170 OUTS (outf, " (IU)");
1171 }
1172 else if (opc == 5 && I == 0 && G == 0)
1173 OUTS (outf, "CC = A0 == A1");
1174
1175 else if (opc == 6 && I == 0 && G == 0)
1176 OUTS (outf, "CC = A0 < A1");
1177
1178 else if (opc == 7 && I == 0 && G == 0)
1179 OUTS (outf, "CC = A0 <= A1");
1180
1181 else
1182 return 0;
1183 return 2;
1184 }
1185
1186 static int
1187 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1188 {
1189 /* CC2dreg
1190 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1191 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1192 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1193 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1194 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1195
1196 if (op == 0)
1197 {
1198 OUTS (outf, dregs (reg));
1199 OUTS (outf, " = CC");
1200 }
1201 else if (op == 1)
1202 {
1203 OUTS (outf, "CC = ");
1204 OUTS (outf, dregs (reg));
1205 }
1206 else if (op == 3)
1207 OUTS (outf, "CC = !CC");
1208 else
1209 return 0;
1210
1211 return 2;
1212 }
1213
1214 static int
1215 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1216 {
1217 /* CC2stat
1218 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1219 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1220 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1221 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1222 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1223 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1224
1225 if (op == 0 && D == 0)
1226 {
1227 OUTS (outf, "CC = ");
1228 OUTS (outf, statbits (cbit));
1229 }
1230 else if (op == 1 && D == 0)
1231 {
1232 OUTS (outf, "CC |= ");
1233 OUTS (outf, statbits (cbit));
1234 }
1235 else if (op == 2 && D == 0)
1236 {
1237 OUTS (outf, "CC &= ");
1238 OUTS (outf, statbits (cbit));
1239 }
1240 else if (op == 3 && D == 0)
1241 {
1242 OUTS (outf, "CC ^= ");
1243 OUTS (outf, statbits (cbit));
1244 }
1245 else if (op == 0 && D == 1)
1246 {
1247 OUTS (outf, statbits (cbit));
1248 OUTS (outf, " = CC");
1249 }
1250 else if (op == 1 && D == 1)
1251 {
1252 OUTS (outf, statbits (cbit));
1253 OUTS (outf, " |= CC");
1254 }
1255 else if (op == 2 && D == 1)
1256 {
1257 OUTS (outf, statbits (cbit));
1258 OUTS (outf, " &= CC");
1259 }
1260 else if (op == 3 && D == 1)
1261 {
1262 OUTS (outf, statbits (cbit));
1263 OUTS (outf, " ^= CC");
1264 }
1265 else
1266 return 0;
1267
1268 return 2;
1269 }
1270
1271 static int
1272 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1273 {
1274 /* BRCC
1275 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1276 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1277 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1278 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1279 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1280 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1281
1282 if (T == 1 && B == 1)
1283 {
1284 OUTS (outf, "IF CC JUMP 0x");
1285 OUTS (outf, pcrel10 (offset));
1286 OUTS (outf, " (BP)");
1287 }
1288 else if (T == 0 && B == 1)
1289 {
1290 OUTS (outf, "IF !CC JUMP 0x");
1291 OUTS (outf, pcrel10 (offset));
1292 OUTS (outf, " (BP)");
1293 }
1294 else if (T == 1)
1295 {
1296 OUTS (outf, "IF CC JUMP 0x");
1297 OUTS (outf, pcrel10 (offset));
1298 }
1299 else if (T == 0)
1300 {
1301 OUTS (outf, "IF !CC JUMP 0x");
1302 OUTS (outf, pcrel10 (offset));
1303 }
1304 else
1305 return 0;
1306
1307 return 2;
1308 }
1309
1310 static int
1311 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1312 {
1313 /* UJUMP
1314 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1315 | 0 | 0 | 1 | 0 |.offset........................................|
1316 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1317 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1318
1319 OUTS (outf, "JUMP.S 0x");
1320 OUTS (outf, pcrel12 (offset));
1321 return 2;
1322 }
1323
1324 static int
1325 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1326 {
1327 /* REGMV
1328 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1329 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1330 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1331 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1332 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1333 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1334 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1335
1336 if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src))
1337 || (IS_GENREG (gd, dst) && IS_DAGREG (gs, src))
1338 || (IS_DAGREG (gd, dst) && IS_GENREG (gs, src))
1339 || (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src))
1340 || (IS_GENREG (gd, dst) && gs == 7 && src == 0)
1341 || (gd == 7 && dst == 0 && IS_GENREG (gs, src))
1342 || (IS_DREG (gd, dst) && IS_SYSREG (gs, src))
1343 || (IS_PREG (gd, dst) && IS_SYSREG (gs, src))
1344 || (IS_SYSREG (gd, dst) && IS_DREG (gs, src))
1345 || (IS_SYSREG (gd, dst) && IS_PREG (gs, src))
1346 || (IS_SYSREG (gd, dst) && gs == 7 && src == 0)))
1347 return 0;
1348
1349 OUTS (outf, allregs (dst, gd));
1350 OUTS (outf, " = ");
1351 OUTS (outf, allregs (src, gs));
1352 return 2;
1353 }
1354
1355 static int
1356 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1357 {
1358 /* ALU2op
1359 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1360 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1361 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1362 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1363 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1364 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1365
1366 if (opc == 0)
1367 {
1368 OUTS (outf, dregs (dst));
1369 OUTS (outf, " >>>= ");
1370 OUTS (outf, dregs (src));
1371 }
1372 else if (opc == 1)
1373 {
1374 OUTS (outf, dregs (dst));
1375 OUTS (outf, " >>= ");
1376 OUTS (outf, dregs (src));
1377 }
1378 else if (opc == 2)
1379 {
1380 OUTS (outf, dregs (dst));
1381 OUTS (outf, " <<= ");
1382 OUTS (outf, dregs (src));
1383 }
1384 else if (opc == 3)
1385 {
1386 OUTS (outf, dregs (dst));
1387 OUTS (outf, " *= ");
1388 OUTS (outf, dregs (src));
1389 }
1390 else if (opc == 4)
1391 {
1392 OUTS (outf, dregs (dst));
1393 OUTS (outf, " = (");
1394 OUTS (outf, dregs (dst));
1395 OUTS (outf, " + ");
1396 OUTS (outf, dregs (src));
1397 OUTS (outf, ") << 0x1");
1398 }
1399 else if (opc == 5)
1400 {
1401 OUTS (outf, dregs (dst));
1402 OUTS (outf, " = (");
1403 OUTS (outf, dregs (dst));
1404 OUTS (outf, " + ");
1405 OUTS (outf, dregs (src));
1406 OUTS (outf, ") << 0x2");
1407 }
1408 else if (opc == 8)
1409 {
1410 OUTS (outf, "DIVQ (");
1411 OUTS (outf, dregs (dst));
1412 OUTS (outf, ", ");
1413 OUTS (outf, dregs (src));
1414 OUTS (outf, ")");
1415 }
1416 else if (opc == 9)
1417 {
1418 OUTS (outf, "DIVS (");
1419 OUTS (outf, dregs (dst));
1420 OUTS (outf, ", ");
1421 OUTS (outf, dregs (src));
1422 OUTS (outf, ")");
1423 }
1424 else if (opc == 10)
1425 {
1426 OUTS (outf, dregs (dst));
1427 OUTS (outf, " = ");
1428 OUTS (outf, dregs_lo (src));
1429 OUTS (outf, " (X)");
1430 }
1431 else if (opc == 11)
1432 {
1433 OUTS (outf, dregs (dst));
1434 OUTS (outf, " = ");
1435 OUTS (outf, dregs_lo (src));
1436 OUTS (outf, " (Z)");
1437 }
1438 else if (opc == 12)
1439 {
1440 OUTS (outf, dregs (dst));
1441 OUTS (outf, " = ");
1442 OUTS (outf, dregs_byte (src));
1443 OUTS (outf, " (X)");
1444 }
1445 else if (opc == 13)
1446 {
1447 OUTS (outf, dregs (dst));
1448 OUTS (outf, " = ");
1449 OUTS (outf, dregs_byte (src));
1450 OUTS (outf, " (Z)");
1451 }
1452 else if (opc == 14)
1453 {
1454 OUTS (outf, dregs (dst));
1455 OUTS (outf, " = -");
1456 OUTS (outf, dregs (src));
1457 }
1458 else if (opc == 15)
1459 {
1460 OUTS (outf, dregs (dst));
1461 OUTS (outf, " =~ ");
1462 OUTS (outf, dregs (src));
1463 }
1464 else
1465 return 0;
1466
1467 return 2;
1468 }
1469
1470 static int
1471 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1472 {
1473 /* PTR2op
1474 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1475 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1476 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1477 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1478 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1479 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1480
1481 if (opc == 0)
1482 {
1483 OUTS (outf, pregs (dst));
1484 OUTS (outf, " -= ");
1485 OUTS (outf, pregs (src));
1486 }
1487 else if (opc == 1)
1488 {
1489 OUTS (outf, pregs (dst));
1490 OUTS (outf, " = ");
1491 OUTS (outf, pregs (src));
1492 OUTS (outf, " << 0x2");
1493 }
1494 else if (opc == 3)
1495 {
1496 OUTS (outf, pregs (dst));
1497 OUTS (outf, " = ");
1498 OUTS (outf, pregs (src));
1499 OUTS (outf, " >> 0x2");
1500 }
1501 else if (opc == 4)
1502 {
1503 OUTS (outf, pregs (dst));
1504 OUTS (outf, " = ");
1505 OUTS (outf, pregs (src));
1506 OUTS (outf, " >> 0x1");
1507 }
1508 else if (opc == 5)
1509 {
1510 OUTS (outf, pregs (dst));
1511 OUTS (outf, " += ");
1512 OUTS (outf, pregs (src));
1513 OUTS (outf, " (BREV)");
1514 }
1515 else if (opc == 6)
1516 {
1517 OUTS (outf, pregs (dst));
1518 OUTS (outf, " = (");
1519 OUTS (outf, pregs (dst));
1520 OUTS (outf, " + ");
1521 OUTS (outf, pregs (src));
1522 OUTS (outf, ") << 0x1");
1523 }
1524 else if (opc == 7)
1525 {
1526 OUTS (outf, pregs (dst));
1527 OUTS (outf, " = (");
1528 OUTS (outf, pregs (dst));
1529 OUTS (outf, " + ");
1530 OUTS (outf, pregs (src));
1531 OUTS (outf, ") << 0x2");
1532 }
1533 else
1534 return 0;
1535
1536 return 2;
1537 }
1538
1539 static int
1540 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1541 {
1542 /* LOGI2op
1543 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1544 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1545 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1546 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1547 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1548 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1549
1550 if (opc == 0)
1551 {
1552 OUTS (outf, "CC = !BITTST (");
1553 OUTS (outf, dregs (dst));
1554 OUTS (outf, ", ");
1555 OUTS (outf, uimm5 (src));
1556 OUTS (outf, ");\t\t/* bit");
1557 OUTS (outf, imm7d (src));
1558 OUTS (outf, " */");
1559 comment = 1;
1560 }
1561 else if (opc == 1)
1562 {
1563 OUTS (outf, "CC = BITTST (");
1564 OUTS (outf, dregs (dst));
1565 OUTS (outf, ", ");
1566 OUTS (outf, uimm5 (src));
1567 OUTS (outf, ");\t\t/* bit");
1568 OUTS (outf, imm7d (src));
1569 OUTS (outf, " */");
1570 comment = 1;
1571 }
1572 else if (opc == 2)
1573 {
1574 OUTS (outf, "BITSET (");
1575 OUTS (outf, dregs (dst));
1576 OUTS (outf, ", ");
1577 OUTS (outf, uimm5 (src));
1578 OUTS (outf, ");\t\t/* bit");
1579 OUTS (outf, imm7d (src));
1580 OUTS (outf, " */");
1581 comment = 1;
1582 }
1583 else if (opc == 3)
1584 {
1585 OUTS (outf, "BITTGL (");
1586 OUTS (outf, dregs (dst));
1587 OUTS (outf, ", ");
1588 OUTS (outf, uimm5 (src));
1589 OUTS (outf, ");\t\t/* bit");
1590 OUTS (outf, imm7d (src));
1591 OUTS (outf, " */");
1592 comment = 1;
1593 }
1594 else if (opc == 4)
1595 {
1596 OUTS (outf, "BITCLR (");
1597 OUTS (outf, dregs (dst));
1598 OUTS (outf, ", ");
1599 OUTS (outf, uimm5 (src));
1600 OUTS (outf, ");\t\t/* bit");
1601 OUTS (outf, imm7d (src));
1602 OUTS (outf, " */");
1603 comment = 1;
1604 }
1605 else if (opc == 5)
1606 {
1607 OUTS (outf, dregs (dst));
1608 OUTS (outf, " >>>= ");
1609 OUTS (outf, uimm5 (src));
1610 }
1611 else if (opc == 6)
1612 {
1613 OUTS (outf, dregs (dst));
1614 OUTS (outf, " >>= ");
1615 OUTS (outf, uimm5 (src));
1616 }
1617 else if (opc == 7)
1618 {
1619 OUTS (outf, dregs (dst));
1620 OUTS (outf, " <<= ");
1621 OUTS (outf, uimm5 (src));
1622 }
1623 else
1624 return 0;
1625
1626 return 2;
1627 }
1628
1629 static int
1630 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1631 {
1632 /* COMP3op
1633 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1634 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1635 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1636 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1637 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1638 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1639 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1640
1641 if (opc == 5 && src1 == src0)
1642 {
1643 OUTS (outf, pregs (dst));
1644 OUTS (outf, " = ");
1645 OUTS (outf, pregs (src0));
1646 OUTS (outf, " << 0x1");
1647 }
1648 else if (opc == 1)
1649 {
1650 OUTS (outf, dregs (dst));
1651 OUTS (outf, " = ");
1652 OUTS (outf, dregs (src0));
1653 OUTS (outf, " - ");
1654 OUTS (outf, dregs (src1));
1655 }
1656 else if (opc == 2)
1657 {
1658 OUTS (outf, dregs (dst));
1659 OUTS (outf, " = ");
1660 OUTS (outf, dregs (src0));
1661 OUTS (outf, " & ");
1662 OUTS (outf, dregs (src1));
1663 }
1664 else if (opc == 3)
1665 {
1666 OUTS (outf, dregs (dst));
1667 OUTS (outf, " = ");
1668 OUTS (outf, dregs (src0));
1669 OUTS (outf, " | ");
1670 OUTS (outf, dregs (src1));
1671 }
1672 else if (opc == 4)
1673 {
1674 OUTS (outf, dregs (dst));
1675 OUTS (outf, " = ");
1676 OUTS (outf, dregs (src0));
1677 OUTS (outf, " ^ ");
1678 OUTS (outf, dregs (src1));
1679 }
1680 else if (opc == 5)
1681 {
1682 OUTS (outf, pregs (dst));
1683 OUTS (outf, " = ");
1684 OUTS (outf, pregs (src0));
1685 OUTS (outf, " + ");
1686 OUTS (outf, pregs (src1));
1687 }
1688 else if (opc == 6)
1689 {
1690 OUTS (outf, pregs (dst));
1691 OUTS (outf, " = ");
1692 OUTS (outf, pregs (src0));
1693 OUTS (outf, " + (");
1694 OUTS (outf, pregs (src1));
1695 OUTS (outf, " << 0x1)");
1696 }
1697 else if (opc == 7)
1698 {
1699 OUTS (outf, pregs (dst));
1700 OUTS (outf, " = ");
1701 OUTS (outf, pregs (src0));
1702 OUTS (outf, " + (");
1703 OUTS (outf, pregs (src1));
1704 OUTS (outf, " << 0x2)");
1705 }
1706 else if (opc == 0)
1707 {
1708 OUTS (outf, dregs (dst));
1709 OUTS (outf, " = ");
1710 OUTS (outf, dregs (src0));
1711 OUTS (outf, " + ");
1712 OUTS (outf, dregs (src1));
1713 }
1714 else
1715 return 0;
1716
1717 return 2;
1718 }
1719
1720 static int
1721 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1722 {
1723 /* COMPI2opD
1724 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1725 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1726 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1727 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1728 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1729 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1730
1731 bu32 *pval = get_allreg (0, dst);
1732
1733 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1734 to combine them, so it prints out the right values.
1735 Here we keep track of the registers. */
1736 if (op == 0)
1737 {
1738 *pval = imm7_val (src);
1739 if (src & 0x40)
1740 *pval |= 0xFFFFFF80;
1741 else
1742 *pval &= 0x7F;
1743 }
1744
1745 if (op == 0)
1746 {
1747 OUTS (outf, dregs (dst));
1748 OUTS (outf, " = ");
1749 OUTS (outf, imm7 (src));
1750 OUTS (outf, " (X);\t\t/*\t\t");
1751 OUTS (outf, dregs (dst));
1752 OUTS (outf, "=");
1753 OUTS (outf, uimm32 (*pval));
1754 OUTS (outf, "(");
1755 OUTS (outf, imm32 (*pval));
1756 OUTS (outf, ") */");
1757 comment = 1;
1758 }
1759 else if (op == 1)
1760 {
1761 OUTS (outf, dregs (dst));
1762 OUTS (outf, " += ");
1763 OUTS (outf, imm7 (src));
1764 OUTS (outf, ";\t\t/* (");
1765 OUTS (outf, imm7d (src));
1766 OUTS (outf, ") */");
1767 comment = 1;
1768 }
1769 else
1770 return 0;
1771
1772 return 2;
1773 }
1774
1775 static int
1776 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1777 {
1778 /* COMPI2opP
1779 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1780 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1781 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1782 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1783 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1784 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1785
1786 bu32 *pval = get_allreg (1, dst);
1787
1788 if (op == 0)
1789 {
1790 *pval = imm7_val (src);
1791 if (src & 0x40)
1792 *pval |= 0xFFFFFF80;
1793 else
1794 *pval &= 0x7F;
1795 }
1796
1797 if (op == 0)
1798 {
1799 OUTS (outf, pregs (dst));
1800 OUTS (outf, " = ");
1801 OUTS (outf, imm7 (src));
1802 OUTS (outf, " (X);\t\t/*\t\t");
1803 OUTS (outf, pregs (dst));
1804 OUTS (outf, "=");
1805 OUTS (outf, uimm32 (*pval));
1806 OUTS (outf, "(");
1807 OUTS (outf, imm32 (*pval));
1808 OUTS (outf, ") */");
1809 comment = 1;
1810 }
1811 else if (op == 1)
1812 {
1813 OUTS (outf, pregs (dst));
1814 OUTS (outf, " += ");
1815 OUTS (outf, imm7 (src));
1816 OUTS (outf, ";\t\t/* (");
1817 OUTS (outf, imm7d (src));
1818 OUTS (outf, ") */");
1819 comment = 1;
1820 }
1821 else
1822 return 0;
1823
1824 return 2;
1825 }
1826
1827 static int
1828 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1829 {
1830 /* LDSTpmod
1831 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1832 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1833 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1834 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1835 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1836 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1837 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1838 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1839
1840 if (aop == 1 && W == 0 && idx == ptr)
1841 {
1842 OUTS (outf, dregs_lo (reg));
1843 OUTS (outf, " = W[");
1844 OUTS (outf, pregs (ptr));
1845 OUTS (outf, "]");
1846 }
1847 else if (aop == 2 && W == 0 && idx == ptr)
1848 {
1849 OUTS (outf, dregs_hi (reg));
1850 OUTS (outf, " = W[");
1851 OUTS (outf, pregs (ptr));
1852 OUTS (outf, "]");
1853 }
1854 else if (aop == 1 && W == 1 && idx == ptr)
1855 {
1856 OUTS (outf, "W[");
1857 OUTS (outf, pregs (ptr));
1858 OUTS (outf, "] = ");
1859 OUTS (outf, dregs_lo (reg));
1860 }
1861 else if (aop == 2 && W == 1 && idx == ptr)
1862 {
1863 OUTS (outf, "W[");
1864 OUTS (outf, pregs (ptr));
1865 OUTS (outf, "] = ");
1866 OUTS (outf, dregs_hi (reg));
1867 }
1868 else if (aop == 0 && W == 0)
1869 {
1870 OUTS (outf, dregs (reg));
1871 OUTS (outf, " = [");
1872 OUTS (outf, pregs (ptr));
1873 OUTS (outf, " ++ ");
1874 OUTS (outf, pregs (idx));
1875 OUTS (outf, "]");
1876 }
1877 else if (aop == 1 && W == 0)
1878 {
1879 OUTS (outf, dregs_lo (reg));
1880 OUTS (outf, " = W[");
1881 OUTS (outf, pregs (ptr));
1882 OUTS (outf, " ++ ");
1883 OUTS (outf, pregs (idx));
1884 OUTS (outf, "]");
1885 }
1886 else if (aop == 2 && W == 0)
1887 {
1888 OUTS (outf, dregs_hi (reg));
1889 OUTS (outf, " = W[");
1890 OUTS (outf, pregs (ptr));
1891 OUTS (outf, " ++ ");
1892 OUTS (outf, pregs (idx));
1893 OUTS (outf, "]");
1894 }
1895 else if (aop == 3 && W == 0)
1896 {
1897 OUTS (outf, dregs (reg));
1898 OUTS (outf, " = W[");
1899 OUTS (outf, pregs (ptr));
1900 OUTS (outf, " ++ ");
1901 OUTS (outf, pregs (idx));
1902 OUTS (outf, "] (Z)");
1903 }
1904 else if (aop == 3 && W == 1)
1905 {
1906 OUTS (outf, dregs (reg));
1907 OUTS (outf, " = W[");
1908 OUTS (outf, pregs (ptr));
1909 OUTS (outf, " ++ ");
1910 OUTS (outf, pregs (idx));
1911 OUTS (outf, "] (X)");
1912 }
1913 else if (aop == 0 && W == 1)
1914 {
1915 OUTS (outf, "[");
1916 OUTS (outf, pregs (ptr));
1917 OUTS (outf, " ++ ");
1918 OUTS (outf, pregs (idx));
1919 OUTS (outf, "] = ");
1920 OUTS (outf, dregs (reg));
1921 }
1922 else if (aop == 1 && W == 1)
1923 {
1924 OUTS (outf, "W[");
1925 OUTS (outf, pregs (ptr));
1926 OUTS (outf, " ++ ");
1927 OUTS (outf, pregs (idx));
1928 OUTS (outf, "] = ");
1929 OUTS (outf, dregs_lo (reg));
1930 }
1931 else if (aop == 2 && W == 1)
1932 {
1933 OUTS (outf, "W[");
1934 OUTS (outf, pregs (ptr));
1935 OUTS (outf, " ++ ");
1936 OUTS (outf, pregs (idx));
1937 OUTS (outf, "] = ");
1938 OUTS (outf, dregs_hi (reg));
1939 }
1940 else
1941 return 0;
1942
1943 return 2;
1944 }
1945
1946 static int
1947 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
1948 {
1949 /* dagMODim
1950 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1951 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1952 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1953 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
1954 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
1955 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
1956 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
1957
1958 if (op == 0 && br == 1)
1959 {
1960 OUTS (outf, iregs (i));
1961 OUTS (outf, " += ");
1962 OUTS (outf, mregs (m));
1963 OUTS (outf, " (BREV)");
1964 }
1965 else if (op == 0)
1966 {
1967 OUTS (outf, iregs (i));
1968 OUTS (outf, " += ");
1969 OUTS (outf, mregs (m));
1970 }
1971 else if (op == 1)
1972 {
1973 OUTS (outf, iregs (i));
1974 OUTS (outf, " -= ");
1975 OUTS (outf, mregs (m));
1976 }
1977 else
1978 return 0;
1979
1980 return 2;
1981 }
1982
1983 static int
1984 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
1985 {
1986 /* dagMODik
1987 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1988 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1989 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1990 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
1991 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
1992
1993 if (op == 0)
1994 {
1995 OUTS (outf, iregs (i));
1996 OUTS (outf, " += 0x2");
1997 }
1998 else if (op == 1)
1999 {
2000 OUTS (outf, iregs (i));
2001 OUTS (outf, " -= 0x2");
2002 }
2003 else if (op == 2)
2004 {
2005 OUTS (outf, iregs (i));
2006 OUTS (outf, " += 0x4");
2007 }
2008 else if (op == 3)
2009 {
2010 OUTS (outf, iregs (i));
2011 OUTS (outf, " -= 0x4");
2012 }
2013 else
2014 return 0;
2015
2016 if (! parallel )
2017 {
2018 OUTS (outf, ";\t\t/* ( ");
2019 if (op == 0 || op == 1)
2020 OUTS (outf, "2");
2021 else if (op == 2 || op == 3)
2022 OUTS (outf, "4");
2023 OUTS (outf, ") */");
2024 comment = 1;
2025 }
2026
2027 return 2;
2028 }
2029
2030 static int
2031 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2032 {
2033 /* dspLDST
2034 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2035 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2036 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2037 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2038 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2039 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2040 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2041 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2042
2043 if (aop == 0 && W == 0 && m == 0)
2044 {
2045 OUTS (outf, dregs (reg));
2046 OUTS (outf, " = [");
2047 OUTS (outf, iregs (i));
2048 OUTS (outf, "++]");
2049 }
2050 else if (aop == 0 && W == 0 && m == 1)
2051 {
2052 OUTS (outf, dregs_lo (reg));
2053 OUTS (outf, " = W[");
2054 OUTS (outf, iregs (i));
2055 OUTS (outf, "++]");
2056 }
2057 else if (aop == 0 && W == 0 && m == 2)
2058 {
2059 OUTS (outf, dregs_hi (reg));
2060 OUTS (outf, " = W[");
2061 OUTS (outf, iregs (i));
2062 OUTS (outf, "++]");
2063 }
2064 else if (aop == 1 && W == 0 && m == 0)
2065 {
2066 OUTS (outf, dregs (reg));
2067 OUTS (outf, " = [");
2068 OUTS (outf, iregs (i));
2069 OUTS (outf, "--]");
2070 }
2071 else if (aop == 1 && W == 0 && m == 1)
2072 {
2073 OUTS (outf, dregs_lo (reg));
2074 OUTS (outf, " = W[");
2075 OUTS (outf, iregs (i));
2076 OUTS (outf, "--]");
2077 }
2078 else if (aop == 1 && W == 0 && m == 2)
2079 {
2080 OUTS (outf, dregs_hi (reg));
2081 OUTS (outf, " = W[");
2082 OUTS (outf, iregs (i));
2083 OUTS (outf, "--]");
2084 }
2085 else if (aop == 2 && W == 0 && m == 0)
2086 {
2087 OUTS (outf, dregs (reg));
2088 OUTS (outf, " = [");
2089 OUTS (outf, iregs (i));
2090 OUTS (outf, "]");
2091 }
2092 else if (aop == 2 && W == 0 && m == 1)
2093 {
2094 OUTS (outf, dregs_lo (reg));
2095 OUTS (outf, " = W[");
2096 OUTS (outf, iregs (i));
2097 OUTS (outf, "]");
2098 }
2099 else if (aop == 2 && W == 0 && m == 2)
2100 {
2101 OUTS (outf, dregs_hi (reg));
2102 OUTS (outf, " = W[");
2103 OUTS (outf, iregs (i));
2104 OUTS (outf, "]");
2105 }
2106 else if (aop == 0 && W == 1 && m == 0)
2107 {
2108 OUTS (outf, "[");
2109 OUTS (outf, iregs (i));
2110 OUTS (outf, "++] = ");
2111 OUTS (outf, dregs (reg));
2112 }
2113 else if (aop == 0 && W == 1 && m == 1)
2114 {
2115 OUTS (outf, "W[");
2116 OUTS (outf, iregs (i));
2117 OUTS (outf, "++] = ");
2118 OUTS (outf, dregs_lo (reg));
2119 }
2120 else if (aop == 0 && W == 1 && m == 2)
2121 {
2122 OUTS (outf, "W[");
2123 OUTS (outf, iregs (i));
2124 OUTS (outf, "++] = ");
2125 OUTS (outf, dregs_hi (reg));
2126 }
2127 else if (aop == 1 && W == 1 && m == 0)
2128 {
2129 OUTS (outf, "[");
2130 OUTS (outf, iregs (i));
2131 OUTS (outf, "--] = ");
2132 OUTS (outf, dregs (reg));
2133 }
2134 else if (aop == 1 && W == 1 && m == 1)
2135 {
2136 OUTS (outf, "W[");
2137 OUTS (outf, iregs (i));
2138 OUTS (outf, "--] = ");
2139 OUTS (outf, dregs_lo (reg));
2140 }
2141 else if (aop == 1 && W == 1 && m == 2)
2142 {
2143 OUTS (outf, "W[");
2144 OUTS (outf, iregs (i));
2145 OUTS (outf, "--] = ");
2146 OUTS (outf, dregs_hi (reg));
2147 }
2148 else if (aop == 2 && W == 1 && m == 0)
2149 {
2150 OUTS (outf, "[");
2151 OUTS (outf, iregs (i));
2152 OUTS (outf, "] = ");
2153 OUTS (outf, dregs (reg));
2154 }
2155 else if (aop == 2 && W == 1 && m == 1)
2156 {
2157 OUTS (outf, "W[");
2158 OUTS (outf, iregs (i));
2159 OUTS (outf, "] = ");
2160 OUTS (outf, dregs_lo (reg));
2161 }
2162 else if (aop == 2 && W == 1 && m == 2)
2163 {
2164 OUTS (outf, "W[");
2165 OUTS (outf, iregs (i));
2166 OUTS (outf, "] = ");
2167 OUTS (outf, dregs_hi (reg));
2168 }
2169 else if (aop == 3 && W == 0)
2170 {
2171 OUTS (outf, dregs (reg));
2172 OUTS (outf, " = [");
2173 OUTS (outf, iregs (i));
2174 OUTS (outf, " ++ ");
2175 OUTS (outf, mregs (m));
2176 OUTS (outf, "]");
2177 }
2178 else if (aop == 3 && W == 1)
2179 {
2180 OUTS (outf, "[");
2181 OUTS (outf, iregs (i));
2182 OUTS (outf, " ++ ");
2183 OUTS (outf, mregs (m));
2184 OUTS (outf, "] = ");
2185 OUTS (outf, dregs (reg));
2186 }
2187 else
2188 return 0;
2189
2190 return 2;
2191 }
2192
2193 static int
2194 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2195 {
2196 /* LDST
2197 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2198 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2199 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2200 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2201 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2202 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2203 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2204 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2205 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2206
2207 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2208 {
2209 OUTS (outf, dregs (reg));
2210 OUTS (outf, " = [");
2211 OUTS (outf, pregs (ptr));
2212 OUTS (outf, "++]");
2213 }
2214 else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
2215 {
2216 OUTS (outf, pregs (reg));
2217 OUTS (outf, " = [");
2218 OUTS (outf, pregs (ptr));
2219 OUTS (outf, "++]");
2220 }
2221 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2222 {
2223 OUTS (outf, dregs (reg));
2224 OUTS (outf, " = W[");
2225 OUTS (outf, pregs (ptr));
2226 OUTS (outf, "++] (Z)");
2227 }
2228 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2229 {
2230 OUTS (outf, dregs (reg));
2231 OUTS (outf, " = W[");
2232 OUTS (outf, pregs (ptr));
2233 OUTS (outf, "++] (X)");
2234 }
2235 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2236 {
2237 OUTS (outf, dregs (reg));
2238 OUTS (outf, " = B[");
2239 OUTS (outf, pregs (ptr));
2240 OUTS (outf, "++] (Z)");
2241 }
2242 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2243 {
2244 OUTS (outf, dregs (reg));
2245 OUTS (outf, " = B[");
2246 OUTS (outf, pregs (ptr));
2247 OUTS (outf, "++] (X)");
2248 }
2249 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2250 {
2251 OUTS (outf, dregs (reg));
2252 OUTS (outf, " = [");
2253 OUTS (outf, pregs (ptr));
2254 OUTS (outf, "--]");
2255 }
2256 else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
2257 {
2258 OUTS (outf, pregs (reg));
2259 OUTS (outf, " = [");
2260 OUTS (outf, pregs (ptr));
2261 OUTS (outf, "--]");
2262 }
2263 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2264 {
2265 OUTS (outf, dregs (reg));
2266 OUTS (outf, " = W[");
2267 OUTS (outf, pregs (ptr));
2268 OUTS (outf, "--] (Z)");
2269 }
2270 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2271 {
2272 OUTS (outf, dregs (reg));
2273 OUTS (outf, " = W[");
2274 OUTS (outf, pregs (ptr));
2275 OUTS (outf, "--] (X)");
2276 }
2277 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2278 {
2279 OUTS (outf, dregs (reg));
2280 OUTS (outf, " = B[");
2281 OUTS (outf, pregs (ptr));
2282 OUTS (outf, "--] (Z)");
2283 }
2284 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2285 {
2286 OUTS (outf, dregs (reg));
2287 OUTS (outf, " = B[");
2288 OUTS (outf, pregs (ptr));
2289 OUTS (outf, "--] (X)");
2290 }
2291 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2292 {
2293 OUTS (outf, dregs (reg));
2294 OUTS (outf, " = [");
2295 OUTS (outf, pregs (ptr));
2296 OUTS (outf, "]");
2297 }
2298 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2299 {
2300 OUTS (outf, pregs (reg));
2301 OUTS (outf, " = [");
2302 OUTS (outf, pregs (ptr));
2303 OUTS (outf, "]");
2304 }
2305 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2306 {
2307 OUTS (outf, dregs (reg));
2308 OUTS (outf, " = W[");
2309 OUTS (outf, pregs (ptr));
2310 OUTS (outf, "] (Z)");
2311 }
2312 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2313 {
2314 OUTS (outf, dregs (reg));
2315 OUTS (outf, " = W[");
2316 OUTS (outf, pregs (ptr));
2317 OUTS (outf, "] (X)");
2318 }
2319 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2320 {
2321 OUTS (outf, dregs (reg));
2322 OUTS (outf, " = B[");
2323 OUTS (outf, pregs (ptr));
2324 OUTS (outf, "] (Z)");
2325 }
2326 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2327 {
2328 OUTS (outf, dregs (reg));
2329 OUTS (outf, " = B[");
2330 OUTS (outf, pregs (ptr));
2331 OUTS (outf, "] (X)");
2332 }
2333 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2334 {
2335 OUTS (outf, "[");
2336 OUTS (outf, pregs (ptr));
2337 OUTS (outf, "++] = ");
2338 OUTS (outf, dregs (reg));
2339 }
2340 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2341 {
2342 OUTS (outf, "[");
2343 OUTS (outf, pregs (ptr));
2344 OUTS (outf, "++] = ");
2345 OUTS (outf, pregs (reg));
2346 }
2347 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2348 {
2349 OUTS (outf, "W[");
2350 OUTS (outf, pregs (ptr));
2351 OUTS (outf, "++] = ");
2352 OUTS (outf, dregs (reg));
2353 }
2354 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2355 {
2356 OUTS (outf, "B[");
2357 OUTS (outf, pregs (ptr));
2358 OUTS (outf, "++] = ");
2359 OUTS (outf, dregs (reg));
2360 }
2361 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2362 {
2363 OUTS (outf, "[");
2364 OUTS (outf, pregs (ptr));
2365 OUTS (outf, "--] = ");
2366 OUTS (outf, dregs (reg));
2367 }
2368 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2369 {
2370 OUTS (outf, "[");
2371 OUTS (outf, pregs (ptr));
2372 OUTS (outf, "--] = ");
2373 OUTS (outf, pregs (reg));
2374 }
2375 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2376 {
2377 OUTS (outf, "W[");
2378 OUTS (outf, pregs (ptr));
2379 OUTS (outf, "--] = ");
2380 OUTS (outf, dregs (reg));
2381 }
2382 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2383 {
2384 OUTS (outf, "B[");
2385 OUTS (outf, pregs (ptr));
2386 OUTS (outf, "--] = ");
2387 OUTS (outf, dregs (reg));
2388 }
2389 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2390 {
2391 OUTS (outf, "[");
2392 OUTS (outf, pregs (ptr));
2393 OUTS (outf, "] = ");
2394 OUTS (outf, dregs (reg));
2395 }
2396 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2397 {
2398 OUTS (outf, "[");
2399 OUTS (outf, pregs (ptr));
2400 OUTS (outf, "] = ");
2401 OUTS (outf, pregs (reg));
2402 }
2403 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2404 {
2405 OUTS (outf, "W[");
2406 OUTS (outf, pregs (ptr));
2407 OUTS (outf, "] = ");
2408 OUTS (outf, dregs (reg));
2409 }
2410 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2411 {
2412 OUTS (outf, "B[");
2413 OUTS (outf, pregs (ptr));
2414 OUTS (outf, "] = ");
2415 OUTS (outf, dregs (reg));
2416 }
2417 else
2418 return 0;
2419
2420 return 2;
2421 }
2422
2423 static int
2424 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2425 {
2426 /* LDSTiiFP
2427 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2428 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2429 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2430 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2431 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2432 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2433
2434 if (W == 0)
2435 {
2436 OUTS (outf, dpregs (reg));
2437 OUTS (outf, " = [FP ");
2438 OUTS (outf, negimm5s4 (offset));
2439 OUTS (outf, "]");
2440 }
2441 else if (W == 1)
2442 {
2443 OUTS (outf, "[FP ");
2444 OUTS (outf, negimm5s4 (offset));
2445 OUTS (outf, "] = ");
2446 OUTS (outf, dpregs (reg));
2447 }
2448 else
2449 return 0;
2450
2451 return 2;
2452 }
2453
2454 static int
2455 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2456 {
2457 /* LDSTii
2458 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2459 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2460 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2461 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2462 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2463 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2464 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2465 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2466
2467 if (W == 0 && op == 0)
2468 {
2469 OUTS (outf, dregs (reg));
2470 OUTS (outf, " = [");
2471 OUTS (outf, pregs (ptr));
2472 OUTS (outf, " + ");
2473 OUTS (outf, uimm4s4 (offset));
2474 OUTS (outf, "]");
2475 }
2476 else if (W == 0 && op == 1)
2477 {
2478 OUTS (outf, dregs (reg));
2479 OUTS (outf, " = W[");
2480 OUTS (outf, pregs (ptr));
2481 OUTS (outf, " + ");
2482 OUTS (outf, uimm4s2 (offset));
2483 OUTS (outf, "] (Z)");
2484 }
2485 else if (W == 0 && op == 2)
2486 {
2487 OUTS (outf, dregs (reg));
2488 OUTS (outf, " = W[");
2489 OUTS (outf, pregs (ptr));
2490 OUTS (outf, " + ");
2491 OUTS (outf, uimm4s2 (offset));
2492 OUTS (outf, "] (X)");
2493 }
2494 else if (W == 0 && op == 3)
2495 {
2496 OUTS (outf, pregs (reg));
2497 OUTS (outf, " = [");
2498 OUTS (outf, pregs (ptr));
2499 OUTS (outf, " + ");
2500 OUTS (outf, uimm4s4 (offset));
2501 OUTS (outf, "]");
2502 }
2503 else if (W == 1 && op == 0)
2504 {
2505 OUTS (outf, "[");
2506 OUTS (outf, pregs (ptr));
2507 OUTS (outf, " + ");
2508 OUTS (outf, uimm4s4 (offset));
2509 OUTS (outf, "] = ");
2510 OUTS (outf, dregs (reg));
2511 }
2512 else if (W == 1 && op == 1)
2513 {
2514 OUTS (outf, "W[");
2515 OUTS (outf, pregs (ptr));
2516 OUTS (outf, " + ");
2517 OUTS (outf, uimm4s2 (offset));
2518 OUTS (outf, "] = ");
2519 OUTS (outf, dregs (reg));
2520 }
2521 else if (W == 1 && op == 3)
2522 {
2523 OUTS (outf, "[");
2524 OUTS (outf, pregs (ptr));
2525 OUTS (outf, " + ");
2526 OUTS (outf, uimm4s4 (offset));
2527 OUTS (outf, "] = ");
2528 OUTS (outf, pregs (reg));
2529 }
2530 else
2531 return 0;
2532
2533 return 2;
2534 }
2535
2536 static int
2537 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2538 {
2539 /* LoopSetup
2540 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2541 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2542 |.reg...........| - | - |.eoffset...............................|
2543 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2544 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2545 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2546 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2547 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2548 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2549
2550 if (rop == 0)
2551 {
2552 OUTS (outf, "LSETUP");
2553 OUTS (outf, "(0x");
2554 OUTS (outf, pcrel4 (soffset));
2555 OUTS (outf, ", 0x");
2556 OUTS (outf, lppcrel10 (eoffset));
2557 OUTS (outf, ") ");
2558 OUTS (outf, counters (c));
2559 }
2560 else if (rop == 1)
2561 {
2562 OUTS (outf, "LSETUP");
2563 OUTS (outf, "(0x");
2564 OUTS (outf, pcrel4 (soffset));
2565 OUTS (outf, ", 0x");
2566 OUTS (outf, lppcrel10 (eoffset));
2567 OUTS (outf, ") ");
2568 OUTS (outf, counters (c));
2569 OUTS (outf, " = ");
2570 OUTS (outf, pregs (reg));
2571 }
2572 else if (rop == 3)
2573 {
2574 OUTS (outf, "LSETUP");
2575 OUTS (outf, "(0x");
2576 OUTS (outf, pcrel4 (soffset));
2577 OUTS (outf, ", 0x");
2578 OUTS (outf, lppcrel10 (eoffset));
2579 OUTS (outf, ") ");
2580 OUTS (outf, counters (c));
2581 OUTS (outf, " = ");
2582 OUTS (outf, pregs (reg));
2583 OUTS (outf, " >> 0x1");
2584 }
2585 else
2586 return 0;
2587
2588 return 4;
2589 }
2590
2591 static int
2592 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2593 {
2594 /* LDIMMhalf
2595 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2596 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2597 |.hword.........................................................|
2598 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2599 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2600 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2601 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2602 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2603 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2604 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2605
2606 bu32 *pval = get_allreg (grp, reg);
2607
2608 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2609 to combine them, so it prints out the right values.
2610 Here we keep track of the registers. */
2611 if (H == 0 && S == 1 && Z == 0)
2612 {
2613 /* regs = imm16 (x) */
2614 *pval = imm16_val (hword);
2615 if (hword & 0x8000)
2616 *pval |= 0xFFFF0000;
2617 else
2618 *pval &= 0xFFFF;
2619 }
2620 else if (H == 0 && S == 0 && Z == 1)
2621 {
2622 /* regs = luimm16 (Z) */
2623 *pval = luimm16_val (hword);
2624 *pval &= 0xFFFF;
2625 }
2626 else if (H == 0 && S == 0 && Z == 0)
2627 {
2628 /* regs_lo = luimm16 */
2629 *pval &= 0xFFFF0000;
2630 *pval |= luimm16_val (hword);
2631 }
2632 else if (H == 1 && S == 0 && Z == 0)
2633 {
2634 /* regs_hi = huimm16 */
2635 *pval &= 0xFFFF;
2636 *pval |= luimm16_val (hword) << 16;
2637 }
2638
2639 /* Here we do the disassembly */
2640 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2641 {
2642 OUTS (outf, dregs_lo (reg));
2643 OUTS (outf, " = ");
2644 OUTS (outf, uimm16 (hword));
2645 }
2646 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2647 {
2648 OUTS (outf, dregs_hi (reg));
2649 OUTS (outf, " = ");
2650 OUTS (outf, uimm16 (hword));
2651 }
2652 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2653 {
2654 OUTS (outf, dregs (reg));
2655 OUTS (outf, " = ");
2656 OUTS (outf, imm16 (hword));
2657 OUTS (outf, " (X)");
2658 }
2659 else if (H == 0 && S == 1 && Z == 0)
2660 {
2661 OUTS (outf, regs (reg, grp));
2662 OUTS (outf, " = ");
2663 OUTS (outf, imm16 (hword));
2664 OUTS (outf, " (X)");
2665 }
2666 else if (H == 0 && S == 0 && Z == 1)
2667 {
2668 OUTS (outf, regs (reg, grp));
2669 OUTS (outf, " = ");
2670 OUTS (outf, uimm16 (hword));
2671 OUTS (outf, " (Z)");
2672 }
2673 else if (H == 0 && S == 0 && Z == 0)
2674 {
2675 OUTS (outf, regs_lo (reg, grp));
2676 OUTS (outf, " = ");
2677 OUTS (outf, uimm16 (hword));
2678 }
2679 else if (H == 1 && S == 0 && Z == 0)
2680 {
2681 OUTS (outf, regs_hi (reg, grp));
2682 OUTS (outf, " = ");
2683 OUTS (outf, uimm16 (hword));
2684 }
2685 else
2686 return 0;
2687
2688 /* And we print out the 32-bit value if it is a pointer. */
2689 if (S == 0 && Z == 0)
2690 {
2691 OUTS (outf, ";\t\t/* (");
2692 OUTS (outf, imm16d (hword));
2693 OUTS (outf, ")\t");
2694
2695 /* If it is an MMR, don't print the symbol. */
2696 if (*pval < 0xFFC00000 && grp == 1)
2697 {
2698 OUTS (outf, regs (reg, grp));
2699 OUTS (outf, "=0x");
2700 OUTS (outf, huimm32e (*pval));
2701 }
2702 else
2703 {
2704 OUTS (outf, regs (reg, grp));
2705 OUTS (outf, "=0x");
2706 OUTS (outf, huimm32e (*pval));
2707 OUTS (outf, "(");
2708 OUTS (outf, imm32 (*pval));
2709 OUTS (outf, ")");
2710 }
2711
2712 OUTS (outf, " */");
2713 comment = 1;
2714 }
2715 if (S == 1 || Z == 1)
2716 {
2717 OUTS (outf, ";\t\t/*\t\t");
2718 OUTS (outf, regs (reg, grp));
2719 OUTS (outf, "=0x");
2720 OUTS (outf, huimm32e (*pval));
2721 OUTS (outf, "(");
2722 OUTS (outf, imm32 (*pval));
2723 OUTS (outf, ") */");
2724 comment = 1;
2725 }
2726 return 4;
2727 }
2728
2729 static int
2730 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2731 {
2732 /* CALLa
2733 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2734 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2735 |.lsw...........................................................|
2736 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2737 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2738 int lsw = ((iw1 >> 0) & 0xffff);
2739 int msw = ((iw0 >> 0) & 0xff);
2740
2741 if (S == 1)
2742 OUTS (outf, "CALL 0x");
2743 else if (S == 0)
2744 OUTS (outf, "JUMP.L 0x");
2745 else
2746 return 0;
2747
2748 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2749 return 4;
2750 }
2751
2752 static int
2753 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2754 {
2755 /* LDSTidxI
2756 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2757 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2758 |.offset........................................................|
2759 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2760 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2761 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2762 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2763 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2764 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2765 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2766
2767 if (W == 0 && sz == 0 && Z == 0)
2768 {
2769 OUTS (outf, dregs (reg));
2770 OUTS (outf, " = [");
2771 OUTS (outf, pregs (ptr));
2772 OUTS (outf, " + ");
2773 OUTS (outf, imm16s4 (offset));
2774 OUTS (outf, "]");
2775 }
2776 else if (W == 0 && sz == 0 && Z == 1)
2777 {
2778 OUTS (outf, pregs (reg));
2779 OUTS (outf, " = [");
2780 OUTS (outf, pregs (ptr));
2781 OUTS (outf, " + ");
2782 OUTS (outf, imm16s4 (offset));
2783 OUTS (outf, "]");
2784 }
2785 else if (W == 0 && sz == 1 && Z == 0)
2786 {
2787 OUTS (outf, dregs (reg));
2788 OUTS (outf, " = W[");
2789 OUTS (outf, pregs (ptr));
2790 OUTS (outf, " + ");
2791 OUTS (outf, imm16s2 (offset));
2792 OUTS (outf, "] (Z)");
2793 }
2794 else if (W == 0 && sz == 1 && Z == 1)
2795 {
2796 OUTS (outf, dregs (reg));
2797 OUTS (outf, " = W[");
2798 OUTS (outf, pregs (ptr));
2799 OUTS (outf, " + ");
2800 OUTS (outf, imm16s2 (offset));
2801 OUTS (outf, "] (X)");
2802 }
2803 else if (W == 0 && sz == 2 && Z == 0)
2804 {
2805 OUTS (outf, dregs (reg));
2806 OUTS (outf, " = B[");
2807 OUTS (outf, pregs (ptr));
2808 OUTS (outf, " + ");
2809 OUTS (outf, imm16 (offset));
2810 OUTS (outf, "] (Z)");
2811 }
2812 else if (W == 0 && sz == 2 && Z == 1)
2813 {
2814 OUTS (outf, dregs (reg));
2815 OUTS (outf, " = B[");
2816 OUTS (outf, pregs (ptr));
2817 OUTS (outf, " + ");
2818 OUTS (outf, imm16 (offset));
2819 OUTS (outf, "] (X)");
2820 }
2821 else if (W == 1 && sz == 0 && Z == 0)
2822 {
2823 OUTS (outf, "[");
2824 OUTS (outf, pregs (ptr));
2825 OUTS (outf, " + ");
2826 OUTS (outf, imm16s4 (offset));
2827 OUTS (outf, "] = ");
2828 OUTS (outf, dregs (reg));
2829 }
2830 else if (W == 1 && sz == 0 && Z == 1)
2831 {
2832 OUTS (outf, "[");
2833 OUTS (outf, pregs (ptr));
2834 OUTS (outf, " + ");
2835 OUTS (outf, imm16s4 (offset));
2836 OUTS (outf, "] = ");
2837 OUTS (outf, pregs (reg));
2838 }
2839 else if (W == 1 && sz == 1 && Z == 0)
2840 {
2841 OUTS (outf, "W[");
2842 OUTS (outf, pregs (ptr));
2843 OUTS (outf, " + ");
2844 OUTS (outf, imm16s2 (offset));
2845 OUTS (outf, "] = ");
2846 OUTS (outf, dregs (reg));
2847 }
2848 else if (W == 1 && sz == 2 && Z == 0)
2849 {
2850 OUTS (outf, "B[");
2851 OUTS (outf, pregs (ptr));
2852 OUTS (outf, " + ");
2853 OUTS (outf, imm16 (offset));
2854 OUTS (outf, "] = ");
2855 OUTS (outf, dregs (reg));
2856 }
2857 else
2858 return 0;
2859
2860 return 4;
2861 }
2862
2863 static int
2864 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2865 {
2866 /* linkage
2867 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2868 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2869 |.framesize.....................................................|
2870 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2871 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2872 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2873
2874 if (R == 0)
2875 {
2876 OUTS (outf, "LINK ");
2877 OUTS (outf, uimm16s4 (framesize));
2878 OUTS (outf, ";\t\t/* (");
2879 OUTS (outf, uimm16s4d (framesize));
2880 OUTS (outf, ") */");
2881 comment = 1;
2882 }
2883 else if (R == 1)
2884 OUTS (outf, "UNLINK");
2885 else
2886 return 0;
2887
2888 return 4;
2889 }
2890
2891 static int
2892 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2893 {
2894 /* dsp32mac
2895 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2896 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2897 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2898 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2899 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2900 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2901 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2902 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2903 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2904 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2905 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2906 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2907 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2908 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2909 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2910 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2911 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2912 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2913
2914 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2915 return 0;
2916
2917 if (op1 == 3 && MM)
2918 return 0;
2919
2920 if ((w1 || w0) && mmod == M_W32)
2921 return 0;
2922
2923 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2924 return 0;
2925
2926 if (w1 == 1 || op1 != 3)
2927 {
2928 if (w1)
2929 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
2930
2931 if (op1 == 3)
2932 OUTS (outf, " = A1");
2933 else
2934 {
2935 if (w1)
2936 OUTS (outf, " = (");
2937 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
2938 if (w1)
2939 OUTS (outf, ")");
2940 }
2941
2942 if (w0 == 1 || op0 != 3)
2943 {
2944 if (MM)
2945 OUTS (outf, " (M)");
2946 MM = 0;
2947 OUTS (outf, ", ");
2948 }
2949 }
2950
2951 if (w0 == 1 || op0 != 3)
2952 {
2953 if (w0)
2954 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
2955
2956 if (op0 == 3)
2957 OUTS (outf, " = A0");
2958 else
2959 {
2960 if (w0)
2961 OUTS (outf, " = (");
2962 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
2963 if (w0)
2964 OUTS (outf, ")");
2965 }
2966 }
2967
2968 decode_optmode (mmod, MM, outf);
2969
2970 return 4;
2971 }
2972
2973 static int
2974 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2975 {
2976 /* dsp32mult
2977 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2978 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2979 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2980 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2981 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2982 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2983 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2984 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2985 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2986 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2987 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2988 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2989 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2990 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2991 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2992 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2993
2994 if (w1 == 0 && w0 == 0)
2995 return 0;
2996
2997 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
2998 return 0;
2999
3000 if (w1)
3001 {
3002 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3003 OUTS (outf, " = ");
3004 decode_multfunc (h01, h11, src0, src1, outf);
3005
3006 if (w0)
3007 {
3008 if (MM)
3009 OUTS (outf, " (M)");
3010 MM = 0;
3011 OUTS (outf, ", ");
3012 }
3013 }
3014
3015 if (w0)
3016 {
3017 OUTS (outf, dregs (dst));
3018 OUTS (outf, " = ");
3019 decode_multfunc (h00, h10, src0, src1, outf);
3020 }
3021
3022 decode_optmode (mmod, MM, outf);
3023 return 4;
3024 }
3025
3026 static int
3027 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3028 {
3029 /* dsp32alu
3030 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3031 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3032 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3033 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3034 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3035 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3036 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3037 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3038 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3039 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3040 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3041 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3042 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3043
3044 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3045 {
3046 OUTS (outf, "A0.L = ");
3047 OUTS (outf, dregs_lo (src0));
3048 }
3049 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3050 {
3051 OUTS (outf, "A1.H = ");
3052 OUTS (outf, dregs_hi (src0));
3053 }
3054 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3055 {
3056 OUTS (outf, "A1.L = ");
3057 OUTS (outf, dregs_lo (src0));
3058 }
3059 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3060 {
3061 OUTS (outf, "A0.H = ");
3062 OUTS (outf, dregs_hi (src0));
3063 }
3064 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3065 {
3066 OUTS (outf, dregs_hi (dst0));
3067 OUTS (outf, " = ");
3068 OUTS (outf, dregs (src0));
3069 OUTS (outf, " - ");
3070 OUTS (outf, dregs (src1));
3071 OUTS (outf, " (RND20)");
3072 }
3073 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3074 {
3075 OUTS (outf, dregs_hi (dst0));
3076 OUTS (outf, " = ");
3077 OUTS (outf, dregs (src0));
3078 OUTS (outf, " + ");
3079 OUTS (outf, dregs (src1));
3080 OUTS (outf, " (RND20)");
3081 }
3082 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3083 {
3084 OUTS (outf, dregs_lo (dst0));
3085 OUTS (outf, " = ");
3086 OUTS (outf, dregs (src0));
3087 OUTS (outf, " - ");
3088 OUTS (outf, dregs (src1));
3089 OUTS (outf, " (RND12)");
3090 }
3091 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3092 {
3093 OUTS (outf, dregs_lo (dst0));
3094 OUTS (outf, " = ");
3095 OUTS (outf, dregs (src0));
3096 OUTS (outf, " + ");
3097 OUTS (outf, dregs (src1));
3098 OUTS (outf, " (RND12)");
3099 }
3100 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3101 {
3102 OUTS (outf, dregs_lo (dst0));
3103 OUTS (outf, " = ");
3104 OUTS (outf, dregs (src0));
3105 OUTS (outf, " - ");
3106 OUTS (outf, dregs (src1));
3107 OUTS (outf, " (RND20)");
3108 }
3109 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3110 {
3111 OUTS (outf, dregs_hi (dst0));
3112 OUTS (outf, " = ");
3113 OUTS (outf, dregs (src0));
3114 OUTS (outf, " + ");
3115 OUTS (outf, dregs (src1));
3116 OUTS (outf, " (RND12)");
3117 }
3118 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3119 {
3120 OUTS (outf, dregs_lo (dst0));
3121 OUTS (outf, " = ");
3122 OUTS (outf, dregs (src0));
3123 OUTS (outf, " + ");
3124 OUTS (outf, dregs (src1));
3125 OUTS (outf, " (RND20)");
3126 }
3127 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3128 {
3129 OUTS (outf, dregs_hi (dst0));
3130 OUTS (outf, " = ");
3131 OUTS (outf, dregs (src0));
3132 OUTS (outf, " - ");
3133 OUTS (outf, dregs (src1));
3134 OUTS (outf, " (RND12)");
3135 }
3136 else if (HL == 1 && aop == 0 && aopcde == 2)
3137 {
3138 OUTS (outf, dregs_hi (dst0));
3139 OUTS (outf, " = ");
3140 OUTS (outf, dregs_lo (src0));
3141 OUTS (outf, " + ");
3142 OUTS (outf, dregs_lo (src1));
3143 amod1 (s, x, outf);
3144 }
3145 else if (HL == 1 && aop == 1 && aopcde == 2)
3146 {
3147 OUTS (outf, dregs_hi (dst0));
3148 OUTS (outf, " = ");
3149 OUTS (outf, dregs_lo (src0));
3150 OUTS (outf, " + ");
3151 OUTS (outf, dregs_hi (src1));
3152 amod1 (s, x, outf);
3153 }
3154 else if (HL == 1 && aop == 2 && aopcde == 2)
3155 {
3156 OUTS (outf, dregs_hi (dst0));
3157 OUTS (outf, " = ");
3158 OUTS (outf, dregs_hi (src0));
3159 OUTS (outf, " + ");
3160 OUTS (outf, dregs_lo (src1));
3161 amod1 (s, x, outf);
3162 }
3163 else if (HL == 1 && aop == 3 && aopcde == 2)
3164 {
3165 OUTS (outf, dregs_hi (dst0));
3166 OUTS (outf, " = ");
3167 OUTS (outf, dregs_hi (src0));
3168 OUTS (outf, " + ");
3169 OUTS (outf, dregs_hi (src1));
3170 amod1 (s, x, outf);
3171 }
3172 else if (HL == 0 && aop == 0 && aopcde == 3)
3173 {
3174 OUTS (outf, dregs_lo (dst0));
3175 OUTS (outf, " = ");
3176 OUTS (outf, dregs_lo (src0));
3177 OUTS (outf, " - ");
3178 OUTS (outf, dregs_lo (src1));
3179 amod1 (s, x, outf);
3180 }
3181 else if (HL == 0 && aop == 1 && aopcde == 3)
3182 {
3183 OUTS (outf, dregs_lo (dst0));
3184 OUTS (outf, " = ");
3185 OUTS (outf, dregs_lo (src0));
3186 OUTS (outf, " - ");
3187 OUTS (outf, dregs_hi (src1));
3188 amod1 (s, x, outf);
3189 }
3190 else if (HL == 0 && aop == 3 && aopcde == 2)
3191 {
3192 OUTS (outf, dregs_lo (dst0));
3193 OUTS (outf, " = ");
3194 OUTS (outf, dregs_hi (src0));
3195 OUTS (outf, " + ");
3196 OUTS (outf, dregs_hi (src1));
3197 amod1 (s, x, outf);
3198 }
3199 else if (HL == 1 && aop == 0 && aopcde == 3)
3200 {
3201 OUTS (outf, dregs_hi (dst0));
3202 OUTS (outf, " = ");
3203 OUTS (outf, dregs_lo (src0));
3204 OUTS (outf, " - ");
3205 OUTS (outf, dregs_lo (src1));
3206 amod1 (s, x, outf);
3207 }
3208 else if (HL == 1 && aop == 1 && aopcde == 3)
3209 {
3210 OUTS (outf, dregs_hi (dst0));
3211 OUTS (outf, " = ");
3212 OUTS (outf, dregs_lo (src0));
3213 OUTS (outf, " - ");
3214 OUTS (outf, dregs_hi (src1));
3215 amod1 (s, x, outf);
3216 }
3217 else if (HL == 1 && aop == 2 && aopcde == 3)
3218 {
3219 OUTS (outf, dregs_hi (dst0));
3220 OUTS (outf, " = ");
3221 OUTS (outf, dregs_hi (src0));
3222 OUTS (outf, " - ");
3223 OUTS (outf, dregs_lo (src1));
3224 amod1 (s, x, outf);
3225 }
3226 else if (HL == 1 && aop == 3 && aopcde == 3)
3227 {
3228 OUTS (outf, dregs_hi (dst0));
3229 OUTS (outf, " = ");
3230 OUTS (outf, dregs_hi (src0));
3231 OUTS (outf, " - ");
3232 OUTS (outf, dregs_hi (src1));
3233 amod1 (s, x, outf);
3234 }
3235 else if (HL == 0 && aop == 2 && aopcde == 2)
3236 {
3237 OUTS (outf, dregs_lo (dst0));
3238 OUTS (outf, " = ");
3239 OUTS (outf, dregs_hi (src0));
3240 OUTS (outf, " + ");
3241 OUTS (outf, dregs_lo (src1));
3242 amod1 (s, x, outf);
3243 }
3244 else if (HL == 0 && aop == 1 && aopcde == 2)
3245 {
3246 OUTS (outf, dregs_lo (dst0));
3247 OUTS (outf, " = ");
3248 OUTS (outf, dregs_lo (src0));
3249 OUTS (outf, " + ");
3250 OUTS (outf, dregs_hi (src1));
3251 amod1 (s, x, outf);
3252 }
3253 else if (HL == 0 && aop == 2 && aopcde == 3)
3254 {
3255 OUTS (outf, dregs_lo (dst0));
3256 OUTS (outf, " = ");
3257 OUTS (outf, dregs_hi (src0));
3258 OUTS (outf, " - ");
3259 OUTS (outf, dregs_lo (src1));
3260 amod1 (s, x, outf);
3261 }
3262 else if (HL == 0 && aop == 3 && aopcde == 3)
3263 {
3264 OUTS (outf, dregs_lo (dst0));
3265 OUTS (outf, " = ");
3266 OUTS (outf, dregs_hi (src0));
3267 OUTS (outf, " - ");
3268 OUTS (outf, dregs_hi (src1));
3269 amod1 (s, x, outf);
3270 }
3271 else if (HL == 0 && aop == 0 && aopcde == 2)
3272 {
3273 OUTS (outf, dregs_lo (dst0));
3274 OUTS (outf, " = ");
3275 OUTS (outf, dregs_lo (src0));
3276 OUTS (outf, " + ");
3277 OUTS (outf, dregs_lo (src1));
3278 amod1 (s, x, outf);
3279 }
3280 else if (aop == 0 && aopcde == 9 && s == 1)
3281 {
3282 OUTS (outf, "A0 = ");
3283 OUTS (outf, dregs (src0));
3284 }
3285 else if (aop == 3 && aopcde == 11 && s == 0)
3286 OUTS (outf, "A0 -= A1");
3287
3288 else if (aop == 3 && aopcde == 11 && s == 1)
3289 OUTS (outf, "A0 -= A1 (W32)");
3290
3291 else if (aop == 3 && aopcde == 22 && HL == 1)
3292 {
3293 OUTS (outf, dregs (dst0));
3294 OUTS (outf, " = BYTEOP2M (");
3295 OUTS (outf, dregs (src0 + 1));
3296 OUTS (outf, ":");
3297 OUTS (outf, imm5 (src0));
3298 OUTS (outf, ", ");
3299 OUTS (outf, dregs (src1 + 1));
3300 OUTS (outf, ":");
3301 OUTS (outf, imm5 (src1));
3302 OUTS (outf, ") (TH");
3303 if (s == 1)
3304 OUTS (outf, ", R)");
3305 else
3306 OUTS (outf, ")");
3307 }
3308 else if (aop == 3 && aopcde == 22 && HL == 0)
3309 {
3310 OUTS (outf, dregs (dst0));
3311 OUTS (outf, " = BYTEOP2M (");
3312 OUTS (outf, dregs (src0 + 1));
3313 OUTS (outf, ":");
3314 OUTS (outf, imm5 (src0));
3315 OUTS (outf, ", ");
3316 OUTS (outf, dregs (src1 + 1));
3317 OUTS (outf, ":");
3318 OUTS (outf, imm5 (src1));
3319 OUTS (outf, ") (TL");
3320 if (s == 1)
3321 OUTS (outf, ", R)");
3322 else
3323 OUTS (outf, ")");
3324 }
3325 else if (aop == 2 && aopcde == 22 && HL == 1)
3326 {
3327 OUTS (outf, dregs (dst0));
3328 OUTS (outf, " = BYTEOP2M (");
3329 OUTS (outf, dregs (src0 + 1));
3330 OUTS (outf, ":");
3331 OUTS (outf, imm5 (src0));
3332 OUTS (outf, ", ");
3333 OUTS (outf, dregs (src1 + 1));
3334 OUTS (outf, ":");
3335 OUTS (outf, imm5 (src1));
3336 OUTS (outf, ") (RNDH");
3337 if (s == 1)
3338 OUTS (outf, ", R)");
3339 else
3340 OUTS (outf, ")");
3341 }
3342 else if (aop == 2 && aopcde == 22 && HL == 0)
3343 {
3344 OUTS (outf, dregs (dst0));
3345 OUTS (outf, " = BYTEOP2M (");
3346 OUTS (outf, dregs (src0 + 1));
3347 OUTS (outf, ":");
3348 OUTS (outf, imm5 (src0));
3349 OUTS (outf, ", ");
3350 OUTS (outf, dregs (src1 + 1));
3351 OUTS (outf, ":");
3352 OUTS (outf, imm5 (src1));
3353 OUTS (outf, ") (RNDL");
3354 if (s == 1)
3355 OUTS (outf, ", R)");
3356 else
3357 OUTS (outf, ")");
3358 }
3359 else if (aop == 1 && aopcde == 22 && HL == 1)
3360 {
3361 OUTS (outf, dregs (dst0));
3362 OUTS (outf, " = BYTEOP2P (");
3363 OUTS (outf, dregs (src0 + 1));
3364 OUTS (outf, ":");
3365 OUTS (outf, imm5d (src0));
3366 OUTS (outf, ", ");
3367 OUTS (outf, dregs (src1 + 1));
3368 OUTS (outf, ":");
3369 OUTS (outf, imm5d (src1));
3370 OUTS (outf, ") (TH");
3371 if (s == 1)
3372 OUTS (outf, ", R)");
3373 else
3374 OUTS (outf, ")");
3375 }
3376 else if (aop == 1 && aopcde == 22 && HL == 0)
3377 {
3378 OUTS (outf, dregs (dst0));
3379 OUTS (outf, " = BYTEOP2P (");
3380 OUTS (outf, dregs (src0 + 1));
3381 OUTS (outf, ":");
3382 OUTS (outf, imm5d (src0));
3383 OUTS (outf, ", ");
3384 OUTS (outf, dregs (src1 + 1));
3385 OUTS (outf, ":");
3386 OUTS (outf, imm5d (src1));
3387 OUTS (outf, ") (TL");
3388 if (s == 1)
3389 OUTS (outf, ", R)");
3390 else
3391 OUTS (outf, ")");
3392 }
3393 else if (aop == 0 && aopcde == 22 && HL == 1)
3394 {
3395 OUTS (outf, dregs (dst0));
3396 OUTS (outf, " = BYTEOP2P (");
3397 OUTS (outf, dregs (src0 + 1));
3398 OUTS (outf, ":");
3399 OUTS (outf, imm5d (src0));
3400 OUTS (outf, ", ");
3401 OUTS (outf, dregs (src1 + 1));
3402 OUTS (outf, ":");
3403 OUTS (outf, imm5d (src1));
3404 OUTS (outf, ") (RNDH");
3405 if (s == 1)
3406 OUTS (outf, ", R)");
3407 else
3408 OUTS (outf, ")");
3409 }
3410 else if (aop == 0 && aopcde == 22 && HL == 0)
3411 {
3412 OUTS (outf, dregs (dst0));
3413 OUTS (outf, " = BYTEOP2P (");
3414 OUTS (outf, dregs (src0 + 1));
3415 OUTS (outf, ":");
3416 OUTS (outf, imm5d (src0));
3417 OUTS (outf, ", ");
3418 OUTS (outf, dregs (src1 + 1));
3419 OUTS (outf, ":");
3420 OUTS (outf, imm5d (src1));
3421 OUTS (outf, ") (RNDL");
3422 if (s == 1)
3423 OUTS (outf, ", R)");
3424 else
3425 OUTS (outf, ")");
3426 }
3427 else if (aop == 0 && s == 0 && aopcde == 8)
3428 OUTS (outf, "A0 = 0");
3429
3430 else if (aop == 0 && s == 1 && aopcde == 8)
3431 OUTS (outf, "A0 = A0 (S)");
3432
3433 else if (aop == 1 && s == 0 && aopcde == 8)
3434 OUTS (outf, "A1 = 0");
3435
3436 else if (aop == 1 && s == 1 && aopcde == 8)
3437 OUTS (outf, "A1 = A1 (S)");
3438
3439 else if (aop == 2 && s == 0 && aopcde == 8)
3440 OUTS (outf, "A1 = A0 = 0");
3441
3442 else if (aop == 2 && s == 1 && aopcde == 8)
3443 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3444
3445 else if (aop == 3 && s == 0 && aopcde == 8)
3446 OUTS (outf, "A0 = A1");
3447
3448 else if (aop == 3 && s == 1 && aopcde == 8)
3449 OUTS (outf, "A1 = A0");
3450
3451 else if (aop == 1 && aopcde == 9 && s == 0)
3452 {
3453 OUTS (outf, "A0.X = ");
3454 OUTS (outf, dregs_lo (src0));
3455 }
3456 else if (aop == 1 && HL == 0 && aopcde == 11)
3457 {
3458 OUTS (outf, dregs_lo (dst0));
3459 OUTS (outf, " = (A0 += A1)");
3460 }
3461 else if (aop == 3 && HL == 0 && aopcde == 16)
3462 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3463
3464 else if (aop == 0 && aopcde == 23 && HL == 1)
3465 {
3466 OUTS (outf, dregs (dst0));
3467 OUTS (outf, " = BYTEOP3P (");
3468 OUTS (outf, dregs (src0 + 1));
3469 OUTS (outf, ":");
3470 OUTS (outf, imm5d (src0));
3471 OUTS (outf, ", ");
3472 OUTS (outf, dregs (src1 + 1));
3473 OUTS (outf, ":");
3474 OUTS (outf, imm5d (src1));
3475 OUTS (outf, ") (HI");
3476 if (s == 1)
3477 OUTS (outf, ", R)");
3478 else
3479 OUTS (outf, ")");
3480 }
3481 else if (aop == 3 && aopcde == 9 && s == 0)
3482 {
3483 OUTS (outf, "A1.X = ");
3484 OUTS (outf, dregs_lo (src0));
3485 }
3486 else if (aop == 1 && HL == 1 && aopcde == 16)
3487 OUTS (outf, "A1 = ABS A1");
3488
3489 else if (aop == 0 && HL == 1 && aopcde == 16)
3490 OUTS (outf, "A1 = ABS A0");
3491
3492 else if (aop == 2 && aopcde == 9 && s == 1)
3493 {
3494 OUTS (outf, "A1 = ");
3495 OUTS (outf, dregs (src0));
3496 }
3497 else if (HL == 0 && aop == 3 && aopcde == 12)
3498 {
3499 OUTS (outf, dregs_lo (dst0));
3500 OUTS (outf, " = ");
3501 OUTS (outf, dregs (src0));
3502 OUTS (outf, " (RND)");
3503 }
3504 else if (aop == 1 && HL == 0 && aopcde == 16)
3505 OUTS (outf, "A0 = ABS A1");
3506
3507 else if (aop == 0 && HL == 0 && aopcde == 16)
3508 OUTS (outf, "A0 = ABS A0");
3509
3510 else if (aop == 3 && HL == 0 && aopcde == 15)
3511 {
3512 OUTS (outf, dregs (dst0));
3513 OUTS (outf, " = -");
3514 OUTS (outf, dregs (src0));
3515 OUTS (outf, " (V)");
3516 }
3517 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3518 {
3519 OUTS (outf, dregs (dst0));
3520 OUTS (outf, " = -");
3521 OUTS (outf, dregs (src0));
3522 OUTS (outf, " (S)");
3523 }
3524 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3525 {
3526 OUTS (outf, dregs (dst0));
3527 OUTS (outf, " = -");
3528 OUTS (outf, dregs (src0));
3529 OUTS (outf, " (NS)");
3530 }
3531 else if (aop == 1 && HL == 1 && aopcde == 11)
3532 {
3533 OUTS (outf, dregs_hi (dst0));
3534 OUTS (outf, " = (A0 += A1)");
3535 }
3536 else if (aop == 2 && aopcde == 11 && s == 0)
3537 OUTS (outf, "A0 += A1");
3538
3539 else if (aop == 2 && aopcde == 11 && s == 1)
3540 OUTS (outf, "A0 += A1 (W32)");
3541
3542 else if (aop == 3 && HL == 0 && aopcde == 14)
3543 OUTS (outf, "A1 = -A1, A0 = -A0");
3544
3545 else if (HL == 1 && aop == 3 && aopcde == 12)
3546 {
3547 OUTS (outf, dregs_hi (dst0));
3548 OUTS (outf, " = ");
3549 OUTS (outf, dregs (src0));
3550 OUTS (outf, " (RND)");
3551 }
3552 else if (aop == 0 && aopcde == 23 && HL == 0)
3553 {
3554 OUTS (outf, dregs (dst0));
3555 OUTS (outf, " = BYTEOP3P (");
3556 OUTS (outf, dregs (src0 + 1));
3557 OUTS (outf, ":");
3558 OUTS (outf, imm5d (src0));
3559 OUTS (outf, ", ");
3560 OUTS (outf, dregs (src1 + 1));
3561 OUTS (outf, ":");
3562 OUTS (outf, imm5d (src1));
3563 OUTS (outf, ") (LO");
3564 if (s == 1)
3565 OUTS (outf, ", R)");
3566 else
3567 OUTS (outf, ")");
3568 }
3569 else if (aop == 0 && HL == 0 && aopcde == 14)
3570 OUTS (outf, "A0 = -A0");
3571
3572 else if (aop == 1 && HL == 0 && aopcde == 14)
3573 OUTS (outf, "A0 = -A1");
3574
3575 else if (aop == 0 && HL == 1 && aopcde == 14)
3576 OUTS (outf, "A1 = -A0");
3577
3578 else if (aop == 1 && HL == 1 && aopcde == 14)
3579 OUTS (outf, "A1 = -A1");
3580
3581 else if (aop == 0 && aopcde == 12)
3582 {
3583 OUTS (outf, dregs_hi (dst0));
3584 OUTS (outf, " = ");
3585 OUTS (outf, dregs_lo (dst0));
3586 OUTS (outf, " = SIGN (");
3587 OUTS (outf, dregs_hi (src0));
3588 OUTS (outf, ") * ");
3589 OUTS (outf, dregs_hi (src1));
3590 OUTS (outf, " + SIGN (");
3591 OUTS (outf, dregs_lo (src0));
3592 OUTS (outf, ") * ");
3593 OUTS (outf, dregs_lo (src1));
3594 }
3595 else if (aop == 2 && aopcde == 0)
3596 {
3597 OUTS (outf, dregs (dst0));
3598 OUTS (outf, " = ");
3599 OUTS (outf, dregs (src0));
3600 OUTS (outf, " -|+ ");
3601 OUTS (outf, dregs (src1));
3602 amod0 (s, x, outf);
3603 }
3604 else if (aop == 1 && aopcde == 12)
3605 {
3606 OUTS (outf, dregs (dst1));
3607 OUTS (outf, " = A1.L + A1.H, ");
3608 OUTS (outf, dregs (dst0));
3609 OUTS (outf, " = A0.L + A0.H");
3610 }
3611 else if (aop == 2 && aopcde == 4)
3612 {
3613 OUTS (outf, dregs (dst1));
3614 OUTS (outf, " = ");
3615 OUTS (outf, dregs (src0));
3616 OUTS (outf, " + ");
3617 OUTS (outf, dregs (src1));
3618 OUTS (outf, ", ");
3619 OUTS (outf, dregs (dst0));
3620 OUTS (outf, " = ");
3621 OUTS (outf, dregs (src0));
3622 OUTS (outf, " - ");
3623 OUTS (outf, dregs (src1));
3624 amod1 (s, x, outf);
3625 }
3626 else if (HL == 0 && aopcde == 1)
3627 {
3628 OUTS (outf, dregs (dst1));
3629 OUTS (outf, " = ");
3630 OUTS (outf, dregs (src0));
3631 OUTS (outf, " +|+ ");
3632 OUTS (outf, dregs (src1));
3633 OUTS (outf, ", ");
3634 OUTS (outf, dregs (dst0));
3635 OUTS (outf, " = ");
3636 OUTS (outf, dregs (src0));
3637 OUTS (outf, " -|- ");
3638 OUTS (outf, dregs (src1));
3639 amod0amod2 (s, x, aop, outf);
3640 }
3641 else if (aop == 0 && aopcde == 11)
3642 {
3643 OUTS (outf, dregs (dst0));
3644 OUTS (outf, " = (A0 += A1)");
3645 }
3646 else if (aop == 0 && aopcde == 10)
3647 {
3648 OUTS (outf, dregs_lo (dst0));
3649 OUTS (outf, " = A0.X");
3650 }
3651 else if (aop == 1 && aopcde == 10)
3652 {
3653 OUTS (outf, dregs_lo (dst0));
3654 OUTS (outf, " = A1.X");
3655 }
3656 else if (aop == 1 && aopcde == 0)
3657 {
3658 OUTS (outf, dregs (dst0));
3659 OUTS (outf, " = ");
3660 OUTS (outf, dregs (src0));
3661 OUTS (outf, " +|- ");
3662 OUTS (outf, dregs (src1));
3663 amod0 (s, x, outf);
3664 }
3665 else if (aop == 3 && aopcde == 0)
3666 {
3667 OUTS (outf, dregs (dst0));
3668 OUTS (outf, " = ");
3669 OUTS (outf, dregs (src0));
3670 OUTS (outf, " -|- ");
3671 OUTS (outf, dregs (src1));
3672 amod0 (s, x, outf);
3673 }
3674 else if (aop == 1 && aopcde == 4)
3675 {
3676 OUTS (outf, dregs (dst0));
3677 OUTS (outf, " = ");
3678 OUTS (outf, dregs (src0));
3679 OUTS (outf, " - ");
3680 OUTS (outf, dregs (src1));
3681 amod1 (s, x, outf);
3682 }
3683 else if (aop == 0 && aopcde == 17)
3684 {
3685 OUTS (outf, dregs (dst1));
3686 OUTS (outf, " = A1 + A0, ");
3687 OUTS (outf, dregs (dst0));
3688 OUTS (outf, " = A1 - A0");
3689 amod1 (s, x, outf);
3690 }
3691 else if (aop == 1 && aopcde == 17)
3692 {
3693 OUTS (outf, dregs (dst1));
3694 OUTS (outf, " = A0 + A1, ");
3695 OUTS (outf, dregs (dst0));
3696 OUTS (outf, " = A0 - A1");
3697 amod1 (s, x, outf);
3698 }
3699 else if (aop == 0 && aopcde == 18)
3700 {
3701 OUTS (outf, "SAA (");
3702 OUTS (outf, dregs (src0 + 1));
3703 OUTS (outf, ":");
3704 OUTS (outf, imm5d (src0));
3705 OUTS (outf, ", ");
3706 OUTS (outf, dregs (src1 + 1));
3707 OUTS (outf, ":");
3708 OUTS (outf, imm5d (src1));
3709 OUTS (outf, ")");
3710 aligndir (s, outf);
3711 }
3712 else if (aop == 3 && aopcde == 18)
3713 OUTS (outf, "DISALGNEXCPT");
3714
3715 else if (aop == 0 && aopcde == 20)
3716 {
3717 OUTS (outf, dregs (dst0));
3718 OUTS (outf, " = BYTEOP1P (");
3719 OUTS (outf, dregs (src0 + 1));
3720 OUTS (outf, ":");
3721 OUTS (outf, imm5d (src0));
3722 OUTS (outf, ", ");
3723 OUTS (outf, dregs (src1 + 1));
3724 OUTS (outf, ":");
3725 OUTS (outf, imm5d (src1));
3726 OUTS (outf, ")");
3727 aligndir (s, outf);
3728 }
3729 else if (aop == 1 && aopcde == 20)
3730 {
3731 OUTS (outf, dregs (dst0));
3732 OUTS (outf, " = BYTEOP1P (");
3733 OUTS (outf, dregs (src0 + 1));
3734 OUTS (outf, ":");
3735 OUTS (outf, imm5d (src0));
3736 OUTS (outf, ", ");
3737 OUTS (outf, dregs (src1 + 1));
3738 OUTS (outf, ":");
3739 OUTS (outf, imm5d (src1));
3740 OUTS (outf, ") (T");
3741 if (s == 1)
3742 OUTS (outf, ", R)");
3743 else
3744 OUTS (outf, ")");
3745 }
3746 else if (aop == 0 && aopcde == 21)
3747 {
3748 OUTS (outf, "(");
3749 OUTS (outf, dregs (dst1));
3750 OUTS (outf, ", ");
3751 OUTS (outf, dregs (dst0));
3752 OUTS (outf, ") = BYTEOP16P (");
3753 OUTS (outf, dregs (src0 + 1));
3754 OUTS (outf, ":");
3755 OUTS (outf, imm5d (src0));
3756 OUTS (outf, ", ");
3757 OUTS (outf, dregs (src1 + 1));
3758 OUTS (outf, ":");
3759 OUTS (outf, imm5d (src1));
3760 OUTS (outf, ")");
3761 aligndir (s, outf);
3762 }
3763 else if (aop == 1 && aopcde == 21)
3764 {
3765 OUTS (outf, "(");
3766 OUTS (outf, dregs (dst1));
3767 OUTS (outf, ", ");
3768 OUTS (outf, dregs (dst0));
3769 OUTS (outf, ") = BYTEOP16M (");
3770 OUTS (outf, dregs (src0 + 1));
3771 OUTS (outf, ":");
3772 OUTS (outf, imm5d (src0));
3773 OUTS (outf, ", ");
3774 OUTS (outf, dregs (src1 + 1));
3775 OUTS (outf, ":");
3776 OUTS (outf, imm5d (src1));
3777 OUTS (outf, ")");
3778 aligndir (s, outf);
3779 }
3780 else if (aop == 2 && aopcde == 7)
3781 {
3782 OUTS (outf, dregs (dst0));
3783 OUTS (outf, " = ABS ");
3784 OUTS (outf, dregs (src0));
3785 }
3786 else if (aop == 1 && aopcde == 7)
3787 {
3788 OUTS (outf, dregs (dst0));
3789 OUTS (outf, " = MIN (");
3790 OUTS (outf, dregs (src0));
3791 OUTS (outf, ", ");
3792 OUTS (outf, dregs (src1));
3793 OUTS (outf, ")");
3794 }
3795 else if (aop == 0 && aopcde == 7)
3796 {
3797 OUTS (outf, dregs (dst0));
3798 OUTS (outf, " = MAX (");
3799 OUTS (outf, dregs (src0));
3800 OUTS (outf, ", ");
3801 OUTS (outf, dregs (src1));
3802 OUTS (outf, ")");
3803 }
3804 else if (aop == 2 && aopcde == 6)
3805 {
3806 OUTS (outf, dregs (dst0));
3807 OUTS (outf, " = ABS ");
3808 OUTS (outf, dregs (src0));
3809 OUTS (outf, " (V)");
3810 }
3811 else if (aop == 1 && aopcde == 6)
3812 {
3813 OUTS (outf, dregs (dst0));
3814 OUTS (outf, " = MIN (");
3815 OUTS (outf, dregs (src0));
3816 OUTS (outf, ", ");
3817 OUTS (outf, dregs (src1));
3818 OUTS (outf, ") (V)");
3819 }
3820 else if (aop == 0 && aopcde == 6)
3821 {
3822 OUTS (outf, dregs (dst0));
3823 OUTS (outf, " = MAX (");
3824 OUTS (outf, dregs (src0));
3825 OUTS (outf, ", ");
3826 OUTS (outf, dregs (src1));
3827 OUTS (outf, ") (V)");
3828 }
3829 else if (HL == 1 && aopcde == 1)
3830 {
3831 OUTS (outf, dregs (dst1));
3832 OUTS (outf, " = ");
3833 OUTS (outf, dregs (src0));
3834 OUTS (outf, " +|- ");
3835 OUTS (outf, dregs (src1));
3836 OUTS (outf, ", ");
3837 OUTS (outf, dregs (dst0));
3838 OUTS (outf, " = ");
3839 OUTS (outf, dregs (src0));
3840 OUTS (outf, " -|+ ");
3841 OUTS (outf, dregs (src1));
3842 amod0amod2 (s, x, aop, outf);
3843 }
3844 else if (aop == 0 && aopcde == 4)
3845 {
3846 OUTS (outf, dregs (dst0));
3847 OUTS (outf, " = ");
3848 OUTS (outf, dregs (src0));
3849 OUTS (outf, " + ");
3850 OUTS (outf, dregs (src1));
3851 amod1 (s, x, outf);
3852 }
3853 else if (aop == 0 && aopcde == 0)
3854 {
3855 OUTS (outf, dregs (dst0));
3856 OUTS (outf, " = ");
3857 OUTS (outf, dregs (src0));
3858 OUTS (outf, " +|+ ");
3859 OUTS (outf, dregs (src1));
3860 amod0 (s, x, outf);
3861 }
3862 else if (aop == 0 && aopcde == 24)
3863 {
3864 OUTS (outf, dregs (dst0));
3865 OUTS (outf, " = BYTEPACK (");
3866 OUTS (outf, dregs (src0));
3867 OUTS (outf, ", ");
3868 OUTS (outf, dregs (src1));
3869 OUTS (outf, ")");
3870 }
3871 else if (aop == 1 && aopcde == 24)
3872 {
3873 OUTS (outf, "(");
3874 OUTS (outf, dregs (dst1));
3875 OUTS (outf, ", ");
3876 OUTS (outf, dregs (dst0));
3877 OUTS (outf, ") = BYTEUNPACK ");
3878 OUTS (outf, dregs (src0 + 1));
3879 OUTS (outf, ":");
3880 OUTS (outf, imm5d (src0));
3881 aligndir (s, outf);
3882 }
3883 else if (aopcde == 13)
3884 {
3885 OUTS (outf, "(");
3886 OUTS (outf, dregs (dst1));
3887 OUTS (outf, ", ");
3888 OUTS (outf, dregs (dst0));
3889 OUTS (outf, ") = SEARCH ");
3890 OUTS (outf, dregs (src0));
3891 OUTS (outf, " (");
3892 searchmod (aop, outf);
3893 OUTS (outf, ")");
3894 }
3895 else
3896 return 0;
3897
3898 return 4;
3899 }
3900
3901 static int
3902 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3903 {
3904 /* dsp32shift
3905 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3906 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3907 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3908 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3909 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3910 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3911 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3912 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3913 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3914 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
3915 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
3916
3917 if (HLs == 0 && sop == 0 && sopcde == 0)
3918 {
3919 OUTS (outf, dregs_lo (dst0));
3920 OUTS (outf, " = ASHIFT ");
3921 OUTS (outf, dregs_lo (src1));
3922 OUTS (outf, " BY ");
3923 OUTS (outf, dregs_lo (src0));
3924 }
3925 else if (HLs == 1 && sop == 0 && sopcde == 0)
3926 {
3927 OUTS (outf, dregs_lo (dst0));
3928 OUTS (outf, " = ASHIFT ");
3929 OUTS (outf, dregs_hi (src1));
3930 OUTS (outf, " BY ");
3931 OUTS (outf, dregs_lo (src0));
3932 }
3933 else if (HLs == 2 && sop == 0 && sopcde == 0)
3934 {
3935 OUTS (outf, dregs_hi (dst0));
3936 OUTS (outf, " = ASHIFT ");
3937 OUTS (outf, dregs_lo (src1));
3938 OUTS (outf, " BY ");
3939 OUTS (outf, dregs_lo (src0));
3940 }
3941 else if (HLs == 3 && sop == 0 && sopcde == 0)
3942 {
3943 OUTS (outf, dregs_hi (dst0));
3944 OUTS (outf, " = ASHIFT ");
3945 OUTS (outf, dregs_hi (src1));
3946 OUTS (outf, " BY ");
3947 OUTS (outf, dregs_lo (src0));
3948 }
3949 else if (HLs == 0 && sop == 1 && sopcde == 0)
3950 {
3951 OUTS (outf, dregs_lo (dst0));
3952 OUTS (outf, " = ASHIFT ");
3953 OUTS (outf, dregs_lo (src1));
3954 OUTS (outf, " BY ");
3955 OUTS (outf, dregs_lo (src0));
3956 OUTS (outf, " (S)");
3957 }
3958 else if (HLs == 1 && sop == 1 && sopcde == 0)
3959 {
3960 OUTS (outf, dregs_lo (dst0));
3961 OUTS (outf, " = ASHIFT ");
3962 OUTS (outf, dregs_hi (src1));
3963 OUTS (outf, " BY ");
3964 OUTS (outf, dregs_lo (src0));
3965 OUTS (outf, " (S)");
3966 }
3967 else if (HLs == 2 && sop == 1 && sopcde == 0)
3968 {
3969 OUTS (outf, dregs_hi (dst0));
3970 OUTS (outf, " = ASHIFT ");
3971 OUTS (outf, dregs_lo (src1));
3972 OUTS (outf, " BY ");
3973 OUTS (outf, dregs_lo (src0));
3974 OUTS (outf, " (S)");
3975 }
3976 else if (HLs == 3 && sop == 1 && sopcde == 0)
3977 {
3978 OUTS (outf, dregs_hi (dst0));
3979 OUTS (outf, " = ASHIFT ");
3980 OUTS (outf, dregs_hi (src1));
3981 OUTS (outf, " BY ");
3982 OUTS (outf, dregs_lo (src0));
3983 OUTS (outf, " (S)");
3984 }
3985 else if (sop == 2 && sopcde == 0)
3986 {
3987 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
3988 OUTS (outf, " = LSHIFT ");
3989 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
3990 OUTS (outf, " BY ");
3991 OUTS (outf, dregs_lo (src0));
3992 }
3993 else if (sop == 0 && sopcde == 3)
3994 {
3995 OUTS (outf, acc01);
3996 OUTS (outf, " = ASHIFT ");
3997 OUTS (outf, acc01);
3998 OUTS (outf, " BY ");
3999 OUTS (outf, dregs_lo (src0));
4000 }
4001 else if (sop == 1 && sopcde == 3)
4002 {
4003 OUTS (outf, acc01);
4004 OUTS (outf, " = LSHIFT ");
4005 OUTS (outf, acc01);
4006 OUTS (outf, " BY ");
4007 OUTS (outf, dregs_lo (src0));
4008 }
4009 else if (sop == 2 && sopcde == 3)
4010 {
4011 OUTS (outf, acc01);
4012 OUTS (outf, " = ROT ");
4013 OUTS (outf, acc01);
4014 OUTS (outf, " BY ");
4015 OUTS (outf, dregs_lo (src0));
4016 }
4017 else if (sop == 3 && sopcde == 3)
4018 {
4019 OUTS (outf, dregs (dst0));
4020 OUTS (outf, " = ROT ");
4021 OUTS (outf, dregs (src1));
4022 OUTS (outf, " BY ");
4023 OUTS (outf, dregs_lo (src0));
4024 }
4025 else if (sop == 1 && sopcde == 1)
4026 {
4027 OUTS (outf, dregs (dst0));
4028 OUTS (outf, " = ASHIFT ");
4029 OUTS (outf, dregs (src1));
4030 OUTS (outf, " BY ");
4031 OUTS (outf, dregs_lo (src0));
4032 OUTS (outf, " (V, S)");
4033 }
4034 else if (sop == 0 && sopcde == 1)
4035 {
4036 OUTS (outf, dregs (dst0));
4037 OUTS (outf, " = ASHIFT ");
4038 OUTS (outf, dregs (src1));
4039 OUTS (outf, " BY ");
4040 OUTS (outf, dregs_lo (src0));
4041 OUTS (outf, " (V)");
4042 }
4043 else if (sop == 0 && sopcde == 2)
4044 {
4045 OUTS (outf, dregs (dst0));
4046 OUTS (outf, " = ASHIFT ");
4047 OUTS (outf, dregs (src1));
4048 OUTS (outf, " BY ");
4049 OUTS (outf, dregs_lo (src0));
4050 }
4051 else if (sop == 1 && sopcde == 2)
4052 {
4053 OUTS (outf, dregs (dst0));
4054 OUTS (outf, " = ASHIFT ");
4055 OUTS (outf, dregs (src1));
4056 OUTS (outf, " BY ");
4057 OUTS (outf, dregs_lo (src0));
4058 OUTS (outf, " (S)");
4059 }
4060 else if (sop == 2 && sopcde == 2)
4061 {
4062 OUTS (outf, dregs (dst0));
4063 OUTS (outf, " = LSHIFT ");
4064 OUTS (outf, dregs (src1));
4065 OUTS (outf, " BY ");
4066 OUTS (outf, dregs_lo (src0));
4067 }
4068 else if (sop == 3 && sopcde == 2)
4069 {
4070 OUTS (outf, dregs (dst0));
4071 OUTS (outf, " = ROT ");
4072 OUTS (outf, dregs (src1));
4073 OUTS (outf, " BY ");
4074 OUTS (outf, dregs_lo (src0));
4075 }
4076 else if (sop == 2 && sopcde == 1)
4077 {
4078 OUTS (outf, dregs (dst0));
4079 OUTS (outf, " = LSHIFT ");
4080 OUTS (outf, dregs (src1));
4081 OUTS (outf, " BY ");
4082 OUTS (outf, dregs_lo (src0));
4083 OUTS (outf, " (V)");
4084 }
4085 else if (sop == 0 && sopcde == 4)
4086 {
4087 OUTS (outf, dregs (dst0));
4088 OUTS (outf, " = PACK (");
4089 OUTS (outf, dregs_lo (src1));
4090 OUTS (outf, ", ");
4091 OUTS (outf, dregs_lo (src0));
4092 OUTS (outf, ")");
4093 }
4094 else if (sop == 1 && sopcde == 4)
4095 {
4096 OUTS (outf, dregs (dst0));
4097 OUTS (outf, " = PACK (");
4098 OUTS (outf, dregs_lo (src1));
4099 OUTS (outf, ", ");
4100 OUTS (outf, dregs_hi (src0));
4101 OUTS (outf, ")");
4102 }
4103 else if (sop == 2 && sopcde == 4)
4104 {
4105 OUTS (outf, dregs (dst0));
4106 OUTS (outf, " = PACK (");
4107 OUTS (outf, dregs_hi (src1));
4108 OUTS (outf, ", ");
4109 OUTS (outf, dregs_lo (src0));
4110 OUTS (outf, ")");
4111 }
4112 else if (sop == 3 && sopcde == 4)
4113 {
4114 OUTS (outf, dregs (dst0));
4115 OUTS (outf, " = PACK (");
4116 OUTS (outf, dregs_hi (src1));
4117 OUTS (outf, ", ");
4118 OUTS (outf, dregs_hi (src0));
4119 OUTS (outf, ")");
4120 }
4121 else if (sop == 0 && sopcde == 5)
4122 {
4123 OUTS (outf, dregs_lo (dst0));
4124 OUTS (outf, " = SIGNBITS ");
4125 OUTS (outf, dregs (src1));
4126 }
4127 else if (sop == 1 && sopcde == 5)
4128 {
4129 OUTS (outf, dregs_lo (dst0));
4130 OUTS (outf, " = SIGNBITS ");
4131 OUTS (outf, dregs_lo (src1));
4132 }
4133 else if (sop == 2 && sopcde == 5)
4134 {
4135 OUTS (outf, dregs_lo (dst0));
4136 OUTS (outf, " = SIGNBITS ");
4137 OUTS (outf, dregs_hi (src1));
4138 }
4139 else if (sop == 0 && sopcde == 6)
4140 {
4141 OUTS (outf, dregs_lo (dst0));
4142 OUTS (outf, " = SIGNBITS A0");
4143 }
4144 else if (sop == 1 && sopcde == 6)
4145 {
4146 OUTS (outf, dregs_lo (dst0));
4147 OUTS (outf, " = SIGNBITS A1");
4148 }
4149 else if (sop == 3 && sopcde == 6)
4150 {
4151 OUTS (outf, dregs_lo (dst0));
4152 OUTS (outf, " = ONES ");
4153 OUTS (outf, dregs (src1));
4154 }
4155 else if (sop == 0 && sopcde == 7)
4156 {
4157 OUTS (outf, dregs_lo (dst0));
4158 OUTS (outf, " = EXPADJ (");
4159 OUTS (outf, dregs (src1));
4160 OUTS (outf, ", ");
4161 OUTS (outf, dregs_lo (src0));
4162 OUTS (outf, ")");
4163 }
4164 else if (sop == 1 && sopcde == 7)
4165 {
4166 OUTS (outf, dregs_lo (dst0));
4167 OUTS (outf, " = EXPADJ (");
4168 OUTS (outf, dregs (src1));
4169 OUTS (outf, ", ");
4170 OUTS (outf, dregs_lo (src0));
4171 OUTS (outf, ") (V)");
4172 }
4173 else if (sop == 2 && sopcde == 7)
4174 {
4175 OUTS (outf, dregs_lo (dst0));
4176 OUTS (outf, " = EXPADJ (");
4177 OUTS (outf, dregs_lo (src1));
4178 OUTS (outf, ", ");
4179 OUTS (outf, dregs_lo (src0));
4180 OUTS (outf, ")");
4181 }
4182 else if (sop == 3 && sopcde == 7)
4183 {
4184 OUTS (outf, dregs_lo (dst0));
4185 OUTS (outf, " = EXPADJ (");
4186 OUTS (outf, dregs_hi (src1));
4187 OUTS (outf, ", ");
4188 OUTS (outf, dregs_lo (src0));
4189 OUTS (outf, ")");
4190 }
4191 else if (sop == 0 && sopcde == 8)
4192 {
4193 OUTS (outf, "BITMUX (");
4194 OUTS (outf, dregs (src0));
4195 OUTS (outf, ", ");
4196 OUTS (outf, dregs (src1));
4197 OUTS (outf, ", A0) (ASR)");
4198 }
4199 else if (sop == 1 && sopcde == 8)
4200 {
4201 OUTS (outf, "BITMUX (");
4202 OUTS (outf, dregs (src0));
4203 OUTS (outf, ", ");
4204 OUTS (outf, dregs (src1));
4205 OUTS (outf, ", A0) (ASL)");
4206 }
4207 else if (sop == 0 && sopcde == 9)
4208 {
4209 OUTS (outf, dregs_lo (dst0));
4210 OUTS (outf, " = VIT_MAX (");
4211 OUTS (outf, dregs (src1));
4212 OUTS (outf, ") (ASL)");
4213 }
4214 else if (sop == 1 && sopcde == 9)
4215 {
4216 OUTS (outf, dregs_lo (dst0));
4217 OUTS (outf, " = VIT_MAX (");
4218 OUTS (outf, dregs (src1));
4219 OUTS (outf, ") (ASR)");
4220 }
4221 else if (sop == 2 && sopcde == 9)
4222 {
4223 OUTS (outf, dregs (dst0));
4224 OUTS (outf, " = VIT_MAX (");
4225 OUTS (outf, dregs (src1));
4226 OUTS (outf, ", ");
4227 OUTS (outf, dregs (src0));
4228 OUTS (outf, ") (ASL)");
4229 }
4230 else if (sop == 3 && sopcde == 9)
4231 {
4232 OUTS (outf, dregs (dst0));
4233 OUTS (outf, " = VIT_MAX (");
4234 OUTS (outf, dregs (src1));
4235 OUTS (outf, ", ");
4236 OUTS (outf, dregs (src0));
4237 OUTS (outf, ") (ASR)");
4238 }
4239 else if (sop == 0 && sopcde == 10)
4240 {
4241 OUTS (outf, dregs (dst0));
4242 OUTS (outf, " = EXTRACT (");
4243 OUTS (outf, dregs (src1));
4244 OUTS (outf, ", ");
4245 OUTS (outf, dregs_lo (src0));
4246 OUTS (outf, ") (Z)");
4247 }
4248 else if (sop == 1 && sopcde == 10)
4249 {
4250 OUTS (outf, dregs (dst0));
4251 OUTS (outf, " = EXTRACT (");
4252 OUTS (outf, dregs (src1));
4253 OUTS (outf, ", ");
4254 OUTS (outf, dregs_lo (src0));
4255 OUTS (outf, ") (X)");
4256 }
4257 else if (sop == 2 && sopcde == 10)
4258 {
4259 OUTS (outf, dregs (dst0));
4260 OUTS (outf, " = DEPOSIT (");
4261 OUTS (outf, dregs (src1));
4262 OUTS (outf, ", ");
4263 OUTS (outf, dregs (src0));
4264 OUTS (outf, ")");
4265 }
4266 else if (sop == 3 && sopcde == 10)
4267 {
4268 OUTS (outf, dregs (dst0));
4269 OUTS (outf, " = DEPOSIT (");
4270 OUTS (outf, dregs (src1));
4271 OUTS (outf, ", ");
4272 OUTS (outf, dregs (src0));
4273 OUTS (outf, ") (X)");
4274 }
4275 else if (sop == 0 && sopcde == 11)
4276 {
4277 OUTS (outf, dregs_lo (dst0));
4278 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4279 OUTS (outf, dregs (src0));
4280 OUTS (outf, ")");
4281 }
4282 else if (sop == 1 && sopcde == 11)
4283 {
4284 OUTS (outf, dregs_lo (dst0));
4285 OUTS (outf, " = CC = BXOR (A0, ");
4286 OUTS (outf, dregs (src0));
4287 OUTS (outf, ")");
4288 }
4289 else if (sop == 0 && sopcde == 12)
4290 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4291
4292 else if (sop == 1 && sopcde == 12)
4293 {
4294 OUTS (outf, dregs_lo (dst0));
4295 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4296 }
4297 else if (sop == 0 && sopcde == 13)
4298 {
4299 OUTS (outf, dregs (dst0));
4300 OUTS (outf, " = ALIGN8 (");
4301 OUTS (outf, dregs (src1));
4302 OUTS (outf, ", ");
4303 OUTS (outf, dregs (src0));
4304 OUTS (outf, ")");
4305 }
4306 else if (sop == 1 && sopcde == 13)
4307 {
4308 OUTS (outf, dregs (dst0));
4309 OUTS (outf, " = ALIGN16 (");
4310 OUTS (outf, dregs (src1));
4311 OUTS (outf, ", ");
4312 OUTS (outf, dregs (src0));
4313 OUTS (outf, ")");
4314 }
4315 else if (sop == 2 && sopcde == 13)
4316 {
4317 OUTS (outf, dregs (dst0));
4318 OUTS (outf, " = ALIGN24 (");
4319 OUTS (outf, dregs (src1));
4320 OUTS (outf, ", ");
4321 OUTS (outf, dregs (src0));
4322 OUTS (outf, ")");
4323 }
4324 else
4325 return 0;
4326
4327 return 4;
4328 }
4329
4330 static int
4331 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4332 {
4333 /* dsp32shiftimm
4334 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4335 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4336 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4337 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4338 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4339 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4340 int bit8 = ((iw1 >> 8) & 0x1);
4341 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4342 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4343 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4344 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4345 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4346
4347
4348 if (sop == 0 && sopcde == 0)
4349 {
4350 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4351 OUTS (outf, " = ");
4352 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4353 OUTS (outf, " >>> ");
4354 OUTS (outf, uimm4 (newimmag));
4355 }
4356 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4357 {
4358 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4359 OUTS (outf, " = ");
4360 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4361 OUTS (outf, " << ");
4362 OUTS (outf, uimm4 (immag));
4363 OUTS (outf, " (S)");
4364 }
4365 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4366 {
4367 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4368 OUTS (outf, " = ");
4369 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4370 OUTS (outf, " >>> ");
4371 OUTS (outf, uimm4 (newimmag));
4372 OUTS (outf, " (S)");
4373 }
4374 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4375 {
4376 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4377 OUTS (outf, " = ");
4378 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4379 OUTS (outf, " << ");
4380 OUTS (outf, uimm4 (immag));
4381 }
4382 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4383 {
4384 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4385 OUTS (outf, " = ");
4386 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4387 OUTS (outf, " >> ");
4388 OUTS (outf, uimm4 (newimmag));
4389 }
4390 else if (sop == 2 && sopcde == 3 && HLs == 1)
4391 {
4392 OUTS (outf, "A1 = ROT A1 BY ");
4393 OUTS (outf, imm6 (immag));
4394 }
4395 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4396 {
4397 OUTS (outf, "A0 = A0 << ");
4398 OUTS (outf, uimm5 (immag));
4399 }
4400 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4401 {
4402 OUTS (outf, "A0 = A0 >>> ");
4403 OUTS (outf, uimm5 (newimmag));
4404 }
4405 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4406 {
4407 OUTS (outf, "A1 = A1 << ");
4408 OUTS (outf, uimm5 (immag));
4409 }
4410 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4411 {
4412 OUTS (outf, "A1 = A1 >>> ");
4413 OUTS (outf, uimm5 (newimmag));
4414 }
4415 else if (sop == 1 && sopcde == 3 && HLs == 0)
4416 {
4417 OUTS (outf, "A0 = A0 >> ");
4418 OUTS (outf, uimm5 (newimmag));
4419 }
4420 else if (sop == 1 && sopcde == 3 && HLs == 1)
4421 {
4422 OUTS (outf, "A1 = A1 >> ");
4423 OUTS (outf, uimm5 (newimmag));
4424 }
4425 else if (sop == 2 && sopcde == 3 && HLs == 0)
4426 {
4427 OUTS (outf, "A0 = ROT A0 BY ");
4428 OUTS (outf, imm6 (immag));
4429 }
4430 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4431 {
4432 OUTS (outf, dregs (dst0));
4433 OUTS (outf, " = ");
4434 OUTS (outf, dregs (src1));
4435 OUTS (outf, " << ");
4436 OUTS (outf, uimm5 (immag));
4437 OUTS (outf, " (V, S)");
4438 }
4439 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4440 {
4441 OUTS (outf, dregs (dst0));
4442 OUTS (outf, " = ");
4443 OUTS (outf, dregs (src1));
4444 OUTS (outf, " >>> ");
4445 OUTS (outf, imm5 (-immag));
4446 OUTS (outf, " (V)");
4447 }
4448 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4449 {
4450 OUTS (outf, dregs (dst0));
4451 OUTS (outf, " = ");
4452 OUTS (outf, dregs (src1));
4453 OUTS (outf, " >> ");
4454 OUTS (outf, uimm5 (newimmag));
4455 OUTS (outf, " (V)");
4456 }
4457 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4458 {
4459 OUTS (outf, dregs (dst0));
4460 OUTS (outf, " = ");
4461 OUTS (outf, dregs (src1));
4462 OUTS (outf, " << ");
4463 OUTS (outf, imm5 (immag));
4464 OUTS (outf, " (V)");
4465 }
4466 else if (sop == 0 && sopcde == 1)
4467 {
4468 OUTS (outf, dregs (dst0));
4469 OUTS (outf, " = ");
4470 OUTS (outf, dregs (src1));
4471 OUTS (outf, " >>> ");
4472 OUTS (outf, uimm5 (newimmag));
4473 OUTS (outf, " (V)");
4474 }
4475 else if (sop == 1 && sopcde == 2)
4476 {
4477 OUTS (outf, dregs (dst0));
4478 OUTS (outf, " = ");
4479 OUTS (outf, dregs (src1));
4480 OUTS (outf, " << ");
4481 OUTS (outf, uimm5 (immag));
4482 OUTS (outf, " (S)");
4483 }
4484 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4485 {
4486 OUTS (outf, dregs (dst0));
4487 OUTS (outf, " = ");
4488 OUTS (outf, dregs (src1));
4489 OUTS (outf, " >> ");
4490 OUTS (outf, uimm5 (newimmag));
4491 }
4492 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4493 {
4494 OUTS (outf, dregs (dst0));
4495 OUTS (outf, " = ");
4496 OUTS (outf, dregs (src1));
4497 OUTS (outf, " << ");
4498 OUTS (outf, uimm5 (immag));
4499 }
4500 else if (sop == 3 && sopcde == 2)
4501 {
4502 OUTS (outf, dregs (dst0));
4503 OUTS (outf, " = ROT ");
4504 OUTS (outf, dregs (src1));
4505 OUTS (outf, " BY ");
4506 OUTS (outf, imm6 (immag));
4507 }
4508 else if (sop == 0 && sopcde == 2)
4509 {
4510 OUTS (outf, dregs (dst0));
4511 OUTS (outf, " = ");
4512 OUTS (outf, dregs (src1));
4513 OUTS (outf, " >>> ");
4514 OUTS (outf, uimm5 (newimmag));
4515 }
4516 else
4517 return 0;
4518
4519 return 4;
4520 }
4521
4522 static int
4523 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4524 {
4525 /* pseudoDEBUG
4526 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4527 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4528 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4529 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4530 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4531 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4532
4533 if (reg == 0 && fn == 3)
4534 OUTS (outf, "DBG A0");
4535
4536 else if (reg == 1 && fn == 3)
4537 OUTS (outf, "DBG A1");
4538
4539 else if (reg == 3 && fn == 3)
4540 OUTS (outf, "ABORT");
4541
4542 else if (reg == 4 && fn == 3)
4543 OUTS (outf, "HLT");
4544
4545 else if (reg == 5 && fn == 3)
4546 OUTS (outf, "DBGHALT");
4547
4548 else if (reg == 6 && fn == 3)
4549 {
4550 OUTS (outf, "DBGCMPLX (");
4551 OUTS (outf, dregs (grp));
4552 OUTS (outf, ")");
4553 }
4554 else if (reg == 7 && fn == 3)
4555 OUTS (outf, "DBG");
4556
4557 else if (grp == 0 && fn == 2)
4558 {
4559 OUTS (outf, "OUTC ");
4560 OUTS (outf, dregs (reg));
4561 }
4562 else if (fn == 0)
4563 {
4564 OUTS (outf, "DBG ");
4565 OUTS (outf, allregs (reg, grp));
4566 }
4567 else if (fn == 1)
4568 {
4569 OUTS (outf, "PRNT");
4570 OUTS (outf, allregs (reg, grp));
4571 }
4572 else
4573 return 0;
4574
4575 return 2;
4576 }
4577
4578 static int
4579 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4580 {
4581 /* psedoOChar
4582 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4583 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4584 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4585 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4586
4587 OUTS (outf, "OUTC ");
4588 OUTS (outf, uimm8 (ch));
4589
4590 return 2;
4591 }
4592
4593 static int
4594 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4595 {
4596 /* pseudodbg_assert
4597 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4598 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4599 |.expected......................................................|
4600 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4601 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4602 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4603 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4604 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4605
4606 if (dbgop == 0)
4607 {
4608 OUTS (outf, "DBGA (");
4609 OUTS (outf, regs_lo (regtest, grp));
4610 OUTS (outf, ", ");
4611 OUTS (outf, uimm16 (expected));
4612 OUTS (outf, ")");
4613 }
4614 else if (dbgop == 1)
4615 {
4616 OUTS (outf, "DBGA (");
4617 OUTS (outf, regs_hi (regtest, grp));
4618 OUTS (outf, ", ");
4619 OUTS (outf, uimm16 (expected));
4620 OUTS (outf, ")");
4621 }
4622 else if (dbgop == 2)
4623 {
4624 OUTS (outf, "DBGAL (");
4625 OUTS (outf, allregs (regtest, grp));
4626 OUTS (outf, ", ");
4627 OUTS (outf, uimm16 (expected));
4628 OUTS (outf, ")");
4629 }
4630 else if (dbgop == 3)
4631 {
4632 OUTS (outf, "DBGAH (");
4633 OUTS (outf, allregs (regtest, grp));
4634 OUTS (outf, ", ");
4635 OUTS (outf, uimm16 (expected));
4636 OUTS (outf, ")");
4637 }
4638 else
4639 return 0;
4640 return 4;
4641 }
4642
4643 static int
4644 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4645 {
4646 bfd_byte buf[4];
4647 TIword iw0;
4648 TIword iw1;
4649 int status;
4650 int rv = 0;
4651
4652 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4653 /* FIXME */
4654 (void) status;
4655 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4656 /* FIXME */
4657 (void) status;
4658
4659 iw0 = bfd_getl16 (buf);
4660 iw1 = bfd_getl16 (buf + 2);
4661
4662 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4663 {
4664 OUTS (outf, "MNOP");
4665 return 4;
4666 }
4667 else if ((iw0 & 0xff00) == 0x0000)
4668 rv = decode_ProgCtrl_0 (iw0, outf);
4669 else if ((iw0 & 0xffc0) == 0x0240)
4670 rv = decode_CaCTRL_0 (iw0, outf);
4671 else if ((iw0 & 0xff80) == 0x0100)
4672 rv = decode_PushPopReg_0 (iw0, outf);
4673 else if ((iw0 & 0xfe00) == 0x0400)
4674 rv = decode_PushPopMultiple_0 (iw0, outf);
4675 else if ((iw0 & 0xfe00) == 0x0600)
4676 rv = decode_ccMV_0 (iw0, outf);
4677 else if ((iw0 & 0xf800) == 0x0800)
4678 rv = decode_CCflag_0 (iw0, outf);
4679 else if ((iw0 & 0xffe0) == 0x0200)
4680 rv = decode_CC2dreg_0 (iw0, outf);
4681 else if ((iw0 & 0xff00) == 0x0300)
4682 rv = decode_CC2stat_0 (iw0, outf);
4683 else if ((iw0 & 0xf000) == 0x1000)
4684 rv = decode_BRCC_0 (iw0, pc, outf);
4685 else if ((iw0 & 0xf000) == 0x2000)
4686 rv = decode_UJUMP_0 (iw0, pc, outf);
4687 else if ((iw0 & 0xf000) == 0x3000)
4688 rv = decode_REGMV_0 (iw0, outf);
4689 else if ((iw0 & 0xfc00) == 0x4000)
4690 rv = decode_ALU2op_0 (iw0, outf);
4691 else if ((iw0 & 0xfe00) == 0x4400)
4692 rv = decode_PTR2op_0 (iw0, outf);
4693 else if ((iw0 & 0xf800) == 0x4800)
4694 rv = decode_LOGI2op_0 (iw0, outf);
4695 else if ((iw0 & 0xf000) == 0x5000)
4696 rv = decode_COMP3op_0 (iw0, outf);
4697 else if ((iw0 & 0xf800) == 0x6000)
4698 rv = decode_COMPI2opD_0 (iw0, outf);
4699 else if ((iw0 & 0xf800) == 0x6800)
4700 rv = decode_COMPI2opP_0 (iw0, outf);
4701 else if ((iw0 & 0xf000) == 0x8000)
4702 rv = decode_LDSTpmod_0 (iw0, outf);
4703 else if ((iw0 & 0xff60) == 0x9e60)
4704 rv = decode_dagMODim_0 (iw0, outf);
4705 else if ((iw0 & 0xfff0) == 0x9f60)
4706 rv = decode_dagMODik_0 (iw0, outf);
4707 else if ((iw0 & 0xfc00) == 0x9c00)
4708 rv = decode_dspLDST_0 (iw0, outf);
4709 else if ((iw0 & 0xf000) == 0x9000)
4710 rv = decode_LDST_0 (iw0, outf);
4711 else if ((iw0 & 0xfc00) == 0xb800)
4712 rv = decode_LDSTiiFP_0 (iw0, outf);
4713 else if ((iw0 & 0xe000) == 0xA000)
4714 rv = decode_LDSTii_0 (iw0, outf);
4715 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4716 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4717 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4718 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4719 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4720 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4721 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4722 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4723 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4724 rv = decode_linkage_0 (iw0, iw1, outf);
4725 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4726 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4727 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4728 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4729 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4730 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4731 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4732 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4733 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4734 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4735 else if ((iw0 & 0xff00) == 0xf800)
4736 rv = decode_pseudoDEBUG_0 (iw0, outf);
4737 else if ((iw0 & 0xFF00) == 0xF900)
4738 rv = decode_pseudoOChar_0 (iw0, outf);
4739 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4740 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4741
4742 return rv;
4743 }
4744
4745
4746 int
4747 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4748 {
4749 bfd_byte buf[2];
4750 unsigned short iw0;
4751 int status;
4752 int count = 0;
4753
4754 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4755 /* FIXME */
4756 (void) status;
4757 iw0 = bfd_getl16 (buf);
4758
4759 count += _print_insn_bfin (pc, outf);
4760
4761 /* Proper display of multiple issue instructions. */
4762
4763 if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4764 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4765 {
4766 parallel = 1;
4767 outf->fprintf_func (outf->stream, " || ");
4768 count += _print_insn_bfin (pc + 4, outf);
4769 outf->fprintf_func (outf->stream, " || ");
4770 count += _print_insn_bfin (pc + 6, outf);
4771 parallel = 0;
4772 }
4773 if (count == 0)
4774 {
4775 outf->fprintf_func (outf->stream, "ILLEGAL");
4776 return 2;
4777 }
4778 if (!comment)
4779 outf->fprintf_func (outf->stream, ";");
4780
4781 comment = 0;
4782
4783 return count;
4784 }
git-cvsimport of binutils cvsroot