opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* extended MMX support (with SSE or 3DNow!Ext) required */
  54 #define CpuMMX2         (CpuMMX + 1)
  55 /* SSE support required */
  56 #define CpuSSE          (CpuMMX2 + 1)
  57 /* SSE2 support required */
  58 #define CpuSSE2         (CpuSSE + 1)
  59 /* 3dnow! support required */
  60 #define Cpu3dnow        (CpuSSE2 + 1)
  61 /* 3dnow! Extensions support required */
  62 #define Cpu3dnowA       (Cpu3dnow + 1)
  63 /* SSE3 support required */
  64 #define CpuSSE3         (Cpu3dnowA + 1)
  65 /* VIA PadLock required */
  66 #define CpuPadLock      (CpuSSE3 + 1)
  67 /* AMD Secure Virtual Machine Ext-s required */
  68 #define CpuSVME         (CpuPadLock + 1)
  69 /* VMX Instructions required */
  70 #define CpuVMX          (CpuSVME + 1)
  71 /* SMX Instructions required */
  72 #define CpuSMX          (CpuVMX + 1)
  73 /* SSSE3 support required */
  74 #define CpuSSSE3        (CpuSMX + 1)
  75 /* SSE4a support required */
  76 #define CpuSSE4a        (CpuSSSE3 + 1)
  77 /* ABM New Instructions required */
  78 #define CpuABM          (CpuSSE4a + 1)
  79 /* SSE4.1 support required */
  80 #define CpuSSE4_1       (CpuABM + 1)
  81 /* SSE4.2 support required */
  82 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  83 /* SSE5 support required */
  84 #define CpuSSE5         (CpuSSE4_2 + 1)
  85 /* 64bit support available, used by -march= in assembler.  */
  86 #define CpuLM           (CpuSSE5 + 1)
  87 /* 64bit support required  */
  88 #define Cpu64           (CpuLM + 1)
  89 /* Not supported in the 64bit mode  */
  90 #define CpuNo64         (Cpu64 + 1)
  91 /* The last bitfield in i386_cpu_flags.  */
  92 #define CpuMax          CpuNo64
  93
  94 #define CpuNumOfUints \
  95   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
  96 #define CpuNumOfBits \
  97   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
  98
  99 /* If you get a compiler error for zero width of the unused field,
 100    comment it out.  */
 101 #define CpuUnused       (CpuMax + 1)
 102
 103 /* We can check if an instruction is available with array instead
 104    of bitfield. */
 105 typedef union i386_cpu_flags
 106 {
 107   struct
 108     {
 109       unsigned int cpui186:1;
 110       unsigned int cpui286:1;
 111       unsigned int cpui386:1;
 112       unsigned int cpui486:1;
 113       unsigned int cpui586:1;
 114       unsigned int cpui686:1;
 115       unsigned int cpup4:1;
 116       unsigned int cpuk6:1;
 117       unsigned int cpuk8:1;
 118       unsigned int cpummx:1;
 119       unsigned int cpummx2:1;
 120       unsigned int cpusse:1;
 121       unsigned int cpusse2:1;
 122       unsigned int cpua3dnow:1;
 123       unsigned int cpua3dnowa:1;
 124       unsigned int cpusse3:1;
 125       unsigned int cpupadlock:1;
 126       unsigned int cpusvme:1;
 127       unsigned int cpuvmx:1;
 128       unsigned int cpusmx:1;
 129       unsigned int cpussse3:1;
 130       unsigned int cpusse4a:1;
 131       unsigned int cpuabm:1;
 132       unsigned int cpusse4_1:1;
 133       unsigned int cpusse4_2:1;
 134       unsigned int cpusse5:1;
 135       unsigned int cpulm:1;
 136       unsigned int cpu64:1;
 137       unsigned int cpuno64:1;
 138 #ifdef CpuUnused
 139       unsigned int unused:(CpuNumOfBits - CpuUnused);
 140 #endif
 141     } bitfield;
 142   unsigned int array[CpuNumOfUints];
 143 } i386_cpu_flags;
 144
 145 /* Position of opcode_modifier bits.  */
 146
 147 /* has direction bit. */
 148 #define D                       0
 149 /* set if operands can be words or dwords encoded the canonical way */
 150 #define W                       (D + 1)
 151 /* insn has a modrm byte. */
 152 #define Modrm                   (W + 1)
 153 /* register is in low 3 bits of opcode */
 154 #define ShortForm               (Modrm + 1)
 155 /* special case for jump insns.  */
 156 #define Jump                    (ShortForm + 1)
 157 /* call and jump */
 158 #define JumpDword               (Jump + 1)
 159 /* loop and jecxz */
 160 #define JumpByte                (JumpDword + 1)
 161 /* special case for intersegment leaps/calls */
 162 #define JumpInterSegment        (JumpByte + 1)
 163 /* FP insn memory format bit, sized by 0x4 */
 164 #define FloatMF                 (JumpInterSegment + 1)
 165 /* src/dest swap for floats. */
 166 #define FloatR                  (FloatMF + 1)
 167 /* has float insn direction bit. */
 168 #define FloatD                  (FloatR + 1)
 169 /* needs size prefix if in 32-bit mode */
 170 #define Size16                  (FloatD + 1)
 171 /* needs size prefix if in 16-bit mode */
 172 #define Size32                  (Size16 + 1)
 173 /* needs size prefix if in 64-bit mode */
 174 #define Size64                  (Size32 + 1)
 175 /* instruction ignores operand size prefix and in Intel mode ignores
 176    mnemonic size suffix check.  */
 177 #define IgnoreSize              (Size64 + 1)
 178 /* default insn size depends on mode */
 179 #define DefaultSize             (IgnoreSize + 1)
 180 /* b suffix on instruction illegal */
 181 #define No_bSuf                 (DefaultSize + 1)
 182 /* w suffix on instruction illegal */
 183 #define No_wSuf                 (No_bSuf + 1)
 184 /* l suffix on instruction illegal */
 185 #define No_lSuf                 (No_wSuf + 1)
 186 /* s suffix on instruction illegal */
 187 #define No_sSuf                 (No_lSuf + 1)
 188 /* q suffix on instruction illegal */
 189 #define No_qSuf                 (No_sSuf + 1)
 190 /* long double suffix on instruction illegal */
 191 #define No_ldSuf                (No_qSuf + 1)
 192 /* check memory size on instruction in Intel mode if it is specified.  */
 193 #define CheckSize               (No_ldSuf + 1)
 194 /* BYTE memory on instruction */
 195 #define Byte                    (CheckSize + 1)
 196 /* WORD memory on instruction */
 197 #define Word                    (Byte + 1)
 198 /* DWORD memory on instruction */
 199 #define Dword                   (Word + 1)
 200 /* QWORD memory on instruction */
 201 #define Qword                   (Dword + 1)
 202 /* XMMWORD memory on instruction */
 203 #define Xmmword                 (Qword + 1)
 204 /* instruction needs FWAIT */
 205 #define FWait                   (Xmmword + 1)
 206 /* quick test for string instructions */
 207 #define IsString                (FWait + 1)
 208 /* fake an extra reg operand for clr, imul and special register
 209    processing for some instructions.  */
 210 #define RegKludge               (IsString + 1)
 211 /* The first operand must be xmm0 */
 212 #define FirstXmm0               (RegKludge + 1)
 213 /* BYTE is OK in Intel syntax. */
 214 #define ByteOkIntel             (FirstXmm0 + 1)
 215 /* Convert to DWORD */
 216 #define ToDword                 (ByteOkIntel + 1)
 217 /* Convert to QWORD */
 218 #define ToQword                 (ToDword + 1)
 219 /* Address prefix changes operand 0 */
 220 #define AddrPrefixOp0           (ToQword + 1)
 221 /* opcode is a prefix */
 222 #define IsPrefix                (AddrPrefixOp0 + 1)
 223 /* instruction has extension in 8 bit imm */
 224 #define ImmExt                  (IsPrefix + 1)
 225 /* instruction don't need Rex64 prefix.  */
 226 #define NoRex64                 (ImmExt + 1)
 227 /* instruction require Rex64 prefix.  */
 228 #define Rex64                   (NoRex64 + 1)
 229 /* deprecated fp insn, gets a warning */
 230 #define Ugh                     (Rex64 + 1)
 231 #define Drex                    (Ugh + 1)
 232 /* instruction needs DREX with multiple encodings for memory ops */
 233 #define Drexv                   (Drex + 1)
 234 /* special DREX for comparisons */
 235 #define Drexc                   (Drexv + 1)
 236 /* Compatible with old (<= 2.8.1) versions of gcc  */
 237 #define OldGcc                  (Drexc + 1)
 238 /* AT&T mnemonic.  */
 239 #define ATTMnemonic             (OldGcc + 1)
 240 /* Intel mnemonic.  */
 241 #define IntelMnemonic           (ATTMnemonic + 1)
 242 /* The last bitfield in i386_opcode_modifier.  */
 243 #define Opcode_Modifier_Max     IntelMnemonic
 244
 245 typedef struct i386_opcode_modifier
 246 {
 247   unsigned int d:1;
 248   unsigned int w:1;
 249   unsigned int modrm:1;
 250   unsigned int shortform:1;
 251   unsigned int jump:1;
 252   unsigned int jumpdword:1;
 253   unsigned int jumpbyte:1;
 254   unsigned int jumpintersegment:1;
 255   unsigned int floatmf:1;
 256   unsigned int floatr:1;
 257   unsigned int floatd:1;
 258   unsigned int size16:1;
 259   unsigned int size32:1;
 260   unsigned int size64:1;
 261   unsigned int ignoresize:1;
 262   unsigned int defaultsize:1;
 263   unsigned int no_bsuf:1;
 264   unsigned int no_wsuf:1;
 265   unsigned int no_lsuf:1;
 266   unsigned int no_ssuf:1;
 267   unsigned int no_qsuf:1;
 268   unsigned int no_ldsuf:1;
 269   unsigned int checksize:1;
 270   unsigned int byte:1;
 271   unsigned int word:1;
 272   unsigned int dword:1;
 273   unsigned int qword:1;
 274   unsigned int xmmword:1;
 275   unsigned int fwait:1;
 276   unsigned int isstring:1;
 277   unsigned int regkludge:1;
 278   unsigned int firstxmm0:1;
 279   unsigned int byteokintel:1;
 280   unsigned int todword:1;
 281   unsigned int toqword:1;
 282   unsigned int addrprefixop0:1;
 283   unsigned int isprefix:1;
 284   unsigned int immext:1;
 285   unsigned int norex64:1;
 286   unsigned int rex64:1;
 287   unsigned int ugh:1;
 288   unsigned int drex:1;
 289   unsigned int drexv:1;
 290   unsigned int drexc:1;
 291   unsigned int oldgcc:1;
 292   unsigned int attmnemonic:1;
 293   unsigned int intelmnemonic:1;
 294 } i386_opcode_modifier;
 295
 296 /* Position of operand_type bits.  */
 297
 298 /* Registers  */
 299
 300 /* 8 bit reg */
 301 #define Reg8                    0
 302 /* 16 bit reg */
 303 #define Reg16                   (Reg8 + 1)
 304 /* 32 bit reg */
 305 #define Reg32                   (Reg16 + 1)
 306 /* 64 bit reg */
 307 #define Reg64                   (Reg32 + 1)
 308
 309 /* immediate */
 310
 311 /* 8 bit immediate */
 312 #define Imm8                    (Reg64 + 1)
 313 /* 8 bit immediate sign extended */
 314 #define Imm8S                   (Imm8 + 1)
 315 /* 16 bit immediate */
 316 #define Imm16                   (Imm8S + 1)
 317 /* 32 bit immediate */
 318 #define Imm32                   (Imm16 + 1)
 319 /* 32 bit immediate sign extended */
 320 #define Imm32S                  (Imm32 + 1)
 321 /* 64 bit immediate */
 322 #define Imm64                   (Imm32S + 1)
 323 /* 1 bit immediate */
 324 #define Imm1                    (Imm64 + 1)
 325
 326 /* memory */
 327
 328 #define BaseIndex               (Imm1 + 1)
 329 /* Disp8,16,32 are used in different ways, depending on the
 330    instruction.  For jumps, they specify the size of the PC relative
 331    displacement, for baseindex type instructions, they specify the
 332    size of the offset relative to the base register, and for memory
 333    offset instructions such as `mov 1234,%al' they specify the size of
 334    the offset relative to the segment base.  */
 335 /* 8 bit displacement */
 336 #define Disp8                   (BaseIndex + 1)
 337 /* 16 bit displacement */
 338 #define Disp16                  (Disp8 + 1)
 339 /* 32 bit displacement */
 340 #define Disp32                  (Disp16 + 1)
 341 /* 32 bit signed displacement */
 342 #define Disp32S                 (Disp32 + 1)
 343 /* 64 bit displacement */
 344 #define Disp64                  (Disp32S + 1)
 345
 346 /* specials */
 347
 348 /* register to hold in/out port addr = dx */
 349 #define InOutPortReg            (Disp64 + 1)
 350 /* register to hold shift count = cl */
 351 #define ShiftCount              (InOutPortReg + 1)
 352 /* Control register */
 353 #define Control                 (ShiftCount + 1)
 354 /* Debug register */
 355 #define Debug                   (Control + 1)
 356 /* Test register */
 357 #define Test                    (Debug + 1)
 358 /* Float register */
 359 #define FloatReg                (Test + 1)
 360 /* Float stack top %st(0) */
 361 #define FloatAcc                (FloatReg + 1)
 362 /* 2 bit segment register */
 363 #define SReg2                   (FloatAcc + 1)
 364 /* 3 bit segment register */
 365 #define SReg3                   (SReg2 + 1)
 366 /* Accumulator %al or %ax or %eax */
 367 #define Acc                     (SReg3 + 1)
 368 #define JumpAbsolute            (Acc + 1)
 369 /* MMX register */
 370 #define RegMMX                  (JumpAbsolute + 1)
 371 /* XMM registers in PIII */
 372 #define RegXMM                  (RegMMX + 1)
 373 /* String insn operand with fixed es segment */
 374 #define EsSeg                   (RegXMM + 1)
 375
 376 /* RegMem is for instructions with a modrm byte where the register
 377    destination operand should be encoded in the mod and regmem fields.
 378    Normally, it will be encoded in the reg field. We add a RegMem
 379    flag to the destination register operand to indicate that it should
 380    be encoded in the regmem field.  */
 381 #define RegMem                  (EsSeg + 1)
 382
 383 /* The last bitfield in i386_operand_type.  */
 384 #define OTMax                   RegMem
 385
 386 #define OTNumOfUints \
 387   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 388 #define OTNumOfBits \
 389   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 390
 391 /* If you get a compiler error for zero width of the unused field,
 392    comment it out.  */
 393 #if 0
 394 #define OTUnused                (OTMax + 1)
 395 #endif
 396
 397 typedef union i386_operand_type
 398 {
 399   struct
 400     {
 401       unsigned int reg8:1;
 402       unsigned int reg16:1;
 403       unsigned int reg32:1;
 404       unsigned int reg64:1;
 405       unsigned int imm8:1;
 406       unsigned int imm8s:1;
 407       unsigned int imm16:1;
 408       unsigned int imm32:1;
 409       unsigned int imm32s:1;
 410       unsigned int imm64:1;
 411       unsigned int imm1:1;
 412       unsigned int baseindex:1;
 413       unsigned int disp8:1;
 414       unsigned int disp16:1;
 415       unsigned int disp32:1;
 416       unsigned int disp32s:1;
 417       unsigned int disp64:1;
 418       unsigned int inoutportreg:1;
 419       unsigned int shiftcount:1;
 420       unsigned int control:1;
 421       unsigned int debug:1;
 422       unsigned int test:1;
 423       unsigned int floatreg:1;
 424       unsigned int floatacc:1;
 425       unsigned int sreg2:1;
 426       unsigned int sreg3:1;
 427       unsigned int acc:1;
 428       unsigned int jumpabsolute:1;
 429       unsigned int regmmx:1;
 430       unsigned int regxmm:1;
 431       unsigned int esseg:1;
 432       unsigned int regmem:1;
 433 #ifdef OTUnused
 434       unsigned int unused:(OTNumOfBits - OTUnused);
 435 #endif
 436     } bitfield;
 437   unsigned int array[OTNumOfUints];
 438 } i386_operand_type;
 439
 440 typedef struct template
 441 {
 442   /* instruction name sans width suffix ("mov" for movl insns) */
 443   char *name;
 444
 445   /* how many operands */
 446   unsigned int operands;
 447
 448   /* base_opcode is the fundamental opcode byte without optional
 449      prefix(es).  */
 450   unsigned int base_opcode;
 451 #define Opcode_D        0x2 /* Direction bit:
 452                                set if Reg --> Regmem;
 453                                unset if Regmem --> Reg. */
 454 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 455 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 456
 457   /* extension_opcode is the 3 bit extension for group <n> insns.
 458      This field is also used to store the 8-bit opcode suffix for the
 459      AMD 3DNow! instructions.
 460      If this template has no extension opcode (the usual case) use None
 461      Instructions with Drex use this to specify 2 bits for OC */
 462   unsigned int extension_opcode;
 463 #define None 0xffff             /* If no extension_opcode is possible.  */
 464
 465   /* Opcode length.  */
 466   unsigned char opcode_length;
 467
 468   /* cpu feature flags */
 469   i386_cpu_flags cpu_flags;
 470
 471   /* the bits in opcode_modifier are used to generate the final opcode from
 472      the base_opcode.  These bits also are used to detect alternate forms of
 473      the same instruction */
 474   i386_opcode_modifier opcode_modifier;
 475
 476   /* operand_types[i] describes the type of operand i.  This is made
 477      by OR'ing together all of the possible type masks.  (e.g.
 478      'operand_types[i] = Reg|Imm' specifies that operand i can be
 479      either a register or an immediate operand.  */
 480   i386_operand_type operand_types[MAX_OPERANDS];
 481 }
 482 template;
 483
 484 extern const template i386_optab[];
 485
 486 /* these are for register name --> number & type hash lookup */
 487 typedef struct
 488 {
 489   char *reg_name;
 490   i386_operand_type reg_type;
 491   unsigned int reg_flags;
 492 #define RegRex      0x1  /* Extended register.  */
 493 #define RegRex64    0x2  /* Extended 8 bit register.  */
 494   unsigned int reg_num;
 495 #define RegRip  ((unsigned int ) ~0)
 496 #define RegEip  (RegRip - 1)
 497 /* EIZ and RIZ are fake index registers.  */
 498 #define RegEiz  (RegEip - 1)
 499 #define RegRiz  (RegEiz - 1)
 500 }
 501 reg_entry;
 502
 503 /* Entries in i386_regtab.  */
 504 #define REGNAM_AL 1
 505 #define REGNAM_AX 25
 506 #define REGNAM_EAX 41
 507
 508 extern const reg_entry i386_regtab[];
 509 extern const unsigned int i386_regtab_size;
 510
 511 typedef struct
 512 {
 513   char *seg_name;
 514   unsigned int seg_prefix;
 515 }
 516 seg_entry;
 517
 518 extern const seg_entry cs;
 519 extern const seg_entry ds;
 520 extern const seg_entry ss;
 521 extern const seg_entry es;
 522 extern const seg_entry fs;
 523 extern const seg_entry gs;