opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* CLFLUSH Instuction support required */
  46 #define CpuClflush      (Cpu686 + 1)
  47 /* SYSCALL Instuctions support required */
  48 #define CpuSYSCALL      (CpuClflush + 1)
  49 /* Floating point support required */
  50 #define Cpu8087         (CpuSYSCALL + 1)
  51 /* i287 support required */
  52 #define Cpu287          (Cpu8087 + 1)
  53 /* i387 support required */
  54 #define Cpu387          (Cpu287 + 1)
  55 /* i686 and floating point support required */
  56 #define Cpu687          (Cpu387 + 1)
  57 /* SSE3 and floating point support required */
  58 #define CpuFISTTP               (Cpu687 + 1)
  59 /* MMX support required */
  60 #define CpuMMX          (CpuFISTTP + 1)
  61 /* SSE support required */
  62 #define CpuSSE          (CpuMMX + 1)
  63 /* SSE2 support required */
  64 #define CpuSSE2         (CpuSSE + 1)
  65 /* 3dnow! support required */
  66 #define Cpu3dnow        (CpuSSE2 + 1)
  67 /* 3dnow! Extensions support required */
  68 #define Cpu3dnowA       (Cpu3dnow + 1)
  69 /* SSE3 support required */
  70 #define CpuSSE3         (Cpu3dnowA + 1)
  71 /* VIA PadLock required */
  72 #define CpuPadLock      (CpuSSE3 + 1)
  73 /* AMD Secure Virtual Machine Ext-s required */
  74 #define CpuSVME         (CpuPadLock + 1)
  75 /* VMX Instructions required */
  76 #define CpuVMX          (CpuSVME + 1)
  77 /* SMX Instructions required */
  78 #define CpuSMX          (CpuVMX + 1)
  79 /* SSSE3 support required */
  80 #define CpuSSSE3        (CpuSMX + 1)
  81 /* SSE4a support required */
  82 #define CpuSSE4a        (CpuSSSE3 + 1)
  83 /* ABM New Instructions required */
  84 #define CpuABM          (CpuSSE4a + 1)
  85 /* SSE4.1 support required */
  86 #define CpuSSE4_1       (CpuABM + 1)
  87 /* SSE4.2 support required */
  88 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  89 /* AVX support required */
  90 #define CpuAVX          (CpuSSE4_2 + 1)
  91 /* Xsave/xrstor New Instuctions support required */
  92 #define CpuXsave        (CpuAVX + 1)
  93 /* AES support required */
  94 #define CpuAES          (CpuXsave + 1)
  95 /* PCLMUL support required */
  96 #define CpuPCLMUL       (CpuAES + 1)
  97 /* FMA support required */
  98 #define CpuFMA          (CpuPCLMUL + 1)
  99 /* FMA4 support required */
 100 #define CpuFMA4         (CpuFMA + 1)
 101 /* MOVBE Instuction support required */
 102 #define CpuMovbe        (CpuFMA4 + 1)
 103 /* EPT Instructions required */
 104 #define CpuEPT          (CpuMovbe + 1)
 105 /* RDTSCP Instuction support required */
 106 #define CpuRdtscp       (CpuEPT + 1)
 107 /* 64bit support available, used by -march= in assembler.  */
 108 #define CpuLM           (CpuRdtscp + 1)
 109 /* 64bit support required  */
 110 #define Cpu64           (CpuLM + 1)
 111 /* Not supported in the 64bit mode  */
 112 #define CpuNo64         (Cpu64 + 1)
 113 /* The last bitfield in i386_cpu_flags.  */
 114 #define CpuMax          CpuNo64
 115
 116 #define CpuNumOfUints \
 117   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 118 #define CpuNumOfBits \
 119   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 120
 121 /* If you get a compiler error for zero width of the unused field,
 122    comment it out.  */
 123 #define CpuUnused       (CpuMax + 1)
 124
 125 /* We can check if an instruction is available with array instead
 126    of bitfield. */
 127 typedef union i386_cpu_flags
 128 {
 129   struct
 130     {
 131       unsigned int cpui186:1;
 132       unsigned int cpui286:1;
 133       unsigned int cpui386:1;
 134       unsigned int cpui486:1;
 135       unsigned int cpui586:1;
 136       unsigned int cpui686:1;
 137       unsigned int cpuclflush:1;
 138       unsigned int cpusyscall:1;
 139       unsigned int cpu8087:1;
 140       unsigned int cpu287:1;
 141       unsigned int cpu387:1;
 142       unsigned int cpu687:1;
 143       unsigned int cpufisttp:1;
 144       unsigned int cpummx:1;
 145       unsigned int cpusse:1;
 146       unsigned int cpusse2:1;
 147       unsigned int cpua3dnow:1;
 148       unsigned int cpua3dnowa:1;
 149       unsigned int cpusse3:1;
 150       unsigned int cpupadlock:1;
 151       unsigned int cpusvme:1;
 152       unsigned int cpuvmx:1;
 153       unsigned int cpusmx:1;
 154       unsigned int cpussse3:1;
 155       unsigned int cpusse4a:1;
 156       unsigned int cpuabm:1;
 157       unsigned int cpusse4_1:1;
 158       unsigned int cpusse4_2:1;
 159       unsigned int cpuavx:1;
 160       unsigned int cpuxsave:1;
 161       unsigned int cpuaes:1;
 162       unsigned int cpupclmul:1;
 163       unsigned int cpufma:1;
 164       unsigned int cpufma4:1;
 165       unsigned int cpumovbe:1;
 166       unsigned int cpuept:1;
 167       unsigned int cpurdtscp:1;
 168       unsigned int cpulm:1;
 169       unsigned int cpu64:1;
 170       unsigned int cpuno64:1;
 171 #ifdef CpuUnused
 172       unsigned int unused:(CpuNumOfBits - CpuUnused);
 173 #endif
 174     } bitfield;
 175   unsigned int array[CpuNumOfUints];
 176 } i386_cpu_flags;
 177
 178 /* Position of opcode_modifier bits.  */
 179
 180 /* has direction bit. */
 181 #define D                       0
 182 /* set if operands can be words or dwords encoded the canonical way */
 183 #define W                       (D + 1)
 184 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 185    operand in encoding.  */
 186 #define S                       (W + 1)
 187 /* insn has a modrm byte. */
 188 #define Modrm                   (S + 1)
 189 /* register is in low 3 bits of opcode */
 190 #define ShortForm               (Modrm + 1)
 191 /* special case for jump insns.  */
 192 #define Jump                    (ShortForm + 1)
 193 /* call and jump */
 194 #define JumpDword               (Jump + 1)
 195 /* loop and jecxz */
 196 #define JumpByte                (JumpDword + 1)
 197 /* special case for intersegment leaps/calls */
 198 #define JumpInterSegment        (JumpByte + 1)
 199 /* FP insn memory format bit, sized by 0x4 */
 200 #define FloatMF                 (JumpInterSegment + 1)
 201 /* src/dest swap for floats. */
 202 #define FloatR                  (FloatMF + 1)
 203 /* has float insn direction bit. */
 204 #define FloatD                  (FloatR + 1)
 205 /* needs size prefix if in 32-bit mode */
 206 #define Size16                  (FloatD + 1)
 207 /* needs size prefix if in 16-bit mode */
 208 #define Size32                  (Size16 + 1)
 209 /* needs size prefix if in 64-bit mode */
 210 #define Size64                  (Size32 + 1)
 211 /* instruction ignores operand size prefix and in Intel mode ignores
 212    mnemonic size suffix check.  */
 213 #define IgnoreSize              (Size64 + 1)
 214 /* default insn size depends on mode */
 215 #define DefaultSize             (IgnoreSize + 1)
 216 /* b suffix on instruction illegal */
 217 #define No_bSuf                 (DefaultSize + 1)
 218 /* w suffix on instruction illegal */
 219 #define No_wSuf                 (No_bSuf + 1)
 220 /* l suffix on instruction illegal */
 221 #define No_lSuf                 (No_wSuf + 1)
 222 /* s suffix on instruction illegal */
 223 #define No_sSuf                 (No_lSuf + 1)
 224 /* q suffix on instruction illegal */
 225 #define No_qSuf                 (No_sSuf + 1)
 226 /* long double suffix on instruction illegal */
 227 #define No_ldSuf                (No_qSuf + 1)
 228 /* instruction needs FWAIT */
 229 #define FWait                   (No_ldSuf + 1)
 230 /* quick test for string instructions */
 231 #define IsString                (FWait + 1)
 232 /* fake an extra reg operand for clr, imul and special register
 233    processing for some instructions.  */
 234 #define RegKludge               (IsString + 1)
 235 /* The first operand must be xmm0 */
 236 #define FirstXmm0               (RegKludge + 1)
 237 /* An implicit xmm0 as the first operand */
 238 #define Implicit1stXmm0         (FirstXmm0 + 1)
 239 /* BYTE is OK in Intel syntax. */
 240 #define ByteOkIntel             (Implicit1stXmm0 + 1)
 241 /* Convert to DWORD */
 242 #define ToDword                 (ByteOkIntel + 1)
 243 /* Convert to QWORD */
 244 #define ToQword                 (ToDword + 1)
 245 /* Address prefix changes operand 0 */
 246 #define AddrPrefixOp0           (ToQword + 1)
 247 /* opcode is a prefix */
 248 #define IsPrefix                (AddrPrefixOp0 + 1)
 249 /* instruction has extension in 8 bit imm */
 250 #define ImmExt                  (IsPrefix + 1)
 251 /* instruction don't need Rex64 prefix.  */
 252 #define NoRex64                 (ImmExt + 1)
 253 /* instruction require Rex64 prefix.  */
 254 #define Rex64                   (NoRex64 + 1)
 255 /* deprecated fp insn, gets a warning */
 256 #define Ugh                     (Rex64 + 1)
 257 /* insn has VEX prefix. */
 258 #define Vex                     (Ugh + 1)
 259 /* insn has 256bit VEX prefix. */
 260 #define Vex256                  (Vex + 1)
 261 /* insn has VEX NDS. Register-only source is encoded in Vex prefix.
 262    We use VexNDS on insns with VEX DDS since the register-only source
 263    is the second source register.  */
 264 #define VexNDS                  (Vex256 + 1)
 265 /* insn has VEX NDD. Register destination is encoded in Vex
 266    prefix. */
 267 #define VexNDD                  (VexNDS + 1)
 268 /* insn has VEX W0. */
 269 #define VexW0                   (VexNDD + 1)
 270 /* insn has VEX W1. */
 271 #define VexW1                   (VexW0 + 1)
 272 /* insn has VEX 0x0F opcode prefix. */
 273 #define Vex0F                   (VexW1 + 1)
 274 /* insn has VEX 0x0F38 opcode prefix. */
 275 #define Vex0F38                 (Vex0F + 1)
 276 /* insn has VEX 0x0F3A opcode prefix. */
 277 #define Vex0F3A                 (Vex0F38 + 1)
 278 /* insn has VEX prefix with 3 soures. */
 279 #define Vex3Sources             (Vex0F3A + 1)
 280 /* instruction has VEX 8 bit imm */
 281 #define VexImmExt               (Vex3Sources + 1)
 282 /* SSE to AVX support required */
 283 #define SSE2AVX                 (VexImmExt + 1)
 284 /* No AVX equivalent */
 285 #define NoAVX                   (SSE2AVX + 1)
 286 /* Compatible with old (<= 2.8.1) versions of gcc  */
 287 #define OldGcc                  (NoAVX + 1)
 288 /* AT&T mnemonic.  */
 289 #define ATTMnemonic             (OldGcc + 1)
 290 /* AT&T syntax.  */
 291 #define ATTSyntax               (ATTMnemonic + 1)
 292 /* Intel syntax.  */
 293 #define IntelSyntax             (ATTSyntax + 1)
 294 /* The last bitfield in i386_opcode_modifier.  */
 295 #define Opcode_Modifier_Max     IntelSyntax
 296
 297 typedef struct i386_opcode_modifier
 298 {
 299   unsigned int d:1;
 300   unsigned int w:1;
 301   unsigned int s:1;
 302   unsigned int modrm:1;
 303   unsigned int shortform:1;
 304   unsigned int jump:1;
 305   unsigned int jumpdword:1;
 306   unsigned int jumpbyte:1;
 307   unsigned int jumpintersegment:1;
 308   unsigned int floatmf:1;
 309   unsigned int floatr:1;
 310   unsigned int floatd:1;
 311   unsigned int size16:1;
 312   unsigned int size32:1;
 313   unsigned int size64:1;
 314   unsigned int ignoresize:1;
 315   unsigned int defaultsize:1;
 316   unsigned int no_bsuf:1;
 317   unsigned int no_wsuf:1;
 318   unsigned int no_lsuf:1;
 319   unsigned int no_ssuf:1;
 320   unsigned int no_qsuf:1;
 321   unsigned int no_ldsuf:1;
 322   unsigned int fwait:1;
 323   unsigned int isstring:1;
 324   unsigned int regkludge:1;
 325   unsigned int firstxmm0:1;
 326   unsigned int implicit1stxmm0:1;
 327   unsigned int byteokintel:1;
 328   unsigned int todword:1;
 329   unsigned int toqword:1;
 330   unsigned int addrprefixop0:1;
 331   unsigned int isprefix:1;
 332   unsigned int immext:1;
 333   unsigned int norex64:1;
 334   unsigned int rex64:1;
 335   unsigned int ugh:1;
 336   unsigned int vex:1;
 337   unsigned int vex256:1;
 338   unsigned int vexnds:1;
 339   unsigned int vexndd:1;
 340   unsigned int vexw0:1;
 341   unsigned int vexw1:1;
 342   unsigned int vex0f:1;
 343   unsigned int vex0f38:1;
 344   unsigned int vex0f3a:1;
 345   unsigned int vex3sources:1;
 346   unsigned int veximmext:1;
 347   unsigned int sse2avx:1;
 348   unsigned int noavx:1;
 349   unsigned int oldgcc:1;
 350   unsigned int attmnemonic:1;
 351   unsigned int attsyntax:1;
 352   unsigned int intelsyntax:1;
 353 } i386_opcode_modifier;
 354
 355 /* Position of operand_type bits.  */
 356
 357 /* 8bit register */
 358 #define Reg8                    0
 359 /* 16bit register */
 360 #define Reg16                   (Reg8 + 1)
 361 /* 32bit register */
 362 #define Reg32                   (Reg16 + 1)
 363 /* 64bit register */
 364 #define Reg64                   (Reg32 + 1)
 365 /* Floating pointer stack register */
 366 #define FloatReg                (Reg64 + 1)
 367 /* MMX register */
 368 #define RegMMX                  (FloatReg + 1)
 369 /* SSE register */
 370 #define RegXMM                  (RegMMX + 1)
 371 /* AVX registers */
 372 #define RegYMM                  (RegXMM + 1)
 373 /* Control register */
 374 #define Control                 (RegYMM + 1)
 375 /* Debug register */
 376 #define Debug                   (Control + 1)
 377 /* Test register */
 378 #define Test                    (Debug + 1)
 379 /* 2 bit segment register */
 380 #define SReg2                   (Test + 1)
 381 /* 3 bit segment register */
 382 #define SReg3                   (SReg2 + 1)
 383 /* 1 bit immediate */
 384 #define Imm1                    (SReg3 + 1)
 385 /* 8 bit immediate */
 386 #define Imm8                    (Imm1 + 1)
 387 /* 8 bit immediate sign extended */
 388 #define Imm8S                   (Imm8 + 1)
 389 /* 16 bit immediate */
 390 #define Imm16                   (Imm8S + 1)
 391 /* 32 bit immediate */
 392 #define Imm32                   (Imm16 + 1)
 393 /* 32 bit immediate sign extended */
 394 #define Imm32S                  (Imm32 + 1)
 395 /* 64 bit immediate */
 396 #define Imm64                   (Imm32S + 1)
 397 /* 8bit/16bit/32bit displacements are used in different ways,
 398    depending on the instruction.  For jumps, they specify the
 399    size of the PC relative displacement, for instructions with
 400    memory operand, they specify the size of the offset relative
 401    to the base register, and for instructions with memory offset
 402    such as `mov 1234,%al' they specify the size of the offset
 403    relative to the segment base.  */
 404 /* 8 bit displacement */
 405 #define Disp8                   (Imm64 + 1)
 406 /* 16 bit displacement */
 407 #define Disp16                  (Disp8 + 1)
 408 /* 32 bit displacement */
 409 #define Disp32                  (Disp16 + 1)
 410 /* 32 bit signed displacement */
 411 #define Disp32S                 (Disp32 + 1)
 412 /* 64 bit displacement */
 413 #define Disp64                  (Disp32S + 1)
 414 /* Accumulator %al/%ax/%eax/%rax */
 415 #define Acc                     (Disp64 + 1)
 416 /* Floating pointer top stack register %st(0) */
 417 #define FloatAcc                (Acc + 1)
 418 /* Register which can be used for base or index in memory operand.  */
 419 #define BaseIndex               (FloatAcc + 1)
 420 /* Register to hold in/out port addr = dx */
 421 #define InOutPortReg            (BaseIndex + 1)
 422 /* Register to hold shift count = cl */
 423 #define ShiftCount              (InOutPortReg + 1)
 424 /* Absolute address for jump.  */
 425 #define JumpAbsolute            (ShiftCount + 1)
 426 /* String insn operand with fixed es segment */
 427 #define EsSeg                   (JumpAbsolute + 1)
 428 /* RegMem is for instructions with a modrm byte where the register
 429    destination operand should be encoded in the mod and regmem fields.
 430    Normally, it will be encoded in the reg field. We add a RegMem
 431    flag to the destination register operand to indicate that it should
 432    be encoded in the regmem field.  */
 433 #define RegMem                  (EsSeg + 1)
 434 /* Memory.  */
 435 #define Mem                     (RegMem + 1)
 436 /* BYTE memory. */
 437 #define Byte                    (Mem + 1)
 438 /* WORD memory. 2 byte */
 439 #define Word                    (Byte + 1)
 440 /* DWORD memory. 4 byte */
 441 #define Dword                   (Word + 1)
 442 /* FWORD memory. 6 byte */
 443 #define Fword                   (Dword + 1)
 444 /* QWORD memory. 8 byte */
 445 #define Qword                   (Fword + 1)
 446 /* TBYTE memory. 10 byte */
 447 #define Tbyte                   (Qword + 1)
 448 /* XMMWORD memory. */
 449 #define Xmmword                 (Tbyte + 1)
 450 /* YMMWORD memory. */
 451 #define Ymmword                 (Xmmword + 1)
 452 /* Unspecified memory size.  */
 453 #define Unspecified             (Ymmword + 1)
 454 /* Any memory size.  */
 455 #define Anysize                 (Unspecified  + 1)
 456
 457 /* The last bitfield in i386_operand_type.  */
 458 #define OTMax                   Anysize
 459
 460 #define OTNumOfUints \
 461   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 462 #define OTNumOfBits \
 463   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 464
 465 /* If you get a compiler error for zero width of the unused field,
 466    comment it out.  */
 467 #define OTUnused                (OTMax + 1)
 468
 469 typedef union i386_operand_type
 470 {
 471   struct
 472     {
 473       unsigned int reg8:1;
 474       unsigned int reg16:1;
 475       unsigned int reg32:1;
 476       unsigned int reg64:1;
 477       unsigned int floatreg:1;
 478       unsigned int regmmx:1;
 479       unsigned int regxmm:1;
 480       unsigned int regymm:1;
 481       unsigned int control:1;
 482       unsigned int debug:1;
 483       unsigned int test:1;
 484       unsigned int sreg2:1;
 485       unsigned int sreg3:1;
 486       unsigned int imm1:1;
 487       unsigned int imm8:1;
 488       unsigned int imm8s:1;
 489       unsigned int imm16:1;
 490       unsigned int imm32:1;
 491       unsigned int imm32s:1;
 492       unsigned int imm64:1;
 493       unsigned int disp8:1;
 494       unsigned int disp16:1;
 495       unsigned int disp32:1;
 496       unsigned int disp32s:1;
 497       unsigned int disp64:1;
 498       unsigned int acc:1;
 499       unsigned int floatacc:1;
 500       unsigned int baseindex:1;
 501       unsigned int inoutportreg:1;
 502       unsigned int shiftcount:1;
 503       unsigned int jumpabsolute:1;
 504       unsigned int esseg:1;
 505       unsigned int regmem:1;
 506       unsigned int mem:1;
 507       unsigned int byte:1;
 508       unsigned int word:1;
 509       unsigned int dword:1;
 510       unsigned int fword:1;
 511       unsigned int qword:1;
 512       unsigned int tbyte:1;
 513       unsigned int xmmword:1;
 514       unsigned int ymmword:1;
 515       unsigned int unspecified:1;
 516       unsigned int anysize:1;
 517 #ifdef OTUnused
 518       unsigned int unused:(OTNumOfBits - OTUnused);
 519 #endif
 520     } bitfield;
 521   unsigned int array[OTNumOfUints];
 522 } i386_operand_type;
 523
 524 typedef struct template
 525 {
 526   /* instruction name sans width suffix ("mov" for movl insns) */
 527   char *name;
 528
 529   /* how many operands */
 530   unsigned int operands;
 531
 532   /* base_opcode is the fundamental opcode byte without optional
 533      prefix(es).  */
 534   unsigned int base_opcode;
 535 #define Opcode_D        0x2 /* Direction bit:
 536                                set if Reg --> Regmem;
 537                                unset if Regmem --> Reg. */
 538 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 539 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 540
 541   /* extension_opcode is the 3 bit extension for group <n> insns.
 542      This field is also used to store the 8-bit opcode suffix for the
 543      AMD 3DNow! instructions.
 544      If this template has no extension opcode (the usual case) use None
 545      Instructions */
 546   unsigned int extension_opcode;
 547 #define None 0xffff             /* If no extension_opcode is possible.  */
 548
 549   /* Opcode length.  */
 550   unsigned char opcode_length;
 551
 552   /* cpu feature flags */
 553   i386_cpu_flags cpu_flags;
 554
 555   /* the bits in opcode_modifier are used to generate the final opcode from
 556      the base_opcode.  These bits also are used to detect alternate forms of
 557      the same instruction */
 558   i386_opcode_modifier opcode_modifier;
 559
 560   /* operand_types[i] describes the type of operand i.  This is made
 561      by OR'ing together all of the possible type masks.  (e.g.
 562      'operand_types[i] = Reg|Imm' specifies that operand i can be
 563      either a register or an immediate operand.  */
 564   i386_operand_type operand_types[MAX_OPERANDS];
 565 }
 566 template;
 567
 568 extern const template i386_optab[];
 569
 570 /* these are for register name --> number & type hash lookup */
 571 typedef struct
 572 {
 573   char *reg_name;
 574   i386_operand_type reg_type;
 575   unsigned char reg_flags;
 576 #define RegRex      0x1  /* Extended register.  */
 577 #define RegRex64    0x2  /* Extended 8 bit register.  */
 578   unsigned char reg_num;
 579 #define RegRip  ((unsigned char ) ~0)
 580 #define RegEip  (RegRip - 1)
 581 /* EIZ and RIZ are fake index registers.  */
 582 #define RegEiz  (RegEip - 1)
 583 #define RegRiz  (RegEiz - 1)
 584 /* FLAT is a fake segment register (Intel mode).  */
 585 #define RegFlat     ((unsigned char) ~0)
 586   signed char dw2_regnum[2];
 587 #define Dw2Inval (-1)
 588 }
 589 reg_entry;
 590
 591 /* Entries in i386_regtab.  */
 592 #define REGNAM_AL 1
 593 #define REGNAM_AX 25
 594 #define REGNAM_EAX 41
 595
 596 extern const reg_entry i386_regtab[];
 597 extern const unsigned int i386_regtab_size;
 598
 599 typedef struct
 600 {
 601   char *seg_name;
 602   unsigned int seg_prefix;
 603 }
 604 seg_entry;
 605
 606 extern const seg_entry cs;
 607 extern const seg_entry ds;
 608 extern const seg_entry ss;
 609 extern const seg_entry es;
 610 extern const seg_entry fs;
 611 extern const seg_entry gs;