1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static void set_code_flag (int);
66 static void set_16bit_gcc_code_flag (int);
67 static void set_intel_syntax (int);
68 static void set_cpu_arch (int);
70 static void pe_directive_secrel (int);
72 static void signed_cons (int);
73 static char *output_invalid (int c
);
74 static int i386_operand (char *);
75 static int i386_intel_operand (char *, int);
76 static const reg_entry
*parse_register (char *, char **);
77 static char *parse_insn (char *, char *);
78 static char *parse_operands (char *, const char *);
79 static void swap_operands (void);
80 static void swap_2_operands (int, int);
81 static void optimize_imm (void);
82 static void optimize_disp (void);
83 static int match_template (void);
84 static int check_string (void);
85 static int process_suffix (void);
86 static int check_byte_reg (void);
87 static int check_long_reg (void);
88 static int check_qword_reg (void);
89 static int check_word_reg (void);
90 static int finalize_imm (void);
91 static int process_operands (void);
92 static const seg_entry
*build_modrm_byte (void);
93 static void output_insn (void);
94 static void output_imm (fragS
*, offsetT
);
95 static void output_disp (fragS
*, offsetT
);
97 static void s_bss (int);
99 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
103 static const char *default_arch
= DEFAULT_ARCH
;
105 /* 'md_assemble ()' gathers together information and puts it into a
112 const reg_entry
*regs
;
117 /* TM holds the template for the insn were currently assembling. */
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
124 /* OPERANDS gives the number of given operands. */
125 unsigned int operands
;
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
130 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
132 /* TYPES [i] is the type (see above #defines) which tells us how to
133 use OP[i] for the corresponding operand. */
134 unsigned int types
[MAX_OPERANDS
];
136 /* Displacement expression, immediate expression, or register for each
138 union i386_op op
[MAX_OPERANDS
];
140 /* Flags for operands. */
141 unsigned int flags
[MAX_OPERANDS
];
142 #define Operand_PCrel 1
144 /* Relocation type for operand */
145 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry
*base_reg
;
150 const reg_entry
*index_reg
;
151 unsigned int log2_scale_factor
;
153 /* SEG gives the seg_entries of this insn. They are zero unless
154 explicit segment overrides are given. */
155 const seg_entry
*seg
[2];
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes
;
160 unsigned char prefix
[MAX_PREFIXES
];
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
170 typedef struct _i386_insn i386_insn
;
172 /* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
174 const char extra_symbol_chars
[] = "*%-(["
183 #if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
185 && !defined (TE_GNU) \
186 && !defined (TE_LINUX) \
187 && !defined (TE_NETWARE) \
188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
190 /* This array holds the chars that always start a comment. If the
191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193 const char *i386_comment_chars
= "#/";
194 #define SVR4_COMMENT_CHARS 1
195 #define PREFIX_SEPARATOR '\\'
198 const char *i386_comment_chars
= "#";
199 #define PREFIX_SEPARATOR '/'
202 /* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
206 first line of the input file. This is because the compiler outputs
207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
209 '/' isn't otherwise defined. */
210 const char line_comment_chars
[] = "#/";
212 const char line_separator_chars
[] = ";";
214 /* Chars that can be used to separate mant from exp in floating point
216 const char EXP_CHARS
[] = "eE";
218 /* Chars that mean this number is a floating point constant
221 const char FLT_CHARS
[] = "fFdDxX";
223 /* Tables for lexical analysis. */
224 static char mnemonic_chars
[256];
225 static char register_chars
[256];
226 static char operand_chars
[256];
227 static char identifier_chars
[256];
228 static char digit_chars
[256];
230 /* Lexical macros. */
231 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232 #define is_operand_char(x) (operand_chars[(unsigned char) x])
233 #define is_register_char(x) (register_chars[(unsigned char) x])
234 #define is_space_char(x) ((x) == ' ')
235 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236 #define is_digit_char(x) (digit_chars[(unsigned char) x])
238 /* All non-digit non-letter characters that may occur in an operand. */
239 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
241 /* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
244 assembler instruction). */
245 static char save_stack
[32];
246 static char *save_stack_p
;
247 #define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249 #define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
252 /* The instruction we're assembling. */
255 /* Possible templates for current insn. */
256 static const templates
*current_templates
;
258 /* Per instruction expressionS buffers: max displacements & immediates. */
259 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
260 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
262 /* Current operand we are working on. */
263 static int this_operand
;
265 /* We support four different modes. FLAG_CODE variable is used to distinguish
272 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
274 static enum flag_code flag_code
;
275 static unsigned int object_64bit
;
276 static int use_rela_relocations
= 0;
278 /* The names used to print error messages. */
279 static const char *flag_code_names
[] =
286 /* 1 for intel syntax,
288 static int intel_syntax
= 0;
290 /* 1 if register prefix % not required. */
291 static int allow_naked_reg
= 0;
293 /* Register prefix used for error message. */
294 static const char *register_prefix
= "%";
296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299 static char stackop_size
= '\0';
301 /* Non-zero to optimize code alignment. */
302 int optimize_align_code
= 1;
304 /* Non-zero to quieten some warnings. */
305 static int quiet_warnings
= 0;
308 static const char *cpu_arch_name
= NULL
;
309 static const char *cpu_sub_arch_name
= NULL
;
311 /* CPU feature flags. */
312 static unsigned int cpu_arch_flags
= CpuUnknownFlags
| CpuNo64
;
314 /* If we have selected a cpu we are generating instructions for. */
315 static int cpu_arch_tune_set
= 0;
317 /* Cpu we are generating instructions for. */
318 static enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
320 /* CPU feature flags of cpu we are generating instructions for. */
321 static unsigned int cpu_arch_tune_flags
= 0;
323 /* CPU instruction set architecture used. */
324 static enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
326 /* CPU feature flags of instruction set architecture used. */
327 static unsigned int cpu_arch_isa_flags
= 0;
329 /* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331 static unsigned int no_cond_jump_promotion
= 0;
333 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
334 static symbolS
*GOT_symbol
;
336 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
337 unsigned int x86_dwarf2_return_column
;
339 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340 int x86_cie_data_alignment
;
342 /* Interface to relax_segment.
343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
348 #define UNCOND_JUMP 0
350 #define COND_JUMP86 2
355 #define SMALL16 (SMALL | CODE16)
357 #define BIG16 (BIG | CODE16)
361 #define INLINE __inline__
367 #define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369 #define TYPE_FROM_RELAX_STATE(s) \
371 #define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
374 /* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
382 const relax_typeS md_relax_table
[] =
385 1) most positive reach of this state,
386 2) most negative reach of this state,
387 3) how many bytes this mode will have in the variable part of the frag
388 4) which index into the table to try if we can't fit into this one. */
390 /* UNCOND_JUMP states. */
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
406 /* word conditionals add 3 bytes to frag:
407 1 extra opcode byte, 2 displacement bytes. */
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
421 static const arch_entry cpu_arch
[] =
423 {"generic32", PROCESSOR_GENERIC32
,
424 Cpu186
|Cpu286
|Cpu386
},
425 {"generic64", PROCESSOR_GENERIC64
,
426 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
427 |CpuMMX2
|CpuSSE
|CpuSSE2
},
428 {"i8086", PROCESSOR_UNKNOWN
,
430 {"i186", PROCESSOR_UNKNOWN
,
432 {"i286", PROCESSOR_UNKNOWN
,
434 {"i386", PROCESSOR_I386
,
435 Cpu186
|Cpu286
|Cpu386
},
436 {"i486", PROCESSOR_I486
,
437 Cpu186
|Cpu286
|Cpu386
|Cpu486
},
438 {"i586", PROCESSOR_PENTIUM
,
439 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
440 {"i686", PROCESSOR_PENTIUMPRO
,
441 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
442 {"pentium", PROCESSOR_PENTIUM
,
443 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
},
444 {"pentiumpro",PROCESSOR_PENTIUMPRO
,
445 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
},
446 {"pentiumii", PROCESSOR_PENTIUMPRO
,
447 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
},
448 {"pentiumiii",PROCESSOR_PENTIUMPRO
,
449 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuMMX2
|CpuSSE
},
450 {"pentium4", PROCESSOR_PENTIUM4
,
451 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
452 |CpuMMX2
|CpuSSE
|CpuSSE2
},
453 {"prescott", PROCESSOR_NOCONA
,
454 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
455 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
456 {"nocona", PROCESSOR_NOCONA
,
457 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
458 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
459 {"yonah", PROCESSOR_CORE
,
460 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
461 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
462 {"core", PROCESSOR_CORE
,
463 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
464 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
465 {"merom", PROCESSOR_CORE2
,
466 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
467 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
468 {"core2", PROCESSOR_CORE2
,
469 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
470 |CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
472 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
},
473 {"k6_2", PROCESSOR_K6
,
474 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
475 {"athlon", PROCESSOR_ATHLON
,
476 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
477 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
478 {"sledgehammer", PROCESSOR_K8
,
479 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
480 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
481 {"opteron", PROCESSOR_K8
,
482 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
483 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
485 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
486 |CpuSledgehammer
|CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
},
487 {"amdfam10", PROCESSOR_AMDFAM10
,
488 Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuSledgehammer
489 |CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
491 {".mmx", PROCESSOR_UNKNOWN
,
493 {".sse", PROCESSOR_UNKNOWN
,
494 CpuMMX
|CpuMMX2
|CpuSSE
},
495 {".sse2", PROCESSOR_UNKNOWN
,
496 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
},
497 {".sse3", PROCESSOR_UNKNOWN
,
498 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
},
499 {".ssse3", PROCESSOR_UNKNOWN
,
500 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
},
501 {".sse4.1", PROCESSOR_UNKNOWN
,
502 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4_1
},
503 {".sse4.2", PROCESSOR_UNKNOWN
,
504 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4
},
505 {".sse4", PROCESSOR_UNKNOWN
,
506 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSSE3
|CpuSSE4
},
507 {".3dnow", PROCESSOR_UNKNOWN
,
509 {".3dnowa", PROCESSOR_UNKNOWN
,
510 CpuMMX
|CpuMMX2
|Cpu3dnow
|Cpu3dnowA
},
511 {".padlock", PROCESSOR_UNKNOWN
,
513 {".pacifica", PROCESSOR_UNKNOWN
,
515 {".svme", PROCESSOR_UNKNOWN
,
517 {".sse4a", PROCESSOR_UNKNOWN
,
518 CpuMMX
|CpuMMX2
|CpuSSE
|CpuSSE2
|CpuSSE3
|CpuSSE4a
},
519 {".abm", PROCESSOR_UNKNOWN
,
523 const pseudo_typeS md_pseudo_table
[] =
525 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes
, 0},
528 {"align", s_align_ptwo
, 0},
530 {"arch", set_cpu_arch
, 0},
534 {"ffloat", float_cons
, 'f'},
535 {"dfloat", float_cons
, 'd'},
536 {"tfloat", float_cons
, 'x'},
538 {"slong", signed_cons
, 4},
539 {"noopt", s_ignore
, 0},
540 {"optim", s_ignore
, 0},
541 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
542 {"code16", set_code_flag
, CODE_16BIT
},
543 {"code32", set_code_flag
, CODE_32BIT
},
544 {"code64", set_code_flag
, CODE_64BIT
},
545 {"intel_syntax", set_intel_syntax
, 1},
546 {"att_syntax", set_intel_syntax
, 0},
547 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common
, 0},
550 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
551 {"loc", dwarf2_directive_loc
, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
555 {"secrel32", pe_directive_secrel
, 0},
560 /* For interface with expression (). */
561 extern char *input_line_pointer
;
563 /* Hash table for instruction mnemonic lookup. */
564 static struct hash_control
*op_hash
;
566 /* Hash table for register lookup. */
567 static struct hash_control
*reg_hash
;
570 i386_align_code (fragS
*fragP
, int count
)
572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
575 static const char f32_1
[] =
577 static const char f32_2
[] =
578 {0x66,0x90}; /* xchg %ax,%ax */
579 static const char f32_3
[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4
[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5
[] =
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6
[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7
[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8
[] =
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9
[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10
[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11
[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12
[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13
[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14
[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f16_3
[] =
612 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
613 static const char f16_4
[] =
614 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
615 static const char f16_5
[] =
617 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_6
[] =
619 {0x89,0xf6, /* mov %si,%si */
620 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
621 static const char f16_7
[] =
622 {0x8d,0x74,0x00, /* lea 0(%si),%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_8
[] =
625 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
627 static const char jump_31
[] =
628 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
631 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
632 static const char *const f32_patt
[] = {
633 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
634 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
636 static const char *const f16_patt
[] = {
637 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
640 static const char alt_3
[] =
642 /* nopl 0(%[re]ax) */
643 static const char alt_4
[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5
[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6
[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7
[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8
[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9
[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10
[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11
[] =
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12
[] =
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13
[] =
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14
[] =
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15
[] =
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11
[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12
[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
720 static const char alt_short_13
[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
725 static const char alt_short_14
[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15
[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt
[] = {
734 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
735 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
736 alt_short_14
, alt_short_15
738 static const char *const alt_long_patt
[] = {
739 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
740 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
741 alt_long_14
, alt_long_15
744 /* Only align for at least a positive non-zero boundary. */
745 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
748 /* We need to decide which NOP sequence to use for 32bit and
749 64bit. When -mtune= is used:
751 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
752 PROCESSOR_GENERIC32, f32_patt will be used.
753 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
754 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
755 alt_long_patt will be used.
756 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
757 PROCESSOR_AMDFAM10, alt_short_patt will be used.
759 When -mtune= isn't used, alt_long_patt will be used if
760 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
763 When -march= or .arch is used, we can't use anything beyond
764 cpu_arch_isa_flags. */
766 if (flag_code
== CODE_16BIT
)
770 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
772 /* Adjust jump offset. */
773 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
776 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
777 f16_patt
[count
- 1], count
);
781 const char *const *patt
= NULL
;
783 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
785 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
786 switch (cpu_arch_tune
)
788 case PROCESSOR_UNKNOWN
:
789 /* We use cpu_arch_isa_flags to check if we SHOULD
790 optimize for Cpu686. */
791 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
792 patt
= alt_long_patt
;
796 case PROCESSOR_PENTIUMPRO
:
797 case PROCESSOR_PENTIUM4
:
798 case PROCESSOR_NOCONA
:
800 case PROCESSOR_CORE2
:
801 case PROCESSOR_GENERIC64
:
802 patt
= alt_long_patt
;
805 case PROCESSOR_ATHLON
:
807 case PROCESSOR_AMDFAM10
:
808 patt
= alt_short_patt
;
812 case PROCESSOR_PENTIUM
:
813 case PROCESSOR_GENERIC32
:
820 switch (cpu_arch_tune
)
822 case PROCESSOR_UNKNOWN
:
823 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
824 PROCESSOR_UNKNOWN. */
830 case PROCESSOR_PENTIUM
:
832 case PROCESSOR_ATHLON
:
834 case PROCESSOR_AMDFAM10
:
835 case PROCESSOR_GENERIC32
:
836 /* We use cpu_arch_isa_flags to check if we CAN optimize
838 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
839 patt
= alt_short_patt
;
843 case PROCESSOR_PENTIUMPRO
:
844 case PROCESSOR_PENTIUM4
:
845 case PROCESSOR_NOCONA
:
847 case PROCESSOR_CORE2
:
848 if ((cpu_arch_isa_flags
& Cpu686
) != 0)
849 patt
= alt_long_patt
;
853 case PROCESSOR_GENERIC64
:
854 patt
= alt_long_patt
;
859 if (patt
== f32_patt
)
861 /* If the padding is less than 15 bytes, we use the normal
862 ones. Otherwise, we use a jump instruction and adjust
865 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
866 patt
[count
- 1], count
);
869 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
871 /* Adjust jump offset. */
872 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
877 /* Maximum length of an instruction is 15 byte. If the
878 padding is greater than 15 bytes and we don't use jump,
879 we have to break it into smaller pieces. */
884 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
889 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
890 patt
[padding
- 1], padding
);
893 fragP
->fr_var
= count
;
896 static INLINE
unsigned int
897 mode_from_disp_size (unsigned int t
)
899 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
903 fits_in_signed_byte (offsetT num
)
905 return (num
>= -128) && (num
<= 127);
909 fits_in_unsigned_byte (offsetT num
)
911 return (num
& 0xff) == num
;
915 fits_in_unsigned_word (offsetT num
)
917 return (num
& 0xffff) == num
;
921 fits_in_signed_word (offsetT num
)
923 return (-32768 <= num
) && (num
<= 32767);
927 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
932 return (!(((offsetT
) -1 << 31) & num
)
933 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
935 } /* fits_in_signed_long() */
938 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
943 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
945 } /* fits_in_unsigned_long() */
948 smallest_imm_type (offsetT num
)
950 if (cpu_arch_flags
!= (Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
))
952 /* This code is disabled on the 486 because all the Imm1 forms
953 in the opcode table are slower on the i486. They're the
954 versions with the implicitly specified single-position
955 displacement, which has another syntax if you really want to
958 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
960 return (fits_in_signed_byte (num
)
961 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
962 : fits_in_unsigned_byte (num
)
963 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
964 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
965 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
966 : fits_in_signed_long (num
)
967 ? (Imm32
| Imm32S
| Imm64
)
968 : fits_in_unsigned_long (num
)
974 offset_in_range (offsetT val
, int size
)
980 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
981 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
982 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
984 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
989 /* If BFD64, sign extend val. */
990 if (!use_rela_relocations
)
991 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
992 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
994 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
996 char buf1
[40], buf2
[40];
998 sprint_value (buf1
, val
);
999 sprint_value (buf2
, val
& mask
);
1000 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1005 /* Returns 0 if attempting to add a prefix where one from the same
1006 class already exists, 1 if non rep/repne added, 2 if rep/repne
1009 add_prefix (unsigned int prefix
)
1014 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1015 && flag_code
== CODE_64BIT
)
1017 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1018 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1019 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1030 case CS_PREFIX_OPCODE
:
1031 case DS_PREFIX_OPCODE
:
1032 case ES_PREFIX_OPCODE
:
1033 case FS_PREFIX_OPCODE
:
1034 case GS_PREFIX_OPCODE
:
1035 case SS_PREFIX_OPCODE
:
1039 case REPNE_PREFIX_OPCODE
:
1040 case REPE_PREFIX_OPCODE
:
1043 case LOCK_PREFIX_OPCODE
:
1051 case ADDR_PREFIX_OPCODE
:
1055 case DATA_PREFIX_OPCODE
:
1059 if (i
.prefix
[q
] != 0)
1067 i
.prefix
[q
] |= prefix
;
1070 as_bad (_("same type of prefix used twice"));
1076 set_code_flag (int value
)
1079 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1080 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1081 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
1083 as_bad (_("64bit mode not supported on this CPU."));
1085 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
1087 as_bad (_("32bit mode not supported on this CPU."));
1089 stackop_size
= '\0';
1093 set_16bit_gcc_code_flag (int new_code_flag
)
1095 flag_code
= new_code_flag
;
1096 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
1097 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
1098 stackop_size
= LONG_MNEM_SUFFIX
;
1102 set_intel_syntax (int syntax_flag
)
1104 /* Find out if register prefixing is specified. */
1105 int ask_naked_reg
= 0;
1108 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1110 char *string
= input_line_pointer
;
1111 int e
= get_symbol_end ();
1113 if (strcmp (string
, "prefix") == 0)
1115 else if (strcmp (string
, "noprefix") == 0)
1118 as_bad (_("bad argument to syntax directive."));
1119 *input_line_pointer
= e
;
1121 demand_empty_rest_of_line ();
1123 intel_syntax
= syntax_flag
;
1125 if (ask_naked_reg
== 0)
1126 allow_naked_reg
= (intel_syntax
1127 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1129 allow_naked_reg
= (ask_naked_reg
< 0);
1131 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1132 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1133 register_prefix
= allow_naked_reg
? "" : "%";
1137 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1141 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1143 char *string
= input_line_pointer
;
1144 int e
= get_symbol_end ();
1147 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1149 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1153 cpu_arch_name
= cpu_arch
[i
].name
;
1154 cpu_sub_arch_name
= NULL
;
1155 cpu_arch_flags
= (cpu_arch
[i
].flags
1156 | (flag_code
== CODE_64BIT
1157 ? Cpu64
: CpuNo64
));
1158 cpu_arch_isa
= cpu_arch
[i
].type
;
1159 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1160 if (!cpu_arch_tune_set
)
1162 cpu_arch_tune
= cpu_arch_isa
;
1163 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1167 if ((cpu_arch_flags
| cpu_arch
[i
].flags
) != cpu_arch_flags
)
1169 cpu_sub_arch_name
= cpu_arch
[i
].name
;
1170 cpu_arch_flags
|= cpu_arch
[i
].flags
;
1172 *input_line_pointer
= e
;
1173 demand_empty_rest_of_line ();
1177 if (i
>= ARRAY_SIZE (cpu_arch
))
1178 as_bad (_("no such architecture: `%s'"), string
);
1180 *input_line_pointer
= e
;
1183 as_bad (_("missing cpu architecture"));
1185 no_cond_jump_promotion
= 0;
1186 if (*input_line_pointer
== ','
1187 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1189 char *string
= ++input_line_pointer
;
1190 int e
= get_symbol_end ();
1192 if (strcmp (string
, "nojumps") == 0)
1193 no_cond_jump_promotion
= 1;
1194 else if (strcmp (string
, "jumps") == 0)
1197 as_bad (_("no such architecture modifier: `%s'"), string
);
1199 *input_line_pointer
= e
;
1202 demand_empty_rest_of_line ();
1208 if (!strcmp (default_arch
, "x86_64"))
1209 return bfd_mach_x86_64
;
1210 else if (!strcmp (default_arch
, "i386"))
1211 return bfd_mach_i386_i386
;
1213 as_fatal (_("Unknown architecture"));
1219 const char *hash_err
;
1221 /* Initialize op_hash hash table. */
1222 op_hash
= hash_new ();
1225 const template *optab
;
1226 templates
*core_optab
;
1228 /* Setup for loop. */
1230 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1231 core_optab
->start
= optab
;
1236 if (optab
->name
== NULL
1237 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
1239 /* different name --> ship out current template list;
1240 add to hash table; & begin anew. */
1241 core_optab
->end
= optab
;
1242 hash_err
= hash_insert (op_hash
,
1247 as_fatal (_("Internal Error: Can't hash %s: %s"),
1251 if (optab
->name
== NULL
)
1253 core_optab
= (templates
*) xmalloc (sizeof (templates
));
1254 core_optab
->start
= optab
;
1259 /* Initialize reg_hash hash table. */
1260 reg_hash
= hash_new ();
1262 const reg_entry
*regtab
;
1263 unsigned int regtab_size
= i386_regtab_size
;
1265 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
1267 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
1269 as_fatal (_("Internal Error: Can't hash %s: %s"),
1275 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1280 for (c
= 0; c
< 256; c
++)
1285 mnemonic_chars
[c
] = c
;
1286 register_chars
[c
] = c
;
1287 operand_chars
[c
] = c
;
1289 else if (ISLOWER (c
))
1291 mnemonic_chars
[c
] = c
;
1292 register_chars
[c
] = c
;
1293 operand_chars
[c
] = c
;
1295 else if (ISUPPER (c
))
1297 mnemonic_chars
[c
] = TOLOWER (c
);
1298 register_chars
[c
] = mnemonic_chars
[c
];
1299 operand_chars
[c
] = c
;
1302 if (ISALPHA (c
) || ISDIGIT (c
))
1303 identifier_chars
[c
] = c
;
1306 identifier_chars
[c
] = c
;
1307 operand_chars
[c
] = c
;
1312 identifier_chars
['@'] = '@';
1315 identifier_chars
['?'] = '?';
1316 operand_chars
['?'] = '?';
1318 digit_chars
['-'] = '-';
1319 mnemonic_chars
['-'] = '-';
1320 mnemonic_chars
['.'] = '.';
1321 identifier_chars
['_'] = '_';
1322 identifier_chars
['.'] = '.';
1324 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
1325 operand_chars
[(unsigned char) *p
] = *p
;
1328 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1331 record_alignment (text_section
, 2);
1332 record_alignment (data_section
, 2);
1333 record_alignment (bss_section
, 2);
1337 if (flag_code
== CODE_64BIT
)
1339 x86_dwarf2_return_column
= 16;
1340 x86_cie_data_alignment
= -8;
1344 x86_dwarf2_return_column
= 8;
1345 x86_cie_data_alignment
= -4;
1350 i386_print_statistics (FILE *file
)
1352 hash_print_statistics (file
, "i386 opcode", op_hash
);
1353 hash_print_statistics (file
, "i386 register", reg_hash
);
1358 /* Debugging routines for md_assemble. */
1359 static void pte (template *);
1360 static void pt (unsigned int);
1361 static void pe (expressionS
*);
1362 static void ps (symbolS
*);
1365 pi (char *line
, i386_insn
*x
)
1369 fprintf (stdout
, "%s: template ", line
);
1371 fprintf (stdout
, " address: base %s index %s scale %x\n",
1372 x
->base_reg
? x
->base_reg
->reg_name
: "none",
1373 x
->index_reg
? x
->index_reg
->reg_name
: "none",
1374 x
->log2_scale_factor
);
1375 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
1376 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
1377 fprintf (stdout
, " sib: base %x index %x scale %x\n",
1378 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
1379 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
1380 (x
->rex
& REX_W
) != 0,
1381 (x
->rex
& REX_R
) != 0,
1382 (x
->rex
& REX_X
) != 0,
1383 (x
->rex
& REX_B
) != 0);
1384 for (i
= 0; i
< x
->operands
; i
++)
1386 fprintf (stdout
, " #%d: ", i
+ 1);
1388 fprintf (stdout
, "\n");
1390 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
1391 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
1392 if (x
->types
[i
] & Imm
)
1394 if (x
->types
[i
] & Disp
)
1395 pe (x
->op
[i
].disps
);
1403 fprintf (stdout
, " %d operands ", t
->operands
);
1404 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
1405 if (t
->extension_opcode
!= None
)
1406 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
1407 if (t
->opcode_modifier
& D
)
1408 fprintf (stdout
, "D");
1409 if (t
->opcode_modifier
& W
)
1410 fprintf (stdout
, "W");
1411 fprintf (stdout
, "\n");
1412 for (i
= 0; i
< t
->operands
; i
++)
1414 fprintf (stdout
, " #%d type ", i
+ 1);
1415 pt (t
->operand_types
[i
]);
1416 fprintf (stdout
, "\n");
1423 fprintf (stdout
, " operation %d\n", e
->X_op
);
1424 fprintf (stdout
, " add_number %ld (%lx)\n",
1425 (long) e
->X_add_number
, (long) e
->X_add_number
);
1426 if (e
->X_add_symbol
)
1428 fprintf (stdout
, " add_symbol ");
1429 ps (e
->X_add_symbol
);
1430 fprintf (stdout
, "\n");
1434 fprintf (stdout
, " op_symbol ");
1435 ps (e
->X_op_symbol
);
1436 fprintf (stdout
, "\n");
1443 fprintf (stdout
, "%s type %s%s",
1445 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1446 segment_name (S_GET_SEGMENT (s
)));
1449 static struct type_name
1454 const type_names
[] =
1467 { BaseIndex
, "BaseIndex" },
1471 { Disp32S
, "d32s" },
1473 { InOutPortReg
, "InOutPortReg" },
1474 { ShiftCount
, "ShiftCount" },
1475 { Control
, "control reg" },
1476 { Test
, "test reg" },
1477 { Debug
, "debug reg" },
1478 { FloatReg
, "FReg" },
1479 { FloatAcc
, "FAcc" },
1483 { JumpAbsolute
, "Jump Absolute" },
1494 const struct type_name
*ty
;
1496 for (ty
= type_names
; ty
->mask
; ty
++)
1498 fprintf (stdout
, "%s, ", ty
->tname
);
1502 #endif /* DEBUG386 */
1504 static bfd_reloc_code_real_type
1505 reloc (unsigned int size
,
1508 bfd_reloc_code_real_type other
)
1510 if (other
!= NO_RELOC
)
1512 reloc_howto_type
*reloc
;
1517 case BFD_RELOC_X86_64_GOT32
:
1518 return BFD_RELOC_X86_64_GOT64
;
1520 case BFD_RELOC_X86_64_PLTOFF64
:
1521 return BFD_RELOC_X86_64_PLTOFF64
;
1523 case BFD_RELOC_X86_64_GOTPC32
:
1524 other
= BFD_RELOC_X86_64_GOTPC64
;
1526 case BFD_RELOC_X86_64_GOTPCREL
:
1527 other
= BFD_RELOC_X86_64_GOTPCREL64
;
1529 case BFD_RELOC_X86_64_TPOFF32
:
1530 other
= BFD_RELOC_X86_64_TPOFF64
;
1532 case BFD_RELOC_X86_64_DTPOFF32
:
1533 other
= BFD_RELOC_X86_64_DTPOFF64
;
1539 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1540 if (size
== 4 && flag_code
!= CODE_64BIT
)
1543 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
1545 as_bad (_("unknown relocation (%u)"), other
);
1546 else if (size
!= bfd_get_reloc_size (reloc
))
1547 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1548 bfd_get_reloc_size (reloc
),
1550 else if (pcrel
&& !reloc
->pc_relative
)
1551 as_bad (_("non-pc-relative relocation for pc-relative field"));
1552 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
1554 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
1556 as_bad (_("relocated field and relocation type differ in signedness"));
1565 as_bad (_("there are no unsigned pc-relative relocations"));
1568 case 1: return BFD_RELOC_8_PCREL
;
1569 case 2: return BFD_RELOC_16_PCREL
;
1570 case 4: return BFD_RELOC_32_PCREL
;
1571 case 8: return BFD_RELOC_64_PCREL
;
1573 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
1580 case 4: return BFD_RELOC_X86_64_32S
;
1585 case 1: return BFD_RELOC_8
;
1586 case 2: return BFD_RELOC_16
;
1587 case 4: return BFD_RELOC_32
;
1588 case 8: return BFD_RELOC_64
;
1590 as_bad (_("cannot do %s %u byte relocation"),
1591 sign
> 0 ? "signed" : "unsigned", size
);
1595 return BFD_RELOC_NONE
;
1598 /* Here we decide which fixups can be adjusted to make them relative to
1599 the beginning of the section instead of the symbol. Basically we need
1600 to make sure that the dynamic relocations are done correctly, so in
1601 some cases we force the original symbol to be used. */
1604 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
1606 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1610 /* Don't adjust pc-relative references to merge sections in 64-bit
1612 if (use_rela_relocations
1613 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
1617 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1618 and changed later by validate_fix. */
1619 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
1620 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
1623 /* adjust_reloc_syms doesn't know about the GOT. */
1624 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1625 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1626 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1627 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
1628 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
1629 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
1630 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
1631 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
1632 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
1633 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
1634 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
1635 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
1636 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
1637 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1638 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1639 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
1640 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
1641 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
1642 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
1643 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
1644 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
1645 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
1646 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
1647 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
1648 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
1649 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
1650 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1651 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1658 intel_float_operand (const char *mnemonic
)
1660 /* Note that the value returned is meaningful only for opcodes with (memory)
1661 operands, hence the code here is free to improperly handle opcodes that
1662 have no operands (for better performance and smaller code). */
1664 if (mnemonic
[0] != 'f')
1665 return 0; /* non-math */
1667 switch (mnemonic
[1])
1669 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1670 the fs segment override prefix not currently handled because no
1671 call path can make opcodes without operands get here */
1673 return 2 /* integer op */;
1675 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
1676 return 3; /* fldcw/fldenv */
1679 if (mnemonic
[2] != 'o' /* fnop */)
1680 return 3; /* non-waiting control op */
1683 if (mnemonic
[2] == 's')
1684 return 3; /* frstor/frstpm */
1687 if (mnemonic
[2] == 'a')
1688 return 3; /* fsave */
1689 if (mnemonic
[2] == 't')
1691 switch (mnemonic
[3])
1693 case 'c': /* fstcw */
1694 case 'd': /* fstdw */
1695 case 'e': /* fstenv */
1696 case 's': /* fsts[gw] */
1702 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
1703 return 0; /* fxsave/fxrstor are not really math ops */
1710 /* This is the guts of the machine-dependent assembler. LINE points to a
1711 machine dependent instruction. This function is supposed to emit
1712 the frags/bytes it assembles to. */
1719 char mnemonic
[MAX_MNEM_SIZE
];
1721 /* Initialize globals. */
1722 memset (&i
, '\0', sizeof (i
));
1723 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1724 i
.reloc
[j
] = NO_RELOC
;
1725 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1726 memset (im_expressions
, '\0', sizeof (im_expressions
));
1727 save_stack_p
= save_stack
;
1729 /* First parse an instruction mnemonic & call i386_operand for the operands.
1730 We assume that the scrubber has arranged it so that line[0] is the valid
1731 start of a (possibly prefixed) mnemonic. */
1733 line
= parse_insn (line
, mnemonic
);
1737 line
= parse_operands (line
, mnemonic
);
1741 /* The order of the immediates should be reversed
1742 for 2 immediates extrq and insertq instructions */
1743 if ((i
.imm_operands
== 2)
1744 && ((strcmp (mnemonic
, "extrq") == 0)
1745 || (strcmp (mnemonic
, "insertq") == 0)))
1747 swap_2_operands (0, 1);
1748 /* "extrq" and insertq" are the only two instructions whose operands
1749 have to be reversed even though they have two immediate operands.
1755 /* Now we've parsed the mnemonic into a set of templates, and have the
1756 operands at hand. */
1758 /* All intel opcodes have reversed operands except for "bound" and
1759 "enter". We also don't reverse intersegment "jmp" and "call"
1760 instructions with 2 immediate operands so that the immediate segment
1761 precedes the offset, as it does when in AT&T mode. */
1764 && (strcmp (mnemonic
, "bound") != 0)
1765 && (strcmp (mnemonic
, "invlpga") != 0)
1766 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1772 /* Don't optimize displacement for movabs since it only takes 64bit
1775 && (flag_code
!= CODE_64BIT
1776 || strcmp (mnemonic
, "movabs") != 0))
1779 /* Next, we find a template that matches the given insn,
1780 making sure the overlap of the given operands types is consistent
1781 with the template operand types. */
1783 if (!match_template ())
1788 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1790 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1791 i
.tm
.base_opcode
^= Opcode_FloatR
;
1793 /* Zap movzx and movsx suffix. The suffix may have been set from
1794 "word ptr" or "byte ptr" on the source operand, but we'll use
1795 the suffix later to choose the destination register. */
1796 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
1798 if (i
.reg_operands
< 2
1800 && (~i
.tm
.opcode_modifier
1807 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
1813 if (i
.tm
.opcode_modifier
& FWait
)
1814 if (!add_prefix (FWAIT_OPCODE
))
1817 /* Check string instruction segment overrides. */
1818 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1820 if (!check_string ())
1824 if (!process_suffix ())
1827 /* Make still unresolved immediate matches conform to size of immediate
1828 given in i.suffix. */
1829 if (!finalize_imm ())
1832 if (i
.types
[0] & Imm1
)
1833 i
.imm_operands
= 0; /* kludge for shift insns. */
1834 if (i
.types
[0] & ImplicitRegister
)
1836 if (i
.types
[1] & ImplicitRegister
)
1838 if (i
.types
[2] & ImplicitRegister
)
1841 if (i
.tm
.opcode_modifier
& ImmExt
)
1845 if ((i
.tm
.cpu_flags
& CpuSSE3
) && i
.operands
> 0)
1847 /* Streaming SIMD extensions 3 Instructions have the fixed
1848 operands with an opcode suffix which is coded in the same
1849 place as an 8-bit immediate field would be. Here we check
1850 those operands and remove them afterwards. */
1853 for (x
= 0; x
< i
.operands
; x
++)
1854 if (i
.op
[x
].regs
->reg_num
!= x
)
1855 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1857 i
.op
[x
].regs
->reg_name
,
1863 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1864 opcode suffix which is coded in the same place as an 8-bit
1865 immediate field would be. Here we fake an 8-bit immediate
1866 operand from the opcode suffix stored in tm.extension_opcode. */
1868 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1870 exp
= &im_expressions
[i
.imm_operands
++];
1871 i
.op
[i
.operands
].imms
= exp
;
1872 i
.types
[i
.operands
++] = Imm8
;
1873 exp
->X_op
= O_constant
;
1874 exp
->X_add_number
= i
.tm
.extension_opcode
;
1875 i
.tm
.extension_opcode
= None
;
1878 /* For insns with operands there are more diddles to do to the opcode. */
1881 if (!process_operands ())
1884 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
1886 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1887 as_warn (_("translating to `%sp'"), i
.tm
.name
);
1890 /* Handle conversion of 'int $3' --> special int3 insn. */
1891 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
1893 i
.tm
.base_opcode
= INT3_OPCODE
;
1897 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
1898 && i
.op
[0].disps
->X_op
== O_constant
)
1900 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1901 the absolute address given by the constant. Since ix86 jumps and
1902 calls are pc relative, we need to generate a reloc. */
1903 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
1904 i
.op
[0].disps
->X_op
= O_symbol
;
1907 if ((i
.tm
.opcode_modifier
& Rex64
) != 0)
1910 /* For 8 bit registers we need an empty rex prefix. Also if the
1911 instruction already has a prefix, we need to convert old
1912 registers to new ones. */
1914 if (((i
.types
[0] & Reg8
) != 0
1915 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
1916 || ((i
.types
[1] & Reg8
) != 0
1917 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
1918 || (((i
.types
[0] & Reg8
) != 0 || (i
.types
[1] & Reg8
) != 0)
1923 i
.rex
|= REX_OPCODE
;
1924 for (x
= 0; x
< 2; x
++)
1926 /* Look for 8 bit operand that uses old registers. */
1927 if ((i
.types
[x
] & Reg8
) != 0
1928 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
1930 /* In case it is "hi" register, give up. */
1931 if (i
.op
[x
].regs
->reg_num
> 3)
1932 as_bad (_("can't encode register '%s%s' in an "
1933 "instruction requiring REX prefix."),
1934 register_prefix
, i
.op
[x
].regs
->reg_name
);
1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1940 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
1946 add_prefix (REX_OPCODE
| i
.rex
);
1948 /* We are ready to output the insn. */
1953 parse_insn (char *line
, char *mnemonic
)
1956 char *token_start
= l
;
1961 /* Non-zero if we found a prefix only acceptable with string insns. */
1962 const char *expecting_string_instruction
= NULL
;
1967 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1970 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
1972 as_bad (_("no such instruction: `%s'"), token_start
);
1977 if (!is_space_char (*l
)
1978 && *l
!= END_OF_INSN
1980 || (*l
!= PREFIX_SEPARATOR
1983 as_bad (_("invalid character %s in mnemonic"),
1984 output_invalid (*l
));
1987 if (token_start
== l
)
1989 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
1990 as_bad (_("expecting prefix; got nothing"));
1992 as_bad (_("expecting mnemonic; got nothing"));
1996 /* Look up instruction (or prefix) via hash table. */
1997 current_templates
= hash_find (op_hash
, mnemonic
);
1999 if (*l
!= END_OF_INSN
2000 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2001 && current_templates
2002 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
2004 if (current_templates
->start
->cpu_flags
2005 & (flag_code
!= CODE_64BIT
? Cpu64
: CpuNo64
))
2007 as_bad ((flag_code
!= CODE_64BIT
2008 ? _("`%s' is only supported in 64-bit mode")
2009 : _("`%s' is not supported in 64-bit mode")),
2010 current_templates
->start
->name
);
2013 /* If we are in 16-bit mode, do not allow addr16 or data16.
2014 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2015 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
2016 && flag_code
!= CODE_64BIT
2017 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
2018 ^ (flag_code
== CODE_16BIT
)))
2020 as_bad (_("redundant %s prefix"),
2021 current_templates
->start
->name
);
2024 /* Add prefix, checking for repeated prefixes. */
2025 switch (add_prefix (current_templates
->start
->base_opcode
))
2030 expecting_string_instruction
= current_templates
->start
->name
;
2033 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2040 if (!current_templates
)
2042 /* See if we can get a match by trimming off a suffix. */
2045 case WORD_MNEM_SUFFIX
:
2046 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
2047 i
.suffix
= SHORT_MNEM_SUFFIX
;
2049 case BYTE_MNEM_SUFFIX
:
2050 case QWORD_MNEM_SUFFIX
:
2051 i
.suffix
= mnem_p
[-1];
2053 current_templates
= hash_find (op_hash
, mnemonic
);
2055 case SHORT_MNEM_SUFFIX
:
2056 case LONG_MNEM_SUFFIX
:
2059 i
.suffix
= mnem_p
[-1];
2061 current_templates
= hash_find (op_hash
, mnemonic
);
2069 if (intel_float_operand (mnemonic
) == 1)
2070 i
.suffix
= SHORT_MNEM_SUFFIX
;
2072 i
.suffix
= LONG_MNEM_SUFFIX
;
2074 current_templates
= hash_find (op_hash
, mnemonic
);
2078 if (!current_templates
)
2080 as_bad (_("no such instruction: `%s'"), token_start
);
2085 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpByte
))
2087 /* Check for a branch hint. We allow ",pt" and ",pn" for
2088 predict taken and predict not taken respectively.
2089 I'm not sure that branch hints actually do anything on loop
2090 and jcxz insns (JumpByte) for current Pentium4 chips. They
2091 may work in the future and it doesn't hurt to accept them
2093 if (l
[0] == ',' && l
[1] == 'p')
2097 if (!add_prefix (DS_PREFIX_OPCODE
))
2101 else if (l
[2] == 'n')
2103 if (!add_prefix (CS_PREFIX_OPCODE
))
2109 /* Any other comma loses. */
2112 as_bad (_("invalid character %s in mnemonic"),
2113 output_invalid (*l
));
2117 /* Check if instruction is supported on specified architecture. */
2119 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2121 if (!((t
->cpu_flags
& ~(Cpu64
| CpuNo64
))
2122 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
))))
2124 if (!(t
->cpu_flags
& (flag_code
== CODE_64BIT
? CpuNo64
: Cpu64
)))
2127 if (!(supported
& 2))
2129 as_bad (flag_code
== CODE_64BIT
2130 ? _("`%s' is not supported in 64-bit mode")
2131 : _("`%s' is only supported in 64-bit mode"),
2132 current_templates
->start
->name
);
2135 if (!(supported
& 1))
2137 as_warn (_("`%s' is not supported on `%s%s'"),
2138 current_templates
->start
->name
,
2140 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
2142 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
2144 as_warn (_("use .code16 to ensure correct addressing mode"));
2147 /* Check for rep/repne without a string instruction. */
2148 if (expecting_string_instruction
)
2150 static templates override
;
2152 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
2153 if (t
->opcode_modifier
& IsString
)
2155 if (t
>= current_templates
->end
)
2157 as_bad (_("expecting string instruction after `%s'"),
2158 expecting_string_instruction
);
2161 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
2162 if (!(t
->opcode_modifier
& IsString
))
2165 current_templates
= &override
;
2172 parse_operands (char *l
, const char *mnemonic
)
2176 /* 1 if operand is pending after ','. */
2177 unsigned int expecting_operand
= 0;
2179 /* Non-zero if operand parens not balanced. */
2180 unsigned int paren_not_balanced
;
2182 while (*l
!= END_OF_INSN
)
2184 /* Skip optional white space before operand. */
2185 if (is_space_char (*l
))
2187 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
2189 as_bad (_("invalid character %s before operand %d"),
2190 output_invalid (*l
),
2194 token_start
= l
; /* after white space */
2195 paren_not_balanced
= 0;
2196 while (paren_not_balanced
|| *l
!= ',')
2198 if (*l
== END_OF_INSN
)
2200 if (paren_not_balanced
)
2203 as_bad (_("unbalanced parenthesis in operand %d."),
2206 as_bad (_("unbalanced brackets in operand %d."),
2211 break; /* we are done */
2213 else if (!is_operand_char (*l
) && !is_space_char (*l
))
2215 as_bad (_("invalid character %s in operand %d"),
2216 output_invalid (*l
),
2223 ++paren_not_balanced
;
2225 --paren_not_balanced
;
2230 ++paren_not_balanced
;
2232 --paren_not_balanced
;
2236 if (l
!= token_start
)
2237 { /* Yes, we've read in another operand. */
2238 unsigned int operand_ok
;
2239 this_operand
= i
.operands
++;
2240 if (i
.operands
> MAX_OPERANDS
)
2242 as_bad (_("spurious operands; (%d operands/instruction max)"),
2246 /* Now parse operand adding info to 'i' as we go along. */
2247 END_STRING_AND_SAVE (l
);
2251 i386_intel_operand (token_start
,
2252 intel_float_operand (mnemonic
));
2254 operand_ok
= i386_operand (token_start
);
2256 RESTORE_END_STRING (l
);
2262 if (expecting_operand
)
2264 expecting_operand_after_comma
:
2265 as_bad (_("expecting operand after ','; got nothing"));
2270 as_bad (_("expecting operand before ','; got nothing"));
2275 /* Now *l must be either ',' or END_OF_INSN. */
2278 if (*++l
== END_OF_INSN
)
2280 /* Just skip it, if it's \n complain. */
2281 goto expecting_operand_after_comma
;
2283 expecting_operand
= 1;
2290 swap_2_operands (int xchg1
, int xchg2
)
2292 union i386_op temp_op
;
2293 unsigned int temp_type
;
2294 enum bfd_reloc_code_real temp_reloc
;
2296 temp_type
= i
.types
[xchg2
];
2297 i
.types
[xchg2
] = i
.types
[xchg1
];
2298 i
.types
[xchg1
] = temp_type
;
2299 temp_op
= i
.op
[xchg2
];
2300 i
.op
[xchg2
] = i
.op
[xchg1
];
2301 i
.op
[xchg1
] = temp_op
;
2302 temp_reloc
= i
.reloc
[xchg2
];
2303 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
2304 i
.reloc
[xchg1
] = temp_reloc
;
2308 swap_operands (void)
2313 swap_2_operands (1, i
.operands
- 2);
2316 swap_2_operands (0, i
.operands
- 1);
2322 if (i
.mem_operands
== 2)
2324 const seg_entry
*temp_seg
;
2325 temp_seg
= i
.seg
[0];
2326 i
.seg
[0] = i
.seg
[1];
2327 i
.seg
[1] = temp_seg
;
2331 /* Try to ensure constant immediates are represented in the smallest
2336 char guess_suffix
= 0;
2340 guess_suffix
= i
.suffix
;
2341 else if (i
.reg_operands
)
2343 /* Figure out a suffix from the last register operand specified.
2344 We can't do this properly yet, ie. excluding InOutPortReg,
2345 but the following works for instructions with immediates.
2346 In any case, we can't set i.suffix yet. */
2347 for (op
= i
.operands
; --op
>= 0;)
2348 if (i
.types
[op
] & Reg
)
2350 if (i
.types
[op
] & Reg8
)
2351 guess_suffix
= BYTE_MNEM_SUFFIX
;
2352 else if (i
.types
[op
] & Reg16
)
2353 guess_suffix
= WORD_MNEM_SUFFIX
;
2354 else if (i
.types
[op
] & Reg32
)
2355 guess_suffix
= LONG_MNEM_SUFFIX
;
2356 else if (i
.types
[op
] & Reg64
)
2357 guess_suffix
= QWORD_MNEM_SUFFIX
;
2361 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
2362 guess_suffix
= WORD_MNEM_SUFFIX
;
2364 for (op
= i
.operands
; --op
>= 0;)
2365 if (i
.types
[op
] & Imm
)
2367 switch (i
.op
[op
].imms
->X_op
)
2370 /* If a suffix is given, this operand may be shortened. */
2371 switch (guess_suffix
)
2373 case LONG_MNEM_SUFFIX
:
2374 i
.types
[op
] |= Imm32
| Imm64
;
2376 case WORD_MNEM_SUFFIX
:
2377 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
2379 case BYTE_MNEM_SUFFIX
:
2380 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
2384 /* If this operand is at most 16 bits, convert it
2385 to a signed 16 bit number before trying to see
2386 whether it will fit in an even smaller size.
2387 This allows a 16-bit operand such as $0xffe0 to
2388 be recognised as within Imm8S range. */
2389 if ((i
.types
[op
] & Imm16
)
2390 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
2392 i
.op
[op
].imms
->X_add_number
=
2393 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2395 if ((i
.types
[op
] & Imm32
)
2396 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
2399 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
2400 ^ ((offsetT
) 1 << 31))
2401 - ((offsetT
) 1 << 31));
2403 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
2405 /* We must avoid matching of Imm32 templates when 64bit
2406 only immediate is available. */
2407 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
2408 i
.types
[op
] &= ~Imm32
;
2415 /* Symbols and expressions. */
2417 /* Convert symbolic operand to proper sizes for matching, but don't
2418 prevent matching a set of insns that only supports sizes other
2419 than those matching the insn suffix. */
2421 unsigned int mask
, allowed
= 0;
2424 for (t
= current_templates
->start
;
2425 t
< current_templates
->end
;
2427 allowed
|= t
->operand_types
[op
];
2428 switch (guess_suffix
)
2430 case QWORD_MNEM_SUFFIX
:
2431 mask
= Imm64
| Imm32S
;
2433 case LONG_MNEM_SUFFIX
:
2436 case WORD_MNEM_SUFFIX
:
2439 case BYTE_MNEM_SUFFIX
:
2447 i
.types
[op
] &= mask
;
2454 /* Try to use the smallest displacement type too. */
2456 optimize_disp (void)
2460 for (op
= i
.operands
; --op
>= 0;)
2461 if (i
.types
[op
] & Disp
)
2463 if (i
.op
[op
].disps
->X_op
== O_constant
)
2465 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
2467 if ((i
.types
[op
] & Disp16
)
2468 && (disp
& ~(offsetT
) 0xffff) == 0)
2470 /* If this operand is at most 16 bits, convert
2471 to a signed 16 bit number and don't use 64bit
2473 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
2474 i
.types
[op
] &= ~Disp64
;
2476 if ((i
.types
[op
] & Disp32
)
2477 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
2479 /* If this operand is at most 32 bits, convert
2480 to a signed 32 bit number and don't use 64bit
2482 disp
&= (((offsetT
) 2 << 31) - 1);
2483 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
2484 i
.types
[op
] &= ~Disp64
;
2486 if (!disp
&& (i
.types
[op
] & BaseIndex
))
2488 i
.types
[op
] &= ~Disp
;
2492 else if (flag_code
== CODE_64BIT
)
2494 if (fits_in_signed_long (disp
))
2496 i
.types
[op
] &= ~Disp64
;
2497 i
.types
[op
] |= Disp32S
;
2499 if (fits_in_unsigned_long (disp
))
2500 i
.types
[op
] |= Disp32
;
2502 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
2503 && fits_in_signed_byte (disp
))
2504 i
.types
[op
] |= Disp8
;
2506 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
2507 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
2509 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
2510 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
2511 i
.types
[op
] &= ~Disp
;
2514 /* We only support 64bit displacement on constants. */
2515 i
.types
[op
] &= ~Disp64
;
2520 match_template (void)
2522 /* Points to template once we've found it. */
2524 unsigned int overlap0
, overlap1
, overlap2
, overlap3
;
2525 unsigned int found_reverse_match
;
2527 unsigned int operand_types
[MAX_OPERANDS
];
2528 int addr_prefix_disp
;
2531 #if MAX_OPERANDS != 4
2532 # error "MAX_OPERANDS must be 4."
2535 #define MATCH(overlap, given, template) \
2536 ((overlap & ~JumpAbsolute) \
2537 && (((given) & (BaseIndex | JumpAbsolute)) \
2538 == ((overlap) & (BaseIndex | JumpAbsolute))))
2540 /* If given types r0 and r1 are registers they must be of the same type
2541 unless the expected operand type register overlap is null.
2542 Note that Acc in a template matches every size of reg. */
2543 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2544 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2545 || ((g0) & Reg) == ((g1) & Reg) \
2546 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2552 found_reverse_match
= 0;
2553 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2554 operand_types
[j
] = 0;
2555 addr_prefix_disp
= -1;
2556 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
2558 : (i
.suffix
== WORD_MNEM_SUFFIX
2560 : (i
.suffix
== SHORT_MNEM_SUFFIX
2562 : (i
.suffix
== LONG_MNEM_SUFFIX
2564 : (i
.suffix
== QWORD_MNEM_SUFFIX
2566 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
2567 ? No_xSuf
: 0))))));
2569 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
2571 addr_prefix_disp
= -1;
2573 /* Must have right number of operands. */
2574 if (i
.operands
!= t
->operands
)
2577 /* Check the suffix, except for some instructions in intel mode. */
2578 if ((t
->opcode_modifier
& suffix_check
)
2580 && (t
->opcode_modifier
& IgnoreSize
)))
2583 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2584 operand_types
[j
] = t
->operand_types
[j
];
2586 /* In general, don't allow 64-bit operands in 32-bit mode. */
2587 if (i
.suffix
== QWORD_MNEM_SUFFIX
2588 && flag_code
!= CODE_64BIT
2590 ? (!(t
->opcode_modifier
& IgnoreSize
)
2591 && !intel_float_operand (t
->name
))
2592 : intel_float_operand (t
->name
) != 2)
2593 && (!(operand_types
[0] & (RegMMX
| RegXMM
))
2594 || !(operand_types
[t
->operands
> 1] & (RegMMX
| RegXMM
)))
2595 && (t
->base_opcode
!= 0x0fc7
2596 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
2599 /* Do not verify operands when there are none. */
2600 else if (!t
->operands
)
2602 if (t
->cpu_flags
& ~cpu_arch_flags
)
2604 /* We've found a match; break out of loop. */
2608 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2609 into Disp32/Disp16/Disp32 operand. */
2610 if (i
.prefix
[ADDR_PREFIX
] != 0)
2612 unsigned int DispOn
= 0, DispOff
= 0;
2630 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2632 /* There should be only one Disp operand. */
2633 if ((operand_types
[j
] & DispOff
))
2635 addr_prefix_disp
= j
;
2636 operand_types
[j
] |= DispOn
;
2637 operand_types
[j
] &= ~DispOff
;
2643 overlap0
= i
.types
[0] & operand_types
[0];
2644 switch (t
->operands
)
2647 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0]))
2651 /* xchg %eax, %eax is a special case. It is an aliase for nop
2652 only in 32bit mode and we can use opcode 0x90. In 64bit
2653 mode, we can't use 0x90 for xchg %eax, %eax since it should
2654 zero-extend %eax to %rax. */
2655 if (flag_code
== CODE_64BIT
2656 && t
->base_opcode
== 0x90
2657 && i
.types
[0] == (Acc
| Reg32
)
2658 && i
.types
[1] == (Acc
| Reg32
))
2662 overlap1
= i
.types
[1] & operand_types
[1];
2663 if (!MATCH (overlap0
, i
.types
[0], operand_types
[0])
2664 || !MATCH (overlap1
, i
.types
[1], operand_types
[1])
2665 /* monitor in SSE3 is a very special case. The first
2666 register and the second register may have different
2667 sizes. The same applies to crc32 in SSE4.2. It is
2668 also true for invlpga, vmload, vmrun and vmsave in
2670 || !((t
->base_opcode
== 0x0f01
2671 && (t
->extension_opcode
== 0xc8
2672 || t
->extension_opcode
== 0xd8
2673 || t
->extension_opcode
== 0xda
2674 || t
->extension_opcode
== 0xdb
2675 || t
->extension_opcode
== 0xdf))
2676 || t
->base_opcode
== 0xf20f38f1
2677 || CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2679 overlap1
, i
.types
[1],
2682 /* Check if other direction is valid ... */
2683 if ((t
->opcode_modifier
& (D
| FloatD
)) == 0)
2686 /* Try reversing direction of operands. */
2687 overlap0
= i
.types
[0] & operand_types
[1];
2688 overlap1
= i
.types
[1] & operand_types
[0];
2689 if (!MATCH (overlap0
, i
.types
[0], operand_types
[1])
2690 || !MATCH (overlap1
, i
.types
[1], operand_types
[0])
2691 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
2693 overlap1
, i
.types
[1],
2696 /* Does not match either direction. */
2699 /* found_reverse_match holds which of D or FloatDR
2701 if ((t
->opcode_modifier
& D
))
2702 found_reverse_match
= Opcode_D
;
2703 else if ((t
->opcode_modifier
& FloatD
))
2704 found_reverse_match
= Opcode_FloatD
;
2706 found_reverse_match
= 0;
2707 if ((t
->opcode_modifier
& FloatR
))
2708 found_reverse_match
|= Opcode_FloatR
;
2712 /* Found a forward 2 operand match here. */
2713 switch (t
->operands
)
2716 overlap3
= i
.types
[3] & operand_types
[3];
2718 overlap2
= i
.types
[2] & operand_types
[2];
2722 switch (t
->operands
)
2725 if (!MATCH (overlap3
, i
.types
[3], operand_types
[3])
2726 || !CONSISTENT_REGISTER_MATCH (overlap2
,
2734 /* Here we make use of the fact that there are no
2735 reverse match 3 operand instructions, and all 3
2736 operand instructions only need to be checked for
2737 register consistency between operands 2 and 3. */
2738 if (!MATCH (overlap2
, i
.types
[2], operand_types
[2])
2739 || !CONSISTENT_REGISTER_MATCH (overlap1
,
2749 /* Found either forward/reverse 2, 3 or 4 operand match here:
2750 slip through to break. */
2752 if (t
->cpu_flags
& ~cpu_arch_flags
)
2754 found_reverse_match
= 0;
2757 /* We've found a match; break out of loop. */
2761 if (t
== current_templates
->end
)
2763 /* We found no match. */
2764 as_bad (_("suffix or operands invalid for `%s'"),
2765 current_templates
->start
->name
);
2769 if (!quiet_warnings
)
2772 && ((i
.types
[0] & JumpAbsolute
)
2773 != (operand_types
[0] & JumpAbsolute
)))
2775 as_warn (_("indirect %s without `*'"), t
->name
);
2778 if ((t
->opcode_modifier
& (IsPrefix
| IgnoreSize
))
2779 == (IsPrefix
| IgnoreSize
))
2781 /* Warn them that a data or address size prefix doesn't
2782 affect assembly of the next line of code. */
2783 as_warn (_("stand-alone `%s' prefix"), t
->name
);
2787 /* Copy the template we found. */
2790 if (addr_prefix_disp
!= -1)
2791 i
.tm
.operand_types
[addr_prefix_disp
]
2792 = operand_types
[addr_prefix_disp
];
2794 if (found_reverse_match
)
2796 /* If we found a reverse match we must alter the opcode
2797 direction bit. found_reverse_match holds bits to change
2798 (different for int & float insns). */
2800 i
.tm
.base_opcode
^= found_reverse_match
;
2802 i
.tm
.operand_types
[0] = operand_types
[1];
2803 i
.tm
.operand_types
[1] = operand_types
[0];
2812 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
2813 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
2815 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
2817 as_bad (_("`%s' operand %d must use `%%es' segment"),
2822 /* There's only ever one segment override allowed per instruction.
2823 This instruction possibly has a legal segment override on the
2824 second operand, so copy the segment to where non-string
2825 instructions store it, allowing common code. */
2826 i
.seg
[0] = i
.seg
[1];
2828 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
2830 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
2832 as_bad (_("`%s' operand %d must use `%%es' segment"),
2842 process_suffix (void)
2844 /* If matched instruction specifies an explicit instruction mnemonic
2846 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
2848 if (i
.tm
.opcode_modifier
& Size16
)
2849 i
.suffix
= WORD_MNEM_SUFFIX
;
2850 else if (i
.tm
.opcode_modifier
& Size64
)
2851 i
.suffix
= QWORD_MNEM_SUFFIX
;
2853 i
.suffix
= LONG_MNEM_SUFFIX
;
2855 else if (i
.reg_operands
)
2857 /* If there's no instruction mnemonic suffix we try to invent one
2858 based on register operands. */
2861 /* We take i.suffix from the last register operand specified,
2862 Destination register type is more significant than source
2863 register type. crc32 in SSE4.2 prefers source register
2865 if (i
.tm
.base_opcode
== 0xf20f38f1)
2867 if ((i
.types
[0] & Reg
))
2868 i
.suffix
= ((i
.types
[0] & Reg16
) ? WORD_MNEM_SUFFIX
:
2871 else if (i
.tm
.base_opcode
== 0xf20f38f0)
2873 if ((i
.types
[0] & Reg8
))
2874 i
.suffix
= BYTE_MNEM_SUFFIX
;
2881 if (i
.tm
.base_opcode
== 0xf20f38f1
2882 || i
.tm
.base_opcode
== 0xf20f38f0)
2884 /* We have to know the operand size for crc32. */
2885 as_bad (_("ambiguous memory operand size for `%s`"),
2890 for (op
= i
.operands
; --op
>= 0;)
2891 if ((i
.types
[op
] & Reg
)
2892 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
2894 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
2895 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
2896 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
2902 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
2904 if (!check_byte_reg ())
2907 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
2909 if (!check_long_reg ())
2912 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2914 if (!check_qword_reg ())
2917 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2919 if (!check_word_reg ())
2922 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2923 /* Do nothing if the instruction is going to ignore the prefix. */
2928 else if ((i
.tm
.opcode_modifier
& DefaultSize
)
2930 /* exclude fldenv/frstor/fsave/fstenv */
2931 && (i
.tm
.opcode_modifier
& No_sSuf
))
2933 i
.suffix
= stackop_size
;
2935 else if (intel_syntax
2937 && ((i
.tm
.operand_types
[0] & JumpAbsolute
)
2938 || (i
.tm
.opcode_modifier
& (JumpByte
|JumpInterSegment
))
2939 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
2940 && i
.tm
.extension_opcode
<= 3)))
2945 if (!(i
.tm
.opcode_modifier
& No_qSuf
))
2947 i
.suffix
= QWORD_MNEM_SUFFIX
;
2951 if (!(i
.tm
.opcode_modifier
& No_lSuf
))
2952 i
.suffix
= LONG_MNEM_SUFFIX
;
2955 if (!(i
.tm
.opcode_modifier
& No_wSuf
))
2956 i
.suffix
= WORD_MNEM_SUFFIX
;
2965 if (i
.tm
.opcode_modifier
& W
)
2967 as_bad (_("no instruction mnemonic suffix given and "
2968 "no register operands; can't size instruction"));
2974 unsigned int suffixes
= (~i
.tm
.opcode_modifier
2982 if ((i
.tm
.opcode_modifier
& W
)
2983 || ((suffixes
& (suffixes
- 1))
2984 && !(i
.tm
.opcode_modifier
& (DefaultSize
| IgnoreSize
))))
2986 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2992 /* Change the opcode based on the operand size given by i.suffix;
2993 We don't need to change things for byte insns. */
2995 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2997 /* It's not a byte, select word/dword operation. */
2998 if (i
.tm
.opcode_modifier
& W
)
3000 if (i
.tm
.opcode_modifier
& ShortForm
)
3001 i
.tm
.base_opcode
|= 8;
3003 i
.tm
.base_opcode
|= 1;
3006 /* Now select between word & dword operations via the operand
3007 size prefix, except for instructions that will ignore this
3009 if (i
.tm
.base_opcode
== 0x0f01
3010 && (i
.tm
.extension_opcode
== 0xc8
3011 || i
.tm
.extension_opcode
== 0xd8
3012 || i
.tm
.extension_opcode
== 0xda
3013 || i
.tm
.extension_opcode
== 0xdb
3014 || i
.tm
.extension_opcode
== 0xdf))
3016 /* monitor in SSE3 is a very special case. The default size
3017 of AX is the size of mode. The address size override
3018 prefix will change the size of AX. It is also true for
3019 invlpga, vmload, vmrun and vmsave in SVME. */
3020 if (i
.op
->regs
[0].reg_type
&
3021 (flag_code
== CODE_32BIT
? Reg16
: Reg32
))
3022 if (!add_prefix (ADDR_PREFIX_OPCODE
))
3025 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
3026 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
3027 && !(i
.tm
.opcode_modifier
& (IgnoreSize
| FloatMF
))
3028 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
3029 || (flag_code
== CODE_64BIT
3030 && (i
.tm
.opcode_modifier
& JumpByte
))))
3032 unsigned int prefix
= DATA_PREFIX_OPCODE
;
3034 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
3035 prefix
= ADDR_PREFIX_OPCODE
;
3037 if (!add_prefix (prefix
))
3041 /* Set mode64 for an operand. */
3042 if (i
.suffix
== QWORD_MNEM_SUFFIX
3043 && flag_code
== CODE_64BIT
3044 && (i
.tm
.opcode_modifier
& NoRex64
) == 0)
3046 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3047 need rex64. cmpxchg8b is also a special case. */
3048 if (! (i
.operands
== 2
3049 && i
.tm
.base_opcode
== 0x90
3050 && i
.tm
.extension_opcode
== None
3051 && i
.types
[0] == (Acc
| Reg64
)
3052 && i
.types
[1] == (Acc
| Reg64
))
3053 && ! (i
.operands
== 1
3054 && i
.tm
.base_opcode
== 0xfc7
3055 && i
.tm
.extension_opcode
== 1
3056 && (i
.types
[0] & Reg
) == 0
3057 && (i
.types
[0] & AnyMem
) != 0))
3061 /* Size floating point instruction. */
3062 if (i
.suffix
== LONG_MNEM_SUFFIX
)
3063 if (i
.tm
.opcode_modifier
& FloatMF
)
3064 i
.tm
.base_opcode
^= 4;
3071 check_byte_reg (void)
3075 for (op
= i
.operands
; --op
>= 0;)
3077 /* If this is an eight bit register, it's OK. If it's the 16 or
3078 32 bit version of an eight bit register, we will just use the
3079 low portion, and that's OK too. */
3080 if (i
.types
[op
] & Reg8
)
3083 /* movzx, movsx, pextrb and pinsrb should not generate this
3086 && (i
.tm
.base_opcode
== 0xfb7
3087 || i
.tm
.base_opcode
== 0xfb6
3088 || i
.tm
.base_opcode
== 0x63
3089 || i
.tm
.base_opcode
== 0xfbe
3090 || i
.tm
.base_opcode
== 0xfbf
3091 || i
.tm
.base_opcode
== 0x660f3a14
3092 || i
.tm
.base_opcode
== 0x660f3a20))
3095 /* crc32 doesn't generate this warning. */
3096 if (i
.tm
.base_opcode
== 0xf20f38f0)
3099 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4)
3101 /* Prohibit these changes in the 64bit mode, since the
3102 lowering is more complicated. */
3103 if (flag_code
== CODE_64BIT
3104 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3106 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3107 register_prefix
, i
.op
[op
].regs
->reg_name
,
3111 #if REGISTER_WARNINGS
3113 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
3114 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3116 (i
.op
[op
].regs
+ (i
.types
[op
] & Reg16
3117 ? REGNAM_AL
- REGNAM_AX
3118 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
3120 i
.op
[op
].regs
->reg_name
,
3125 /* Any other register is bad. */
3126 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3128 | Control
| Debug
| Test
3129 | FloatReg
| FloatAcc
))
3131 as_bad (_("`%s%s' not allowed with `%s%c'"),
3133 i
.op
[op
].regs
->reg_name
,
3143 check_long_reg (void)
3147 for (op
= i
.operands
; --op
>= 0;)
3148 /* Reject eight bit registers, except where the template requires
3149 them. (eg. movzb) */
3150 if ((i
.types
[op
] & Reg8
) != 0
3151 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3153 as_bad (_("`%s%s' not allowed with `%s%c'"),
3155 i
.op
[op
].regs
->reg_name
,
3160 /* Warn if the e prefix on a general reg is missing. */
3161 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3162 && (i
.types
[op
] & Reg16
) != 0
3163 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3165 /* Prohibit these changes in the 64bit mode, since the
3166 lowering is more complicated. */
3167 if (flag_code
== CODE_64BIT
)
3169 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3170 register_prefix
, i
.op
[op
].regs
->reg_name
,
3174 #if REGISTER_WARNINGS
3176 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3178 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
3180 i
.op
[op
].regs
->reg_name
,
3184 /* Warn if the r prefix on a general reg is missing. */
3185 else if ((i
.types
[op
] & Reg64
) != 0
3186 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3189 && i
.tm
.base_opcode
== 0xf30f2d
3190 && (i
.types
[0] & RegXMM
) == 0)
3192 /* cvtss2si converts DWORD memory to Reg64. We want
3194 i
.suffix
= QWORD_MNEM_SUFFIX
;
3198 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3199 register_prefix
, i
.op
[op
].regs
->reg_name
,
3208 check_qword_reg (void)
3212 for (op
= i
.operands
; --op
>= 0; )
3213 /* Reject eight bit registers, except where the template requires
3214 them. (eg. movzb) */
3215 if ((i
.types
[op
] & Reg8
) != 0
3216 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3218 as_bad (_("`%s%s' not allowed with `%s%c'"),
3220 i
.op
[op
].regs
->reg_name
,
3225 /* Warn if the e prefix on a general reg is missing. */
3226 else if ((i
.types
[op
] & (Reg16
| Reg32
)) != 0
3227 && (i
.tm
.operand_types
[op
] & (Reg32
| Acc
)) != 0)
3229 /* Prohibit these changes in the 64bit mode, since the
3230 lowering is more complicated. */
3232 && i
.tm
.base_opcode
== 0xf20f2d
3233 && (i
.types
[0] & RegXMM
) == 0)
3235 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3237 i
.suffix
= LONG_MNEM_SUFFIX
;
3241 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3242 register_prefix
, i
.op
[op
].regs
->reg_name
,
3251 check_word_reg (void)
3254 for (op
= i
.operands
; --op
>= 0;)
3255 /* Reject eight bit registers, except where the template requires
3256 them. (eg. movzb) */
3257 if ((i
.types
[op
] & Reg8
) != 0
3258 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
3260 as_bad (_("`%s%s' not allowed with `%s%c'"),
3262 i
.op
[op
].regs
->reg_name
,
3267 /* Warn if the e prefix on a general reg is present. */
3268 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
3269 && (i
.types
[op
] & Reg32
) != 0
3270 && (i
.tm
.operand_types
[op
] & (Reg16
| Acc
)) != 0)
3272 /* Prohibit these changes in the 64bit mode, since the
3273 lowering is more complicated. */
3274 if (flag_code
== CODE_64BIT
)
3276 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3277 register_prefix
, i
.op
[op
].regs
->reg_name
,
3282 #if REGISTER_WARNINGS
3283 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3285 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
3287 i
.op
[op
].regs
->reg_name
,
3297 unsigned int overlap0
, overlap1
, overlap2
;
3299 overlap0
= i
.types
[0] & i
.tm
.operand_types
[0];
3300 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
))
3301 && overlap0
!= Imm8
&& overlap0
!= Imm8S
3302 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3303 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3307 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3309 : (i
.suffix
== WORD_MNEM_SUFFIX
3311 : (i
.suffix
== QWORD_MNEM_SUFFIX
3315 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
3316 || overlap0
== (Imm16
| Imm32
)
3317 || overlap0
== (Imm16
| Imm32S
))
3319 overlap0
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3322 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
3323 && overlap0
!= Imm16
&& overlap0
!= Imm32S
3324 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
3326 as_bad (_("no instruction mnemonic suffix given; "
3327 "can't determine immediate size"));
3331 i
.types
[0] = overlap0
;
3333 overlap1
= i
.types
[1] & i
.tm
.operand_types
[1];
3334 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
| Imm64
))
3335 && overlap1
!= Imm8
&& overlap1
!= Imm8S
3336 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3337 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3341 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
3343 : (i
.suffix
== WORD_MNEM_SUFFIX
3345 : (i
.suffix
== QWORD_MNEM_SUFFIX
3349 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
3350 || overlap1
== (Imm16
| Imm32
)
3351 || overlap1
== (Imm16
| Imm32S
))
3353 overlap1
= ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)
3356 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
3357 && overlap1
!= Imm16
&& overlap1
!= Imm32S
3358 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
3360 as_bad (_("no instruction mnemonic suffix given; "
3361 "can't determine immediate size %x %c"),
3362 overlap1
, i
.suffix
);
3366 i
.types
[1] = overlap1
;
3368 overlap2
= i
.types
[2] & i
.tm
.operand_types
[2];
3369 assert ((overlap2
& Imm
) == 0);
3370 i
.types
[2] = overlap2
;
3376 process_operands (void)
3378 /* Default segment register this instruction will use for memory
3379 accesses. 0 means unknown. This is only for optimizing out
3380 unnecessary segment overrides. */
3381 const seg_entry
*default_seg
= 0;
3383 /* The imul $imm, %reg instruction is converted into
3384 imul $imm, %reg, %reg, and the clr %reg instruction
3385 is converted into xor %reg, %reg. */
3386 if (i
.tm
.opcode_modifier
& RegKludge
)
3388 if ((i
.tm
.cpu_flags
& CpuSSE4_1
))
3390 /* The first operand in instruction blendvpd, blendvps and
3391 pblendvb in SSE4.1 is implicit and must be xmm0. */
3392 assert (i
.operands
== 3
3393 && i
.reg_operands
>= 2
3394 && i
.types
[0] == RegXMM
);
3395 if (i
.op
[0].regs
->reg_num
!= 0)
3398 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3399 i
.tm
.name
, register_prefix
);
3401 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3402 i
.tm
.name
, register_prefix
);
3407 i
.types
[0] = i
.types
[1];
3408 i
.types
[1] = i
.types
[2];
3412 /* We need to adjust fields in i.tm since they are used by
3413 build_modrm_byte. */
3414 i
.tm
.operand_types
[0] = i
.tm
.operand_types
[1];
3415 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[2];
3420 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
3421 /* Pretend we saw the extra register operand. */
3422 assert (i
.reg_operands
== 1
3423 && i
.op
[first_reg_op
+ 1].regs
== 0);
3424 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
3425 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
3431 if (i
.tm
.opcode_modifier
& ShortForm
)
3433 if (i
.types
[0] & (SReg2
| SReg3
))
3435 if (i
.tm
.base_opcode
== POP_SEG_SHORT
3436 && i
.op
[0].regs
->reg_num
== 1)
3438 as_bad (_("you can't `pop %%cs'"));
3441 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
3442 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
3447 /* The register or float register operand is in operand 0 or 1. */
3448 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
3449 /* Register goes in low 3 bits of opcode. */
3450 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
3451 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3453 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
3455 /* Warn about some common errors, but press on regardless.
3456 The first case can be generated by gcc (<= 2.8.1). */
3457 if (i
.operands
== 2)
3459 /* Reversed arguments on faddp, fsubp, etc. */
3460 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
3461 register_prefix
, i
.op
[1].regs
->reg_name
,
3462 register_prefix
, i
.op
[0].regs
->reg_name
);
3466 /* Extraneous `l' suffix on fp insn. */
3467 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
3468 register_prefix
, i
.op
[0].regs
->reg_name
);
3473 else if (i
.tm
.opcode_modifier
& Modrm
)
3475 /* The opcode is completed (modulo i.tm.extension_opcode which
3476 must be put into the modrm byte). Now, we make the modrm and
3477 index base bytes based on all the info we've collected. */
3479 default_seg
= build_modrm_byte ();
3481 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
3485 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
3487 /* For the string instructions that allow a segment override
3488 on one of their operands, the default segment is ds. */
3492 if (i
.tm
.base_opcode
== 0x8d /* lea */
3495 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
3497 /* If a segment was explicitly specified, and the specified segment
3498 is not the default, use an opcode prefix to select it. If we
3499 never figured out what the default segment is, then default_seg
3500 will be zero at this point, and the specified segment prefix will
3502 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
3504 if (!add_prefix (i
.seg
[0]->seg_prefix
))
3510 static const seg_entry
*
3511 build_modrm_byte (void)
3513 const seg_entry
*default_seg
= 0;
3515 /* i.reg_operands MUST be the number of real register operands;
3516 implicit registers do not count. */
3517 if (i
.reg_operands
== 2)
3519 unsigned int source
, dest
;
3527 /* When there are 3 operands, one of them may be immediate,
3528 which may be the first or the last operand. Otherwise,
3529 the first operand must be shift count register (cl). */
3530 assert (i
.imm_operands
== 1
3531 || (i
.imm_operands
== 0
3532 && (i
.types
[0] & ShiftCount
)));
3533 source
= (i
.types
[0] & (Imm
| ShiftCount
)) ? 1 : 0;
3536 /* When there are 4 operands, the first two must be immediate
3537 operands. The source operand will be the 3rd one. */
3538 assert (i
.imm_operands
== 2
3539 && (i
.types
[0] & Imm
)
3540 && (i
.types
[1] & Imm
));
3550 /* One of the register operands will be encoded in the i.tm.reg
3551 field, the other in the combined i.tm.mode and i.tm.regmem
3552 fields. If no form of this instruction supports a memory
3553 destination operand, then we assume the source operand may
3554 sometimes be a memory operand and so we need to store the
3555 destination in the i.rm.reg field. */
3556 if ((i
.tm
.operand_types
[dest
] & (AnyMem
| RegMem
)) == 0)
3558 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
3559 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
3560 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3562 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3567 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
3568 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
3569 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
3571 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
3574 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
3576 if (!((i
.types
[0] | i
.types
[1]) & Control
))
3578 i
.rex
&= ~(REX_R
| REX_B
);
3579 add_prefix (LOCK_PREFIX_OPCODE
);
3583 { /* If it's not 2 reg operands... */
3586 unsigned int fake_zero_displacement
= 0;
3589 for (op
= 0; op
< i
.operands
; op
++)
3590 if ((i
.types
[op
] & AnyMem
))
3592 assert (op
< i
.operands
);
3596 if (i
.base_reg
== 0)
3599 if (!i
.disp_operands
)
3600 fake_zero_displacement
= 1;
3601 if (i
.index_reg
== 0)
3603 /* Operand is just <disp> */
3604 if (flag_code
== CODE_64BIT
)
3606 /* 64bit mode overwrites the 32bit absolute
3607 addressing by RIP relative addressing and
3608 absolute addressing is encoded by one of the
3609 redundant SIB forms. */
3610 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3611 i
.sib
.base
= NO_BASE_REGISTER
;
3612 i
.sib
.index
= NO_INDEX_REGISTER
;
3613 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
3614 ? Disp32S
: Disp32
);
3616 else if ((flag_code
== CODE_16BIT
)
3617 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3619 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
3620 i
.types
[op
] = Disp16
;
3624 i
.rm
.regmem
= NO_BASE_REGISTER
;
3625 i
.types
[op
] = Disp32
;
3628 else /* !i.base_reg && i.index_reg */
3630 i
.sib
.index
= i
.index_reg
->reg_num
;
3631 i
.sib
.base
= NO_BASE_REGISTER
;
3632 i
.sib
.scale
= i
.log2_scale_factor
;
3633 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3634 i
.types
[op
] &= ~Disp
;
3635 if (flag_code
!= CODE_64BIT
)
3636 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
3638 i
.types
[op
] |= Disp32S
;
3639 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3643 /* RIP addressing for 64bit mode. */
3644 else if (i
.base_reg
->reg_type
== BaseIndex
)
3646 i
.rm
.regmem
= NO_BASE_REGISTER
;
3647 i
.types
[op
] &= ~ Disp
;
3648 i
.types
[op
] |= Disp32S
;
3649 i
.flags
[op
] |= Operand_PCrel
;
3650 if (! i
.disp_operands
)
3651 fake_zero_displacement
= 1;
3653 else if (i
.base_reg
->reg_type
& Reg16
)
3655 switch (i
.base_reg
->reg_num
)
3658 if (i
.index_reg
== 0)
3660 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3661 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
3665 if (i
.index_reg
== 0)
3668 if ((i
.types
[op
] & Disp
) == 0)
3670 /* fake (%bp) into 0(%bp) */
3671 i
.types
[op
] |= Disp8
;
3672 fake_zero_displacement
= 1;
3675 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3676 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
3678 default: /* (%si) -> 4 or (%di) -> 5 */
3679 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
3681 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3683 else /* i.base_reg and 32/64 bit mode */
3685 if (flag_code
== CODE_64BIT
3686 && (i
.types
[op
] & Disp
))
3687 i
.types
[op
] = ((i
.types
[op
] & Disp8
)
3688 | (i
.prefix
[ADDR_PREFIX
] == 0
3689 ? Disp32S
: Disp32
));
3691 i
.rm
.regmem
= i
.base_reg
->reg_num
;
3692 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
3694 i
.sib
.base
= i
.base_reg
->reg_num
;
3695 /* x86-64 ignores REX prefix bit here to avoid decoder
3697 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
3700 if (i
.disp_operands
== 0)
3702 fake_zero_displacement
= 1;
3703 i
.types
[op
] |= Disp8
;
3706 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
3710 i
.sib
.scale
= i
.log2_scale_factor
;
3711 if (i
.index_reg
== 0)
3713 /* <disp>(%esp) becomes two byte modrm with no index
3714 register. We've already stored the code for esp
3715 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3716 Any base register besides %esp will not use the
3717 extra modrm byte. */
3718 i
.sib
.index
= NO_INDEX_REGISTER
;
3719 #if !SCALE1_WHEN_NO_INDEX
3720 /* Another case where we force the second modrm byte. */
3721 if (i
.log2_scale_factor
)
3722 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3727 i
.sib
.index
= i
.index_reg
->reg_num
;
3728 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
3729 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
3734 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3735 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
3738 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
3741 if (fake_zero_displacement
)
3743 /* Fakes a zero displacement assuming that i.types[op]
3744 holds the correct displacement size. */
3747 assert (i
.op
[op
].disps
== 0);
3748 exp
= &disp_expressions
[i
.disp_operands
++];
3749 i
.op
[op
].disps
= exp
;
3750 exp
->X_op
= O_constant
;
3751 exp
->X_add_number
= 0;
3752 exp
->X_add_symbol
= (symbolS
*) 0;
3753 exp
->X_op_symbol
= (symbolS
*) 0;
3757 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3758 (if any) based on i.tm.extension_opcode. Again, we must be
3759 careful to make sure that segment/control/debug/test/MMX
3760 registers are coded into the i.rm.reg field. */
3765 for (op
= 0; op
< i
.operands
; op
++)
3766 if ((i
.types
[op
] & (Reg
| RegMMX
| RegXMM
3768 | Control
| Debug
| Test
)))
3770 assert (op
< i
.operands
);
3772 /* If there is an extension opcode to put here, the register
3773 number must be put into the regmem field. */
3774 if (i
.tm
.extension_opcode
!= None
)
3776 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
3777 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3782 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
3783 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
3787 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3788 must set it to 3 to indicate this is a register operand
3789 in the regmem field. */
3790 if (!i
.mem_operands
)
3794 /* Fill in i.rm.reg field with extension opcode (if any). */
3795 if (i
.tm
.extension_opcode
!= None
)
3796 i
.rm
.reg
= i
.tm
.extension_opcode
;
3802 output_branch (void)
3807 relax_substateT subtype
;
3812 if (flag_code
== CODE_16BIT
)
3816 if (i
.prefix
[DATA_PREFIX
] != 0)
3822 /* Pentium4 branch hints. */
3823 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3824 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3829 if (i
.prefix
[REX_PREFIX
] != 0)
3835 if (i
.prefixes
!= 0 && !intel_syntax
)
3836 as_warn (_("skipping prefixes on this instruction"));
3838 /* It's always a symbol; End frag & setup for relax.
3839 Make sure there is enough room in this frag for the largest
3840 instruction we may generate in md_convert_frag. This is 2
3841 bytes for the opcode and room for the prefix and largest
3843 frag_grow (prefix
+ 2 + 4);
3844 /* Prefix and 1 opcode byte go in fr_fix. */
3845 p
= frag_more (prefix
+ 1);
3846 if (i
.prefix
[DATA_PREFIX
] != 0)
3847 *p
++ = DATA_PREFIX_OPCODE
;
3848 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
3849 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
3850 *p
++ = i
.prefix
[SEG_PREFIX
];
3851 if (i
.prefix
[REX_PREFIX
] != 0)
3852 *p
++ = i
.prefix
[REX_PREFIX
];
3853 *p
= i
.tm
.base_opcode
;
3855 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
3856 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
3857 else if ((cpu_arch_flags
& Cpu386
) != 0)
3858 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
3860 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
3863 sym
= i
.op
[0].disps
->X_add_symbol
;
3864 off
= i
.op
[0].disps
->X_add_number
;
3866 if (i
.op
[0].disps
->X_op
!= O_constant
3867 && i
.op
[0].disps
->X_op
!= O_symbol
)
3869 /* Handle complex expressions. */
3870 sym
= make_expr_symbol (i
.op
[0].disps
);
3874 /* 1 possible extra opcode + 4 byte displacement go in var part.
3875 Pass reloc in fr_var. */
3876 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
3886 if (i
.tm
.opcode_modifier
& JumpByte
)
3888 /* This is a loop or jecxz type instruction. */
3890 if (i
.prefix
[ADDR_PREFIX
] != 0)
3892 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
3895 /* Pentium4 branch hints. */
3896 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
3897 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
3899 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
3908 if (flag_code
== CODE_16BIT
)
3911 if (i
.prefix
[DATA_PREFIX
] != 0)
3913 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
3923 if (i
.prefix
[REX_PREFIX
] != 0)
3925 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
3929 if (i
.prefixes
!= 0 && !intel_syntax
)
3930 as_warn (_("skipping prefixes on this instruction"));
3932 p
= frag_more (1 + size
);
3933 *p
++ = i
.tm
.base_opcode
;
3935 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3936 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
3938 /* All jumps handled here are signed, but don't use a signed limit
3939 check for 32 and 16 bit jumps as we want to allow wrap around at
3940 4G and 64k respectively. */
3942 fixP
->fx_signed
= 1;
3946 output_interseg_jump (void)
3954 if (flag_code
== CODE_16BIT
)
3958 if (i
.prefix
[DATA_PREFIX
] != 0)
3964 if (i
.prefix
[REX_PREFIX
] != 0)
3974 if (i
.prefixes
!= 0 && !intel_syntax
)
3975 as_warn (_("skipping prefixes on this instruction"));
3977 /* 1 opcode; 2 segment; offset */
3978 p
= frag_more (prefix
+ 1 + 2 + size
);
3980 if (i
.prefix
[DATA_PREFIX
] != 0)
3981 *p
++ = DATA_PREFIX_OPCODE
;
3983 if (i
.prefix
[REX_PREFIX
] != 0)
3984 *p
++ = i
.prefix
[REX_PREFIX
];
3986 *p
++ = i
.tm
.base_opcode
;
3987 if (i
.op
[1].imms
->X_op
== O_constant
)
3989 offsetT n
= i
.op
[1].imms
->X_add_number
;
3992 && !fits_in_unsigned_word (n
)
3993 && !fits_in_signed_word (n
))
3995 as_bad (_("16-bit jump out of range"));
3998 md_number_to_chars (p
, n
, size
);
4001 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4002 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
4003 if (i
.op
[0].imms
->X_op
!= O_constant
)
4004 as_bad (_("can't handle non absolute segment in `%s'"),
4006 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
4012 fragS
*insn_start_frag
;
4013 offsetT insn_start_off
;
4015 /* Tie dwarf2 debug info to the address at the start of the insn.
4016 We can't do this after the insn has been output as the current
4017 frag may have been closed off. eg. by frag_var. */
4018 dwarf2_emit_insn (0);
4020 insn_start_frag
= frag_now
;
4021 insn_start_off
= frag_now_fix ();
4024 if (i
.tm
.opcode_modifier
& Jump
)
4026 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
4028 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
4029 output_interseg_jump ();
4032 /* Output normal instructions here. */
4035 unsigned int prefix
;
4037 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
4038 SSE4 instructions have 3 bytes. We may use one more higher
4039 byte to specify a prefix the instruction requires. Exclude
4040 instructions which are in both SSE4 and ABM. */
4041 if ((i
.tm
.cpu_flags
& (CpuSSSE3
| CpuSSE4
)) != 0
4042 && (i
.tm
.cpu_flags
& CpuABM
) == 0)
4044 if (i
.tm
.base_opcode
& 0xff000000)
4046 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
4050 else if ((i
.tm
.base_opcode
& 0xff0000) != 0)
4052 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
4053 if ((i
.tm
.cpu_flags
& CpuPadLock
) != 0)
4056 if (prefix
!= REPE_PREFIX_OPCODE
4057 || i
.prefix
[LOCKREP_PREFIX
] != REPE_PREFIX_OPCODE
)
4058 add_prefix (prefix
);
4061 add_prefix (prefix
);
4064 /* The prefix bytes. */
4066 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
4072 md_number_to_chars (p
, (valueT
) *q
, 1);
4076 /* Now the opcode; be careful about word order here! */
4077 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
4079 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
4083 if ((i
.tm
.cpu_flags
& (CpuSSSE3
| CpuSSE4
)) != 0
4084 && (i
.tm
.cpu_flags
& CpuABM
) == 0)
4087 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
4092 /* Put out high byte first: can't use md_number_to_chars! */
4093 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
4094 *p
= i
.tm
.base_opcode
& 0xff;
4097 /* Now the modrm byte and sib byte (if present). */
4098 if (i
.tm
.opcode_modifier
& Modrm
)
4101 md_number_to_chars (p
,
4102 (valueT
) (i
.rm
.regmem
<< 0
4106 /* If i.rm.regmem == ESP (4)
4107 && i.rm.mode != (Register mode)
4109 ==> need second modrm byte. */
4110 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
4112 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
4115 md_number_to_chars (p
,
4116 (valueT
) (i
.sib
.base
<< 0
4118 | i
.sib
.scale
<< 6),
4123 if (i
.disp_operands
)
4124 output_disp (insn_start_frag
, insn_start_off
);
4127 output_imm (insn_start_frag
, insn_start_off
);
4133 pi ("" /*line*/, &i
);
4135 #endif /* DEBUG386 */
4138 /* Return the size of the displacement operand N. */
4141 disp_size (unsigned int n
)
4144 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
4147 if (i
.types
[n
] & Disp8
)
4149 if (i
.types
[n
] & Disp64
)
4155 /* Return the size of the immediate operand N. */
4158 imm_size (unsigned int n
)
4161 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
4164 if (i
.types
[n
] & (Imm8
| Imm8S
))
4166 if (i
.types
[n
] & Imm64
)
4173 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
4178 for (n
= 0; n
< i
.operands
; n
++)
4180 if (i
.types
[n
] & Disp
)
4182 if (i
.op
[n
].disps
->X_op
== O_constant
)
4184 int size
= disp_size (n
);
4187 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
4189 p
= frag_more (size
);
4190 md_number_to_chars (p
, val
, size
);
4194 enum bfd_reloc_code_real reloc_type
;
4195 int size
= disp_size (n
);
4196 int sign
= (i
.types
[n
] & Disp32S
) != 0;
4197 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
4199 /* We can't have 8 bit displacement here. */
4200 assert ((i
.types
[n
] & Disp8
) == 0);
4202 /* The PC relative address is computed relative
4203 to the instruction boundary, so in case immediate
4204 fields follows, we need to adjust the value. */
4205 if (pcrel
&& i
.imm_operands
)
4210 for (n1
= 0; n1
< i
.operands
; n1
++)
4211 if (i
.types
[n1
] & Imm
)
4213 /* Only one immediate is allowed for PC
4214 relative address. */
4217 i
.op
[n
].disps
->X_add_number
-= sz
;
4219 /* We should find the immediate. */
4223 p
= frag_more (size
);
4224 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
4226 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
4227 && (((reloc_type
== BFD_RELOC_32
4228 || reloc_type
== BFD_RELOC_X86_64_32S
4229 || (reloc_type
== BFD_RELOC_64
4231 && (i
.op
[n
].disps
->X_op
== O_symbol
4232 || (i
.op
[n
].disps
->X_op
== O_add
4233 && ((symbol_get_value_expression
4234 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
4236 || reloc_type
== BFD_RELOC_32_PCREL
))
4240 if (insn_start_frag
== frag_now
)
4241 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4246 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4247 for (fr
= insn_start_frag
->fr_next
;
4248 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4250 add
+= p
- frag_now
->fr_literal
;
4255 reloc_type
= BFD_RELOC_386_GOTPC
;
4256 i
.op
[n
].imms
->X_add_number
+= add
;
4258 else if (reloc_type
== BFD_RELOC_64
)
4259 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4261 /* Don't do the adjustment for x86-64, as there
4262 the pcrel addressing is relative to the _next_
4263 insn, and that is taken care of in other code. */
4264 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4266 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4267 i
.op
[n
].disps
, pcrel
, reloc_type
);
4274 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
4279 for (n
= 0; n
< i
.operands
; n
++)
4281 if (i
.types
[n
] & Imm
)
4283 if (i
.op
[n
].imms
->X_op
== O_constant
)
4285 int size
= imm_size (n
);
4288 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
4290 p
= frag_more (size
);
4291 md_number_to_chars (p
, val
, size
);
4295 /* Not absolute_section.
4296 Need a 32-bit fixup (don't support 8bit
4297 non-absolute imms). Try to support other
4299 enum bfd_reloc_code_real reloc_type
;
4300 int size
= imm_size (n
);
4303 if ((i
.types
[n
] & (Imm32S
))
4304 && (i
.suffix
== QWORD_MNEM_SUFFIX
4305 || (!i
.suffix
&& (i
.tm
.opcode_modifier
& No_lSuf
))))
4310 p
= frag_more (size
);
4311 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
4313 /* This is tough to explain. We end up with this one if we
4314 * have operands that look like
4315 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4316 * obtain the absolute address of the GOT, and it is strongly
4317 * preferable from a performance point of view to avoid using
4318 * a runtime relocation for this. The actual sequence of
4319 * instructions often look something like:
4324 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4326 * The call and pop essentially return the absolute address
4327 * of the label .L66 and store it in %ebx. The linker itself
4328 * will ultimately change the first operand of the addl so
4329 * that %ebx points to the GOT, but to keep things simple, the
4330 * .o file must have this operand set so that it generates not
4331 * the absolute address of .L66, but the absolute address of
4332 * itself. This allows the linker itself simply treat a GOTPC
4333 * relocation as asking for a pcrel offset to the GOT to be
4334 * added in, and the addend of the relocation is stored in the
4335 * operand field for the instruction itself.
4337 * Our job here is to fix the operand so that it would add
4338 * the correct offset so that %ebx would point to itself. The
4339 * thing that is tricky is that .-.L66 will point to the
4340 * beginning of the instruction, so we need to further modify
4341 * the operand so that it will point to itself. There are
4342 * other cases where you have something like:
4344 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4346 * and here no correction would be required. Internally in
4347 * the assembler we treat operands of this form as not being
4348 * pcrel since the '.' is explicitly mentioned, and I wonder
4349 * whether it would simplify matters to do it this way. Who
4350 * knows. In earlier versions of the PIC patches, the
4351 * pcrel_adjust field was used to store the correction, but
4352 * since the expression is not pcrel, I felt it would be
4353 * confusing to do it this way. */
4355 if ((reloc_type
== BFD_RELOC_32
4356 || reloc_type
== BFD_RELOC_X86_64_32S
4357 || reloc_type
== BFD_RELOC_64
)
4359 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
4360 && (i
.op
[n
].imms
->X_op
== O_symbol
4361 || (i
.op
[n
].imms
->X_op
== O_add
4362 && ((symbol_get_value_expression
4363 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
4368 if (insn_start_frag
== frag_now
)
4369 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
4374 add
= insn_start_frag
->fr_fix
- insn_start_off
;
4375 for (fr
= insn_start_frag
->fr_next
;
4376 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
4378 add
+= p
- frag_now
->fr_literal
;
4382 reloc_type
= BFD_RELOC_386_GOTPC
;
4384 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
4386 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
4387 i
.op
[n
].imms
->X_add_number
+= add
;
4389 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
4390 i
.op
[n
].imms
, 0, reloc_type
);
4396 /* x86_cons_fix_new is called via the expression parsing code when a
4397 reloc is needed. We use this hook to get the correct .got reloc. */
4398 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
4399 static int cons_sign
= -1;
4402 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
4405 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
4407 got_reloc
= NO_RELOC
;
4410 if (exp
->X_op
== O_secrel
)
4412 exp
->X_op
= O_symbol
;
4413 r
= BFD_RELOC_32_SECREL
;
4417 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
4420 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4421 # define lex_got(reloc, adjust, types) NULL
4423 /* Parse operands of the form
4424 <symbol>@GOTOFF+<nnn>
4425 and similar .plt or .got references.
4427 If we find one, set up the correct relocation in RELOC and copy the
4428 input string, minus the `@GOTOFF' into a malloc'd buffer for
4429 parsing by the calling routine. Return this buffer, and if ADJUST
4430 is non-null set it to the length of the string we removed from the
4431 input line. Otherwise return NULL. */
4433 lex_got (enum bfd_reloc_code_real
*reloc
,
4435 unsigned int *types
)
4437 /* Some of the relocations depend on the size of what field is to
4438 be relocated. But in our callers i386_immediate and i386_displacement
4439 we don't yet know the operand size (this will be set by insn
4440 matching). Hence we record the word32 relocation here,
4441 and adjust the reloc according to the real size in reloc(). */
4442 static const struct {
4444 const enum bfd_reloc_code_real rel
[2];
4445 const unsigned int types64
;
4448 BFD_RELOC_X86_64_PLTOFF64
},
4450 { "PLT", { BFD_RELOC_386_PLT32
,
4451 BFD_RELOC_X86_64_PLT32
},
4452 Imm32
| Imm32S
| Disp32
},
4454 BFD_RELOC_X86_64_GOTPLT64
},
4456 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
4457 BFD_RELOC_X86_64_GOTOFF64
},
4460 BFD_RELOC_X86_64_GOTPCREL
},
4461 Imm32
| Imm32S
| Disp32
},
4462 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
4463 BFD_RELOC_X86_64_TLSGD
},
4464 Imm32
| Imm32S
| Disp32
},
4465 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
4469 BFD_RELOC_X86_64_TLSLD
},
4470 Imm32
| Imm32S
| Disp32
},
4471 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
4472 BFD_RELOC_X86_64_GOTTPOFF
},
4473 Imm32
| Imm32S
| Disp32
},
4474 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
4475 BFD_RELOC_X86_64_TPOFF32
},
4476 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4477 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
4480 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
4481 BFD_RELOC_X86_64_DTPOFF32
},
4482 Imm32
| Imm32S
| Imm64
| Disp32
| Disp64
},
4483 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
4486 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
4489 { "GOT", { BFD_RELOC_386_GOT32
,
4490 BFD_RELOC_X86_64_GOT32
},
4491 Imm32
| Imm32S
| Disp32
| Imm64
},
4492 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
4493 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
4494 Imm32
| Imm32S
| Disp32
},
4495 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
4496 BFD_RELOC_X86_64_TLSDESC_CALL
},
4497 Imm32
| Imm32S
| Disp32
}
4505 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
4506 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
4509 for (j
= 0; j
< sizeof (gotrel
) / sizeof (gotrel
[0]); j
++)
4513 len
= strlen (gotrel
[j
].str
);
4514 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
4516 if (gotrel
[j
].rel
[object_64bit
] != 0)
4519 char *tmpbuf
, *past_reloc
;
4521 *reloc
= gotrel
[j
].rel
[object_64bit
];
4527 if (flag_code
!= CODE_64BIT
)
4528 *types
= Imm32
| Disp32
;
4530 *types
= gotrel
[j
].types64
;
4533 if (GOT_symbol
== NULL
)
4534 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
4536 /* The length of the first part of our input line. */
4537 first
= cp
- input_line_pointer
;
4539 /* The second part goes from after the reloc token until
4540 (and including) an end_of_line char or comma. */
4541 past_reloc
= cp
+ 1 + len
;
4543 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
4545 second
= cp
+ 1 - past_reloc
;
4547 /* Allocate and copy string. The trailing NUL shouldn't
4548 be necessary, but be safe. */
4549 tmpbuf
= xmalloc (first
+ second
+ 2);
4550 memcpy (tmpbuf
, input_line_pointer
, first
);
4551 if (second
!= 0 && *past_reloc
!= ' ')
4552 /* Replace the relocation token with ' ', so that
4553 errors like foo@GOTOFF1 will be detected. */
4554 tmpbuf
[first
++] = ' ';
4555 memcpy (tmpbuf
+ first
, past_reloc
, second
);
4556 tmpbuf
[first
+ second
] = '\0';
4560 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4561 gotrel
[j
].str
, 1 << (5 + object_64bit
));
4566 /* Might be a symbol version string. Don't as_bad here. */
4571 x86_cons (expressionS
*exp
, int size
)
4573 if (size
== 4 || (object_64bit
&& size
== 8))
4575 /* Handle @GOTOFF and the like in an expression. */
4577 char *gotfree_input_line
;
4580 save
= input_line_pointer
;
4581 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
4582 if (gotfree_input_line
)
4583 input_line_pointer
= gotfree_input_line
;
4587 if (gotfree_input_line
)
4589 /* expression () has merrily parsed up to the end of line,
4590 or a comma - in the wrong buffer. Transfer how far
4591 input_line_pointer has moved to the right buffer. */
4592 input_line_pointer
= (save
4593 + (input_line_pointer
- gotfree_input_line
)
4595 free (gotfree_input_line
);
4596 if (exp
->X_op
== O_constant
4597 || exp
->X_op
== O_absent
4598 || exp
->X_op
== O_illegal
4599 || exp
->X_op
== O_register
4600 || exp
->X_op
== O_big
)
4602 char c
= *input_line_pointer
;
4603 *input_line_pointer
= 0;
4604 as_bad (_("missing or invalid expression `%s'"), save
);
4605 *input_line_pointer
= c
;
4614 static void signed_cons (int size
)
4616 if (flag_code
== CODE_64BIT
)
4624 pe_directive_secrel (dummy
)
4625 int dummy ATTRIBUTE_UNUSED
;
4632 if (exp
.X_op
== O_symbol
)
4633 exp
.X_op
= O_secrel
;
4635 emit_expr (&exp
, 4);
4637 while (*input_line_pointer
++ == ',');
4639 input_line_pointer
--;
4640 demand_empty_rest_of_line ();
4645 i386_immediate (char *imm_start
)
4647 char *save_input_line_pointer
;
4648 char *gotfree_input_line
;
4651 unsigned int types
= ~0U;
4653 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
4655 as_bad (_("at most %d immediate operands are allowed"),
4656 MAX_IMMEDIATE_OPERANDS
);
4660 exp
= &im_expressions
[i
.imm_operands
++];
4661 i
.op
[this_operand
].imms
= exp
;
4663 if (is_space_char (*imm_start
))
4666 save_input_line_pointer
= input_line_pointer
;
4667 input_line_pointer
= imm_start
;
4669 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4670 if (gotfree_input_line
)
4671 input_line_pointer
= gotfree_input_line
;
4673 exp_seg
= expression (exp
);
4676 if (*input_line_pointer
)
4677 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4679 input_line_pointer
= save_input_line_pointer
;
4680 if (gotfree_input_line
)
4681 free (gotfree_input_line
);
4683 if (exp
->X_op
== O_absent
4684 || exp
->X_op
== O_illegal
4685 || exp
->X_op
== O_big
4686 || (gotfree_input_line
4687 && (exp
->X_op
== O_constant
4688 || exp
->X_op
== O_register
)))
4690 as_bad (_("missing or invalid immediate expression `%s'"),
4694 else if (exp
->X_op
== O_constant
)
4696 /* Size it properly later. */
4697 i
.types
[this_operand
] |= Imm64
;
4698 /* If BFD64, sign extend val. */
4699 if (!use_rela_relocations
4700 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
4702 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
4704 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4705 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
4706 && exp_seg
!= absolute_section
4707 && exp_seg
!= text_section
4708 && exp_seg
!= data_section
4709 && exp_seg
!= bss_section
4710 && exp_seg
!= undefined_section
4711 && !bfd_is_com_section (exp_seg
))
4713 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4717 else if (!intel_syntax
&& exp
->X_op
== O_register
)
4719 as_bad (_("illegal immediate register operand %s"), imm_start
);
4724 /* This is an address. The size of the address will be
4725 determined later, depending on destination register,
4726 suffix, or the default for the section. */
4727 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
4728 i
.types
[this_operand
] &= types
;
4735 i386_scale (char *scale
)
4738 char *save
= input_line_pointer
;
4740 input_line_pointer
= scale
;
4741 val
= get_absolute_expression ();
4746 i
.log2_scale_factor
= 0;
4749 i
.log2_scale_factor
= 1;
4752 i
.log2_scale_factor
= 2;
4755 i
.log2_scale_factor
= 3;
4759 char sep
= *input_line_pointer
;
4761 *input_line_pointer
= '\0';
4762 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4764 *input_line_pointer
= sep
;
4765 input_line_pointer
= save
;
4769 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
4771 as_warn (_("scale factor of %d without an index register"),
4772 1 << i
.log2_scale_factor
);
4773 #if SCALE1_WHEN_NO_INDEX
4774 i
.log2_scale_factor
= 0;
4777 scale
= input_line_pointer
;
4778 input_line_pointer
= save
;
4783 i386_displacement (char *disp_start
, char *disp_end
)
4787 char *save_input_line_pointer
;
4788 char *gotfree_input_line
;
4789 int bigdisp
, override
;
4790 unsigned int types
= Disp
;
4793 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
4795 as_bad (_("at most %d displacement operands are allowed"),
4796 MAX_MEMORY_OPERANDS
);
4800 if ((i
.types
[this_operand
] & JumpAbsolute
)
4801 || !(current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
)))
4804 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
4808 /* For PC-relative branches, the width of the displacement
4809 is dependent upon data size, not address size. */
4811 override
= (i
.prefix
[DATA_PREFIX
] != 0);
4813 if (flag_code
== CODE_64BIT
)
4816 bigdisp
= ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
4818 : Disp32S
| Disp32
);
4820 bigdisp
= Disp64
| Disp32S
| Disp32
;
4827 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
4829 : LONG_MNEM_SUFFIX
));
4832 if ((flag_code
== CODE_16BIT
) ^ override
)
4835 i
.types
[this_operand
] |= bigdisp
;
4837 exp
= &disp_expressions
[i
.disp_operands
];
4838 i
.op
[this_operand
].disps
= exp
;
4840 save_input_line_pointer
= input_line_pointer
;
4841 input_line_pointer
= disp_start
;
4842 END_STRING_AND_SAVE (disp_end
);
4844 #ifndef GCC_ASM_O_HACK
4845 #define GCC_ASM_O_HACK 0
4848 END_STRING_AND_SAVE (disp_end
+ 1);
4849 if ((i
.types
[this_operand
] & BaseIndex
) != 0
4850 && displacement_string_end
[-1] == '+')
4852 /* This hack is to avoid a warning when using the "o"
4853 constraint within gcc asm statements.
4856 #define _set_tssldt_desc(n,addr,limit,type) \
4857 __asm__ __volatile__ ( \
4859 "movw %w1,2+%0\n\t" \
4861 "movb %b1,4+%0\n\t" \
4862 "movb %4,5+%0\n\t" \
4863 "movb $0,6+%0\n\t" \
4864 "movb %h1,7+%0\n\t" \
4866 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4868 This works great except that the output assembler ends
4869 up looking a bit weird if it turns out that there is
4870 no offset. You end up producing code that looks like:
4883 So here we provide the missing zero. */
4885 *displacement_string_end
= '0';
4888 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
4889 if (gotfree_input_line
)
4890 input_line_pointer
= gotfree_input_line
;
4892 exp_seg
= expression (exp
);
4895 if (*input_line_pointer
)
4896 as_bad (_("junk `%s' after expression"), input_line_pointer
);
4898 RESTORE_END_STRING (disp_end
+ 1);
4900 input_line_pointer
= save_input_line_pointer
;
4901 if (gotfree_input_line
)
4902 free (gotfree_input_line
);
4905 /* We do this to make sure that the section symbol is in
4906 the symbol table. We will ultimately change the relocation
4907 to be relative to the beginning of the section. */
4908 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
4909 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
4910 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4912 if (exp
->X_op
!= O_symbol
)
4915 if (S_IS_LOCAL (exp
->X_add_symbol
)
4916 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
4917 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
4918 exp
->X_op
= O_subtract
;
4919 exp
->X_op_symbol
= GOT_symbol
;
4920 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
4921 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
4922 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
4923 i
.reloc
[this_operand
] = BFD_RELOC_64
;
4925 i
.reloc
[this_operand
] = BFD_RELOC_32
;
4928 else if (exp
->X_op
== O_absent
4929 || exp
->X_op
== O_illegal
4930 || exp
->X_op
== O_big
4931 || (gotfree_input_line
4932 && (exp
->X_op
== O_constant
4933 || exp
->X_op
== O_register
)))
4936 as_bad (_("missing or invalid displacement expression `%s'"),
4941 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4942 else if (exp
->X_op
!= O_constant
4943 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
4944 && exp_seg
!= absolute_section
4945 && exp_seg
!= text_section
4946 && exp_seg
!= data_section
4947 && exp_seg
!= bss_section
4948 && exp_seg
!= undefined_section
4949 && !bfd_is_com_section (exp_seg
))
4951 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
4956 RESTORE_END_STRING (disp_end
);
4958 if (!(i
.types
[this_operand
] & ~Disp
))
4959 i
.types
[this_operand
] &= types
;
4964 /* Make sure the memory operand we've been dealt is valid.
4965 Return 1 on success, 0 on a failure. */
4968 i386_index_check (const char *operand_string
)
4971 #if INFER_ADDR_PREFIX
4977 if (flag_code
== CODE_64BIT
)
4979 unsigned RegXX
= (i
.prefix
[ADDR_PREFIX
] == 0 ? Reg64
: Reg32
);
4982 && ((i
.base_reg
->reg_type
& RegXX
) == 0)
4983 && (i
.base_reg
->reg_type
!= BaseIndex
4986 && ((i
.index_reg
->reg_type
& (RegXX
| BaseIndex
))
4987 != (RegXX
| BaseIndex
))))
4992 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4996 && ((i
.base_reg
->reg_type
& (Reg16
| BaseIndex
))
4997 != (Reg16
| BaseIndex
)))
4999 && (((i
.index_reg
->reg_type
& (Reg16
| BaseIndex
))
5000 != (Reg16
| BaseIndex
))
5002 && i
.base_reg
->reg_num
< 6
5003 && i
.index_reg
->reg_num
>= 6
5004 && i
.log2_scale_factor
== 0))))
5011 && (i
.base_reg
->reg_type
& Reg32
) != Reg32
)
5013 && ((i
.index_reg
->reg_type
& (Reg32
| BaseIndex
))
5014 != (Reg32
| BaseIndex
))))
5020 #if INFER_ADDR_PREFIX
5021 if (i
.prefix
[ADDR_PREFIX
] == 0)
5023 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
5025 /* Change the size of any displacement too. At most one of
5026 Disp16 or Disp32 is set.
5027 FIXME. There doesn't seem to be any real need for separate
5028 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
5029 Removing them would probably clean up the code quite a lot. */
5030 if (flag_code
!= CODE_64BIT
5031 && (i
.types
[this_operand
] & (Disp16
| Disp32
)))
5032 i
.types
[this_operand
] ^= (Disp16
| Disp32
);
5037 as_bad (_("`%s' is not a valid base/index expression"),
5041 as_bad (_("`%s' is not a valid %s bit base/index expression"),
5043 flag_code_names
[flag_code
]);
5048 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
5052 i386_operand (char *operand_string
)
5056 char *op_string
= operand_string
;
5058 if (is_space_char (*op_string
))
5061 /* We check for an absolute prefix (differentiating,
5062 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
5063 if (*op_string
== ABSOLUTE_PREFIX
)
5066 if (is_space_char (*op_string
))
5068 i
.types
[this_operand
] |= JumpAbsolute
;
5071 /* Check if operand is a register. */
5072 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
5074 /* Check for a segment override by searching for ':' after a
5075 segment register. */
5077 if (is_space_char (*op_string
))
5079 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
5084 i
.seg
[i
.mem_operands
] = &es
;
5087 i
.seg
[i
.mem_operands
] = &cs
;
5090 i
.seg
[i
.mem_operands
] = &ss
;
5093 i
.seg
[i
.mem_operands
] = &ds
;
5096 i
.seg
[i
.mem_operands
] = &fs
;
5099 i
.seg
[i
.mem_operands
] = &gs
;
5103 /* Skip the ':' and whitespace. */
5105 if (is_space_char (*op_string
))
5108 if (!is_digit_char (*op_string
)
5109 && !is_identifier_char (*op_string
)
5110 && *op_string
!= '('
5111 && *op_string
!= ABSOLUTE_PREFIX
)
5113 as_bad (_("bad memory operand `%s'"), op_string
);
5116 /* Handle case of %es:*foo. */
5117 if (*op_string
== ABSOLUTE_PREFIX
)
5120 if (is_space_char (*op_string
))
5122 i
.types
[this_operand
] |= JumpAbsolute
;
5124 goto do_memory_reference
;
5128 as_bad (_("junk `%s' after register"), op_string
);
5131 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
5132 i
.op
[this_operand
].regs
= r
;
5135 else if (*op_string
== REGISTER_PREFIX
)
5137 as_bad (_("bad register name `%s'"), op_string
);
5140 else if (*op_string
== IMMEDIATE_PREFIX
)
5143 if (i
.types
[this_operand
] & JumpAbsolute
)
5145 as_bad (_("immediate operand illegal with absolute jump"));
5148 if (!i386_immediate (op_string
))
5151 else if (is_digit_char (*op_string
)
5152 || is_identifier_char (*op_string
)
5153 || *op_string
== '(')
5155 /* This is a memory reference of some sort. */
5158 /* Start and end of displacement string expression (if found). */
5159 char *displacement_string_start
;
5160 char *displacement_string_end
;
5162 do_memory_reference
:
5163 if ((i
.mem_operands
== 1
5164 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5165 || i
.mem_operands
== 2)
5167 as_bad (_("too many memory references for `%s'"),
5168 current_templates
->start
->name
);
5172 /* Check for base index form. We detect the base index form by
5173 looking for an ')' at the end of the operand, searching
5174 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5176 base_string
= op_string
+ strlen (op_string
);
5179 if (is_space_char (*base_string
))
5182 /* If we only have a displacement, set-up for it to be parsed later. */
5183 displacement_string_start
= op_string
;
5184 displacement_string_end
= base_string
+ 1;
5186 if (*base_string
== ')')
5189 unsigned int parens_balanced
= 1;
5190 /* We've already checked that the number of left & right ()'s are
5191 equal, so this loop will not be infinite. */
5195 if (*base_string
== ')')
5197 if (*base_string
== '(')
5200 while (parens_balanced
);
5202 temp_string
= base_string
;
5204 /* Skip past '(' and whitespace. */
5206 if (is_space_char (*base_string
))
5209 if (*base_string
== ','
5210 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
5213 displacement_string_end
= temp_string
;
5215 i
.types
[this_operand
] |= BaseIndex
;
5219 base_string
= end_op
;
5220 if (is_space_char (*base_string
))
5224 /* There may be an index reg or scale factor here. */
5225 if (*base_string
== ',')
5228 if (is_space_char (*base_string
))
5231 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
5234 base_string
= end_op
;
5235 if (is_space_char (*base_string
))
5237 if (*base_string
== ',')
5240 if (is_space_char (*base_string
))
5243 else if (*base_string
!= ')')
5245 as_bad (_("expecting `,' or `)' "
5246 "after index register in `%s'"),
5251 else if (*base_string
== REGISTER_PREFIX
)
5253 as_bad (_("bad register name `%s'"), base_string
);
5257 /* Check for scale factor. */
5258 if (*base_string
!= ')')
5260 char *end_scale
= i386_scale (base_string
);
5265 base_string
= end_scale
;
5266 if (is_space_char (*base_string
))
5268 if (*base_string
!= ')')
5270 as_bad (_("expecting `)' "
5271 "after scale factor in `%s'"),
5276 else if (!i
.index_reg
)
5278 as_bad (_("expecting index register or scale factor "
5279 "after `,'; got '%c'"),
5284 else if (*base_string
!= ')')
5286 as_bad (_("expecting `,' or `)' "
5287 "after base register in `%s'"),
5292 else if (*base_string
== REGISTER_PREFIX
)
5294 as_bad (_("bad register name `%s'"), base_string
);
5299 /* If there's an expression beginning the operand, parse it,
5300 assuming displacement_string_start and
5301 displacement_string_end are meaningful. */
5302 if (displacement_string_start
!= displacement_string_end
)
5304 if (!i386_displacement (displacement_string_start
,
5305 displacement_string_end
))
5309 /* Special case for (%dx) while doing input/output op. */
5311 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
5313 && i
.log2_scale_factor
== 0
5314 && i
.seg
[i
.mem_operands
] == 0
5315 && (i
.types
[this_operand
] & Disp
) == 0)
5317 i
.types
[this_operand
] = InOutPortReg
;
5321 if (i386_index_check (operand_string
) == 0)
5327 /* It's not a memory operand; argh! */
5328 as_bad (_("invalid char %s beginning operand %d `%s'"),
5329 output_invalid (*op_string
),
5334 return 1; /* Normal return. */
5337 /* md_estimate_size_before_relax()
5339 Called just before relax() for rs_machine_dependent frags. The x86
5340 assembler uses these frags to handle variable size jump
5343 Any symbol that is now undefined will not become defined.
5344 Return the correct fr_subtype in the frag.
5345 Return the initial "guess for variable size of frag" to caller.
5346 The guess is actually the growth beyond the fixed part. Whatever
5347 we do to grow the fixed or variable part contributes to our
5351 md_estimate_size_before_relax (fragP
, segment
)
5355 /* We've already got fragP->fr_subtype right; all we have to do is
5356 check for un-relaxable symbols. On an ELF system, we can't relax
5357 an externally visible symbol, because it may be overridden by a
5359 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
5360 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5362 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
5363 || S_IS_WEAK (fragP
->fr_symbol
)))
5367 /* Symbol is undefined in this segment, or we need to keep a
5368 reloc so that weak symbols can be overridden. */
5369 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
5370 enum bfd_reloc_code_real reloc_type
;
5371 unsigned char *opcode
;
5374 if (fragP
->fr_var
!= NO_RELOC
)
5375 reloc_type
= fragP
->fr_var
;
5377 reloc_type
= BFD_RELOC_16_PCREL
;
5379 reloc_type
= BFD_RELOC_32_PCREL
;
5381 old_fr_fix
= fragP
->fr_fix
;
5382 opcode
= (unsigned char *) fragP
->fr_opcode
;
5384 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
5387 /* Make jmp (0xeb) a (d)word displacement jump. */
5389 fragP
->fr_fix
+= size
;
5390 fix_new (fragP
, old_fr_fix
, size
,
5392 fragP
->fr_offset
, 1,
5398 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
5400 /* Negate the condition, and branch past an
5401 unconditional jump. */
5404 /* Insert an unconditional jump. */
5406 /* We added two extra opcode bytes, and have a two byte
5408 fragP
->fr_fix
+= 2 + 2;
5409 fix_new (fragP
, old_fr_fix
+ 2, 2,
5411 fragP
->fr_offset
, 1,
5418 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
5423 fixP
= fix_new (fragP
, old_fr_fix
, 1,
5425 fragP
->fr_offset
, 1,
5427 fixP
->fx_signed
= 1;
5431 /* This changes the byte-displacement jump 0x7N
5432 to the (d)word-displacement jump 0x0f,0x8N. */
5433 opcode
[1] = opcode
[0] + 0x10;
5434 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5435 /* We've added an opcode byte. */
5436 fragP
->fr_fix
+= 1 + size
;
5437 fix_new (fragP
, old_fr_fix
+ 1, size
,
5439 fragP
->fr_offset
, 1,
5444 BAD_CASE (fragP
->fr_subtype
);
5448 return fragP
->fr_fix
- old_fr_fix
;
5451 /* Guess size depending on current relax state. Initially the relax
5452 state will correspond to a short jump and we return 1, because
5453 the variable part of the frag (the branch offset) is one byte
5454 long. However, we can relax a section more than once and in that
5455 case we must either set fr_subtype back to the unrelaxed state,
5456 or return the value for the appropriate branch. */
5457 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5460 /* Called after relax() is finished.
5462 In: Address of frag.
5463 fr_type == rs_machine_dependent.
5464 fr_subtype is what the address relaxed to.
5466 Out: Any fixSs and constants are set up.
5467 Caller will turn frag into a ".space 0". */
5470 md_convert_frag (abfd
, sec
, fragP
)
5471 bfd
*abfd ATTRIBUTE_UNUSED
;
5472 segT sec ATTRIBUTE_UNUSED
;
5475 unsigned char *opcode
;
5476 unsigned char *where_to_put_displacement
= NULL
;
5477 offsetT target_address
;
5478 offsetT opcode_address
;
5479 unsigned int extension
= 0;
5480 offsetT displacement_from_opcode_start
;
5482 opcode
= (unsigned char *) fragP
->fr_opcode
;
5484 /* Address we want to reach in file space. */
5485 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
5487 /* Address opcode resides at in file space. */
5488 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
5490 /* Displacement from opcode start to fill into instruction. */
5491 displacement_from_opcode_start
= target_address
- opcode_address
;
5493 if ((fragP
->fr_subtype
& BIG
) == 0)
5495 /* Don't have to change opcode. */
5496 extension
= 1; /* 1 opcode + 1 displacement */
5497 where_to_put_displacement
= &opcode
[1];
5501 if (no_cond_jump_promotion
5502 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
5503 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5504 _("long jump required"));
5506 switch (fragP
->fr_subtype
)
5508 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
5509 extension
= 4; /* 1 opcode + 4 displacement */
5511 where_to_put_displacement
= &opcode
[1];
5514 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
5515 extension
= 2; /* 1 opcode + 2 displacement */
5517 where_to_put_displacement
= &opcode
[1];
5520 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
5521 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
5522 extension
= 5; /* 2 opcode + 4 displacement */
5523 opcode
[1] = opcode
[0] + 0x10;
5524 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5525 where_to_put_displacement
= &opcode
[2];
5528 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
5529 extension
= 3; /* 2 opcode + 2 displacement */
5530 opcode
[1] = opcode
[0] + 0x10;
5531 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
5532 where_to_put_displacement
= &opcode
[2];
5535 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
5540 where_to_put_displacement
= &opcode
[3];
5544 BAD_CASE (fragP
->fr_subtype
);
5549 /* If size if less then four we are sure that the operand fits,
5550 but if it's 4, then it could be that the displacement is larger
5552 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
5554 && ((addressT
) (displacement_from_opcode_start
- extension
5555 + ((addressT
) 1 << 31))
5556 > (((addressT
) 2 << 31) - 1)))
5558 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5559 _("jump target out of range"));
5560 /* Make us emit 0. */
5561 displacement_from_opcode_start
= extension
;
5563 /* Now put displacement after opcode. */
5564 md_number_to_chars ((char *) where_to_put_displacement
,
5565 (valueT
) (displacement_from_opcode_start
- extension
),
5566 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
5567 fragP
->fr_fix
+= extension
;
5570 /* Size of byte displacement jmp. */
5571 int md_short_jump_size
= 2;
5573 /* Size of dword displacement jmp. */
5574 int md_long_jump_size
= 5;
5577 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5579 addressT from_addr
, to_addr
;
5580 fragS
*frag ATTRIBUTE_UNUSED
;
5581 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5585 offset
= to_addr
- (from_addr
+ 2);
5586 /* Opcode for byte-disp jump. */
5587 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
5588 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
5592 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
5594 addressT from_addr
, to_addr
;
5595 fragS
*frag ATTRIBUTE_UNUSED
;
5596 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
5600 offset
= to_addr
- (from_addr
+ 5);
5601 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
5602 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
5605 /* Apply a fixup (fixS) to segment data, once it has been determined
5606 by our caller that we have all the info we need to fix it up.
5608 On the 386, immediates, displacements, and data pointers are all in
5609 the same (little-endian) format, so we don't need to care about which
5613 md_apply_fix (fixP
, valP
, seg
)
5614 /* The fix we're to put in. */
5616 /* Pointer to the value of the bits. */
5618 /* Segment fix is from. */
5619 segT seg ATTRIBUTE_UNUSED
;
5621 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5622 valueT value
= *valP
;
5624 #if !defined (TE_Mach)
5627 switch (fixP
->fx_r_type
)
5633 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
5636 case BFD_RELOC_X86_64_32S
:
5637 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
5640 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
5643 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
5648 if (fixP
->fx_addsy
!= NULL
5649 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
5650 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
5651 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
5652 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
5653 && !use_rela_relocations
)
5655 /* This is a hack. There should be a better way to handle this.
5656 This covers for the fact that bfd_install_relocation will
5657 subtract the current location (for partial_inplace, PC relative
5658 relocations); see more below. */
5662 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
5665 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5667 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5670 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
5673 || (symbol_section_p (fixP
->fx_addsy
)
5674 && sym_seg
!= absolute_section
))
5675 && !generic_force_reloc (fixP
))
5677 /* Yes, we add the values in twice. This is because
5678 bfd_install_relocation subtracts them out again. I think
5679 bfd_install_relocation is broken, but I don't dare change
5681 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5685 #if defined (OBJ_COFF) && defined (TE_PE)
5686 /* For some reason, the PE format does not store a
5687 section address offset for a PC relative symbol. */
5688 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
5689 || S_IS_WEAK (fixP
->fx_addsy
))
5690 value
+= md_pcrel_from (fixP
);
5694 /* Fix a few things - the dynamic linker expects certain values here,
5695 and we must not disappoint it. */
5696 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5697 if (IS_ELF
&& fixP
->fx_addsy
)
5698 switch (fixP
->fx_r_type
)
5700 case BFD_RELOC_386_PLT32
:
5701 case BFD_RELOC_X86_64_PLT32
:
5702 /* Make the jump instruction point to the address of the operand. At
5703 runtime we merely add the offset to the actual PLT entry. */
5707 case BFD_RELOC_386_TLS_GD
:
5708 case BFD_RELOC_386_TLS_LDM
:
5709 case BFD_RELOC_386_TLS_IE_32
:
5710 case BFD_RELOC_386_TLS_IE
:
5711 case BFD_RELOC_386_TLS_GOTIE
:
5712 case BFD_RELOC_386_TLS_GOTDESC
:
5713 case BFD_RELOC_X86_64_TLSGD
:
5714 case BFD_RELOC_X86_64_TLSLD
:
5715 case BFD_RELOC_X86_64_GOTTPOFF
:
5716 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
5717 value
= 0; /* Fully resolved at runtime. No addend. */
5719 case BFD_RELOC_386_TLS_LE
:
5720 case BFD_RELOC_386_TLS_LDO_32
:
5721 case BFD_RELOC_386_TLS_LE_32
:
5722 case BFD_RELOC_X86_64_DTPOFF32
:
5723 case BFD_RELOC_X86_64_DTPOFF64
:
5724 case BFD_RELOC_X86_64_TPOFF32
:
5725 case BFD_RELOC_X86_64_TPOFF64
:
5726 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5729 case BFD_RELOC_386_TLS_DESC_CALL
:
5730 case BFD_RELOC_X86_64_TLSDESC_CALL
:
5731 value
= 0; /* Fully resolved at runtime. No addend. */
5732 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5736 case BFD_RELOC_386_GOT32
:
5737 case BFD_RELOC_X86_64_GOT32
:
5738 value
= 0; /* Fully resolved at runtime. No addend. */
5741 case BFD_RELOC_VTABLE_INHERIT
:
5742 case BFD_RELOC_VTABLE_ENTRY
:
5749 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5751 #endif /* !defined (TE_Mach) */
5753 /* Are we finished with this relocation now? */
5754 if (fixP
->fx_addsy
== NULL
)
5756 else if (use_rela_relocations
)
5758 fixP
->fx_no_overflow
= 1;
5759 /* Remember value for tc_gen_reloc. */
5760 fixP
->fx_addnumber
= value
;
5764 md_number_to_chars (p
, value
, fixP
->fx_size
);
5767 #define MAX_LITTLENUMS 6
5769 /* Turn the string pointed to by litP into a floating point constant
5770 of type TYPE, and emit the appropriate bytes. The number of
5771 LITTLENUMS emitted is stored in *SIZEP. An error message is
5772 returned, or NULL on OK. */
5775 md_atof (type
, litP
, sizeP
)
5781 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5782 LITTLENUM_TYPE
*wordP
;
5804 return _("Bad call to md_atof ()");
5806 t
= atof_ieee (input_line_pointer
, type
, words
);
5808 input_line_pointer
= t
;
5810 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
5811 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5812 the bigendian 386. */
5813 for (wordP
= words
+ prec
- 1; prec
--;)
5815 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
5816 litP
+= sizeof (LITTLENUM_TYPE
);
5821 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
5824 output_invalid (int c
)
5827 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5830 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
5831 "(0x%x)", (unsigned char) c
);
5832 return output_invalid_buf
;
5835 /* REG_STRING starts *before* REGISTER_PREFIX. */
5837 static const reg_entry
*
5838 parse_real_register (char *reg_string
, char **end_op
)
5840 char *s
= reg_string
;
5842 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
5845 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5846 if (*s
== REGISTER_PREFIX
)
5849 if (is_space_char (*s
))
5853 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
5855 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
5856 return (const reg_entry
*) NULL
;
5860 /* For naked regs, make sure that we are not dealing with an identifier.
5861 This prevents confusing an identifier like `eax_var' with register
5863 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
5864 return (const reg_entry
*) NULL
;
5868 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
5870 /* Handle floating point regs, allowing spaces in the (i) part. */
5871 if (r
== i386_regtab
/* %st is first entry of table */)
5873 if (is_space_char (*s
))
5878 if (is_space_char (*s
))
5880 if (*s
>= '0' && *s
<= '7')
5884 if (is_space_char (*s
))
5889 r
= hash_find (reg_hash
, "st(0)");
5894 /* We have "%st(" then garbage. */
5895 return (const reg_entry
*) NULL
;
5900 && ((r
->reg_flags
& (RegRex64
| RegRex
))
5901 || (r
->reg_type
& Reg64
))
5902 && (r
->reg_type
!= Control
|| !(cpu_arch_flags
& CpuSledgehammer
))
5903 && flag_code
!= CODE_64BIT
)
5904 return (const reg_entry
*) NULL
;
5909 /* REG_STRING starts *before* REGISTER_PREFIX. */
5911 static const reg_entry
*
5912 parse_register (char *reg_string
, char **end_op
)
5916 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5917 r
= parse_real_register (reg_string
, end_op
);
5922 char *save
= input_line_pointer
;
5926 input_line_pointer
= reg_string
;
5927 c
= get_symbol_end ();
5928 symbolP
= symbol_find (reg_string
);
5929 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
5931 const expressionS
*e
= symbol_get_value_expression (symbolP
);
5933 know (e
->X_op
== O_register
);
5934 know (e
->X_add_number
>= 0
5935 && (valueT
) e
->X_add_number
< i386_regtab_size
);
5936 r
= i386_regtab
+ e
->X_add_number
;
5937 *end_op
= input_line_pointer
;
5939 *input_line_pointer
= c
;
5940 input_line_pointer
= save
;
5946 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
5949 char *end
= input_line_pointer
;
5952 r
= parse_register (name
, &input_line_pointer
);
5953 if (r
&& end
<= input_line_pointer
)
5955 *nextcharP
= *input_line_pointer
;
5956 *input_line_pointer
= 0;
5957 e
->X_op
= O_register
;
5958 e
->X_add_number
= r
- i386_regtab
;
5961 input_line_pointer
= end
;
5967 md_operand (expressionS
*e
)
5969 if (*input_line_pointer
== REGISTER_PREFIX
)
5972 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
5976 e
->X_op
= O_register
;
5977 e
->X_add_number
= r
- i386_regtab
;
5978 input_line_pointer
= end
;
5984 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5985 const char *md_shortopts
= "kVQ:sqn";
5987 const char *md_shortopts
= "qn";
5990 #define OPTION_32 (OPTION_MD_BASE + 0)
5991 #define OPTION_64 (OPTION_MD_BASE + 1)
5992 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5993 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5994 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5996 struct option md_longopts
[] =
5998 {"32", no_argument
, NULL
, OPTION_32
},
5999 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6000 {"64", no_argument
, NULL
, OPTION_64
},
6002 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
6003 {"march", required_argument
, NULL
, OPTION_MARCH
},
6004 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
6005 {NULL
, no_argument
, NULL
, 0}
6007 size_t md_longopts_size
= sizeof (md_longopts
);
6010 md_parse_option (int c
, char *arg
)
6017 optimize_align_code
= 0;
6024 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6025 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6026 should be emitted or not. FIXME: Not implemented. */
6030 /* -V: SVR4 argument to print version ID. */
6032 print_version_id ();
6035 /* -k: Ignore for FreeBSD compatibility. */
6040 /* -s: On i386 Solaris, this tells the native assembler to use
6041 .stab instead of .stab.excl. We always use .stab anyhow. */
6044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6047 const char **list
, **l
;
6049 list
= bfd_target_list ();
6050 for (l
= list
; *l
!= NULL
; l
++)
6051 if (CONST_STRNEQ (*l
, "elf64-x86-64")
6052 || strcmp (*l
, "coff-x86-64") == 0
6053 || strcmp (*l
, "pe-x86-64") == 0
6054 || strcmp (*l
, "pei-x86-64") == 0)
6056 default_arch
= "x86_64";
6060 as_fatal (_("No compiled in support for x86_64"));
6067 default_arch
= "i386";
6071 #ifdef SVR4_COMMENT_CHARS
6076 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
6078 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
6082 i386_comment_chars
= n
;
6089 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6090 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6092 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6094 cpu_arch_isa
= cpu_arch
[i
].type
;
6095 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
6096 if (!cpu_arch_tune_set
)
6098 cpu_arch_tune
= cpu_arch_isa
;
6099 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
6104 if (i
>= ARRAY_SIZE (cpu_arch
))
6105 as_fatal (_("Invalid -march= option: `%s'"), arg
);
6110 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6111 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
6113 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
6115 cpu_arch_tune_set
= 1;
6116 cpu_arch_tune
= cpu_arch
[i
].type
;
6117 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
6121 if (i
>= ARRAY_SIZE (cpu_arch
))
6122 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
6132 md_show_usage (stream
)
6135 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6136 fprintf (stream
, _("\
6138 -V print assembler version number\n\
6141 fprintf (stream
, _("\
6142 -n Do not optimize code alignment\n\
6143 -q quieten some warnings\n"));
6144 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6145 fprintf (stream
, _("\
6148 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6149 fprintf (stream
, _("\
6150 --32/--64 generate 32bit/64bit code\n"));
6152 #ifdef SVR4_COMMENT_CHARS
6153 fprintf (stream
, _("\
6154 --divide do not treat `/' as a comment character\n"));
6156 fprintf (stream
, _("\
6157 --divide ignored\n"));
6159 fprintf (stream
, _("\
6160 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6161 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
6162 core, core2, k6, athlon, k8, generic32, generic64\n"));
6166 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6167 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
6169 /* Pick the target format to use. */
6172 i386_target_format (void)
6174 if (!strcmp (default_arch
, "x86_64"))
6176 set_code_flag (CODE_64BIT
);
6177 if (cpu_arch_isa_flags
== 0)
6178 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6179 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6181 if (cpu_arch_tune_flags
== 0)
6182 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
|Cpu486
6183 |Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuMMX2
6186 else if (!strcmp (default_arch
, "i386"))
6188 set_code_flag (CODE_32BIT
);
6189 if (cpu_arch_isa_flags
== 0)
6190 cpu_arch_isa_flags
= Cpu186
|Cpu286
|Cpu386
;
6191 if (cpu_arch_tune_flags
== 0)
6192 cpu_arch_tune_flags
= Cpu186
|Cpu286
|Cpu386
;
6195 as_fatal (_("Unknown architecture"));
6196 switch (OUTPUT_FLAVOR
)
6199 case bfd_target_coff_flavour
:
6200 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "coff-i386";
6203 #ifdef OBJ_MAYBE_AOUT
6204 case bfd_target_aout_flavour
:
6205 return AOUT_TARGET_FORMAT
;
6207 #ifdef OBJ_MAYBE_COFF
6208 case bfd_target_coff_flavour
:
6211 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6212 case bfd_target_elf_flavour
:
6214 if (flag_code
== CODE_64BIT
)
6217 use_rela_relocations
= 1;
6219 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
6228 #endif /* OBJ_MAYBE_ more than one */
6230 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
6232 i386_elf_emit_arch_note (void)
6234 if (IS_ELF
&& cpu_arch_name
!= NULL
)
6237 asection
*seg
= now_seg
;
6238 subsegT subseg
= now_subseg
;
6239 Elf_Internal_Note i_note
;
6240 Elf_External_Note e_note
;
6241 asection
*note_secp
;
6244 /* Create the .note section. */
6245 note_secp
= subseg_new (".note", 0);
6246 bfd_set_section_flags (stdoutput
,
6248 SEC_HAS_CONTENTS
| SEC_READONLY
);
6250 /* Process the arch string. */
6251 len
= strlen (cpu_arch_name
);
6253 i_note
.namesz
= len
+ 1;
6255 i_note
.type
= NT_ARCH
;
6256 p
= frag_more (sizeof (e_note
.namesz
));
6257 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
6258 p
= frag_more (sizeof (e_note
.descsz
));
6259 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
6260 p
= frag_more (sizeof (e_note
.type
));
6261 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
6262 p
= frag_more (len
+ 1);
6263 strcpy (p
, cpu_arch_name
);
6265 frag_align (2, 0, 0);
6267 subseg_set (seg
, subseg
);
6273 md_undefined_symbol (name
)
6276 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
6277 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
6278 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
6279 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
6283 if (symbol_find (name
))
6284 as_bad (_("GOT already in symbol table"));
6285 GOT_symbol
= symbol_new (name
, undefined_section
,
6286 (valueT
) 0, &zero_address_frag
);
6293 /* Round up a section size to the appropriate boundary. */
6296 md_section_align (segment
, size
)
6297 segT segment ATTRIBUTE_UNUSED
;
6300 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6301 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
6303 /* For a.out, force the section size to be aligned. If we don't do
6304 this, BFD will align it for us, but it will not write out the
6305 final bytes of the section. This may be a bug in BFD, but it is
6306 easier to fix it here since that is how the other a.out targets
6310 align
= bfd_get_section_alignment (stdoutput
, segment
);
6311 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
6318 /* On the i386, PC-relative offsets are relative to the start of the
6319 next instruction. That is, the address of the offset, plus its
6320 size, since the offset is always the last part of the insn. */
6323 md_pcrel_from (fixS
*fixP
)
6325 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6331 s_bss (int ignore ATTRIBUTE_UNUSED
)
6335 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6337 obj_elf_section_change_hook ();
6339 temp
= get_absolute_expression ();
6340 subseg_set (bss_section
, (subsegT
) temp
);
6341 demand_empty_rest_of_line ();
6347 i386_validate_fix (fixS
*fixp
)
6349 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
6351 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
6355 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
6360 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
6362 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
6369 tc_gen_reloc (section
, fixp
)
6370 asection
*section ATTRIBUTE_UNUSED
;
6374 bfd_reloc_code_real_type code
;
6376 switch (fixp
->fx_r_type
)
6378 case BFD_RELOC_X86_64_PLT32
:
6379 case BFD_RELOC_X86_64_GOT32
:
6380 case BFD_RELOC_X86_64_GOTPCREL
:
6381 case BFD_RELOC_386_PLT32
:
6382 case BFD_RELOC_386_GOT32
:
6383 case BFD_RELOC_386_GOTOFF
:
6384 case BFD_RELOC_386_GOTPC
:
6385 case BFD_RELOC_386_TLS_GD
:
6386 case BFD_RELOC_386_TLS_LDM
:
6387 case BFD_RELOC_386_TLS_LDO_32
:
6388 case BFD_RELOC_386_TLS_IE_32
:
6389 case BFD_RELOC_386_TLS_IE
:
6390 case BFD_RELOC_386_TLS_GOTIE
:
6391 case BFD_RELOC_386_TLS_LE_32
:
6392 case BFD_RELOC_386_TLS_LE
:
6393 case BFD_RELOC_386_TLS_GOTDESC
:
6394 case BFD_RELOC_386_TLS_DESC_CALL
:
6395 case BFD_RELOC_X86_64_TLSGD
:
6396 case BFD_RELOC_X86_64_TLSLD
:
6397 case BFD_RELOC_X86_64_DTPOFF32
:
6398 case BFD_RELOC_X86_64_DTPOFF64
:
6399 case BFD_RELOC_X86_64_GOTTPOFF
:
6400 case BFD_RELOC_X86_64_TPOFF32
:
6401 case BFD_RELOC_X86_64_TPOFF64
:
6402 case BFD_RELOC_X86_64_GOTOFF64
:
6403 case BFD_RELOC_X86_64_GOTPC32
:
6404 case BFD_RELOC_X86_64_GOT64
:
6405 case BFD_RELOC_X86_64_GOTPCREL64
:
6406 case BFD_RELOC_X86_64_GOTPC64
:
6407 case BFD_RELOC_X86_64_GOTPLT64
:
6408 case BFD_RELOC_X86_64_PLTOFF64
:
6409 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6410 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6412 case BFD_RELOC_VTABLE_ENTRY
:
6413 case BFD_RELOC_VTABLE_INHERIT
:
6415 case BFD_RELOC_32_SECREL
:
6417 code
= fixp
->fx_r_type
;
6419 case BFD_RELOC_X86_64_32S
:
6420 if (!fixp
->fx_pcrel
)
6422 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6423 code
= fixp
->fx_r_type
;
6429 switch (fixp
->fx_size
)
6432 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6433 _("can not do %d byte pc-relative relocation"),
6435 code
= BFD_RELOC_32_PCREL
;
6437 case 1: code
= BFD_RELOC_8_PCREL
; break;
6438 case 2: code
= BFD_RELOC_16_PCREL
; break;
6439 case 4: code
= BFD_RELOC_32_PCREL
; break;
6441 case 8: code
= BFD_RELOC_64_PCREL
; break;
6447 switch (fixp
->fx_size
)
6450 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6451 _("can not do %d byte relocation"),
6453 code
= BFD_RELOC_32
;
6455 case 1: code
= BFD_RELOC_8
; break;
6456 case 2: code
= BFD_RELOC_16
; break;
6457 case 4: code
= BFD_RELOC_32
; break;
6459 case 8: code
= BFD_RELOC_64
; break;
6466 if ((code
== BFD_RELOC_32
6467 || code
== BFD_RELOC_32_PCREL
6468 || code
== BFD_RELOC_X86_64_32S
)
6470 && fixp
->fx_addsy
== GOT_symbol
)
6473 code
= BFD_RELOC_386_GOTPC
;
6475 code
= BFD_RELOC_X86_64_GOTPC32
;
6477 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
6479 && fixp
->fx_addsy
== GOT_symbol
)
6481 code
= BFD_RELOC_X86_64_GOTPC64
;
6484 rel
= (arelent
*) xmalloc (sizeof (arelent
));
6485 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6486 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6488 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6490 if (!use_rela_relocations
)
6492 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6493 vtable entry to be used in the relocation's section offset. */
6494 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6495 rel
->address
= fixp
->fx_offset
;
6499 /* Use the rela in 64bit mode. */
6502 if (!fixp
->fx_pcrel
)
6503 rel
->addend
= fixp
->fx_offset
;
6507 case BFD_RELOC_X86_64_PLT32
:
6508 case BFD_RELOC_X86_64_GOT32
:
6509 case BFD_RELOC_X86_64_GOTPCREL
:
6510 case BFD_RELOC_X86_64_TLSGD
:
6511 case BFD_RELOC_X86_64_TLSLD
:
6512 case BFD_RELOC_X86_64_GOTTPOFF
:
6513 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
6514 case BFD_RELOC_X86_64_TLSDESC_CALL
:
6515 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
6518 rel
->addend
= (section
->vma
6520 + fixp
->fx_addnumber
6521 + md_pcrel_from (fixp
));
6526 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6527 if (rel
->howto
== NULL
)
6529 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6530 _("cannot represent relocation type %s"),
6531 bfd_get_reloc_code_name (code
));
6532 /* Set howto to a garbage value so that we can keep going. */
6533 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
6534 assert (rel
->howto
!= NULL
);
6541 /* Parse operands using Intel syntax. This implements a recursive descent
6542 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6545 FIXME: We do not recognize the full operand grammar defined in the MASM
6546 documentation. In particular, all the structure/union and
6547 high-level macro operands are missing.
6549 Uppercase words are terminals, lower case words are non-terminals.
6550 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6551 bars '|' denote choices. Most grammar productions are implemented in
6552 functions called 'intel_<production>'.
6554 Initial production is 'expr'.
6560 binOp & | AND | \| | OR | ^ | XOR
6562 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6564 constant digits [[ radixOverride ]]
6566 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6604 => expr expr cmpOp e04
6607 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6608 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6610 hexdigit a | b | c | d | e | f
6611 | A | B | C | D | E | F
6617 mulOp * | / | % | MOD | << | SHL | >> | SHR
6621 register specialRegister
6625 segmentRegister CS | DS | ES | FS | GS | SS
6627 specialRegister CR0 | CR2 | CR3 | CR4
6628 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6629 | TR3 | TR4 | TR5 | TR6 | TR7
6631 We simplify the grammar in obvious places (e.g., register parsing is
6632 done by calling parse_register) and eliminate immediate left recursion
6633 to implement a recursive-descent parser.
6637 expr' cmpOp e04 expr'
6688 /* Parsing structure for the intel syntax parser. Used to implement the
6689 semantic actions for the operand grammar. */
6690 struct intel_parser_s
6692 char *op_string
; /* The string being parsed. */
6693 int got_a_float
; /* Whether the operand is a float. */
6694 int op_modifier
; /* Operand modifier. */
6695 int is_mem
; /* 1 if operand is memory reference. */
6696 int in_offset
; /* >=1 if parsing operand of offset. */
6697 int in_bracket
; /* >=1 if parsing operand in brackets. */
6698 const reg_entry
*reg
; /* Last register reference found. */
6699 char *disp
; /* Displacement string being built. */
6700 char *next_operand
; /* Resume point when splitting operands. */
6703 static struct intel_parser_s intel_parser
;
6705 /* Token structure for parsing intel syntax. */
6708 int code
; /* Token code. */
6709 const reg_entry
*reg
; /* Register entry for register tokens. */
6710 char *str
; /* String representation. */
6713 static struct intel_token cur_token
, prev_token
;
6715 /* Token codes for the intel parser. Since T_SHORT is already used
6716 by COFF, undefine it first to prevent a warning. */
6735 /* Prototypes for intel parser functions. */
6736 static int intel_match_token (int);
6737 static void intel_putback_token (void);
6738 static void intel_get_token (void);
6739 static int intel_expr (void);
6740 static int intel_e04 (void);
6741 static int intel_e05 (void);
6742 static int intel_e06 (void);
6743 static int intel_e09 (void);
6744 static int intel_e10 (void);
6745 static int intel_e11 (void);
6748 i386_intel_operand (char *operand_string
, int got_a_float
)
6753 p
= intel_parser
.op_string
= xstrdup (operand_string
);
6754 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
6758 /* Initialize token holders. */
6759 cur_token
.code
= prev_token
.code
= T_NIL
;
6760 cur_token
.reg
= prev_token
.reg
= NULL
;
6761 cur_token
.str
= prev_token
.str
= NULL
;
6763 /* Initialize parser structure. */
6764 intel_parser
.got_a_float
= got_a_float
;
6765 intel_parser
.op_modifier
= 0;
6766 intel_parser
.is_mem
= 0;
6767 intel_parser
.in_offset
= 0;
6768 intel_parser
.in_bracket
= 0;
6769 intel_parser
.reg
= NULL
;
6770 intel_parser
.disp
[0] = '\0';
6771 intel_parser
.next_operand
= NULL
;
6773 /* Read the first token and start the parser. */
6775 ret
= intel_expr ();
6780 if (cur_token
.code
!= T_NIL
)
6782 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6783 current_templates
->start
->name
, cur_token
.str
);
6786 /* If we found a memory reference, hand it over to i386_displacement
6787 to fill in the rest of the operand fields. */
6788 else if (intel_parser
.is_mem
)
6790 if ((i
.mem_operands
== 1
6791 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
6792 || i
.mem_operands
== 2)
6794 as_bad (_("too many memory references for '%s'"),
6795 current_templates
->start
->name
);
6800 char *s
= intel_parser
.disp
;
6803 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
6804 /* See the comments in intel_bracket_expr. */
6805 as_warn (_("Treating `%s' as memory reference"), operand_string
);
6807 /* Add the displacement expression. */
6809 ret
= i386_displacement (s
, s
+ strlen (s
));
6812 /* Swap base and index in 16-bit memory operands like
6813 [si+bx]. Since i386_index_check is also used in AT&T
6814 mode we have to do that here. */
6817 && (i
.base_reg
->reg_type
& Reg16
)
6818 && (i
.index_reg
->reg_type
& Reg16
)
6819 && i
.base_reg
->reg_num
>= 6
6820 && i
.index_reg
->reg_num
< 6)
6822 const reg_entry
*base
= i
.index_reg
;
6824 i
.index_reg
= i
.base_reg
;
6827 ret
= i386_index_check (operand_string
);
6832 /* Constant and OFFSET expressions are handled by i386_immediate. */
6833 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
6834 || intel_parser
.reg
== NULL
)
6835 ret
= i386_immediate (intel_parser
.disp
);
6837 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
6839 if (!ret
|| !intel_parser
.next_operand
)
6841 intel_parser
.op_string
= intel_parser
.next_operand
;
6842 this_operand
= i
.operands
++;
6846 free (intel_parser
.disp
);
6851 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6855 expr' cmpOp e04 expr'
6860 /* XXX Implement the comparison operators. */
6861 return intel_e04 ();
6878 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6879 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
6881 if (cur_token
.code
== '+')
6883 else if (cur_token
.code
== '-')
6884 nregs
= NUM_ADDRESS_REGS
;
6888 strcat (intel_parser
.disp
, cur_token
.str
);
6889 intel_match_token (cur_token
.code
);
6900 int nregs
= ~NUM_ADDRESS_REGS
;
6907 if (cur_token
.code
== '&'
6908 || cur_token
.code
== '|'
6909 || cur_token
.code
== '^')
6913 str
[0] = cur_token
.code
;
6915 strcat (intel_parser
.disp
, str
);
6920 intel_match_token (cur_token
.code
);
6925 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6926 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
6937 int nregs
= ~NUM_ADDRESS_REGS
;
6944 if (cur_token
.code
== '*'
6945 || cur_token
.code
== '/'
6946 || cur_token
.code
== '%')
6950 str
[0] = cur_token
.code
;
6952 strcat (intel_parser
.disp
, str
);
6954 else if (cur_token
.code
== T_SHL
)
6955 strcat (intel_parser
.disp
, "<<");
6956 else if (cur_token
.code
== T_SHR
)
6957 strcat (intel_parser
.disp
, ">>");
6961 intel_match_token (cur_token
.code
);
6966 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
6967 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
6985 int nregs
= ~NUM_ADDRESS_REGS
;
6990 /* Don't consume constants here. */
6991 if (cur_token
.code
== '+' || cur_token
.code
== '-')
6993 /* Need to look one token ahead - if the next token
6994 is a constant, the current token is its sign. */
6997 intel_match_token (cur_token
.code
);
6998 next_code
= cur_token
.code
;
6999 intel_putback_token ();
7000 if (next_code
== T_CONST
)
7004 /* e09 OFFSET e09 */
7005 if (cur_token
.code
== T_OFFSET
)
7008 ++intel_parser
.in_offset
;
7012 else if (cur_token
.code
== T_SHORT
)
7013 intel_parser
.op_modifier
|= 1 << T_SHORT
;
7016 else if (cur_token
.code
== '+')
7017 strcat (intel_parser
.disp
, "+");
7022 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
7028 str
[0] = cur_token
.code
;
7030 strcat (intel_parser
.disp
, str
);
7037 intel_match_token (cur_token
.code
);
7045 /* e09' PTR e10 e09' */
7046 if (cur_token
.code
== T_PTR
)
7050 if (prev_token
.code
== T_BYTE
)
7051 suffix
= BYTE_MNEM_SUFFIX
;
7053 else if (prev_token
.code
== T_WORD
)
7055 if (current_templates
->start
->name
[0] == 'l'
7056 && current_templates
->start
->name
[2] == 's'
7057 && current_templates
->start
->name
[3] == 0)
7058 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7059 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
7060 suffix
= SHORT_MNEM_SUFFIX
;
7062 suffix
= WORD_MNEM_SUFFIX
;
7065 else if (prev_token
.code
== T_DWORD
)
7067 if (current_templates
->start
->name
[0] == 'l'
7068 && current_templates
->start
->name
[2] == 's'
7069 && current_templates
->start
->name
[3] == 0)
7070 suffix
= WORD_MNEM_SUFFIX
;
7071 else if (flag_code
== CODE_16BIT
7072 && (current_templates
->start
->opcode_modifier
7073 & (Jump
| JumpDword
)))
7074 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7075 else if (intel_parser
.got_a_float
== 1) /* "f..." */
7076 suffix
= SHORT_MNEM_SUFFIX
;
7078 suffix
= LONG_MNEM_SUFFIX
;
7081 else if (prev_token
.code
== T_FWORD
)
7083 if (current_templates
->start
->name
[0] == 'l'
7084 && current_templates
->start
->name
[2] == 's'
7085 && current_templates
->start
->name
[3] == 0)
7086 suffix
= LONG_MNEM_SUFFIX
;
7087 else if (!intel_parser
.got_a_float
)
7089 if (flag_code
== CODE_16BIT
)
7090 add_prefix (DATA_PREFIX_OPCODE
);
7091 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7094 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7097 else if (prev_token
.code
== T_QWORD
)
7099 if (intel_parser
.got_a_float
== 1) /* "f..." */
7100 suffix
= LONG_MNEM_SUFFIX
;
7102 suffix
= QWORD_MNEM_SUFFIX
;
7105 else if (prev_token
.code
== T_TBYTE
)
7107 if (intel_parser
.got_a_float
== 1)
7108 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
7110 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
7113 else if (prev_token
.code
== T_XMMWORD
)
7115 /* XXX ignored for now, but accepted since gcc uses it */
7121 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
7125 /* Operands for jump/call using 'ptr' notation denote absolute
7127 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7128 i
.types
[this_operand
] |= JumpAbsolute
;
7130 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
7134 else if (i
.suffix
!= suffix
)
7136 as_bad (_("Conflicting operand modifiers"));
7142 /* e09' : e10 e09' */
7143 else if (cur_token
.code
== ':')
7145 if (prev_token
.code
!= T_REG
)
7147 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7148 segment/group identifier (which we don't have), using comma
7149 as the operand separator there is even less consistent, since
7150 there all branches only have a single operand. */
7151 if (this_operand
!= 0
7152 || intel_parser
.in_offset
7153 || intel_parser
.in_bracket
7154 || (!(current_templates
->start
->opcode_modifier
7155 & (Jump
|JumpDword
|JumpInterSegment
))
7156 && !(current_templates
->start
->operand_types
[0]
7158 return intel_match_token (T_NIL
);
7159 /* Remember the start of the 2nd operand and terminate 1st
7161 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7162 another expression), but it gets at least the simplest case
7163 (a plain number or symbol on the left side) right. */
7164 intel_parser
.next_operand
= intel_parser
.op_string
;
7165 *--intel_parser
.op_string
= '\0';
7166 return intel_match_token (':');
7174 intel_match_token (cur_token
.code
);
7180 --intel_parser
.in_offset
;
7183 if (NUM_ADDRESS_REGS
> nregs
)
7185 as_bad (_("Invalid operand to `OFFSET'"));
7188 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
7191 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
7192 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
7197 intel_bracket_expr (void)
7199 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
7200 const char *start
= intel_parser
.op_string
;
7203 if (i
.op
[this_operand
].regs
)
7204 return intel_match_token (T_NIL
);
7206 intel_match_token ('[');
7208 /* Mark as a memory operand only if it's not already known to be an
7209 offset expression. If it's an offset expression, we need to keep
7211 if (!intel_parser
.in_offset
)
7213 ++intel_parser
.in_bracket
;
7215 /* Operands for jump/call inside brackets denote absolute addresses. */
7216 if (current_templates
->start
->opcode_modifier
& (Jump
| JumpDword
))
7217 i
.types
[this_operand
] |= JumpAbsolute
;
7219 /* Unfortunately gas always diverged from MASM in a respect that can't
7220 be easily fixed without risking to break code sequences likely to be
7221 encountered (the testsuite even check for this): MASM doesn't consider
7222 an expression inside brackets unconditionally as a memory reference.
7223 When that is e.g. a constant, an offset expression, or the sum of the
7224 two, this is still taken as a constant load. gas, however, always
7225 treated these as memory references. As a compromise, we'll try to make
7226 offset expressions inside brackets work the MASM way (since that's
7227 less likely to be found in real world code), but make constants alone
7228 continue to work the traditional gas way. In either case, issue a
7230 intel_parser
.op_modifier
&= ~was_offset
;
7233 strcat (intel_parser
.disp
, "[");
7235 /* Add a '+' to the displacement string if necessary. */
7236 if (*intel_parser
.disp
!= '\0'
7237 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
7238 strcat (intel_parser
.disp
, "+");
7241 && (len
= intel_parser
.op_string
- start
- 1,
7242 intel_match_token (']')))
7244 /* Preserve brackets when the operand is an offset expression. */
7245 if (intel_parser
.in_offset
)
7246 strcat (intel_parser
.disp
, "]");
7249 --intel_parser
.in_bracket
;
7250 if (i
.base_reg
|| i
.index_reg
)
7251 intel_parser
.is_mem
= 1;
7252 if (!intel_parser
.is_mem
)
7254 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
7255 /* Defer the warning until all of the operand was parsed. */
7256 intel_parser
.is_mem
= -1;
7257 else if (!quiet_warnings
)
7258 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7259 len
, start
, len
, start
);
7262 intel_parser
.op_modifier
|= was_offset
;
7279 while (cur_token
.code
== '[')
7281 if (!intel_bracket_expr ())
7306 switch (cur_token
.code
)
7310 intel_match_token ('(');
7311 strcat (intel_parser
.disp
, "(");
7313 if (intel_expr () && intel_match_token (')'))
7315 strcat (intel_parser
.disp
, ")");
7322 return intel_bracket_expr ();
7327 strcat (intel_parser
.disp
, cur_token
.str
);
7328 intel_match_token (cur_token
.code
);
7330 /* Mark as a memory operand only if it's not already known to be an
7331 offset expression. */
7332 if (!intel_parser
.in_offset
)
7333 intel_parser
.is_mem
= 1;
7340 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
7342 intel_match_token (T_REG
);
7344 /* Check for segment change. */
7345 if (cur_token
.code
== ':')
7347 if (!(reg
->reg_type
& (SReg2
| SReg3
)))
7349 as_bad (_("`%s' is not a valid segment register"),
7353 else if (i
.seg
[i
.mem_operands
])
7354 as_warn (_("Extra segment override ignored"));
7357 if (!intel_parser
.in_offset
)
7358 intel_parser
.is_mem
= 1;
7359 switch (reg
->reg_num
)
7362 i
.seg
[i
.mem_operands
] = &es
;
7365 i
.seg
[i
.mem_operands
] = &cs
;
7368 i
.seg
[i
.mem_operands
] = &ss
;
7371 i
.seg
[i
.mem_operands
] = &ds
;
7374 i
.seg
[i
.mem_operands
] = &fs
;
7377 i
.seg
[i
.mem_operands
] = &gs
;
7383 /* Not a segment register. Check for register scaling. */
7384 else if (cur_token
.code
== '*')
7386 if (!intel_parser
.in_bracket
)
7388 as_bad (_("Register scaling only allowed in memory operands"));
7392 if (reg
->reg_type
& Reg16
) /* Disallow things like [si*1]. */
7393 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
7394 else if (i
.index_reg
)
7395 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
7397 /* What follows must be a valid scale. */
7398 intel_match_token ('*');
7400 i
.types
[this_operand
] |= BaseIndex
;
7402 /* Set the scale after setting the register (otherwise,
7403 i386_scale will complain) */
7404 if (cur_token
.code
== '+' || cur_token
.code
== '-')
7406 char *str
, sign
= cur_token
.code
;
7407 intel_match_token (cur_token
.code
);
7408 if (cur_token
.code
!= T_CONST
)
7410 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7414 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7415 strcpy (str
+ 1, cur_token
.str
);
7417 if (!i386_scale (str
))
7421 else if (!i386_scale (cur_token
.str
))
7423 intel_match_token (cur_token
.code
);
7426 /* No scaling. If this is a memory operand, the register is either a
7427 base register (first occurrence) or an index register (second
7429 else if (intel_parser
.in_bracket
)
7434 else if (!i
.index_reg
)
7438 as_bad (_("Too many register references in memory operand"));
7442 i
.types
[this_operand
] |= BaseIndex
;
7445 /* It's neither base nor index. */
7446 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
7448 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
7449 i
.op
[this_operand
].regs
= reg
;
7454 as_bad (_("Invalid use of register"));
7458 /* Since registers are not part of the displacement string (except
7459 when we're parsing offset operands), we may need to remove any
7460 preceding '+' from the displacement string. */
7461 if (*intel_parser
.disp
!= '\0'
7462 && !intel_parser
.in_offset
)
7464 char *s
= intel_parser
.disp
;
7465 s
+= strlen (s
) - 1;
7488 intel_match_token (cur_token
.code
);
7490 if (cur_token
.code
== T_PTR
)
7493 /* It must have been an identifier. */
7494 intel_putback_token ();
7495 cur_token
.code
= T_ID
;
7501 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
7505 /* The identifier represents a memory reference only if it's not
7506 preceded by an offset modifier and if it's not an equate. */
7507 symbolP
= symbol_find(cur_token
.str
);
7508 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
7509 intel_parser
.is_mem
= 1;
7517 char *save_str
, sign
= 0;
7519 /* Allow constants that start with `+' or `-'. */
7520 if (cur_token
.code
== '-' || cur_token
.code
== '+')
7522 sign
= cur_token
.code
;
7523 intel_match_token (cur_token
.code
);
7524 if (cur_token
.code
!= T_CONST
)
7526 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7532 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
7533 strcpy (save_str
+ !!sign
, cur_token
.str
);
7537 /* Get the next token to check for register scaling. */
7538 intel_match_token (cur_token
.code
);
7540 /* Check if this constant is a scaling factor for an
7542 if (cur_token
.code
== '*')
7544 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
7546 const reg_entry
*reg
= cur_token
.reg
;
7548 if (!intel_parser
.in_bracket
)
7550 as_bad (_("Register scaling only allowed "
7551 "in memory operands"));
7555 /* Disallow things like [1*si].
7556 sp and esp are invalid as index. */
7557 if (reg
->reg_type
& Reg16
)
7558 reg
= i386_regtab
+ REGNAM_AX
+ 4;
7559 else if (i
.index_reg
)
7560 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
7562 /* The constant is followed by `* reg', so it must be
7565 i
.types
[this_operand
] |= BaseIndex
;
7567 /* Set the scale after setting the register (otherwise,
7568 i386_scale will complain) */
7569 if (!i386_scale (save_str
))
7571 intel_match_token (T_REG
);
7573 /* Since registers are not part of the displacement
7574 string, we may need to remove any preceding '+' from
7575 the displacement string. */
7576 if (*intel_parser
.disp
!= '\0')
7578 char *s
= intel_parser
.disp
;
7579 s
+= strlen (s
) - 1;
7589 /* The constant was not used for register scaling. Since we have
7590 already consumed the token following `*' we now need to put it
7591 back in the stream. */
7592 intel_putback_token ();
7595 /* Add the constant to the displacement string. */
7596 strcat (intel_parser
.disp
, save_str
);
7603 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
7607 /* Match the given token against cur_token. If they match, read the next
7608 token from the operand string. */
7610 intel_match_token (int code
)
7612 if (cur_token
.code
== code
)
7619 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
7624 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7626 intel_get_token (void)
7629 const reg_entry
*reg
;
7630 struct intel_token new_token
;
7632 new_token
.code
= T_NIL
;
7633 new_token
.reg
= NULL
;
7634 new_token
.str
= NULL
;
7636 /* Free the memory allocated to the previous token and move
7637 cur_token to prev_token. */
7639 free (prev_token
.str
);
7641 prev_token
= cur_token
;
7643 /* Skip whitespace. */
7644 while (is_space_char (*intel_parser
.op_string
))
7645 intel_parser
.op_string
++;
7647 /* Return an empty token if we find nothing else on the line. */
7648 if (*intel_parser
.op_string
== '\0')
7650 cur_token
= new_token
;
7654 /* The new token cannot be larger than the remainder of the operand
7656 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
7657 new_token
.str
[0] = '\0';
7659 if (strchr ("0123456789", *intel_parser
.op_string
))
7661 char *p
= new_token
.str
;
7662 char *q
= intel_parser
.op_string
;
7663 new_token
.code
= T_CONST
;
7665 /* Allow any kind of identifier char to encompass floating point and
7666 hexadecimal numbers. */
7667 while (is_identifier_char (*q
))
7671 /* Recognize special symbol names [0-9][bf]. */
7672 if (strlen (intel_parser
.op_string
) == 2
7673 && (intel_parser
.op_string
[1] == 'b'
7674 || intel_parser
.op_string
[1] == 'f'))
7675 new_token
.code
= T_ID
;
7678 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
7680 size_t len
= end_op
- intel_parser
.op_string
;
7682 new_token
.code
= T_REG
;
7683 new_token
.reg
= reg
;
7685 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
7686 new_token
.str
[len
] = '\0';
7689 else if (is_identifier_char (*intel_parser
.op_string
))
7691 char *p
= new_token
.str
;
7692 char *q
= intel_parser
.op_string
;
7694 /* A '.' or '$' followed by an identifier char is an identifier.
7695 Otherwise, it's operator '.' followed by an expression. */
7696 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
7698 new_token
.code
= '.';
7699 new_token
.str
[0] = '.';
7700 new_token
.str
[1] = '\0';
7704 while (is_identifier_char (*q
) || *q
== '@')
7708 if (strcasecmp (new_token
.str
, "NOT") == 0)
7709 new_token
.code
= '~';
7711 else if (strcasecmp (new_token
.str
, "MOD") == 0)
7712 new_token
.code
= '%';
7714 else if (strcasecmp (new_token
.str
, "AND") == 0)
7715 new_token
.code
= '&';
7717 else if (strcasecmp (new_token
.str
, "OR") == 0)
7718 new_token
.code
= '|';
7720 else if (strcasecmp (new_token
.str
, "XOR") == 0)
7721 new_token
.code
= '^';
7723 else if (strcasecmp (new_token
.str
, "SHL") == 0)
7724 new_token
.code
= T_SHL
;
7726 else if (strcasecmp (new_token
.str
, "SHR") == 0)
7727 new_token
.code
= T_SHR
;
7729 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
7730 new_token
.code
= T_BYTE
;
7732 else if (strcasecmp (new_token
.str
, "WORD") == 0)
7733 new_token
.code
= T_WORD
;
7735 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
7736 new_token
.code
= T_DWORD
;
7738 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
7739 new_token
.code
= T_FWORD
;
7741 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
7742 new_token
.code
= T_QWORD
;
7744 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
7745 /* XXX remove (gcc still uses it) */
7746 || strcasecmp (new_token
.str
, "XWORD") == 0)
7747 new_token
.code
= T_TBYTE
;
7749 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
7750 || strcasecmp (new_token
.str
, "OWORD") == 0)
7751 new_token
.code
= T_XMMWORD
;
7753 else if (strcasecmp (new_token
.str
, "PTR") == 0)
7754 new_token
.code
= T_PTR
;
7756 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
7757 new_token
.code
= T_SHORT
;
7759 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
7761 new_token
.code
= T_OFFSET
;
7763 /* ??? This is not mentioned in the MASM grammar but gcc
7764 makes use of it with -mintel-syntax. OFFSET may be
7765 followed by FLAT: */
7766 if (strncasecmp (q
, " FLAT:", 6) == 0)
7767 strcat (new_token
.str
, " FLAT:");
7770 /* ??? This is not mentioned in the MASM grammar. */
7771 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
7773 new_token
.code
= T_OFFSET
;
7775 strcat (new_token
.str
, ":");
7777 as_bad (_("`:' expected"));
7781 new_token
.code
= T_ID
;
7785 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
7787 new_token
.code
= *intel_parser
.op_string
;
7788 new_token
.str
[0] = *intel_parser
.op_string
;
7789 new_token
.str
[1] = '\0';
7792 else if (strchr ("<>", *intel_parser
.op_string
)
7793 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
7795 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
7796 new_token
.str
[0] = *intel_parser
.op_string
;
7797 new_token
.str
[1] = *intel_parser
.op_string
;
7798 new_token
.str
[2] = '\0';
7802 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
7804 intel_parser
.op_string
+= strlen (new_token
.str
);
7805 cur_token
= new_token
;
7808 /* Put cur_token back into the token stream and make cur_token point to
7811 intel_putback_token (void)
7813 if (cur_token
.code
!= T_NIL
)
7815 intel_parser
.op_string
-= strlen (cur_token
.str
);
7816 free (cur_token
.str
);
7818 cur_token
= prev_token
;
7820 /* Forget prev_token. */
7821 prev_token
.code
= T_NIL
;
7822 prev_token
.reg
= NULL
;
7823 prev_token
.str
= NULL
;
7827 tc_x86_regname_to_dw2regnum (char *regname
)
7829 unsigned int regnum
;
7830 unsigned int regnames_count
;
7831 static const char *const regnames_32
[] =
7833 "eax", "ecx", "edx", "ebx",
7834 "esp", "ebp", "esi", "edi",
7835 "eip", "eflags", NULL
,
7836 "st0", "st1", "st2", "st3",
7837 "st4", "st5", "st6", "st7",
7839 "xmm0", "xmm1", "xmm2", "xmm3",
7840 "xmm4", "xmm5", "xmm6", "xmm7",
7841 "mm0", "mm1", "mm2", "mm3",
7842 "mm4", "mm5", "mm6", "mm7",
7843 "fcw", "fsw", "mxcsr",
7844 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7847 static const char *const regnames_64
[] =
7849 "rax", "rdx", "rcx", "rbx",
7850 "rsi", "rdi", "rbp", "rsp",
7851 "r8", "r9", "r10", "r11",
7852 "r12", "r13", "r14", "r15",
7854 "xmm0", "xmm1", "xmm2", "xmm3",
7855 "xmm4", "xmm5", "xmm6", "xmm7",
7856 "xmm8", "xmm9", "xmm10", "xmm11",
7857 "xmm12", "xmm13", "xmm14", "xmm15",
7858 "st0", "st1", "st2", "st3",
7859 "st4", "st5", "st6", "st7",
7860 "mm0", "mm1", "mm2", "mm3",
7861 "mm4", "mm5", "mm6", "mm7",
7863 "es", "cs", "ss", "ds", "fs", "gs", NULL
, NULL
,
7864 "fs.base", "gs.base", NULL
, NULL
,
7866 "mxcsr", "fcw", "fsw"
7868 const char *const *regnames
;
7870 if (flag_code
== CODE_64BIT
)
7872 regnames
= regnames_64
;
7873 regnames_count
= ARRAY_SIZE (regnames_64
);
7877 regnames
= regnames_32
;
7878 regnames_count
= ARRAY_SIZE (regnames_32
);
7881 for (regnum
= 0; regnum
< regnames_count
; regnum
++)
7882 if (regnames
[regnum
] != NULL
7883 && strcmp (regname
, regnames
[regnum
]) == 0)
7890 tc_x86_frame_initial_instructions (void)
7892 static unsigned int sp_regno
;
7895 sp_regno
= tc_x86_regname_to_dw2regnum (flag_code
== CODE_64BIT
7898 cfi_add_CFA_def_cfa (sp_regno
, -x86_cie_data_alignment
);
7899 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
7903 i386_elf_section_type (const char *str
, size_t len
)
7905 if (flag_code
== CODE_64BIT
7906 && len
== sizeof ("unwind") - 1
7907 && strncmp (str
, "unwind", 6) == 0)
7908 return SHT_X86_64_UNWIND
;
7915 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
7919 expr
.X_op
= O_secrel
;
7920 expr
.X_add_symbol
= symbol
;
7921 expr
.X_add_number
= 0;
7922 emit_expr (&expr
, size
);
7926 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7927 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7930 x86_64_section_letter (int letter
, char **ptr_msg
)
7932 if (flag_code
== CODE_64BIT
)
7935 return SHF_X86_64_LARGE
;
7937 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7940 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
7945 x86_64_section_word (char *str
, size_t len
)
7947 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
7948 return SHF_X86_64_LARGE
;
7954 handle_large_common (int small ATTRIBUTE_UNUSED
)
7956 if (flag_code
!= CODE_64BIT
)
7958 s_comm_internal (0, elf_common_parse
);
7959 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7963 static segT lbss_section
;
7964 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
7965 asection
*saved_bss_section
= bss_section
;
7967 if (lbss_section
== NULL
)
7969 flagword applicable
;
7971 subsegT subseg
= now_subseg
;
7973 /* The .lbss section is for local .largecomm symbols. */
7974 lbss_section
= subseg_new (".lbss", 0);
7975 applicable
= bfd_applicable_section_flags (stdoutput
);
7976 bfd_set_section_flags (stdoutput
, lbss_section
,
7977 applicable
& SEC_ALLOC
);
7978 seg_info (lbss_section
)->bss
= 1;
7980 subseg_set (seg
, subseg
);
7983 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
7984 bss_section
= lbss_section
;
7986 s_comm_internal (0, elf_common_parse
);
7988 elf_com_section_ptr
= saved_com_section_ptr
;
7989 bss_section
= saved_bss_section
;
7992 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */