1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better.
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int smallest_imm_type
PARAMS ((offsetT
));
60 static offsetT offset_in_range
PARAMS ((offsetT
, int));
61 static int add_prefix
PARAMS ((unsigned int));
62 static void set_16bit_code_flag
PARAMS ((int));
63 static void set_16bit_gcc_code_flag
PARAMS((int));
64 static void set_intel_syntax
PARAMS ((int));
67 static bfd_reloc_code_real_type reloc
68 PARAMS ((int, int, bfd_reloc_code_real_type
));
71 /* 'md_assemble ()' gathers together information and puts it into a
78 const reg_entry
*regs
;
83 /* TM holds the template for the insn were currently assembling. */
86 /* SUFFIX holds the instruction mnemonic suffix if given.
87 (e.g. 'l' for 'movl') */
90 /* OPERANDS gives the number of given operands. */
91 unsigned int operands
;
93 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
94 of given register, displacement, memory operands and immediate
96 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
98 /* TYPES [i] is the type (see above #defines) which tells us how to
99 use OP[i] for the corresponding operand. */
100 unsigned int types
[MAX_OPERANDS
];
102 /* Displacement expression, immediate expression, or register for each
104 union i386_op op
[MAX_OPERANDS
];
106 /* Relocation type for operand */
108 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
110 int disp_reloc
[MAX_OPERANDS
];
113 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
114 the base index byte below. */
115 const reg_entry
*base_reg
;
116 const reg_entry
*index_reg
;
117 unsigned int log2_scale_factor
;
119 /* SEG gives the seg_entries of this insn. They are zero unless
120 explicit segment overrides are given. */
121 const seg_entry
*seg
[2]; /* segments for memory operands (if given) */
123 /* PREFIX holds all the given prefix opcodes (usually null).
124 PREFIXES is the number of prefix opcodes. */
125 unsigned int prefixes
;
126 unsigned char prefix
[MAX_PREFIXES
];
128 /* RM and SIB are the modrm byte and the sib byte where the
129 addressing modes of this insn are encoded. */
135 typedef struct _i386_insn i386_insn
;
137 /* List of chars besides those in app.c:symbol_chars that can start an
138 operand. Used to prevent the scrubber eating vital white-space. */
140 const char extra_symbol_chars
[] = "*%-(@";
142 const char extra_symbol_chars
[] = "*%-(";
145 /* This array holds the chars that always start a comment. If the
146 pre-processor is disabled, these aren't very useful */
147 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX))
148 /* Putting '/' here makes it impossible to use the divide operator.
149 However, we need it for compatibility with SVR4 systems. */
150 const char comment_chars
[] = "#/";
151 #define PREFIX_SEPARATOR '\\'
153 const char comment_chars
[] = "#";
154 #define PREFIX_SEPARATOR '/'
157 /* This array holds the chars that only start a comment at the beginning of
158 a line. If the line seems to have the form '# 123 filename'
159 .line and .file directives will appear in the pre-processed output */
160 /* Note that input_file.c hand checks for '#' at the beginning of the
161 first line of the input file. This is because the compiler outputs
162 #NO_APP at the beginning of its output. */
163 /* Also note that comments started like this one will always work if
164 '/' isn't otherwise defined. */
165 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX))
166 const char line_comment_chars
[] = "";
168 const char line_comment_chars
[] = "/";
171 const char line_separator_chars
[] = "";
173 /* Chars that can be used to separate mant from exp in floating point nums */
174 const char EXP_CHARS
[] = "eE";
176 /* Chars that mean this number is a floating point constant */
179 const char FLT_CHARS
[] = "fFdDxX";
181 /* tables for lexical analysis */
182 static char mnemonic_chars
[256];
183 static char register_chars
[256];
184 static char operand_chars
[256];
185 static char identifier_chars
[256];
186 static char digit_chars
[256];
189 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
190 #define is_operand_char(x) (operand_chars[(unsigned char) x])
191 #define is_register_char(x) (register_chars[(unsigned char) x])
192 #define is_space_char(x) ((x) == ' ')
193 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
194 #define is_digit_char(x) (digit_chars[(unsigned char) x])
196 /* put here all non-digit non-letter charcters that may occur in an operand */
197 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
199 /* md_assemble() always leaves the strings it's passed unaltered. To
200 effect this we maintain a stack of saved characters that we've smashed
201 with '\0's (indicating end of strings for various sub-fields of the
202 assembler instruction). */
203 static char save_stack
[32];
204 static char *save_stack_p
; /* stack pointer */
205 #define END_STRING_AND_SAVE(s) \
206 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
207 #define RESTORE_END_STRING(s) \
208 do { *(s) = *--save_stack_p; } while (0)
210 /* The instruction we're assembling. */
213 /* Possible templates for current insn. */
214 static const templates
*current_templates
;
216 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
217 static expressionS disp_expressions
[2], im_expressions
[2];
219 static int this_operand
; /* current operand we are working on */
221 static int flag_do_long_jump
; /* FIXME what does this do? */
223 static int flag_16bit_code
; /* 1 if we're writing 16-bit code, 0 if 32-bit */
225 static int intel_syntax
= 0; /* 1 for intel syntax, 0 if att syntax */
227 static int allow_naked_reg
= 0; /* 1 if register prefix % not required */
229 static char stackop_size
= '\0'; /* Used in 16 bit gcc mode to add an l
230 suffix to call, ret, enter, leave, push,
231 and pop instructions so that gcc has the
232 same stack frame as in 32 bit mode. */
234 /* Interface to relax_segment.
235 There are 2 relax states for 386 jump insns: one for conditional &
236 one for unconditional jumps. This is because these two types of
237 jumps add different sizes to frags when we're figuring out what
238 sort of jump to choose to reach a given label. */
241 #define COND_JUMP 1 /* conditional jump */
242 #define UNCOND_JUMP 2 /* unconditional jump */
246 #define SMALL16 (SMALL|CODE16)
248 #define BIG16 (BIG|CODE16)
252 #define INLINE __inline__
258 #define ENCODE_RELAX_STATE(type,size) \
259 ((relax_substateT)((type<<2) | (size)))
260 #define SIZE_FROM_RELAX_STATE(s) \
261 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
263 /* This table is used by relax_frag to promote short jumps to long
264 ones where necessary. SMALL (short) jumps may be promoted to BIG
265 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
266 don't allow a short jump in a 32 bit code segment to be promoted to
267 a 16 bit offset jump because it's slower (requires data size
268 prefix), and doesn't work, unless the destination is in the bottom
269 64k of the code segment (The top 16 bits of eip are zeroed). */
271 const relax_typeS md_relax_table
[] =
274 1) most positive reach of this state,
275 2) most negative reach of this state,
276 3) how many bytes this mode will add to the size of the current frag
277 4) which index into the table to try if we can't fit into this one.
284 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
285 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
286 /* dword conditionals adds 4 bytes to frag:
287 1 extra opcode byte, 3 extra displacement bytes. */
289 /* word conditionals add 2 bytes to frag:
290 1 extra opcode byte, 1 extra displacement byte. */
293 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
294 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
295 /* dword jmp adds 3 bytes to frag:
296 0 extra opcode bytes, 3 extra displacement bytes. */
298 /* word jmp adds 1 byte to frag:
299 0 extra opcode bytes, 1 extra displacement byte. */
306 i386_align_code (fragP
, count
)
310 /* Various efficient no-op patterns for aligning code labels. */
311 /* Note: Don't try to assemble the instructions in the comments. */
312 /* 0L and 0w are not legal */
313 static const char f32_1
[] =
315 static const char f32_2
[] =
316 {0x89,0xf6}; /* movl %esi,%esi */
317 static const char f32_3
[] =
318 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
319 static const char f32_4
[] =
320 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
321 static const char f32_5
[] =
323 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
324 static const char f32_6
[] =
325 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
326 static const char f32_7
[] =
327 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
328 static const char f32_8
[] =
330 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
331 static const char f32_9
[] =
332 {0x89,0xf6, /* movl %esi,%esi */
333 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
334 static const char f32_10
[] =
335 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
336 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
337 static const char f32_11
[] =
338 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
339 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
340 static const char f32_12
[] =
341 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
342 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
343 static const char f32_13
[] =
344 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
345 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
346 static const char f32_14
[] =
347 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
348 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
349 static const char f32_15
[] =
350 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
351 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
352 static const char f16_3
[] =
353 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
354 static const char f16_4
[] =
355 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
356 static const char f16_5
[] =
358 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
359 static const char f16_6
[] =
360 {0x89,0xf6, /* mov %si,%si */
361 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
362 static const char f16_7
[] =
363 {0x8d,0x74,0x00, /* lea 0(%si),%si */
364 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
365 static const char f16_8
[] =
366 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
367 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
368 static const char *const f32_patt
[] = {
369 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
370 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
372 static const char *const f16_patt
[] = {
373 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
374 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
377 if (count
> 0 && count
<= 15)
381 memcpy(fragP
->fr_literal
+ fragP
->fr_fix
,
382 f16_patt
[count
- 1], count
);
383 if (count
> 8) /* adjust jump offset */
384 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
387 memcpy(fragP
->fr_literal
+ fragP
->fr_fix
,
388 f32_patt
[count
- 1], count
);
389 fragP
->fr_var
= count
;
393 static char *output_invalid
PARAMS ((int c
));
394 static int i386_operand
PARAMS ((char *operand_string
));
395 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
396 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
400 static void s_bss
PARAMS ((int));
403 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
405 static INLINE
unsigned int
406 mode_from_disp_size (t
)
409 return (t
& Disp8
) ? 1 : (t
& (Disp16
|Disp32
)) ? 2 : 0;
413 fits_in_signed_byte (num
)
416 return (num
>= -128) && (num
<= 127);
417 } /* fits_in_signed_byte() */
420 fits_in_unsigned_byte (num
)
423 return (num
& 0xff) == num
;
424 } /* fits_in_unsigned_byte() */
427 fits_in_unsigned_word (num
)
430 return (num
& 0xffff) == num
;
431 } /* fits_in_unsigned_word() */
434 fits_in_signed_word (num
)
437 return (-32768 <= num
) && (num
<= 32767);
438 } /* fits_in_signed_word() */
441 smallest_imm_type (num
)
445 /* This code is disabled because all the Imm1 forms in the opcode table
446 are slower on the i486, and they're the versions with the implicitly
447 specified single-position displacement, which has another syntax if
448 you really want to use that form. If you really prefer to have the
449 one-byte-shorter Imm1 form despite these problems, re-enable this
452 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
;
454 return (fits_in_signed_byte (num
)
455 ? (Imm8S
| Imm8
| Imm16
| Imm32
)
456 : fits_in_unsigned_byte (num
)
457 ? (Imm8
| Imm16
| Imm32
)
458 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
461 } /* smallest_imm_type() */
464 offset_in_range (val
, size
)
471 case 1: mask
= ((offsetT
) 1 << 8) - 1; break;
472 case 2: mask
= ((offsetT
) 1 << 16) - 1; break;
473 case 4: mask
= ((offsetT
) 1 << 32) - 1; break;
477 if ((val
& ~ mask
) != 0 && (val
& ~ mask
) != ~ mask
)
479 char buf1
[40], buf2
[40];
481 sprint_value (buf1
, val
);
482 sprint_value (buf2
, val
& mask
);
483 as_warn (_("%s shortened to %s"), buf1
, buf2
);
488 /* Returns 0 if attempting to add a prefix where one from the same
489 class already exists, 1 if non rep/repne added, 2 if rep/repne
503 case CS_PREFIX_OPCODE
:
504 case DS_PREFIX_OPCODE
:
505 case ES_PREFIX_OPCODE
:
506 case FS_PREFIX_OPCODE
:
507 case GS_PREFIX_OPCODE
:
508 case SS_PREFIX_OPCODE
:
512 case REPNE_PREFIX_OPCODE
:
513 case REPE_PREFIX_OPCODE
:
516 case LOCK_PREFIX_OPCODE
:
524 case ADDR_PREFIX_OPCODE
:
528 case DATA_PREFIX_OPCODE
:
535 as_bad (_("same type of prefix used twice"));
540 i
.prefix
[q
] = prefix
;
545 set_16bit_code_flag (new_16bit_code_flag
)
546 int new_16bit_code_flag
;
548 flag_16bit_code
= new_16bit_code_flag
;
553 set_16bit_gcc_code_flag (new_16bit_code_flag
)
554 int new_16bit_code_flag
;
556 flag_16bit_code
= new_16bit_code_flag
;
557 stackop_size
= new_16bit_code_flag
? 'l' : '\0';
561 set_intel_syntax (syntax_flag
)
564 /* Find out if register prefixing is specified. */
565 int ask_naked_reg
= 0;
568 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
570 char *string
= input_line_pointer
;
571 int e
= get_symbol_end ();
573 if (strcmp(string
, "prefix") == 0)
575 else if (strcmp(string
, "noprefix") == 0)
578 as_bad (_("bad argument to syntax directive."));
579 *input_line_pointer
= e
;
581 demand_empty_rest_of_line ();
583 intel_syntax
= syntax_flag
;
585 if (ask_naked_reg
== 0)
588 allow_naked_reg
= (intel_syntax
589 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
591 allow_naked_reg
= 0; /* conservative default */
595 allow_naked_reg
= (ask_naked_reg
< 0);
598 const pseudo_typeS md_pseudo_table
[] =
603 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
604 {"align", s_align_bytes
, 0},
606 {"align", s_align_ptwo
, 0},
608 {"ffloat", float_cons
, 'f'},
609 {"dfloat", float_cons
, 'd'},
610 {"tfloat", float_cons
, 'x'},
612 {"noopt", s_ignore
, 0},
613 {"optim", s_ignore
, 0},
614 {"code16gcc", set_16bit_gcc_code_flag
, 1},
615 {"code16", set_16bit_code_flag
, 1},
616 {"code32", set_16bit_code_flag
, 0},
617 {"intel_syntax", set_intel_syntax
, 1},
618 {"att_syntax", set_intel_syntax
, 0},
622 /* for interface with expression () */
623 extern char *input_line_pointer
;
625 /* hash table for instruction mnemonic lookup */
626 static struct hash_control
*op_hash
;
627 /* hash table for register lookup */
628 static struct hash_control
*reg_hash
;
634 const char *hash_err
;
636 /* initialize op_hash hash table */
637 op_hash
= hash_new ();
640 register const template *optab
;
641 register templates
*core_optab
;
643 optab
= i386_optab
; /* setup for loop */
644 core_optab
= (templates
*) xmalloc (sizeof (templates
));
645 core_optab
->start
= optab
;
650 if (optab
->name
== NULL
651 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
653 /* different name --> ship out current template list;
654 add to hash table; & begin anew */
655 core_optab
->end
= optab
;
656 hash_err
= hash_insert (op_hash
,
662 as_fatal (_("Internal Error: Can't hash %s: %s"),
666 if (optab
->name
== NULL
)
668 core_optab
= (templates
*) xmalloc (sizeof (templates
));
669 core_optab
->start
= optab
;
674 /* initialize reg_hash hash table */
675 reg_hash
= hash_new ();
677 register const reg_entry
*regtab
;
679 for (regtab
= i386_regtab
;
680 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
683 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
689 /* fill in lexical tables: mnemonic_chars, operand_chars. */
694 for (c
= 0; c
< 256; c
++)
699 mnemonic_chars
[c
] = c
;
700 register_chars
[c
] = c
;
701 operand_chars
[c
] = c
;
703 else if (islower (c
))
705 mnemonic_chars
[c
] = c
;
706 register_chars
[c
] = c
;
707 operand_chars
[c
] = c
;
709 else if (isupper (c
))
711 mnemonic_chars
[c
] = tolower (c
);
712 register_chars
[c
] = mnemonic_chars
[c
];
713 operand_chars
[c
] = c
;
716 if (isalpha (c
) || isdigit (c
))
717 identifier_chars
[c
] = c
;
720 identifier_chars
[c
] = c
;
721 operand_chars
[c
] = c
;
726 identifier_chars
['@'] = '@';
728 digit_chars
['-'] = '-';
729 identifier_chars
['_'] = '_';
730 identifier_chars
['.'] = '.';
732 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
733 operand_chars
[(unsigned char) *p
] = *p
;
736 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
737 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
739 record_alignment (text_section
, 2);
740 record_alignment (data_section
, 2);
741 record_alignment (bss_section
, 2);
747 i386_print_statistics (file
)
750 hash_print_statistics (file
, "i386 opcode", op_hash
);
751 hash_print_statistics (file
, "i386 register", reg_hash
);
757 /* debugging routines for md_assemble */
758 static void pi
PARAMS ((char *, i386_insn
*));
759 static void pte
PARAMS ((template *));
760 static void pt
PARAMS ((unsigned int));
761 static void pe
PARAMS ((expressionS
*));
762 static void ps
PARAMS ((symbolS
*));
769 register template *p
;
772 fprintf (stdout
, "%s: template ", line
);
774 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
775 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
776 fprintf (stdout
, " base %x index %x scale %x\n",
777 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
778 for (i
= 0; i
< x
->operands
; i
++)
780 fprintf (stdout
, " #%d: ", i
+ 1);
782 fprintf (stdout
, "\n");
784 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
785 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
786 if (x
->types
[i
] & Imm
)
788 if (x
->types
[i
] & Disp
)
798 fprintf (stdout
, " %d operands ", t
->operands
);
799 fprintf (stdout
, "opcode %x ",
801 if (t
->extension_opcode
!= None
)
802 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
803 if (t
->opcode_modifier
& D
)
804 fprintf (stdout
, "D");
805 if (t
->opcode_modifier
& W
)
806 fprintf (stdout
, "W");
807 fprintf (stdout
, "\n");
808 for (i
= 0; i
< t
->operands
; i
++)
810 fprintf (stdout
, " #%d type ", i
+ 1);
811 pt (t
->operand_types
[i
]);
812 fprintf (stdout
, "\n");
820 fprintf (stdout
, " operation %d\n", e
->X_op
);
821 fprintf (stdout
, " add_number %ld (%lx)\n",
822 (long) e
->X_add_number
, (long) e
->X_add_number
);
825 fprintf (stdout
, " add_symbol ");
826 ps (e
->X_add_symbol
);
827 fprintf (stdout
, "\n");
831 fprintf (stdout
, " op_symbol ");
833 fprintf (stdout
, "\n");
841 fprintf (stdout
, "%s type %s%s",
843 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
844 segment_name (S_GET_SEGMENT (s
)));
863 { BaseIndex
, "BaseIndex" },
867 { InOutPortReg
, "InOutPortReg" },
868 { ShiftCount
, "ShiftCount" },
869 { Control
, "control reg" },
870 { Test
, "test reg" },
871 { Debug
, "debug reg" },
872 { FloatReg
, "FReg" },
873 { FloatAcc
, "FAcc" },
877 { JumpAbsolute
, "Jump Absolute" },
888 register struct type_name
*ty
;
892 fprintf (stdout
, _("Unknown"));
896 for (ty
= type_names
; ty
->mask
; ty
++)
898 fprintf (stdout
, "%s, ", ty
->tname
);
903 #endif /* DEBUG386 */
906 tc_i386_force_relocation (fixp
)
910 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
911 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
916 return fixp
->fx_r_type
== 7;
921 static bfd_reloc_code_real_type reloc
922 PARAMS ((int, int, bfd_reloc_code_real_type
));
924 static bfd_reloc_code_real_type
925 reloc (size
, pcrel
, other
)
928 bfd_reloc_code_real_type other
;
930 if (other
!= NO_RELOC
) return other
;
936 case 1: return BFD_RELOC_8_PCREL
;
937 case 2: return BFD_RELOC_16_PCREL
;
938 case 4: return BFD_RELOC_32_PCREL
;
940 as_bad (_("can not do %d byte pc-relative relocation"), size
);
946 case 1: return BFD_RELOC_8
;
947 case 2: return BFD_RELOC_16
;
948 case 4: return BFD_RELOC_32
;
950 as_bad (_("can not do %d byte relocation"), size
);
953 return BFD_RELOC_NONE
;
957 * Here we decide which fixups can be adjusted to make them relative to
958 * the beginning of the section instead of the symbol. Basically we need
959 * to make sure that the dynamic relocations are done correctly, so in
960 * some cases we force the original symbol to be used.
963 tc_i386_fix_adjustable (fixP
)
966 #if defined (OBJ_ELF) || defined (TE_PE)
967 /* Prevent all adjustments to global symbols, or else dynamic
968 linking will not work correctly. */
969 if (S_IS_EXTERN (fixP
->fx_addsy
))
971 if (S_IS_WEAK (fixP
->fx_addsy
))
974 /* adjust_reloc_syms doesn't know about the GOT */
975 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
976 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
977 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
978 || fixP
->fx_r_type
== BFD_RELOC_RVA
979 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
980 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
985 #define reloc(SIZE,PCREL,OTHER) 0
986 #define BFD_RELOC_16 0
987 #define BFD_RELOC_32 0
988 #define BFD_RELOC_16_PCREL 0
989 #define BFD_RELOC_32_PCREL 0
990 #define BFD_RELOC_386_PLT32 0
991 #define BFD_RELOC_386_GOT32 0
992 #define BFD_RELOC_386_GOTOFF 0
996 intel_float_operand
PARAMS ((char *mnemonic
));
999 intel_float_operand (mnemonic
)
1002 if (mnemonic
[0] == 'f' && mnemonic
[1] =='i')
1005 if (mnemonic
[0] == 'f')
1011 /* This is the guts of the machine-dependent assembler. LINE points to a
1012 machine dependent instruction. This function is supposed to emit
1013 the frags/bytes it assembles to. */
1019 /* Points to template once we've found it. */
1022 /* Count the size of the instruction generated. */
1027 char mnemonic
[MAX_MNEM_SIZE
];
1029 /* Initialize globals. */
1030 memset (&i
, '\0', sizeof (i
));
1031 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1032 i
.disp_reloc
[j
] = NO_RELOC
;
1033 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1034 memset (im_expressions
, '\0', sizeof (im_expressions
));
1035 save_stack_p
= save_stack
; /* reset stack pointer */
1037 /* First parse an instruction mnemonic & call i386_operand for the operands.
1038 We assume that the scrubber has arranged it so that line[0] is the valid
1039 start of a (possibly prefixed) mnemonic. */
1042 char *token_start
= l
;
1045 /* Non-zero if we found a prefix only acceptable with string insns. */
1046 const char *expecting_string_instruction
= NULL
;
1051 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1054 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1056 as_bad (_("no such 386 instruction: `%s'"), token_start
);
1061 if (!is_space_char (*l
)
1062 && *l
!= END_OF_INSN
1063 && *l
!= PREFIX_SEPARATOR
)
1065 as_bad (_("invalid character %s in mnemonic"),
1066 output_invalid (*l
));
1069 if (token_start
== l
)
1071 if (*l
== PREFIX_SEPARATOR
)
1072 as_bad (_("expecting prefix; got nothing"));
1074 as_bad (_("expecting mnemonic; got nothing"));
1078 /* Look up instruction (or prefix) via hash table. */
1079 current_templates
= hash_find (op_hash
, mnemonic
);
1081 if (*l
!= END_OF_INSN
1082 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1083 && current_templates
1084 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1086 /* If we are in 16-bit mode, do not allow addr16 or data16.
1087 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1088 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1089 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1092 as_bad (_("redundant %s prefix"),
1093 current_templates
->start
->name
);
1096 /* Add prefix, checking for repeated prefixes. */
1097 switch (add_prefix (current_templates
->start
->base_opcode
))
1102 expecting_string_instruction
=
1103 current_templates
->start
->name
;
1106 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1113 if (!current_templates
)
1115 /* See if we can get a match by trimming off a suffix. */
1118 case WORD_MNEM_SUFFIX
:
1119 case BYTE_MNEM_SUFFIX
:
1120 case SHORT_MNEM_SUFFIX
:
1121 case LONG_MNEM_SUFFIX
:
1122 i
.suffix
= mnem_p
[-1];
1124 current_templates
= hash_find (op_hash
, mnemonic
);
1128 case DWORD_MNEM_SUFFIX
:
1131 i
.suffix
= mnem_p
[-1];
1133 current_templates
= hash_find (op_hash
, mnemonic
);
1137 if (!current_templates
)
1139 as_bad (_("no such 386 instruction: `%s'"), token_start
);
1144 /* check for rep/repne without a string instruction */
1145 if (expecting_string_instruction
1146 && !(current_templates
->start
->opcode_modifier
& IsString
))
1148 as_bad (_("expecting string instruction after `%s'"),
1149 expecting_string_instruction
);
1153 /* There may be operands to parse. */
1154 if (*l
!= END_OF_INSN
)
1156 /* parse operands */
1158 /* 1 if operand is pending after ','. */
1159 unsigned int expecting_operand
= 0;
1161 /* Non-zero if operand parens not balanced. */
1162 unsigned int paren_not_balanced
;
1166 /* skip optional white space before operand */
1167 if (is_space_char (*l
))
1169 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1171 as_bad (_("invalid character %s before operand %d"),
1172 output_invalid (*l
),
1176 token_start
= l
; /* after white space */
1177 paren_not_balanced
= 0;
1178 while (paren_not_balanced
|| *l
!= ',')
1180 if (*l
== END_OF_INSN
)
1182 if (paren_not_balanced
)
1185 as_bad (_("unbalanced parenthesis in operand %d."),
1188 as_bad (_("unbalanced brackets in operand %d."),
1193 break; /* we are done */
1195 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1197 as_bad (_("invalid character %s in operand %d"),
1198 output_invalid (*l
),
1205 ++paren_not_balanced
;
1207 --paren_not_balanced
;
1212 ++paren_not_balanced
;
1214 --paren_not_balanced
;
1218 if (l
!= token_start
)
1219 { /* yes, we've read in another operand */
1220 unsigned int operand_ok
;
1221 this_operand
= i
.operands
++;
1222 if (i
.operands
> MAX_OPERANDS
)
1224 as_bad (_("spurious operands; (%d operands/instruction max)"),
1228 /* now parse operand adding info to 'i' as we go along */
1229 END_STRING_AND_SAVE (l
);
1232 operand_ok
= i386_intel_operand (token_start
, intel_float_operand (mnemonic
));
1234 operand_ok
= i386_operand (token_start
);
1236 RESTORE_END_STRING (l
); /* restore old contents */
1242 if (expecting_operand
)
1244 expecting_operand_after_comma
:
1245 as_bad (_("expecting operand after ','; got nothing"));
1250 as_bad (_("expecting operand before ','; got nothing"));
1255 /* now *l must be either ',' or END_OF_INSN */
1258 if (*++l
== END_OF_INSN
)
1259 { /* just skip it, if it's \n complain */
1260 goto expecting_operand_after_comma
;
1262 expecting_operand
= 1;
1265 while (*l
!= END_OF_INSN
); /* until we get end of insn */
1269 /* Now we've parsed the mnemonic into a set of templates, and have the
1272 Next, we find a template that matches the given insn,
1273 making sure the overlap of the given operands types is consistent
1274 with the template operand types. */
1276 #define MATCH(overlap, given, template) \
1277 ((overlap & ~JumpAbsolute) \
1278 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1280 /* If given types r0 and r1 are registers they must be of the same type
1281 unless the expected operand type register overlap is null.
1282 Note that Acc in a template matches every size of reg. */
1283 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1284 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1285 ((g0) & Reg) == ((g1) & Reg) || \
1286 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1289 register unsigned int overlap0
, overlap1
;
1290 unsigned int overlap2
;
1291 unsigned int found_reverse_match
;
1294 /* All intel opcodes have reversed operands except for "bound" and
1295 "enter". We also don't reverse intersegment "jmp" and "call"
1296 instructions with 2 immediate operands so that the immediate segment
1297 precedes the offset, as it does when in AT&T mode. "enter" and the
1298 intersegment "jmp" and "call" instructions are the only ones that
1299 have two immediate operands. */
1300 if (intel_syntax
&& i
.operands
> 1
1301 && (strcmp (mnemonic
, "bound") != 0)
1302 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1304 union i386_op temp_op
;
1305 unsigned int temp_type
;
1309 if (i
.operands
== 2)
1314 else if (i
.operands
== 3)
1319 temp_type
= i
.types
[xchg2
];
1320 i
.types
[xchg2
] = i
.types
[xchg1
];
1321 i
.types
[xchg1
] = temp_type
;
1322 temp_op
= i
.op
[xchg2
];
1323 i
.op
[xchg2
] = i
.op
[xchg1
];
1324 i
.op
[xchg1
] = temp_op
;
1326 if (i
.mem_operands
== 2)
1328 const seg_entry
*temp_seg
;
1329 temp_seg
= i
.seg
[0];
1330 i
.seg
[0] = i
.seg
[1];
1331 i
.seg
[1] = temp_seg
;
1337 /* Try to ensure constant immediates are represented in the smallest
1339 char guess_suffix
= 0;
1343 guess_suffix
= i
.suffix
;
1344 else if (i
.reg_operands
)
1346 /* Figure out a suffix from the last register operand specified.
1347 We can't do this properly yet, ie. excluding InOutPortReg,
1348 but the following works for instructions with immediates.
1349 In any case, we can't set i.suffix yet. */
1350 for (op
= i
.operands
; --op
>= 0; )
1351 if (i
.types
[op
] & Reg
)
1353 if (i
.types
[op
] & Reg8
)
1354 guess_suffix
= BYTE_MNEM_SUFFIX
;
1355 else if (i
.types
[op
] & Reg16
)
1356 guess_suffix
= WORD_MNEM_SUFFIX
;
1360 else if (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0))
1361 guess_suffix
= WORD_MNEM_SUFFIX
;
1363 for (op
= i
.operands
; --op
>= 0; )
1364 if ((i
.types
[op
] & Imm
)
1365 && i
.op
[op
].imms
->X_op
== O_constant
)
1367 /* If a suffix is given, this operand may be shortened. */
1368 switch (guess_suffix
)
1370 case WORD_MNEM_SUFFIX
:
1371 i
.types
[op
] |= Imm16
;
1373 case BYTE_MNEM_SUFFIX
:
1374 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
;
1378 /* If this operand is at most 16 bits, convert it to a
1379 signed 16 bit number before trying to see whether it will
1380 fit in an even smaller size. This allows a 16-bit operand
1381 such as $0xffe0 to be recognised as within Imm8S range. */
1382 if ((i
.types
[op
] & Imm16
)
1383 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1385 i
.op
[op
].imms
->X_add_number
=
1386 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1388 i
.types
[op
] |= smallest_imm_type ((long) i
.op
[op
].imms
->X_add_number
);
1395 found_reverse_match
= 0;
1396 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1398 : (i
.suffix
== WORD_MNEM_SUFFIX
1400 : (i
.suffix
== SHORT_MNEM_SUFFIX
1402 : (i
.suffix
== LONG_MNEM_SUFFIX
1404 : (i
.suffix
== DWORD_MNEM_SUFFIX
1406 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1408 for (t
= current_templates
->start
;
1409 t
< current_templates
->end
;
1412 /* Must have right number of operands. */
1413 if (i
.operands
!= t
->operands
)
1416 /* Check the suffix, except for some instructions in intel mode. */
1417 if ((t
->opcode_modifier
& suffix_check
)
1419 && t
->base_opcode
== 0xd9
1420 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1421 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1424 else if (!t
->operands
)
1425 break; /* 0 operands always matches */
1427 overlap0
= i
.types
[0] & t
->operand_types
[0];
1428 switch (t
->operands
)
1431 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1436 overlap1
= i
.types
[1] & t
->operand_types
[1];
1437 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1438 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1439 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1440 t
->operand_types
[0],
1441 overlap1
, i
.types
[1],
1442 t
->operand_types
[1]))
1445 /* check if other direction is valid ... */
1446 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1449 /* try reversing direction of operands */
1450 overlap0
= i
.types
[0] & t
->operand_types
[1];
1451 overlap1
= i
.types
[1] & t
->operand_types
[0];
1452 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1453 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1454 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1455 t
->operand_types
[1],
1456 overlap1
, i
.types
[1],
1457 t
->operand_types
[0]))
1459 /* does not match either direction */
1462 /* found_reverse_match holds which of D or FloatDR
1464 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1467 /* found a forward 2 operand match here */
1468 if (t
->operands
== 3)
1470 /* Here we make use of the fact that there are no
1471 reverse match 3 operand instructions, and all 3
1472 operand instructions only need to be checked for
1473 register consistency between operands 2 and 3. */
1474 overlap2
= i
.types
[2] & t
->operand_types
[2];
1475 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1476 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1477 t
->operand_types
[1],
1478 overlap2
, i
.types
[2],
1479 t
->operand_types
[2]))
1483 /* found either forward/reverse 2 or 3 operand match here:
1484 slip through to break */
1486 break; /* we've found a match; break out of loop */
1487 } /* for (t = ... */
1488 if (t
== current_templates
->end
)
1489 { /* we found no match */
1490 as_bad (_("suffix or operands invalid for `%s'"),
1491 current_templates
->start
->name
);
1496 && (i
.types
[0] & JumpAbsolute
) != (t
->operand_types
[0] & JumpAbsolute
))
1498 as_warn (_("indirect %s without `*'"), t
->name
);
1501 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
)) == (IsPrefix
|IgnoreSize
))
1503 /* Warn them that a data or address size prefix doesn't affect
1504 assembly of the next line of code. */
1505 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1508 /* Copy the template we found. */
1510 if (found_reverse_match
)
1512 /* If we found a reverse match we must alter the opcode
1513 direction bit. found_reverse_match holds bits to change
1514 (different for int & float insns). */
1516 i
.tm
.base_opcode
^= found_reverse_match
;
1518 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1519 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1522 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1525 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1526 i
.tm
.base_opcode
^= FloatR
;
1528 if (i
.tm
.opcode_modifier
& FWait
)
1529 if (! add_prefix (FWAIT_OPCODE
))
1532 /* Check string instruction segment overrides */
1533 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1535 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1536 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1538 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1540 as_bad (_("`%s' operand %d must use `%%es' segment"),
1545 /* There's only ever one segment override allowed per instruction.
1546 This instruction possibly has a legal segment override on the
1547 second operand, so copy the segment to where non-string
1548 instructions store it, allowing common code. */
1549 i
.seg
[0] = i
.seg
[1];
1551 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1553 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1555 as_bad (_("`%s' operand %d must use `%%es' segment"),
1563 /* If matched instruction specifies an explicit instruction mnemonic
1565 if (i
.tm
.opcode_modifier
& (Size16
| Size32
))
1567 if (i
.tm
.opcode_modifier
& Size16
)
1568 i
.suffix
= WORD_MNEM_SUFFIX
;
1570 i
.suffix
= LONG_MNEM_SUFFIX
;
1572 else if (i
.reg_operands
)
1574 /* If there's no instruction mnemonic suffix we try to invent one
1575 based on register operands. */
1578 /* We take i.suffix from the last register operand specified,
1579 Destination register type is more significant than source
1582 for (op
= i
.operands
; --op
>= 0; )
1583 if ((i
.types
[op
] & Reg
)
1584 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1586 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1587 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1592 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1595 for (op
= i
.operands
; --op
>= 0; )
1597 /* If this is an eight bit register, it's OK. If it's
1598 the 16 or 32 bit version of an eight bit register,
1599 we will just use the low portion, and that's OK too. */
1600 if (i
.types
[op
] & Reg8
)
1603 /* movzx and movsx should not generate this warning. */
1605 && (i
.tm
.base_opcode
== 0xfb7
1606 || i
.tm
.base_opcode
== 0xfb6
1607 || i
.tm
.base_opcode
== 0xfbe
1608 || i
.tm
.base_opcode
== 0xfbf))
1611 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1613 /* Check that the template allows eight bit regs
1614 This kills insns such as `orb $1,%edx', which
1615 maybe should be allowed. */
1616 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1620 #if REGISTER_WARNINGS
1621 if ((i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1622 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1623 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1624 i
.op
[op
].regs
->reg_name
,
1629 /* Any other register is bad */
1630 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1632 | Control
| Debug
| Test
1633 | FloatReg
| FloatAcc
))
1635 as_bad (_("`%%%s' not allowed with `%s%c'"),
1636 i
.op
[op
].regs
->reg_name
,
1643 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1646 for (op
= i
.operands
; --op
>= 0; )
1647 /* Reject eight bit registers, except where the template
1648 requires them. (eg. movzb) */
1649 if ((i
.types
[op
] & Reg8
) != 0
1650 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1652 as_bad (_("`%%%s' not allowed with `%s%c'"),
1653 i
.op
[op
].regs
->reg_name
,
1658 #if REGISTER_WARNINGS
1659 /* Warn if the e prefix on a general reg is missing. */
1660 else if ((i
.types
[op
] & Reg16
) != 0
1661 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1663 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1664 (i
.op
[op
].regs
+ 8)->reg_name
,
1665 i
.op
[op
].regs
->reg_name
,
1670 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
1673 for (op
= i
.operands
; --op
>= 0; )
1674 /* Reject eight bit registers, except where the template
1675 requires them. (eg. movzb) */
1676 if ((i
.types
[op
] & Reg8
) != 0
1677 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1679 as_bad (_("`%%%s' not allowed with `%s%c'"),
1680 i
.op
[op
].regs
->reg_name
,
1685 #if REGISTER_WARNINGS
1686 /* Warn if the e prefix on a general reg is present. */
1687 else if ((i
.types
[op
] & Reg32
) != 0
1688 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
1690 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1691 (i
.op
[op
].regs
- 8)->reg_name
,
1692 i
.op
[op
].regs
->reg_name
,
1700 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
1702 i
.suffix
= stackop_size
;
1705 /* Make still unresolved immediate matches conform to size of immediate
1706 given in i.suffix. Note: overlap2 cannot be an immediate! */
1707 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1708 && overlap0
!= Imm8
&& overlap0
!= Imm8S
1709 && overlap0
!= Imm16
&& overlap0
!= Imm32
)
1713 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1714 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1716 else if (overlap0
== (Imm16
| Imm32
))
1719 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1723 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1727 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1728 && overlap1
!= Imm8
&& overlap1
!= Imm8S
1729 && overlap1
!= Imm16
&& overlap1
!= Imm32
)
1733 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1734 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1736 else if (overlap1
== (Imm16
| Imm32
))
1739 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1743 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1747 assert ((overlap2
& Imm
) == 0);
1749 i
.types
[0] = overlap0
;
1750 if (overlap0
& ImplicitRegister
)
1752 if (overlap0
& Imm1
)
1753 i
.imm_operands
= 0; /* kludge for shift insns */
1755 i
.types
[1] = overlap1
;
1756 if (overlap1
& ImplicitRegister
)
1759 i
.types
[2] = overlap2
;
1760 if (overlap2
& ImplicitRegister
)
1763 /* Finalize opcode. First, we change the opcode based on the operand
1764 size given by i.suffix: We need not change things for byte insns. */
1766 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
1768 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1772 /* For movzx and movsx, need to check the register type */
1774 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
1775 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
1777 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1779 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
1780 if (!add_prefix (prefix
))
1784 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
1786 /* It's not a byte, select word/dword operation. */
1787 if (i
.tm
.opcode_modifier
& W
)
1789 if (i
.tm
.opcode_modifier
& ShortForm
)
1790 i
.tm
.base_opcode
|= 8;
1792 i
.tm
.base_opcode
|= 1;
1794 /* Now select between word & dword operations via the operand
1795 size prefix, except for instructions that will ignore this
1797 if (((intel_syntax
&& (i
.suffix
== DWORD_MNEM_SUFFIX
))
1798 || i
.suffix
== LONG_MNEM_SUFFIX
) == flag_16bit_code
1799 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
1801 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1802 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
1803 prefix
= ADDR_PREFIX_OPCODE
;
1805 if (! add_prefix (prefix
))
1808 /* Size floating point instruction. */
1809 if (i
.suffix
== LONG_MNEM_SUFFIX
1810 || (intel_syntax
&& i
.suffix
== DWORD_MNEM_SUFFIX
))
1812 if (i
.tm
.opcode_modifier
& FloatMF
)
1813 i
.tm
.base_opcode
^= 4;
1817 if (i
.tm
.opcode_modifier
& ImmExt
)
1819 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1820 opcode suffix which is coded in the same place as an 8-bit
1821 immediate field would be. Here we fake an 8-bit immediate
1822 operand from the opcode suffix stored in tm.extension_opcode. */
1826 assert(i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1828 exp
= &im_expressions
[i
.imm_operands
++];
1829 i
.op
[i
.operands
].imms
= exp
;
1830 i
.types
[i
.operands
++] = Imm8
;
1831 exp
->X_op
= O_constant
;
1832 exp
->X_add_number
= i
.tm
.extension_opcode
;
1833 i
.tm
.extension_opcode
= None
;
1836 /* For insns with operands there are more diddles to do to the opcode. */
1839 /* Default segment register this instruction will use
1840 for memory accesses. 0 means unknown.
1841 This is only for optimizing out unnecessary segment overrides. */
1842 const seg_entry
*default_seg
= 0;
1844 /* The imul $imm, %reg instruction is converted into
1845 imul $imm, %reg, %reg, and the clr %reg instruction
1846 is converted into xor %reg, %reg. */
1847 if (i
.tm
.opcode_modifier
& regKludge
)
1849 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
1850 /* Pretend we saw the extra register operand. */
1851 assert (i
.op
[first_reg_op
+1].regs
== 0);
1852 i
.op
[first_reg_op
+1].regs
= i
.op
[first_reg_op
].regs
;
1853 i
.types
[first_reg_op
+1] = i
.types
[first_reg_op
];
1857 if (i
.tm
.opcode_modifier
& ShortForm
)
1859 /* The register or float register operand is in operand 0 or 1. */
1860 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
1861 /* Register goes in low 3 bits of opcode. */
1862 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
1863 if ((i
.tm
.opcode_modifier
& Ugh
) != 0)
1865 /* Warn about some common errors, but press on regardless.
1866 The first case can be generated by gcc (<= 2.8.1). */
1867 if (i
.operands
== 2)
1869 /* reversed arguments on faddp, fsubp, etc. */
1870 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
1871 i
.op
[1].regs
->reg_name
,
1872 i
.op
[0].regs
->reg_name
);
1876 /* extraneous `l' suffix on fp insn */
1877 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
1878 i
.op
[0].regs
->reg_name
);
1882 else if (i
.tm
.opcode_modifier
& Modrm
)
1884 /* The opcode is completed (modulo i.tm.extension_opcode which
1885 must be put into the modrm byte).
1886 Now, we make the modrm & index base bytes based on all the
1887 info we've collected. */
1889 /* i.reg_operands MUST be the number of real register operands;
1890 implicit registers do not count. */
1891 if (i
.reg_operands
== 2)
1893 unsigned int source
, dest
;
1894 source
= ((i
.types
[0]
1895 & (Reg
| RegMMX
| RegXMM
1897 | Control
| Debug
| Test
))
1902 /* One of the register operands will be encoded in the
1903 i.tm.reg field, the other in the combined i.tm.mode
1904 and i.tm.regmem fields. If no form of this
1905 instruction supports a memory destination operand,
1906 then we assume the source operand may sometimes be
1907 a memory operand and so we need to store the
1908 destination in the i.rm.reg field. */
1909 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
1911 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
1912 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
1916 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
1917 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
1921 { /* if it's not 2 reg operands... */
1924 unsigned int fake_zero_displacement
= 0;
1925 unsigned int op
= ((i
.types
[0] & AnyMem
)
1927 : (i
.types
[1] & AnyMem
) ? 1 : 2);
1934 if (! i
.disp_operands
)
1935 fake_zero_displacement
= 1;
1938 /* Operand is just <disp> */
1939 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
1941 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
1942 i
.types
[op
] &= ~Disp
;
1943 i
.types
[op
] |= Disp16
;
1947 i
.rm
.regmem
= NO_BASE_REGISTER
;
1948 i
.types
[op
] &= ~Disp
;
1949 i
.types
[op
] |= Disp32
;
1952 else /* ! i.base_reg && i.index_reg */
1954 i
.sib
.index
= i
.index_reg
->reg_num
;
1955 i
.sib
.base
= NO_BASE_REGISTER
;
1956 i
.sib
.scale
= i
.log2_scale_factor
;
1957 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
1958 i
.types
[op
] &= ~Disp
;
1959 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
1962 else if (i
.base_reg
->reg_type
& Reg16
)
1964 switch (i
.base_reg
->reg_num
)
1969 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
1970 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
1977 if ((i
.types
[op
] & Disp
) == 0)
1979 /* fake (%bp) into 0(%bp) */
1980 i
.types
[op
] |= Disp8
;
1981 fake_zero_displacement
= 1;
1984 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
1985 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
1987 default: /* (%si) -> 4 or (%di) -> 5 */
1988 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
1990 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
1992 else /* i.base_reg and 32 bit mode */
1994 i
.rm
.regmem
= i
.base_reg
->reg_num
;
1995 i
.sib
.base
= i
.base_reg
->reg_num
;
1996 if (i
.base_reg
->reg_num
== EBP_REG_NUM
)
1999 if (i
.disp_operands
== 0)
2001 fake_zero_displacement
= 1;
2002 i
.types
[op
] |= Disp8
;
2005 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2009 i
.sib
.scale
= i
.log2_scale_factor
;
2012 /* <disp>(%esp) becomes two byte modrm
2013 with no index register. We've already
2014 stored the code for esp in i.rm.regmem
2015 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2016 base register besides %esp will not use
2017 the extra modrm byte. */
2018 i
.sib
.index
= NO_INDEX_REGISTER
;
2019 #if ! SCALE1_WHEN_NO_INDEX
2020 /* Another case where we force the second
2022 if (i
.log2_scale_factor
)
2023 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2028 i
.sib
.index
= i
.index_reg
->reg_num
;
2029 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2031 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2034 if (fake_zero_displacement
)
2036 /* Fakes a zero displacement assuming that i.types[op]
2037 holds the correct displacement size. */
2040 assert (i
.op
[op
].disps
== 0);
2041 exp
= &disp_expressions
[i
.disp_operands
++];
2042 i
.op
[op
].disps
= exp
;
2043 exp
->X_op
= O_constant
;
2044 exp
->X_add_number
= 0;
2045 exp
->X_add_symbol
= (symbolS
*) 0;
2046 exp
->X_op_symbol
= (symbolS
*) 0;
2050 /* Fill in i.rm.reg or i.rm.regmem field with register
2051 operand (if any) based on i.tm.extension_opcode.
2052 Again, we must be careful to make sure that
2053 segment/control/debug/test/MMX registers are coded
2054 into the i.rm.reg field. */
2059 & (Reg
| RegMMX
| RegXMM
2061 | Control
| Debug
| Test
))
2064 & (Reg
| RegMMX
| RegXMM
2066 | Control
| Debug
| Test
))
2069 /* If there is an extension opcode to put here, the
2070 register number must be put into the regmem field. */
2071 if (i
.tm
.extension_opcode
!= None
)
2072 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2074 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2076 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2077 we must set it to 3 to indicate this is a register
2078 operand in the regmem field. */
2079 if (!i
.mem_operands
)
2083 /* Fill in i.rm.reg field with extension opcode (if any). */
2084 if (i
.tm
.extension_opcode
!= None
)
2085 i
.rm
.reg
= i
.tm
.extension_opcode
;
2088 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2090 if (i
.tm
.base_opcode
== POP_SEG_SHORT
&& i
.op
[0].regs
->reg_num
== 1)
2092 as_bad (_("you can't `pop %%cs'"));
2095 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2097 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2101 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2103 /* For the string instructions that allow a segment override
2104 on one of their operands, the default segment is ds. */
2108 /* If a segment was explicitly specified,
2109 and the specified segment is not the default,
2110 use an opcode prefix to select it.
2111 If we never figured out what the default segment is,
2112 then default_seg will be zero at this point,
2113 and the specified segment prefix will always be used. */
2114 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2116 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2120 else if ((i
.tm
.opcode_modifier
& Ugh
) != 0)
2122 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2123 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2127 /* Handle conversion of 'int $3' --> special int3 insn. */
2128 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2130 i
.tm
.base_opcode
= INT3_OPCODE
;
2134 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2135 && i
.op
[0].disps
->X_op
== O_constant
)
2137 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2138 the absolute address given by the constant. Since ix86 jumps and
2139 calls are pc relative, we need to generate a reloc. */
2140 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2141 i
.op
[0].disps
->X_op
= O_symbol
;
2144 /* We are ready to output the insn. */
2149 if (i
.tm
.opcode_modifier
& Jump
)
2156 if (flag_16bit_code
)
2160 if (i
.prefix
[DATA_PREFIX
])
2171 if (i
.prefixes
!= 0 && !intel_syntax
)
2172 as_warn (_("skipping prefixes on this instruction"));
2174 /* It's always a symbol; End frag & setup for relax.
2175 Make sure there is enough room in this frag for the largest
2176 instruction we may generate in md_convert_frag. This is 2
2177 bytes for the opcode and room for the prefix and largest
2179 frag_grow (prefix
+ 2 + size
);
2180 insn_size
+= prefix
+ 1;
2181 /* Prefix and 1 opcode byte go in fr_fix. */
2182 p
= frag_more (prefix
+ 1);
2184 *p
++ = DATA_PREFIX_OPCODE
;
2185 *p
= i
.tm
.base_opcode
;
2186 /* 1 possible extra opcode + displacement go in fr_var. */
2187 frag_var (rs_machine_dependent
,
2190 ((unsigned char) *p
== JUMP_PC_RELATIVE
2191 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2192 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2193 i
.op
[0].disps
->X_add_symbol
,
2194 i
.op
[0].disps
->X_add_number
,
2197 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2201 if (i
.tm
.opcode_modifier
& JumpByte
)
2203 /* This is a loop or jecxz type instruction. */
2205 if (i
.prefix
[ADDR_PREFIX
])
2208 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2217 if (flag_16bit_code
)
2220 if (i
.prefix
[DATA_PREFIX
])
2223 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2233 if (i
.prefixes
!= 0 && !intel_syntax
)
2234 as_warn (_("skipping prefixes on this instruction"));
2236 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2238 insn_size
+= 1 + size
;
2239 p
= frag_more (1 + size
);
2243 /* opcode can be at most two bytes */
2244 insn_size
+= 2 + size
;
2245 p
= frag_more (2 + size
);
2246 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2248 *p
++ = i
.tm
.base_opcode
& 0xff;
2250 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2251 i
.op
[0].disps
, 1, reloc (size
, 1, i
.disp_reloc
[0]));
2253 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2260 if (flag_16bit_code
)
2264 if (i
.prefix
[DATA_PREFIX
])
2275 if (i
.prefixes
!= 0 && !intel_syntax
)
2276 as_warn (_("skipping prefixes on this instruction"));
2278 insn_size
+= prefix
+ 1 + 2 + size
; /* 1 opcode; 2 segment; offset */
2279 p
= frag_more (prefix
+ 1 + 2 + size
);
2281 *p
++ = DATA_PREFIX_OPCODE
;
2282 *p
++ = i
.tm
.base_opcode
;
2283 if (i
.op
[1].imms
->X_op
== O_constant
)
2285 offsetT n
= i
.op
[1].imms
->X_add_number
;
2288 && !fits_in_unsigned_word (n
)
2289 && !fits_in_signed_word (n
))
2291 as_bad (_("16-bit jump out of range"));
2294 md_number_to_chars (p
, n
, size
);
2297 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2298 i
.op
[1].imms
, 0, reloc (size
, 0, i
.disp_reloc
[0]));
2299 if (i
.op
[0].imms
->X_op
!= O_constant
)
2300 as_bad (_("can't handle non absolute segment in `%s'"),
2302 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2306 /* Output normal instructions here. */
2309 /* The prefix bytes. */
2311 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2318 md_number_to_chars (p
, (valueT
) *q
, 1);
2322 /* Now the opcode; be careful about word order here! */
2323 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2326 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2328 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2332 /* put out high byte first: can't use md_number_to_chars! */
2333 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2334 *p
= i
.tm
.base_opcode
& 0xff;
2337 { /* opcode is either 3 or 4 bytes */
2338 if (i
.tm
.base_opcode
& 0xff000000)
2342 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2349 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2350 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2351 *p
= (i
.tm
.base_opcode
) & 0xff;
2354 /* Now the modrm byte and sib byte (if present). */
2355 if (i
.tm
.opcode_modifier
& Modrm
)
2359 md_number_to_chars (p
,
2360 (valueT
) (i
.rm
.regmem
<< 0
2364 /* If i.rm.regmem == ESP (4)
2365 && i.rm.mode != (Register mode)
2367 ==> need second modrm byte. */
2368 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2370 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2374 md_number_to_chars (p
,
2375 (valueT
) (i
.sib
.base
<< 0
2377 | i
.sib
.scale
<< 6),
2382 if (i
.disp_operands
)
2384 register unsigned int n
;
2386 for (n
= 0; n
< i
.operands
; n
++)
2388 if (i
.types
[n
] & Disp
)
2390 if (i
.op
[n
].disps
->X_op
== O_constant
)
2396 if (i
.types
[n
] & (Disp8
| Disp16
))
2399 if (i
.types
[n
] & Disp8
)
2402 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2405 p
= frag_more (size
);
2406 md_number_to_chars (p
, val
, size
);
2412 if (i
.types
[n
] & Disp16
)
2416 p
= frag_more (size
);
2417 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2419 reloc (size
, 0, i
.disp_reloc
[n
]));
2423 } /* end displacement output */
2425 /* output immediate */
2428 register unsigned int n
;
2430 for (n
= 0; n
< i
.operands
; n
++)
2432 if (i
.types
[n
] & Imm
)
2434 if (i
.op
[n
].imms
->X_op
== O_constant
)
2440 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
))
2443 if (i
.types
[n
] & (Imm8
| Imm8S
))
2446 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
2449 p
= frag_more (size
);
2450 md_number_to_chars (p
, val
, size
);
2453 { /* not absolute_section */
2454 /* Need a 32-bit fixup (don't support 8bit
2455 non-absolute imms). Try to support other
2457 #ifdef BFD_ASSEMBLER
2458 enum bfd_reloc_code_real reloc_type
;
2464 if (i
.types
[n
] & Imm16
)
2466 else if (i
.types
[n
] & (Imm8
| Imm8S
))
2470 p
= frag_more (size
);
2471 reloc_type
= reloc (size
, 0, i
.disp_reloc
[0]);
2472 #ifdef BFD_ASSEMBLER
2473 if (reloc_type
== BFD_RELOC_32
2475 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
2476 && (i
.op
[n
].imms
->X_op
== O_symbol
2477 || (i
.op
[n
].imms
->X_op
== O_add
2478 && ((symbol_get_value_expression
2479 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
2482 reloc_type
= BFD_RELOC_386_GOTPC
;
2483 i
.op
[n
].imms
->X_add_number
+= 3;
2486 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2487 i
.op
[n
].imms
, 0, reloc_type
);
2491 } /* end immediate output */
2499 #endif /* DEBUG386 */
2503 static int i386_immediate
PARAMS ((char *));
2506 i386_immediate (imm_start
)
2509 char *save_input_line_pointer
;
2513 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
2515 as_bad (_("only 1 or 2 immediate operands are allowed"));
2519 exp
= &im_expressions
[i
.imm_operands
++];
2520 i
.op
[this_operand
].imms
= exp
;
2522 if (is_space_char (*imm_start
))
2525 save_input_line_pointer
= input_line_pointer
;
2526 input_line_pointer
= imm_start
;
2531 * We can have operands of the form
2532 * <symbol>@GOTOFF+<nnn>
2533 * Take the easy way out here and copy everything
2534 * into a temporary buffer...
2538 cp
= strchr (input_line_pointer
, '@');
2545 /* GOT relocations are not supported in 16 bit mode */
2546 if (flag_16bit_code
)
2547 as_bad (_("GOT relocations not supported in 16 bit mode"));
2549 if (GOT_symbol
== NULL
)
2550 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2552 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2554 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2557 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2559 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2562 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2564 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2568 as_bad (_("bad reloc specifier in expression"));
2570 /* Replace the relocation token with ' ', so that errors like
2571 foo@GOTOFF1 will be detected. */
2572 first
= cp
- input_line_pointer
;
2573 tmpbuf
= (char *) alloca (strlen(input_line_pointer
));
2574 memcpy (tmpbuf
, input_line_pointer
, first
);
2575 tmpbuf
[first
] = ' ';
2576 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2577 input_line_pointer
= tmpbuf
;
2582 exp_seg
= expression (exp
);
2585 if (*input_line_pointer
)
2586 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
2588 input_line_pointer
= save_input_line_pointer
;
2590 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2592 /* missing or bad expr becomes absolute 0 */
2593 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2595 exp
->X_op
= O_constant
;
2596 exp
->X_add_number
= 0;
2597 exp
->X_add_symbol
= (symbolS
*) 0;
2598 exp
->X_op_symbol
= (symbolS
*) 0;
2601 if (exp
->X_op
== O_constant
)
2603 i
.types
[this_operand
] |= Imm32
; /* Size it properly later. */
2605 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2607 #ifdef BFD_ASSEMBLER
2608 OUTPUT_FLAVOR
== bfd_target_aout_flavour
&&
2610 exp_seg
!= text_section
2611 && exp_seg
!= data_section
2612 && exp_seg
!= bss_section
2613 && exp_seg
!= undefined_section
2614 #ifdef BFD_ASSEMBLER
2615 && !bfd_is_com_section (exp_seg
)
2619 #ifdef BFD_ASSEMBLER
2620 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2622 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2629 /* This is an address. The size of the address will be
2630 determined later, depending on destination register,
2631 suffix, or the default for the section. We exclude
2632 Imm8S here so that `push $foo' and other instructions
2633 with an Imm8S form will use Imm16 or Imm32. */
2634 i
.types
[this_operand
] |= (Imm8
| Imm16
| Imm32
);
2640 static int i386_scale
PARAMS ((char *));
2646 if (!isdigit (*scale
))
2653 i
.log2_scale_factor
= 0;
2656 i
.log2_scale_factor
= 1;
2659 i
.log2_scale_factor
= 2;
2662 i
.log2_scale_factor
= 3;
2666 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
2670 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
2672 as_warn (_("scale factor of %d without an index register"),
2673 1 << i
.log2_scale_factor
);
2674 #if SCALE1_WHEN_NO_INDEX
2675 i
.log2_scale_factor
= 0;
2681 static int i386_displacement
PARAMS ((char *, char *));
2684 i386_displacement (disp_start
, disp_end
)
2688 register expressionS
*exp
;
2690 char *save_input_line_pointer
;
2691 int bigdisp
= Disp32
;
2693 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2695 i
.types
[this_operand
] |= bigdisp
;
2697 exp
= &disp_expressions
[i
.disp_operands
];
2698 i
.op
[this_operand
].disps
= exp
;
2700 save_input_line_pointer
= input_line_pointer
;
2701 input_line_pointer
= disp_start
;
2702 END_STRING_AND_SAVE (disp_end
);
2704 #ifndef GCC_ASM_O_HACK
2705 #define GCC_ASM_O_HACK 0
2708 END_STRING_AND_SAVE (disp_end
+ 1);
2709 if ((i
.types
[this_operand
] & BaseIndex
) != 0
2710 && displacement_string_end
[-1] == '+')
2712 /* This hack is to avoid a warning when using the "o"
2713 constraint within gcc asm statements.
2716 #define _set_tssldt_desc(n,addr,limit,type) \
2717 __asm__ __volatile__ ( \
2719 "movw %w1,2+%0\n\t" \
2721 "movb %b1,4+%0\n\t" \
2722 "movb %4,5+%0\n\t" \
2723 "movb $0,6+%0\n\t" \
2724 "movb %h1,7+%0\n\t" \
2726 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2728 This works great except that the output assembler ends
2729 up looking a bit weird if it turns out that there is
2730 no offset. You end up producing code that looks like:
2743 So here we provide the missing zero.
2746 *displacement_string_end
= '0';
2752 * We can have operands of the form
2753 * <symbol>@GOTOFF+<nnn>
2754 * Take the easy way out here and copy everything
2755 * into a temporary buffer...
2759 cp
= strchr (input_line_pointer
, '@');
2766 /* GOT relocations are not supported in 16 bit mode */
2767 if (flag_16bit_code
)
2768 as_bad (_("GOT relocations not supported in 16 bit mode"));
2770 if (GOT_symbol
== NULL
)
2771 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2773 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2775 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2778 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2780 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2783 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2785 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2789 as_bad (_("bad reloc specifier in expression"));
2791 /* Replace the relocation token with ' ', so that errors like
2792 foo@GOTOFF1 will be detected. */
2793 first
= cp
- input_line_pointer
;
2794 tmpbuf
= (char *) alloca (strlen(input_line_pointer
));
2795 memcpy (tmpbuf
, input_line_pointer
, first
);
2796 tmpbuf
[first
] = ' ';
2797 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2798 input_line_pointer
= tmpbuf
;
2803 exp_seg
= expression (exp
);
2805 #ifdef BFD_ASSEMBLER
2806 /* We do this to make sure that the section symbol is in
2807 the symbol table. We will ultimately change the relocation
2808 to be relative to the beginning of the section */
2809 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
)
2811 if (S_IS_LOCAL(exp
->X_add_symbol
)
2812 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
2813 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
2814 assert (exp
->X_op
== O_symbol
);
2815 exp
->X_op
= O_subtract
;
2816 exp
->X_op_symbol
= GOT_symbol
;
2817 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
2822 if (*input_line_pointer
)
2823 as_bad (_("ignoring junk `%s' after expression"),
2824 input_line_pointer
);
2826 RESTORE_END_STRING (disp_end
+ 1);
2828 RESTORE_END_STRING (disp_end
);
2829 input_line_pointer
= save_input_line_pointer
;
2831 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2833 /* missing or bad expr becomes absolute 0 */
2834 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2836 exp
->X_op
= O_constant
;
2837 exp
->X_add_number
= 0;
2838 exp
->X_add_symbol
= (symbolS
*) 0;
2839 exp
->X_op_symbol
= (symbolS
*) 0;
2842 if (exp
->X_op
== O_constant
)
2844 if (i
.types
[this_operand
] & Disp16
)
2846 /* We know this operand is at most 16 bits, so convert to a
2847 signed 16 bit number before trying to see whether it will
2848 fit in an even smaller size. */
2850 (((exp
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
2852 if (fits_in_signed_byte (exp
->X_add_number
))
2853 i
.types
[this_operand
] |= Disp8
;
2855 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2857 #ifdef BFD_ASSEMBLER
2858 OUTPUT_FLAVOR
== bfd_target_aout_flavour
&&
2860 exp_seg
!= text_section
2861 && exp_seg
!= data_section
2862 && exp_seg
!= bss_section
2863 && exp_seg
!= undefined_section
)
2865 #ifdef BFD_ASSEMBLER
2866 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2868 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2876 static int i386_operand_modifier
PARAMS ((char **, int));
2879 i386_operand_modifier (op_string
, got_a_float
)
2883 if (!strncasecmp (*op_string
, "BYTE PTR", 8))
2885 i
.suffix
= BYTE_MNEM_SUFFIX
;
2890 else if (!strncasecmp (*op_string
, "WORD PTR", 8))
2892 if (got_a_float
== 2) /* "fi..." */
2893 i
.suffix
= SHORT_MNEM_SUFFIX
;
2895 i
.suffix
= WORD_MNEM_SUFFIX
;
2900 else if (!strncasecmp (*op_string
, "DWORD PTR", 9))
2902 if (got_a_float
== 1) /* "f..." */
2903 i
.suffix
= SHORT_MNEM_SUFFIX
;
2905 i
.suffix
= LONG_MNEM_SUFFIX
;
2910 else if (!strncasecmp (*op_string
, "QWORD PTR", 9))
2912 i
.suffix
= DWORD_MNEM_SUFFIX
;
2917 else if (!strncasecmp (*op_string
, "XWORD PTR", 9))
2919 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
2924 else if (!strncasecmp (*op_string
, "SHORT", 5))
2930 else if (!strncasecmp (*op_string
, "OFFSET FLAT:", 12))
2936 else if (!strncasecmp (*op_string
, "FLAT", 4))
2942 else return NONE_FOUND
;
2945 static char * build_displacement_string
PARAMS ((int, char *));
2948 build_displacement_string (initial_disp
, op_string
)
2952 char *temp_string
= (char *) malloc (strlen (op_string
) + 1);
2953 char *end_of_operand_string
;
2957 temp_string
[0] = '\0';
2958 tc
= end_of_operand_string
= strchr (op_string
, '[');
2959 if (initial_disp
&& !end_of_operand_string
)
2961 strcpy (temp_string
, op_string
);
2965 /* Build the whole displacement string */
2968 strncpy (temp_string
, op_string
, end_of_operand_string
- op_string
);
2969 temp_string
[end_of_operand_string
- op_string
] = '\0';
2973 temp_disp
= op_string
;
2975 while (*temp_disp
!= '\0')
2978 int add_minus
= (*temp_disp
== '-');
2980 if (*temp_disp
== '+' || *temp_disp
== '-' || *temp_disp
== '[')
2983 if (is_space_char (*temp_disp
))
2986 /* Don't consider registers */
2987 if ( !((*temp_disp
== REGISTER_PREFIX
|| allow_naked_reg
)
2988 && parse_register (temp_disp
, &end_op
)) )
2990 char *string_start
= temp_disp
;
2992 while (*temp_disp
!= ']'
2993 && *temp_disp
!= '+'
2994 && *temp_disp
!= '-'
2995 && *temp_disp
!= '*')
2999 strcat (temp_string
, "-");
3001 strcat (temp_string
, "+");
3003 strncat (temp_string
, string_start
, temp_disp
- string_start
);
3004 if (*temp_disp
== '+' || *temp_disp
== '-')
3008 while (*temp_disp
!= '\0'
3009 && *temp_disp
!= '+'
3010 && *temp_disp
!= '-')
3017 static int i386_parse_seg
PARAMS ((char *));
3020 i386_parse_seg (op_string
)
3023 if (is_space_char (*op_string
))
3026 /* Should be one of es, cs, ss, ds fs or gs */
3027 switch (*op_string
++)
3030 i
.seg
[i
.mem_operands
] = &es
;
3033 i
.seg
[i
.mem_operands
] = &cs
;
3036 i
.seg
[i
.mem_operands
] = &ss
;
3039 i
.seg
[i
.mem_operands
] = &ds
;
3042 i
.seg
[i
.mem_operands
] = &fs
;
3045 i
.seg
[i
.mem_operands
] = &gs
;
3048 as_bad (_("bad segment name `%s'"), op_string
);
3052 if (*op_string
++ != 's')
3054 as_bad (_("bad segment name `%s'"), op_string
);
3058 if (is_space_char (*op_string
))
3061 if (*op_string
!= ':')
3063 as_bad (_("bad segment name `%s'"), op_string
);
3071 static int i386_index_check
PARAMS((const char *));
3073 /* Make sure the memory operand we've been dealt is valid.
3074 Returns 1 on success, 0 on a failure.
3077 i386_index_check (operand_string
)
3078 const char *operand_string
;
3080 #if INFER_ADDR_PREFIX
3085 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0)
3086 /* 16 bit mode checks */
3088 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
))
3089 != (Reg16
|BaseIndex
)))
3091 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3092 != (Reg16
|BaseIndex
))
3094 && i
.base_reg
->reg_num
< 6
3095 && i
.index_reg
->reg_num
>= 6
3096 && i
.log2_scale_factor
== 0))))
3097 /* 32 bit mode checks */
3099 && (i
.base_reg
->reg_type
& Reg32
) == 0)
3101 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
))
3102 != (Reg32
|BaseIndex
)))))
3104 #if INFER_ADDR_PREFIX
3105 if (i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3107 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3109 /* Change the size of any displacement too. At most one of
3110 Disp16 or Disp32 is set.
3111 FIXME. There doesn't seem to be any real need for separate
3112 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3113 Removing them would probably clean up the code quite a lot.
3115 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3116 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3121 as_bad (_("`%s' is not a valid base/index expression"),
3125 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3127 flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0) ? "16" : "32");
3133 static int i386_intel_memory_operand
PARAMS ((char *));
3136 i386_intel_memory_operand (operand_string
)
3137 char *operand_string
;
3139 char *op_string
= operand_string
;
3140 char *end_of_operand_string
;
3142 if ((i
.mem_operands
== 1
3143 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3144 || i
.mem_operands
== 2)
3146 as_bad (_("too many memory references for `%s'"),
3147 current_templates
->start
->name
);
3151 /* First check for a segment override. */
3152 if (*op_string
!= '[')
3156 end_seg
= strchr (op_string
, ':');
3159 if (!i386_parse_seg (op_string
))
3161 op_string
= end_seg
+ 1;
3165 /* Look for displacement preceding open bracket */
3166 if (*op_string
!= '[')
3170 if (i
.disp_operands
)
3173 temp_string
= build_displacement_string (true, op_string
);
3175 if (!i386_displacement (temp_string
, temp_string
+ strlen (temp_string
)))
3182 end_of_operand_string
= strchr (op_string
, '[');
3183 if (!end_of_operand_string
)
3184 end_of_operand_string
= op_string
+ strlen (op_string
);
3186 if (is_space_char (*end_of_operand_string
))
3187 --end_of_operand_string
;
3189 op_string
= end_of_operand_string
;
3192 if (*op_string
== '[')
3196 /* Pick off each component and figure out where it belongs */
3198 end_of_operand_string
= op_string
;
3200 while (*op_string
!= ']')
3202 const reg_entry
*temp_reg
;
3206 while (*end_of_operand_string
!= '+'
3207 && *end_of_operand_string
!= '-'
3208 && *end_of_operand_string
!= '*'
3209 && *end_of_operand_string
!= ']')
3210 end_of_operand_string
++;
3212 temp_string
= op_string
;
3213 if (*temp_string
== '+')
3216 if (is_space_char (*temp_string
))
3220 if ((*temp_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3221 && (temp_reg
= parse_register (temp_string
, &end_op
)) != NULL
)
3223 if (i
.base_reg
== NULL
)
3224 i
.base_reg
= temp_reg
;
3226 i
.index_reg
= temp_reg
;
3228 i
.types
[this_operand
] |= BaseIndex
;
3230 else if (*temp_string
== REGISTER_PREFIX
)
3232 as_bad (_("bad register name `%s'"), temp_string
);
3235 else if (is_digit_char (*op_string
)
3236 || *op_string
== '+' || *op_string
== '-')
3240 if (i
.disp_operands
!= 0)
3243 temp_string
= build_displacement_string (false, op_string
);
3245 temp_str
= temp_string
;
3246 if (*temp_str
== '+')
3249 if (!i386_displacement (temp_str
, temp_str
+ strlen (temp_str
)))
3257 end_of_operand_string
= op_string
;
3258 while (*end_of_operand_string
!= ']'
3259 && *end_of_operand_string
!= '+'
3260 && *end_of_operand_string
!= '-'
3261 && *end_of_operand_string
!= '*')
3262 ++end_of_operand_string
;
3264 else if (*op_string
== '*')
3268 if (i
.base_reg
&& !i
.index_reg
)
3270 i
.index_reg
= i
.base_reg
;
3274 if (!i386_scale (op_string
))
3277 op_string
= end_of_operand_string
;
3278 ++end_of_operand_string
;
3282 if (i386_index_check (operand_string
) == 0)
3290 i386_intel_operand (operand_string
, got_a_float
)
3291 char *operand_string
;
3294 const reg_entry
* r
;
3296 char *op_string
= operand_string
;
3298 int operand_modifier
= i386_operand_modifier (&op_string
, got_a_float
);
3299 if (is_space_char (*op_string
))
3302 switch (operand_modifier
)
3309 if (!i386_intel_memory_operand (op_string
))
3315 if (!i386_immediate (op_string
))
3321 /* Should be register or immediate */
3322 if (is_digit_char (*op_string
)
3323 && strchr (op_string
, '[') == 0)
3325 if (!i386_immediate (op_string
))
3328 else if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3329 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3331 /* Check for a segment override by searching for ':' after a
3332 segment register. */
3334 if (is_space_char (*op_string
))
3336 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3341 i
.seg
[i
.mem_operands
] = &es
;
3344 i
.seg
[i
.mem_operands
] = &cs
;
3347 i
.seg
[i
.mem_operands
] = &ss
;
3350 i
.seg
[i
.mem_operands
] = &ds
;
3353 i
.seg
[i
.mem_operands
] = &fs
;
3356 i
.seg
[i
.mem_operands
] = &gs
;
3361 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3362 i
.op
[this_operand
].regs
= r
;
3365 else if (*op_string
== REGISTER_PREFIX
)
3367 as_bad (_("bad register name `%s'"), op_string
);
3370 else if (!i386_intel_memory_operand (op_string
))
3379 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3383 i386_operand (operand_string
)
3384 char *operand_string
;
3388 char *op_string
= operand_string
;
3390 if (is_space_char (*op_string
))
3393 /* We check for an absolute prefix (differentiating,
3394 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3395 if (*op_string
== ABSOLUTE_PREFIX
)
3398 if (is_space_char (*op_string
))
3400 i
.types
[this_operand
] |= JumpAbsolute
;
3403 /* Check if operand is a register. */
3404 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3405 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3407 /* Check for a segment override by searching for ':' after a
3408 segment register. */
3410 if (is_space_char (*op_string
))
3412 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3417 i
.seg
[i
.mem_operands
] = &es
;
3420 i
.seg
[i
.mem_operands
] = &cs
;
3423 i
.seg
[i
.mem_operands
] = &ss
;
3426 i
.seg
[i
.mem_operands
] = &ds
;
3429 i
.seg
[i
.mem_operands
] = &fs
;
3432 i
.seg
[i
.mem_operands
] = &gs
;
3436 /* Skip the ':' and whitespace. */
3438 if (is_space_char (*op_string
))
3441 if (!is_digit_char (*op_string
)
3442 && !is_identifier_char (*op_string
)
3443 && *op_string
!= '('
3444 && *op_string
!= ABSOLUTE_PREFIX
)
3446 as_bad (_("bad memory operand `%s'"), op_string
);
3449 /* Handle case of %es:*foo. */
3450 if (*op_string
== ABSOLUTE_PREFIX
)
3453 if (is_space_char (*op_string
))
3455 i
.types
[this_operand
] |= JumpAbsolute
;
3457 goto do_memory_reference
;
3461 as_bad (_("junk `%s' after register"), op_string
);
3464 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3465 i
.op
[this_operand
].regs
= r
;
3468 else if (*op_string
== REGISTER_PREFIX
)
3470 as_bad (_("bad register name `%s'"), op_string
);
3473 else if (*op_string
== IMMEDIATE_PREFIX
)
3474 { /* ... or an immediate */
3476 if (i
.types
[this_operand
] & JumpAbsolute
)
3478 as_bad (_("immediate operand illegal with absolute jump"));
3481 if (!i386_immediate (op_string
))
3484 else if (is_digit_char (*op_string
)
3485 || is_identifier_char (*op_string
)
3486 || *op_string
== '(' )
3488 /* This is a memory reference of some sort. */
3491 /* Start and end of displacement string expression (if found). */
3492 char *displacement_string_start
;
3493 char *displacement_string_end
;
3495 do_memory_reference
:
3496 if ((i
.mem_operands
== 1
3497 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3498 || i
.mem_operands
== 2)
3500 as_bad (_("too many memory references for `%s'"),
3501 current_templates
->start
->name
);
3505 /* Check for base index form. We detect the base index form by
3506 looking for an ')' at the end of the operand, searching
3507 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3509 base_string
= op_string
+ strlen (op_string
);
3512 if (is_space_char (*base_string
))
3515 /* If we only have a displacement, set-up for it to be parsed later. */
3516 displacement_string_start
= op_string
;
3517 displacement_string_end
= base_string
+ 1;
3519 if (*base_string
== ')')
3522 unsigned int parens_balanced
= 1;
3523 /* We've already checked that the number of left & right ()'s are
3524 equal, so this loop will not be infinite. */
3528 if (*base_string
== ')')
3530 if (*base_string
== '(')
3533 while (parens_balanced
);
3535 temp_string
= base_string
;
3537 /* Skip past '(' and whitespace. */
3539 if (is_space_char (*base_string
))
3542 if (*base_string
== ','
3543 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3544 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3546 displacement_string_end
= temp_string
;
3548 i
.types
[this_operand
] |= BaseIndex
;
3552 base_string
= end_op
;
3553 if (is_space_char (*base_string
))
3557 /* There may be an index reg or scale factor here. */
3558 if (*base_string
== ',')
3561 if (is_space_char (*base_string
))
3564 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3565 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3567 base_string
= end_op
;
3568 if (is_space_char (*base_string
))
3570 if (*base_string
== ',')
3573 if (is_space_char (*base_string
))
3576 else if (*base_string
!= ')' )
3578 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3583 else if (*base_string
== REGISTER_PREFIX
)
3585 as_bad (_("bad register name `%s'"), base_string
);
3589 /* Check for scale factor. */
3590 if (isdigit ((unsigned char) *base_string
))
3592 if (!i386_scale (base_string
))
3596 if (is_space_char (*base_string
))
3598 if (*base_string
!= ')')
3600 as_bad (_("expecting `)' after scale factor in `%s'"),
3605 else if (!i
.index_reg
)
3607 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3612 else if (*base_string
!= ')')
3614 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3619 else if (*base_string
== REGISTER_PREFIX
)
3621 as_bad (_("bad register name `%s'"), base_string
);
3626 /* If there's an expression beginning the operand, parse it,
3627 assuming displacement_string_start and
3628 displacement_string_end are meaningful. */
3629 if (displacement_string_start
!= displacement_string_end
)
3631 if (!i386_displacement (displacement_string_start
,
3632 displacement_string_end
))
3636 /* Special case for (%dx) while doing input/output op. */
3638 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3640 && i
.log2_scale_factor
== 0
3641 && i
.seg
[i
.mem_operands
] == 0
3642 && (i
.types
[this_operand
] & Disp
) == 0)
3644 i
.types
[this_operand
] = InOutPortReg
;
3648 if (i386_index_check (operand_string
) == 0)
3653 { /* it's not a memory operand; argh! */
3654 as_bad (_("invalid char %s beginning operand %d `%s'"),
3655 output_invalid (*op_string
),
3660 return 1; /* normal return */
3664 * md_estimate_size_before_relax()
3666 * Called just before relax().
3667 * Any symbol that is now undefined will not become defined.
3668 * Return the correct fr_subtype in the frag.
3669 * Return the initial "guess for fr_var" to caller.
3670 * The guess for fr_var is ACTUALLY the growth beyond fr_fix.
3671 * Whatever we do to grow fr_fix or fr_var contributes to our returned value.
3672 * Although it may not be explicit in the frag, pretend fr_var starts with a
3676 md_estimate_size_before_relax (fragP
, segment
)
3677 register fragS
*fragP
;
3678 register segT segment
;
3680 register unsigned char *opcode
;
3681 register int old_fr_fix
;
3683 old_fr_fix
= fragP
->fr_fix
;
3684 opcode
= (unsigned char *) fragP
->fr_opcode
;
3685 /* We've already got fragP->fr_subtype right; all we have to do is
3686 check for un-relaxable symbols. */
3687 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
3689 /* symbol is undefined in this segment */
3690 int code16
= fragP
->fr_subtype
& CODE16
;
3691 int size
= code16
? 2 : 4;
3692 #ifdef BFD_ASSEMBLER
3693 enum bfd_reloc_code_real reloc_type
;
3698 if (GOT_symbol
/* Not quite right - we should switch on presence of
3699 @PLT, but I cannot see how to get to that from
3700 here. We should have done this in md_assemble to
3701 really get it right all of the time, but I think it
3702 does not matter that much, as this will be right
3703 most of the time. ERY */
3704 && S_GET_SEGMENT(fragP
->fr_symbol
) == undefined_section
)
3705 reloc_type
= BFD_RELOC_386_PLT32
;
3707 reloc_type
= BFD_RELOC_16_PCREL
;
3709 reloc_type
= BFD_RELOC_32_PCREL
;
3713 case JUMP_PC_RELATIVE
: /* make jmp (0xeb) a dword displacement jump */
3714 opcode
[0] = 0xe9; /* dword disp jmp */
3715 fragP
->fr_fix
+= size
;
3716 fix_new (fragP
, old_fr_fix
, size
,
3718 fragP
->fr_offset
, 1,
3723 /* This changes the byte-displacement jump 0x7N
3724 to the dword-displacement jump 0x0f,0x8N. */
3725 opcode
[1] = opcode
[0] + 0x10;
3726 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3727 fragP
->fr_fix
+= 1 + size
; /* we've added an opcode byte */
3728 fix_new (fragP
, old_fr_fix
+ 1, size
,
3730 fragP
->fr_offset
, 1,
3736 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
3737 } /* md_estimate_size_before_relax() */
3740 * md_convert_frag();
3742 * Called after relax() is finished.
3743 * In: Address of frag.
3744 * fr_type == rs_machine_dependent.
3745 * fr_subtype is what the address relaxed to.
3747 * Out: Any fixSs and constants are set up.
3748 * Caller will turn frag into a ".space 0".
3750 #ifndef BFD_ASSEMBLER
3752 md_convert_frag (headers
, sec
, fragP
)
3753 object_headers
*headers ATTRIBUTE_UNUSED
;
3754 segT sec ATTRIBUTE_UNUSED
;
3755 register fragS
*fragP
;
3758 md_convert_frag (abfd
, sec
, fragP
)
3759 bfd
*abfd ATTRIBUTE_UNUSED
;
3760 segT sec ATTRIBUTE_UNUSED
;
3761 register fragS
*fragP
;
3764 register unsigned char *opcode
;
3765 unsigned char *where_to_put_displacement
= NULL
;
3766 offsetT target_address
;
3767 offsetT opcode_address
;
3768 unsigned int extension
= 0;
3769 offsetT displacement_from_opcode_start
;
3771 opcode
= (unsigned char *) fragP
->fr_opcode
;
3773 /* Address we want to reach in file space. */
3774 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3775 #ifdef BFD_ASSEMBLER /* not needed otherwise? */
3776 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3779 /* Address opcode resides at in file space. */
3780 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3782 /* Displacement from opcode start to fill into instruction. */
3783 displacement_from_opcode_start
= target_address
- opcode_address
;
3785 switch (fragP
->fr_subtype
)
3787 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3788 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3789 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3790 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3791 /* don't have to change opcode */
3792 extension
= 1; /* 1 opcode + 1 displacement */
3793 where_to_put_displacement
= &opcode
[1];
3796 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3797 extension
= 5; /* 2 opcode + 4 displacement */
3798 opcode
[1] = opcode
[0] + 0x10;
3799 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3800 where_to_put_displacement
= &opcode
[2];
3803 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3804 extension
= 4; /* 1 opcode + 4 displacement */
3806 where_to_put_displacement
= &opcode
[1];
3809 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3810 extension
= 3; /* 2 opcode + 2 displacement */
3811 opcode
[1] = opcode
[0] + 0x10;
3812 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3813 where_to_put_displacement
= &opcode
[2];
3816 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3817 extension
= 2; /* 1 opcode + 2 displacement */
3819 where_to_put_displacement
= &opcode
[1];
3823 BAD_CASE (fragP
->fr_subtype
);
3826 /* now put displacement after opcode */
3827 md_number_to_chars ((char *) where_to_put_displacement
,
3828 (valueT
) (displacement_from_opcode_start
- extension
),
3829 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
3830 fragP
->fr_fix
+= extension
;
3834 int md_short_jump_size
= 2; /* size of byte displacement jmp */
3835 int md_long_jump_size
= 5; /* size of dword displacement jmp */
3836 const int md_reloc_size
= 8; /* Size of relocation record */
3839 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3841 addressT from_addr
, to_addr
;
3842 fragS
*frag ATTRIBUTE_UNUSED
;
3843 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3847 offset
= to_addr
- (from_addr
+ 2);
3848 md_number_to_chars (ptr
, (valueT
) 0xeb, 1); /* opcode for byte-disp jump */
3849 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
3853 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3855 addressT from_addr
, to_addr
;
3861 if (flag_do_long_jump
)
3863 offset
= to_addr
- S_GET_VALUE (to_symbol
);
3864 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);/* opcode for long jmp */
3865 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3866 fix_new (frag
, (ptr
+ 1) - frag
->fr_literal
, 4,
3867 to_symbol
, (offsetT
) 0, 0, BFD_RELOC_32
);
3871 offset
= to_addr
- (from_addr
+ 5);
3872 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
3873 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3877 /* Apply a fixup (fixS) to segment data, once it has been determined
3878 by our caller that we have all the info we need to fix it up.
3880 On the 386, immediates, displacements, and data pointers are all in
3881 the same (little-endian) format, so we don't need to care about which
3885 md_apply_fix3 (fixP
, valp
, seg
)
3886 fixS
*fixP
; /* The fix we're to put in. */
3887 valueT
*valp
; /* Pointer to the value of the bits. */
3888 segT seg ATTRIBUTE_UNUSED
; /* Segment fix is from. */
3890 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3891 valueT value
= *valp
;
3893 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
3896 switch (fixP
->fx_r_type
)
3902 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
3905 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
3908 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
3913 /* This is a hack. There should be a better way to handle this.
3914 This covers for the fact that bfd_install_relocation will
3915 subtract the current location (for partial_inplace, PC relative
3916 relocations); see more below. */
3917 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
3918 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
3919 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
3923 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3925 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
3928 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3930 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3931 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
3933 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
3936 || (symbol_section_p (fixP
->fx_addsy
)
3937 && fseg
!= absolute_section
))
3938 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
3939 && ! S_IS_WEAK (fixP
->fx_addsy
)
3940 && S_IS_DEFINED (fixP
->fx_addsy
)
3941 && ! S_IS_COMMON (fixP
->fx_addsy
))
3943 /* Yes, we add the values in twice. This is because
3944 bfd_perform_relocation subtracts them out again. I think
3945 bfd_perform_relocation is broken, but I don't dare change
3947 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3951 #if defined (OBJ_COFF) && defined (TE_PE)
3952 /* For some reason, the PE format does not store a section
3953 address offset for a PC relative symbol. */
3954 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
3955 value
+= md_pcrel_from (fixP
);
3956 else if (S_IS_EXTERNAL (fixP
->fx_addsy
)
3957 || S_IS_WEAK (fixP
->fx_addsy
))
3959 /* We are generating an external relocation for this defined
3960 symbol. We add the address, because
3961 bfd_install_relocation will subtract it. VALUE already
3962 holds the symbol value, because fixup_segment added it
3963 in. We subtract it out, and then we subtract it out
3964 again because bfd_install_relocation will add it in
3966 value
+= md_pcrel_from (fixP
);
3967 value
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3972 else if (fixP
->fx_addsy
!= NULL
3973 && S_IS_DEFINED (fixP
->fx_addsy
)
3974 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3975 || S_IS_WEAK (fixP
->fx_addsy
)))
3977 /* We are generating an external relocation for this defined
3978 symbol. VALUE already holds the symbol value, and
3979 bfd_install_relocation will add it in again. We don't want
3981 value
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3985 /* Fix a few things - the dynamic linker expects certain values here,
3986 and we must not dissappoint it. */
3987 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3988 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3990 switch (fixP
->fx_r_type
) {
3991 case BFD_RELOC_386_PLT32
:
3992 /* Make the jump instruction point to the address of the operand. At
3993 runtime we merely add the offset to the actual PLT entry. */
3996 case BFD_RELOC_386_GOTPC
:
3998 * This is tough to explain. We end up with this one if we have
3999 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4000 * here is to obtain the absolute address of the GOT, and it is strongly
4001 * preferable from a performance point of view to avoid using a runtime
4002 * relocation for this. The actual sequence of instructions often look
4008 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4010 * The call and pop essentially return the absolute address of
4011 * the label .L66 and store it in %ebx. The linker itself will
4012 * ultimately change the first operand of the addl so that %ebx points to
4013 * the GOT, but to keep things simple, the .o file must have this operand
4014 * set so that it generates not the absolute address of .L66, but the
4015 * absolute address of itself. This allows the linker itself simply
4016 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4017 * added in, and the addend of the relocation is stored in the operand
4018 * field for the instruction itself.
4020 * Our job here is to fix the operand so that it would add the correct
4021 * offset so that %ebx would point to itself. The thing that is tricky is
4022 * that .-.L66 will point to the beginning of the instruction, so we need
4023 * to further modify the operand so that it will point to itself.
4024 * There are other cases where you have something like:
4026 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4028 * and here no correction would be required. Internally in the assembler
4029 * we treat operands of this form as not being pcrel since the '.' is
4030 * explicitly mentioned, and I wonder whether it would simplify matters
4031 * to do it this way. Who knows. In earlier versions of the PIC patches,
4032 * the pcrel_adjust field was used to store the correction, but since the
4033 * expression is not pcrel, I felt it would be confusing to do it this way.
4037 case BFD_RELOC_386_GOT32
:
4038 value
= 0; /* Fully resolved at runtime. No addend. */
4040 case BFD_RELOC_386_GOTOFF
:
4043 case BFD_RELOC_VTABLE_INHERIT
:
4044 case BFD_RELOC_VTABLE_ENTRY
:
4051 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4053 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4054 md_number_to_chars (p
, value
, fixP
->fx_size
);
4060 #define MAX_LITTLENUMS 6
4062 /* Turn the string pointed to by litP into a floating point constant of type
4063 type, and emit the appropriate bytes. The number of LITTLENUMS emitted
4064 is stored in *sizeP . An error message is returned, or NULL on OK. */
4066 md_atof (type
, litP
, sizeP
)
4072 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4073 LITTLENUM_TYPE
*wordP
;
4095 return _("Bad call to md_atof ()");
4097 t
= atof_ieee (input_line_pointer
, type
, words
);
4099 input_line_pointer
= t
;
4101 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4102 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4103 the bigendian 386. */
4104 for (wordP
= words
+ prec
- 1; prec
--;)
4106 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4107 litP
+= sizeof (LITTLENUM_TYPE
);
4112 char output_invalid_buf
[8];
4119 sprintf (output_invalid_buf
, "'%c'", c
);
4121 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4122 return output_invalid_buf
;
4126 /* REG_STRING starts *before* REGISTER_PREFIX. */
4128 static const reg_entry
*
4129 parse_register (reg_string
, end_op
)
4133 char *s
= reg_string
;
4135 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4138 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4139 if (*s
== REGISTER_PREFIX
)
4142 if (is_space_char (*s
))
4146 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4148 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4149 return (const reg_entry
*) NULL
;
4155 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4157 /* Handle floating point regs, allowing spaces in the (i) part. */
4158 if (r
== i386_regtab
/* %st is first entry of table */)
4160 if (is_space_char (*s
))
4165 if (is_space_char (*s
))
4167 if (*s
>= '0' && *s
<= '7')
4169 r
= &i386_float_regtab
[*s
- '0'];
4171 if (is_space_char (*s
))
4179 /* We have "%st(" then garbage */
4180 return (const reg_entry
*) NULL
;
4187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4188 CONST
char *md_shortopts
= "kmVQ:sq";
4190 CONST
char *md_shortopts
= "m";
4192 struct option md_longopts
[] = {
4193 {NULL
, no_argument
, NULL
, 0}
4195 size_t md_longopts_size
= sizeof (md_longopts
);
4198 md_parse_option (c
, arg
)
4200 char *arg ATTRIBUTE_UNUSED
;
4205 flag_do_long_jump
= 1;
4208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4209 /* -k: Ignore for FreeBSD compatibility. */
4213 /* -V: SVR4 argument to print version ID. */
4215 print_version_id ();
4218 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4219 should be emitted or not. FIXME: Not implemented. */
4224 /* -s: On i386 Solaris, this tells the native assembler to use
4225 .stab instead of .stab.excl. We always use .stab anyhow. */
4229 /* -q: On i386 Solaris, this tells the native assembler does
4241 md_show_usage (stream
)
4244 fprintf (stream
, _("\
4245 -m do long jump\n"));
4246 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4247 fprintf (stream
, _("\
4248 -V print assembler version number\n\
4256 #ifdef BFD_ASSEMBLER
4257 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
4258 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
4259 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
4261 /* Pick the target format to use. */
4264 i386_target_format ()
4266 switch (OUTPUT_FLAVOR
)
4268 #ifdef OBJ_MAYBE_AOUT
4269 case bfd_target_aout_flavour
:
4270 return AOUT_TARGET_FORMAT
;
4272 #ifdef OBJ_MAYBE_COFF
4273 case bfd_target_coff_flavour
:
4276 #ifdef OBJ_MAYBE_ELF
4277 case bfd_target_elf_flavour
:
4278 return "elf32-i386";
4286 #endif /* OBJ_MAYBE_ more than one */
4287 #endif /* BFD_ASSEMBLER */
4290 md_undefined_symbol (name
)
4293 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4294 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4295 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4296 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4300 if (symbol_find (name
))
4301 as_bad (_("GOT already in symbol table"));
4302 GOT_symbol
= symbol_new (name
, undefined_section
,
4303 (valueT
) 0, &zero_address_frag
);
4310 /* Round up a section size to the appropriate boundary. */
4312 md_section_align (segment
, size
)
4313 segT segment ATTRIBUTE_UNUSED
;
4316 #ifdef BFD_ASSEMBLER
4317 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4318 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4320 /* For a.out, force the section size to be aligned. If we don't do
4321 this, BFD will align it for us, but it will not write out the
4322 final bytes of the section. This may be a bug in BFD, but it is
4323 easier to fix it here since that is how the other a.out targets
4327 align
= bfd_get_section_alignment (stdoutput
, segment
);
4328 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4336 /* On the i386, PC-relative offsets are relative to the start of the
4337 next instruction. That is, the address of the offset, plus its
4338 size, since the offset is always the last part of the insn. */
4341 md_pcrel_from (fixP
)
4344 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4351 int ignore ATTRIBUTE_UNUSED
;
4355 temp
= get_absolute_expression ();
4356 subseg_set (bss_section
, (subsegT
) temp
);
4357 demand_empty_rest_of_line ();
4363 #ifdef BFD_ASSEMBLER
4366 i386_validate_fix (fixp
)
4369 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4371 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4377 tc_gen_reloc (section
, fixp
)
4378 asection
*section ATTRIBUTE_UNUSED
;
4382 bfd_reloc_code_real_type code
;
4384 switch (fixp
->fx_r_type
)
4386 case BFD_RELOC_386_PLT32
:
4387 case BFD_RELOC_386_GOT32
:
4388 case BFD_RELOC_386_GOTOFF
:
4389 case BFD_RELOC_386_GOTPC
:
4391 case BFD_RELOC_VTABLE_ENTRY
:
4392 case BFD_RELOC_VTABLE_INHERIT
:
4393 code
= fixp
->fx_r_type
;
4398 switch (fixp
->fx_size
)
4401 as_bad (_("can not do %d byte pc-relative relocation"),
4403 code
= BFD_RELOC_32_PCREL
;
4405 case 1: code
= BFD_RELOC_8_PCREL
; break;
4406 case 2: code
= BFD_RELOC_16_PCREL
; break;
4407 case 4: code
= BFD_RELOC_32_PCREL
; break;
4412 switch (fixp
->fx_size
)
4415 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4416 code
= BFD_RELOC_32
;
4418 case 1: code
= BFD_RELOC_8
; break;
4419 case 2: code
= BFD_RELOC_16
; break;
4420 case 4: code
= BFD_RELOC_32
; break;
4426 if (code
== BFD_RELOC_32
4428 && fixp
->fx_addsy
== GOT_symbol
)
4429 code
= BFD_RELOC_386_GOTPC
;
4431 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4432 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4433 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4435 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4436 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4437 vtable entry to be used in the relocation's section offset. */
4438 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4439 rel
->address
= fixp
->fx_offset
;
4442 rel
->addend
= fixp
->fx_addnumber
;
4446 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4447 if (rel
->howto
== NULL
)
4449 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4450 _("cannot represent relocation type %s"),
4451 bfd_get_reloc_code_name (code
));
4452 /* Set howto to a garbage value so that we can keep going. */
4453 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4454 assert (rel
->howto
!= NULL
);
4460 #else /* ! BFD_ASSEMBLER */
4462 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4464 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4467 relax_addressT segment_address_in_file
;
4470 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4471 * Out: GNU LD relocation length code: 0, 1, or 2.
4474 static const unsigned char nbytes_r_length
[] = {42, 0, 1, 42, 2};
4477 know (fixP
->fx_addsy
!= NULL
);
4479 md_number_to_chars (where
,
4480 (valueT
) (fixP
->fx_frag
->fr_address
4481 + fixP
->fx_where
- segment_address_in_file
),
4484 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4485 ? S_GET_TYPE (fixP
->fx_addsy
)
4486 : fixP
->fx_addsy
->sy_number
);
4488 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4489 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4490 where
[4] = r_symbolnum
& 0x0ff;
4491 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4492 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4493 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4496 #endif /* OBJ_AOUT or OBJ_BOUT */
4498 #if defined (I386COFF)
4501 tc_coff_fix2rtype (fixP
)
4504 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4507 return (fixP
->fx_pcrel
?
4508 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4509 fixP
->fx_size
== 2 ? R_PCRWORD
:
4511 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4512 fixP
->fx_size
== 2 ? R_RELWORD
:
4517 tc_coff_sizemachdep (frag
)
4521 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4526 #endif /* I386COFF */
4528 #endif /* ! BFD_ASSEMBLER */
4530 /* end of tc-i386.c */