opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int);
  59 static void OP_E_extended (int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_EX_Vex (int, int);
  97 static void OP_EX_VexW (int, int);
  98 static void OP_XMM_Vex (int, int);
  99 static void OP_XMM_VexW (int, int);
 100 static void OP_REG_VexI4 (int, int);
 101 static void PCLMUL_Fixup (int, int);
 102 static void VEXI4_Fixup (int, int);
 103 static void VZERO_Fixup (int, int);
 104 static void VCMP_Fixup (int, int);
 105 static void OP_0f07 (int, int);
 106 static void OP_Monitor (int, int);
 107 static void OP_Mwait (int, int);
 108 static void NOP_Fixup1 (int, int);
 109 static void NOP_Fixup2 (int, int);
 110 static void OP_3DNowSuffix (int, int);
 111 static void CMP_Fixup (int, int);
 112 static void BadOp (void);
 113 static void REP_Fixup (int, int);
 114 static void CMPXCHG8B_Fixup (int, int);
 115 static void XMM_Fixup (int, int);
 116 static void CRC32_Fixup (int, int);
 117 static void OP_LWPCB_E (int, int);
 118 static void OP_LWP_E (int, int);
 119 static void OP_LWP_I (int, int);
 120
 121 static void MOVBE_Fixup (int, int);
 122
 123 struct dis_private {
 124   /* Points to first byte not fetched.  */
 125   bfd_byte *max_fetched;
 126   bfd_byte the_buffer[MAX_MNEM_SIZE];
 127   bfd_vma insn_start;
 128   int orig_sizeflag;
 129   jmp_buf bailout;
 130 };
 131
 132 enum address_mode
 133 {
 134   mode_16bit,
 135   mode_32bit,
 136   mode_64bit
 137 };
 138
 139 enum address_mode address_mode;
 140
 141 /* Flags for the prefixes for the current instruction.  See below.  */
 142 static int prefixes;
 143
 144 /* REX prefix the current instruction.  See below.  */
 145 static int rex;
 146 /* Bits of REX we've already used.  */
 147 static int rex_used;
 148 /* Original REX prefix.  */
 149 static int rex_original;
 150 /* REX bits in original REX prefix ignored.  It may not be the same
 151    as rex_original since some bits may not be ignored.  */
 152 static int rex_ignored;
 153 /* Mark parts used in the REX prefix.  When we are testing for
 154    empty prefix (for 8bit register REX extension), just mask it
 155    out.  Otherwise test for REX bit is excuse for existence of REX
 156    only in case value is nonzero.  */
 157 #define USED_REX(value)                                 \
 158   {                                                     \
 159     if (value)                                          \
 160       {                                                 \
 161         if ((rex & value))                              \
 162           rex_used |= (value) | REX_OPCODE;             \
 163       }                                                 \
 164     else                                                \
 165       rex_used |= REX_OPCODE;                           \
 166   }
 167
 168 /* Flags for prefixes which we somehow handled when printing the
 169    current instruction.  */
 170 static int used_prefixes;
 171
 172 /* Flags stored in PREFIXES.  */
 173 #define PREFIX_REPZ 1
 174 #define PREFIX_REPNZ 2
 175 #define PREFIX_LOCK 4
 176 #define PREFIX_CS 8
 177 #define PREFIX_SS 0x10
 178 #define PREFIX_DS 0x20
 179 #define PREFIX_ES 0x40
 180 #define PREFIX_FS 0x80
 181 #define PREFIX_GS 0x100
 182 #define PREFIX_DATA 0x200
 183 #define PREFIX_ADDR 0x400
 184 #define PREFIX_FWAIT 0x800
 185
 186 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 187    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 188    on error.  */
 189 #define FETCH_DATA(info, addr) \
 190   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 191    ? 1 : fetch_data ((info), (addr)))
 192
 193 static int
 194 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 195 {
 196   int status;
 197   struct dis_private *priv = (struct dis_private *) info->private_data;
 198   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 199
 200   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 201     status = (*info->read_memory_func) (start,
 202                                         priv->max_fetched,
 203                                         addr - priv->max_fetched,
 204                                         info);
 205   else
 206     status = -1;
 207   if (status != 0)
 208     {
 209       /* If we did manage to read at least one byte, then
 210          print_insn_i386 will do something sensible.  Otherwise, print
 211          an error.  We do that here because this is where we know
 212          STATUS.  */
 213       if (priv->max_fetched == priv->the_buffer)
 214         (*info->memory_error_func) (status, start, info);
 215       longjmp (priv->bailout, 1);
 216     }
 217   else
 218     priv->max_fetched = addr;
 219   return 1;
 220 }
 221
 222 #define XX { NULL, 0 }
 223
 224 #define Eb { OP_E, b_mode }
 225 #define EbS { OP_E, b_swap_mode }
 226 #define Ev { OP_E, v_mode }
 227 #define EvS { OP_E, v_swap_mode }
 228 #define Ed { OP_E, d_mode }
 229 #define Edq { OP_E, dq_mode }
 230 #define Edqw { OP_E, dqw_mode }
 231 #define Edqb { OP_E, dqb_mode }
 232 #define Edqd { OP_E, dqd_mode }
 233 #define Eq { OP_E, q_mode }
 234 #define indirEv { OP_indirE, stack_v_mode }
 235 #define indirEp { OP_indirE, f_mode }
 236 #define stackEv { OP_E, stack_v_mode }
 237 #define Em { OP_E, m_mode }
 238 #define Ew { OP_E, w_mode }
 239 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 240 #define Ma { OP_M, a_mode }
 241 #define Mb { OP_M, b_mode }
 242 #define Md { OP_M, d_mode }
 243 #define Mo { OP_M, o_mode }
 244 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 245 #define Mq { OP_M, q_mode }
 246 #define Mx { OP_M, x_mode }
 247 #define Mxmm { OP_M, xmm_mode }
 248 #define Gb { OP_G, b_mode }
 249 #define Gv { OP_G, v_mode }
 250 #define Gd { OP_G, d_mode }
 251 #define Gdq { OP_G, dq_mode }
 252 #define Gm { OP_G, m_mode }
 253 #define Gw { OP_G, w_mode }
 254 #define Rd { OP_R, d_mode }
 255 #define Rm { OP_R, m_mode }
 256 #define Ib { OP_I, b_mode }
 257 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 258 #define Iv { OP_I, v_mode }
 259 #define Iq { OP_I, q_mode }
 260 #define Iv64 { OP_I64, v_mode }
 261 #define Iw { OP_I, w_mode }
 262 #define I1 { OP_I, const_1_mode }
 263 #define Jb { OP_J, b_mode }
 264 #define Jv { OP_J, v_mode }
 265 #define Cm { OP_C, m_mode }
 266 #define Dm { OP_D, m_mode }
 267 #define Td { OP_T, d_mode }
 268 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 269
 270 #define RMeAX { OP_REG, eAX_reg }
 271 #define RMeBX { OP_REG, eBX_reg }
 272 #define RMeCX { OP_REG, eCX_reg }
 273 #define RMeDX { OP_REG, eDX_reg }
 274 #define RMeSP { OP_REG, eSP_reg }
 275 #define RMeBP { OP_REG, eBP_reg }
 276 #define RMeSI { OP_REG, eSI_reg }
 277 #define RMeDI { OP_REG, eDI_reg }
 278 #define RMrAX { OP_REG, rAX_reg }
 279 #define RMrBX { OP_REG, rBX_reg }
 280 #define RMrCX { OP_REG, rCX_reg }
 281 #define RMrDX { OP_REG, rDX_reg }
 282 #define RMrSP { OP_REG, rSP_reg }
 283 #define RMrBP { OP_REG, rBP_reg }
 284 #define RMrSI { OP_REG, rSI_reg }
 285 #define RMrDI { OP_REG, rDI_reg }
 286 #define RMAL { OP_REG, al_reg }
 287 #define RMAL { OP_REG, al_reg }
 288 #define RMCL { OP_REG, cl_reg }
 289 #define RMDL { OP_REG, dl_reg }
 290 #define RMBL { OP_REG, bl_reg }
 291 #define RMAH { OP_REG, ah_reg }
 292 #define RMCH { OP_REG, ch_reg }
 293 #define RMDH { OP_REG, dh_reg }
 294 #define RMBH { OP_REG, bh_reg }
 295 #define RMAX { OP_REG, ax_reg }
 296 #define RMDX { OP_REG, dx_reg }
 297
 298 #define eAX { OP_IMREG, eAX_reg }
 299 #define eBX { OP_IMREG, eBX_reg }
 300 #define eCX { OP_IMREG, eCX_reg }
 301 #define eDX { OP_IMREG, eDX_reg }
 302 #define eSP { OP_IMREG, eSP_reg }
 303 #define eBP { OP_IMREG, eBP_reg }
 304 #define eSI { OP_IMREG, eSI_reg }
 305 #define eDI { OP_IMREG, eDI_reg }
 306 #define AL { OP_IMREG, al_reg }
 307 #define CL { OP_IMREG, cl_reg }
 308 #define DL { OP_IMREG, dl_reg }
 309 #define BL { OP_IMREG, bl_reg }
 310 #define AH { OP_IMREG, ah_reg }
 311 #define CH { OP_IMREG, ch_reg }
 312 #define DH { OP_IMREG, dh_reg }
 313 #define BH { OP_IMREG, bh_reg }
 314 #define AX { OP_IMREG, ax_reg }
 315 #define DX { OP_IMREG, dx_reg }
 316 #define zAX { OP_IMREG, z_mode_ax_reg }
 317 #define indirDX { OP_IMREG, indir_dx_reg }
 318
 319 #define Sw { OP_SEG, w_mode }
 320 #define Sv { OP_SEG, v_mode }
 321 #define Ap { OP_DIR, 0 }
 322 #define Ob { OP_OFF64, b_mode }
 323 #define Ov { OP_OFF64, v_mode }
 324 #define Xb { OP_DSreg, eSI_reg }
 325 #define Xv { OP_DSreg, eSI_reg }
 326 #define Xz { OP_DSreg, eSI_reg }
 327 #define Yb { OP_ESreg, eDI_reg }
 328 #define Yv { OP_ESreg, eDI_reg }
 329 #define DSBX { OP_DSreg, eBX_reg }
 330
 331 #define es { OP_REG, es_reg }
 332 #define ss { OP_REG, ss_reg }
 333 #define cs { OP_REG, cs_reg }
 334 #define ds { OP_REG, ds_reg }
 335 #define fs { OP_REG, fs_reg }
 336 #define gs { OP_REG, gs_reg }
 337
 338 #define MX { OP_MMX, 0 }
 339 #define XM { OP_XMM, 0 }
 340 #define XMM { OP_XMM, xmm_mode }
 341 #define EM { OP_EM, v_mode }
 342 #define EMS { OP_EM, v_swap_mode }
 343 #define EMd { OP_EM, d_mode }
 344 #define EMx { OP_EM, x_mode }
 345 #define EXw { OP_EX, w_mode }
 346 #define EXd { OP_EX, d_mode }
 347 #define EXdS { OP_EX, d_swap_mode }
 348 #define EXq { OP_EX, q_mode }
 349 #define EXqS { OP_EX, q_swap_mode }
 350 #define EXx { OP_EX, x_mode }
 351 #define EXxS { OP_EX, x_swap_mode }
 352 #define EXxmm { OP_EX, xmm_mode }
 353 #define EXxmmq { OP_EX, xmmq_mode }
 354 #define EXymmq { OP_EX, ymmq_mode }
 355 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 356 #define MS { OP_MS, v_mode }
 357 #define XS { OP_XS, v_mode }
 358 #define EMCq { OP_EMC, q_mode }
 359 #define MXC { OP_MXC, 0 }
 360 #define OPSUF { OP_3DNowSuffix, 0 }
 361 #define CMP { CMP_Fixup, 0 }
 362 #define XMM0 { XMM_Fixup, 0 }
 363
 364 #define Vex { OP_VEX, vex_mode }
 365 #define Vex128 { OP_VEX, vex128_mode }
 366 #define Vex256 { OP_VEX, vex256_mode }
 367 #define VexI4 { VEXI4_Fixup, 0}
 368 #define EXdVex { OP_EX_Vex, d_mode }
 369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 370 #define EXqVex { OP_EX_Vex, q_mode }
 371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 372 #define EXVexW { OP_EX_VexW, x_mode }
 373 #define EXdVexW { OP_EX_VexW, d_mode }
 374 #define EXqVexW { OP_EX_VexW, q_mode }
 375 #define XMVex { OP_XMM_Vex, 0 }
 376 #define XMVexW { OP_XMM_VexW, 0 }
 377 #define XMVexI4 { OP_REG_VexI4, x_mode }
 378 #define PCLMUL { PCLMUL_Fixup, 0 }
 379 #define VZERO { VZERO_Fixup, 0 }
 380 #define VCMP { VCMP_Fixup, 0 }
 381
 382 /* Used handle "rep" prefix for string instructions.  */
 383 #define Xbr { REP_Fixup, eSI_reg }
 384 #define Xvr { REP_Fixup, eSI_reg }
 385 #define Ybr { REP_Fixup, eDI_reg }
 386 #define Yvr { REP_Fixup, eDI_reg }
 387 #define Yzr { REP_Fixup, eDI_reg }
 388 #define indirDXr { REP_Fixup, indir_dx_reg }
 389 #define ALr { REP_Fixup, al_reg }
 390 #define eAXr { REP_Fixup, eAX_reg }
 391
 392 #define cond_jump_flag { NULL, cond_jump_mode }
 393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 394
 395 /* bits in sizeflag */
 396 #define SUFFIX_ALWAYS 4
 397 #define AFLAG 2
 398 #define DFLAG 1
 399
 400 enum
 401 {
 402   /* byte operand */
 403   b_mode = 1,
 404   /* byte operand with operand swapped */
 405   b_swap_mode,
 406   /* operand size depends on prefixes */
 407   v_mode,
 408   /* operand size depends on prefixes with operand swapped */
 409   v_swap_mode,
 410   /* word operand */
 411   w_mode,
 412   /* double word operand  */
 413   d_mode,
 414   /* double word operand with operand swapped */
 415   d_swap_mode,
 416   /* quad word operand */
 417   q_mode,
 418   /* quad word operand with operand swapped */
 419   q_swap_mode,
 420   /* ten-byte operand */
 421   t_mode,
 422   /* 16-byte XMM or 32-byte YMM operand */
 423   x_mode,
 424   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 425   x_swap_mode,
 426   /* 16-byte XMM operand */
 427   xmm_mode,
 428   /* 16-byte XMM or quad word operand */
 429   xmmq_mode,
 430   /* 32-byte YMM or quad word operand */
 431   ymmq_mode,
 432   /* d_mode in 32bit, q_mode in 64bit mode.  */
 433   m_mode,
 434   /* pair of v_mode operands */
 435   a_mode,
 436   cond_jump_mode,
 437   loop_jcxz_mode,
 438   /* operand size depends on REX prefixes.  */
 439   dq_mode,
 440   /* registers like dq_mode, memory like w_mode.  */
 441   dqw_mode,
 442   /* 4- or 6-byte pointer operand */
 443   f_mode,
 444   const_1_mode,
 445   /* v_mode for stack-related opcodes.  */
 446   stack_v_mode,
 447   /* non-quad operand size depends on prefixes */
 448   z_mode,
 449   /* 16-byte operand */
 450   o_mode,
 451   /* registers like dq_mode, memory like b_mode.  */
 452   dqb_mode,
 453   /* registers like dq_mode, memory like d_mode.  */
 454   dqd_mode,
 455   /* normal vex mode */
 456   vex_mode,
 457   /* 128bit vex mode */
 458   vex128_mode,
 459   /* 256bit vex mode */
 460   vex256_mode,
 461   /* operand size depends on the VEX.W bit.  */
 462   vex_w_dq_mode,
 463
 464   es_reg,
 465   cs_reg,
 466   ss_reg,
 467   ds_reg,
 468   fs_reg,
 469   gs_reg,
 470
 471   eAX_reg,
 472   eCX_reg,
 473   eDX_reg,
 474   eBX_reg,
 475   eSP_reg,
 476   eBP_reg,
 477   eSI_reg,
 478   eDI_reg,
 479
 480   al_reg,
 481   cl_reg,
 482   dl_reg,
 483   bl_reg,
 484   ah_reg,
 485   ch_reg,
 486   dh_reg,
 487   bh_reg,
 488
 489   ax_reg,
 490   cx_reg,
 491   dx_reg,
 492   bx_reg,
 493   sp_reg,
 494   bp_reg,
 495   si_reg,
 496   di_reg,
 497
 498   rAX_reg,
 499   rCX_reg,
 500   rDX_reg,
 501   rBX_reg,
 502   rSP_reg,
 503   rBP_reg,
 504   rSI_reg,
 505   rDI_reg,
 506
 507   z_mode_ax_reg,
 508   indir_dx_reg
 509 };
 510
 511 enum
 512 {
 513   FLOATCODE = 1,
 514   USE_REG_TABLE,
 515   USE_MOD_TABLE,
 516   USE_RM_TABLE,
 517   USE_PREFIX_TABLE,
 518   USE_X86_64_TABLE,
 519   USE_3BYTE_TABLE,
 520   USE_XOP_8F_TABLE,
 521   USE_VEX_C4_TABLE,
 522   USE_VEX_C5_TABLE,
 523   USE_VEX_LEN_TABLE
 524 };
 525
 526 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 527
 528 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 529 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 530 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 531 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 532 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 533 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 534 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 535 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 536 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 537 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 538 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 539
 540 enum
 541 {
 542   REG_80 = 0,
 543   REG_81,
 544   REG_82,
 545   REG_8F,
 546   REG_C0,
 547   REG_C1,
 548   REG_C6,
 549   REG_C7,
 550   REG_D0,
 551   REG_D1,
 552   REG_D2,
 553   REG_D3,
 554   REG_F6,
 555   REG_F7,
 556   REG_FE,
 557   REG_FF,
 558   REG_0F00,
 559   REG_0F01,
 560   REG_0F0D,
 561   REG_0F18,
 562   REG_0F71,
 563   REG_0F72,
 564   REG_0F73,
 565   REG_0FA6,
 566   REG_0FA7,
 567   REG_0FAE,
 568   REG_0FBA,
 569   REG_0FC7,
 570   REG_VEX_71,
 571   REG_VEX_72,
 572   REG_VEX_73,
 573   REG_VEX_AE,
 574   REG_XOP_LWPCB,
 575   REG_XOP_LWP
 576 };
 577
 578 enum
 579 {
 580   MOD_8D = 0,
 581   MOD_0F01_REG_0,
 582   MOD_0F01_REG_1,
 583   MOD_0F01_REG_2,
 584   MOD_0F01_REG_3,
 585   MOD_0F01_REG_7,
 586   MOD_0F12_PREFIX_0,
 587   MOD_0F13,
 588   MOD_0F16_PREFIX_0,
 589   MOD_0F17,
 590   MOD_0F18_REG_0,
 591   MOD_0F18_REG_1,
 592   MOD_0F18_REG_2,
 593   MOD_0F18_REG_3,
 594   MOD_0F20,
 595   MOD_0F21,
 596   MOD_0F22,
 597   MOD_0F23,
 598   MOD_0F24,
 599   MOD_0F26,
 600   MOD_0F2B_PREFIX_0,
 601   MOD_0F2B_PREFIX_1,
 602   MOD_0F2B_PREFIX_2,
 603   MOD_0F2B_PREFIX_3,
 604   MOD_0F51,
 605   MOD_0F71_REG_2,
 606   MOD_0F71_REG_4,
 607   MOD_0F71_REG_6,
 608   MOD_0F72_REG_2,
 609   MOD_0F72_REG_4,
 610   MOD_0F72_REG_6,
 611   MOD_0F73_REG_2,
 612   MOD_0F73_REG_3,
 613   MOD_0F73_REG_6,
 614   MOD_0F73_REG_7,
 615   MOD_0FAE_REG_0,
 616   MOD_0FAE_REG_1,
 617   MOD_0FAE_REG_2,
 618   MOD_0FAE_REG_3,
 619   MOD_0FAE_REG_4,
 620   MOD_0FAE_REG_5,
 621   MOD_0FAE_REG_6,
 622   MOD_0FAE_REG_7,
 623   MOD_0FB2,
 624   MOD_0FB4,
 625   MOD_0FB5,
 626   MOD_0FC7_REG_6,
 627   MOD_0FC7_REG_7,
 628   MOD_0FD7,
 629   MOD_0FE7_PREFIX_2,
 630   MOD_0FF0_PREFIX_3,
 631   MOD_0F382A_PREFIX_2,
 632   MOD_62_32BIT,
 633   MOD_C4_32BIT,
 634   MOD_C5_32BIT,
 635   MOD_VEX_12_PREFIX_0,
 636   MOD_VEX_13,
 637   MOD_VEX_16_PREFIX_0,
 638   MOD_VEX_17,
 639   MOD_VEX_2B,
 640   MOD_VEX_51,
 641   MOD_VEX_71_REG_2,
 642   MOD_VEX_71_REG_4,
 643   MOD_VEX_71_REG_6,
 644   MOD_VEX_72_REG_2,
 645   MOD_VEX_72_REG_4,
 646   MOD_VEX_72_REG_6,
 647   MOD_VEX_73_REG_2,
 648   MOD_VEX_73_REG_3,
 649   MOD_VEX_73_REG_6,
 650   MOD_VEX_73_REG_7,
 651   MOD_VEX_AE_REG_2,
 652   MOD_VEX_AE_REG_3,
 653   MOD_VEX_D7_PREFIX_2,
 654   MOD_VEX_E7_PREFIX_2,
 655   MOD_VEX_F0_PREFIX_3,
 656   MOD_VEX_3818_PREFIX_2,
 657   MOD_VEX_3819_PREFIX_2,
 658   MOD_VEX_381A_PREFIX_2,
 659   MOD_VEX_382A_PREFIX_2,
 660   MOD_VEX_382C_PREFIX_2,
 661   MOD_VEX_382D_PREFIX_2,
 662   MOD_VEX_382E_PREFIX_2,
 663   MOD_VEX_382F_PREFIX_2
 664 };
 665
 666 enum
 667 {
 668   RM_0F01_REG_0 = 0,
 669   RM_0F01_REG_1,
 670   RM_0F01_REG_2,
 671   RM_0F01_REG_3,
 672   RM_0F01_REG_7,
 673   RM_0FAE_REG_5,
 674   RM_0FAE_REG_6,
 675   RM_0FAE_REG_7
 676 };
 677
 678 enum
 679 {
 680   PREFIX_90 = 0,
 681   PREFIX_0F10,
 682   PREFIX_0F11,
 683   PREFIX_0F12,
 684   PREFIX_0F16,
 685   PREFIX_0F2A,
 686   PREFIX_0F2B,
 687   PREFIX_0F2C,
 688   PREFIX_0F2D,
 689   PREFIX_0F2E,
 690   PREFIX_0F2F,
 691   PREFIX_0F51,
 692   PREFIX_0F52,
 693   PREFIX_0F53,
 694   PREFIX_0F58,
 695   PREFIX_0F59,
 696   PREFIX_0F5A,
 697   PREFIX_0F5B,
 698   PREFIX_0F5C,
 699   PREFIX_0F5D,
 700   PREFIX_0F5E,
 701   PREFIX_0F5F,
 702   PREFIX_0F60,
 703   PREFIX_0F61,
 704   PREFIX_0F62,
 705   PREFIX_0F6C,
 706   PREFIX_0F6D,
 707   PREFIX_0F6F,
 708   PREFIX_0F70,
 709   PREFIX_0F73_REG_3,
 710   PREFIX_0F73_REG_7,
 711   PREFIX_0F78,
 712   PREFIX_0F79,
 713   PREFIX_0F7C,
 714   PREFIX_0F7D,
 715   PREFIX_0F7E,
 716   PREFIX_0F7F,
 717   PREFIX_0FB8,
 718   PREFIX_0FBD,
 719   PREFIX_0FC2,
 720   PREFIX_0FC3,
 721   PREFIX_0FC7_REG_6,
 722   PREFIX_0FD0,
 723   PREFIX_0FD6,
 724   PREFIX_0FE6,
 725   PREFIX_0FE7,
 726   PREFIX_0FF0,
 727   PREFIX_0FF7,
 728   PREFIX_0F3810,
 729   PREFIX_0F3814,
 730   PREFIX_0F3815,
 731   PREFIX_0F3817,
 732   PREFIX_0F3820,
 733   PREFIX_0F3821,
 734   PREFIX_0F3822,
 735   PREFIX_0F3823,
 736   PREFIX_0F3824,
 737   PREFIX_0F3825,
 738   PREFIX_0F3828,
 739   PREFIX_0F3829,
 740   PREFIX_0F382A,
 741   PREFIX_0F382B,
 742   PREFIX_0F3830,
 743   PREFIX_0F3831,
 744   PREFIX_0F3832,
 745   PREFIX_0F3833,
 746   PREFIX_0F3834,
 747   PREFIX_0F3835,
 748   PREFIX_0F3837,
 749   PREFIX_0F3838,
 750   PREFIX_0F3839,
 751   PREFIX_0F383A,
 752   PREFIX_0F383B,
 753   PREFIX_0F383C,
 754   PREFIX_0F383D,
 755   PREFIX_0F383E,
 756   PREFIX_0F383F,
 757   PREFIX_0F3840,
 758   PREFIX_0F3841,
 759   PREFIX_0F3880,
 760   PREFIX_0F3881,
 761   PREFIX_0F38DB,
 762   PREFIX_0F38DC,
 763   PREFIX_0F38DD,
 764   PREFIX_0F38DE,
 765   PREFIX_0F38DF,
 766   PREFIX_0F38F0,
 767   PREFIX_0F38F1,
 768   PREFIX_0F3A08,
 769   PREFIX_0F3A09,
 770   PREFIX_0F3A0A,
 771   PREFIX_0F3A0B,
 772   PREFIX_0F3A0C,
 773   PREFIX_0F3A0D,
 774   PREFIX_0F3A0E,
 775   PREFIX_0F3A14,
 776   PREFIX_0F3A15,
 777   PREFIX_0F3A16,
 778   PREFIX_0F3A17,
 779   PREFIX_0F3A20,
 780   PREFIX_0F3A21,
 781   PREFIX_0F3A22,
 782   PREFIX_0F3A40,
 783   PREFIX_0F3A41,
 784   PREFIX_0F3A42,
 785   PREFIX_0F3A44,
 786   PREFIX_0F3A60,
 787   PREFIX_0F3A61,
 788   PREFIX_0F3A62,
 789   PREFIX_0F3A63,
 790   PREFIX_0F3ADF,
 791   PREFIX_VEX_10,
 792   PREFIX_VEX_11,
 793   PREFIX_VEX_12,
 794   PREFIX_VEX_16,
 795   PREFIX_VEX_2A,
 796   PREFIX_VEX_2C,
 797   PREFIX_VEX_2D,
 798   PREFIX_VEX_2E,
 799   PREFIX_VEX_2F,
 800   PREFIX_VEX_51,
 801   PREFIX_VEX_52,
 802   PREFIX_VEX_53,
 803   PREFIX_VEX_58,
 804   PREFIX_VEX_59,
 805   PREFIX_VEX_5A,
 806   PREFIX_VEX_5B,
 807   PREFIX_VEX_5C,
 808   PREFIX_VEX_5D,
 809   PREFIX_VEX_5E,
 810   PREFIX_VEX_5F,
 811   PREFIX_VEX_60,
 812   PREFIX_VEX_61,
 813   PREFIX_VEX_62,
 814   PREFIX_VEX_63,
 815   PREFIX_VEX_64,
 816   PREFIX_VEX_65,
 817   PREFIX_VEX_66,
 818   PREFIX_VEX_67,
 819   PREFIX_VEX_68,
 820   PREFIX_VEX_69,
 821   PREFIX_VEX_6A,
 822   PREFIX_VEX_6B,
 823   PREFIX_VEX_6C,
 824   PREFIX_VEX_6D,
 825   PREFIX_VEX_6E,
 826   PREFIX_VEX_6F,
 827   PREFIX_VEX_70,
 828   PREFIX_VEX_71_REG_2,
 829   PREFIX_VEX_71_REG_4,
 830   PREFIX_VEX_71_REG_6,
 831   PREFIX_VEX_72_REG_2,
 832   PREFIX_VEX_72_REG_4,
 833   PREFIX_VEX_72_REG_6,
 834   PREFIX_VEX_73_REG_2,
 835   PREFIX_VEX_73_REG_3,
 836   PREFIX_VEX_73_REG_6,
 837   PREFIX_VEX_73_REG_7,
 838   PREFIX_VEX_74,
 839   PREFIX_VEX_75,
 840   PREFIX_VEX_76,
 841   PREFIX_VEX_77,
 842   PREFIX_VEX_7C,
 843   PREFIX_VEX_7D,
 844   PREFIX_VEX_7E,
 845   PREFIX_VEX_7F,
 846   PREFIX_VEX_C2,
 847   PREFIX_VEX_C4,
 848   PREFIX_VEX_C5,
 849   PREFIX_VEX_D0,
 850   PREFIX_VEX_D1,
 851   PREFIX_VEX_D2,
 852   PREFIX_VEX_D3,
 853   PREFIX_VEX_D4,
 854   PREFIX_VEX_D5,
 855   PREFIX_VEX_D6,
 856   PREFIX_VEX_D7,
 857   PREFIX_VEX_D8,
 858   PREFIX_VEX_D9,
 859   PREFIX_VEX_DA,
 860   PREFIX_VEX_DB,
 861   PREFIX_VEX_DC,
 862   PREFIX_VEX_DD,
 863   PREFIX_VEX_DE,
 864   PREFIX_VEX_DF,
 865   PREFIX_VEX_E0,
 866   PREFIX_VEX_E1,
 867   PREFIX_VEX_E2,
 868   PREFIX_VEX_E3,
 869   PREFIX_VEX_E4,
 870   PREFIX_VEX_E5,
 871   PREFIX_VEX_E6,
 872   PREFIX_VEX_E7,
 873   PREFIX_VEX_E8,
 874   PREFIX_VEX_E9,
 875   PREFIX_VEX_EA,
 876   PREFIX_VEX_EB,
 877   PREFIX_VEX_EC,
 878   PREFIX_VEX_ED,
 879   PREFIX_VEX_EE,
 880   PREFIX_VEX_EF,
 881   PREFIX_VEX_F0,
 882   PREFIX_VEX_F1,
 883   PREFIX_VEX_F2,
 884   PREFIX_VEX_F3,
 885   PREFIX_VEX_F4,
 886   PREFIX_VEX_F5,
 887   PREFIX_VEX_F6,
 888   PREFIX_VEX_F7,
 889   PREFIX_VEX_F8,
 890   PREFIX_VEX_F9,
 891   PREFIX_VEX_FA,
 892   PREFIX_VEX_FB,
 893   PREFIX_VEX_FC,
 894   PREFIX_VEX_FD,
 895   PREFIX_VEX_FE,
 896   PREFIX_VEX_3800,
 897   PREFIX_VEX_3801,
 898   PREFIX_VEX_3802,
 899   PREFIX_VEX_3803,
 900   PREFIX_VEX_3804,
 901   PREFIX_VEX_3805,
 902   PREFIX_VEX_3806,
 903   PREFIX_VEX_3807,
 904   PREFIX_VEX_3808,
 905   PREFIX_VEX_3809,
 906   PREFIX_VEX_380A,
 907   PREFIX_VEX_380B,
 908   PREFIX_VEX_380C,
 909   PREFIX_VEX_380D,
 910   PREFIX_VEX_380E,
 911   PREFIX_VEX_380F,
 912   PREFIX_VEX_3817,
 913   PREFIX_VEX_3818,
 914   PREFIX_VEX_3819,
 915   PREFIX_VEX_381A,
 916   PREFIX_VEX_381C,
 917   PREFIX_VEX_381D,
 918   PREFIX_VEX_381E,
 919   PREFIX_VEX_3820,
 920   PREFIX_VEX_3821,
 921   PREFIX_VEX_3822,
 922   PREFIX_VEX_3823,
 923   PREFIX_VEX_3824,
 924   PREFIX_VEX_3825,
 925   PREFIX_VEX_3828,
 926   PREFIX_VEX_3829,
 927   PREFIX_VEX_382A,
 928   PREFIX_VEX_382B,
 929   PREFIX_VEX_382C,
 930   PREFIX_VEX_382D,
 931   PREFIX_VEX_382E,
 932   PREFIX_VEX_382F,
 933   PREFIX_VEX_3830,
 934   PREFIX_VEX_3831,
 935   PREFIX_VEX_3832,
 936   PREFIX_VEX_3833,
 937   PREFIX_VEX_3834,
 938   PREFIX_VEX_3835,
 939   PREFIX_VEX_3837,
 940   PREFIX_VEX_3838,
 941   PREFIX_VEX_3839,
 942   PREFIX_VEX_383A,
 943   PREFIX_VEX_383B,
 944   PREFIX_VEX_383C,
 945   PREFIX_VEX_383D,
 946   PREFIX_VEX_383E,
 947   PREFIX_VEX_383F,
 948   PREFIX_VEX_3840,
 949   PREFIX_VEX_3841,
 950   PREFIX_VEX_3896,
 951   PREFIX_VEX_3897,
 952   PREFIX_VEX_3898,
 953   PREFIX_VEX_3899,
 954   PREFIX_VEX_389A,
 955   PREFIX_VEX_389B,
 956   PREFIX_VEX_389C,
 957   PREFIX_VEX_389D,
 958   PREFIX_VEX_389E,
 959   PREFIX_VEX_389F,
 960   PREFIX_VEX_38A6,
 961   PREFIX_VEX_38A7,
 962   PREFIX_VEX_38A8,
 963   PREFIX_VEX_38A9,
 964   PREFIX_VEX_38AA,
 965   PREFIX_VEX_38AB,
 966   PREFIX_VEX_38AC,
 967   PREFIX_VEX_38AD,
 968   PREFIX_VEX_38AE,
 969   PREFIX_VEX_38AF,
 970   PREFIX_VEX_38B6,
 971   PREFIX_VEX_38B7,
 972   PREFIX_VEX_38B8,
 973   PREFIX_VEX_38B9,
 974   PREFIX_VEX_38BA,
 975   PREFIX_VEX_38BB,
 976   PREFIX_VEX_38BC,
 977   PREFIX_VEX_38BD,
 978   PREFIX_VEX_38BE,
 979   PREFIX_VEX_38BF,
 980   PREFIX_VEX_38DB,
 981   PREFIX_VEX_38DC,
 982   PREFIX_VEX_38DD,
 983   PREFIX_VEX_38DE,
 984   PREFIX_VEX_38DF,
 985   PREFIX_VEX_3A04,
 986   PREFIX_VEX_3A05,
 987   PREFIX_VEX_3A06,
 988   PREFIX_VEX_3A08,
 989   PREFIX_VEX_3A09,
 990   PREFIX_VEX_3A0A,
 991   PREFIX_VEX_3A0B,
 992   PREFIX_VEX_3A0C,
 993   PREFIX_VEX_3A0D,
 994   PREFIX_VEX_3A0E,
 995   PREFIX_VEX_3A0F,
 996   PREFIX_VEX_3A14,
 997   PREFIX_VEX_3A15,
 998   PREFIX_VEX_3A16,
 999   PREFIX_VEX_3A17,
1000   PREFIX_VEX_3A18,
1001   PREFIX_VEX_3A19,
1002   PREFIX_VEX_3A20,
1003   PREFIX_VEX_3A21,
1004   PREFIX_VEX_3A22,
1005   PREFIX_VEX_3A40,
1006   PREFIX_VEX_3A41,
1007   PREFIX_VEX_3A42,
1008   PREFIX_VEX_3A44,
1009   PREFIX_VEX_3A4A,
1010   PREFIX_VEX_3A4B,
1011   PREFIX_VEX_3A4C,
1012   PREFIX_VEX_3A5C,
1013   PREFIX_VEX_3A5D,
1014   PREFIX_VEX_3A5E,
1015   PREFIX_VEX_3A5F,
1016   PREFIX_VEX_3A60,
1017   PREFIX_VEX_3A61,
1018   PREFIX_VEX_3A62,
1019   PREFIX_VEX_3A63,
1020   PREFIX_VEX_3A68,
1021   PREFIX_VEX_3A69,
1022   PREFIX_VEX_3A6A,
1023   PREFIX_VEX_3A6B,
1024   PREFIX_VEX_3A6C,
1025   PREFIX_VEX_3A6D,
1026   PREFIX_VEX_3A6E,
1027   PREFIX_VEX_3A6F,
1028   PREFIX_VEX_3A78,
1029   PREFIX_VEX_3A79,
1030   PREFIX_VEX_3A7A,
1031   PREFIX_VEX_3A7B,
1032   PREFIX_VEX_3A7C,
1033   PREFIX_VEX_3A7D,
1034   PREFIX_VEX_3A7E,
1035   PREFIX_VEX_3A7F,
1036   PREFIX_VEX_3ADF
1037 };
1038
1039 enum
1040 {
1041   X86_64_06 = 0,
1042   X86_64_07,
1043   X86_64_0D,
1044   X86_64_16,
1045   X86_64_17,
1046   X86_64_1E,
1047   X86_64_1F,
1048   X86_64_27,
1049   X86_64_2F,
1050   X86_64_37,
1051   X86_64_3F,
1052   X86_64_60,
1053   X86_64_61,
1054   X86_64_62,
1055   X86_64_63,
1056   X86_64_6D,
1057   X86_64_6F,
1058   X86_64_9A,
1059   X86_64_C4,
1060   X86_64_C5,
1061   X86_64_CE,
1062   X86_64_D4,
1063   X86_64_D5,
1064   X86_64_EA,
1065   X86_64_0F01_REG_0,
1066   X86_64_0F01_REG_1,
1067   X86_64_0F01_REG_2,
1068   X86_64_0F01_REG_3
1069 };
1070
1071 enum
1072 {
1073   THREE_BYTE_0F38 = 0,
1074   THREE_BYTE_0F3A,
1075   THREE_BYTE_0F7A
1076 };
1077
1078 enum
1079 {
1080   XOP_09 = 0,
1081   XOP_0A
1082 };
1083
1084 enum
1085 {
1086   VEX_0F = 0,
1087   VEX_0F38,
1088   VEX_0F3A
1089 };
1090
1091 enum
1092 {
1093   VEX_LEN_10_P_1 = 0,
1094   VEX_LEN_10_P_3,
1095   VEX_LEN_11_P_1,
1096   VEX_LEN_11_P_3,
1097   VEX_LEN_12_P_0_M_0,
1098   VEX_LEN_12_P_0_M_1,
1099   VEX_LEN_12_P_2,
1100   VEX_LEN_13_M_0,
1101   VEX_LEN_16_P_0_M_0,
1102   VEX_LEN_16_P_0_M_1,
1103   VEX_LEN_16_P_2,
1104   VEX_LEN_17_M_0,
1105   VEX_LEN_2A_P_1,
1106   VEX_LEN_2A_P_3,
1107   VEX_LEN_2C_P_1,
1108   VEX_LEN_2C_P_3,
1109   VEX_LEN_2D_P_1,
1110   VEX_LEN_2D_P_3,
1111   VEX_LEN_2E_P_0,
1112   VEX_LEN_2E_P_2,
1113   VEX_LEN_2F_P_0,
1114   VEX_LEN_2F_P_2,
1115   VEX_LEN_51_P_1,
1116   VEX_LEN_51_P_3,
1117   VEX_LEN_52_P_1,
1118   VEX_LEN_53_P_1,
1119   VEX_LEN_58_P_1,
1120   VEX_LEN_58_P_3,
1121   VEX_LEN_59_P_1,
1122   VEX_LEN_59_P_3,
1123   VEX_LEN_5A_P_1,
1124   VEX_LEN_5A_P_3,
1125   VEX_LEN_5C_P_1,
1126   VEX_LEN_5C_P_3,
1127   VEX_LEN_5D_P_1,
1128   VEX_LEN_5D_P_3,
1129   VEX_LEN_5E_P_1,
1130   VEX_LEN_5E_P_3,
1131   VEX_LEN_5F_P_1,
1132   VEX_LEN_5F_P_3,
1133   VEX_LEN_60_P_2,
1134   VEX_LEN_61_P_2,
1135   VEX_LEN_62_P_2,
1136   VEX_LEN_63_P_2,
1137   VEX_LEN_64_P_2,
1138   VEX_LEN_65_P_2,
1139   VEX_LEN_66_P_2,
1140   VEX_LEN_67_P_2,
1141   VEX_LEN_68_P_2,
1142   VEX_LEN_69_P_2,
1143   VEX_LEN_6A_P_2,
1144   VEX_LEN_6B_P_2,
1145   VEX_LEN_6C_P_2,
1146   VEX_LEN_6D_P_2,
1147   VEX_LEN_6E_P_2,
1148   VEX_LEN_70_P_1,
1149   VEX_LEN_70_P_2,
1150   VEX_LEN_70_P_3,
1151   VEX_LEN_71_R_2_P_2,
1152   VEX_LEN_71_R_4_P_2,
1153   VEX_LEN_71_R_6_P_2,
1154   VEX_LEN_72_R_2_P_2,
1155   VEX_LEN_72_R_4_P_2,
1156   VEX_LEN_72_R_6_P_2,
1157   VEX_LEN_73_R_2_P_2,
1158   VEX_LEN_73_R_3_P_2,
1159   VEX_LEN_73_R_6_P_2,
1160   VEX_LEN_73_R_7_P_2,
1161   VEX_LEN_74_P_2,
1162   VEX_LEN_75_P_2,
1163   VEX_LEN_76_P_2,
1164   VEX_LEN_7E_P_1,
1165   VEX_LEN_7E_P_2,
1166   VEX_LEN_AE_R_2_M_0,
1167   VEX_LEN_AE_R_3_M_0,
1168   VEX_LEN_C2_P_1,
1169   VEX_LEN_C2_P_3,
1170   VEX_LEN_C4_P_2,
1171   VEX_LEN_C5_P_2,
1172   VEX_LEN_D1_P_2,
1173   VEX_LEN_D2_P_2,
1174   VEX_LEN_D3_P_2,
1175   VEX_LEN_D4_P_2,
1176   VEX_LEN_D5_P_2,
1177   VEX_LEN_D6_P_2,
1178   VEX_LEN_D7_P_2_M_1,
1179   VEX_LEN_D8_P_2,
1180   VEX_LEN_D9_P_2,
1181   VEX_LEN_DA_P_2,
1182   VEX_LEN_DB_P_2,
1183   VEX_LEN_DC_P_2,
1184   VEX_LEN_DD_P_2,
1185   VEX_LEN_DE_P_2,
1186   VEX_LEN_DF_P_2,
1187   VEX_LEN_E0_P_2,
1188   VEX_LEN_E1_P_2,
1189   VEX_LEN_E2_P_2,
1190   VEX_LEN_E3_P_2,
1191   VEX_LEN_E4_P_2,
1192   VEX_LEN_E5_P_2,
1193   VEX_LEN_E8_P_2,
1194   VEX_LEN_E9_P_2,
1195   VEX_LEN_EA_P_2,
1196   VEX_LEN_EB_P_2,
1197   VEX_LEN_EC_P_2,
1198   VEX_LEN_ED_P_2,
1199   VEX_LEN_EE_P_2,
1200   VEX_LEN_EF_P_2,
1201   VEX_LEN_F1_P_2,
1202   VEX_LEN_F2_P_2,
1203   VEX_LEN_F3_P_2,
1204   VEX_LEN_F4_P_2,
1205   VEX_LEN_F5_P_2,
1206   VEX_LEN_F6_P_2,
1207   VEX_LEN_F7_P_2,
1208   VEX_LEN_F8_P_2,
1209   VEX_LEN_F9_P_2,
1210   VEX_LEN_FA_P_2,
1211   VEX_LEN_FB_P_2,
1212   VEX_LEN_FC_P_2,
1213   VEX_LEN_FD_P_2,
1214   VEX_LEN_FE_P_2,
1215   VEX_LEN_3800_P_2,
1216   VEX_LEN_3801_P_2,
1217   VEX_LEN_3802_P_2,
1218   VEX_LEN_3803_P_2,
1219   VEX_LEN_3804_P_2,
1220   VEX_LEN_3805_P_2,
1221   VEX_LEN_3806_P_2,
1222   VEX_LEN_3807_P_2,
1223   VEX_LEN_3808_P_2,
1224   VEX_LEN_3809_P_2,
1225   VEX_LEN_380A_P_2,
1226   VEX_LEN_380B_P_2,
1227   VEX_LEN_3819_P_2_M_0,
1228   VEX_LEN_381A_P_2_M_0,
1229   VEX_LEN_381C_P_2,
1230   VEX_LEN_381D_P_2,
1231   VEX_LEN_381E_P_2,
1232   VEX_LEN_3820_P_2,
1233   VEX_LEN_3821_P_2,
1234   VEX_LEN_3822_P_2,
1235   VEX_LEN_3823_P_2,
1236   VEX_LEN_3824_P_2,
1237   VEX_LEN_3825_P_2,
1238   VEX_LEN_3828_P_2,
1239   VEX_LEN_3829_P_2,
1240   VEX_LEN_382A_P_2_M_0,
1241   VEX_LEN_382B_P_2,
1242   VEX_LEN_3830_P_2,
1243   VEX_LEN_3831_P_2,
1244   VEX_LEN_3832_P_2,
1245   VEX_LEN_3833_P_2,
1246   VEX_LEN_3834_P_2,
1247   VEX_LEN_3835_P_2,
1248   VEX_LEN_3837_P_2,
1249   VEX_LEN_3838_P_2,
1250   VEX_LEN_3839_P_2,
1251   VEX_LEN_383A_P_2,
1252   VEX_LEN_383B_P_2,
1253   VEX_LEN_383C_P_2,
1254   VEX_LEN_383D_P_2,
1255   VEX_LEN_383E_P_2,
1256   VEX_LEN_383F_P_2,
1257   VEX_LEN_3840_P_2,
1258   VEX_LEN_3841_P_2,
1259   VEX_LEN_38DB_P_2,
1260   VEX_LEN_38DC_P_2,
1261   VEX_LEN_38DD_P_2,
1262   VEX_LEN_38DE_P_2,
1263   VEX_LEN_38DF_P_2,
1264   VEX_LEN_3A06_P_2,
1265   VEX_LEN_3A0A_P_2,
1266   VEX_LEN_3A0B_P_2,
1267   VEX_LEN_3A0E_P_2,
1268   VEX_LEN_3A0F_P_2,
1269   VEX_LEN_3A14_P_2,
1270   VEX_LEN_3A15_P_2,
1271   VEX_LEN_3A16_P_2,
1272   VEX_LEN_3A17_P_2,
1273   VEX_LEN_3A18_P_2,
1274   VEX_LEN_3A19_P_2,
1275   VEX_LEN_3A20_P_2,
1276   VEX_LEN_3A21_P_2,
1277   VEX_LEN_3A22_P_2,
1278   VEX_LEN_3A41_P_2,
1279   VEX_LEN_3A42_P_2,
1280   VEX_LEN_3A44_P_2,
1281   VEX_LEN_3A4C_P_2,
1282   VEX_LEN_3A60_P_2,
1283   VEX_LEN_3A61_P_2,
1284   VEX_LEN_3A62_P_2,
1285   VEX_LEN_3A63_P_2,
1286   VEX_LEN_3A6A_P_2,
1287   VEX_LEN_3A6B_P_2,
1288   VEX_LEN_3A6E_P_2,
1289   VEX_LEN_3A6F_P_2,
1290   VEX_LEN_3A7A_P_2,
1291   VEX_LEN_3A7B_P_2,
1292   VEX_LEN_3A7E_P_2,
1293   VEX_LEN_3A7F_P_2,
1294   VEX_LEN_3ADF_P_2
1295 };
1296
1297 typedef void (*op_rtn) (int bytemode, int sizeflag);
1298
1299 struct dis386 {
1300   const char *name;
1301   struct
1302     {
1303       op_rtn rtn;
1304       int bytemode;
1305     } op[MAX_OPERANDS];
1306 };
1307
1308 /* Upper case letters in the instruction names here are macros.
1309    'A' => print 'b' if no register operands or suffix_always is true
1310    'B' => print 'b' if suffix_always is true
1311    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1312           size prefix
1313    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1314           suffix_always is true
1315    'E' => print 'e' if 32-bit form of jcxz
1316    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1317    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1318    'H' => print ",pt" or ",pn" branch hint
1319    'I' => honor following macro letter even in Intel mode (implemented only
1320           for some of the macro letters)
1321    'J' => print 'l'
1322    'K' => print 'd' or 'q' if rex prefix is present.
1323    'L' => print 'l' if suffix_always is true
1324    'M' => print 'r' if intel_mnemonic is false.
1325    'N' => print 'n' if instruction has no wait "prefix"
1326    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1327    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1328           or suffix_always is true.  print 'q' if rex prefix is present.
1329    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1330           is true
1331    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1332    'S' => print 'w', 'l' or 'q' if suffix_always is true
1333    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1334    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1335    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1336    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1337    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1338    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1339           suffix_always is true.
1340    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1341    '!' => change condition from true to false or from false to true.
1342    '%' => add 1 upper case letter to the macro.
1343
1344    2 upper case letter macros:
1345    "XY" => print 'x' or 'y' if no register operands or suffix_always
1346            is true.
1347    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1348    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1349            or suffix_always is true
1350    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1351    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1352    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1353
1354    Many of the above letters print nothing in Intel mode.  See "putop"
1355    for the details.
1356
1357    Braces '{' and '}', and vertical bars '|', indicate alternative
1358    mnemonic strings for AT&T and Intel.  */
1359
1360 static const struct dis386 dis386[] = {
1361   /* 00 */
1362   { "addB",             { Eb, Gb } },
1363   { "addS",             { Ev, Gv } },
1364   { "addB",             { Gb, EbS } },
1365   { "addS",             { Gv, EvS } },
1366   { "addB",             { AL, Ib } },
1367   { "addS",             { eAX, Iv } },
1368   { X86_64_TABLE (X86_64_06) },
1369   { X86_64_TABLE (X86_64_07) },
1370   /* 08 */
1371   { "orB",              { Eb, Gb } },
1372   { "orS",              { Ev, Gv } },
1373   { "orB",              { Gb, EbS } },
1374   { "orS",              { Gv, EvS } },
1375   { "orB",              { AL, Ib } },
1376   { "orS",              { eAX, Iv } },
1377   { X86_64_TABLE (X86_64_0D) },
1378   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1379   /* 10 */
1380   { "adcB",             { Eb, Gb } },
1381   { "adcS",             { Ev, Gv } },
1382   { "adcB",             { Gb, EbS } },
1383   { "adcS",             { Gv, EvS } },
1384   { "adcB",             { AL, Ib } },
1385   { "adcS",             { eAX, Iv } },
1386   { X86_64_TABLE (X86_64_16) },
1387   { X86_64_TABLE (X86_64_17) },
1388   /* 18 */
1389   { "sbbB",             { Eb, Gb } },
1390   { "sbbS",             { Ev, Gv } },
1391   { "sbbB",             { Gb, EbS } },
1392   { "sbbS",             { Gv, EvS } },
1393   { "sbbB",             { AL, Ib } },
1394   { "sbbS",             { eAX, Iv } },
1395   { X86_64_TABLE (X86_64_1E) },
1396   { X86_64_TABLE (X86_64_1F) },
1397   /* 20 */
1398   { "andB",             { Eb, Gb } },
1399   { "andS",             { Ev, Gv } },
1400   { "andB",             { Gb, EbS } },
1401   { "andS",             { Gv, EvS } },
1402   { "andB",             { AL, Ib } },
1403   { "andS",             { eAX, Iv } },
1404   { "(bad)",            { XX } },       /* SEG ES prefix */
1405   { X86_64_TABLE (X86_64_27) },
1406   /* 28 */
1407   { "subB",             { Eb, Gb } },
1408   { "subS",             { Ev, Gv } },
1409   { "subB",             { Gb, EbS } },
1410   { "subS",             { Gv, EvS } },
1411   { "subB",             { AL, Ib } },
1412   { "subS",             { eAX, Iv } },
1413   { "(bad)",            { XX } },       /* SEG CS prefix */
1414   { X86_64_TABLE (X86_64_2F) },
1415   /* 30 */
1416   { "xorB",             { Eb, Gb } },
1417   { "xorS",             { Ev, Gv } },
1418   { "xorB",             { Gb, EbS } },
1419   { "xorS",             { Gv, EvS } },
1420   { "xorB",             { AL, Ib } },
1421   { "xorS",             { eAX, Iv } },
1422   { "(bad)",            { XX } },       /* SEG SS prefix */
1423   { X86_64_TABLE (X86_64_37) },
1424   /* 38 */
1425   { "cmpB",             { Eb, Gb } },
1426   { "cmpS",             { Ev, Gv } },
1427   { "cmpB",             { Gb, EbS } },
1428   { "cmpS",             { Gv, EvS } },
1429   { "cmpB",             { AL, Ib } },
1430   { "cmpS",             { eAX, Iv } },
1431   { "(bad)",            { XX } },       /* SEG DS prefix */
1432   { X86_64_TABLE (X86_64_3F) },
1433   /* 40 */
1434   { "inc{S|}",          { RMeAX } },
1435   { "inc{S|}",          { RMeCX } },
1436   { "inc{S|}",          { RMeDX } },
1437   { "inc{S|}",          { RMeBX } },
1438   { "inc{S|}",          { RMeSP } },
1439   { "inc{S|}",          { RMeBP } },
1440   { "inc{S|}",          { RMeSI } },
1441   { "inc{S|}",          { RMeDI } },
1442   /* 48 */
1443   { "dec{S|}",          { RMeAX } },
1444   { "dec{S|}",          { RMeCX } },
1445   { "dec{S|}",          { RMeDX } },
1446   { "dec{S|}",          { RMeBX } },
1447   { "dec{S|}",          { RMeSP } },
1448   { "dec{S|}",          { RMeBP } },
1449   { "dec{S|}",          { RMeSI } },
1450   { "dec{S|}",          { RMeDI } },
1451   /* 50 */
1452   { "pushV",            { RMrAX } },
1453   { "pushV",            { RMrCX } },
1454   { "pushV",            { RMrDX } },
1455   { "pushV",            { RMrBX } },
1456   { "pushV",            { RMrSP } },
1457   { "pushV",            { RMrBP } },
1458   { "pushV",            { RMrSI } },
1459   { "pushV",            { RMrDI } },
1460   /* 58 */
1461   { "popV",             { RMrAX } },
1462   { "popV",             { RMrCX } },
1463   { "popV",             { RMrDX } },
1464   { "popV",             { RMrBX } },
1465   { "popV",             { RMrSP } },
1466   { "popV",             { RMrBP } },
1467   { "popV",             { RMrSI } },
1468   { "popV",             { RMrDI } },
1469   /* 60 */
1470   { X86_64_TABLE (X86_64_60) },
1471   { X86_64_TABLE (X86_64_61) },
1472   { X86_64_TABLE (X86_64_62) },
1473   { X86_64_TABLE (X86_64_63) },
1474   { "(bad)",            { XX } },       /* seg fs */
1475   { "(bad)",            { XX } },       /* seg gs */
1476   { "(bad)",            { XX } },       /* op size prefix */
1477   { "(bad)",            { XX } },       /* adr size prefix */
1478   /* 68 */
1479   { "pushT",            { Iq } },
1480   { "imulS",            { Gv, Ev, Iv } },
1481   { "pushT",            { sIb } },
1482   { "imulS",            { Gv, Ev, sIb } },
1483   { "ins{b|}",          { Ybr, indirDX } },
1484   { X86_64_TABLE (X86_64_6D) },
1485   { "outs{b|}",         { indirDXr, Xb } },
1486   { X86_64_TABLE (X86_64_6F) },
1487   /* 70 */
1488   { "joH",              { Jb, XX, cond_jump_flag } },
1489   { "jnoH",             { Jb, XX, cond_jump_flag } },
1490   { "jbH",              { Jb, XX, cond_jump_flag } },
1491   { "jaeH",             { Jb, XX, cond_jump_flag } },
1492   { "jeH",              { Jb, XX, cond_jump_flag } },
1493   { "jneH",             { Jb, XX, cond_jump_flag } },
1494   { "jbeH",             { Jb, XX, cond_jump_flag } },
1495   { "jaH",              { Jb, XX, cond_jump_flag } },
1496   /* 78 */
1497   { "jsH",              { Jb, XX, cond_jump_flag } },
1498   { "jnsH",             { Jb, XX, cond_jump_flag } },
1499   { "jpH",              { Jb, XX, cond_jump_flag } },
1500   { "jnpH",             { Jb, XX, cond_jump_flag } },
1501   { "jlH",              { Jb, XX, cond_jump_flag } },
1502   { "jgeH",             { Jb, XX, cond_jump_flag } },
1503   { "jleH",             { Jb, XX, cond_jump_flag } },
1504   { "jgH",              { Jb, XX, cond_jump_flag } },
1505   /* 80 */
1506   { REG_TABLE (REG_80) },
1507   { REG_TABLE (REG_81) },
1508   { "(bad)",            { XX } },
1509   { REG_TABLE (REG_82) },
1510   { "testB",            { Eb, Gb } },
1511   { "testS",            { Ev, Gv } },
1512   { "xchgB",            { Eb, Gb } },
1513   { "xchgS",            { Ev, Gv } },
1514   /* 88 */
1515   { "movB",             { Eb, Gb } },
1516   { "movS",             { Ev, Gv } },
1517   { "movB",             { Gb, EbS } },
1518   { "movS",             { Gv, EvS } },
1519   { "movD",             { Sv, Sw } },
1520   { MOD_TABLE (MOD_8D) },
1521   { "movD",             { Sw, Sv } },
1522   { REG_TABLE (REG_8F) },
1523   /* 90 */
1524   { PREFIX_TABLE (PREFIX_90) },
1525   { "xchgS",            { RMeCX, eAX } },
1526   { "xchgS",            { RMeDX, eAX } },
1527   { "xchgS",            { RMeBX, eAX } },
1528   { "xchgS",            { RMeSP, eAX } },
1529   { "xchgS",            { RMeBP, eAX } },
1530   { "xchgS",            { RMeSI, eAX } },
1531   { "xchgS",            { RMeDI, eAX } },
1532   /* 98 */
1533   { "cW{t|}R",          { XX } },
1534   { "cR{t|}O",          { XX } },
1535   { X86_64_TABLE (X86_64_9A) },
1536   { "(bad)",            { XX } },       /* fwait */
1537   { "pushfT",           { XX } },
1538   { "popfT",            { XX } },
1539   { "sahf",             { XX } },
1540   { "lahf",             { XX } },
1541   /* a0 */
1542   { "mov%LB",           { AL, Ob } },
1543   { "mov%LS",           { eAX, Ov } },
1544   { "mov%LB",           { Ob, AL } },
1545   { "mov%LS",           { Ov, eAX } },
1546   { "movs{b|}",         { Ybr, Xb } },
1547   { "movs{R|}",         { Yvr, Xv } },
1548   { "cmps{b|}",         { Xb, Yb } },
1549   { "cmps{R|}",         { Xv, Yv } },
1550   /* a8 */
1551   { "testB",            { AL, Ib } },
1552   { "testS",            { eAX, Iv } },
1553   { "stosB",            { Ybr, AL } },
1554   { "stosS",            { Yvr, eAX } },
1555   { "lodsB",            { ALr, Xb } },
1556   { "lodsS",            { eAXr, Xv } },
1557   { "scasB",            { AL, Yb } },
1558   { "scasS",            { eAX, Yv } },
1559   /* b0 */
1560   { "movB",             { RMAL, Ib } },
1561   { "movB",             { RMCL, Ib } },
1562   { "movB",             { RMDL, Ib } },
1563   { "movB",             { RMBL, Ib } },
1564   { "movB",             { RMAH, Ib } },
1565   { "movB",             { RMCH, Ib } },
1566   { "movB",             { RMDH, Ib } },
1567   { "movB",             { RMBH, Ib } },
1568   /* b8 */
1569   { "mov%LV",           { RMeAX, Iv64 } },
1570   { "mov%LV",           { RMeCX, Iv64 } },
1571   { "mov%LV",           { RMeDX, Iv64 } },
1572   { "mov%LV",           { RMeBX, Iv64 } },
1573   { "mov%LV",           { RMeSP, Iv64 } },
1574   { "mov%LV",           { RMeBP, Iv64 } },
1575   { "mov%LV",           { RMeSI, Iv64 } },
1576   { "mov%LV",           { RMeDI, Iv64 } },
1577   /* c0 */
1578   { REG_TABLE (REG_C0) },
1579   { REG_TABLE (REG_C1) },
1580   { "retT",             { Iw } },
1581   { "retT",             { XX } },
1582   { X86_64_TABLE (X86_64_C4) },
1583   { X86_64_TABLE (X86_64_C5) },
1584   { REG_TABLE (REG_C6) },
1585   { REG_TABLE (REG_C7) },
1586   /* c8 */
1587   { "enterT",           { Iw, Ib } },
1588   { "leaveT",           { XX } },
1589   { "Jret{|f}P",        { Iw } },
1590   { "Jret{|f}P",        { XX } },
1591   { "int3",             { XX } },
1592   { "int",              { Ib } },
1593   { X86_64_TABLE (X86_64_CE) },
1594   { "iretP",            { XX } },
1595   /* d0 */
1596   { REG_TABLE (REG_D0) },
1597   { REG_TABLE (REG_D1) },
1598   { REG_TABLE (REG_D2) },
1599   { REG_TABLE (REG_D3) },
1600   { X86_64_TABLE (X86_64_D4) },
1601   { X86_64_TABLE (X86_64_D5) },
1602   { "(bad)",            { XX } },
1603   { "xlat",             { DSBX } },
1604   /* d8 */
1605   { FLOAT },
1606   { FLOAT },
1607   { FLOAT },
1608   { FLOAT },
1609   { FLOAT },
1610   { FLOAT },
1611   { FLOAT },
1612   { FLOAT },
1613   /* e0 */
1614   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1615   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1616   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1617   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1618   { "inB",              { AL, Ib } },
1619   { "inG",              { zAX, Ib } },
1620   { "outB",             { Ib, AL } },
1621   { "outG",             { Ib, zAX } },
1622   /* e8 */
1623   { "callT",            { Jv } },
1624   { "jmpT",             { Jv } },
1625   { X86_64_TABLE (X86_64_EA) },
1626   { "jmp",              { Jb } },
1627   { "inB",              { AL, indirDX } },
1628   { "inG",              { zAX, indirDX } },
1629   { "outB",             { indirDX, AL } },
1630   { "outG",             { indirDX, zAX } },
1631   /* f0 */
1632   { "(bad)",            { XX } },       /* lock prefix */
1633   { "icebp",            { XX } },
1634   { "(bad)",            { XX } },       /* repne */
1635   { "(bad)",            { XX } },       /* repz */
1636   { "hlt",              { XX } },
1637   { "cmc",              { XX } },
1638   { REG_TABLE (REG_F6) },
1639   { REG_TABLE (REG_F7) },
1640   /* f8 */
1641   { "clc",              { XX } },
1642   { "stc",              { XX } },
1643   { "cli",              { XX } },
1644   { "sti",              { XX } },
1645   { "cld",              { XX } },
1646   { "std",              { XX } },
1647   { REG_TABLE (REG_FE) },
1648   { REG_TABLE (REG_FF) },
1649 };
1650
1651 static const struct dis386 dis386_twobyte[] = {
1652   /* 00 */
1653   { REG_TABLE (REG_0F00 ) },
1654   { REG_TABLE (REG_0F01 ) },
1655   { "larS",             { Gv, Ew } },
1656   { "lslS",             { Gv, Ew } },
1657   { "(bad)",            { XX } },
1658   { "syscall",          { XX } },
1659   { "clts",             { XX } },
1660   { "sysretP",          { XX } },
1661   /* 08 */
1662   { "invd",             { XX } },
1663   { "wbinvd",           { XX } },
1664   { "(bad)",            { XX } },
1665   { "ud2a",             { XX } },
1666   { "(bad)",            { XX } },
1667   { REG_TABLE (REG_0F0D) },
1668   { "femms",            { XX } },
1669   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1670   /* 10 */
1671   { PREFIX_TABLE (PREFIX_0F10) },
1672   { PREFIX_TABLE (PREFIX_0F11) },
1673   { PREFIX_TABLE (PREFIX_0F12) },
1674   { MOD_TABLE (MOD_0F13) },
1675   { "unpcklpX",         { XM, EXx } },
1676   { "unpckhpX",         { XM, EXx } },
1677   { PREFIX_TABLE (PREFIX_0F16) },
1678   { MOD_TABLE (MOD_0F17) },
1679   /* 18 */
1680   { REG_TABLE (REG_0F18) },
1681   { "nopQ",             { Ev } },
1682   { "nopQ",             { Ev } },
1683   { "nopQ",             { Ev } },
1684   { "nopQ",             { Ev } },
1685   { "nopQ",             { Ev } },
1686   { "nopQ",             { Ev } },
1687   { "nopQ",             { Ev } },
1688   /* 20 */
1689   { MOD_TABLE (MOD_0F20) },
1690   { MOD_TABLE (MOD_0F21) },
1691   { MOD_TABLE (MOD_0F22) },
1692   { MOD_TABLE (MOD_0F23) },
1693   { MOD_TABLE (MOD_0F24) },
1694   { "(bad)",            { XX } },
1695   { MOD_TABLE (MOD_0F26) },
1696   { "(bad)",            { XX } },
1697   /* 28 */
1698   { "movapX",           { XM, EXx } },
1699   { "movapX",           { EXxS, XM } },
1700   { PREFIX_TABLE (PREFIX_0F2A) },
1701   { PREFIX_TABLE (PREFIX_0F2B) },
1702   { PREFIX_TABLE (PREFIX_0F2C) },
1703   { PREFIX_TABLE (PREFIX_0F2D) },
1704   { PREFIX_TABLE (PREFIX_0F2E) },
1705   { PREFIX_TABLE (PREFIX_0F2F) },
1706   /* 30 */
1707   { "wrmsr",            { XX } },
1708   { "rdtsc",            { XX } },
1709   { "rdmsr",            { XX } },
1710   { "rdpmc",            { XX } },
1711   { "sysenter",         { XX } },
1712   { "sysexit",          { XX } },
1713   { "(bad)",            { XX } },
1714   { "getsec",           { XX } },
1715   /* 38 */
1716   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1717   { "(bad)",            { XX } },
1718   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1719   { "(bad)",            { XX } },
1720   { "(bad)",            { XX } },
1721   { "(bad)",            { XX } },
1722   { "(bad)",            { XX } },
1723   { "(bad)",            { XX } },
1724   /* 40 */
1725   { "cmovoS",           { Gv, Ev } },
1726   { "cmovnoS",          { Gv, Ev } },
1727   { "cmovbS",           { Gv, Ev } },
1728   { "cmovaeS",          { Gv, Ev } },
1729   { "cmoveS",           { Gv, Ev } },
1730   { "cmovneS",          { Gv, Ev } },
1731   { "cmovbeS",          { Gv, Ev } },
1732   { "cmovaS",           { Gv, Ev } },
1733   /* 48 */
1734   { "cmovsS",           { Gv, Ev } },
1735   { "cmovnsS",          { Gv, Ev } },
1736   { "cmovpS",           { Gv, Ev } },
1737   { "cmovnpS",          { Gv, Ev } },
1738   { "cmovlS",           { Gv, Ev } },
1739   { "cmovgeS",          { Gv, Ev } },
1740   { "cmovleS",          { Gv, Ev } },
1741   { "cmovgS",           { Gv, Ev } },
1742   /* 50 */
1743   { MOD_TABLE (MOD_0F51) },
1744   { PREFIX_TABLE (PREFIX_0F51) },
1745   { PREFIX_TABLE (PREFIX_0F52) },
1746   { PREFIX_TABLE (PREFIX_0F53) },
1747   { "andpX",            { XM, EXx } },
1748   { "andnpX",           { XM, EXx } },
1749   { "orpX",             { XM, EXx } },
1750   { "xorpX",            { XM, EXx } },
1751   /* 58 */
1752   { PREFIX_TABLE (PREFIX_0F58) },
1753   { PREFIX_TABLE (PREFIX_0F59) },
1754   { PREFIX_TABLE (PREFIX_0F5A) },
1755   { PREFIX_TABLE (PREFIX_0F5B) },
1756   { PREFIX_TABLE (PREFIX_0F5C) },
1757   { PREFIX_TABLE (PREFIX_0F5D) },
1758   { PREFIX_TABLE (PREFIX_0F5E) },
1759   { PREFIX_TABLE (PREFIX_0F5F) },
1760   /* 60 */
1761   { PREFIX_TABLE (PREFIX_0F60) },
1762   { PREFIX_TABLE (PREFIX_0F61) },
1763   { PREFIX_TABLE (PREFIX_0F62) },
1764   { "packsswb",         { MX, EM } },
1765   { "pcmpgtb",          { MX, EM } },
1766   { "pcmpgtw",          { MX, EM } },
1767   { "pcmpgtd",          { MX, EM } },
1768   { "packuswb",         { MX, EM } },
1769   /* 68 */
1770   { "punpckhbw",        { MX, EM } },
1771   { "punpckhwd",        { MX, EM } },
1772   { "punpckhdq",        { MX, EM } },
1773   { "packssdw",         { MX, EM } },
1774   { PREFIX_TABLE (PREFIX_0F6C) },
1775   { PREFIX_TABLE (PREFIX_0F6D) },
1776   { "movK",             { MX, Edq } },
1777   { PREFIX_TABLE (PREFIX_0F6F) },
1778   /* 70 */
1779   { PREFIX_TABLE (PREFIX_0F70) },
1780   { REG_TABLE (REG_0F71) },
1781   { REG_TABLE (REG_0F72) },
1782   { REG_TABLE (REG_0F73) },
1783   { "pcmpeqb",          { MX, EM } },
1784   { "pcmpeqw",          { MX, EM } },
1785   { "pcmpeqd",          { MX, EM } },
1786   { "emms",             { XX } },
1787   /* 78 */
1788   { PREFIX_TABLE (PREFIX_0F78) },
1789   { PREFIX_TABLE (PREFIX_0F79) },
1790   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1791   { "(bad)",            { XX } },
1792   { PREFIX_TABLE (PREFIX_0F7C) },
1793   { PREFIX_TABLE (PREFIX_0F7D) },
1794   { PREFIX_TABLE (PREFIX_0F7E) },
1795   { PREFIX_TABLE (PREFIX_0F7F) },
1796   /* 80 */
1797   { "joH",              { Jv, XX, cond_jump_flag } },
1798   { "jnoH",             { Jv, XX, cond_jump_flag } },
1799   { "jbH",              { Jv, XX, cond_jump_flag } },
1800   { "jaeH",             { Jv, XX, cond_jump_flag } },
1801   { "jeH",              { Jv, XX, cond_jump_flag } },
1802   { "jneH",             { Jv, XX, cond_jump_flag } },
1803   { "jbeH",             { Jv, XX, cond_jump_flag } },
1804   { "jaH",              { Jv, XX, cond_jump_flag } },
1805   /* 88 */
1806   { "jsH",              { Jv, XX, cond_jump_flag } },
1807   { "jnsH",             { Jv, XX, cond_jump_flag } },
1808   { "jpH",              { Jv, XX, cond_jump_flag } },
1809   { "jnpH",             { Jv, XX, cond_jump_flag } },
1810   { "jlH",              { Jv, XX, cond_jump_flag } },
1811   { "jgeH",             { Jv, XX, cond_jump_flag } },
1812   { "jleH",             { Jv, XX, cond_jump_flag } },
1813   { "jgH",              { Jv, XX, cond_jump_flag } },
1814   /* 90 */
1815   { "seto",             { Eb } },
1816   { "setno",            { Eb } },
1817   { "setb",             { Eb } },
1818   { "setae",            { Eb } },
1819   { "sete",             { Eb } },
1820   { "setne",            { Eb } },
1821   { "setbe",            { Eb } },
1822   { "seta",             { Eb } },
1823   /* 98 */
1824   { "sets",             { Eb } },
1825   { "setns",            { Eb } },
1826   { "setp",             { Eb } },
1827   { "setnp",            { Eb } },
1828   { "setl",             { Eb } },
1829   { "setge",            { Eb } },
1830   { "setle",            { Eb } },
1831   { "setg",             { Eb } },
1832   /* a0 */
1833   { "pushT",            { fs } },
1834   { "popT",             { fs } },
1835   { "cpuid",            { XX } },
1836   { "btS",              { Ev, Gv } },
1837   { "shldS",            { Ev, Gv, Ib } },
1838   { "shldS",            { Ev, Gv, CL } },
1839   { REG_TABLE (REG_0FA6) },
1840   { REG_TABLE (REG_0FA7) },
1841   /* a8 */
1842   { "pushT",            { gs } },
1843   { "popT",             { gs } },
1844   { "rsm",              { XX } },
1845   { "btsS",             { Ev, Gv } },
1846   { "shrdS",            { Ev, Gv, Ib } },
1847   { "shrdS",            { Ev, Gv, CL } },
1848   { REG_TABLE (REG_0FAE) },
1849   { "imulS",            { Gv, Ev } },
1850   /* b0 */
1851   { "cmpxchgB",         { Eb, Gb } },
1852   { "cmpxchgS",         { Ev, Gv } },
1853   { MOD_TABLE (MOD_0FB2) },
1854   { "btrS",             { Ev, Gv } },
1855   { MOD_TABLE (MOD_0FB4) },
1856   { MOD_TABLE (MOD_0FB5) },
1857   { "movz{bR|x}",       { Gv, Eb } },
1858   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1859   /* b8 */
1860   { PREFIX_TABLE (PREFIX_0FB8) },
1861   { "ud2b",             { XX } },
1862   { REG_TABLE (REG_0FBA) },
1863   { "btcS",             { Ev, Gv } },
1864   { "bsfS",             { Gv, Ev } },
1865   { PREFIX_TABLE (PREFIX_0FBD) },
1866   { "movs{bR|x}",       { Gv, Eb } },
1867   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1868   /* c0 */
1869   { "xaddB",            { Eb, Gb } },
1870   { "xaddS",            { Ev, Gv } },
1871   { PREFIX_TABLE (PREFIX_0FC2) },
1872   { PREFIX_TABLE (PREFIX_0FC3) },
1873   { "pinsrw",           { MX, Edqw, Ib } },
1874   { "pextrw",           { Gdq, MS, Ib } },
1875   { "shufpX",           { XM, EXx, Ib } },
1876   { REG_TABLE (REG_0FC7) },
1877   /* c8 */
1878   { "bswap",            { RMeAX } },
1879   { "bswap",            { RMeCX } },
1880   { "bswap",            { RMeDX } },
1881   { "bswap",            { RMeBX } },
1882   { "bswap",            { RMeSP } },
1883   { "bswap",            { RMeBP } },
1884   { "bswap",            { RMeSI } },
1885   { "bswap",            { RMeDI } },
1886   /* d0 */
1887   { PREFIX_TABLE (PREFIX_0FD0) },
1888   { "psrlw",            { MX, EM } },
1889   { "psrld",            { MX, EM } },
1890   { "psrlq",            { MX, EM } },
1891   { "paddq",            { MX, EM } },
1892   { "pmullw",           { MX, EM } },
1893   { PREFIX_TABLE (PREFIX_0FD6) },
1894   { MOD_TABLE (MOD_0FD7) },
1895   /* d8 */
1896   { "psubusb",          { MX, EM } },
1897   { "psubusw",          { MX, EM } },
1898   { "pminub",           { MX, EM } },
1899   { "pand",             { MX, EM } },
1900   { "paddusb",          { MX, EM } },
1901   { "paddusw",          { MX, EM } },
1902   { "pmaxub",           { MX, EM } },
1903   { "pandn",            { MX, EM } },
1904   /* e0 */
1905   { "pavgb",            { MX, EM } },
1906   { "psraw",            { MX, EM } },
1907   { "psrad",            { MX, EM } },
1908   { "pavgw",            { MX, EM } },
1909   { "pmulhuw",          { MX, EM } },
1910   { "pmulhw",           { MX, EM } },
1911   { PREFIX_TABLE (PREFIX_0FE6) },
1912   { PREFIX_TABLE (PREFIX_0FE7) },
1913   /* e8 */
1914   { "psubsb",           { MX, EM } },
1915   { "psubsw",           { MX, EM } },
1916   { "pminsw",           { MX, EM } },
1917   { "por",              { MX, EM } },
1918   { "paddsb",           { MX, EM } },
1919   { "paddsw",           { MX, EM } },
1920   { "pmaxsw",           { MX, EM } },
1921   { "pxor",             { MX, EM } },
1922   /* f0 */
1923   { PREFIX_TABLE (PREFIX_0FF0) },
1924   { "psllw",            { MX, EM } },
1925   { "pslld",            { MX, EM } },
1926   { "psllq",            { MX, EM } },
1927   { "pmuludq",          { MX, EM } },
1928   { "pmaddwd",          { MX, EM } },
1929   { "psadbw",           { MX, EM } },
1930   { PREFIX_TABLE (PREFIX_0FF7) },
1931   /* f8 */
1932   { "psubb",            { MX, EM } },
1933   { "psubw",            { MX, EM } },
1934   { "psubd",            { MX, EM } },
1935   { "psubq",            { MX, EM } },
1936   { "paddb",            { MX, EM } },
1937   { "paddw",            { MX, EM } },
1938   { "paddd",            { MX, EM } },
1939   { "(bad)",            { XX } },
1940 };
1941
1942 static const unsigned char onebyte_has_modrm[256] = {
1943   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1944   /*       -------------------------------        */
1945   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1946   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1947   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1948   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1949   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1950   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1951   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1952   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1953   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1954   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1955   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1956   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1957   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1958   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1959   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1960   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1961   /*       -------------------------------        */
1962   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1963 };
1964
1965 static const unsigned char twobyte_has_modrm[256] = {
1966   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1967   /*       -------------------------------        */
1968   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1969   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1970   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1971   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1972   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1973   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1974   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1975   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1976   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1977   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1978   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1979   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1980   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1981   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1982   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1983   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1984   /*       -------------------------------        */
1985   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1986 };
1987
1988 static char obuf[100];
1989 static char *obufp;
1990 static char *mnemonicendp;
1991 static char scratchbuf[100];
1992 static unsigned char *start_codep;
1993 static unsigned char *insn_codep;
1994 static unsigned char *codep;
1995 static const char *lock_prefix;
1996 static const char *data_prefix;
1997 static const char *addr_prefix;
1998 static const char *repz_prefix;
1999 static const char *repnz_prefix;
2000 static disassemble_info *the_info;
2001 static struct
2002   {
2003     int mod;
2004     int reg;
2005     int rm;
2006   }
2007 modrm;
2008 static unsigned char need_modrm;
2009 static struct
2010   {
2011     int register_specifier;
2012     int length;
2013     int prefix;
2014     int w;
2015   }
2016 vex;
2017 static unsigned char need_vex;
2018 static unsigned char need_vex_reg;
2019 static unsigned char vex_w_done;
2020
2021 struct op
2022   {
2023     const char *name;
2024     unsigned int len;
2025   };
2026
2027 /* If we are accessing mod/rm/reg without need_modrm set, then the
2028    values are stale.  Hitting this abort likely indicates that you
2029    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2030 #define MODRM_CHECK  if (!need_modrm) abort ()
2031
2032 static const char **names64;
2033 static const char **names32;
2034 static const char **names16;
2035 static const char **names8;
2036 static const char **names8rex;
2037 static const char **names_seg;
2038 static const char *index64;
2039 static const char *index32;
2040 static const char **index16;
2041
2042 static const char *intel_names64[] = {
2043   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2044   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2045 };
2046 static const char *intel_names32[] = {
2047   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2048   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2049 };
2050 static const char *intel_names16[] = {
2051   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2052   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2053 };
2054 static const char *intel_names8[] = {
2055   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2056 };
2057 static const char *intel_names8rex[] = {
2058   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2059   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2060 };
2061 static const char *intel_names_seg[] = {
2062   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2063 };
2064 static const char *intel_index64 = "riz";
2065 static const char *intel_index32 = "eiz";
2066 static const char *intel_index16[] = {
2067   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2068 };
2069
2070 static const char *att_names64[] = {
2071   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2072   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2073 };
2074 static const char *att_names32[] = {
2075   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2076   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2077 };
2078 static const char *att_names16[] = {
2079   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2080   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2081 };
2082 static const char *att_names8[] = {
2083   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2084 };
2085 static const char *att_names8rex[] = {
2086   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2087   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2088 };
2089 static const char *att_names_seg[] = {
2090   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2091 };
2092 static const char *att_index64 = "%riz";
2093 static const char *att_index32 = "%eiz";
2094 static const char *att_index16[] = {
2095   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2096 };
2097
2098 static const struct dis386 reg_table[][8] = {
2099   /* REG_80 */
2100   {
2101     { "addA",   { Eb, Ib } },
2102     { "orA",    { Eb, Ib } },
2103     { "adcA",   { Eb, Ib } },
2104     { "sbbA",   { Eb, Ib } },
2105     { "andA",   { Eb, Ib } },
2106     { "subA",   { Eb, Ib } },
2107     { "xorA",   { Eb, Ib } },
2108     { "cmpA",   { Eb, Ib } },
2109   },
2110   /* REG_81 */
2111   {
2112     { "addQ",   { Ev, Iv } },
2113     { "orQ",    { Ev, Iv } },
2114     { "adcQ",   { Ev, Iv } },
2115     { "sbbQ",   { Ev, Iv } },
2116     { "andQ",   { Ev, Iv } },
2117     { "subQ",   { Ev, Iv } },
2118     { "xorQ",   { Ev, Iv } },
2119     { "cmpQ",   { Ev, Iv } },
2120   },
2121   /* REG_82 */
2122   {
2123     { "addQ",   { Ev, sIb } },
2124     { "orQ",    { Ev, sIb } },
2125     { "adcQ",   { Ev, sIb } },
2126     { "sbbQ",   { Ev, sIb } },
2127     { "andQ",   { Ev, sIb } },
2128     { "subQ",   { Ev, sIb } },
2129     { "xorQ",   { Ev, sIb } },
2130     { "cmpQ",   { Ev, sIb } },
2131   },
2132   /* REG_8F */
2133   {
2134     { "popU",   { stackEv } },
2135     { "(bad)",  { XX } },
2136     { "(bad)",  { XX } },
2137     { "(bad)",  { XX } },
2138     { "(bad)",  { XX } },
2139     { XOP_8F_TABLE (XOP_09) },
2140     { "(bad)",  { XX } },
2141     { "(bad)",  { XX } },
2142   },
2143   /* REG_C0 */
2144   {
2145     { "rolA",   { Eb, Ib } },
2146     { "rorA",   { Eb, Ib } },
2147     { "rclA",   { Eb, Ib } },
2148     { "rcrA",   { Eb, Ib } },
2149     { "shlA",   { Eb, Ib } },
2150     { "shrA",   { Eb, Ib } },
2151     { "(bad)",  { XX } },
2152     { "sarA",   { Eb, Ib } },
2153   },
2154   /* REG_C1 */
2155   {
2156     { "rolQ",   { Ev, Ib } },
2157     { "rorQ",   { Ev, Ib } },
2158     { "rclQ",   { Ev, Ib } },
2159     { "rcrQ",   { Ev, Ib } },
2160     { "shlQ",   { Ev, Ib } },
2161     { "shrQ",   { Ev, Ib } },
2162     { "(bad)",  { XX } },
2163     { "sarQ",   { Ev, Ib } },
2164   },
2165   /* REG_C6 */
2166   {
2167     { "movA",   { Eb, Ib } },
2168     { "(bad)",  { XX } },
2169     { "(bad)",  { XX } },
2170     { "(bad)",  { XX } },
2171     { "(bad)",  { XX } },
2172     { "(bad)",  { XX } },
2173     { "(bad)",  { XX } },
2174     { "(bad)",  { XX } },
2175   },
2176   /* REG_C7 */
2177   {
2178     { "movQ",   { Ev, Iv } },
2179     { "(bad)",  { XX } },
2180     { "(bad)",  { XX } },
2181     { "(bad)",  { XX } },
2182     { "(bad)",  { XX } },
2183     { "(bad)",  { XX } },
2184     { "(bad)",  { XX } },
2185     { "(bad)",  { XX } },
2186   },
2187   /* REG_D0 */
2188   {
2189     { "rolA",   { Eb, I1 } },
2190     { "rorA",   { Eb, I1 } },
2191     { "rclA",   { Eb, I1 } },
2192     { "rcrA",   { Eb, I1 } },
2193     { "shlA",   { Eb, I1 } },
2194     { "shrA",   { Eb, I1 } },
2195     { "(bad)",  { XX } },
2196     { "sarA",   { Eb, I1 } },
2197   },
2198   /* REG_D1 */
2199   {
2200     { "rolQ",   { Ev, I1 } },
2201     { "rorQ",   { Ev, I1 } },
2202     { "rclQ",   { Ev, I1 } },
2203     { "rcrQ",   { Ev, I1 } },
2204     { "shlQ",   { Ev, I1 } },
2205     { "shrQ",   { Ev, I1 } },
2206     { "(bad)",  { XX } },
2207     { "sarQ",   { Ev, I1 } },
2208   },
2209   /* REG_D2 */
2210   {
2211     { "rolA",   { Eb, CL } },
2212     { "rorA",   { Eb, CL } },
2213     { "rclA",   { Eb, CL } },
2214     { "rcrA",   { Eb, CL } },
2215     { "shlA",   { Eb, CL } },
2216     { "shrA",   { Eb, CL } },
2217     { "(bad)",  { XX } },
2218     { "sarA",   { Eb, CL } },
2219   },
2220   /* REG_D3 */
2221   {
2222     { "rolQ",   { Ev, CL } },
2223     { "rorQ",   { Ev, CL } },
2224     { "rclQ",   { Ev, CL } },
2225     { "rcrQ",   { Ev, CL } },
2226     { "shlQ",   { Ev, CL } },
2227     { "shrQ",   { Ev, CL } },
2228     { "(bad)",  { XX } },
2229     { "sarQ",   { Ev, CL } },
2230   },
2231   /* REG_F6 */
2232   {
2233     { "testA",  { Eb, Ib } },
2234     { "(bad)",  { XX } },
2235     { "notA",   { Eb } },
2236     { "negA",   { Eb } },
2237     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2238     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2239     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2240     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2241   },
2242   /* REG_F7 */
2243   {
2244     { "testQ",  { Ev, Iv } },
2245     { "(bad)",  { XX } },
2246     { "notQ",   { Ev } },
2247     { "negQ",   { Ev } },
2248     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2249     { "imulQ",  { Ev } },
2250     { "divQ",   { Ev } },
2251     { "idivQ",  { Ev } },
2252   },
2253   /* REG_FE */
2254   {
2255     { "incA",   { Eb } },
2256     { "decA",   { Eb } },
2257     { "(bad)",  { XX } },
2258     { "(bad)",  { XX } },
2259     { "(bad)",  { XX } },
2260     { "(bad)",  { XX } },
2261     { "(bad)",  { XX } },
2262     { "(bad)",  { XX } },
2263   },
2264   /* REG_FF */
2265   {
2266     { "incQ",   { Ev } },
2267     { "decQ",   { Ev } },
2268     { "callT",  { indirEv } },
2269     { "JcallT", { indirEp } },
2270     { "jmpT",   { indirEv } },
2271     { "JjmpT",  { indirEp } },
2272     { "pushU",  { stackEv } },
2273     { "(bad)",  { XX } },
2274   },
2275   /* REG_0F00 */
2276   {
2277     { "sldtD",  { Sv } },
2278     { "strD",   { Sv } },
2279     { "lldt",   { Ew } },
2280     { "ltr",    { Ew } },
2281     { "verr",   { Ew } },
2282     { "verw",   { Ew } },
2283     { "(bad)",  { XX } },
2284     { "(bad)",  { XX } },
2285   },
2286   /* REG_0F01 */
2287   {
2288     { MOD_TABLE (MOD_0F01_REG_0) },
2289     { MOD_TABLE (MOD_0F01_REG_1) },
2290     { MOD_TABLE (MOD_0F01_REG_2) },
2291     { MOD_TABLE (MOD_0F01_REG_3) },
2292     { "smswD",  { Sv } },
2293     { "(bad)",  { XX } },
2294     { "lmsw",   { Ew } },
2295     { MOD_TABLE (MOD_0F01_REG_7) },
2296   },
2297   /* REG_0F0D */
2298   {
2299     { "prefetch",       { Eb } },
2300     { "prefetchw",      { Eb } },
2301     { "(bad)",          { XX } },
2302     { "(bad)",          { XX } },
2303     { "(bad)",          { XX } },
2304     { "(bad)",          { XX } },
2305     { "(bad)",          { XX } },
2306     { "(bad)",          { XX } },
2307   },
2308   /* REG_0F18 */
2309   {
2310     { MOD_TABLE (MOD_0F18_REG_0) },
2311     { MOD_TABLE (MOD_0F18_REG_1) },
2312     { MOD_TABLE (MOD_0F18_REG_2) },
2313     { MOD_TABLE (MOD_0F18_REG_3) },
2314     { "(bad)",  { XX } },
2315     { "(bad)",  { XX } },
2316     { "(bad)",  { XX } },
2317     { "(bad)",  { XX } },
2318   },
2319   /* REG_0F71 */
2320   {
2321     { "(bad)",  { XX } },
2322     { "(bad)",  { XX } },
2323     { MOD_TABLE (MOD_0F71_REG_2) },
2324     { "(bad)",  { XX } },
2325     { MOD_TABLE (MOD_0F71_REG_4) },
2326     { "(bad)",  { XX } },
2327     { MOD_TABLE (MOD_0F71_REG_6) },
2328     { "(bad)",  { XX } },
2329   },
2330   /* REG_0F72 */
2331   {
2332     { "(bad)",  { XX } },
2333     { "(bad)",  { XX } },
2334     { MOD_TABLE (MOD_0F72_REG_2) },
2335     { "(bad)",  { XX } },
2336     { MOD_TABLE (MOD_0F72_REG_4) },
2337     { "(bad)",  { XX } },
2338     { MOD_TABLE (MOD_0F72_REG_6) },
2339     { "(bad)",  { XX } },
2340   },
2341   /* REG_0F73 */
2342   {
2343     { "(bad)",  { XX } },
2344     { "(bad)",  { XX } },
2345     { MOD_TABLE (MOD_0F73_REG_2) },
2346     { MOD_TABLE (MOD_0F73_REG_3) },
2347     { "(bad)",  { XX } },
2348     { "(bad)",  { XX } },
2349     { MOD_TABLE (MOD_0F73_REG_6) },
2350     { MOD_TABLE (MOD_0F73_REG_7) },
2351   },
2352   /* REG_0FA6 */
2353   {
2354     { "montmul",        { { OP_0f07, 0 } } },
2355     { "xsha1",          { { OP_0f07, 0 } } },
2356     { "xsha256",        { { OP_0f07, 0 } } },
2357     { "(bad)",          { { OP_0f07, 0 } } },
2358     { "(bad)",          { { OP_0f07, 0 } } },
2359     { "(bad)",          { { OP_0f07, 0 } } },
2360     { "(bad)",          { { OP_0f07, 0 } } },
2361     { "(bad)",          { { OP_0f07, 0 } } },
2362   },
2363   /* REG_0FA7 */
2364   {
2365     { "xstore-rng",     { { OP_0f07, 0 } } },
2366     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2367     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2368     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2369     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2370     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2371     { "(bad)",          { { OP_0f07, 0 } } },
2372     { "(bad)",          { { OP_0f07, 0 } } },
2373   },
2374   /* REG_0FAE */
2375   {
2376     { MOD_TABLE (MOD_0FAE_REG_0) },
2377     { MOD_TABLE (MOD_0FAE_REG_1) },
2378     { MOD_TABLE (MOD_0FAE_REG_2) },
2379     { MOD_TABLE (MOD_0FAE_REG_3) },
2380     { MOD_TABLE (MOD_0FAE_REG_4) },
2381     { MOD_TABLE (MOD_0FAE_REG_5) },
2382     { MOD_TABLE (MOD_0FAE_REG_6) },
2383     { MOD_TABLE (MOD_0FAE_REG_7) },
2384   },
2385   /* REG_0FBA */
2386   {
2387     { "(bad)",  { XX } },
2388     { "(bad)",  { XX } },
2389     { "(bad)",  { XX } },
2390     { "(bad)",  { XX } },
2391     { "btQ",    { Ev, Ib } },
2392     { "btsQ",   { Ev, Ib } },
2393     { "btrQ",   { Ev, Ib } },
2394     { "btcQ",   { Ev, Ib } },
2395   },
2396   /* REG_0FC7 */
2397   {
2398     { "(bad)",  { XX } },
2399     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2400     { "(bad)",  { XX } },
2401     { "(bad)",  { XX } },
2402     { "(bad)",  { XX } },
2403     { "(bad)",  { XX } },
2404     { MOD_TABLE (MOD_0FC7_REG_6) },
2405     { MOD_TABLE (MOD_0FC7_REG_7) },
2406   },
2407   /* REG_VEX_71 */
2408   {
2409     { "(bad)",  { XX } },
2410     { "(bad)",  { XX } },
2411     { MOD_TABLE (MOD_VEX_71_REG_2) },
2412     { "(bad)",  { XX } },
2413     { MOD_TABLE (MOD_VEX_71_REG_4) },
2414     { "(bad)",  { XX } },
2415     { MOD_TABLE (MOD_VEX_71_REG_6) },
2416     { "(bad)",  { XX } },
2417   },
2418   /* REG_VEX_72 */
2419   {
2420     { "(bad)",  { XX } },
2421     { "(bad)",  { XX } },
2422     { MOD_TABLE (MOD_VEX_72_REG_2) },
2423     { "(bad)",  { XX } },
2424     { MOD_TABLE (MOD_VEX_72_REG_4) },
2425     { "(bad)",  { XX } },
2426     { MOD_TABLE (MOD_VEX_72_REG_6) },
2427     { "(bad)",  { XX } },
2428   },
2429   /* REG_VEX_73 */
2430   {
2431     { "(bad)",  { XX } },
2432     { "(bad)",  { XX } },
2433     { MOD_TABLE (MOD_VEX_73_REG_2) },
2434     { MOD_TABLE (MOD_VEX_73_REG_3) },
2435     { "(bad)",  { XX } },
2436     { "(bad)",  { XX } },
2437     { MOD_TABLE (MOD_VEX_73_REG_6) },
2438     { MOD_TABLE (MOD_VEX_73_REG_7) },
2439   },
2440   /* REG_VEX_AE */
2441   {
2442     { "(bad)",  { XX } },
2443     { "(bad)",  { XX } },
2444     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2445     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2446     { "(bad)",  { XX } },
2447     { "(bad)",  { XX } },
2448     { "(bad)",  { XX } },
2449     { "(bad)",  { XX } },
2450   },
2451   /* REG_XOP_LWPCB */
2452   {
2453     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2454     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2455     { "(bad)",  { XX } },
2456     { "(bad)",  { XX } },
2457     { "(bad)",  { XX } },
2458     { "(bad)",  { XX } },
2459     { "(bad)",  { XX } },
2460     { "(bad)",  { XX } },
2461   },
2462   /* REG_XOP_LWP */
2463   {
2464     { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2465     { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2466     { "(bad)",  { XX } },
2467     { "(bad)",  { XX } },
2468     { "(bad)",  { XX } },
2469     { "(bad)",  { XX } },
2470     { "(bad)",  { XX } },
2471     { "(bad)",  { XX } },
2472   },
2473 };
2474
2475 static const struct dis386 prefix_table[][4] = {
2476   /* PREFIX_90 */
2477   {
2478     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2479     { "pause", { XX } },
2480     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2481     { "(bad)", { XX } },
2482   },
2483
2484   /* PREFIX_0F10 */
2485   {
2486     { "movups", { XM, EXx } },
2487     { "movss",  { XM, EXd } },
2488     { "movupd", { XM, EXx } },
2489     { "movsd",  { XM, EXq } },
2490   },
2491
2492   /* PREFIX_0F11 */
2493   {
2494     { "movups", { EXxS, XM } },
2495     { "movss",  { EXdS, XM } },
2496     { "movupd", { EXxS, XM } },
2497     { "movsd",  { EXqS, XM } },
2498   },
2499
2500   /* PREFIX_0F12 */
2501   {
2502     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2503     { "movsldup", { XM, EXx } },
2504     { "movlpd", { XM, EXq } },
2505     { "movddup", { XM, EXq } },
2506   },
2507
2508   /* PREFIX_0F16 */
2509   {
2510     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2511     { "movshdup", { XM, EXx } },
2512     { "movhpd", { XM, EXq } },
2513     { "(bad)",  { XX } },
2514   },
2515
2516   /* PREFIX_0F2A */
2517   {
2518     { "cvtpi2ps", { XM, EMCq } },
2519     { "cvtsi2ss%LQ", { XM, Ev } },
2520     { "cvtpi2pd", { XM, EMCq } },
2521     { "cvtsi2sd%LQ", { XM, Ev } },
2522   },
2523
2524   /* PREFIX_0F2B */
2525   {
2526     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2527     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2528     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2529     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2530   },
2531
2532   /* PREFIX_0F2C */
2533   {
2534     { "cvttps2pi", { MXC, EXq } },
2535     { "cvttss2siY", { Gv, EXd } },
2536     { "cvttpd2pi", { MXC, EXx } },
2537     { "cvttsd2siY", { Gv, EXq } },
2538   },
2539
2540   /* PREFIX_0F2D */
2541   {
2542     { "cvtps2pi", { MXC, EXq } },
2543     { "cvtss2siY", { Gv, EXd } },
2544     { "cvtpd2pi", { MXC, EXx } },
2545     { "cvtsd2siY", { Gv, EXq } },
2546   },
2547
2548   /* PREFIX_0F2E */
2549   {
2550     { "ucomiss",{ XM, EXd } },
2551     { "(bad)",  { XX } },
2552     { "ucomisd",{ XM, EXq } },
2553     { "(bad)",  { XX } },
2554   },
2555
2556   /* PREFIX_0F2F */
2557   {
2558     { "comiss", { XM, EXd } },
2559     { "(bad)",  { XX } },
2560     { "comisd", { XM, EXq } },
2561     { "(bad)",  { XX } },
2562   },
2563
2564   /* PREFIX_0F51 */
2565   {
2566     { "sqrtps", { XM, EXx } },
2567     { "sqrtss", { XM, EXd } },
2568     { "sqrtpd", { XM, EXx } },
2569     { "sqrtsd", { XM, EXq } },
2570   },
2571
2572   /* PREFIX_0F52 */
2573   {
2574     { "rsqrtps",{ XM, EXx } },
2575     { "rsqrtss",{ XM, EXd } },
2576     { "(bad)",  { XX } },
2577     { "(bad)",  { XX } },
2578   },
2579
2580   /* PREFIX_0F53 */
2581   {
2582     { "rcpps",  { XM, EXx } },
2583     { "rcpss",  { XM, EXd } },
2584     { "(bad)",  { XX } },
2585     { "(bad)",  { XX } },
2586   },
2587
2588   /* PREFIX_0F58 */
2589   {
2590     { "addps", { XM, EXx } },
2591     { "addss", { XM, EXd } },
2592     { "addpd", { XM, EXx } },
2593     { "addsd", { XM, EXq } },
2594   },
2595
2596   /* PREFIX_0F59 */
2597   {
2598     { "mulps",  { XM, EXx } },
2599     { "mulss",  { XM, EXd } },
2600     { "mulpd",  { XM, EXx } },
2601     { "mulsd",  { XM, EXq } },
2602   },
2603
2604   /* PREFIX_0F5A */
2605   {
2606     { "cvtps2pd", { XM, EXq } },
2607     { "cvtss2sd", { XM, EXd } },
2608     { "cvtpd2ps", { XM, EXx } },
2609     { "cvtsd2ss", { XM, EXq } },
2610   },
2611
2612   /* PREFIX_0F5B */
2613   {
2614     { "cvtdq2ps", { XM, EXx } },
2615     { "cvttps2dq", { XM, EXx } },
2616     { "cvtps2dq", { XM, EXx } },
2617     { "(bad)",  { XX } },
2618   },
2619
2620   /* PREFIX_0F5C */
2621   {
2622     { "subps",  { XM, EXx } },
2623     { "subss",  { XM, EXd } },
2624     { "subpd",  { XM, EXx } },
2625     { "subsd",  { XM, EXq } },
2626   },
2627
2628   /* PREFIX_0F5D */
2629   {
2630     { "minps",  { XM, EXx } },
2631     { "minss",  { XM, EXd } },
2632     { "minpd",  { XM, EXx } },
2633     { "minsd",  { XM, EXq } },
2634   },
2635
2636   /* PREFIX_0F5E */
2637   {
2638     { "divps",  { XM, EXx } },
2639     { "divss",  { XM, EXd } },
2640     { "divpd",  { XM, EXx } },
2641     { "divsd",  { XM, EXq } },
2642   },
2643
2644   /* PREFIX_0F5F */
2645   {
2646     { "maxps",  { XM, EXx } },
2647     { "maxss",  { XM, EXd } },
2648     { "maxpd",  { XM, EXx } },
2649     { "maxsd",  { XM, EXq } },
2650   },
2651
2652   /* PREFIX_0F60 */
2653   {
2654     { "punpcklbw",{ MX, EMd } },
2655     { "(bad)",  { XX } },
2656     { "punpcklbw",{ MX, EMx } },
2657     { "(bad)",  { XX } },
2658   },
2659
2660   /* PREFIX_0F61 */
2661   {
2662     { "punpcklwd",{ MX, EMd } },
2663     { "(bad)",  { XX } },
2664     { "punpcklwd",{ MX, EMx } },
2665     { "(bad)",  { XX } },
2666   },
2667
2668   /* PREFIX_0F62 */
2669   {
2670     { "punpckldq",{ MX, EMd } },
2671     { "(bad)",  { XX } },
2672     { "punpckldq",{ MX, EMx } },
2673     { "(bad)",  { XX } },
2674   },
2675
2676   /* PREFIX_0F6C */
2677   {
2678     { "(bad)",  { XX } },
2679     { "(bad)",  { XX } },
2680     { "punpcklqdq", { XM, EXx } },
2681     { "(bad)",  { XX } },
2682   },
2683
2684   /* PREFIX_0F6D */
2685   {
2686     { "(bad)",  { XX } },
2687     { "(bad)",  { XX } },
2688     { "punpckhqdq", { XM, EXx } },
2689     { "(bad)",  { XX } },
2690   },
2691
2692   /* PREFIX_0F6F */
2693   {
2694     { "movq",   { MX, EM } },
2695     { "movdqu", { XM, EXx } },
2696     { "movdqa", { XM, EXx } },
2697     { "(bad)",  { XX } },
2698   },
2699
2700   /* PREFIX_0F70 */
2701   {
2702     { "pshufw", { MX, EM, Ib } },
2703     { "pshufhw",{ XM, EXx, Ib } },
2704     { "pshufd", { XM, EXx, Ib } },
2705     { "pshuflw",{ XM, EXx, Ib } },
2706   },
2707
2708   /* PREFIX_0F73_REG_3 */
2709   {
2710     { "(bad)",  { XX } },
2711     { "(bad)",  { XX } },
2712     { "psrldq", { XS, Ib } },
2713     { "(bad)",  { XX } },
2714   },
2715
2716   /* PREFIX_0F73_REG_7 */
2717   {
2718     { "(bad)",  { XX } },
2719     { "(bad)",  { XX } },
2720     { "pslldq", { XS, Ib } },
2721     { "(bad)",  { XX } },
2722   },
2723
2724   /* PREFIX_0F78 */
2725   {
2726     {"vmread",  { Em, Gm } },
2727     {"(bad)",   { XX } },
2728     {"extrq",   { XS, Ib, Ib } },
2729     {"insertq", { XM, XS, Ib, Ib } },
2730   },
2731
2732   /* PREFIX_0F79 */
2733   {
2734     {"vmwrite", { Gm, Em } },
2735     {"(bad)",   { XX } },
2736     {"extrq",   { XM, XS } },
2737     {"insertq", { XM, XS } },
2738   },
2739
2740   /* PREFIX_0F7C */
2741   {
2742     { "(bad)",  { XX } },
2743     { "(bad)",  { XX } },
2744     { "haddpd", { XM, EXx } },
2745     { "haddps", { XM, EXx } },
2746   },
2747
2748   /* PREFIX_0F7D */
2749   {
2750     { "(bad)",  { XX } },
2751     { "(bad)",  { XX } },
2752     { "hsubpd", { XM, EXx } },
2753     { "hsubps", { XM, EXx } },
2754   },
2755
2756   /* PREFIX_0F7E */
2757   {
2758     { "movK",   { Edq, MX } },
2759     { "movq",   { XM, EXq } },
2760     { "movK",   { Edq, XM } },
2761     { "(bad)",  { XX } },
2762   },
2763
2764   /* PREFIX_0F7F */
2765   {
2766     { "movq",   { EMS, MX } },
2767     { "movdqu", { EXxS, XM } },
2768     { "movdqa", { EXxS, XM } },
2769     { "(bad)",  { XX } },
2770   },
2771
2772   /* PREFIX_0FB8 */
2773   {
2774     { "(bad)", { XX } },
2775     { "popcntS", { Gv, Ev } },
2776     { "(bad)", { XX } },
2777     { "(bad)", { XX } },
2778   },
2779
2780   /* PREFIX_0FBD */
2781   {
2782     { "bsrS",   { Gv, Ev } },
2783     { "lzcntS", { Gv, Ev } },
2784     { "bsrS",   { Gv, Ev } },
2785     { "(bad)",  { XX } },
2786   },
2787
2788   /* PREFIX_0FC2 */
2789   {
2790     { "cmpps",  { XM, EXx, CMP } },
2791     { "cmpss",  { XM, EXd, CMP } },
2792     { "cmppd",  { XM, EXx, CMP } },
2793     { "cmpsd",  { XM, EXq, CMP } },
2794   },
2795
2796   /* PREFIX_0FC3 */
2797   {
2798     { "movntiS", { Ma, Gv } },
2799     { "(bad)",  { XX } },
2800     { "(bad)",  { XX } },
2801     { "(bad)",  { XX } },
2802   },
2803
2804   /* PREFIX_0FC7_REG_6 */
2805   {
2806     { "vmptrld",{ Mq } },
2807     { "vmxon",  { Mq } },
2808     { "vmclear",{ Mq } },
2809     { "(bad)",  { XX } },
2810   },
2811
2812   /* PREFIX_0FD0 */
2813   {
2814     { "(bad)",  { XX } },
2815     { "(bad)",  { XX } },
2816     { "addsubpd", { XM, EXx } },
2817     { "addsubps", { XM, EXx } },
2818   },
2819
2820   /* PREFIX_0FD6 */
2821   {
2822     { "(bad)",  { XX } },
2823     { "movq2dq",{ XM, MS } },
2824     { "movq",   { EXqS, XM } },
2825     { "movdq2q",{ MX, XS } },
2826   },
2827
2828   /* PREFIX_0FE6 */
2829   {
2830     { "(bad)",  { XX } },
2831     { "cvtdq2pd", { XM, EXq } },
2832     { "cvttpd2dq", { XM, EXx } },
2833     { "cvtpd2dq", { XM, EXx } },
2834   },
2835
2836   /* PREFIX_0FE7 */
2837   {
2838     { "movntq", { Mq, MX } },
2839     { "(bad)",  { XX } },
2840     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2841     { "(bad)",  { XX } },
2842   },
2843
2844   /* PREFIX_0FF0 */
2845   {
2846     { "(bad)",  { XX } },
2847     { "(bad)",  { XX } },
2848     { "(bad)",  { XX } },
2849     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2850   },
2851
2852   /* PREFIX_0FF7 */
2853   {
2854     { "maskmovq", { MX, MS } },
2855     { "(bad)",  { XX } },
2856     { "maskmovdqu", { XM, XS } },
2857     { "(bad)",  { XX } },
2858   },
2859
2860   /* PREFIX_0F3810 */
2861   {
2862     { "(bad)",  { XX } },
2863     { "(bad)",  { XX } },
2864     { "pblendvb", { XM, EXx, XMM0 } },
2865     { "(bad)",  { XX } },
2866   },
2867
2868   /* PREFIX_0F3814 */
2869   {
2870     { "(bad)",  { XX } },
2871     { "(bad)",  { XX } },
2872     { "blendvps", { XM, EXx, XMM0 } },
2873     { "(bad)",  { XX } },
2874   },
2875
2876   /* PREFIX_0F3815 */
2877   {
2878     { "(bad)",  { XX } },
2879     { "(bad)",  { XX } },
2880     { "blendvpd", { XM, EXx, XMM0 } },
2881     { "(bad)",  { XX } },
2882   },
2883
2884   /* PREFIX_0F3817 */
2885   {
2886     { "(bad)",  { XX } },
2887     { "(bad)",  { XX } },
2888     { "ptest",  { XM, EXx } },
2889     { "(bad)",  { XX } },
2890   },
2891
2892   /* PREFIX_0F3820 */
2893   {
2894     { "(bad)",  { XX } },
2895     { "(bad)",  { XX } },
2896     { "pmovsxbw", { XM, EXq } },
2897     { "(bad)",  { XX } },
2898   },
2899
2900   /* PREFIX_0F3821 */
2901   {
2902     { "(bad)",  { XX } },
2903     { "(bad)",  { XX } },
2904     { "pmovsxbd", { XM, EXd } },
2905     { "(bad)",  { XX } },
2906   },
2907
2908   /* PREFIX_0F3822 */
2909   {
2910     { "(bad)",  { XX } },
2911     { "(bad)",  { XX } },
2912     { "pmovsxbq", { XM, EXw } },
2913     { "(bad)",  { XX } },
2914   },
2915
2916   /* PREFIX_0F3823 */
2917   {
2918     { "(bad)",  { XX } },
2919     { "(bad)",  { XX } },
2920     { "pmovsxwd", { XM, EXq } },
2921     { "(bad)",  { XX } },
2922   },
2923
2924   /* PREFIX_0F3824 */
2925   {
2926     { "(bad)",  { XX } },
2927     { "(bad)",  { XX } },
2928     { "pmovsxwq", { XM, EXd } },
2929     { "(bad)",  { XX } },
2930   },
2931
2932   /* PREFIX_0F3825 */
2933   {
2934     { "(bad)",  { XX } },
2935     { "(bad)",  { XX } },
2936     { "pmovsxdq", { XM, EXq } },
2937     { "(bad)",  { XX } },
2938   },
2939
2940   /* PREFIX_0F3828 */
2941   {
2942     { "(bad)",  { XX } },
2943     { "(bad)",  { XX } },
2944     { "pmuldq", { XM, EXx } },
2945     { "(bad)",  { XX } },
2946   },
2947
2948   /* PREFIX_0F3829 */
2949   {
2950     { "(bad)",  { XX } },
2951     { "(bad)",  { XX } },
2952     { "pcmpeqq", { XM, EXx } },
2953     { "(bad)",  { XX } },
2954   },
2955
2956   /* PREFIX_0F382A */
2957   {
2958     { "(bad)",  { XX } },
2959     { "(bad)",  { XX } },
2960     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2961     { "(bad)",  { XX } },
2962   },
2963
2964   /* PREFIX_0F382B */
2965   {
2966     { "(bad)",  { XX } },
2967     { "(bad)",  { XX } },
2968     { "packusdw", { XM, EXx } },
2969     { "(bad)",  { XX } },
2970   },
2971
2972   /* PREFIX_0F3830 */
2973   {
2974     { "(bad)",  { XX } },
2975     { "(bad)",  { XX } },
2976     { "pmovzxbw", { XM, EXq } },
2977     { "(bad)",  { XX } },
2978   },
2979
2980   /* PREFIX_0F3831 */
2981   {
2982     { "(bad)",  { XX } },
2983     { "(bad)",  { XX } },
2984     { "pmovzxbd", { XM, EXd } },
2985     { "(bad)",  { XX } },
2986   },
2987
2988   /* PREFIX_0F3832 */
2989   {
2990     { "(bad)",  { XX } },
2991     { "(bad)",  { XX } },
2992     { "pmovzxbq", { XM, EXw } },
2993     { "(bad)",  { XX } },
2994   },
2995
2996   /* PREFIX_0F3833 */
2997   {
2998     { "(bad)",  { XX } },
2999     { "(bad)",  { XX } },
3000     { "pmovzxwd", { XM, EXq } },
3001     { "(bad)",  { XX } },
3002   },
3003
3004   /* PREFIX_0F3834 */
3005   {
3006     { "(bad)",  { XX } },
3007     { "(bad)",  { XX } },
3008     { "pmovzxwq", { XM, EXd } },
3009     { "(bad)",  { XX } },
3010   },
3011
3012   /* PREFIX_0F3835 */
3013   {
3014     { "(bad)",  { XX } },
3015     { "(bad)",  { XX } },
3016     { "pmovzxdq", { XM, EXq } },
3017     { "(bad)",  { XX } },
3018   },
3019
3020   /* PREFIX_0F3837 */
3021   {
3022     { "(bad)",  { XX } },
3023     { "(bad)",  { XX } },
3024     { "pcmpgtq", { XM, EXx } },
3025     { "(bad)",  { XX } },
3026   },
3027
3028   /* PREFIX_0F3838 */
3029   {
3030     { "(bad)",  { XX } },
3031     { "(bad)",  { XX } },
3032     { "pminsb", { XM, EXx } },
3033     { "(bad)",  { XX } },
3034   },
3035
3036   /* PREFIX_0F3839 */
3037   {
3038     { "(bad)",  { XX } },
3039     { "(bad)",  { XX } },
3040     { "pminsd", { XM, EXx } },
3041     { "(bad)",  { XX } },
3042   },
3043
3044   /* PREFIX_0F383A */
3045   {
3046     { "(bad)",  { XX } },
3047     { "(bad)",  { XX } },
3048     { "pminuw", { XM, EXx } },
3049     { "(bad)",  { XX } },
3050   },
3051
3052   /* PREFIX_0F383B */
3053   {
3054     { "(bad)",  { XX } },
3055     { "(bad)",  { XX } },
3056     { "pminud", { XM, EXx } },
3057     { "(bad)",  { XX } },
3058   },
3059
3060   /* PREFIX_0F383C */
3061   {
3062     { "(bad)",  { XX } },
3063     { "(bad)",  { XX } },
3064     { "pmaxsb", { XM, EXx } },
3065     { "(bad)",  { XX } },
3066   },
3067
3068   /* PREFIX_0F383D */
3069   {
3070     { "(bad)",  { XX } },
3071     { "(bad)",  { XX } },
3072     { "pmaxsd", { XM, EXx } },
3073     { "(bad)",  { XX } },
3074   },
3075
3076   /* PREFIX_0F383E */
3077   {
3078     { "(bad)",  { XX } },
3079     { "(bad)",  { XX } },
3080     { "pmaxuw", { XM, EXx } },
3081     { "(bad)",  { XX } },
3082   },
3083
3084   /* PREFIX_0F383F */
3085   {
3086     { "(bad)",  { XX } },
3087     { "(bad)",  { XX } },
3088     { "pmaxud", { XM, EXx } },
3089     { "(bad)",  { XX } },
3090   },
3091
3092   /* PREFIX_0F3840 */
3093   {
3094     { "(bad)",  { XX } },
3095     { "(bad)",  { XX } },
3096     { "pmulld", { XM, EXx } },
3097     { "(bad)",  { XX } },
3098   },
3099
3100   /* PREFIX_0F3841 */
3101   {
3102     { "(bad)",  { XX } },
3103     { "(bad)",  { XX } },
3104     { "phminposuw", { XM, EXx } },
3105     { "(bad)",  { XX } },
3106   },
3107
3108   /* PREFIX_0F3880 */
3109   {
3110     { "(bad)",  { XX } },
3111     { "(bad)",  { XX } },
3112     { "invept", { Gm, Mo } },
3113     { "(bad)",  { XX } },
3114   },
3115
3116   /* PREFIX_0F3881 */
3117   {
3118     { "(bad)",  { XX } },
3119     { "(bad)",  { XX } },
3120     { "invvpid", { Gm, Mo } },
3121     { "(bad)",  { XX } },
3122   },
3123
3124   /* PREFIX_0F38DB */
3125   {
3126     { "(bad)",  { XX } },
3127     { "(bad)",  { XX } },
3128     { "aesimc", { XM, EXx } },
3129     { "(bad)",  { XX } },
3130   },
3131
3132   /* PREFIX_0F38DC */
3133   {
3134     { "(bad)",  { XX } },
3135     { "(bad)",  { XX } },
3136     { "aesenc", { XM, EXx } },
3137     { "(bad)",  { XX } },
3138   },
3139
3140   /* PREFIX_0F38DD */
3141   {
3142     { "(bad)",  { XX } },
3143     { "(bad)",  { XX } },
3144     { "aesenclast", { XM, EXx } },
3145     { "(bad)",  { XX } },
3146   },
3147
3148   /* PREFIX_0F38DE */
3149   {
3150     { "(bad)",  { XX } },
3151     { "(bad)",  { XX } },
3152     { "aesdec", { XM, EXx } },
3153     { "(bad)",  { XX } },
3154   },
3155
3156   /* PREFIX_0F38DF */
3157   {
3158     { "(bad)",  { XX } },
3159     { "(bad)",  { XX } },
3160     { "aesdeclast", { XM, EXx } },
3161     { "(bad)",  { XX } },
3162   },
3163
3164   /* PREFIX_0F38F0 */
3165   {
3166     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3167     { "(bad)",  { XX } },
3168     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3169     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3170   },
3171
3172   /* PREFIX_0F38F1 */
3173   {
3174     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3175     { "(bad)",  { XX } },
3176     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3177     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3178   },
3179
3180   /* PREFIX_0F3A08 */
3181   {
3182     { "(bad)",  { XX } },
3183     { "(bad)",  { XX } },
3184     { "roundps", { XM, EXx, Ib } },
3185     { "(bad)",  { XX } },
3186   },
3187
3188   /* PREFIX_0F3A09 */
3189   {
3190     { "(bad)",  { XX } },
3191     { "(bad)",  { XX } },
3192     { "roundpd", { XM, EXx, Ib } },
3193     { "(bad)",  { XX } },
3194   },
3195
3196   /* PREFIX_0F3A0A */
3197   {
3198     { "(bad)",  { XX } },
3199     { "(bad)",  { XX } },
3200     { "roundss", { XM, EXd, Ib } },
3201     { "(bad)",  { XX } },
3202   },
3203
3204   /* PREFIX_0F3A0B */
3205   {
3206     { "(bad)",  { XX } },
3207     { "(bad)",  { XX } },
3208     { "roundsd", { XM, EXq, Ib } },
3209     { "(bad)",  { XX } },
3210   },
3211
3212   /* PREFIX_0F3A0C */
3213   {
3214     { "(bad)",  { XX } },
3215     { "(bad)",  { XX } },
3216     { "blendps", { XM, EXx, Ib } },
3217     { "(bad)",  { XX } },
3218   },
3219
3220   /* PREFIX_0F3A0D */
3221   {
3222     { "(bad)",  { XX } },
3223     { "(bad)",  { XX } },
3224     { "blendpd", { XM, EXx, Ib } },
3225     { "(bad)",  { XX } },
3226   },
3227
3228   /* PREFIX_0F3A0E */
3229   {
3230     { "(bad)",  { XX } },
3231     { "(bad)",  { XX } },
3232     { "pblendw", { XM, EXx, Ib } },
3233     { "(bad)",  { XX } },
3234   },
3235
3236   /* PREFIX_0F3A14 */
3237   {
3238     { "(bad)",  { XX } },
3239     { "(bad)",  { XX } },
3240     { "pextrb", { Edqb, XM, Ib } },
3241     { "(bad)",  { XX } },
3242   },
3243
3244   /* PREFIX_0F3A15 */
3245   {
3246     { "(bad)",  { XX } },
3247     { "(bad)",  { XX } },
3248     { "pextrw", { Edqw, XM, Ib } },
3249     { "(bad)",  { XX } },
3250   },
3251
3252   /* PREFIX_0F3A16 */
3253   {
3254     { "(bad)",  { XX } },
3255     { "(bad)",  { XX } },
3256     { "pextrK", { Edq, XM, Ib } },
3257     { "(bad)",  { XX } },
3258   },
3259
3260   /* PREFIX_0F3A17 */
3261   {
3262     { "(bad)",  { XX } },
3263     { "(bad)",  { XX } },
3264     { "extractps", { Edqd, XM, Ib } },
3265     { "(bad)",  { XX } },
3266   },
3267
3268   /* PREFIX_0F3A20 */
3269   {
3270     { "(bad)",  { XX } },
3271     { "(bad)",  { XX } },
3272     { "pinsrb", { XM, Edqb, Ib } },
3273     { "(bad)",  { XX } },
3274   },
3275
3276   /* PREFIX_0F3A21 */
3277   {
3278     { "(bad)",  { XX } },
3279     { "(bad)",  { XX } },
3280     { "insertps", { XM, EXd, Ib } },
3281     { "(bad)",  { XX } },
3282   },
3283
3284   /* PREFIX_0F3A22 */
3285   {
3286     { "(bad)",  { XX } },
3287     { "(bad)",  { XX } },
3288     { "pinsrK", { XM, Edq, Ib } },
3289     { "(bad)",  { XX } },
3290   },
3291
3292   /* PREFIX_0F3A40 */
3293   {
3294     { "(bad)",  { XX } },
3295     { "(bad)",  { XX } },
3296     { "dpps",   { XM, EXx, Ib } },
3297     { "(bad)",  { XX } },
3298   },
3299
3300   /* PREFIX_0F3A41 */
3301   {
3302     { "(bad)",  { XX } },
3303     { "(bad)",  { XX } },
3304     { "dppd",   { XM, EXx, Ib } },
3305     { "(bad)",  { XX } },
3306   },
3307
3308   /* PREFIX_0F3A42 */
3309   {
3310     { "(bad)",  { XX } },
3311     { "(bad)",  { XX } },
3312     { "mpsadbw", { XM, EXx, Ib } },
3313     { "(bad)",  { XX } },
3314   },
3315
3316   /* PREFIX_0F3A44 */
3317   {
3318     { "(bad)",  { XX } },
3319     { "(bad)",  { XX } },
3320     { "pclmulqdq", { XM, EXx, PCLMUL } },
3321     { "(bad)",  { XX } },
3322   },
3323
3324   /* PREFIX_0F3A60 */
3325   {
3326     { "(bad)",  { XX } },
3327     { "(bad)",  { XX } },
3328     { "pcmpestrm", { XM, EXx, Ib } },
3329     { "(bad)",  { XX } },
3330   },
3331
3332   /* PREFIX_0F3A61 */
3333   {
3334     { "(bad)",  { XX } },
3335     { "(bad)",  { XX } },
3336     { "pcmpestri", { XM, EXx, Ib } },
3337     { "(bad)",  { XX } },
3338   },
3339
3340   /* PREFIX_0F3A62 */
3341   {
3342     { "(bad)",  { XX } },
3343     { "(bad)",  { XX } },
3344     { "pcmpistrm", { XM, EXx, Ib } },
3345     { "(bad)",  { XX } },
3346   },
3347
3348   /* PREFIX_0F3A63 */
3349   {
3350     { "(bad)",  { XX } },
3351     { "(bad)",  { XX } },
3352     { "pcmpistri", { XM, EXx, Ib } },
3353     { "(bad)",  { XX } },
3354   },
3355
3356   /* PREFIX_0F3ADF */
3357   {
3358     { "(bad)",  { XX } },
3359     { "(bad)",  { XX } },
3360     { "aeskeygenassist", { XM, EXx, Ib } },
3361     { "(bad)",  { XX } },
3362   },
3363
3364   /* PREFIX_VEX_10 */
3365   {
3366     { "vmovups", { XM, EXx } },
3367     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3368     { "vmovupd", { XM, EXx } },
3369     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3370   },
3371
3372   /* PREFIX_VEX_11 */
3373   {
3374     { "vmovups", { EXxS, XM } },
3375     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3376     { "vmovupd", { EXxS, XM } },
3377     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3378   },
3379
3380   /* PREFIX_VEX_12 */
3381   {
3382     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3383     { "vmovsldup", { XM, EXx } },
3384     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3385     { "vmovddup", { XM, EXymmq } },
3386   },
3387
3388   /* PREFIX_VEX_16 */
3389   {
3390     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3391     { "vmovshdup", { XM, EXx } },
3392     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3393     { "(bad)",  { XX } },
3394   },
3395
3396   /* PREFIX_VEX_2A */
3397   {
3398     { "(bad)",  { XX } },
3399     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3400     { "(bad)",  { XX } },
3401     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3402   },
3403
3404   /* PREFIX_VEX_2C */
3405   {
3406     { "(bad)",  { XX } },
3407     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3408     { "(bad)",  { XX } },
3409     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3410   },
3411
3412   /* PREFIX_VEX_2D */
3413   {
3414     { "(bad)",  { XX } },
3415     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3416     { "(bad)",  { XX } },
3417     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3418   },
3419
3420   /* PREFIX_VEX_2E */
3421   {
3422     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3423     { "(bad)",  { XX } },
3424     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3425     { "(bad)",  { XX } },
3426   },
3427
3428   /* PREFIX_VEX_2F */
3429   {
3430     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3431     { "(bad)",  { XX } },
3432     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3433     { "(bad)",  { XX } },
3434   },
3435
3436   /* PREFIX_VEX_51 */
3437   {
3438     { "vsqrtps", { XM, EXx } },
3439     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3440     { "vsqrtpd", { XM, EXx } },
3441     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3442   },
3443
3444   /* PREFIX_VEX_52 */
3445   {
3446     { "vrsqrtps", { XM, EXx } },
3447     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3448     { "(bad)",  { XX } },
3449     { "(bad)",  { XX } },
3450   },
3451
3452   /* PREFIX_VEX_53 */
3453   {
3454     { "vrcpps", { XM, EXx } },
3455     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3456     { "(bad)",  { XX } },
3457     { "(bad)",  { XX } },
3458   },
3459
3460   /* PREFIX_VEX_58 */
3461   {
3462     { "vaddps", { XM, Vex, EXx } },
3463     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3464     { "vaddpd", { XM, Vex, EXx } },
3465     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3466   },
3467
3468   /* PREFIX_VEX_59 */
3469   {
3470     { "vmulps", { XM, Vex, EXx } },
3471     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3472     { "vmulpd", { XM, Vex, EXx } },
3473     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3474   },
3475
3476   /* PREFIX_VEX_5A */
3477   {
3478     { "vcvtps2pd", { XM, EXxmmq } },
3479     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3480     { "vcvtpd2ps%XY", { XMM, EXx } },
3481     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3482   },
3483
3484   /* PREFIX_VEX_5B */
3485   {
3486     { "vcvtdq2ps", { XM, EXx } },
3487     { "vcvttps2dq", { XM, EXx } },
3488     { "vcvtps2dq", { XM, EXx } },
3489     { "(bad)",  { XX } },
3490   },
3491
3492   /* PREFIX_VEX_5C */
3493   {
3494     { "vsubps", { XM, Vex, EXx } },
3495     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3496     { "vsubpd", { XM, Vex, EXx } },
3497     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3498   },
3499
3500   /* PREFIX_VEX_5D */
3501   {
3502     { "vminps", { XM, Vex, EXx } },
3503     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3504     { "vminpd", { XM, Vex, EXx } },
3505     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3506   },
3507
3508   /* PREFIX_VEX_5E */
3509   {
3510     { "vdivps", { XM, Vex, EXx } },
3511     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3512     { "vdivpd", { XM, Vex, EXx } },
3513     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3514   },
3515
3516   /* PREFIX_VEX_5F */
3517   {
3518     { "vmaxps", { XM, Vex, EXx } },
3519     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3520     { "vmaxpd", { XM, Vex, EXx } },
3521     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3522   },
3523
3524   /* PREFIX_VEX_60 */
3525   {
3526     { "(bad)",  { XX } },
3527     { "(bad)",  { XX } },
3528     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3529     { "(bad)",  { XX } },
3530   },
3531
3532   /* PREFIX_VEX_61 */
3533   {
3534     { "(bad)",  { XX } },
3535     { "(bad)",  { XX } },
3536     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3537     { "(bad)",  { XX } },
3538   },
3539
3540   /* PREFIX_VEX_62 */
3541   {
3542     { "(bad)",  { XX } },
3543     { "(bad)",  { XX } },
3544     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3545     { "(bad)",  { XX } },
3546   },
3547
3548   /* PREFIX_VEX_63 */
3549   {
3550     { "(bad)",  { XX } },
3551     { "(bad)",  { XX } },
3552     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3553     { "(bad)",  { XX } },
3554   },
3555
3556   /* PREFIX_VEX_64 */
3557   {
3558     { "(bad)",  { XX } },
3559     { "(bad)",  { XX } },
3560     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3561     { "(bad)",  { XX } },
3562   },
3563
3564   /* PREFIX_VEX_65 */
3565   {
3566     { "(bad)",  { XX } },
3567     { "(bad)",  { XX } },
3568     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3569     { "(bad)",  { XX } },
3570   },
3571
3572   /* PREFIX_VEX_66 */
3573   {
3574     { "(bad)",  { XX } },
3575     { "(bad)",  { XX } },
3576     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3577     { "(bad)",  { XX } },
3578   },
3579
3580   /* PREFIX_VEX_67 */
3581   {
3582     { "(bad)",  { XX } },
3583     { "(bad)",  { XX } },
3584     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3585     { "(bad)",  { XX } },
3586   },
3587
3588   /* PREFIX_VEX_68 */
3589   {
3590     { "(bad)",  { XX } },
3591     { "(bad)",  { XX } },
3592     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3593     { "(bad)",  { XX } },
3594   },
3595
3596   /* PREFIX_VEX_69 */
3597   {
3598     { "(bad)",  { XX } },
3599     { "(bad)",  { XX } },
3600     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3601     { "(bad)",  { XX } },
3602   },
3603
3604   /* PREFIX_VEX_6A */
3605   {
3606     { "(bad)",  { XX } },
3607     { "(bad)",  { XX } },
3608     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3609     { "(bad)",  { XX } },
3610   },
3611
3612   /* PREFIX_VEX_6B */
3613   {
3614     { "(bad)",  { XX } },
3615     { "(bad)",  { XX } },
3616     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3617     { "(bad)",  { XX } },
3618   },
3619
3620   /* PREFIX_VEX_6C */
3621   {
3622     { "(bad)",  { XX } },
3623     { "(bad)",  { XX } },
3624     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3625     { "(bad)",  { XX } },
3626   },
3627
3628   /* PREFIX_VEX_6D */
3629   {
3630     { "(bad)",  { XX } },
3631     { "(bad)",  { XX } },
3632     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3633     { "(bad)",  { XX } },
3634   },
3635
3636   /* PREFIX_VEX_6E */
3637   {
3638     { "(bad)",  { XX } },
3639     { "(bad)",  { XX } },
3640     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3641     { "(bad)",  { XX } },
3642   },
3643
3644   /* PREFIX_VEX_6F */
3645   {
3646     { "(bad)",  { XX } },
3647     { "vmovdqu", { XM, EXx } },
3648     { "vmovdqa", { XM, EXx } },
3649     { "(bad)",  { XX } },
3650   },
3651
3652   /* PREFIX_VEX_70 */
3653   {
3654     { "(bad)",  { XX } },
3655     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3656     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3657     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3658   },
3659
3660   /* PREFIX_VEX_71_REG_2 */
3661   {
3662     { "(bad)",  { XX } },
3663     { "(bad)",  { XX } },
3664     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3665     { "(bad)",  { XX } },
3666   },
3667
3668   /* PREFIX_VEX_71_REG_4 */
3669   {
3670     { "(bad)",  { XX } },
3671     { "(bad)",  { XX } },
3672     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3673     { "(bad)",  { XX } },
3674   },
3675
3676   /* PREFIX_VEX_71_REG_6 */
3677   {
3678     { "(bad)",  { XX } },
3679     { "(bad)",  { XX } },
3680     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3681     { "(bad)",  { XX } },
3682   },
3683
3684   /* PREFIX_VEX_72_REG_2 */
3685   {
3686     { "(bad)",  { XX } },
3687     { "(bad)",  { XX } },
3688     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3689     { "(bad)",  { XX } },
3690   },
3691
3692   /* PREFIX_VEX_72_REG_4 */
3693   {
3694     { "(bad)",  { XX } },
3695     { "(bad)",  { XX } },
3696     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3697     { "(bad)",  { XX } },
3698   },
3699
3700   /* PREFIX_VEX_72_REG_6 */
3701   {
3702     { "(bad)",  { XX } },
3703     { "(bad)",  { XX } },
3704     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3705     { "(bad)",  { XX } },
3706   },
3707
3708   /* PREFIX_VEX_73_REG_2 */
3709   {
3710     { "(bad)",  { XX } },
3711     { "(bad)",  { XX } },
3712     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3713     { "(bad)",  { XX } },
3714   },
3715
3716   /* PREFIX_VEX_73_REG_3 */
3717   {
3718     { "(bad)",  { XX } },
3719     { "(bad)",  { XX } },
3720     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3721     { "(bad)",  { XX } },
3722   },
3723
3724   /* PREFIX_VEX_73_REG_6 */
3725   {
3726     { "(bad)",  { XX } },
3727     { "(bad)",  { XX } },
3728     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3729     { "(bad)",  { XX } },
3730   },
3731
3732   /* PREFIX_VEX_73_REG_7 */
3733   {
3734     { "(bad)",  { XX } },
3735     { "(bad)",  { XX } },
3736     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3737     { "(bad)",  { XX } },
3738   },
3739
3740   /* PREFIX_VEX_74 */
3741   {
3742     { "(bad)",  { XX } },
3743     { "(bad)",  { XX } },
3744     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3745     { "(bad)",  { XX } },
3746   },
3747
3748   /* PREFIX_VEX_75 */
3749   {
3750     { "(bad)",  { XX } },
3751     { "(bad)",  { XX } },
3752     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3753     { "(bad)",  { XX } },
3754   },
3755
3756   /* PREFIX_VEX_76 */
3757   {
3758     { "(bad)",  { XX } },
3759     { "(bad)",  { XX } },
3760     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3761     { "(bad)",  { XX } },
3762   },
3763
3764   /* PREFIX_VEX_77 */
3765   {
3766     { "",       { VZERO } },
3767     { "(bad)",  { XX } },
3768     { "(bad)",  { XX } },
3769     { "(bad)",  { XX } },
3770   },
3771
3772   /* PREFIX_VEX_7C */
3773   {
3774     { "(bad)",  { XX } },
3775     { "(bad)",  { XX } },
3776     { "vhaddpd", { XM, Vex, EXx } },
3777     { "vhaddps", { XM, Vex, EXx } },
3778   },
3779
3780   /* PREFIX_VEX_7D */
3781   {
3782     { "(bad)",  { XX } },
3783     { "(bad)",  { XX } },
3784     { "vhsubpd", { XM, Vex, EXx } },
3785     { "vhsubps", { XM, Vex, EXx } },
3786   },
3787
3788   /* PREFIX_VEX_7E */
3789   {
3790     { "(bad)",  { XX } },
3791     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3792     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3793     { "(bad)",  { XX } },
3794   },
3795
3796   /* PREFIX_VEX_7F */
3797   {
3798     { "(bad)",  { XX } },
3799     { "vmovdqu", { EXxS, XM } },
3800     { "vmovdqa", { EXxS, XM } },
3801     { "(bad)",  { XX } },
3802   },
3803
3804   /* PREFIX_VEX_C2 */
3805   {
3806     { "vcmpps", { XM, Vex, EXx, VCMP } },
3807     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3808     { "vcmppd", { XM, Vex, EXx, VCMP } },
3809     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3810   },
3811
3812   /* PREFIX_VEX_C4 */
3813   {
3814     { "(bad)",  { XX } },
3815     { "(bad)",  { XX } },
3816     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3817     { "(bad)",  { XX } },
3818   },
3819
3820   /* PREFIX_VEX_C5 */
3821   {
3822     { "(bad)",  { XX } },
3823     { "(bad)",  { XX } },
3824     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3825     { "(bad)",  { XX } },
3826   },
3827
3828   /* PREFIX_VEX_D0 */
3829   {
3830     { "(bad)",  { XX } },
3831     { "(bad)",  { XX } },
3832     { "vaddsubpd", { XM, Vex, EXx } },
3833     { "vaddsubps", { XM, Vex, EXx } },
3834   },
3835
3836   /* PREFIX_VEX_D1 */
3837   {
3838     { "(bad)",  { XX } },
3839     { "(bad)",  { XX } },
3840     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3841     { "(bad)",  { XX } },
3842   },
3843
3844   /* PREFIX_VEX_D2 */
3845   {
3846     { "(bad)",  { XX } },
3847     { "(bad)",  { XX } },
3848     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3849     { "(bad)",  { XX } },
3850   },
3851
3852   /* PREFIX_VEX_D3 */
3853   {
3854     { "(bad)",  { XX } },
3855     { "(bad)",  { XX } },
3856     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3857     { "(bad)",  { XX } },
3858   },
3859
3860   /* PREFIX_VEX_D4 */
3861   {
3862     { "(bad)",  { XX } },
3863     { "(bad)",  { XX } },
3864     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3865     { "(bad)",  { XX } },
3866   },
3867
3868   /* PREFIX_VEX_D5 */
3869   {
3870     { "(bad)",  { XX } },
3871     { "(bad)",  { XX } },
3872     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3873     { "(bad)",  { XX } },
3874   },
3875
3876   /* PREFIX_VEX_D6 */
3877   {
3878     { "(bad)",  { XX } },
3879     { "(bad)",  { XX } },
3880     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3881     { "(bad)",  { XX } },
3882   },
3883
3884   /* PREFIX_VEX_D7 */
3885   {
3886     { "(bad)",  { XX } },
3887     { "(bad)",  { XX } },
3888     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3889     { "(bad)",  { XX } },
3890   },
3891
3892   /* PREFIX_VEX_D8 */
3893   {
3894     { "(bad)",  { XX } },
3895     { "(bad)",  { XX } },
3896     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3897     { "(bad)",  { XX } },
3898   },
3899
3900   /* PREFIX_VEX_D9 */
3901   {
3902     { "(bad)",  { XX } },
3903     { "(bad)",  { XX } },
3904     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3905     { "(bad)",  { XX } },
3906   },
3907
3908   /* PREFIX_VEX_DA */
3909   {
3910     { "(bad)",  { XX } },
3911     { "(bad)",  { XX } },
3912     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3913     { "(bad)",  { XX } },
3914   },
3915
3916   /* PREFIX_VEX_DB */
3917   {
3918     { "(bad)",  { XX } },
3919     { "(bad)",  { XX } },
3920     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3921     { "(bad)",  { XX } },
3922   },
3923
3924   /* PREFIX_VEX_DC */
3925   {
3926     { "(bad)",  { XX } },
3927     { "(bad)",  { XX } },
3928     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3929     { "(bad)",  { XX } },
3930   },
3931
3932   /* PREFIX_VEX_DD */
3933   {
3934     { "(bad)",  { XX } },
3935     { "(bad)",  { XX } },
3936     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3937     { "(bad)",  { XX } },
3938   },
3939
3940   /* PREFIX_VEX_DE */
3941   {
3942     { "(bad)",  { XX } },
3943     { "(bad)",  { XX } },
3944     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3945     { "(bad)",  { XX } },
3946   },
3947
3948   /* PREFIX_VEX_DF */
3949   {
3950     { "(bad)",  { XX } },
3951     { "(bad)",  { XX } },
3952     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3953     { "(bad)",  { XX } },
3954   },
3955
3956   /* PREFIX_VEX_E0 */
3957   {
3958     { "(bad)",  { XX } },
3959     { "(bad)",  { XX } },
3960     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3961     { "(bad)",  { XX } },
3962   },
3963
3964   /* PREFIX_VEX_E1 */
3965   {
3966     { "(bad)",  { XX } },
3967     { "(bad)",  { XX } },
3968     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3969     { "(bad)",  { XX } },
3970   },
3971
3972   /* PREFIX_VEX_E2 */
3973   {
3974     { "(bad)",  { XX } },
3975     { "(bad)",  { XX } },
3976     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3977     { "(bad)",  { XX } },
3978   },
3979
3980   /* PREFIX_VEX_E3 */
3981   {
3982     { "(bad)",  { XX } },
3983     { "(bad)",  { XX } },
3984     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3985     { "(bad)",  { XX } },
3986   },
3987
3988   /* PREFIX_VEX_E4 */
3989   {
3990     { "(bad)",  { XX } },
3991     { "(bad)",  { XX } },
3992     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3993     { "(bad)",  { XX } },
3994   },
3995
3996   /* PREFIX_VEX_E5 */
3997   {
3998     { "(bad)",  { XX } },
3999     { "(bad)",  { XX } },
4000     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4001     { "(bad)",  { XX } },
4002   },
4003
4004   /* PREFIX_VEX_E6 */
4005   {
4006     { "(bad)",  { XX } },
4007     { "vcvtdq2pd", { XM, EXxmmq } },
4008     { "vcvttpd2dq%XY", { XMM, EXx } },
4009     { "vcvtpd2dq%XY", { XMM, EXx } },
4010   },
4011
4012   /* PREFIX_VEX_E7 */
4013   {
4014     { "(bad)",  { XX } },
4015     { "(bad)",  { XX } },
4016     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4017     { "(bad)",  { XX } },
4018   },
4019
4020   /* PREFIX_VEX_E8 */
4021   {
4022     { "(bad)",  { XX } },
4023     { "(bad)",  { XX } },
4024     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4025     { "(bad)",  { XX } },
4026   },
4027
4028   /* PREFIX_VEX_E9 */
4029   {
4030     { "(bad)",  { XX } },
4031     { "(bad)",  { XX } },
4032     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4033     { "(bad)",  { XX } },
4034   },
4035
4036   /* PREFIX_VEX_EA */
4037   {
4038     { "(bad)",  { XX } },
4039     { "(bad)",  { XX } },
4040     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4041     { "(bad)",  { XX } },
4042   },
4043
4044   /* PREFIX_VEX_EB */
4045   {
4046     { "(bad)",  { XX } },
4047     { "(bad)",  { XX } },
4048     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4049     { "(bad)",  { XX } },
4050   },
4051
4052   /* PREFIX_VEX_EC */
4053   {
4054     { "(bad)",  { XX } },
4055     { "(bad)",  { XX } },
4056     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4057     { "(bad)",  { XX } },
4058   },
4059
4060   /* PREFIX_VEX_ED */
4061   {
4062     { "(bad)",  { XX } },
4063     { "(bad)",  { XX } },
4064     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4065     { "(bad)",  { XX } },
4066   },
4067
4068   /* PREFIX_VEX_EE */
4069   {
4070     { "(bad)",  { XX } },
4071     { "(bad)",  { XX } },
4072     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4073     { "(bad)",  { XX } },
4074   },
4075
4076   /* PREFIX_VEX_EF */
4077   {
4078     { "(bad)",  { XX } },
4079     { "(bad)",  { XX } },
4080     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4081     { "(bad)",  { XX } },
4082   },
4083
4084   /* PREFIX_VEX_F0 */
4085   {
4086     { "(bad)",  { XX } },
4087     { "(bad)",  { XX } },
4088     { "(bad)",  { XX } },
4089     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4090   },
4091
4092   /* PREFIX_VEX_F1 */
4093   {
4094     { "(bad)",  { XX } },
4095     { "(bad)",  { XX } },
4096     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4097     { "(bad)",  { XX } },
4098   },
4099
4100   /* PREFIX_VEX_F2 */
4101   {
4102     { "(bad)",  { XX } },
4103     { "(bad)",  { XX } },
4104     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4105     { "(bad)",  { XX } },
4106   },
4107
4108   /* PREFIX_VEX_F3 */
4109   {
4110     { "(bad)",  { XX } },
4111     { "(bad)",  { XX } },
4112     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4113     { "(bad)",  { XX } },
4114   },
4115
4116   /* PREFIX_VEX_F4 */
4117   {
4118     { "(bad)",  { XX } },
4119     { "(bad)",  { XX } },
4120     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4121     { "(bad)",  { XX } },
4122   },
4123
4124   /* PREFIX_VEX_F5 */
4125   {
4126     { "(bad)",  { XX } },
4127     { "(bad)",  { XX } },
4128     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4129     { "(bad)",  { XX } },
4130   },
4131
4132   /* PREFIX_VEX_F6 */
4133   {
4134     { "(bad)",  { XX } },
4135     { "(bad)",  { XX } },
4136     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4137     { "(bad)",  { XX } },
4138   },
4139
4140   /* PREFIX_VEX_F7 */
4141   {
4142     { "(bad)",  { XX } },
4143     { "(bad)",  { XX } },
4144     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4145     { "(bad)",  { XX } },
4146   },
4147
4148   /* PREFIX_VEX_F8 */
4149   {
4150     { "(bad)",  { XX } },
4151     { "(bad)",  { XX } },
4152     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4153     { "(bad)",  { XX } },
4154   },
4155
4156   /* PREFIX_VEX_F9 */
4157   {
4158     { "(bad)",  { XX } },
4159     { "(bad)",  { XX } },
4160     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4161     { "(bad)",  { XX } },
4162   },
4163
4164   /* PREFIX_VEX_FA */
4165   {
4166     { "(bad)",  { XX } },
4167     { "(bad)",  { XX } },
4168     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4169     { "(bad)",  { XX } },
4170   },
4171
4172   /* PREFIX_VEX_FB */
4173   {
4174     { "(bad)",  { XX } },
4175     { "(bad)",  { XX } },
4176     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4177     { "(bad)",  { XX } },
4178   },
4179
4180   /* PREFIX_VEX_FC */
4181   {
4182     { "(bad)",  { XX } },
4183     { "(bad)",  { XX } },
4184     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4185     { "(bad)",  { XX } },
4186   },
4187
4188   /* PREFIX_VEX_FD */
4189   {
4190     { "(bad)",  { XX } },
4191     { "(bad)",  { XX } },
4192     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4193     { "(bad)",  { XX } },
4194   },
4195
4196   /* PREFIX_VEX_FE */
4197   {
4198     { "(bad)",  { XX } },
4199     { "(bad)",  { XX } },
4200     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4201     { "(bad)",  { XX } },
4202   },
4203
4204   /* PREFIX_VEX_3800 */
4205   {
4206     { "(bad)",  { XX } },
4207     { "(bad)",  { XX } },
4208     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4209     { "(bad)",  { XX } },
4210   },
4211
4212   /* PREFIX_VEX_3801 */
4213   {
4214     { "(bad)",  { XX } },
4215     { "(bad)",  { XX } },
4216     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4217     { "(bad)",  { XX } },
4218   },
4219
4220   /* PREFIX_VEX_3802 */
4221   {
4222     { "(bad)",  { XX } },
4223     { "(bad)",  { XX } },
4224     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4225     { "(bad)",  { XX } },
4226   },
4227
4228   /* PREFIX_VEX_3803 */
4229   {
4230     { "(bad)",  { XX } },
4231     { "(bad)",  { XX } },
4232     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4233     { "(bad)",  { XX } },
4234   },
4235
4236   /* PREFIX_VEX_3804 */
4237   {
4238     { "(bad)",  { XX } },
4239     { "(bad)",  { XX } },
4240     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4241     { "(bad)",  { XX } },
4242   },
4243
4244   /* PREFIX_VEX_3805 */
4245   {
4246     { "(bad)",  { XX } },
4247     { "(bad)",  { XX } },
4248     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4249     { "(bad)",  { XX } },
4250   },
4251
4252   /* PREFIX_VEX_3806 */
4253   {
4254     { "(bad)",  { XX } },
4255     { "(bad)",  { XX } },
4256     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4257     { "(bad)",  { XX } },
4258   },
4259
4260   /* PREFIX_VEX_3807 */
4261   {
4262     { "(bad)",  { XX } },
4263     { "(bad)",  { XX } },
4264     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4265     { "(bad)",  { XX } },
4266   },
4267
4268   /* PREFIX_VEX_3808 */
4269   {
4270     { "(bad)",  { XX } },
4271     { "(bad)",  { XX } },
4272     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4273     { "(bad)",  { XX } },
4274   },
4275
4276   /* PREFIX_VEX_3809 */
4277   {
4278     { "(bad)",  { XX } },
4279     { "(bad)",  { XX } },
4280     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4281     { "(bad)",  { XX } },
4282   },
4283
4284   /* PREFIX_VEX_380A */
4285   {
4286     { "(bad)",  { XX } },
4287     { "(bad)",  { XX } },
4288     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4289     { "(bad)",  { XX } },
4290   },
4291
4292   /* PREFIX_VEX_380B */
4293   {
4294     { "(bad)",  { XX } },
4295     { "(bad)",  { XX } },
4296     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4297     { "(bad)",  { XX } },
4298   },
4299
4300   /* PREFIX_VEX_380C */
4301   {
4302     { "(bad)",  { XX } },
4303     { "(bad)",  { XX } },
4304     { "vpermilps", { XM, Vex, EXx } },
4305     { "(bad)",  { XX } },
4306   },
4307
4308   /* PREFIX_VEX_380D */
4309   {
4310     { "(bad)",  { XX } },
4311     { "(bad)",  { XX } },
4312     { "vpermilpd", { XM, Vex, EXx } },
4313     { "(bad)",  { XX } },
4314   },
4315
4316   /* PREFIX_VEX_380E */
4317   {
4318     { "(bad)",  { XX } },
4319     { "(bad)",  { XX } },
4320     { "vtestps", { XM, EXx } },
4321     { "(bad)",  { XX } },
4322   },
4323
4324   /* PREFIX_VEX_380F */
4325   {
4326     { "(bad)",  { XX } },
4327     { "(bad)",  { XX } },
4328     { "vtestpd", { XM, EXx } },
4329     { "(bad)",  { XX } },
4330   },
4331
4332   /* PREFIX_VEX_3817 */
4333   {
4334     { "(bad)",  { XX } },
4335     { "(bad)",  { XX } },
4336     { "vptest", { XM, EXx } },
4337     { "(bad)",  { XX } },
4338   },
4339
4340   /* PREFIX_VEX_3818 */
4341   {
4342     { "(bad)",  { XX } },
4343     { "(bad)",  { XX } },
4344     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4345     { "(bad)",  { XX } },
4346   },
4347
4348   /* PREFIX_VEX_3819 */
4349   {
4350     { "(bad)",  { XX } },
4351     { "(bad)",  { XX } },
4352     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4353     { "(bad)",  { XX } },
4354   },
4355
4356   /* PREFIX_VEX_381A */
4357   {
4358     { "(bad)",  { XX } },
4359     { "(bad)",  { XX } },
4360     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4361     { "(bad)",  { XX } },
4362   },
4363
4364   /* PREFIX_VEX_381C */
4365   {
4366     { "(bad)",  { XX } },
4367     { "(bad)",  { XX } },
4368     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4369     { "(bad)",  { XX } },
4370   },
4371
4372   /* PREFIX_VEX_381D */
4373   {
4374     { "(bad)",  { XX } },
4375     { "(bad)",  { XX } },
4376     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4377     { "(bad)",  { XX } },
4378   },
4379
4380   /* PREFIX_VEX_381E */
4381   {
4382     { "(bad)",  { XX } },
4383     { "(bad)",  { XX } },
4384     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4385     { "(bad)",  { XX } },
4386   },
4387
4388   /* PREFIX_VEX_3820 */
4389   {
4390     { "(bad)",  { XX } },
4391     { "(bad)",  { XX } },
4392     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4393     { "(bad)",  { XX } },
4394   },
4395
4396   /* PREFIX_VEX_3821 */
4397   {
4398     { "(bad)",  { XX } },
4399     { "(bad)",  { XX } },
4400     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4401     { "(bad)",  { XX } },
4402   },
4403
4404   /* PREFIX_VEX_3822 */
4405   {
4406     { "(bad)",  { XX } },
4407     { "(bad)",  { XX } },
4408     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4409     { "(bad)",  { XX } },
4410   },
4411
4412   /* PREFIX_VEX_3823 */
4413   {
4414     { "(bad)",  { XX } },
4415     { "(bad)",  { XX } },
4416     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4417     { "(bad)",  { XX } },
4418   },
4419
4420   /* PREFIX_VEX_3824 */
4421   {
4422     { "(bad)",  { XX } },
4423     { "(bad)",  { XX } },
4424     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4425     { "(bad)",  { XX } },
4426   },
4427
4428   /* PREFIX_VEX_3825 */
4429   {
4430     { "(bad)",  { XX } },
4431     { "(bad)",  { XX } },
4432     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4433     { "(bad)",  { XX } },
4434   },
4435
4436   /* PREFIX_VEX_3828 */
4437   {
4438     { "(bad)",  { XX } },
4439     { "(bad)",  { XX } },
4440     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4441     { "(bad)",  { XX } },
4442   },
4443
4444   /* PREFIX_VEX_3829 */
4445   {
4446     { "(bad)",  { XX } },
4447     { "(bad)",  { XX } },
4448     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4449     { "(bad)",  { XX } },
4450   },
4451
4452   /* PREFIX_VEX_382A */
4453   {
4454     { "(bad)",  { XX } },
4455     { "(bad)",  { XX } },
4456     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4457     { "(bad)",  { XX } },
4458   },
4459
4460   /* PREFIX_VEX_382B */
4461   {
4462     { "(bad)",  { XX } },
4463     { "(bad)",  { XX } },
4464     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4465     { "(bad)",  { XX } },
4466   },
4467
4468   /* PREFIX_VEX_382C */
4469   {
4470     { "(bad)",  { XX } },
4471     { "(bad)",  { XX } },
4472      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4473     { "(bad)",  { XX } },
4474   },
4475
4476   /* PREFIX_VEX_382D */
4477   {
4478     { "(bad)",  { XX } },
4479     { "(bad)",  { XX } },
4480      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4481     { "(bad)",  { XX } },
4482   },
4483
4484   /* PREFIX_VEX_382E */
4485   {
4486     { "(bad)",  { XX } },
4487     { "(bad)",  { XX } },
4488      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4489     { "(bad)",  { XX } },
4490   },
4491
4492   /* PREFIX_VEX_382F */
4493   {
4494     { "(bad)",  { XX } },
4495     { "(bad)",  { XX } },
4496      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4497     { "(bad)",  { XX } },
4498   },
4499
4500   /* PREFIX_VEX_3830 */
4501   {
4502     { "(bad)",  { XX } },
4503     { "(bad)",  { XX } },
4504     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4505     { "(bad)",  { XX } },
4506   },
4507
4508   /* PREFIX_VEX_3831 */
4509   {
4510     { "(bad)",  { XX } },
4511     { "(bad)",  { XX } },
4512     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4513     { "(bad)",  { XX } },
4514   },
4515
4516   /* PREFIX_VEX_3832 */
4517   {
4518     { "(bad)",  { XX } },
4519     { "(bad)",  { XX } },
4520     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4521     { "(bad)",  { XX } },
4522   },
4523
4524   /* PREFIX_VEX_3833 */
4525   {
4526     { "(bad)",  { XX } },
4527     { "(bad)",  { XX } },
4528     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4529     { "(bad)",  { XX } },
4530   },
4531
4532   /* PREFIX_VEX_3834 */
4533   {
4534     { "(bad)",  { XX } },
4535     { "(bad)",  { XX } },
4536     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4537     { "(bad)",  { XX } },
4538   },
4539
4540   /* PREFIX_VEX_3835 */
4541   {
4542     { "(bad)",  { XX } },
4543     { "(bad)",  { XX } },
4544     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4545     { "(bad)",  { XX } },
4546   },
4547
4548   /* PREFIX_VEX_3837 */
4549   {
4550     { "(bad)",  { XX } },
4551     { "(bad)",  { XX } },
4552     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4553     { "(bad)",  { XX } },
4554   },
4555
4556   /* PREFIX_VEX_3838 */
4557   {
4558     { "(bad)",  { XX } },
4559     { "(bad)",  { XX } },
4560     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4561     { "(bad)",  { XX } },
4562   },
4563
4564   /* PREFIX_VEX_3839 */
4565   {
4566     { "(bad)",  { XX } },
4567     { "(bad)",  { XX } },
4568     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4569     { "(bad)",  { XX } },
4570   },
4571
4572   /* PREFIX_VEX_383A */
4573   {
4574     { "(bad)",  { XX } },
4575     { "(bad)",  { XX } },
4576     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4577     { "(bad)",  { XX } },
4578   },
4579
4580   /* PREFIX_VEX_383B */
4581   {
4582     { "(bad)",  { XX } },
4583     { "(bad)",  { XX } },
4584     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4585     { "(bad)",  { XX } },
4586   },
4587
4588   /* PREFIX_VEX_383C */
4589   {
4590     { "(bad)",  { XX } },
4591     { "(bad)",  { XX } },
4592     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4593     { "(bad)",  { XX } },
4594   },
4595
4596   /* PREFIX_VEX_383D */
4597   {
4598     { "(bad)",  { XX } },
4599     { "(bad)",  { XX } },
4600     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4601     { "(bad)",  { XX } },
4602   },
4603
4604   /* PREFIX_VEX_383E */
4605   {
4606     { "(bad)",  { XX } },
4607     { "(bad)",  { XX } },
4608     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4609     { "(bad)",  { XX } },
4610   },
4611
4612   /* PREFIX_VEX_383F */
4613   {
4614     { "(bad)",  { XX } },
4615     { "(bad)",  { XX } },
4616     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4617     { "(bad)",  { XX } },
4618   },
4619
4620   /* PREFIX_VEX_3840 */
4621   {
4622     { "(bad)",  { XX } },
4623     { "(bad)",  { XX } },
4624     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4625     { "(bad)",  { XX } },
4626   },
4627
4628   /* PREFIX_VEX_3841 */
4629   {
4630     { "(bad)",  { XX } },
4631     { "(bad)",  { XX } },
4632     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4633     { "(bad)",  { XX } },
4634   },
4635
4636   /* PREFIX_VEX_3896 */
4637   {
4638     { "(bad)",  { XX } },
4639     { "(bad)",  { XX } },
4640     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4641     { "(bad)",  { XX } },
4642   },
4643
4644   /* PREFIX_VEX_3897 */
4645   {
4646     { "(bad)",  { XX } },
4647     { "(bad)",  { XX } },
4648     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4649     { "(bad)",  { XX } },
4650   },
4651
4652   /* PREFIX_VEX_3898 */
4653   {
4654     { "(bad)",  { XX } },
4655     { "(bad)",  { XX } },
4656     { "vfmadd132p%XW", { XM, Vex, EXx } },
4657     { "(bad)",  { XX } },
4658   },
4659
4660   /* PREFIX_VEX_3899 */
4661   {
4662     { "(bad)",  { XX } },
4663     { "(bad)",  { XX } },
4664     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4665     { "(bad)",  { XX } },
4666   },
4667
4668   /* PREFIX_VEX_389A */
4669   {
4670     { "(bad)",  { XX } },
4671     { "(bad)",  { XX } },
4672     { "vfmsub132p%XW", { XM, Vex, EXx } },
4673     { "(bad)",  { XX } },
4674   },
4675
4676   /* PREFIX_VEX_389B */
4677   {
4678     { "(bad)",  { XX } },
4679     { "(bad)",  { XX } },
4680     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4681     { "(bad)",  { XX } },
4682   },
4683
4684   /* PREFIX_VEX_389C */
4685   {
4686     { "(bad)",  { XX } },
4687     { "(bad)",  { XX } },
4688     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4689     { "(bad)",  { XX } },
4690   },
4691
4692   /* PREFIX_VEX_389D */
4693   {
4694     { "(bad)",  { XX } },
4695     { "(bad)",  { XX } },
4696     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4697     { "(bad)",  { XX } },
4698   },
4699
4700   /* PREFIX_VEX_389E */
4701   {
4702     { "(bad)",  { XX } },
4703     { "(bad)",  { XX } },
4704     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4705     { "(bad)",  { XX } },
4706   },
4707
4708   /* PREFIX_VEX_389F */
4709   {
4710     { "(bad)",  { XX } },
4711     { "(bad)",  { XX } },
4712     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4713     { "(bad)",  { XX } },
4714   },
4715
4716   /* PREFIX_VEX_38A6 */
4717   {
4718     { "(bad)",  { XX } },
4719     { "(bad)",  { XX } },
4720     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4721     { "(bad)",  { XX } },
4722   },
4723
4724   /* PREFIX_VEX_38A7 */
4725   {
4726     { "(bad)",  { XX } },
4727     { "(bad)",  { XX } },
4728     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4729     { "(bad)",  { XX } },
4730   },
4731
4732   /* PREFIX_VEX_38A8 */
4733   {
4734     { "(bad)",  { XX } },
4735     { "(bad)",  { XX } },
4736     { "vfmadd213p%XW", { XM, Vex, EXx } },
4737     { "(bad)",  { XX } },
4738   },
4739
4740   /* PREFIX_VEX_38A9 */
4741   {
4742     { "(bad)",  { XX } },
4743     { "(bad)",  { XX } },
4744     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4745     { "(bad)",  { XX } },
4746   },
4747
4748   /* PREFIX_VEX_38AA */
4749   {
4750     { "(bad)",  { XX } },
4751     { "(bad)",  { XX } },
4752     { "vfmsub213p%XW", { XM, Vex, EXx } },
4753     { "(bad)",  { XX } },
4754   },
4755
4756   /* PREFIX_VEX_38AB */
4757   {
4758     { "(bad)",  { XX } },
4759     { "(bad)",  { XX } },
4760     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4761     { "(bad)",  { XX } },
4762   },
4763
4764   /* PREFIX_VEX_38AC */
4765   {
4766     { "(bad)",  { XX } },
4767     { "(bad)",  { XX } },
4768     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4769     { "(bad)",  { XX } },
4770   },
4771
4772   /* PREFIX_VEX_38AD */
4773   {
4774     { "(bad)",  { XX } },
4775     { "(bad)",  { XX } },
4776     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4777     { "(bad)",  { XX } },
4778   },
4779
4780   /* PREFIX_VEX_38AE */
4781   {
4782     { "(bad)",  { XX } },
4783     { "(bad)",  { XX } },
4784     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4785     { "(bad)",  { XX } },
4786   },
4787
4788   /* PREFIX_VEX_38AF */
4789   {
4790     { "(bad)",  { XX } },
4791     { "(bad)",  { XX } },
4792     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4793     { "(bad)",  { XX } },
4794   },
4795
4796   /* PREFIX_VEX_38B6 */
4797   {
4798     { "(bad)",  { XX } },
4799     { "(bad)",  { XX } },
4800     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4801     { "(bad)",  { XX } },
4802   },
4803
4804   /* PREFIX_VEX_38B7 */
4805   {
4806     { "(bad)",  { XX } },
4807     { "(bad)",  { XX } },
4808     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4809     { "(bad)",  { XX } },
4810   },
4811
4812   /* PREFIX_VEX_38B8 */
4813   {
4814     { "(bad)",  { XX } },
4815     { "(bad)",  { XX } },
4816     { "vfmadd231p%XW", { XM, Vex, EXx } },
4817     { "(bad)",  { XX } },
4818   },
4819
4820   /* PREFIX_VEX_38B9 */
4821   {
4822     { "(bad)",  { XX } },
4823     { "(bad)",  { XX } },
4824     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4825     { "(bad)",  { XX } },
4826   },
4827
4828   /* PREFIX_VEX_38BA */
4829   {
4830     { "(bad)",  { XX } },
4831     { "(bad)",  { XX } },
4832     { "vfmsub231p%XW", { XM, Vex, EXx } },
4833     { "(bad)",  { XX } },
4834   },
4835
4836   /* PREFIX_VEX_38BB */
4837   {
4838     { "(bad)",  { XX } },
4839     { "(bad)",  { XX } },
4840     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4841     { "(bad)",  { XX } },
4842   },
4843
4844   /* PREFIX_VEX_38BC */
4845   {
4846     { "(bad)",  { XX } },
4847     { "(bad)",  { XX } },
4848     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4849     { "(bad)",  { XX } },
4850   },
4851
4852   /* PREFIX_VEX_38BD */
4853   {
4854     { "(bad)",  { XX } },
4855     { "(bad)",  { XX } },
4856     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4857     { "(bad)",  { XX } },
4858   },
4859
4860   /* PREFIX_VEX_38BE */
4861   {
4862     { "(bad)",  { XX } },
4863     { "(bad)",  { XX } },
4864     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4865     { "(bad)",  { XX } },
4866   },
4867
4868   /* PREFIX_VEX_38BF */
4869   {
4870     { "(bad)",  { XX } },
4871     { "(bad)",  { XX } },
4872     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4873     { "(bad)",  { XX } },
4874   },
4875
4876   /* PREFIX_VEX_38DB */
4877   {
4878     { "(bad)",  { XX } },
4879     { "(bad)",  { XX } },
4880     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4881     { "(bad)",  { XX } },
4882   },
4883
4884   /* PREFIX_VEX_38DC */
4885   {
4886     { "(bad)",  { XX } },
4887     { "(bad)",  { XX } },
4888     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4889     { "(bad)",  { XX } },
4890   },
4891
4892   /* PREFIX_VEX_38DD */
4893   {
4894     { "(bad)",  { XX } },
4895     { "(bad)",  { XX } },
4896     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4897     { "(bad)",  { XX } },
4898   },
4899
4900   /* PREFIX_VEX_38DE */
4901   {
4902     { "(bad)",  { XX } },
4903     { "(bad)",  { XX } },
4904     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4905     { "(bad)",  { XX } },
4906   },
4907
4908   /* PREFIX_VEX_38DF */
4909   {
4910     { "(bad)",  { XX } },
4911     { "(bad)",  { XX } },
4912     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4913     { "(bad)",  { XX } },
4914   },
4915
4916   /* PREFIX_VEX_3A04 */
4917   {
4918     { "(bad)",  { XX } },
4919     { "(bad)",  { XX } },
4920     { "vpermilps", { XM, EXx, Ib } },
4921     { "(bad)",  { XX } },
4922   },
4923
4924   /* PREFIX_VEX_3A05 */
4925   {
4926     { "(bad)",  { XX } },
4927     { "(bad)",  { XX } },
4928     { "vpermilpd", { XM, EXx, Ib } },
4929     { "(bad)",  { XX } },
4930   },
4931
4932   /* PREFIX_VEX_3A06 */
4933   {
4934     { "(bad)",  { XX } },
4935     { "(bad)",  { XX } },
4936     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4937     { "(bad)",  { XX } },
4938   },
4939
4940   /* PREFIX_VEX_3A08 */
4941   {
4942     { "(bad)",  { XX } },
4943     { "(bad)",  { XX } },
4944     { "vroundps", { XM, EXx, Ib } },
4945     { "(bad)",  { XX } },
4946   },
4947
4948   /* PREFIX_VEX_3A09 */
4949   {
4950     { "(bad)",  { XX } },
4951     { "(bad)",  { XX } },
4952     { "vroundpd", { XM, EXx, Ib } },
4953     { "(bad)",  { XX } },
4954   },
4955
4956   /* PREFIX_VEX_3A0A */
4957   {
4958     { "(bad)",  { XX } },
4959     { "(bad)",  { XX } },
4960     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4961     { "(bad)",  { XX } },
4962   },
4963
4964   /* PREFIX_VEX_3A0B */
4965   {
4966     { "(bad)",  { XX } },
4967     { "(bad)",  { XX } },
4968     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4969     { "(bad)",  { XX } },
4970   },
4971
4972   /* PREFIX_VEX_3A0C */
4973   {
4974     { "(bad)",  { XX } },
4975     { "(bad)",  { XX } },
4976     { "vblendps", { XM, Vex, EXx, Ib } },
4977     { "(bad)",  { XX } },
4978   },
4979
4980   /* PREFIX_VEX_3A0D */
4981   {
4982     { "(bad)",  { XX } },
4983     { "(bad)",  { XX } },
4984     { "vblendpd", { XM, Vex, EXx, Ib } },
4985     { "(bad)",  { XX } },
4986   },
4987
4988   /* PREFIX_VEX_3A0E */
4989   {
4990     { "(bad)",  { XX } },
4991     { "(bad)",  { XX } },
4992     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4993     { "(bad)",  { XX } },
4994   },
4995
4996   /* PREFIX_VEX_3A0F */
4997   {
4998     { "(bad)",  { XX } },
4999     { "(bad)",  { XX } },
5000     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
5001     { "(bad)",  { XX } },
5002   },
5003
5004   /* PREFIX_VEX_3A14 */
5005   {
5006     { "(bad)",  { XX } },
5007     { "(bad)",  { XX } },
5008     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
5009     { "(bad)",  { XX } },
5010   },
5011
5012   /* PREFIX_VEX_3A15 */
5013   {
5014     { "(bad)",  { XX } },
5015     { "(bad)",  { XX } },
5016     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
5017     { "(bad)",  { XX } },
5018   },
5019
5020   /* PREFIX_VEX_3A16 */
5021   {
5022     { "(bad)",  { XX } },
5023     { "(bad)",  { XX } },
5024     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
5025     { "(bad)",  { XX } },
5026   },
5027
5028   /* PREFIX_VEX_3A17 */
5029   {
5030     { "(bad)",  { XX } },
5031     { "(bad)",  { XX } },
5032     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5033     { "(bad)",  { XX } },
5034   },
5035
5036   /* PREFIX_VEX_3A18 */
5037   {
5038     { "(bad)",  { XX } },
5039     { "(bad)",  { XX } },
5040     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5041     { "(bad)",  { XX } },
5042   },
5043
5044   /* PREFIX_VEX_3A19 */
5045   {
5046     { "(bad)",  { XX } },
5047     { "(bad)",  { XX } },
5048     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5049     { "(bad)",  { XX } },
5050   },
5051
5052   /* PREFIX_VEX_3A20 */
5053   {
5054     { "(bad)",  { XX } },
5055     { "(bad)",  { XX } },
5056     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5057     { "(bad)",  { XX } },
5058   },
5059
5060   /* PREFIX_VEX_3A21 */
5061   {
5062     { "(bad)",  { XX } },
5063     { "(bad)",  { XX } },
5064     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5065     { "(bad)",  { XX } },
5066   },
5067
5068   /* PREFIX_VEX_3A22 */
5069   {
5070     { "(bad)",  { XX } },
5071     { "(bad)",  { XX } },
5072     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5073     { "(bad)",  { XX } },
5074   },
5075
5076   /* PREFIX_VEX_3A40 */
5077   {
5078     { "(bad)",  { XX } },
5079     { "(bad)",  { XX } },
5080     { "vdpps",  { XM, Vex, EXx, Ib } },
5081     { "(bad)",  { XX } },
5082   },
5083
5084   /* PREFIX_VEX_3A41 */
5085   {
5086     { "(bad)",  { XX } },
5087     { "(bad)",  { XX } },
5088     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5089     { "(bad)",  { XX } },
5090   },
5091
5092   /* PREFIX_VEX_3A42 */
5093   {
5094     { "(bad)",  { XX } },
5095     { "(bad)",  { XX } },
5096     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5097     { "(bad)",  { XX } },
5098   },
5099
5100   /* PREFIX_VEX_3A44 */
5101   {
5102     { "(bad)",  { XX } },
5103     { "(bad)",  { XX } },
5104     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5105     { "(bad)",  { XX } },
5106   },
5107
5108   /* PREFIX_VEX_3A4A */
5109   {
5110     { "(bad)",  { XX } },
5111     { "(bad)",  { XX } },
5112     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
5113     { "(bad)",  { XX } },
5114   },
5115
5116   /* PREFIX_VEX_3A4B */
5117   {
5118     { "(bad)",  { XX } },
5119     { "(bad)",  { XX } },
5120     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
5121     { "(bad)",  { XX } },
5122   },
5123
5124   /* PREFIX_VEX_3A4C */
5125   {
5126     { "(bad)",  { XX } },
5127     { "(bad)",  { XX } },
5128     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5129     { "(bad)",  { XX } },
5130   },
5131
5132   /* PREFIX_VEX_3A5C */
5133   {
5134     { "(bad)",  { XX } },
5135     { "(bad)",  { XX } },
5136     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5137     { "(bad)",  { XX } },
5138   },
5139
5140   /* PREFIX_VEX_3A5D */
5141   {
5142     { "(bad)",  { XX } },
5143     { "(bad)",  { XX } },
5144     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5145     { "(bad)",  { XX } },
5146   },
5147
5148   /* PREFIX_VEX_3A5E */
5149   {
5150     { "(bad)",  { XX } },
5151     { "(bad)",  { XX } },
5152     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5153     { "(bad)",  { XX } },
5154   },
5155
5156   /* PREFIX_VEX_3A5F */
5157   {
5158     { "(bad)",  { XX } },
5159     { "(bad)",  { XX } },
5160     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5161     { "(bad)",  { XX } },
5162   },
5163
5164   /* PREFIX_VEX_3A60 */
5165   {
5166     { "(bad)",  { XX } },
5167     { "(bad)",  { XX } },
5168     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5169     { "(bad)",  { XX } },
5170   },
5171
5172   /* PREFIX_VEX_3A61 */
5173   {
5174     { "(bad)",  { XX } },
5175     { "(bad)",  { XX } },
5176     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5177     { "(bad)",  { XX } },
5178   },
5179
5180   /* PREFIX_VEX_3A62 */
5181   {
5182     { "(bad)",  { XX } },
5183     { "(bad)",  { XX } },
5184     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5185     { "(bad)",  { XX } },
5186   },
5187
5188   /* PREFIX_VEX_3A63 */
5189   {
5190     { "(bad)",  { XX } },
5191     { "(bad)",  { XX } },
5192     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5193     { "(bad)",  { XX } },
5194   },
5195
5196   /* PREFIX_VEX_3A68 */
5197   {
5198     { "(bad)",  { XX } },
5199     { "(bad)",  { XX } },
5200     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5201     { "(bad)",  { XX } },
5202   },
5203
5204   /* PREFIX_VEX_3A69 */
5205   {
5206     { "(bad)",  { XX } },
5207     { "(bad)",  { XX } },
5208     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5209     { "(bad)",  { XX } },
5210   },
5211
5212   /* PREFIX_VEX_3A6A */
5213   {
5214     { "(bad)",  { XX } },
5215     { "(bad)",  { XX } },
5216     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5217     { "(bad)",  { XX } },
5218   },
5219
5220   /* PREFIX_VEX_3A6B */
5221   {
5222     { "(bad)",  { XX } },
5223     { "(bad)",  { XX } },
5224     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5225     { "(bad)",  { XX } },
5226   },
5227
5228   /* PREFIX_VEX_3A6C */
5229   {
5230     { "(bad)",  { XX } },
5231     { "(bad)",  { XX } },
5232     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5233     { "(bad)",  { XX } },
5234   },
5235
5236   /* PREFIX_VEX_3A6D */
5237   {
5238     { "(bad)",  { XX } },
5239     { "(bad)",  { XX } },
5240     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5241     { "(bad)",  { XX } },
5242   },
5243
5244   /* PREFIX_VEX_3A6E */
5245   {
5246     { "(bad)",  { XX } },
5247     { "(bad)",  { XX } },
5248     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5249     { "(bad)",  { XX } },
5250   },
5251
5252   /* PREFIX_VEX_3A6F */
5253   {
5254     { "(bad)",  { XX } },
5255     { "(bad)",  { XX } },
5256     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5257     { "(bad)",  { XX } },
5258   },
5259
5260   /* PREFIX_VEX_3A78 */
5261   {
5262     { "(bad)",  { XX } },
5263     { "(bad)",  { XX } },
5264     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5265     { "(bad)",  { XX } },
5266   },
5267
5268   /* PREFIX_VEX_3A79 */
5269   {
5270     { "(bad)",  { XX } },
5271     { "(bad)",  { XX } },
5272     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5273     { "(bad)",  { XX } },
5274   },
5275
5276   /* PREFIX_VEX_3A7A */
5277   {
5278     { "(bad)",  { XX } },
5279     { "(bad)",  { XX } },
5280     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5281     { "(bad)",  { XX } },
5282   },
5283
5284   /* PREFIX_VEX_3A7B */
5285   {
5286     { "(bad)",  { XX } },
5287     { "(bad)",  { XX } },
5288     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5289     { "(bad)",  { XX } },
5290   },
5291
5292   /* PREFIX_VEX_3A7C */
5293   {
5294     { "(bad)",  { XX } },
5295     { "(bad)",  { XX } },
5296     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5297     { "(bad)",  { XX } },
5298   },
5299
5300   /* PREFIX_VEX_3A7D */
5301   {
5302     { "(bad)",  { XX } },
5303     { "(bad)",  { XX } },
5304     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5305     { "(bad)",  { XX } },
5306   },
5307
5308   /* PREFIX_VEX_3A7E */
5309   {
5310     { "(bad)",  { XX } },
5311     { "(bad)",  { XX } },
5312     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5313     { "(bad)",  { XX } },
5314   },
5315
5316   /* PREFIX_VEX_3A7F */
5317   {
5318     { "(bad)",  { XX } },
5319     { "(bad)",  { XX } },
5320     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5321     { "(bad)",  { XX } },
5322   },
5323
5324   /* PREFIX_VEX_3ADF */
5325   {
5326     { "(bad)",  { XX } },
5327     { "(bad)",  { XX } },
5328     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5329     { "(bad)",  { XX } },
5330   },
5331 };
5332
5333 static const struct dis386 x86_64_table[][2] = {
5334   /* X86_64_06 */
5335   {
5336     { "push{T|}", { es } },
5337     { "(bad)", { XX } },
5338   },
5339
5340   /* X86_64_07 */
5341   {
5342     { "pop{T|}", { es } },
5343     { "(bad)", { XX } },
5344   },
5345
5346   /* X86_64_0D */
5347   {
5348     { "push{T|}", { cs } },
5349     { "(bad)", { XX } },
5350   },
5351
5352   /* X86_64_16 */
5353   {
5354     { "push{T|}", { ss } },
5355     { "(bad)", { XX } },
5356   },
5357
5358   /* X86_64_17 */
5359   {
5360     { "pop{T|}", { ss } },
5361     { "(bad)", { XX } },
5362   },
5363
5364   /* X86_64_1E */
5365   {
5366     { "push{T|}", { ds } },
5367     { "(bad)", { XX } },
5368   },
5369
5370   /* X86_64_1F */
5371   {
5372     { "pop{T|}", { ds } },
5373     { "(bad)", { XX } },
5374   },
5375
5376   /* X86_64_27 */
5377   {
5378     { "daa", { XX } },
5379     { "(bad)", { XX } },
5380   },
5381
5382   /* X86_64_2F */
5383   {
5384     { "das", { XX } },
5385     { "(bad)", { XX } },
5386   },
5387
5388   /* X86_64_37 */
5389   {
5390     { "aaa", { XX } },
5391     { "(bad)", { XX } },
5392   },
5393
5394   /* X86_64_3F */
5395   {
5396     { "aas", { XX } },
5397     { "(bad)", { XX } },
5398   },
5399
5400   /* X86_64_60 */
5401   {
5402     { "pusha{P|}", { XX } },
5403     { "(bad)", { XX } },
5404   },
5405
5406   /* X86_64_61 */
5407   {
5408     { "popa{P|}", { XX } },
5409     { "(bad)", { XX } },
5410   },
5411
5412   /* X86_64_62 */
5413   {
5414     { MOD_TABLE (MOD_62_32BIT) },
5415     { "(bad)", { XX } },
5416   },
5417
5418   /* X86_64_63 */
5419   {
5420     { "arpl", { Ew, Gw } },
5421     { "movs{lq|xd}", { Gv, Ed } },
5422   },
5423
5424   /* X86_64_6D */
5425   {
5426     { "ins{R|}", { Yzr, indirDX } },
5427     { "ins{G|}", { Yzr, indirDX } },
5428   },
5429
5430   /* X86_64_6F */
5431   {
5432     { "outs{R|}", { indirDXr, Xz } },
5433     { "outs{G|}", { indirDXr, Xz } },
5434   },
5435
5436   /* X86_64_9A */
5437   {
5438     { "Jcall{T|}", { Ap } },
5439     { "(bad)", { XX } },
5440   },
5441
5442   /* X86_64_C4 */
5443   {
5444     { MOD_TABLE (MOD_C4_32BIT) },
5445     { VEX_C4_TABLE (VEX_0F) },
5446   },
5447
5448   /* X86_64_C5 */
5449   {
5450     { MOD_TABLE (MOD_C5_32BIT) },
5451     { VEX_C5_TABLE (VEX_0F) },
5452   },
5453
5454   /* X86_64_CE */
5455   {
5456     { "into", { XX } },
5457     { "(bad)", { XX } },
5458   },
5459
5460   /* X86_64_D4 */
5461   {
5462     { "aam", { sIb } },
5463     { "(bad)", { XX } },
5464   },
5465
5466   /* X86_64_D5 */
5467   {
5468     { "aad", { sIb } },
5469     { "(bad)", { XX } },
5470   },
5471
5472   /* X86_64_EA */
5473   {
5474     { "Jjmp{T|}", { Ap } },
5475     { "(bad)", { XX } },
5476   },
5477
5478   /* X86_64_0F01_REG_0 */
5479   {
5480     { "sgdt{Q|IQ}", { M } },
5481     { "sgdt", { M } },
5482   },
5483
5484   /* X86_64_0F01_REG_1 */
5485   {
5486     { "sidt{Q|IQ}", { M } },
5487     { "sidt", { M } },
5488   },
5489
5490   /* X86_64_0F01_REG_2 */
5491   {
5492     { "lgdt{Q|Q}", { M } },
5493     { "lgdt", { M } },
5494   },
5495
5496   /* X86_64_0F01_REG_3 */
5497   {
5498     { "lidt{Q|Q}", { M } },
5499     { "lidt", { M } },
5500   },
5501 };
5502
5503 static const struct dis386 three_byte_table[][256] = {
5504
5505   /* THREE_BYTE_0F38 */
5506   {
5507     /* 00 */
5508     { "pshufb",         { MX, EM } },
5509     { "phaddw",         { MX, EM } },
5510     { "phaddd",         { MX, EM } },
5511     { "phaddsw",        { MX, EM } },
5512     { "pmaddubsw",      { MX, EM } },
5513     { "phsubw",         { MX, EM } },
5514     { "phsubd",         { MX, EM } },
5515     { "phsubsw",        { MX, EM } },
5516     /* 08 */
5517     { "psignb",         { MX, EM } },
5518     { "psignw",         { MX, EM } },
5519     { "psignd",         { MX, EM } },
5520     { "pmulhrsw",       { MX, EM } },
5521     { "(bad)",          { XX } },
5522     { "(bad)",          { XX } },
5523     { "(bad)",          { XX } },
5524     { "(bad)",          { XX } },
5525     /* 10 */
5526     { PREFIX_TABLE (PREFIX_0F3810) },
5527     { "(bad)",          { XX } },
5528     { "(bad)",          { XX } },
5529     { "(bad)",          { XX } },
5530     { PREFIX_TABLE (PREFIX_0F3814) },
5531     { PREFIX_TABLE (PREFIX_0F3815) },
5532     { "(bad)",          { XX } },
5533     { PREFIX_TABLE (PREFIX_0F3817) },
5534     /* 18 */
5535     { "(bad)",          { XX } },
5536     { "(bad)",          { XX } },
5537     { "(bad)",          { XX } },
5538     { "(bad)",          { XX } },
5539     { "pabsb",          { MX, EM } },
5540     { "pabsw",          { MX, EM } },
5541     { "pabsd",          { MX, EM } },
5542     { "(bad)",          { XX } },
5543     /* 20 */
5544     { PREFIX_TABLE (PREFIX_0F3820) },
5545     { PREFIX_TABLE (PREFIX_0F3821) },
5546     { PREFIX_TABLE (PREFIX_0F3822) },
5547     { PREFIX_TABLE (PREFIX_0F3823) },
5548     { PREFIX_TABLE (PREFIX_0F3824) },
5549     { PREFIX_TABLE (PREFIX_0F3825) },
5550     { "(bad)",          { XX } },
5551     { "(bad)",          { XX } },
5552     /* 28 */
5553     { PREFIX_TABLE (PREFIX_0F3828) },
5554     { PREFIX_TABLE (PREFIX_0F3829) },
5555     { PREFIX_TABLE (PREFIX_0F382A) },
5556     { PREFIX_TABLE (PREFIX_0F382B) },
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     /* 30 */
5562     { PREFIX_TABLE (PREFIX_0F3830) },
5563     { PREFIX_TABLE (PREFIX_0F3831) },
5564     { PREFIX_TABLE (PREFIX_0F3832) },
5565     { PREFIX_TABLE (PREFIX_0F3833) },
5566     { PREFIX_TABLE (PREFIX_0F3834) },
5567     { PREFIX_TABLE (PREFIX_0F3835) },
5568     { "(bad)",          { XX } },
5569     { PREFIX_TABLE (PREFIX_0F3837) },
5570     /* 38 */
5571     { PREFIX_TABLE (PREFIX_0F3838) },
5572     { PREFIX_TABLE (PREFIX_0F3839) },
5573     { PREFIX_TABLE (PREFIX_0F383A) },
5574     { PREFIX_TABLE (PREFIX_0F383B) },
5575     { PREFIX_TABLE (PREFIX_0F383C) },
5576     { PREFIX_TABLE (PREFIX_0F383D) },
5577     { PREFIX_TABLE (PREFIX_0F383E) },
5578     { PREFIX_TABLE (PREFIX_0F383F) },
5579     /* 40 */
5580     { PREFIX_TABLE (PREFIX_0F3840) },
5581     { PREFIX_TABLE (PREFIX_0F3841) },
5582     { "(bad)",          { XX } },
5583     { "(bad)",          { XX } },
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     { "(bad)",          { XX } },
5587     { "(bad)",          { XX } },
5588     /* 48 */
5589     { "(bad)",          { XX } },
5590     { "(bad)",          { XX } },
5591     { "(bad)",          { XX } },
5592     { "(bad)",          { XX } },
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     /* 50 */
5598     { "(bad)",          { XX } },
5599     { "(bad)",          { XX } },
5600     { "(bad)",          { XX } },
5601     { "(bad)",          { XX } },
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     /* 58 */
5607     { "(bad)",          { XX } },
5608     { "(bad)",          { XX } },
5609     { "(bad)",          { XX } },
5610     { "(bad)",          { XX } },
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     /* 60 */
5616     { "(bad)",          { XX } },
5617     { "(bad)",          { XX } },
5618     { "(bad)",          { XX } },
5619     { "(bad)",          { XX } },
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     /* 68 */
5625     { "(bad)",          { XX } },
5626     { "(bad)",          { XX } },
5627     { "(bad)",          { XX } },
5628     { "(bad)",          { XX } },
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     /* 70 */
5634     { "(bad)",          { XX } },
5635     { "(bad)",          { XX } },
5636     { "(bad)",          { XX } },
5637     { "(bad)",          { XX } },
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     /* 78 */
5643     { "(bad)",          { XX } },
5644     { "(bad)",          { XX } },
5645     { "(bad)",          { XX } },
5646     { "(bad)",          { XX } },
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     /* 80 */
5652     { PREFIX_TABLE (PREFIX_0F3880) },
5653     { PREFIX_TABLE (PREFIX_0F3881) },
5654     { "(bad)",          { XX } },
5655     { "(bad)",          { XX } },
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     /* 88 */
5661     { "(bad)",          { XX } },
5662     { "(bad)",          { XX } },
5663     { "(bad)",          { XX } },
5664     { "(bad)",          { XX } },
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     /* 90 */
5670     { "(bad)",          { XX } },
5671     { "(bad)",          { XX } },
5672     { "(bad)",          { XX } },
5673     { "(bad)",          { XX } },
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     /* 98 */
5679     { "(bad)",          { XX } },
5680     { "(bad)",          { XX } },
5681     { "(bad)",          { XX } },
5682     { "(bad)",          { XX } },
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     /* a0 */
5688     { "(bad)",          { XX } },
5689     { "(bad)",          { XX } },
5690     { "(bad)",          { XX } },
5691     { "(bad)",          { XX } },
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     /* a8 */
5697     { "(bad)",          { XX } },
5698     { "(bad)",          { XX } },
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     /* b0 */
5706     { "(bad)",          { XX } },
5707     { "(bad)",          { XX } },
5708     { "(bad)",          { XX } },
5709     { "(bad)",          { XX } },
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     /* b8 */
5715     { "(bad)",          { XX } },
5716     { "(bad)",          { XX } },
5717     { "(bad)",          { XX } },
5718     { "(bad)",          { XX } },
5719     { "(bad)",          { XX } },
5720     { "(bad)",          { XX } },
5721     { "(bad)",          { XX } },
5722     { "(bad)",          { XX } },
5723     /* c0 */
5724     { "(bad)",          { XX } },
5725     { "(bad)",          { XX } },
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     /* c8 */
5733     { "(bad)",          { XX } },
5734     { "(bad)",          { XX } },
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     /* d0 */
5742     { "(bad)",          { XX } },
5743     { "(bad)",          { XX } },
5744     { "(bad)",          { XX } },
5745     { "(bad)",          { XX } },
5746     { "(bad)",          { XX } },
5747     { "(bad)",          { XX } },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     /* d8 */
5751     { "(bad)",          { XX } },
5752     { "(bad)",          { XX } },
5753     { "(bad)",          { XX } },
5754     { PREFIX_TABLE (PREFIX_0F38DB) },
5755     { PREFIX_TABLE (PREFIX_0F38DC) },
5756     { PREFIX_TABLE (PREFIX_0F38DD) },
5757     { PREFIX_TABLE (PREFIX_0F38DE) },
5758     { PREFIX_TABLE (PREFIX_0F38DF) },
5759     /* e0 */
5760     { "(bad)",          { XX } },
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763     { "(bad)",          { XX } },
5764     { "(bad)",          { XX } },
5765     { "(bad)",          { XX } },
5766     { "(bad)",          { XX } },
5767     { "(bad)",          { XX } },
5768     /* e8 */
5769     { "(bad)",          { XX } },
5770     { "(bad)",          { XX } },
5771     { "(bad)",          { XX } },
5772     { "(bad)",          { XX } },
5773     { "(bad)",          { XX } },
5774     { "(bad)",          { XX } },
5775     { "(bad)",          { XX } },
5776     { "(bad)",          { XX } },
5777     /* f0 */
5778     { PREFIX_TABLE (PREFIX_0F38F0) },
5779     { PREFIX_TABLE (PREFIX_0F38F1) },
5780     { "(bad)",          { XX } },
5781     { "(bad)",          { XX } },
5782     { "(bad)",          { XX } },
5783     { "(bad)",          { XX } },
5784     { "(bad)",          { XX } },
5785     { "(bad)",          { XX } },
5786     /* f8 */
5787     { "(bad)",          { XX } },
5788     { "(bad)",          { XX } },
5789     { "(bad)",          { XX } },
5790     { "(bad)",          { XX } },
5791     { "(bad)",          { XX } },
5792     { "(bad)",          { XX } },
5793     { "(bad)",          { XX } },
5794     { "(bad)",          { XX } },
5795   },
5796   /* THREE_BYTE_0F3A */
5797   {
5798     /* 00 */
5799     { "(bad)",          { XX } },
5800     { "(bad)",          { XX } },
5801     { "(bad)",          { XX } },
5802     { "(bad)",          { XX } },
5803     { "(bad)",          { XX } },
5804     { "(bad)",          { XX } },
5805     { "(bad)",          { XX } },
5806     { "(bad)",          { XX } },
5807     /* 08 */
5808     { PREFIX_TABLE (PREFIX_0F3A08) },
5809     { PREFIX_TABLE (PREFIX_0F3A09) },
5810     { PREFIX_TABLE (PREFIX_0F3A0A) },
5811     { PREFIX_TABLE (PREFIX_0F3A0B) },
5812     { PREFIX_TABLE (PREFIX_0F3A0C) },
5813     { PREFIX_TABLE (PREFIX_0F3A0D) },
5814     { PREFIX_TABLE (PREFIX_0F3A0E) },
5815     { "palignr",        { MX, EM, Ib } },
5816     /* 10 */
5817     { "(bad)",          { XX } },
5818     { "(bad)",          { XX } },
5819     { "(bad)",          { XX } },
5820     { "(bad)",          { XX } },
5821     { PREFIX_TABLE (PREFIX_0F3A14) },
5822     { PREFIX_TABLE (PREFIX_0F3A15) },
5823     { PREFIX_TABLE (PREFIX_0F3A16) },
5824     { PREFIX_TABLE (PREFIX_0F3A17) },
5825     /* 18 */
5826     { "(bad)",          { XX } },
5827     { "(bad)",          { XX } },
5828     { "(bad)",          { XX } },
5829     { "(bad)",          { XX } },
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     { "(bad)",          { XX } },
5833     { "(bad)",          { XX } },
5834     /* 20 */
5835     { PREFIX_TABLE (PREFIX_0F3A20) },
5836     { PREFIX_TABLE (PREFIX_0F3A21) },
5837     { PREFIX_TABLE (PREFIX_0F3A22) },
5838     { "(bad)",          { XX } },
5839     { "(bad)",          { XX } },
5840     { "(bad)",          { XX } },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     /* 28 */
5844     { "(bad)",          { XX } },
5845     { "(bad)",          { XX } },
5846     { "(bad)",          { XX } },
5847     { "(bad)",          { XX } },
5848     { "(bad)",          { XX } },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     /* 30 */
5853     { "(bad)",          { XX } },
5854     { "(bad)",          { XX } },
5855     { "(bad)",          { XX } },
5856     { "(bad)",          { XX } },
5857     { "(bad)",          { XX } },
5858     { "(bad)",          { XX } },
5859     { "(bad)",          { XX } },
5860     { "(bad)",          { XX } },
5861     /* 38 */
5862     { "(bad)",          { XX } },
5863     { "(bad)",          { XX } },
5864     { "(bad)",          { XX } },
5865     { "(bad)",          { XX } },
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     /* 40 */
5871     { PREFIX_TABLE (PREFIX_0F3A40) },
5872     { PREFIX_TABLE (PREFIX_0F3A41) },
5873     { PREFIX_TABLE (PREFIX_0F3A42) },
5874     { "(bad)",          { XX } },
5875     { PREFIX_TABLE (PREFIX_0F3A44) },
5876     { "(bad)",          { XX } },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     /* 48 */
5880     { "(bad)",          { XX } },
5881     { "(bad)",          { XX } },
5882     { "(bad)",          { XX } },
5883     { "(bad)",          { XX } },
5884     { "(bad)",          { XX } },
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     /* 50 */
5889     { "(bad)",          { XX } },
5890     { "(bad)",          { XX } },
5891     { "(bad)",          { XX } },
5892     { "(bad)",          { XX } },
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     /* 58 */
5898     { "(bad)",          { XX } },
5899     { "(bad)",          { XX } },
5900     { "(bad)",          { XX } },
5901     { "(bad)",          { XX } },
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     /* 60 */
5907     { PREFIX_TABLE (PREFIX_0F3A60) },
5908     { PREFIX_TABLE (PREFIX_0F3A61) },
5909     { PREFIX_TABLE (PREFIX_0F3A62) },
5910     { PREFIX_TABLE (PREFIX_0F3A63) },
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     /* 68 */
5916     { "(bad)",          { XX } },
5917     { "(bad)",          { XX } },
5918     { "(bad)",          { XX } },
5919     { "(bad)",          { XX } },
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     /* 70 */
5925     { "(bad)",          { XX } },
5926     { "(bad)",          { XX } },
5927     { "(bad)",          { XX } },
5928     { "(bad)",          { XX } },
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     /* 78 */
5934     { "(bad)",          { XX } },
5935     { "(bad)",          { XX } },
5936     { "(bad)",          { XX } },
5937     { "(bad)",          { XX } },
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     /* 80 */
5943     { "(bad)",          { XX } },
5944     { "(bad)",          { XX } },
5945     { "(bad)",          { XX } },
5946     { "(bad)",          { XX } },
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     /* 88 */
5952     { "(bad)",          { XX } },
5953     { "(bad)",          { XX } },
5954     { "(bad)",          { XX } },
5955     { "(bad)",          { XX } },
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     /* 90 */
5961     { "(bad)",          { XX } },
5962     { "(bad)",          { XX } },
5963     { "(bad)",          { XX } },
5964     { "(bad)",          { XX } },
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     /* 98 */
5970     { "(bad)",          { XX } },
5971     { "(bad)",          { XX } },
5972     { "(bad)",          { XX } },
5973     { "(bad)",          { XX } },
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     /* a0 */
5979     { "(bad)",          { XX } },
5980     { "(bad)",          { XX } },
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     /* a8 */
5988     { "(bad)",          { XX } },
5989     { "(bad)",          { XX } },
5990     { "(bad)",          { XX } },
5991     { "(bad)",          { XX } },
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     /* b0 */
5997     { "(bad)",          { XX } },
5998     { "(bad)",          { XX } },
5999     { "(bad)",          { XX } },
6000     { "(bad)",          { XX } },
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     /* b8 */
6006     { "(bad)",          { XX } },
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     /* c0 */
6015     { "(bad)",          { XX } },
6016     { "(bad)",          { XX } },
6017     { "(bad)",          { XX } },
6018     { "(bad)",          { XX } },
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     /* c8 */
6024     { "(bad)",          { XX } },
6025     { "(bad)",          { XX } },
6026     { "(bad)",          { XX } },
6027     { "(bad)",          { XX } },
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     /* d0 */
6033     { "(bad)",          { XX } },
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     { "(bad)",          { XX } },
6039     { "(bad)",          { XX } },
6040     { "(bad)",          { XX } },
6041     /* d8 */
6042     { "(bad)",          { XX } },
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { PREFIX_TABLE (PREFIX_0F3ADF) },
6050     /* e0 */
6051     { "(bad)",          { XX } },
6052     { "(bad)",          { XX } },
6053     { "(bad)",          { XX } },
6054     { "(bad)",          { XX } },
6055     { "(bad)",          { XX } },
6056     { "(bad)",          { XX } },
6057     { "(bad)",          { XX } },
6058     { "(bad)",          { XX } },
6059     /* e8 */
6060     { "(bad)",          { XX } },
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     /* f0 */
6069     { "(bad)",          { XX } },
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     { "(bad)",          { XX } },
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     { "(bad)",          { XX } },
6077     /* f8 */
6078     { "(bad)",          { XX } },
6079     { "(bad)",          { XX } },
6080     { "(bad)",          { XX } },
6081     { "(bad)",          { XX } },
6082     { "(bad)",          { XX } },
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     { "(bad)",          { XX } },
6086   },
6087
6088   /* THREE_BYTE_0F7A */
6089   {
6090     /* 00 */
6091     { "(bad)",          { XX } },
6092     { "(bad)",          { XX } },
6093     { "(bad)",          { XX } },
6094     { "(bad)",          { XX } },
6095     { "(bad)",          { XX } },
6096     { "(bad)",          { XX } },
6097     { "(bad)",          { XX } },
6098     { "(bad)",          { XX } },
6099     /* 08 */
6100     { "(bad)",          { XX } },
6101     { "(bad)",          { XX } },
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     { "(bad)",          { XX } },
6108     /* 10 */
6109     { "(bad)",          { XX } },
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     /* 18 */
6118     { "(bad)",          { XX } },
6119     { "(bad)",          { XX } },
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     /* 20 */
6127     { "ptest",          { XX } },
6128     { "(bad)",          { XX } },
6129     { "(bad)",          { XX } },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135     /* 28 */
6136     { "(bad)",          { XX } },
6137     { "(bad)",          { XX } },
6138     { "(bad)",          { XX } },
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     /* 30 */
6145     { "(bad)",          { XX } },
6146     { "(bad)",          { XX } },
6147     { "(bad)",          { XX } },
6148     { "(bad)",          { XX } },
6149     { "(bad)",          { XX } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     { "(bad)",          { XX } },
6153     /* 38 */
6154     { "(bad)",          { XX } },
6155     { "(bad)",          { XX } },
6156     { "(bad)",          { XX } },
6157     { "(bad)",          { XX } },
6158     { "(bad)",          { XX } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     { "(bad)",          { XX } },
6162     /* 40 */
6163     { "(bad)",          { XX } },
6164     { "phaddbw",        { XM, EXq } },
6165     { "phaddbd",        { XM, EXq } },
6166     { "phaddbq",        { XM, EXq } },
6167     { "(bad)",          { XX } },
6168     { "(bad)",          { XX } },
6169     { "phaddwd",        { XM, EXq } },
6170     { "phaddwq",        { XM, EXq } },
6171     /* 48 */
6172     { "(bad)",          { XX } },
6173     { "(bad)",          { XX } },
6174     { "(bad)",          { XX } },
6175     { "phadddq",        { XM, EXq } },
6176     { "(bad)",          { XX } },
6177     { "(bad)",          { XX } },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     /* 50 */
6181     { "(bad)",          { XX } },
6182     { "phaddubw",       { XM, EXq } },
6183     { "phaddubd",       { XM, EXq } },
6184     { "phaddubq",       { XM, EXq } },
6185     { "(bad)",          { XX } },
6186     { "(bad)",          { XX } },
6187     { "phadduwd",       { XM, EXq } },
6188     { "phadduwq",       { XM, EXq } },
6189     /* 58 */
6190     { "(bad)",          { XX } },
6191     { "(bad)",          { XX } },
6192     { "(bad)",          { XX } },
6193     { "phaddudq",       { XM, EXq } },
6194     { "(bad)",          { XX } },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     /* 60 */
6199     { "(bad)",          { XX } },
6200     { "phsubbw",        { XM, EXq } },
6201     { "phsubbd",        { XM, EXq } },
6202     { "phsubbq",        { XM, EXq } },
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     /* 68 */
6208     { "(bad)",          { XX } },
6209     { "(bad)",          { XX } },
6210     { "(bad)",          { XX } },
6211     { "(bad)",          { XX } },
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     /* 70 */
6217     { "(bad)",          { XX } },
6218     { "(bad)",          { XX } },
6219     { "(bad)",          { XX } },
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     /* 78 */
6226     { "(bad)",          { XX } },
6227     { "(bad)",          { XX } },
6228     { "(bad)",          { XX } },
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     /* 80 */
6235     { "(bad)",          { XX } },
6236     { "(bad)",          { XX } },
6237     { "(bad)",          { XX } },
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     /* 88 */
6244     { "(bad)",          { XX } },
6245     { "(bad)",          { XX } },
6246     { "(bad)",          { XX } },
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     /* 90 */
6253     { "(bad)",          { XX } },
6254     { "(bad)",          { XX } },
6255     { "(bad)",          { XX } },
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     /* 98 */
6262     { "(bad)",          { XX } },
6263     { "(bad)",          { XX } },
6264     { "(bad)",          { XX } },
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     /* a0 */
6271     { "(bad)",          { XX } },
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     /* a8 */
6280     { "(bad)",          { XX } },
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     /* b0 */
6289     { "(bad)",          { XX } },
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     /* b8 */
6298     { "(bad)",          { XX } },
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     /* c0 */
6307     { "(bad)",          { XX } },
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     /* c8 */
6316     { "(bad)",          { XX } },
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     /* d0 */
6325     { "(bad)",          { XX } },
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     /* d8 */
6334     { "(bad)",          { XX } },
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     /* e0 */
6343     { "(bad)",          { XX } },
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346     { "(bad)",          { XX } },
6347     { "(bad)",          { XX } },
6348     { "(bad)",          { XX } },
6349     { "(bad)",          { XX } },
6350     { "(bad)",          { XX } },
6351     /* e8 */
6352     { "(bad)",          { XX } },
6353     { "(bad)",          { XX } },
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     /* f0 */
6361     { "(bad)",          { XX } },
6362     { "(bad)",          { XX } },
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     /* f8 */
6370     { "(bad)",          { XX } },
6371     { "(bad)",          { XX } },
6372     { "(bad)",          { XX } },
6373     { "(bad)",          { XX } },
6374     { "(bad)",          { XX } },
6375     { "(bad)",          { XX } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378   },
6379 };
6380
6381 static const struct dis386 xop_table[][256] = {
6382   /* XOP_09 */
6383   {
6384     /* 00 */
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389     { "(bad)",          { XX } },
6390     { "(bad)",          { XX } },
6391     { "(bad)",          { XX } },
6392     { "(bad)",          { XX } },
6393     /* 08 */
6394     { "(bad)",          { XX } },
6395     { "(bad)",          { XX } },
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     { "(bad)",          { XX } },
6399     { "(bad)",          { XX } },
6400     { "(bad)",          { XX } },
6401     { "(bad)",          { XX } },
6402     /* 10 */
6403     { "(bad)",          { XX } },
6404     { "(bad)",          { XX } },
6405     { REG_TABLE (REG_XOP_LWPCB) },
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     { "(bad)",          { XX } },
6410     { "(bad)",          { XX } },
6411     /* 18 */
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     { "(bad)",          { XX } },
6420     /* 20 */
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     { "(bad)",          { XX } },
6428     { "(bad)",          { XX } },
6429     /* 28 */
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     { "(bad)",          { XX } },
6438     /* 30 */
6439     { "(bad)",          { XX } },
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     { "(bad)",          { XX } },
6446     { "(bad)",          { XX } },
6447     /* 38 */
6448     { "(bad)",          { XX } },
6449     { "(bad)",          { XX } },
6450     { "(bad)",          { XX } },
6451     { "(bad)",          { XX } },
6452     { "(bad)",          { XX } },
6453     { "(bad)",          { XX } },
6454     { "(bad)",          { XX } },
6455     { "(bad)",          { XX } },
6456     /* 40 */
6457     { "(bad)",          { XX } },
6458     { "(bad)",          { XX } },
6459     { "(bad)",          { XX } },
6460     { "(bad)",          { XX } },
6461     { "(bad)",          { XX } },
6462     { "(bad)",          { XX } },
6463     { "(bad)",          { XX } },
6464     { "(bad)",          { XX } },
6465     /* 48 */
6466     { "(bad)",          { XX } },
6467     { "(bad)",          { XX } },
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     { "(bad)",          { XX } },
6471     { "(bad)",          { XX } },
6472     { "(bad)",          { XX } },
6473     { "(bad)",          { XX } },
6474     /* 50 */
6475     { "(bad)",          { XX } },
6476     { "(bad)",          { XX } },
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     { "(bad)",          { XX } },
6483     /* 58 */
6484     { "(bad)",          { XX } },
6485     { "(bad)",          { XX } },
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     { "(bad)",          { XX } },
6492     /* 60 */
6493     { "(bad)",          { XX } },
6494     { "(bad)",          { XX } },
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     { "(bad)",          { XX } },
6501     /* 68 */
6502     { "(bad)",          { XX } },
6503     { "(bad)",          { XX } },
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     { "(bad)",          { XX } },
6510     /* 70 */
6511     { "(bad)",          { XX } },
6512     { "(bad)",          { XX } },
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     { "(bad)",          { XX } },
6519     /* 78 */
6520     { "(bad)",          { XX } },
6521     { "(bad)",          { XX } },
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     { "(bad)",          { XX } },
6528     /* 80 */
6529     { "(bad)",          { XX } },
6530     { "(bad)",          { XX } },
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     { "(bad)",          { XX } },
6537     /* 88 */
6538     { "(bad)",          { XX } },
6539     { "(bad)",          { XX } },
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     { "(bad)",          { XX } },
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     { "(bad)",          { XX } },
6546     /* 90 */
6547     { "(bad)",          { XX } },
6548     { "(bad)",          { XX } },
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     { "(bad)",          { XX } },
6555     /* 98 */
6556     { "(bad)",          { XX } },
6557     { "(bad)",          { XX } },
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     { "(bad)",          { XX } },
6564     /* a0 */
6565     { "(bad)",          { XX } },
6566     { "(bad)",          { XX } },
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     { "(bad)",          { XX } },
6573     /* a8 */
6574     { "(bad)",          { XX } },
6575     { "(bad)",          { XX } },
6576     { "(bad)",          { XX } },
6577     { "(bad)",          { XX } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581     { "(bad)",          { XX } },
6582     /* b0 */
6583     { "(bad)",          { XX } },
6584     { "(bad)",          { XX } },
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     /* b8 */
6592     { "(bad)",          { XX } },
6593     { "(bad)",          { XX } },
6594     { "(bad)",          { XX } },
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     { "(bad)",          { XX } },
6599     { "(bad)",          { XX } },
6600     /* c0 */
6601     { "(bad)",          { XX } },
6602     { "(bad)",          { XX } },
6603     { "(bad)",          { XX } },
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     /* c8 */
6610     { "(bad)",          { XX } },
6611     { "(bad)",          { XX } },
6612     { "(bad)",          { XX } },
6613     { "(bad)",          { XX } },
6614     { "(bad)",          { XX } },
6615     { "(bad)",          { XX } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     /* d0 */
6619     { "(bad)",          { XX } },
6620     { "(bad)",          { XX } },
6621     { "(bad)",          { XX } },
6622     { "(bad)",          { XX } },
6623     { "(bad)",          { XX } },
6624     { "(bad)",          { XX } },
6625     { "(bad)",          { XX } },
6626     { "(bad)",          { XX } },
6627     /* d8 */
6628     { "(bad)",          { XX } },
6629     { "(bad)",          { XX } },
6630     { "(bad)",          { XX } },
6631     { "(bad)",          { XX } },
6632     { "(bad)",          { XX } },
6633     { "(bad)",          { XX } },
6634     { "(bad)",          { XX } },
6635     { "(bad)",          { XX } },
6636     /* e0 */
6637     { "(bad)",          { XX } },
6638     { "(bad)",          { XX } },
6639     { "(bad)",          { XX } },
6640     { "(bad)",          { XX } },
6641     { "(bad)",          { XX } },
6642     { "(bad)",          { XX } },
6643     { "(bad)",          { XX } },
6644     { "(bad)",          { XX } },
6645     /* e8 */
6646     { "(bad)",          { XX } },
6647     { "(bad)",          { XX } },
6648     { "(bad)",          { XX } },
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     { "(bad)",          { XX } },
6653     { "(bad)",          { XX } },
6654     /* f0 */
6655     { "(bad)",          { XX } },
6656     { "(bad)",          { XX } },
6657     { "(bad)",          { XX } },
6658     { "(bad)",          { XX } },
6659     { "(bad)",          { XX } },
6660     { "(bad)",          { XX } },
6661     { "(bad)",          { XX } },
6662     { "(bad)",          { XX } },
6663     /* f8 */
6664     { "(bad)",          { XX } },
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672   },
6673   /* XOP_0A */
6674   {
6675     /* 00 */
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681     { "(bad)",          { XX } },
6682     { "(bad)",          { XX } },
6683     { "(bad)",          { XX } },
6684     /* 08 */
6685     { "(bad)",          { XX } },
6686     { "(bad)",          { XX } },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     { "(bad)",          { XX } },
6691     { "(bad)",          { XX } },
6692     { "(bad)",          { XX } },
6693     /* 10 */
6694     { "(bad)",          { XX } },
6695     { "(bad)",          { XX } },
6696     { REG_TABLE (REG_XOP_LWP) },
6697     { "(bad)",          { XX } },
6698     { "(bad)",          { XX } },
6699     { "(bad)",          { XX } },
6700     { "(bad)",          { XX } },
6701     { "(bad)",          { XX } },
6702     /* 18 */
6703     { "(bad)",          { XX } },
6704     { "(bad)",          { XX } },
6705     { "(bad)",          { XX } },
6706     { "(bad)",          { XX } },
6707     { "(bad)",          { XX } },
6708     { "(bad)",          { XX } },
6709     { "(bad)",          { XX } },
6710     { "(bad)",          { XX } },
6711     /* 20 */
6712     { "(bad)",          { XX } },
6713     { "(bad)",          { XX } },
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     { "(bad)",          { XX } },
6719     { "(bad)",          { XX } },
6720     /* 28 */
6721     { "(bad)",          { XX } },
6722     { "(bad)",          { XX } },
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727     { "(bad)",          { XX } },
6728     { "(bad)",          { XX } },
6729     /* 30 */
6730     { "(bad)",          { XX } },
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     { "(bad)",          { XX } },
6738     /* 38 */
6739     { "(bad)",          { XX } },
6740     { "(bad)",          { XX } },
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     { "(bad)",          { XX } },
6747     /* 40 */
6748     { "(bad)",          { XX } },
6749     { "(bad)",          { XX } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     { "(bad)",          { XX } },
6756     /* 48 */
6757     { "(bad)",          { XX } },
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     { "(bad)",          { XX } },
6765     /* 50 */
6766     { "(bad)",          { XX } },
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     { "(bad)",          { XX } },
6774     /* 58 */
6775     { "(bad)",          { XX } },
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     { "(bad)",          { XX } },
6783     /* 60 */
6784     { "(bad)",          { XX } },
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     { "(bad)",          { XX } },
6792     /* 68 */
6793     { "(bad)",          { XX } },
6794     { "(bad)",          { XX } },
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     { "(bad)",          { XX } },
6801     /* 70 */
6802     { "(bad)",          { XX } },
6803     { "(bad)",          { XX } },
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     { "(bad)",          { XX } },
6810     /* 78 */
6811     { "(bad)",          { XX } },
6812     { "(bad)",          { XX } },
6813     { "(bad)",          { XX } },
6814     { "(bad)",          { XX } },
6815     { "(bad)",          { XX } },
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     { "(bad)",          { XX } },
6819     /* 80 */
6820     { "(bad)",          { XX } },
6821     { "(bad)",          { XX } },
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     { "(bad)",          { XX } },
6828     /* 88 */
6829     { "(bad)",          { XX } },
6830     { "(bad)",          { XX } },
6831     { "(bad)",          { XX } },
6832     { "(bad)",          { XX } },
6833     { "(bad)",          { XX } },
6834     { "(bad)",          { XX } },
6835     { "(bad)",          { XX } },
6836     { "(bad)",          { XX } },
6837     /* 90 */
6838     { "(bad)",          { XX } },
6839     { "(bad)",          { XX } },
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     { "(bad)",          { XX } },
6846     /* 98 */
6847     { "(bad)",          { XX } },
6848     { "(bad)",          { XX } },
6849     { "(bad)",          { XX } },
6850     { "(bad)",          { XX } },
6851     { "(bad)",          { XX } },
6852     { "(bad)",          { XX } },
6853     { "(bad)",          { XX } },
6854     { "(bad)",          { XX } },
6855     /* a0 */
6856     { "(bad)",          { XX } },
6857     { "(bad)",          { XX } },
6858     { "(bad)",          { XX } },
6859     { "(bad)",          { XX } },
6860     { "(bad)",          { XX } },
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     { "(bad)",          { XX } },
6864     /* a8 */
6865     { "(bad)",          { XX } },
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872     { "(bad)",          { XX } },
6873     /* b0 */
6874     { "(bad)",          { XX } },
6875     { "(bad)",          { XX } },
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     { "(bad)",          { XX } },
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     /* b8 */
6883     { "(bad)",          { XX } },
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     /* c0 */
6892     { "(bad)",          { XX } },
6893     { "(bad)",          { XX } },
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     { "(bad)",          { XX } },
6898     { "(bad)",          { XX } },
6899     { "(bad)",          { XX } },
6900     /* c8 */
6901     { "(bad)",          { XX } },
6902     { "(bad)",          { XX } },
6903     { "(bad)",          { XX } },
6904     { "(bad)",          { XX } },
6905     { "(bad)",          { XX } },
6906     { "(bad)",          { XX } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     /* d0 */
6910     { "(bad)",          { XX } },
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     { "(bad)",          { XX } },
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     /* d8 */
6919     { "(bad)",          { XX } },
6920     { "(bad)",          { XX } },
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     { "(bad)",          { XX } },
6924     { "(bad)",          { XX } },
6925     { "(bad)",          { XX } },
6926     { "(bad)",          { XX } },
6927     /* e0 */
6928     { "(bad)",          { XX } },
6929     { "(bad)",          { XX } },
6930     { "(bad)",          { XX } },
6931     { "(bad)",          { XX } },
6932     { "(bad)",          { XX } },
6933     { "(bad)",          { XX } },
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     /* e8 */
6937     { "(bad)",          { XX } },
6938     { "(bad)",          { XX } },
6939     { "(bad)",          { XX } },
6940     { "(bad)",          { XX } },
6941     { "(bad)",          { XX } },
6942     { "(bad)",          { XX } },
6943     { "(bad)",          { XX } },
6944     { "(bad)",          { XX } },
6945     /* f0 */
6946     { "(bad)",          { XX } },
6947     { "(bad)",          { XX } },
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     { "(bad)",          { XX } },
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     /* f8 */
6955     { "(bad)",          { XX } },
6956     { "(bad)",          { XX } },
6957     { "(bad)",          { XX } },
6958     { "(bad)",          { XX } },
6959     { "(bad)",          { XX } },
6960     { "(bad)",          { XX } },
6961     { "(bad)",          { XX } },
6962     { "(bad)",          { XX } },
6963   },
6964 };
6965
6966 static const struct dis386 vex_table[][256] = {
6967   /* VEX_0F */
6968   {
6969     /* 00 */
6970     { "(bad)",          { XX } },
6971     { "(bad)",          { XX } },
6972     { "(bad)",          { XX } },
6973     { "(bad)",          { XX } },
6974     { "(bad)",          { XX } },
6975     { "(bad)",          { XX } },
6976     { "(bad)",          { XX } },
6977     { "(bad)",          { XX } },
6978     /* 08 */
6979     { "(bad)",          { XX } },
6980     { "(bad)",          { XX } },
6981     { "(bad)",          { XX } },
6982     { "(bad)",          { XX } },
6983     { "(bad)",          { XX } },
6984     { "(bad)",          { XX } },
6985     { "(bad)",          { XX } },
6986     { "(bad)",          { XX } },
6987     /* 10 */
6988     { PREFIX_TABLE (PREFIX_VEX_10) },
6989     { PREFIX_TABLE (PREFIX_VEX_11) },
6990     { PREFIX_TABLE (PREFIX_VEX_12) },
6991     { MOD_TABLE (MOD_VEX_13) },
6992     { "vunpcklpX",      { XM, Vex, EXx } },
6993     { "vunpckhpX",      { XM, Vex, EXx } },
6994     { PREFIX_TABLE (PREFIX_VEX_16) },
6995     { MOD_TABLE (MOD_VEX_17) },
6996     /* 18 */
6997     { "(bad)",          { XX } },
6998     { "(bad)",          { XX } },
6999     { "(bad)",          { XX } },
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     { "(bad)",          { XX } },
7004     { "(bad)",          { XX } },
7005     /* 20 */
7006     { "(bad)",          { XX } },
7007     { "(bad)",          { XX } },
7008     { "(bad)",          { XX } },
7009     { "(bad)",          { XX } },
7010     { "(bad)",          { XX } },
7011     { "(bad)",          { XX } },
7012     { "(bad)",          { XX } },
7013     { "(bad)",          { XX } },
7014     /* 28 */
7015     { "vmovapX",        { XM, EXx } },
7016     { "vmovapX",        { EXxS, XM } },
7017     { PREFIX_TABLE (PREFIX_VEX_2A) },
7018     { MOD_TABLE (MOD_VEX_2B) },
7019     { PREFIX_TABLE (PREFIX_VEX_2C) },
7020     { PREFIX_TABLE (PREFIX_VEX_2D) },
7021     { PREFIX_TABLE (PREFIX_VEX_2E) },
7022     { PREFIX_TABLE (PREFIX_VEX_2F) },
7023     /* 30 */
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     { "(bad)",          { XX } },
7032     /* 38 */
7033     { "(bad)",          { XX } },
7034     { "(bad)",          { XX } },
7035     { "(bad)",          { XX } },
7036     { "(bad)",          { XX } },
7037     { "(bad)",          { XX } },
7038     { "(bad)",          { XX } },
7039     { "(bad)",          { XX } },
7040     { "(bad)",          { XX } },
7041     /* 40 */
7042     { "(bad)",          { XX } },
7043     { "(bad)",          { XX } },
7044     { "(bad)",          { XX } },
7045     { "(bad)",          { XX } },
7046     { "(bad)",          { XX } },
7047     { "(bad)",          { XX } },
7048     { "(bad)",          { XX } },
7049     { "(bad)",          { XX } },
7050     /* 48 */
7051     { "(bad)",          { XX } },
7052     { "(bad)",          { XX } },
7053     { "(bad)",          { XX } },
7054     { "(bad)",          { XX } },
7055     { "(bad)",          { XX } },
7056     { "(bad)",          { XX } },
7057     { "(bad)",          { XX } },
7058     { "(bad)",          { XX } },
7059     /* 50 */
7060     { MOD_TABLE (MOD_VEX_51) },
7061     { PREFIX_TABLE (PREFIX_VEX_51) },
7062     { PREFIX_TABLE (PREFIX_VEX_52) },
7063     { PREFIX_TABLE (PREFIX_VEX_53) },
7064     { "vandpX",         { XM, Vex, EXx } },
7065     { "vandnpX",        { XM, Vex, EXx } },
7066     { "vorpX",          { XM, Vex, EXx } },
7067     { "vxorpX",         { XM, Vex, EXx } },
7068     /* 58 */
7069     { PREFIX_TABLE (PREFIX_VEX_58) },
7070     { PREFIX_TABLE (PREFIX_VEX_59) },
7071     { PREFIX_TABLE (PREFIX_VEX_5A) },
7072     { PREFIX_TABLE (PREFIX_VEX_5B) },
7073     { PREFIX_TABLE (PREFIX_VEX_5C) },
7074     { PREFIX_TABLE (PREFIX_VEX_5D) },
7075     { PREFIX_TABLE (PREFIX_VEX_5E) },
7076     { PREFIX_TABLE (PREFIX_VEX_5F) },
7077     /* 60 */
7078     { PREFIX_TABLE (PREFIX_VEX_60) },
7079     { PREFIX_TABLE (PREFIX_VEX_61) },
7080     { PREFIX_TABLE (PREFIX_VEX_62) },
7081     { PREFIX_TABLE (PREFIX_VEX_63) },
7082     { PREFIX_TABLE (PREFIX_VEX_64) },
7083     { PREFIX_TABLE (PREFIX_VEX_65) },
7084     { PREFIX_TABLE (PREFIX_VEX_66) },
7085     { PREFIX_TABLE (PREFIX_VEX_67) },
7086     /* 68 */
7087     { PREFIX_TABLE (PREFIX_VEX_68) },
7088     { PREFIX_TABLE (PREFIX_VEX_69) },
7089     { PREFIX_TABLE (PREFIX_VEX_6A) },
7090     { PREFIX_TABLE (PREFIX_VEX_6B) },
7091     { PREFIX_TABLE (PREFIX_VEX_6C) },
7092     { PREFIX_TABLE (PREFIX_VEX_6D) },
7093     { PREFIX_TABLE (PREFIX_VEX_6E) },
7094     { PREFIX_TABLE (PREFIX_VEX_6F) },
7095     /* 70 */
7096     { PREFIX_TABLE (PREFIX_VEX_70) },
7097     { REG_TABLE (REG_VEX_71) },
7098     { REG_TABLE (REG_VEX_72) },
7099     { REG_TABLE (REG_VEX_73) },
7100     { PREFIX_TABLE (PREFIX_VEX_74) },
7101     { PREFIX_TABLE (PREFIX_VEX_75) },
7102     { PREFIX_TABLE (PREFIX_VEX_76) },
7103     { PREFIX_TABLE (PREFIX_VEX_77) },
7104     /* 78 */
7105     { "(bad)",          { XX } },
7106     { "(bad)",          { XX } },
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     { PREFIX_TABLE (PREFIX_VEX_7C) },
7110     { PREFIX_TABLE (PREFIX_VEX_7D) },
7111     { PREFIX_TABLE (PREFIX_VEX_7E) },
7112     { PREFIX_TABLE (PREFIX_VEX_7F) },
7113     /* 80 */
7114     { "(bad)",          { XX } },
7115     { "(bad)",          { XX } },
7116     { "(bad)",          { XX } },
7117     { "(bad)",          { XX } },
7118     { "(bad)",          { XX } },
7119     { "(bad)",          { XX } },
7120     { "(bad)",          { XX } },
7121     { "(bad)",          { XX } },
7122     /* 88 */
7123     { "(bad)",          { XX } },
7124     { "(bad)",          { XX } },
7125     { "(bad)",          { XX } },
7126     { "(bad)",          { XX } },
7127     { "(bad)",          { XX } },
7128     { "(bad)",          { XX } },
7129     { "(bad)",          { XX } },
7130     { "(bad)",          { XX } },
7131     /* 90 */
7132     { "(bad)",          { XX } },
7133     { "(bad)",          { XX } },
7134     { "(bad)",          { XX } },
7135     { "(bad)",          { XX } },
7136     { "(bad)",          { XX } },
7137     { "(bad)",          { XX } },
7138     { "(bad)",          { XX } },
7139     { "(bad)",          { XX } },
7140     /* 98 */
7141     { "(bad)",          { XX } },
7142     { "(bad)",          { XX } },
7143     { "(bad)",          { XX } },
7144     { "(bad)",          { XX } },
7145     { "(bad)",          { XX } },
7146     { "(bad)",          { XX } },
7147     { "(bad)",          { XX } },
7148     { "(bad)",          { XX } },
7149     /* a0 */
7150     { "(bad)",          { XX } },
7151     { "(bad)",          { XX } },
7152     { "(bad)",          { XX } },
7153     { "(bad)",          { XX } },
7154     { "(bad)",          { XX } },
7155     { "(bad)",          { XX } },
7156     { "(bad)",          { XX } },
7157     { "(bad)",          { XX } },
7158     /* a8 */
7159     { "(bad)",          { XX } },
7160     { "(bad)",          { XX } },
7161     { "(bad)",          { XX } },
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { "(bad)",          { XX } },
7165     { REG_TABLE (REG_VEX_AE) },
7166     { "(bad)",          { XX } },
7167     /* b0 */
7168     { "(bad)",          { XX } },
7169     { "(bad)",          { XX } },
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     { "(bad)",          { XX } },
7174     { "(bad)",          { XX } },
7175     { "(bad)",          { XX } },
7176     /* b8 */
7177     { "(bad)",          { XX } },
7178     { "(bad)",          { XX } },
7179     { "(bad)",          { XX } },
7180     { "(bad)",          { XX } },
7181     { "(bad)",          { XX } },
7182     { "(bad)",          { XX } },
7183     { "(bad)",          { XX } },
7184     { "(bad)",          { XX } },
7185     /* c0 */
7186     { "(bad)",          { XX } },
7187     { "(bad)",          { XX } },
7188     { PREFIX_TABLE (PREFIX_VEX_C2) },
7189     { "(bad)",          { XX } },
7190     { PREFIX_TABLE (PREFIX_VEX_C4) },
7191     { PREFIX_TABLE (PREFIX_VEX_C5) },
7192     { "vshufpX",        { XM, Vex, EXx, Ib } },
7193     { "(bad)",          { XX } },
7194     /* c8 */
7195     { "(bad)",          { XX } },
7196     { "(bad)",          { XX } },
7197     { "(bad)",          { XX } },
7198     { "(bad)",          { XX } },
7199     { "(bad)",          { XX } },
7200     { "(bad)",          { XX } },
7201     { "(bad)",          { XX } },
7202     { "(bad)",          { XX } },
7203     /* d0 */
7204     { PREFIX_TABLE (PREFIX_VEX_D0) },
7205     { PREFIX_TABLE (PREFIX_VEX_D1) },
7206     { PREFIX_TABLE (PREFIX_VEX_D2) },
7207     { PREFIX_TABLE (PREFIX_VEX_D3) },
7208     { PREFIX_TABLE (PREFIX_VEX_D4) },
7209     { PREFIX_TABLE (PREFIX_VEX_D5) },
7210     { PREFIX_TABLE (PREFIX_VEX_D6) },
7211     { PREFIX_TABLE (PREFIX_VEX_D7) },
7212     /* d8 */
7213     { PREFIX_TABLE (PREFIX_VEX_D8) },
7214     { PREFIX_TABLE (PREFIX_VEX_D9) },
7215     { PREFIX_TABLE (PREFIX_VEX_DA) },
7216     { PREFIX_TABLE (PREFIX_VEX_DB) },
7217     { PREFIX_TABLE (PREFIX_VEX_DC) },
7218     { PREFIX_TABLE (PREFIX_VEX_DD) },
7219     { PREFIX_TABLE (PREFIX_VEX_DE) },
7220     { PREFIX_TABLE (PREFIX_VEX_DF) },
7221     /* e0 */
7222     { PREFIX_TABLE (PREFIX_VEX_E0) },
7223     { PREFIX_TABLE (PREFIX_VEX_E1) },
7224     { PREFIX_TABLE (PREFIX_VEX_E2) },
7225     { PREFIX_TABLE (PREFIX_VEX_E3) },
7226     { PREFIX_TABLE (PREFIX_VEX_E4) },
7227     { PREFIX_TABLE (PREFIX_VEX_E5) },
7228     { PREFIX_TABLE (PREFIX_VEX_E6) },
7229     { PREFIX_TABLE (PREFIX_VEX_E7) },
7230     /* e8 */
7231     { PREFIX_TABLE (PREFIX_VEX_E8) },
7232     { PREFIX_TABLE (PREFIX_VEX_E9) },
7233     { PREFIX_TABLE (PREFIX_VEX_EA) },
7234     { PREFIX_TABLE (PREFIX_VEX_EB) },
7235     { PREFIX_TABLE (PREFIX_VEX_EC) },
7236     { PREFIX_TABLE (PREFIX_VEX_ED) },
7237     { PREFIX_TABLE (PREFIX_VEX_EE) },
7238     { PREFIX_TABLE (PREFIX_VEX_EF) },
7239     /* f0 */
7240     { PREFIX_TABLE (PREFIX_VEX_F0) },
7241     { PREFIX_TABLE (PREFIX_VEX_F1) },
7242     { PREFIX_TABLE (PREFIX_VEX_F2) },
7243     { PREFIX_TABLE (PREFIX_VEX_F3) },
7244     { PREFIX_TABLE (PREFIX_VEX_F4) },
7245     { PREFIX_TABLE (PREFIX_VEX_F5) },
7246     { PREFIX_TABLE (PREFIX_VEX_F6) },
7247     { PREFIX_TABLE (PREFIX_VEX_F7) },
7248     /* f8 */
7249     { PREFIX_TABLE (PREFIX_VEX_F8) },
7250     { PREFIX_TABLE (PREFIX_VEX_F9) },
7251     { PREFIX_TABLE (PREFIX_VEX_FA) },
7252     { PREFIX_TABLE (PREFIX_VEX_FB) },
7253     { PREFIX_TABLE (PREFIX_VEX_FC) },
7254     { PREFIX_TABLE (PREFIX_VEX_FD) },
7255     { PREFIX_TABLE (PREFIX_VEX_FE) },
7256     { "(bad)",          { XX } },
7257   },
7258   /* VEX_0F38 */
7259   {
7260     /* 00 */
7261     { PREFIX_TABLE (PREFIX_VEX_3800) },
7262     { PREFIX_TABLE (PREFIX_VEX_3801) },
7263     { PREFIX_TABLE (PREFIX_VEX_3802) },
7264     { PREFIX_TABLE (PREFIX_VEX_3803) },
7265     { PREFIX_TABLE (PREFIX_VEX_3804) },
7266     { PREFIX_TABLE (PREFIX_VEX_3805) },
7267     { PREFIX_TABLE (PREFIX_VEX_3806) },
7268     { PREFIX_TABLE (PREFIX_VEX_3807) },
7269     /* 08 */
7270     { PREFIX_TABLE (PREFIX_VEX_3808) },
7271     { PREFIX_TABLE (PREFIX_VEX_3809) },
7272     { PREFIX_TABLE (PREFIX_VEX_380A) },
7273     { PREFIX_TABLE (PREFIX_VEX_380B) },
7274     { PREFIX_TABLE (PREFIX_VEX_380C) },
7275     { PREFIX_TABLE (PREFIX_VEX_380D) },
7276     { PREFIX_TABLE (PREFIX_VEX_380E) },
7277     { PREFIX_TABLE (PREFIX_VEX_380F) },
7278     /* 10 */
7279     { "(bad)",          { XX } },
7280     { "(bad)",          { XX } },
7281     { "(bad)",          { XX } },
7282     { "(bad)",          { XX } },
7283     { "(bad)",          { XX } },
7284     { "(bad)",          { XX } },
7285     { "(bad)",          { XX } },
7286     { PREFIX_TABLE (PREFIX_VEX_3817) },
7287     /* 18 */
7288     { PREFIX_TABLE (PREFIX_VEX_3818) },
7289     { PREFIX_TABLE (PREFIX_VEX_3819) },
7290     { PREFIX_TABLE (PREFIX_VEX_381A) },
7291     { "(bad)",          { XX } },
7292     { PREFIX_TABLE (PREFIX_VEX_381C) },
7293     { PREFIX_TABLE (PREFIX_VEX_381D) },
7294     { PREFIX_TABLE (PREFIX_VEX_381E) },
7295     { "(bad)",          { XX } },
7296     /* 20 */
7297     { PREFIX_TABLE (PREFIX_VEX_3820) },
7298     { PREFIX_TABLE (PREFIX_VEX_3821) },
7299     { PREFIX_TABLE (PREFIX_VEX_3822) },
7300     { PREFIX_TABLE (PREFIX_VEX_3823) },
7301     { PREFIX_TABLE (PREFIX_VEX_3824) },
7302     { PREFIX_TABLE (PREFIX_VEX_3825) },
7303     { "(bad)",          { XX } },
7304     { "(bad)",          { XX } },
7305     /* 28 */
7306     { PREFIX_TABLE (PREFIX_VEX_3828) },
7307     { PREFIX_TABLE (PREFIX_VEX_3829) },
7308     { PREFIX_TABLE (PREFIX_VEX_382A) },
7309     { PREFIX_TABLE (PREFIX_VEX_382B) },
7310     { PREFIX_TABLE (PREFIX_VEX_382C) },
7311     { PREFIX_TABLE (PREFIX_VEX_382D) },
7312     { PREFIX_TABLE (PREFIX_VEX_382E) },
7313     { PREFIX_TABLE (PREFIX_VEX_382F) },
7314     /* 30 */
7315     { PREFIX_TABLE (PREFIX_VEX_3830) },
7316     { PREFIX_TABLE (PREFIX_VEX_3831) },
7317     { PREFIX_TABLE (PREFIX_VEX_3832) },
7318     { PREFIX_TABLE (PREFIX_VEX_3833) },
7319     { PREFIX_TABLE (PREFIX_VEX_3834) },
7320     { PREFIX_TABLE (PREFIX_VEX_3835) },
7321     { "(bad)",          { XX } },
7322     { PREFIX_TABLE (PREFIX_VEX_3837) },
7323     /* 38 */
7324     { PREFIX_TABLE (PREFIX_VEX_3838) },
7325     { PREFIX_TABLE (PREFIX_VEX_3839) },
7326     { PREFIX_TABLE (PREFIX_VEX_383A) },
7327     { PREFIX_TABLE (PREFIX_VEX_383B) },
7328     { PREFIX_TABLE (PREFIX_VEX_383C) },
7329     { PREFIX_TABLE (PREFIX_VEX_383D) },
7330     { PREFIX_TABLE (PREFIX_VEX_383E) },
7331     { PREFIX_TABLE (PREFIX_VEX_383F) },
7332     /* 40 */
7333     { PREFIX_TABLE (PREFIX_VEX_3840) },
7334     { PREFIX_TABLE (PREFIX_VEX_3841) },
7335     { "(bad)",          { XX } },
7336     { "(bad)",          { XX } },
7337     { "(bad)",          { XX } },
7338     { "(bad)",          { XX } },
7339     { "(bad)",          { XX } },
7340     { "(bad)",          { XX } },
7341     /* 48 */
7342     { "(bad)",          { XX } },
7343     { "(bad)",          { XX } },
7344     { "(bad)",          { XX } },
7345     { "(bad)",          { XX } },
7346     { "(bad)",          { XX } },
7347     { "(bad)",          { XX } },
7348     { "(bad)",          { XX } },
7349     { "(bad)",          { XX } },
7350     /* 50 */
7351     { "(bad)",          { XX } },
7352     { "(bad)",          { XX } },
7353     { "(bad)",          { XX } },
7354     { "(bad)",          { XX } },
7355     { "(bad)",          { XX } },
7356     { "(bad)",          { XX } },
7357     { "(bad)",          { XX } },
7358     { "(bad)",          { XX } },
7359     /* 58 */
7360     { "(bad)",          { XX } },
7361     { "(bad)",          { XX } },
7362     { "(bad)",          { XX } },
7363     { "(bad)",          { XX } },
7364     { "(bad)",          { XX } },
7365     { "(bad)",          { XX } },
7366     { "(bad)",          { XX } },
7367     { "(bad)",          { XX } },
7368     /* 60 */
7369     { "(bad)",          { XX } },
7370     { "(bad)",          { XX } },
7371     { "(bad)",          { XX } },
7372     { "(bad)",          { XX } },
7373     { "(bad)",          { XX } },
7374     { "(bad)",          { XX } },
7375     { "(bad)",          { XX } },
7376     { "(bad)",          { XX } },
7377     /* 68 */
7378     { "(bad)",          { XX } },
7379     { "(bad)",          { XX } },
7380     { "(bad)",          { XX } },
7381     { "(bad)",          { XX } },
7382     { "(bad)",          { XX } },
7383     { "(bad)",          { XX } },
7384     { "(bad)",          { XX } },
7385     { "(bad)",          { XX } },
7386     /* 70 */
7387     { "(bad)",          { XX } },
7388     { "(bad)",          { XX } },
7389     { "(bad)",          { XX } },
7390     { "(bad)",          { XX } },
7391     { "(bad)",          { XX } },
7392     { "(bad)",          { XX } },
7393     { "(bad)",          { XX } },
7394     { "(bad)",          { XX } },
7395     /* 78 */
7396     { "(bad)",          { XX } },
7397     { "(bad)",          { XX } },
7398     { "(bad)",          { XX } },
7399     { "(bad)",          { XX } },
7400     { "(bad)",          { XX } },
7401     { "(bad)",          { XX } },
7402     { "(bad)",          { XX } },
7403     { "(bad)",          { XX } },
7404     /* 80 */
7405     { "(bad)",          { XX } },
7406     { "(bad)",          { XX } },
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     { "(bad)",          { XX } },
7410     { "(bad)",          { XX } },
7411     { "(bad)",          { XX } },
7412     { "(bad)",          { XX } },
7413     /* 88 */
7414     { "(bad)",          { XX } },
7415     { "(bad)",          { XX } },
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     { "(bad)",          { XX } },
7422     /* 90 */
7423     { "(bad)",          { XX } },
7424     { "(bad)",          { XX } },
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     { PREFIX_TABLE (PREFIX_VEX_3896) },
7430     { PREFIX_TABLE (PREFIX_VEX_3897) },
7431     /* 98 */
7432     { PREFIX_TABLE (PREFIX_VEX_3898) },
7433     { PREFIX_TABLE (PREFIX_VEX_3899) },
7434     { PREFIX_TABLE (PREFIX_VEX_389A) },
7435     { PREFIX_TABLE (PREFIX_VEX_389B) },
7436     { PREFIX_TABLE (PREFIX_VEX_389C) },
7437     { PREFIX_TABLE (PREFIX_VEX_389D) },
7438     { PREFIX_TABLE (PREFIX_VEX_389E) },
7439     { PREFIX_TABLE (PREFIX_VEX_389F) },
7440     /* a0 */
7441     { "(bad)",          { XX } },
7442     { "(bad)",          { XX } },
7443     { "(bad)",          { XX } },
7444     { "(bad)",          { XX } },
7445     { "(bad)",          { XX } },
7446     { "(bad)",          { XX } },
7447     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7448     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7449     /* a8 */
7450     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7451     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7452     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7453     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7454     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7455     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7456     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7457     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7458     /* b0 */
7459     { "(bad)",          { XX } },
7460     { "(bad)",          { XX } },
7461     { "(bad)",          { XX } },
7462     { "(bad)",          { XX } },
7463     { "(bad)",          { XX } },
7464     { "(bad)",          { XX } },
7465     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7466     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7467     /* b8 */
7468     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7469     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7470     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7471     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7472     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7473     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7474     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7475     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7476     /* c0 */
7477     { "(bad)",          { XX } },
7478     { "(bad)",          { XX } },
7479     { "(bad)",          { XX } },
7480     { "(bad)",          { XX } },
7481     { "(bad)",          { XX } },
7482     { "(bad)",          { XX } },
7483     { "(bad)",          { XX } },
7484     { "(bad)",          { XX } },
7485     /* c8 */
7486     { "(bad)",          { XX } },
7487     { "(bad)",          { XX } },
7488     { "(bad)",          { XX } },
7489     { "(bad)",          { XX } },
7490     { "(bad)",          { XX } },
7491     { "(bad)",          { XX } },
7492     { "(bad)",          { XX } },
7493     { "(bad)",          { XX } },
7494     /* d0 */
7495     { "(bad)",          { XX } },
7496     { "(bad)",          { XX } },
7497     { "(bad)",          { XX } },
7498     { "(bad)",          { XX } },
7499     { "(bad)",          { XX } },
7500     { "(bad)",          { XX } },
7501     { "(bad)",          { XX } },
7502     { "(bad)",          { XX } },
7503     /* d8 */
7504     { "(bad)",          { XX } },
7505     { "(bad)",          { XX } },
7506     { "(bad)",          { XX } },
7507     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7508     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7509     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7510     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7511     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7512     /* e0 */
7513     { "(bad)",          { XX } },
7514     { "(bad)",          { XX } },
7515     { "(bad)",          { XX } },
7516     { "(bad)",          { XX } },
7517     { "(bad)",          { XX } },
7518     { "(bad)",          { XX } },
7519     { "(bad)",          { XX } },
7520     { "(bad)",          { XX } },
7521     /* e8 */
7522     { "(bad)",          { XX } },
7523     { "(bad)",          { XX } },
7524     { "(bad)",          { XX } },
7525     { "(bad)",          { XX } },
7526     { "(bad)",          { XX } },
7527     { "(bad)",          { XX } },
7528     { "(bad)",          { XX } },
7529     { "(bad)",          { XX } },
7530     /* f0 */
7531     { "(bad)",          { XX } },
7532     { "(bad)",          { XX } },
7533     { "(bad)",          { XX } },
7534     { "(bad)",          { XX } },
7535     { "(bad)",          { XX } },
7536     { "(bad)",          { XX } },
7537     { "(bad)",          { XX } },
7538     { "(bad)",          { XX } },
7539     /* f8 */
7540     { "(bad)",          { XX } },
7541     { "(bad)",          { XX } },
7542     { "(bad)",          { XX } },
7543     { "(bad)",          { XX } },
7544     { "(bad)",          { XX } },
7545     { "(bad)",          { XX } },
7546     { "(bad)",          { XX } },
7547     { "(bad)",          { XX } },
7548   },
7549   /* VEX_0F3A */
7550   {
7551     /* 00 */
7552     { "(bad)",          { XX } },
7553     { "(bad)",          { XX } },
7554     { "(bad)",          { XX } },
7555     { "(bad)",          { XX } },
7556     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7557     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7558     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7559     { "(bad)",          { XX } },
7560     /* 08 */
7561     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7562     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7563     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7564     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7565     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7566     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7567     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7568     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7569     /* 10 */
7570     { "(bad)",          { XX } },
7571     { "(bad)",          { XX } },
7572     { "(bad)",          { XX } },
7573     { "(bad)",          { XX } },
7574     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7575     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7576     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7577     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7578     /* 18 */
7579     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7580     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7581     { "(bad)",          { XX } },
7582     { "(bad)",          { XX } },
7583     { "(bad)",          { XX } },
7584     { "(bad)",          { XX } },
7585     { "(bad)",          { XX } },
7586     { "(bad)",          { XX } },
7587     /* 20 */
7588     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7589     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7590     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7591     { "(bad)",          { XX } },
7592     { "(bad)",          { XX } },
7593     { "(bad)",          { XX } },
7594     { "(bad)",          { XX } },
7595     { "(bad)",          { XX } },
7596     /* 28 */
7597     { "(bad)",          { XX } },
7598     { "(bad)",          { XX } },
7599     { "(bad)",          { XX } },
7600     { "(bad)",          { XX } },
7601     { "(bad)",          { XX } },
7602     { "(bad)",          { XX } },
7603     { "(bad)",          { XX } },
7604     { "(bad)",          { XX } },
7605     /* 30 */
7606     { "(bad)",          { XX } },
7607     { "(bad)",          { XX } },
7608     { "(bad)",          { XX } },
7609     { "(bad)",          { XX } },
7610     { "(bad)",          { XX } },
7611     { "(bad)",          { XX } },
7612     { "(bad)",          { XX } },
7613     { "(bad)",          { XX } },
7614     /* 38 */
7615     { "(bad)",          { XX } },
7616     { "(bad)",          { XX } },
7617     { "(bad)",          { XX } },
7618     { "(bad)",          { XX } },
7619     { "(bad)",          { XX } },
7620     { "(bad)",          { XX } },
7621     { "(bad)",          { XX } },
7622     { "(bad)",          { XX } },
7623     /* 40 */
7624     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7625     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7626     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7627     { "(bad)",          { XX } },
7628     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7629     { "(bad)",          { XX } },
7630     { "(bad)",          { XX } },
7631     { "(bad)",          { XX } },
7632     /* 48 */
7633     { "(bad)",          { XX } },
7634     { "(bad)",          { XX } },
7635     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7636     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7637     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7638     { "(bad)",          { XX } },
7639     { "(bad)",          { XX } },
7640     { "(bad)",          { XX } },
7641     /* 50 */
7642     { "(bad)",          { XX } },
7643     { "(bad)",          { XX } },
7644     { "(bad)",          { XX } },
7645     { "(bad)",          { XX } },
7646     { "(bad)",          { XX } },
7647     { "(bad)",          { XX } },
7648     { "(bad)",          { XX } },
7649     { "(bad)",          { XX } },
7650     /* 58 */
7651     { "(bad)",          { XX } },
7652     { "(bad)",          { XX } },
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7656     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7657     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7658     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7659     /* 60 */
7660     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7661     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7662     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7663     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7664     { "(bad)",          { XX } },
7665     { "(bad)",          { XX } },
7666     { "(bad)",          { XX } },
7667     { "(bad)",          { XX } },
7668     /* 68 */
7669     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7670     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7671     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7672     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7673     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7674     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7675     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7676     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7677     /* 70 */
7678     { "(bad)",          { XX } },
7679     { "(bad)",          { XX } },
7680     { "(bad)",          { XX } },
7681     { "(bad)",          { XX } },
7682     { "(bad)",          { XX } },
7683     { "(bad)",          { XX } },
7684     { "(bad)",          { XX } },
7685     { "(bad)",          { XX } },
7686     /* 78 */
7687     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7688     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7689     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7690     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7691     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7692     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7693     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7694     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7695     /* 80 */
7696     { "(bad)",          { XX } },
7697     { "(bad)",          { XX } },
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     { "(bad)",          { XX } },
7704     /* 88 */
7705     { "(bad)",          { XX } },
7706     { "(bad)",          { XX } },
7707     { "(bad)",          { XX } },
7708     { "(bad)",          { XX } },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     { "(bad)",          { XX } },
7713     /* 90 */
7714     { "(bad)",          { XX } },
7715     { "(bad)",          { XX } },
7716     { "(bad)",          { XX } },
7717     { "(bad)",          { XX } },
7718     { "(bad)",          { XX } },
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     { "(bad)",          { XX } },
7722     /* 98 */
7723     { "(bad)",          { XX } },
7724     { "(bad)",          { XX } },
7725     { "(bad)",          { XX } },
7726     { "(bad)",          { XX } },
7727     { "(bad)",          { XX } },
7728     { "(bad)",          { XX } },
7729     { "(bad)",          { XX } },
7730     { "(bad)",          { XX } },
7731     /* a0 */
7732     { "(bad)",          { XX } },
7733     { "(bad)",          { XX } },
7734     { "(bad)",          { XX } },
7735     { "(bad)",          { XX } },
7736     { "(bad)",          { XX } },
7737     { "(bad)",          { XX } },
7738     { "(bad)",          { XX } },
7739     { "(bad)",          { XX } },
7740     /* a8 */
7741     { "(bad)",          { XX } },
7742     { "(bad)",          { XX } },
7743     { "(bad)",          { XX } },
7744     { "(bad)",          { XX } },
7745     { "(bad)",          { XX } },
7746     { "(bad)",          { XX } },
7747     { "(bad)",          { XX } },
7748     { "(bad)",          { XX } },
7749     /* b0 */
7750     { "(bad)",          { XX } },
7751     { "(bad)",          { XX } },
7752     { "(bad)",          { XX } },
7753     { "(bad)",          { XX } },
7754     { "(bad)",          { XX } },
7755     { "(bad)",          { XX } },
7756     { "(bad)",          { XX } },
7757     { "(bad)",          { XX } },
7758     /* b8 */
7759     { "(bad)",          { XX } },
7760     { "(bad)",          { XX } },
7761     { "(bad)",          { XX } },
7762     { "(bad)",          { XX } },
7763     { "(bad)",          { XX } },
7764     { "(bad)",          { XX } },
7765     { "(bad)",          { XX } },
7766     { "(bad)",          { XX } },
7767     /* c0 */
7768     { "(bad)",          { XX } },
7769     { "(bad)",          { XX } },
7770     { "(bad)",          { XX } },
7771     { "(bad)",          { XX } },
7772     { "(bad)",          { XX } },
7773     { "(bad)",          { XX } },
7774     { "(bad)",          { XX } },
7775     { "(bad)",          { XX } },
7776     /* c8 */
7777     { "(bad)",          { XX } },
7778     { "(bad)",          { XX } },
7779     { "(bad)",          { XX } },
7780     { "(bad)",          { XX } },
7781     { "(bad)",          { XX } },
7782     { "(bad)",          { XX } },
7783     { "(bad)",          { XX } },
7784     { "(bad)",          { XX } },
7785     /* d0 */
7786     { "(bad)",          { XX } },
7787     { "(bad)",          { XX } },
7788     { "(bad)",          { XX } },
7789     { "(bad)",          { XX } },
7790     { "(bad)",          { XX } },
7791     { "(bad)",          { XX } },
7792     { "(bad)",          { XX } },
7793     { "(bad)",          { XX } },
7794     /* d8 */
7795     { "(bad)",          { XX } },
7796     { "(bad)",          { XX } },
7797     { "(bad)",          { XX } },
7798     { "(bad)",          { XX } },
7799     { "(bad)",          { XX } },
7800     { "(bad)",          { XX } },
7801     { "(bad)",          { XX } },
7802     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7803     /* e0 */
7804     { "(bad)",          { XX } },
7805     { "(bad)",          { XX } },
7806     { "(bad)",          { XX } },
7807     { "(bad)",          { XX } },
7808     { "(bad)",          { XX } },
7809     { "(bad)",          { XX } },
7810     { "(bad)",          { XX } },
7811     { "(bad)",          { XX } },
7812     /* e8 */
7813     { "(bad)",          { XX } },
7814     { "(bad)",          { XX } },
7815     { "(bad)",          { XX } },
7816     { "(bad)",          { XX } },
7817     { "(bad)",          { XX } },
7818     { "(bad)",          { XX } },
7819     { "(bad)",          { XX } },
7820     { "(bad)",          { XX } },
7821     /* f0 */
7822     { "(bad)",          { XX } },
7823     { "(bad)",          { XX } },
7824     { "(bad)",          { XX } },
7825     { "(bad)",          { XX } },
7826     { "(bad)",          { XX } },
7827     { "(bad)",          { XX } },
7828     { "(bad)",          { XX } },
7829     { "(bad)",          { XX } },
7830     /* f8 */
7831     { "(bad)",          { XX } },
7832     { "(bad)",          { XX } },
7833     { "(bad)",          { XX } },
7834     { "(bad)",          { XX } },
7835     { "(bad)",          { XX } },
7836     { "(bad)",          { XX } },
7837     { "(bad)",          { XX } },
7838     { "(bad)",          { XX } },
7839   },
7840 };
7841
7842 static const struct dis386 vex_len_table[][2] = {
7843   /* VEX_LEN_10_P_1 */
7844   {
7845     { "vmovss",         { XMVex, Vex128, EXd } },
7846     { "(bad)",          { XX } },
7847   },
7848
7849   /* VEX_LEN_10_P_3 */
7850   {
7851     { "vmovsd",         { XMVex, Vex128, EXq } },
7852     { "(bad)",          { XX } },
7853   },
7854
7855   /* VEX_LEN_11_P_1 */
7856   {
7857     { "vmovss",         { EXdVexS, Vex128, XM } },
7858     { "(bad)",          { XX } },
7859   },
7860
7861   /* VEX_LEN_11_P_3 */
7862   {
7863     { "vmovsd",         { EXqVexS, Vex128, XM } },
7864     { "(bad)",          { XX } },
7865   },
7866
7867   /* VEX_LEN_12_P_0_M_0 */
7868   {
7869     { "vmovlps",        { XM, Vex128, EXq } },
7870     { "(bad)",          { XX } },
7871   },
7872
7873   /* VEX_LEN_12_P_0_M_1 */
7874   {
7875     { "vmovhlps",       { XM, Vex128, EXq } },
7876     { "(bad)",          { XX } },
7877   },
7878
7879   /* VEX_LEN_12_P_2 */
7880   {
7881     { "vmovlpd",        { XM, Vex128, EXq } },
7882     { "(bad)",          { XX } },
7883   },
7884
7885   /* VEX_LEN_13_M_0 */
7886   {
7887     { "vmovlpX",        { EXq, XM } },
7888     { "(bad)",          { XX } },
7889   },
7890
7891   /* VEX_LEN_16_P_0_M_0 */
7892   {
7893     { "vmovhps",        { XM, Vex128, EXq } },
7894     { "(bad)",          { XX } },
7895   },
7896
7897   /* VEX_LEN_16_P_0_M_1 */
7898   {
7899     { "vmovlhps",       { XM, Vex128, EXq } },
7900     { "(bad)",          { XX } },
7901   },
7902
7903   /* VEX_LEN_16_P_2 */
7904   {
7905     { "vmovhpd",        { XM, Vex128, EXq } },
7906     { "(bad)",          { XX } },
7907   },
7908
7909   /* VEX_LEN_17_M_0 */
7910   {
7911     { "vmovhpX",        { EXq, XM } },
7912     { "(bad)",          { XX } },
7913   },
7914
7915   /* VEX_LEN_2A_P_1 */
7916   {
7917     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7918     { "(bad)",          { XX } },
7919   },
7920
7921   /* VEX_LEN_2A_P_3 */
7922   {
7923     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7924     { "(bad)",          { XX } },
7925   },
7926
7927   /* VEX_LEN_2C_P_1 */
7928   {
7929     { "vcvttss2siY",    { Gv, EXd } },
7930     { "(bad)",          { XX } },
7931   },
7932
7933   /* VEX_LEN_2C_P_3 */
7934   {
7935     { "vcvttsd2siY",    { Gv, EXq } },
7936     { "(bad)",          { XX } },
7937   },
7938
7939   /* VEX_LEN_2D_P_1 */
7940   {
7941     { "vcvtss2siY",     { Gv, EXd } },
7942     { "(bad)",          { XX } },
7943   },
7944
7945   /* VEX_LEN_2D_P_3 */
7946   {
7947     { "vcvtsd2siY",     { Gv, EXq } },
7948     { "(bad)",          { XX } },
7949   },
7950
7951   /* VEX_LEN_2E_P_0 */
7952   {
7953     { "vucomiss",       { XM, EXd } },
7954     { "(bad)",          { XX } },
7955   },
7956
7957   /* VEX_LEN_2E_P_2 */
7958   {
7959     { "vucomisd",       { XM, EXq } },
7960     { "(bad)",          { XX } },
7961   },
7962
7963   /* VEX_LEN_2F_P_0 */
7964   {
7965     { "vcomiss",        { XM, EXd } },
7966     { "(bad)",          { XX } },
7967   },
7968
7969   /* VEX_LEN_2F_P_2 */
7970   {
7971     { "vcomisd",        { XM, EXq } },
7972     { "(bad)",          { XX } },
7973   },
7974
7975   /* VEX_LEN_51_P_1 */
7976   {
7977     { "vsqrtss",        { XM, Vex128, EXd } },
7978     { "(bad)",          { XX } },
7979   },
7980
7981   /* VEX_LEN_51_P_3 */
7982   {
7983     { "vsqrtsd",        { XM, Vex128, EXq } },
7984     { "(bad)",          { XX } },
7985   },
7986
7987   /* VEX_LEN_52_P_1 */
7988   {
7989     { "vrsqrtss",       { XM, Vex128, EXd } },
7990     { "(bad)",          { XX } },
7991   },
7992
7993   /* VEX_LEN_53_P_1 */
7994   {
7995     { "vrcpss",         { XM, Vex128, EXd } },
7996     { "(bad)",          { XX } },
7997   },
7998
7999   /* VEX_LEN_58_P_1 */
8000   {
8001     { "vaddss",         { XM, Vex128, EXd } },
8002     { "(bad)",          { XX } },
8003   },
8004
8005   /* VEX_LEN_58_P_3 */
8006   {
8007     { "vaddsd",         { XM, Vex128, EXq } },
8008     { "(bad)",          { XX } },
8009   },
8010
8011   /* VEX_LEN_59_P_1 */
8012   {
8013     { "vmulss",         { XM, Vex128, EXd } },
8014     { "(bad)",          { XX } },
8015   },
8016
8017   /* VEX_LEN_59_P_3 */
8018   {
8019     { "vmulsd",         { XM, Vex128, EXq } },
8020     { "(bad)",          { XX } },
8021   },
8022
8023   /* VEX_LEN_5A_P_1 */
8024   {
8025     { "vcvtss2sd",      { XM, Vex128, EXd } },
8026     { "(bad)",          { XX } },
8027   },
8028
8029   /* VEX_LEN_5A_P_3 */
8030   {
8031     { "vcvtsd2ss",      { XM, Vex128, EXq } },
8032     { "(bad)",          { XX } },
8033   },
8034
8035   /* VEX_LEN_5C_P_1 */
8036   {
8037     { "vsubss",         { XM, Vex128, EXd } },
8038     { "(bad)",          { XX } },
8039   },
8040
8041   /* VEX_LEN_5C_P_3 */
8042   {
8043     { "vsubsd",         { XM, Vex128, EXq } },
8044     { "(bad)",          { XX } },
8045   },
8046
8047   /* VEX_LEN_5D_P_1 */
8048   {
8049     { "vminss",         { XM, Vex128, EXd } },
8050     { "(bad)",          { XX } },
8051   },
8052
8053   /* VEX_LEN_5D_P_3 */
8054   {
8055     { "vminsd",         { XM, Vex128, EXq } },
8056     { "(bad)",          { XX } },
8057   },
8058
8059   /* VEX_LEN_5E_P_1 */
8060   {
8061     { "vdivss",         { XM, Vex128, EXd } },
8062     { "(bad)",          { XX } },
8063   },
8064
8065   /* VEX_LEN_5E_P_3 */
8066   {
8067     { "vdivsd",         { XM, Vex128, EXq } },
8068     { "(bad)",          { XX } },
8069   },
8070
8071   /* VEX_LEN_5F_P_1 */
8072   {
8073     { "vmaxss",         { XM, Vex128, EXd } },
8074     { "(bad)",          { XX } },
8075   },
8076
8077   /* VEX_LEN_5F_P_3 */
8078   {
8079     { "vmaxsd",         { XM, Vex128, EXq } },
8080     { "(bad)",          { XX } },
8081   },
8082
8083   /* VEX_LEN_60_P_2 */
8084   {
8085     { "vpunpcklbw",     { XM, Vex128, EXx } },
8086     { "(bad)",          { XX } },
8087   },
8088
8089   /* VEX_LEN_61_P_2 */
8090   {
8091     { "vpunpcklwd",     { XM, Vex128, EXx } },
8092     { "(bad)",          { XX } },
8093   },
8094
8095   /* VEX_LEN_62_P_2 */
8096   {
8097     { "vpunpckldq",     { XM, Vex128, EXx } },
8098     { "(bad)",          { XX } },
8099   },
8100
8101   /* VEX_LEN_63_P_2 */
8102   {
8103     { "vpacksswb",      { XM, Vex128, EXx } },
8104     { "(bad)",          { XX } },
8105   },
8106
8107   /* VEX_LEN_64_P_2 */
8108   {
8109     { "vpcmpgtb",       { XM, Vex128, EXx } },
8110     { "(bad)",          { XX } },
8111   },
8112
8113   /* VEX_LEN_65_P_2 */
8114   {
8115     { "vpcmpgtw",       { XM, Vex128, EXx } },
8116     { "(bad)",          { XX } },
8117   },
8118
8119   /* VEX_LEN_66_P_2 */
8120   {
8121     { "vpcmpgtd",       { XM, Vex128, EXx } },
8122     { "(bad)",          { XX } },
8123   },
8124
8125   /* VEX_LEN_67_P_2 */
8126   {
8127     { "vpackuswb",      { XM, Vex128, EXx } },
8128     { "(bad)",          { XX } },
8129   },
8130
8131   /* VEX_LEN_68_P_2 */
8132   {
8133     { "vpunpckhbw",     { XM, Vex128, EXx } },
8134     { "(bad)",          { XX } },
8135   },
8136
8137   /* VEX_LEN_69_P_2 */
8138   {
8139     { "vpunpckhwd",     { XM, Vex128, EXx } },
8140     { "(bad)",          { XX } },
8141   },
8142
8143   /* VEX_LEN_6A_P_2 */
8144   {
8145     { "vpunpckhdq",     { XM, Vex128, EXx } },
8146     { "(bad)",          { XX } },
8147   },
8148
8149   /* VEX_LEN_6B_P_2 */
8150   {
8151     { "vpackssdw",      { XM, Vex128, EXx } },
8152     { "(bad)",          { XX } },
8153   },
8154
8155   /* VEX_LEN_6C_P_2 */
8156   {
8157     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8158     { "(bad)",          { XX } },
8159   },
8160
8161   /* VEX_LEN_6D_P_2 */
8162   {
8163     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8164     { "(bad)",          { XX } },
8165   },
8166
8167   /* VEX_LEN_6E_P_2 */
8168   {
8169     { "vmovK",          { XM, Edq } },
8170     { "(bad)",          { XX } },
8171   },
8172
8173   /* VEX_LEN_70_P_1 */
8174   {
8175     { "vpshufhw",       { XM, EXx, Ib } },
8176     { "(bad)",          { XX } },
8177   },
8178
8179   /* VEX_LEN_70_P_2 */
8180   {
8181     { "vpshufd",        { XM, EXx, Ib } },
8182     { "(bad)",          { XX } },
8183   },
8184
8185   /* VEX_LEN_70_P_3 */
8186   {
8187     { "vpshuflw",       { XM, EXx, Ib } },
8188     { "(bad)",          { XX } },
8189   },
8190
8191   /* VEX_LEN_71_R_2_P_2 */
8192   {
8193     { "vpsrlw",         { Vex128, XS, Ib } },
8194     { "(bad)",          { XX } },
8195   },
8196
8197   /* VEX_LEN_71_R_4_P_2 */
8198   {
8199     { "vpsraw",         { Vex128, XS, Ib } },
8200     { "(bad)",          { XX } },
8201   },
8202
8203   /* VEX_LEN_71_R_6_P_2 */
8204   {
8205     { "vpsllw",         { Vex128, XS, Ib } },
8206     { "(bad)",          { XX } },
8207   },
8208
8209   /* VEX_LEN_72_R_2_P_2 */
8210   {
8211     { "vpsrld",         { Vex128, XS, Ib } },
8212     { "(bad)",          { XX } },
8213   },
8214
8215   /* VEX_LEN_72_R_4_P_2 */
8216   {
8217     { "vpsrad",         { Vex128, XS, Ib } },
8218     { "(bad)",          { XX } },
8219   },
8220
8221   /* VEX_LEN_72_R_6_P_2 */
8222   {
8223     { "vpslld",         { Vex128, XS, Ib } },
8224     { "(bad)",          { XX } },
8225   },
8226
8227   /* VEX_LEN_73_R_2_P_2 */
8228   {
8229     { "vpsrlq",         { Vex128, XS, Ib } },
8230     { "(bad)",          { XX } },
8231   },
8232
8233   /* VEX_LEN_73_R_3_P_2 */
8234   {
8235     { "vpsrldq",        { Vex128, XS, Ib } },
8236     { "(bad)",          { XX } },
8237   },
8238
8239   /* VEX_LEN_73_R_6_P_2 */
8240   {
8241     { "vpsllq",         { Vex128, XS, Ib } },
8242     { "(bad)",          { XX } },
8243   },
8244
8245   /* VEX_LEN_73_R_7_P_2 */
8246   {
8247     { "vpslldq",        { Vex128, XS, Ib } },
8248     { "(bad)",          { XX } },
8249   },
8250
8251   /* VEX_LEN_74_P_2 */
8252   {
8253     { "vpcmpeqb",       { XM, Vex128, EXx } },
8254     { "(bad)",          { XX } },
8255   },
8256
8257   /* VEX_LEN_75_P_2 */
8258   {
8259     { "vpcmpeqw",       { XM, Vex128, EXx } },
8260     { "(bad)",          { XX } },
8261   },
8262
8263   /* VEX_LEN_76_P_2 */
8264   {
8265     { "vpcmpeqd",       { XM, Vex128, EXx } },
8266     { "(bad)",          { XX } },
8267   },
8268
8269   /* VEX_LEN_7E_P_1 */
8270   {
8271     { "vmovq",          { XM, EXq } },
8272     { "(bad)",          { XX } },
8273   },
8274
8275   /* VEX_LEN_7E_P_2 */
8276   {
8277     { "vmovK",          { Edq, XM } },
8278     { "(bad)",          { XX } },
8279   },
8280
8281   /* VEX_LEN_AE_R_2_M_0 */
8282   {
8283     { "vldmxcsr",       { Md } },
8284     { "(bad)",          { XX } },
8285   },
8286
8287   /* VEX_LEN_AE_R_3_M_0 */
8288   {
8289     { "vstmxcsr",       { Md } },
8290     { "(bad)",          { XX } },
8291   },
8292
8293   /* VEX_LEN_C2_P_1 */
8294   {
8295     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8296     { "(bad)",          { XX } },
8297   },
8298
8299   /* VEX_LEN_C2_P_3 */
8300   {
8301     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8302     { "(bad)",          { XX } },
8303   },
8304
8305   /* VEX_LEN_C4_P_2 */
8306   {
8307     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8308     { "(bad)",          { XX } },
8309   },
8310
8311   /* VEX_LEN_C5_P_2 */
8312   {
8313     { "vpextrw",        { Gdq, XS, Ib } },
8314     { "(bad)",          { XX } },
8315   },
8316
8317   /* VEX_LEN_D1_P_2 */
8318   {
8319     { "vpsrlw",         { XM, Vex128, EXx } },
8320     { "(bad)",          { XX } },
8321   },
8322
8323   /* VEX_LEN_D2_P_2 */
8324   {
8325     { "vpsrld",         { XM, Vex128, EXx } },
8326     { "(bad)",          { XX } },
8327   },
8328
8329   /* VEX_LEN_D3_P_2 */
8330   {
8331     { "vpsrlq",         { XM, Vex128, EXx } },
8332     { "(bad)",          { XX } },
8333   },
8334
8335   /* VEX_LEN_D4_P_2 */
8336   {
8337     { "vpaddq",         { XM, Vex128, EXx } },
8338     { "(bad)",          { XX } },
8339   },
8340
8341   /* VEX_LEN_D5_P_2 */
8342   {
8343     { "vpmullw",        { XM, Vex128, EXx } },
8344     { "(bad)",          { XX } },
8345   },
8346
8347   /* VEX_LEN_D6_P_2 */
8348   {
8349     { "vmovq",          { EXqS, XM } },
8350     { "(bad)",          { XX } },
8351   },
8352
8353   /* VEX_LEN_D7_P_2_M_1 */
8354   {
8355     { "vpmovmskb",      { Gdq, XS } },
8356     { "(bad)",          { XX } },
8357   },
8358
8359   /* VEX_LEN_D8_P_2 */
8360   {
8361     { "vpsubusb",       { XM, Vex128, EXx } },
8362     { "(bad)",          { XX } },
8363   },
8364
8365   /* VEX_LEN_D9_P_2 */
8366   {
8367     { "vpsubusw",       { XM, Vex128, EXx } },
8368     { "(bad)",          { XX } },
8369   },
8370
8371   /* VEX_LEN_DA_P_2 */
8372   {
8373     { "vpminub",        { XM, Vex128, EXx } },
8374     { "(bad)",          { XX } },
8375   },
8376
8377   /* VEX_LEN_DB_P_2 */
8378   {
8379     { "vpand",          { XM, Vex128, EXx } },
8380     { "(bad)",          { XX } },
8381   },
8382
8383   /* VEX_LEN_DC_P_2 */
8384   {
8385     { "vpaddusb",       { XM, Vex128, EXx } },
8386     { "(bad)",          { XX } },
8387   },
8388
8389   /* VEX_LEN_DD_P_2 */
8390   {
8391     { "vpaddusw",       { XM, Vex128, EXx } },
8392     { "(bad)",          { XX } },
8393   },
8394
8395   /* VEX_LEN_DE_P_2 */
8396   {
8397     { "vpmaxub",        { XM, Vex128, EXx } },
8398     { "(bad)",          { XX } },
8399   },
8400
8401   /* VEX_LEN_DF_P_2 */
8402   {
8403     { "vpandn",         { XM, Vex128, EXx } },
8404     { "(bad)",          { XX } },
8405   },
8406
8407   /* VEX_LEN_E0_P_2 */
8408   {
8409     { "vpavgb",         { XM, Vex128, EXx } },
8410     { "(bad)",          { XX } },
8411   },
8412
8413   /* VEX_LEN_E1_P_2 */
8414   {
8415     { "vpsraw",         { XM, Vex128, EXx } },
8416     { "(bad)",          { XX } },
8417   },
8418
8419   /* VEX_LEN_E2_P_2 */
8420   {
8421     { "vpsrad",         { XM, Vex128, EXx } },
8422     { "(bad)",          { XX } },
8423   },
8424
8425   /* VEX_LEN_E3_P_2 */
8426   {
8427     { "vpavgw",         { XM, Vex128, EXx } },
8428     { "(bad)",          { XX } },
8429   },
8430
8431   /* VEX_LEN_E4_P_2 */
8432   {
8433     { "vpmulhuw",       { XM, Vex128, EXx } },
8434     { "(bad)",          { XX } },
8435   },
8436
8437   /* VEX_LEN_E5_P_2 */
8438   {
8439     { "vpmulhw",        { XM, Vex128, EXx } },
8440     { "(bad)",          { XX } },
8441   },
8442
8443   /* VEX_LEN_E8_P_2 */
8444   {
8445     { "vpsubsb",        { XM, Vex128, EXx } },
8446     { "(bad)",          { XX } },
8447   },
8448
8449   /* VEX_LEN_E9_P_2 */
8450   {
8451     { "vpsubsw",        { XM, Vex128, EXx } },
8452     { "(bad)",          { XX } },
8453   },
8454
8455   /* VEX_LEN_EA_P_2 */
8456   {
8457     { "vpminsw",        { XM, Vex128, EXx } },
8458     { "(bad)",          { XX } },
8459   },
8460
8461   /* VEX_LEN_EB_P_2 */
8462   {
8463     { "vpor",           { XM, Vex128, EXx } },
8464     { "(bad)",          { XX } },
8465   },
8466
8467   /* VEX_LEN_EC_P_2 */
8468   {
8469     { "vpaddsb",        { XM, Vex128, EXx } },
8470     { "(bad)",          { XX } },
8471   },
8472
8473   /* VEX_LEN_ED_P_2 */
8474   {
8475     { "vpaddsw",        { XM, Vex128, EXx } },
8476     { "(bad)",          { XX } },
8477   },
8478
8479   /* VEX_LEN_EE_P_2 */
8480   {
8481     { "vpmaxsw",        { XM, Vex128, EXx } },
8482     { "(bad)",          { XX } },
8483   },
8484
8485   /* VEX_LEN_EF_P_2 */
8486   {
8487     { "vpxor",          { XM, Vex128, EXx } },
8488     { "(bad)",          { XX } },
8489   },
8490
8491   /* VEX_LEN_F1_P_2 */
8492   {
8493     { "vpsllw",         { XM, Vex128, EXx } },
8494     { "(bad)",          { XX } },
8495   },
8496
8497   /* VEX_LEN_F2_P_2 */
8498   {
8499     { "vpslld",         { XM, Vex128, EXx } },
8500     { "(bad)",          { XX } },
8501   },
8502
8503   /* VEX_LEN_F3_P_2 */
8504   {
8505     { "vpsllq",         { XM, Vex128, EXx } },
8506     { "(bad)",          { XX } },
8507   },
8508
8509   /* VEX_LEN_F4_P_2 */
8510   {
8511     { "vpmuludq",       { XM, Vex128, EXx } },
8512     { "(bad)",          { XX } },
8513   },
8514
8515   /* VEX_LEN_F5_P_2 */
8516   {
8517     { "vpmaddwd",       { XM, Vex128, EXx } },
8518     { "(bad)",          { XX } },
8519   },
8520
8521   /* VEX_LEN_F6_P_2 */
8522   {
8523     { "vpsadbw",        { XM, Vex128, EXx } },
8524     { "(bad)",          { XX } },
8525   },
8526
8527   /* VEX_LEN_F7_P_2 */
8528   {
8529     { "vmaskmovdqu",    { XM, XS } },
8530     { "(bad)",          { XX } },
8531   },
8532
8533   /* VEX_LEN_F8_P_2 */
8534   {
8535     { "vpsubb",         { XM, Vex128, EXx } },
8536     { "(bad)",          { XX } },
8537   },
8538
8539   /* VEX_LEN_F9_P_2 */
8540   {
8541     { "vpsubw",         { XM, Vex128, EXx } },
8542     { "(bad)",          { XX } },
8543   },
8544
8545   /* VEX_LEN_FA_P_2 */
8546   {
8547     { "vpsubd",         { XM, Vex128, EXx } },
8548     { "(bad)",          { XX } },
8549   },
8550
8551   /* VEX_LEN_FB_P_2 */
8552   {
8553     { "vpsubq",         { XM, Vex128, EXx } },
8554     { "(bad)",          { XX } },
8555   },
8556
8557   /* VEX_LEN_FC_P_2 */
8558   {
8559     { "vpaddb",         { XM, Vex128, EXx } },
8560     { "(bad)",          { XX } },
8561   },
8562
8563   /* VEX_LEN_FD_P_2 */
8564   {
8565     { "vpaddw",         { XM, Vex128, EXx } },
8566     { "(bad)",          { XX } },
8567   },
8568
8569   /* VEX_LEN_FE_P_2 */
8570   {
8571     { "vpaddd",         { XM, Vex128, EXx } },
8572     { "(bad)",          { XX } },
8573   },
8574
8575   /* VEX_LEN_3800_P_2 */
8576   {
8577     { "vpshufb",        { XM, Vex128, EXx } },
8578     { "(bad)",          { XX } },
8579   },
8580
8581   /* VEX_LEN_3801_P_2 */
8582   {
8583     { "vphaddw",        { XM, Vex128, EXx } },
8584     { "(bad)",          { XX } },
8585   },
8586
8587   /* VEX_LEN_3802_P_2 */
8588   {
8589     { "vphaddd",        { XM, Vex128, EXx } },
8590     { "(bad)",          { XX } },
8591   },
8592
8593   /* VEX_LEN_3803_P_2 */
8594   {
8595     { "vphaddsw",       { XM, Vex128, EXx } },
8596     { "(bad)",          { XX } },
8597   },
8598
8599   /* VEX_LEN_3804_P_2 */
8600   {
8601     { "vpmaddubsw",     { XM, Vex128, EXx } },
8602     { "(bad)",          { XX } },
8603   },
8604
8605   /* VEX_LEN_3805_P_2 */
8606   {
8607     { "vphsubw",        { XM, Vex128, EXx } },
8608     { "(bad)",          { XX } },
8609   },
8610
8611   /* VEX_LEN_3806_P_2 */
8612   {
8613     { "vphsubd",        { XM, Vex128, EXx } },
8614     { "(bad)",          { XX } },
8615   },
8616
8617   /* VEX_LEN_3807_P_2 */
8618   {
8619     { "vphsubsw",       { XM, Vex128, EXx } },
8620     { "(bad)",          { XX } },
8621   },
8622
8623   /* VEX_LEN_3808_P_2 */
8624   {
8625     { "vpsignb",        { XM, Vex128, EXx } },
8626     { "(bad)",          { XX } },
8627   },
8628
8629   /* VEX_LEN_3809_P_2 */
8630   {
8631     { "vpsignw",        { XM, Vex128, EXx } },
8632     { "(bad)",          { XX } },
8633   },
8634
8635   /* VEX_LEN_380A_P_2 */
8636   {
8637     { "vpsignd",        { XM, Vex128, EXx } },
8638     { "(bad)",          { XX } },
8639   },
8640
8641   /* VEX_LEN_380B_P_2 */
8642   {
8643     { "vpmulhrsw",      { XM, Vex128, EXx } },
8644     { "(bad)",          { XX } },
8645   },
8646
8647   /* VEX_LEN_3819_P_2_M_0 */
8648   {
8649     { "(bad)",          { XX } },
8650     { "vbroadcastsd",   { XM, Mq } },
8651   },
8652
8653   /* VEX_LEN_381A_P_2_M_0 */
8654   {
8655     { "(bad)",          { XX } },
8656     { "vbroadcastf128", { XM, Mxmm } },
8657   },
8658
8659   /* VEX_LEN_381C_P_2 */
8660   {
8661     { "vpabsb",         { XM, EXx } },
8662     { "(bad)",          { XX } },
8663   },
8664
8665   /* VEX_LEN_381D_P_2 */
8666   {
8667     { "vpabsw",         { XM, EXx } },
8668     { "(bad)",          { XX } },
8669   },
8670
8671   /* VEX_LEN_381E_P_2 */
8672   {
8673     { "vpabsd",         { XM, EXx } },
8674     { "(bad)",          { XX } },
8675   },
8676
8677   /* VEX_LEN_3820_P_2 */
8678   {
8679     { "vpmovsxbw",      { XM, EXq } },
8680     { "(bad)",          { XX } },
8681   },
8682
8683   /* VEX_LEN_3821_P_2 */
8684   {
8685     { "vpmovsxbd",      { XM, EXd } },
8686     { "(bad)",          { XX } },
8687   },
8688
8689   /* VEX_LEN_3822_P_2 */
8690   {
8691     { "vpmovsxbq",      { XM, EXw } },
8692     { "(bad)",          { XX } },
8693   },
8694
8695   /* VEX_LEN_3823_P_2 */
8696   {
8697     { "vpmovsxwd",      { XM, EXq } },
8698     { "(bad)",          { XX } },
8699   },
8700
8701   /* VEX_LEN_3824_P_2 */
8702   {
8703     { "vpmovsxwq",      { XM, EXd } },
8704     { "(bad)",          { XX } },
8705   },
8706
8707   /* VEX_LEN_3825_P_2 */
8708   {
8709     { "vpmovsxdq",      { XM, EXq } },
8710     { "(bad)",          { XX } },
8711   },
8712
8713   /* VEX_LEN_3828_P_2 */
8714   {
8715     { "vpmuldq",        { XM, Vex128, EXx } },
8716     { "(bad)",          { XX } },
8717   },
8718
8719   /* VEX_LEN_3829_P_2 */
8720   {
8721     { "vpcmpeqq",       { XM, Vex128, EXx } },
8722     { "(bad)",          { XX } },
8723   },
8724
8725   /* VEX_LEN_382A_P_2_M_0 */
8726   {
8727     { "vmovntdqa",      { XM, Mx } },
8728     { "(bad)",          { XX } },
8729   },
8730
8731   /* VEX_LEN_382B_P_2 */
8732   {
8733     { "vpackusdw",      { XM, Vex128, EXx } },
8734     { "(bad)",          { XX } },
8735   },
8736
8737   /* VEX_LEN_3830_P_2 */
8738   {
8739     { "vpmovzxbw",      { XM, EXq } },
8740     { "(bad)",          { XX } },
8741   },
8742
8743   /* VEX_LEN_3831_P_2 */
8744   {
8745     { "vpmovzxbd",      { XM, EXd } },
8746     { "(bad)",          { XX } },
8747   },
8748
8749   /* VEX_LEN_3832_P_2 */
8750   {
8751     { "vpmovzxbq",      { XM, EXw } },
8752     { "(bad)",          { XX } },
8753   },
8754
8755   /* VEX_LEN_3833_P_2 */
8756   {
8757     { "vpmovzxwd",      { XM, EXq } },
8758     { "(bad)",          { XX } },
8759   },
8760
8761   /* VEX_LEN_3834_P_2 */
8762   {
8763     { "vpmovzxwq",      { XM, EXd } },
8764     { "(bad)",          { XX } },
8765   },
8766
8767   /* VEX_LEN_3835_P_2 */
8768   {
8769     { "vpmovzxdq",      { XM, EXq } },
8770     { "(bad)",          { XX } },
8771   },
8772
8773   /* VEX_LEN_3837_P_2 */
8774   {
8775     { "vpcmpgtq",       { XM, Vex128, EXx } },
8776     { "(bad)",          { XX } },
8777   },
8778
8779   /* VEX_LEN_3838_P_2 */
8780   {
8781     { "vpminsb",        { XM, Vex128, EXx } },
8782     { "(bad)",          { XX } },
8783   },
8784
8785   /* VEX_LEN_3839_P_2 */
8786   {
8787     { "vpminsd",        { XM, Vex128, EXx } },
8788     { "(bad)",          { XX } },
8789   },
8790
8791   /* VEX_LEN_383A_P_2 */
8792   {
8793     { "vpminuw",        { XM, Vex128, EXx } },
8794     { "(bad)",          { XX } },
8795   },
8796
8797   /* VEX_LEN_383B_P_2 */
8798   {
8799     { "vpminud",        { XM, Vex128, EXx } },
8800     { "(bad)",          { XX } },
8801   },
8802
8803   /* VEX_LEN_383C_P_2 */
8804   {
8805     { "vpmaxsb",        { XM, Vex128, EXx } },
8806     { "(bad)",          { XX } },
8807   },
8808
8809   /* VEX_LEN_383D_P_2 */
8810   {
8811     { "vpmaxsd",        { XM, Vex128, EXx } },
8812     { "(bad)",          { XX } },
8813   },
8814
8815   /* VEX_LEN_383E_P_2 */
8816   {
8817     { "vpmaxuw",        { XM, Vex128, EXx } },
8818     { "(bad)",          { XX } },
8819   },
8820
8821   /* VEX_LEN_383F_P_2 */
8822   {
8823     { "vpmaxud",        { XM, Vex128, EXx } },
8824     { "(bad)",          { XX } },
8825   },
8826
8827   /* VEX_LEN_3840_P_2 */
8828   {
8829     { "vpmulld",        { XM, Vex128, EXx } },
8830     { "(bad)",          { XX } },
8831   },
8832
8833   /* VEX_LEN_3841_P_2 */
8834   {
8835     { "vphminposuw",    { XM, EXx } },
8836     { "(bad)",          { XX } },
8837   },
8838
8839   /* VEX_LEN_38DB_P_2 */
8840   {
8841     { "vaesimc",        { XM, EXx } },
8842     { "(bad)",          { XX } },
8843   },
8844
8845   /* VEX_LEN_38DC_P_2 */
8846   {
8847     { "vaesenc",        { XM, Vex128, EXx } },
8848     { "(bad)",          { XX } },
8849   },
8850
8851   /* VEX_LEN_38DD_P_2 */
8852   {
8853     { "vaesenclast",    { XM, Vex128, EXx } },
8854     { "(bad)",          { XX } },
8855   },
8856
8857   /* VEX_LEN_38DE_P_2 */
8858   {
8859     { "vaesdec",        { XM, Vex128, EXx } },
8860     { "(bad)",          { XX } },
8861   },
8862
8863   /* VEX_LEN_38DF_P_2 */
8864   {
8865     { "vaesdeclast",    { XM, Vex128, EXx } },
8866     { "(bad)",          { XX } },
8867   },
8868
8869   /* VEX_LEN_3A06_P_2 */
8870   {
8871     { "(bad)",          { XX } },
8872     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8873   },
8874
8875   /* VEX_LEN_3A0A_P_2 */
8876   {
8877     { "vroundss",       { XM, Vex128, EXd, Ib } },
8878     { "(bad)",          { XX } },
8879   },
8880
8881   /* VEX_LEN_3A0B_P_2 */
8882   {
8883     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8884     { "(bad)",          { XX } },
8885   },
8886
8887   /* VEX_LEN_3A0E_P_2 */
8888   {
8889     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8890     { "(bad)",          { XX } },
8891   },
8892
8893   /* VEX_LEN_3A0F_P_2 */
8894   {
8895     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8896     { "(bad)",          { XX } },
8897   },
8898
8899   /* VEX_LEN_3A14_P_2 */
8900   {
8901     { "vpextrb",        { Edqb, XM, Ib } },
8902     { "(bad)",          { XX } },
8903   },
8904
8905   /* VEX_LEN_3A15_P_2 */
8906   {
8907     { "vpextrw",        { Edqw, XM, Ib } },
8908     { "(bad)",          { XX } },
8909   },
8910
8911   /* VEX_LEN_3A16_P_2  */
8912   {
8913     { "vpextrK",        { Edq, XM, Ib } },
8914     { "(bad)",          { XX } },
8915   },
8916
8917   /* VEX_LEN_3A17_P_2 */
8918   {
8919     { "vextractps",     { Edqd, XM, Ib } },
8920     { "(bad)",          { XX } },
8921   },
8922
8923   /* VEX_LEN_3A18_P_2 */
8924   {
8925     { "(bad)",          { XX } },
8926     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8927   },
8928
8929   /* VEX_LEN_3A19_P_2 */
8930   {
8931     { "(bad)",          { XX } },
8932     { "vextractf128",   { EXxmm, XM, Ib } },
8933   },
8934
8935   /* VEX_LEN_3A20_P_2 */
8936   {
8937     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8938     { "(bad)",          { XX } },
8939   },
8940
8941   /* VEX_LEN_3A21_P_2 */
8942   {
8943     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8944     { "(bad)",          { XX } },
8945   },
8946
8947   /* VEX_LEN_3A22_P_2 */
8948   {
8949     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8950     { "(bad)",          { XX } },
8951   },
8952
8953   /* VEX_LEN_3A41_P_2 */
8954   {
8955     { "vdppd",          { XM, Vex128, EXx, Ib } },
8956     { "(bad)",          { XX } },
8957   },
8958
8959   /* VEX_LEN_3A42_P_2 */
8960   {
8961     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
8962     { "(bad)",          { XX } },
8963   },
8964
8965   /* VEX_LEN_3A44_P_2 */
8966   {
8967     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
8968     { "(bad)",          { XX } },
8969   },
8970
8971   /* VEX_LEN_3A4C_P_2 */
8972   {
8973     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
8974     { "(bad)",          { XX } },
8975   },
8976
8977   /* VEX_LEN_3A60_P_2 */
8978   {
8979     { "vpcmpestrm",     { XM, EXx, Ib } },
8980     { "(bad)",          { XX } },
8981   },
8982
8983   /* VEX_LEN_3A61_P_2 */
8984   {
8985     { "vpcmpestri",     { XM, EXx, Ib } },
8986     { "(bad)",          { XX } },
8987   },
8988
8989   /* VEX_LEN_3A62_P_2 */
8990   {
8991     { "vpcmpistrm",     { XM, EXx, Ib } },
8992     { "(bad)",          { XX } },
8993   },
8994
8995   /* VEX_LEN_3A63_P_2 */
8996   {
8997     { "vpcmpistri",     { XM, EXx, Ib } },
8998     { "(bad)",          { XX } },
8999   },
9000
9001   /* VEX_LEN_3A6A_P_2 */
9002   {
9003     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9004     { "(bad)",          { XX } },
9005   },
9006
9007   /* VEX_LEN_3A6B_P_2 */
9008   {
9009     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9010     { "(bad)",          { XX } },
9011   },
9012
9013   /* VEX_LEN_3A6E_P_2 */
9014   {
9015     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9016     { "(bad)",          { XX } },
9017   },
9018
9019   /* VEX_LEN_3A6F_P_2 */
9020   {
9021     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9022     { "(bad)",          { XX } },
9023   },
9024
9025   /* VEX_LEN_3A7A_P_2 */
9026   {
9027     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9028     { "(bad)",          { XX } },
9029   },
9030
9031   /* VEX_LEN_3A7B_P_2 */
9032   {
9033     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9034     { "(bad)",          { XX } },
9035   },
9036
9037   /* VEX_LEN_3A7E_P_2 */
9038   {
9039     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9040     { "(bad)",          { XX } },
9041   },
9042
9043   /* VEX_LEN_3A7F_P_2 */
9044   {
9045     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9046     { "(bad)",          { XX } },
9047   },
9048
9049   /* VEX_LEN_3ADF_P_2 */
9050   {
9051     { "vaeskeygenassist", { XM, EXx, Ib } },
9052     { "(bad)",          { XX } },
9053   },
9054 };
9055
9056 static const struct dis386 mod_table[][2] = {
9057   {
9058     /* MOD_8D */
9059     { "leaS",           { Gv, M } },
9060     { "(bad)",          { XX } },
9061   },
9062   {
9063     /* MOD_0F01_REG_0 */
9064     { X86_64_TABLE (X86_64_0F01_REG_0) },
9065     { RM_TABLE (RM_0F01_REG_0) },
9066   },
9067   {
9068     /* MOD_0F01_REG_1 */
9069     { X86_64_TABLE (X86_64_0F01_REG_1) },
9070     { RM_TABLE (RM_0F01_REG_1) },
9071   },
9072   {
9073     /* MOD_0F01_REG_2 */
9074     { X86_64_TABLE (X86_64_0F01_REG_2) },
9075     { RM_TABLE (RM_0F01_REG_2) },
9076   },
9077   {
9078     /* MOD_0F01_REG_3 */
9079     { X86_64_TABLE (X86_64_0F01_REG_3) },
9080     { RM_TABLE (RM_0F01_REG_3) },
9081   },
9082   {
9083     /* MOD_0F01_REG_7 */
9084     { "invlpg",         { Mb } },
9085     { RM_TABLE (RM_0F01_REG_7) },
9086   },
9087   {
9088     /* MOD_0F12_PREFIX_0 */
9089     { "movlps",         { XM, EXq } },
9090     { "movhlps",        { XM, EXq } },
9091   },
9092   {
9093     /* MOD_0F13 */
9094     { "movlpX",         { EXq, XM } },
9095     { "(bad)",          { XX } },
9096   },
9097   {
9098     /* MOD_0F16_PREFIX_0 */
9099     { "movhps",         { XM, EXq } },
9100     { "movlhps",        { XM, EXq } },
9101   },
9102   {
9103     /* MOD_0F17 */
9104     { "movhpX",         { EXq, XM } },
9105     { "(bad)",          { XX } },
9106   },
9107   {
9108     /* MOD_0F18_REG_0 */
9109     { "prefetchnta",    { Mb } },
9110     { "(bad)",          { XX } },
9111   },
9112   {
9113     /* MOD_0F18_REG_1 */
9114     { "prefetcht0",     { Mb } },
9115     { "(bad)",          { XX } },
9116   },
9117   {
9118     /* MOD_0F18_REG_2 */
9119     { "prefetcht1",     { Mb } },
9120     { "(bad)",          { XX } },
9121   },
9122   {
9123     /* MOD_0F18_REG_3 */
9124     { "prefetcht2",     { Mb } },
9125     { "(bad)",          { XX } },
9126   },
9127   {
9128     /* MOD_0F20 */
9129     { "(bad)",          { XX } },
9130     { "movZ",           { Rm, Cm } },
9131   },
9132   {
9133     /* MOD_0F21 */
9134     { "(bad)",          { XX } },
9135     { "movZ",           { Rm, Dm } },
9136   },
9137   {
9138     /* MOD_0F22 */
9139     { "(bad)",          { XX } },
9140     { "movZ",           { Cm, Rm } },
9141   },
9142   {
9143     /* MOD_0F23 */
9144     { "(bad)",          { XX } },
9145     { "movZ",           { Dm, Rm } },
9146   },
9147   {
9148     /* MOD_0F24 */
9149     { "(bad)",          { XX } },
9150     { "movL",           { Rd, Td } },
9151   },
9152   {
9153     /* MOD_0F26 */
9154     { "(bad)",          { XX } },
9155     { "movL",           { Td, Rd } },
9156   },
9157   {
9158     /* MOD_0F2B_PREFIX_0 */
9159     {"movntps",         { Mx, XM } },
9160     { "(bad)",          { XX } },
9161   },
9162   {
9163     /* MOD_0F2B_PREFIX_1 */
9164     {"movntss",         { Md, XM } },
9165     { "(bad)",          { XX } },
9166   },
9167   {
9168     /* MOD_0F2B_PREFIX_2 */
9169     {"movntpd",         { Mx, XM } },
9170     { "(bad)",          { XX } },
9171   },
9172   {
9173     /* MOD_0F2B_PREFIX_3 */
9174     {"movntsd",         { Mq, XM } },
9175     { "(bad)",          { XX } },
9176   },
9177   {
9178     /* MOD_0F51 */
9179     { "(bad)",          { XX } },
9180     { "movmskpX",       { Gdq, XS } },
9181   },
9182   {
9183     /* MOD_0F71_REG_2 */
9184     { "(bad)",          { XX } },
9185     { "psrlw",          { MS, Ib } },
9186   },
9187   {
9188     /* MOD_0F71_REG_4 */
9189     { "(bad)",          { XX } },
9190     { "psraw",          { MS, Ib } },
9191   },
9192   {
9193     /* MOD_0F71_REG_6 */
9194     { "(bad)",          { XX } },
9195     { "psllw",          { MS, Ib } },
9196   },
9197   {
9198     /* MOD_0F72_REG_2 */
9199     { "(bad)",          { XX } },
9200     { "psrld",          { MS, Ib } },
9201   },
9202   {
9203     /* MOD_0F72_REG_4 */
9204     { "(bad)",          { XX } },
9205     { "psrad",          { MS, Ib } },
9206   },
9207   {
9208     /* MOD_0F72_REG_6 */
9209     { "(bad)",          { XX } },
9210     { "pslld",          { MS, Ib } },
9211   },
9212   {
9213     /* MOD_0F73_REG_2 */
9214     { "(bad)",          { XX } },
9215     { "psrlq",          { MS, Ib } },
9216   },
9217   {
9218     /* MOD_0F73_REG_3 */
9219     { "(bad)",          { XX } },
9220     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9221   },
9222   {
9223     /* MOD_0F73_REG_6 */
9224     { "(bad)",          { XX } },
9225     { "psllq",          { MS, Ib } },
9226   },
9227   {
9228     /* MOD_0F73_REG_7 */
9229     { "(bad)",          { XX } },
9230     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9231   },
9232   {
9233     /* MOD_0FAE_REG_0 */
9234     { "fxsave",         { M } },
9235     { "(bad)",          { XX } },
9236   },
9237   {
9238     /* MOD_0FAE_REG_1 */
9239     { "fxrstor",        { M } },
9240     { "(bad)",          { XX } },
9241   },
9242   {
9243     /* MOD_0FAE_REG_2 */
9244     { "ldmxcsr",        { Md } },
9245     { "(bad)",          { XX } },
9246   },
9247   {
9248     /* MOD_0FAE_REG_3 */
9249     { "stmxcsr",        { Md } },
9250     { "(bad)",          { XX } },
9251   },
9252   {
9253     /* MOD_0FAE_REG_4 */
9254     { "xsave",          { M } },
9255     { "(bad)",          { XX } },
9256   },
9257   {
9258     /* MOD_0FAE_REG_5 */
9259     { "xrstor",         { M } },
9260     { RM_TABLE (RM_0FAE_REG_5) },
9261   },
9262   {
9263     /* MOD_0FAE_REG_6 */
9264     { "xsaveopt",       { M } },
9265     { RM_TABLE (RM_0FAE_REG_6) },
9266   },
9267   {
9268     /* MOD_0FAE_REG_7 */
9269     { "clflush",        { Mb } },
9270     { RM_TABLE (RM_0FAE_REG_7) },
9271   },
9272   {
9273     /* MOD_0FB2 */
9274     { "lssS",           { Gv, Mp } },
9275     { "(bad)",          { XX } },
9276   },
9277   {
9278     /* MOD_0FB4 */
9279     { "lfsS",           { Gv, Mp } },
9280     { "(bad)",          { XX } },
9281   },
9282   {
9283     /* MOD_0FB5 */
9284     { "lgsS",           { Gv, Mp } },
9285     { "(bad)",          { XX } },
9286   },
9287   {
9288     /* MOD_0FC7_REG_6 */
9289     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9290     { "(bad)",          { XX } },
9291   },
9292   {
9293     /* MOD_0FC7_REG_7 */
9294     { "vmptrst",        { Mq } },
9295     { "(bad)",          { XX } },
9296   },
9297   {
9298     /* MOD_0FD7 */
9299     { "(bad)",          { XX } },
9300     { "pmovmskb",       { Gdq, MS } },
9301   },
9302   {
9303     /* MOD_0FE7_PREFIX_2 */
9304     { "movntdq",        { Mx, XM } },
9305     { "(bad)",          { XX } },
9306   },
9307   {
9308     /* MOD_0FF0_PREFIX_3 */
9309     { "lddqu",          { XM, M } },
9310     { "(bad)",          { XX } },
9311   },
9312   {
9313     /* MOD_0F382A_PREFIX_2 */
9314     { "movntdqa",       { XM, Mx } },
9315     { "(bad)",          { XX } },
9316   },
9317   {
9318     /* MOD_62_32BIT */
9319     { "bound{S|}",      { Gv, Ma } },
9320     { "(bad)",          { XX } },
9321   },
9322   {
9323     /* MOD_C4_32BIT */
9324     { "lesS",           { Gv, Mp } },
9325     { VEX_C4_TABLE (VEX_0F) },
9326   },
9327   {
9328     /* MOD_C5_32BIT */
9329     { "ldsS",           { Gv, Mp } },
9330     { VEX_C5_TABLE (VEX_0F) },
9331   },
9332   {
9333     /* MOD_VEX_12_PREFIX_0 */
9334     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9335     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9336   },
9337   {
9338     /* MOD_VEX_13 */
9339     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9340     { "(bad)",          { XX } },
9341   },
9342   {
9343     /* MOD_VEX_16_PREFIX_0 */
9344     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9345     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9346   },
9347   {
9348     /* MOD_VEX_17 */
9349     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9350     { "(bad)",          { XX } },
9351   },
9352   {
9353     /* MOD_VEX_2B */
9354     { "vmovntpX",       { Mx, XM } },
9355     { "(bad)",          { XX } },
9356   },
9357   {
9358     /* MOD_VEX_51 */
9359     { "(bad)",          { XX } },
9360     { "vmovmskpX",      { Gdq, XS } },
9361   },
9362   {
9363     /* MOD_VEX_71_REG_2 */
9364     { "(bad)",          { XX } },
9365     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9366   },
9367   {
9368     /* MOD_VEX_71_REG_4 */
9369     { "(bad)",          { XX } },
9370     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9371   },
9372   {
9373     /* MOD_VEX_71_REG_6 */
9374     { "(bad)",          { XX } },
9375     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9376   },
9377   {
9378     /* MOD_VEX_72_REG_2 */
9379     { "(bad)",          { XX } },
9380     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9381   },
9382   {
9383     /* MOD_VEX_72_REG_4 */
9384     { "(bad)",          { XX } },
9385     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9386   },
9387   {
9388     /* MOD_VEX_72_REG_6 */
9389     { "(bad)",          { XX } },
9390     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9391   },
9392   {
9393     /* MOD_VEX_73_REG_2 */
9394     { "(bad)",          { XX } },
9395     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9396   },
9397   {
9398     /* MOD_VEX_73_REG_3 */
9399     { "(bad)",          { XX } },
9400     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9401   },
9402   {
9403     /* MOD_VEX_73_REG_6 */
9404     { "(bad)",          { XX } },
9405     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9406   },
9407   {
9408     /* MOD_VEX_73_REG_7 */
9409     { "(bad)",          { XX } },
9410     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9411   },
9412   {
9413     /* MOD_VEX_AE_REG_2 */
9414     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9415     { "(bad)",          { XX } },
9416   },
9417   {
9418     /* MOD_VEX_AE_REG_3 */
9419     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9420     { "(bad)",          { XX } },
9421   },
9422   {
9423     /* MOD_VEX_D7_PREFIX_2 */
9424     { "(bad)",          { XX } },
9425     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9426   },
9427   {
9428     /* MOD_VEX_E7_PREFIX_2 */
9429     { "vmovntdq",       { Mx, XM } },
9430     { "(bad)",          { XX } },
9431   },
9432   {
9433     /* MOD_VEX_F0_PREFIX_3 */
9434     { "vlddqu",         { XM, M } },
9435     { "(bad)",          { XX } },
9436   },
9437   {
9438     /* MOD_VEX_3818_PREFIX_2 */
9439     { "vbroadcastss",   { XM, Md } },
9440     { "(bad)",          { XX } },
9441   },
9442   {
9443     /* MOD_VEX_3819_PREFIX_2 */
9444     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9445     { "(bad)",          { XX } },
9446   },
9447   {
9448     /* MOD_VEX_381A_PREFIX_2 */
9449     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9450     { "(bad)",          { XX } },
9451   },
9452   {
9453     /* MOD_VEX_382A_PREFIX_2 */
9454     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9455     { "(bad)",          { XX } },
9456   },
9457   {
9458     /* MOD_VEX_382C_PREFIX_2 */
9459     { "vmaskmovps",     { XM, Vex, Mx } },
9460     { "(bad)",          { XX } },
9461   },
9462   {
9463     /* MOD_VEX_382D_PREFIX_2 */
9464     { "vmaskmovpd",     { XM, Vex, Mx } },
9465     { "(bad)",          { XX } },
9466   },
9467   {
9468     /* MOD_VEX_382E_PREFIX_2 */
9469     { "vmaskmovps",     { Mx, Vex, XM } },
9470     { "(bad)",          { XX } },
9471   },
9472   {
9473     /* MOD_VEX_382F_PREFIX_2 */
9474     { "vmaskmovpd",     { Mx, Vex, XM } },
9475     { "(bad)",          { XX } },
9476   },
9477 };
9478
9479 static const struct dis386 rm_table[][8] = {
9480   {
9481     /* RM_0F01_REG_0 */
9482     { "(bad)",          { XX } },
9483     { "vmcall",         { Skip_MODRM } },
9484     { "vmlaunch",       { Skip_MODRM } },
9485     { "vmresume",       { Skip_MODRM } },
9486     { "vmxoff",         { Skip_MODRM } },
9487     { "(bad)",          { XX } },
9488     { "(bad)",          { XX } },
9489     { "(bad)",          { XX } },
9490   },
9491   {
9492     /* RM_0F01_REG_1 */
9493     { "monitor",        { { OP_Monitor, 0 } } },
9494     { "mwait",          { { OP_Mwait, 0 } } },
9495     { "(bad)",          { XX } },
9496     { "(bad)",          { XX } },
9497     { "(bad)",          { XX } },
9498     { "(bad)",          { XX } },
9499     { "(bad)",          { XX } },
9500     { "(bad)",          { XX } },
9501   },
9502   {
9503     /* RM_0F01_REG_2 */
9504     { "xgetbv",         { Skip_MODRM } },
9505     { "xsetbv",         { Skip_MODRM } },
9506     { "(bad)",          { XX } },
9507     { "(bad)",          { XX } },
9508     { "(bad)",          { XX } },
9509     { "(bad)",          { XX } },
9510     { "(bad)",          { XX } },
9511     { "(bad)",          { XX } },
9512   },
9513   {
9514     /* RM_0F01_REG_3 */
9515     { "vmrun",          { Skip_MODRM } },
9516     { "vmmcall",        { Skip_MODRM } },
9517     { "vmload",         { Skip_MODRM } },
9518     { "vmsave",         { Skip_MODRM } },
9519     { "stgi",           { Skip_MODRM } },
9520     { "clgi",           { Skip_MODRM } },
9521     { "skinit",         { Skip_MODRM } },
9522     { "invlpga",        { Skip_MODRM } },
9523   },
9524   {
9525     /* RM_0F01_REG_7 */
9526     { "swapgs",         { Skip_MODRM } },
9527     { "rdtscp",         { Skip_MODRM } },
9528     { "(bad)",          { XX } },
9529     { "(bad)",          { XX } },
9530     { "(bad)",          { XX } },
9531     { "(bad)",          { XX } },
9532     { "(bad)",          { XX } },
9533     { "(bad)",          { XX } },
9534   },
9535   {
9536     /* RM_0FAE_REG_5 */
9537     { "lfence",         { Skip_MODRM } },
9538     { "(bad)",          { XX } },
9539     { "(bad)",          { XX } },
9540     { "(bad)",          { XX } },
9541     { "(bad)",          { XX } },
9542     { "(bad)",          { XX } },
9543     { "(bad)",          { XX } },
9544     { "(bad)",          { XX } },
9545   },
9546   {
9547     /* RM_0FAE_REG_6 */
9548     { "mfence",         { Skip_MODRM } },
9549     { "(bad)",          { XX } },
9550     { "(bad)",          { XX } },
9551     { "(bad)",          { XX } },
9552     { "(bad)",          { XX } },
9553     { "(bad)",          { XX } },
9554     { "(bad)",          { XX } },
9555     { "(bad)",          { XX } },
9556   },
9557   {
9558     /* RM_0FAE_REG_7 */
9559     { "sfence",         { Skip_MODRM } },
9560     { "(bad)",          { XX } },
9561     { "(bad)",          { XX } },
9562     { "(bad)",          { XX } },
9563     { "(bad)",          { XX } },
9564     { "(bad)",          { XX } },
9565     { "(bad)",          { XX } },
9566     { "(bad)",          { XX } },
9567   },
9568 };
9569
9570 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9571
9572 static void
9573 ckprefix (void)
9574 {
9575   int newrex;
9576   rex = 0;
9577   rex_original = 0;
9578   rex_ignored = 0;
9579   prefixes = 0;
9580   used_prefixes = 0;
9581   rex_used = 0;
9582   while (1)
9583     {
9584       FETCH_DATA (the_info, codep + 1);
9585       newrex = 0;
9586       switch (*codep)
9587         {
9588         /* REX prefixes family.  */
9589         case 0x40:
9590         case 0x41:
9591         case 0x42:
9592         case 0x43:
9593         case 0x44:
9594         case 0x45:
9595         case 0x46:
9596         case 0x47:
9597         case 0x48:
9598         case 0x49:
9599         case 0x4a:
9600         case 0x4b:
9601         case 0x4c:
9602         case 0x4d:
9603         case 0x4e:
9604         case 0x4f:
9605             if (address_mode == mode_64bit)
9606               newrex = *codep;
9607             else
9608               return;
9609           break;
9610         case 0xf3:
9611           prefixes |= PREFIX_REPZ;
9612           break;
9613         case 0xf2:
9614           prefixes |= PREFIX_REPNZ;
9615           break;
9616         case 0xf0:
9617           prefixes |= PREFIX_LOCK;
9618           break;
9619         case 0x2e:
9620           prefixes |= PREFIX_CS;
9621           break;
9622         case 0x36:
9623           prefixes |= PREFIX_SS;
9624           break;
9625         case 0x3e:
9626           prefixes |= PREFIX_DS;
9627           break;
9628         case 0x26:
9629           prefixes |= PREFIX_ES;
9630           break;
9631         case 0x64:
9632           prefixes |= PREFIX_FS;
9633           break;
9634         case 0x65:
9635           prefixes |= PREFIX_GS;
9636           break;
9637         case 0x66:
9638           prefixes |= PREFIX_DATA;
9639           break;
9640         case 0x67:
9641           prefixes |= PREFIX_ADDR;
9642           break;
9643         case FWAIT_OPCODE:
9644           /* fwait is really an instruction.  If there are prefixes
9645              before the fwait, they belong to the fwait, *not* to the
9646              following instruction.  */
9647           if (prefixes || rex)
9648             {
9649               prefixes |= PREFIX_FWAIT;
9650               codep++;
9651               return;
9652             }
9653           prefixes = PREFIX_FWAIT;
9654           break;
9655         default:
9656           return;
9657         }
9658       /* Rex is ignored when followed by another prefix.  */
9659       if (rex)
9660         {
9661           rex_used = rex;
9662           return;
9663         }
9664       rex = newrex;
9665       rex_original = rex;
9666       codep++;
9667     }
9668 }
9669
9670 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9671    prefix byte.  */
9672
9673 static const char *
9674 prefix_name (int pref, int sizeflag)
9675 {
9676   static const char *rexes [16] =
9677     {
9678       "rex",            /* 0x40 */
9679       "rex.B",          /* 0x41 */
9680       "rex.X",          /* 0x42 */
9681       "rex.XB",         /* 0x43 */
9682       "rex.R",          /* 0x44 */
9683       "rex.RB",         /* 0x45 */
9684       "rex.RX",         /* 0x46 */
9685       "rex.RXB",        /* 0x47 */
9686       "rex.W",          /* 0x48 */
9687       "rex.WB",         /* 0x49 */
9688       "rex.WX",         /* 0x4a */
9689       "rex.WXB",        /* 0x4b */
9690       "rex.WR",         /* 0x4c */
9691       "rex.WRB",        /* 0x4d */
9692       "rex.WRX",        /* 0x4e */
9693       "rex.WRXB",       /* 0x4f */
9694     };
9695
9696   switch (pref)
9697     {
9698     /* REX prefixes family.  */
9699     case 0x40:
9700     case 0x41:
9701     case 0x42:
9702     case 0x43:
9703     case 0x44:
9704     case 0x45:
9705     case 0x46:
9706     case 0x47:
9707     case 0x48:
9708     case 0x49:
9709     case 0x4a:
9710     case 0x4b:
9711     case 0x4c:
9712     case 0x4d:
9713     case 0x4e:
9714     case 0x4f:
9715       return rexes [pref - 0x40];
9716     case 0xf3:
9717       return "repz";
9718     case 0xf2:
9719       return "repnz";
9720     case 0xf0:
9721       return "lock";
9722     case 0x2e:
9723       return "cs";
9724     case 0x36:
9725       return "ss";
9726     case 0x3e:
9727       return "ds";
9728     case 0x26:
9729       return "es";
9730     case 0x64:
9731       return "fs";
9732     case 0x65:
9733       return "gs";
9734     case 0x66:
9735       return (sizeflag & DFLAG) ? "data16" : "data32";
9736     case 0x67:
9737       if (address_mode == mode_64bit)
9738         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9739       else
9740         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9741     case FWAIT_OPCODE:
9742       return "fwait";
9743     default:
9744       return NULL;
9745     }
9746 }
9747
9748 static char op_out[MAX_OPERANDS][100];
9749 static int op_ad, op_index[MAX_OPERANDS];
9750 static int two_source_ops;
9751 static bfd_vma op_address[MAX_OPERANDS];
9752 static bfd_vma op_riprel[MAX_OPERANDS];
9753 static bfd_vma start_pc;
9754
9755 /*
9756  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9757  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9758  *   section of the "Virtual 8086 Mode" chapter.)
9759  * 'pc' should be the address of this instruction, it will
9760  *   be used to print the target address if this is a relative jump or call
9761  * The function returns the length of this instruction in bytes.
9762  */
9763
9764 static char intel_syntax;
9765 static char intel_mnemonic = !SYSV386_COMPAT;
9766 static char open_char;
9767 static char close_char;
9768 static char separator_char;
9769 static char scale_char;
9770
9771 /* Here for backwards compatibility.  When gdb stops using
9772    print_insn_i386_att and print_insn_i386_intel these functions can
9773    disappear, and print_insn_i386 be merged into print_insn.  */
9774 int
9775 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9776 {
9777   intel_syntax = 0;
9778
9779   return print_insn (pc, info);
9780 }
9781
9782 int
9783 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9784 {
9785   intel_syntax = 1;
9786
9787   return print_insn (pc, info);
9788 }
9789
9790 int
9791 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9792 {
9793   intel_syntax = -1;
9794
9795   return print_insn (pc, info);
9796 }
9797
9798 void
9799 print_i386_disassembler_options (FILE *stream)
9800 {
9801   fprintf (stream, _("\n\
9802 The following i386/x86-64 specific disassembler options are supported for use\n\
9803 with the -M switch (multiple options should be separated by commas):\n"));
9804
9805   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9806   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9807   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9808   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9809   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9810   fprintf (stream, _("  att-mnemonic\n"
9811                      "              Display instruction in AT&T mnemonic\n"));
9812   fprintf (stream, _("  intel-mnemonic\n"
9813                      "              Display instruction in Intel mnemonic\n"));
9814   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9815   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9816   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9817   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9818   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9819   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9820 }
9821
9822 /* Get a pointer to struct dis386 with a valid name.  */
9823
9824 static const struct dis386 *
9825 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9826 {
9827   int index, vex_table_index;
9828
9829   if (dp->name != NULL)
9830     return dp;
9831
9832   switch (dp->op[0].bytemode)
9833     {
9834     case USE_REG_TABLE:
9835       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9836       break;
9837
9838     case USE_MOD_TABLE:
9839       index = modrm.mod == 0x3 ? 1 : 0;
9840       dp = &mod_table[dp->op[1].bytemode][index];
9841       break;
9842
9843     case USE_RM_TABLE:
9844       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9845       break;
9846
9847     case USE_PREFIX_TABLE:
9848       if (need_vex)
9849         {
9850           /* The prefix in VEX is implicit.  */
9851           switch (vex.prefix)
9852             {
9853             case 0:
9854               index = 0;
9855               break;
9856             case REPE_PREFIX_OPCODE:
9857               index = 1;
9858               break;
9859             case DATA_PREFIX_OPCODE:
9860               index = 2;
9861               break;
9862             case REPNE_PREFIX_OPCODE:
9863               index = 3;
9864               break;
9865             default:
9866               abort ();
9867               break;
9868             }
9869         }
9870       else
9871         {
9872           index = 0;
9873           used_prefixes |= (prefixes & PREFIX_REPZ);
9874           if (prefixes & PREFIX_REPZ)
9875             {
9876               index = 1;
9877               repz_prefix = NULL;
9878             }
9879           else
9880             {
9881               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9882                  PREFIX_DATA.  */
9883               used_prefixes |= (prefixes & PREFIX_REPNZ);
9884               if (prefixes & PREFIX_REPNZ)
9885                 {
9886                   index = 3;
9887                   repnz_prefix = NULL;
9888                 }
9889               else
9890                 {
9891                   used_prefixes |= (prefixes & PREFIX_DATA);
9892                   if (prefixes & PREFIX_DATA)
9893                     {
9894                       index = 2;
9895                       data_prefix = NULL;
9896                     }
9897                 }
9898             }
9899         }
9900       dp = &prefix_table[dp->op[1].bytemode][index];
9901       break;
9902
9903     case USE_X86_64_TABLE:
9904       index = address_mode == mode_64bit ? 1 : 0;
9905       dp = &x86_64_table[dp->op[1].bytemode][index];
9906       break;
9907
9908     case USE_3BYTE_TABLE:
9909       FETCH_DATA (info, codep + 2);
9910       index = *codep++;
9911       dp = &three_byte_table[dp->op[1].bytemode][index];
9912       modrm.mod = (*codep >> 6) & 3;
9913       modrm.reg = (*codep >> 3) & 7;
9914       modrm.rm = *codep & 7;
9915       break;
9916
9917     case USE_VEX_LEN_TABLE:
9918       if (!need_vex)
9919         abort ();
9920
9921       switch (vex.length)
9922         {
9923         case 128:
9924           index = 0;
9925           break;
9926         case 256:
9927           index = 1;
9928           break;
9929         default:
9930           abort ();
9931           break;
9932         }
9933
9934       dp = &vex_len_table[dp->op[1].bytemode][index];
9935       break;
9936
9937     case USE_XOP_8F_TABLE:
9938       FETCH_DATA (info, codep + 3);
9939       /* All bits in the REX prefix are ignored.  */
9940       rex_ignored = rex;
9941       rex = ~(*codep >> 5) & 0x7;
9942
9943       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9944       switch ((*codep & 0x1f))
9945         {
9946         default:
9947           BadOp ();
9948         case 0x9:
9949           vex_table_index = XOP_09;
9950           break;
9951         case 0xa:
9952           vex_table_index = XOP_0A;
9953           break;
9954         }
9955       codep++;
9956       vex.w = *codep & 0x80;
9957       if (vex.w && address_mode == mode_64bit)
9958         rex |= REX_W;
9959
9960       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9961       if (address_mode != mode_64bit
9962           && vex.register_specifier > 0x7)
9963         BadOp ();
9964
9965       vex.length = (*codep & 0x4) ? 256 : 128;
9966       switch ((*codep & 0x3))
9967         {
9968         case 0:
9969           vex.prefix = 0;
9970           break;
9971         case 1:
9972           vex.prefix = DATA_PREFIX_OPCODE;
9973           break;
9974         case 2:
9975           vex.prefix = REPE_PREFIX_OPCODE;
9976           break;
9977         case 3:
9978           vex.prefix = REPNE_PREFIX_OPCODE;
9979           break;
9980         }
9981       need_vex = 1;
9982       need_vex_reg = 1;
9983       codep++;
9984       index = *codep++;
9985       dp = &xop_table[vex_table_index][index];
9986       /* There is no MODRM byte for VEX [82|77].  */
9987       if (index != 0x77 && index != 0x82)
9988         {
9989           FETCH_DATA (info, codep + 1);
9990           modrm.mod = (*codep >> 6) & 3;
9991           modrm.reg = (*codep >> 3) & 7;
9992           modrm.rm = *codep & 7;
9993         }
9994       break;
9995
9996     case USE_VEX_C4_TABLE:
9997       FETCH_DATA (info, codep + 3);
9998       /* All bits in the REX prefix are ignored.  */
9999       rex_ignored = rex;
10000       rex = ~(*codep >> 5) & 0x7;
10001       switch ((*codep & 0x1f))
10002         {
10003         default:
10004           BadOp ();
10005         case 0x1:
10006           vex_table_index = VEX_0F;
10007           break;
10008         case 0x2:
10009           vex_table_index = VEX_0F38;
10010           break;
10011         case 0x3:
10012           vex_table_index = VEX_0F3A;
10013           break;
10014         }
10015       codep++;
10016       vex.w = *codep & 0x80;
10017       if (vex.w && address_mode == mode_64bit)
10018         rex |= REX_W;
10019
10020       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10021       if (address_mode != mode_64bit
10022           && vex.register_specifier > 0x7)
10023         BadOp ();
10024
10025       vex.length = (*codep & 0x4) ? 256 : 128;
10026       switch ((*codep & 0x3))
10027         {
10028         case 0:
10029           vex.prefix = 0;
10030           break;
10031         case 1:
10032           vex.prefix = DATA_PREFIX_OPCODE;
10033           break;
10034         case 2:
10035           vex.prefix = REPE_PREFIX_OPCODE;
10036           break;
10037         case 3:
10038           vex.prefix = REPNE_PREFIX_OPCODE;
10039           break;
10040         }
10041       need_vex = 1;
10042       need_vex_reg = 1;
10043       codep++;
10044       index = *codep++;
10045       dp = &vex_table[vex_table_index][index];
10046       /* There is no MODRM byte for VEX [82|77].  */
10047       if (index != 0x77 && index != 0x82)
10048         {
10049           FETCH_DATA (info, codep + 1);
10050           modrm.mod = (*codep >> 6) & 3;
10051           modrm.reg = (*codep >> 3) & 7;
10052           modrm.rm = *codep & 7;
10053         }
10054       break;
10055
10056     case USE_VEX_C5_TABLE:
10057       FETCH_DATA (info, codep + 2);
10058       /* All bits in the REX prefix are ignored.  */
10059       rex_ignored = rex;
10060       rex = (*codep & 0x80) ? 0 : REX_R;
10061
10062       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10063       if (address_mode != mode_64bit
10064           && vex.register_specifier > 0x7)
10065         BadOp ();
10066
10067       vex.length = (*codep & 0x4) ? 256 : 128;
10068       switch ((*codep & 0x3))
10069         {
10070         case 0:
10071           vex.prefix = 0;
10072           break;
10073         case 1:
10074           vex.prefix = DATA_PREFIX_OPCODE;
10075           break;
10076         case 2:
10077           vex.prefix = REPE_PREFIX_OPCODE;
10078           break;
10079         case 3:
10080           vex.prefix = REPNE_PREFIX_OPCODE;
10081           break;
10082         }
10083       need_vex = 1;
10084       need_vex_reg = 1;
10085       codep++;
10086       index = *codep++;
10087       dp = &vex_table[dp->op[1].bytemode][index];
10088       /* There is no MODRM byte for VEX [82|77].  */
10089       if (index != 0x77 && index != 0x82)
10090         {
10091           FETCH_DATA (info, codep + 1);
10092           modrm.mod = (*codep >> 6) & 3;
10093           modrm.reg = (*codep >> 3) & 7;
10094           modrm.rm = *codep & 7;
10095         }
10096       break;
10097
10098     default:
10099       abort ();
10100     }
10101
10102   if (dp->name != NULL)
10103     return dp;
10104   else
10105     return get_valid_dis386 (dp, info);
10106 }
10107
10108 static int
10109 print_insn (bfd_vma pc, disassemble_info *info)
10110 {
10111   const struct dis386 *dp;
10112   int i;
10113   char *op_txt[MAX_OPERANDS];
10114   int needcomma;
10115   int sizeflag;
10116   const char *p;
10117   struct dis_private priv;
10118   unsigned char op;
10119   char prefix_obuf[32];
10120   char *prefix_obufp;
10121
10122   if (info->mach == bfd_mach_x86_64_intel_syntax
10123       || info->mach == bfd_mach_x86_64
10124       || info->mach == bfd_mach_l1om
10125       || info->mach == bfd_mach_l1om_intel_syntax)
10126     address_mode = mode_64bit;
10127   else
10128     address_mode = mode_32bit;
10129
10130   if (intel_syntax == (char) -1)
10131     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10132                     || info->mach == bfd_mach_x86_64_intel_syntax
10133                     || info->mach == bfd_mach_l1om_intel_syntax);
10134
10135   if (info->mach == bfd_mach_i386_i386
10136       || info->mach == bfd_mach_x86_64
10137       || info->mach == bfd_mach_l1om
10138       || info->mach == bfd_mach_i386_i386_intel_syntax
10139       || info->mach == bfd_mach_x86_64_intel_syntax
10140       || info->mach == bfd_mach_l1om_intel_syntax)
10141     priv.orig_sizeflag = AFLAG | DFLAG;
10142   else if (info->mach == bfd_mach_i386_i8086)
10143     priv.orig_sizeflag = 0;
10144   else
10145     abort ();
10146
10147   for (p = info->disassembler_options; p != NULL; )
10148     {
10149       if (CONST_STRNEQ (p, "x86-64"))
10150         {
10151           address_mode = mode_64bit;
10152           priv.orig_sizeflag = AFLAG | DFLAG;
10153         }
10154       else if (CONST_STRNEQ (p, "i386"))
10155         {
10156           address_mode = mode_32bit;
10157           priv.orig_sizeflag = AFLAG | DFLAG;
10158         }
10159       else if (CONST_STRNEQ (p, "i8086"))
10160         {
10161           address_mode = mode_16bit;
10162           priv.orig_sizeflag = 0;
10163         }
10164       else if (CONST_STRNEQ (p, "intel"))
10165         {
10166           intel_syntax = 1;
10167           if (CONST_STRNEQ (p + 5, "-mnemonic"))
10168             intel_mnemonic = 1;
10169         }
10170       else if (CONST_STRNEQ (p, "att"))
10171         {
10172           intel_syntax = 0;
10173           if (CONST_STRNEQ (p + 3, "-mnemonic"))
10174             intel_mnemonic = 0;
10175         }
10176       else if (CONST_STRNEQ (p, "addr"))
10177         {
10178           if (address_mode == mode_64bit)
10179             {
10180               if (p[4] == '3' && p[5] == '2')
10181                 priv.orig_sizeflag &= ~AFLAG;
10182               else if (p[4] == '6' && p[5] == '4')
10183                 priv.orig_sizeflag |= AFLAG;
10184             }
10185           else
10186             {
10187               if (p[4] == '1' && p[5] == '6')
10188                 priv.orig_sizeflag &= ~AFLAG;
10189               else if (p[4] == '3' && p[5] == '2')
10190                 priv.orig_sizeflag |= AFLAG;
10191             }
10192         }
10193       else if (CONST_STRNEQ (p, "data"))
10194         {
10195           if (p[4] == '1' && p[5] == '6')
10196             priv.orig_sizeflag &= ~DFLAG;
10197           else if (p[4] == '3' && p[5] == '2')
10198             priv.orig_sizeflag |= DFLAG;
10199         }
10200       else if (CONST_STRNEQ (p, "suffix"))
10201         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10202
10203       p = strchr (p, ',');
10204       if (p != NULL)
10205         p++;
10206     }
10207
10208   if (intel_syntax)
10209     {
10210       names64 = intel_names64;
10211       names32 = intel_names32;
10212       names16 = intel_names16;
10213       names8 = intel_names8;
10214       names8rex = intel_names8rex;
10215       names_seg = intel_names_seg;
10216       index64 = intel_index64;
10217       index32 = intel_index32;
10218       index16 = intel_index16;
10219       open_char = '[';
10220       close_char = ']';
10221       separator_char = '+';
10222       scale_char = '*';
10223     }
10224   else
10225     {
10226       names64 = att_names64;
10227       names32 = att_names32;
10228       names16 = att_names16;
10229       names8 = att_names8;
10230       names8rex = att_names8rex;
10231       names_seg = att_names_seg;
10232       index64 = att_index64;
10233       index32 = att_index32;
10234       index16 = att_index16;
10235       open_char = '(';
10236       close_char =  ')';
10237       separator_char = ',';
10238       scale_char = ',';
10239     }
10240
10241   /* The output looks better if we put 7 bytes on a line, since that
10242      puts most long word instructions on a single line.  Use 8 bytes
10243      for Intel L1OM.  */
10244   if (info->mach == bfd_mach_l1om
10245       || info->mach == bfd_mach_l1om_intel_syntax)
10246     info->bytes_per_line = 8;
10247   else
10248     info->bytes_per_line = 7;
10249
10250   info->private_data = &priv;
10251   priv.max_fetched = priv.the_buffer;
10252   priv.insn_start = pc;
10253
10254   obuf[0] = 0;
10255   for (i = 0; i < MAX_OPERANDS; ++i)
10256     {
10257       op_out[i][0] = 0;
10258       op_index[i] = -1;
10259     }
10260
10261   the_info = info;
10262   start_pc = pc;
10263   start_codep = priv.the_buffer;
10264   codep = priv.the_buffer;
10265
10266   if (setjmp (priv.bailout) != 0)
10267     {
10268       const char *name;
10269
10270       /* Getting here means we tried for data but didn't get it.  That
10271          means we have an incomplete instruction of some sort.  Just
10272          print the first byte as a prefix or a .byte pseudo-op.  */
10273       if (codep > priv.the_buffer)
10274         {
10275           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10276           if (name != NULL)
10277             (*info->fprintf_func) (info->stream, "%s", name);
10278           else
10279             {
10280               /* Just print the first byte as a .byte instruction.  */
10281               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10282                                      (unsigned int) priv.the_buffer[0]);
10283             }
10284
10285           return 1;
10286         }
10287
10288       return -1;
10289     }
10290
10291   obufp = obuf;
10292   ckprefix ();
10293
10294   insn_codep = codep;
10295   sizeflag = priv.orig_sizeflag;
10296
10297   FETCH_DATA (info, codep + 1);
10298   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10299
10300   if (((prefixes & PREFIX_FWAIT)
10301        && ((*codep < 0xd8) || (*codep > 0xdf)))
10302       || (rex && rex_used))
10303     {
10304       const char *name;
10305
10306       /* fwait not followed by floating point instruction, or rex followed
10307          by other prefixes.  Print the first prefix.  */
10308       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10309       if (name == NULL)
10310         name = INTERNAL_DISASSEMBLER_ERROR;
10311       (*info->fprintf_func) (info->stream, "%s", name);
10312       return 1;
10313     }
10314
10315   op = 0;
10316
10317   if (*codep == 0x0f)
10318     {
10319       unsigned char threebyte;
10320       FETCH_DATA (info, codep + 2);
10321       threebyte = *++codep;
10322       dp = &dis386_twobyte[threebyte];
10323       need_modrm = twobyte_has_modrm[*codep];
10324       codep++;
10325     }
10326   else
10327     {
10328       dp = &dis386[*codep];
10329       need_modrm = onebyte_has_modrm[*codep];
10330       codep++;
10331     }
10332
10333   if ((prefixes & PREFIX_REPZ))
10334     {
10335       repz_prefix = "repz ";
10336       used_prefixes |= PREFIX_REPZ;
10337     }
10338   else
10339     repz_prefix = NULL;
10340
10341   if ((prefixes & PREFIX_REPNZ))
10342     {
10343       repnz_prefix = "repnz ";
10344       used_prefixes |= PREFIX_REPNZ;
10345     }
10346   else
10347     repnz_prefix = NULL;
10348
10349   if ((prefixes & PREFIX_LOCK))
10350     {
10351       lock_prefix = "lock ";
10352       used_prefixes |= PREFIX_LOCK;
10353     }
10354   else
10355     lock_prefix = NULL;
10356
10357   addr_prefix = NULL;
10358   if (prefixes & PREFIX_ADDR)
10359     {
10360       sizeflag ^= AFLAG;
10361       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10362         {
10363           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10364             addr_prefix = "addr32 ";
10365           else
10366             addr_prefix = "addr16 ";
10367           used_prefixes |= PREFIX_ADDR;
10368         }
10369     }
10370
10371   data_prefix = NULL;
10372   if ((prefixes & PREFIX_DATA))
10373     {
10374       sizeflag ^= DFLAG;
10375       if (dp->op[2].bytemode == cond_jump_mode
10376           && dp->op[0].bytemode == v_mode
10377           && !intel_syntax)
10378         {
10379           if (sizeflag & DFLAG)
10380             data_prefix = "data32 ";
10381           else
10382             data_prefix = "data16 ";
10383           used_prefixes |= PREFIX_DATA;
10384         }
10385     }
10386
10387   if (need_modrm)
10388     {
10389       FETCH_DATA (info, codep + 1);
10390       modrm.mod = (*codep >> 6) & 3;
10391       modrm.reg = (*codep >> 3) & 7;
10392       modrm.rm = *codep & 7;
10393     }
10394
10395    need_vex = 0;
10396    need_vex_reg = 0;
10397    vex_w_done = 0;
10398
10399   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10400     {
10401       dofloat (sizeflag);
10402     }
10403   else
10404     {
10405       dp = get_valid_dis386 (dp, info);
10406       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10407         {
10408           for (i = 0; i < MAX_OPERANDS; ++i)
10409             {
10410               obufp = op_out[i];
10411               op_ad = MAX_OPERANDS - 1 - i;
10412               if (dp->op[i].rtn)
10413                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10414             }
10415         }
10416     }
10417
10418   /* See if any prefixes were not used.  If so, print the first one
10419      separately.  If we don't do this, we'll wind up printing an
10420      instruction stream which does not precisely correspond to the
10421      bytes we are disassembling.  */
10422   if ((prefixes & ~used_prefixes) != 0)
10423     {
10424       const char *name;
10425
10426       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10427       if (name == NULL)
10428         name = INTERNAL_DISASSEMBLER_ERROR;
10429       (*info->fprintf_func) (info->stream, "%s", name);
10430       return 1;
10431     }
10432   if ((rex_original & ~rex_used) || rex_ignored)
10433     {
10434       const char *name;
10435       name = prefix_name (rex_original, priv.orig_sizeflag);
10436       if (name == NULL)
10437         name = INTERNAL_DISASSEMBLER_ERROR;
10438       (*info->fprintf_func) (info->stream, "%s ", name);
10439     }
10440
10441   prefix_obuf[0] = 0;
10442   prefix_obufp = prefix_obuf;
10443   if (lock_prefix)
10444     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10445   if (repz_prefix)
10446     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10447   if (repnz_prefix)
10448     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10449   if (addr_prefix)
10450     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10451   if (data_prefix)
10452     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10453
10454   if (prefix_obuf[0] != 0)
10455     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10456
10457   obufp = mnemonicendp;
10458   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10459     oappend (" ");
10460   oappend (" ");
10461   (*info->fprintf_func) (info->stream, "%s", obuf);
10462
10463   /* The enter and bound instructions are printed with operands in the same
10464      order as the intel book; everything else is printed in reverse order.  */
10465   if (intel_syntax || two_source_ops)
10466     {
10467       bfd_vma riprel;
10468
10469       for (i = 0; i < MAX_OPERANDS; ++i)
10470         op_txt[i] = op_out[i];
10471
10472       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10473         {
10474           op_ad = op_index[i];
10475           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10476           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10477           riprel = op_riprel[i];
10478           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10479           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10480         }
10481     }
10482   else
10483     {
10484       for (i = 0; i < MAX_OPERANDS; ++i)
10485         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10486     }
10487
10488   needcomma = 0;
10489   for (i = 0; i < MAX_OPERANDS; ++i)
10490     if (*op_txt[i])
10491       {
10492         if (needcomma)
10493           (*info->fprintf_func) (info->stream, ",");
10494         if (op_index[i] != -1 && !op_riprel[i])
10495           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10496         else
10497           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10498         needcomma = 1;
10499       }
10500
10501   for (i = 0; i < MAX_OPERANDS; i++)
10502     if (op_index[i] != -1 && op_riprel[i])
10503       {
10504         (*info->fprintf_func) (info->stream, "        # ");
10505         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10506                                                 + op_address[op_index[i]]), info);
10507         break;
10508       }
10509   return codep - priv.the_buffer;
10510 }
10511
10512 static const char *float_mem[] = {
10513   /* d8 */
10514   "fadd{s|}",
10515   "fmul{s|}",
10516   "fcom{s|}",
10517   "fcomp{s|}",
10518   "fsub{s|}",
10519   "fsubr{s|}",
10520   "fdiv{s|}",
10521   "fdivr{s|}",
10522   /* d9 */
10523   "fld{s|}",
10524   "(bad)",
10525   "fst{s|}",
10526   "fstp{s|}",
10527   "fldenvIC",
10528   "fldcw",
10529   "fNstenvIC",
10530   "fNstcw",
10531   /* da */
10532   "fiadd{l|}",
10533   "fimul{l|}",
10534   "ficom{l|}",
10535   "ficomp{l|}",
10536   "fisub{l|}",
10537   "fisubr{l|}",
10538   "fidiv{l|}",
10539   "fidivr{l|}",
10540   /* db */
10541   "fild{l|}",
10542   "fisttp{l|}",
10543   "fist{l|}",
10544   "fistp{l|}",
10545   "(bad)",
10546   "fld{t||t|}",
10547   "(bad)",
10548   "fstp{t||t|}",
10549   /* dc */
10550   "fadd{l|}",
10551   "fmul{l|}",
10552   "fcom{l|}",
10553   "fcomp{l|}",
10554   "fsub{l|}",
10555   "fsubr{l|}",
10556   "fdiv{l|}",
10557   "fdivr{l|}",
10558   /* dd */
10559   "fld{l|}",
10560   "fisttp{ll|}",
10561   "fst{l||}",
10562   "fstp{l|}",
10563   "frstorIC",
10564   "(bad)",
10565   "fNsaveIC",
10566   "fNstsw",
10567   /* de */
10568   "fiadd",
10569   "fimul",
10570   "ficom",
10571   "ficomp",
10572   "fisub",
10573   "fisubr",
10574   "fidiv",
10575   "fidivr",
10576   /* df */
10577   "fild",
10578   "fisttp",
10579   "fist",
10580   "fistp",
10581   "fbld",
10582   "fild{ll|}",
10583   "fbstp",
10584   "fistp{ll|}",
10585 };
10586
10587 static const unsigned char float_mem_mode[] = {
10588   /* d8 */
10589   d_mode,
10590   d_mode,
10591   d_mode,
10592   d_mode,
10593   d_mode,
10594   d_mode,
10595   d_mode,
10596   d_mode,
10597   /* d9 */
10598   d_mode,
10599   0,
10600   d_mode,
10601   d_mode,
10602   0,
10603   w_mode,
10604   0,
10605   w_mode,
10606   /* da */
10607   d_mode,
10608   d_mode,
10609   d_mode,
10610   d_mode,
10611   d_mode,
10612   d_mode,
10613   d_mode,
10614   d_mode,
10615   /* db */
10616   d_mode,
10617   d_mode,
10618   d_mode,
10619   d_mode,
10620   0,
10621   t_mode,
10622   0,
10623   t_mode,
10624   /* dc */
10625   q_mode,
10626   q_mode,
10627   q_mode,
10628   q_mode,
10629   q_mode,
10630   q_mode,
10631   q_mode,
10632   q_mode,
10633   /* dd */
10634   q_mode,
10635   q_mode,
10636   q_mode,
10637   q_mode,
10638   0,
10639   0,
10640   0,
10641   w_mode,
10642   /* de */
10643   w_mode,
10644   w_mode,
10645   w_mode,
10646   w_mode,
10647   w_mode,
10648   w_mode,
10649   w_mode,
10650   w_mode,
10651   /* df */
10652   w_mode,
10653   w_mode,
10654   w_mode,
10655   w_mode,
10656   t_mode,
10657   q_mode,
10658   t_mode,
10659   q_mode
10660 };
10661
10662 #define ST { OP_ST, 0 }
10663 #define STi { OP_STi, 0 }
10664
10665 #define FGRPd9_2 NULL, { { NULL, 0 } }
10666 #define FGRPd9_4 NULL, { { NULL, 1 } }
10667 #define FGRPd9_5 NULL, { { NULL, 2 } }
10668 #define FGRPd9_6 NULL, { { NULL, 3 } }
10669 #define FGRPd9_7 NULL, { { NULL, 4 } }
10670 #define FGRPda_5 NULL, { { NULL, 5 } }
10671 #define FGRPdb_4 NULL, { { NULL, 6 } }
10672 #define FGRPde_3 NULL, { { NULL, 7 } }
10673 #define FGRPdf_4 NULL, { { NULL, 8 } }
10674
10675 static const struct dis386 float_reg[][8] = {
10676   /* d8 */
10677   {
10678     { "fadd",   { ST, STi } },
10679     { "fmul",   { ST, STi } },
10680     { "fcom",   { STi } },
10681     { "fcomp",  { STi } },
10682     { "fsub",   { ST, STi } },
10683     { "fsubr",  { ST, STi } },
10684     { "fdiv",   { ST, STi } },
10685     { "fdivr",  { ST, STi } },
10686   },
10687   /* d9 */
10688   {
10689     { "fld",    { STi } },
10690     { "fxch",   { STi } },
10691     { FGRPd9_2 },
10692     { "(bad)",  { XX } },
10693     { FGRPd9_4 },
10694     { FGRPd9_5 },
10695     { FGRPd9_6 },
10696     { FGRPd9_7 },
10697   },
10698   /* da */
10699   {
10700     { "fcmovb", { ST, STi } },
10701     { "fcmove", { ST, STi } },
10702     { "fcmovbe",{ ST, STi } },
10703     { "fcmovu", { ST, STi } },
10704     { "(bad)",  { XX } },
10705     { FGRPda_5 },
10706     { "(bad)",  { XX } },
10707     { "(bad)",  { XX } },
10708   },
10709   /* db */
10710   {
10711     { "fcmovnb",{ ST, STi } },
10712     { "fcmovne",{ ST, STi } },
10713     { "fcmovnbe",{ ST, STi } },
10714     { "fcmovnu",{ ST, STi } },
10715     { FGRPdb_4 },
10716     { "fucomi", { ST, STi } },
10717     { "fcomi",  { ST, STi } },
10718     { "(bad)",  { XX } },
10719   },
10720   /* dc */
10721   {
10722     { "fadd",   { STi, ST } },
10723     { "fmul",   { STi, ST } },
10724     { "(bad)",  { XX } },
10725     { "(bad)",  { XX } },
10726     { "fsub!M", { STi, ST } },
10727     { "fsubM",  { STi, ST } },
10728     { "fdiv!M", { STi, ST } },
10729     { "fdivM",  { STi, ST } },
10730   },
10731   /* dd */
10732   {
10733     { "ffree",  { STi } },
10734     { "(bad)",  { XX } },
10735     { "fst",    { STi } },
10736     { "fstp",   { STi } },
10737     { "fucom",  { STi } },
10738     { "fucomp", { STi } },
10739     { "(bad)",  { XX } },
10740     { "(bad)",  { XX } },
10741   },
10742   /* de */
10743   {
10744     { "faddp",  { STi, ST } },
10745     { "fmulp",  { STi, ST } },
10746     { "(bad)",  { XX } },
10747     { FGRPde_3 },
10748     { "fsub!Mp", { STi, ST } },
10749     { "fsubMp", { STi, ST } },
10750     { "fdiv!Mp", { STi, ST } },
10751     { "fdivMp", { STi, ST } },
10752   },
10753   /* df */
10754   {
10755     { "ffreep", { STi } },
10756     { "(bad)",  { XX } },
10757     { "(bad)",  { XX } },
10758     { "(bad)",  { XX } },
10759     { FGRPdf_4 },
10760     { "fucomip", { ST, STi } },
10761     { "fcomip", { ST, STi } },
10762     { "(bad)",  { XX } },
10763   },
10764 };
10765
10766 static char *fgrps[][8] = {
10767   /* d9_2  0 */
10768   {
10769     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10770   },
10771
10772   /* d9_4  1 */
10773   {
10774     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10775   },
10776
10777   /* d9_5  2 */
10778   {
10779     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10780   },
10781
10782   /* d9_6  3 */
10783   {
10784     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10785   },
10786
10787   /* d9_7  4 */
10788   {
10789     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10790   },
10791
10792   /* da_5  5 */
10793   {
10794     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10795   },
10796
10797   /* db_4  6 */
10798   {
10799     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10800     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10801   },
10802
10803   /* de_3  7 */
10804   {
10805     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10806   },
10807
10808   /* df_4  8 */
10809   {
10810     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10811   },
10812 };
10813
10814 static void
10815 swap_operand (void)
10816 {
10817   mnemonicendp[0] = '.';
10818   mnemonicendp[1] = 's';
10819   mnemonicendp += 2;
10820 }
10821
10822 static void
10823 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10824                int sizeflag ATTRIBUTE_UNUSED)
10825 {
10826   /* Skip mod/rm byte.  */
10827   MODRM_CHECK;
10828   codep++;
10829 }
10830
10831 static void
10832 dofloat (int sizeflag)
10833 {
10834   const struct dis386 *dp;
10835   unsigned char floatop;
10836
10837   floatop = codep[-1];
10838
10839   if (modrm.mod != 3)
10840     {
10841       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10842
10843       putop (float_mem[fp_indx], sizeflag);
10844       obufp = op_out[0];
10845       op_ad = 2;
10846       OP_E (float_mem_mode[fp_indx], sizeflag);
10847       return;
10848     }
10849   /* Skip mod/rm byte.  */
10850   MODRM_CHECK;
10851   codep++;
10852
10853   dp = &float_reg[floatop - 0xd8][modrm.reg];
10854   if (dp->name == NULL)
10855     {
10856       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10857
10858       /* Instruction fnstsw is only one with strange arg.  */
10859       if (floatop == 0xdf && codep[-1] == 0xe0)
10860         strcpy (op_out[0], names16[0]);
10861     }
10862   else
10863     {
10864       putop (dp->name, sizeflag);
10865
10866       obufp = op_out[0];
10867       op_ad = 2;
10868       if (dp->op[0].rtn)
10869         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10870
10871       obufp = op_out[1];
10872       op_ad = 1;
10873       if (dp->op[1].rtn)
10874         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10875     }
10876 }
10877
10878 static void
10879 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10880 {
10881   oappend ("%st" + intel_syntax);
10882 }
10883
10884 static void
10885 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10886 {
10887   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10888   oappend (scratchbuf + intel_syntax);
10889 }
10890
10891 /* Capital letters in template are macros.  */
10892 static int
10893 putop (const char *in_template, int sizeflag)
10894 {
10895   const char *p;
10896   int alt = 0;
10897   int cond = 1;
10898   unsigned int l = 0, len = 1;
10899   char last[4];
10900
10901 #define SAVE_LAST(c)                    \
10902   if (l < len && l < sizeof (last))     \
10903     last[l++] = c;                      \
10904   else                                  \
10905     abort ();
10906
10907   for (p = in_template; *p; p++)
10908     {
10909       switch (*p)
10910         {
10911         default:
10912           *obufp++ = *p;
10913           break;
10914         case '%':
10915           len++;
10916           break;
10917         case '!':
10918           cond = 0;
10919           break;
10920         case '{':
10921           alt = 0;
10922           if (intel_syntax)
10923             {
10924               while (*++p != '|')
10925                 if (*p == '}' || *p == '\0')
10926                   abort ();
10927             }
10928           /* Fall through.  */
10929         case 'I':
10930           alt = 1;
10931           continue;
10932         case '|':
10933           while (*++p != '}')
10934             {
10935               if (*p == '\0')
10936                 abort ();
10937             }
10938           break;
10939         case '}':
10940           break;
10941         case 'A':
10942           if (intel_syntax)
10943             break;
10944           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10945             *obufp++ = 'b';
10946           break;
10947         case 'B':
10948           if (l == 0 && len == 1)
10949             {
10950 case_B:
10951               if (intel_syntax)
10952                 break;
10953               if (sizeflag & SUFFIX_ALWAYS)
10954                 *obufp++ = 'b';
10955             }
10956           else
10957             {
10958               if (l != 1
10959                   || len != 2
10960                   || last[0] != 'L')
10961                 {
10962                   SAVE_LAST (*p);
10963                   break;
10964                 }
10965
10966               if (address_mode == mode_64bit
10967                   && !(prefixes & PREFIX_ADDR))
10968                 {
10969                   *obufp++ = 'a';
10970                   *obufp++ = 'b';
10971                   *obufp++ = 's';
10972                 }
10973
10974               goto case_B;
10975             }
10976           break;
10977         case 'C':
10978           if (intel_syntax && !alt)
10979             break;
10980           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10981             {
10982               if (sizeflag & DFLAG)
10983                 *obufp++ = intel_syntax ? 'd' : 'l';
10984               else
10985                 *obufp++ = intel_syntax ? 'w' : 's';
10986               used_prefixes |= (prefixes & PREFIX_DATA);
10987             }
10988           break;
10989         case 'D':
10990           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10991             break;
10992           USED_REX (REX_W);
10993           if (modrm.mod == 3)
10994             {
10995               if (rex & REX_W)
10996                 *obufp++ = 'q';
10997               else if (sizeflag & DFLAG)
10998                 *obufp++ = intel_syntax ? 'd' : 'l';
10999               else
11000                 *obufp++ = 'w';
11001               used_prefixes |= (prefixes & PREFIX_DATA);
11002             }
11003           else
11004             *obufp++ = 'w';
11005           break;
11006         case 'E':               /* For jcxz/jecxz */
11007           if (address_mode == mode_64bit)
11008             {
11009               if (sizeflag & AFLAG)
11010                 *obufp++ = 'r';
11011               else
11012                 *obufp++ = 'e';
11013             }
11014           else
11015             if (sizeflag & AFLAG)
11016               *obufp++ = 'e';
11017           used_prefixes |= (prefixes & PREFIX_ADDR);
11018           break;
11019         case 'F':
11020           if (intel_syntax)
11021             break;
11022           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
11023             {
11024               if (sizeflag & AFLAG)
11025                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
11026               else
11027                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
11028               used_prefixes |= (prefixes & PREFIX_ADDR);
11029             }
11030           break;
11031         case 'G':
11032           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
11033             break;
11034           if ((rex & REX_W) || (sizeflag & DFLAG))
11035             *obufp++ = 'l';
11036           else
11037             *obufp++ = 'w';
11038           if (!(rex & REX_W))
11039             used_prefixes |= (prefixes & PREFIX_DATA);
11040           break;
11041         case 'H':
11042           if (intel_syntax)
11043             break;
11044           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
11045               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
11046             {
11047               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
11048               *obufp++ = ',';
11049               *obufp++ = 'p';
11050               if (prefixes & PREFIX_DS)
11051                 *obufp++ = 't';
11052               else
11053                 *obufp++ = 'n';
11054             }
11055           break;
11056         case 'J':
11057           if (intel_syntax)
11058             break;
11059           *obufp++ = 'l';
11060           break;
11061         case 'K':
11062           USED_REX (REX_W);
11063           if (rex & REX_W)
11064             *obufp++ = 'q';
11065           else
11066             *obufp++ = 'd';
11067           break;
11068         case 'Z':
11069           if (intel_syntax)
11070             break;
11071           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
11072             {
11073               *obufp++ = 'q';
11074               break;
11075             }
11076           /* Fall through.  */
11077           goto case_L;
11078         case 'L':
11079           if (l != 0 || len != 1)
11080             {
11081               SAVE_LAST (*p);
11082               break;
11083             }
11084 case_L:
11085           if (intel_syntax)
11086             break;
11087           if (sizeflag & SUFFIX_ALWAYS)
11088             *obufp++ = 'l';
11089           break;
11090         case 'M':
11091           if (intel_mnemonic != cond)
11092             *obufp++ = 'r';
11093           break;
11094         case 'N':
11095           if ((prefixes & PREFIX_FWAIT) == 0)
11096             *obufp++ = 'n';
11097           else
11098             used_prefixes |= PREFIX_FWAIT;
11099           break;
11100         case 'O':
11101           USED_REX (REX_W);
11102           if (rex & REX_W)
11103             *obufp++ = 'o';
11104           else if (intel_syntax && (sizeflag & DFLAG))
11105             *obufp++ = 'q';
11106           else
11107             *obufp++ = 'd';
11108           if (!(rex & REX_W))
11109             used_prefixes |= (prefixes & PREFIX_DATA);
11110           break;
11111         case 'T':
11112           if (intel_syntax)
11113             break;
11114           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11115             {
11116               *obufp++ = 'q';
11117               break;
11118             }
11119           /* Fall through.  */
11120         case 'P':
11121           if (intel_syntax)
11122             break;
11123           if ((prefixes & PREFIX_DATA)
11124               || (rex & REX_W)
11125               || (sizeflag & SUFFIX_ALWAYS))
11126             {
11127               USED_REX (REX_W);
11128               if (rex & REX_W)
11129                 *obufp++ = 'q';
11130               else
11131                 {
11132                    if (sizeflag & DFLAG)
11133                       *obufp++ = 'l';
11134                    else
11135                      *obufp++ = 'w';
11136                 }
11137               used_prefixes |= (prefixes & PREFIX_DATA);
11138             }
11139           break;
11140         case 'U':
11141           if (intel_syntax)
11142             break;
11143           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11144             {
11145               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11146                 *obufp++ = 'q';
11147               break;
11148             }
11149           /* Fall through.  */
11150           goto case_Q;
11151         case 'Q':
11152           if (l == 0 && len == 1)
11153             {
11154 case_Q:
11155               if (intel_syntax && !alt)
11156                 break;
11157               USED_REX (REX_W);
11158               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11159                 {
11160                   if (rex & REX_W)
11161                     *obufp++ = 'q';
11162                   else
11163                     {
11164                       if (sizeflag & DFLAG)
11165                         *obufp++ = intel_syntax ? 'd' : 'l';
11166                       else
11167                         *obufp++ = 'w';
11168                     }
11169                   used_prefixes |= (prefixes & PREFIX_DATA);
11170                 }
11171             }
11172           else
11173             {
11174               if (l != 1 || len != 2 || last[0] != 'L')
11175                 {
11176                   SAVE_LAST (*p);
11177                   break;
11178                 }
11179               if (intel_syntax
11180                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11181                 break;
11182               if ((rex & REX_W))
11183                 {
11184                   USED_REX (REX_W);
11185                   *obufp++ = 'q';
11186                 }
11187               else
11188                 *obufp++ = 'l';
11189             }
11190           break;
11191         case 'R':
11192           USED_REX (REX_W);
11193           if (rex & REX_W)
11194             *obufp++ = 'q';
11195           else if (sizeflag & DFLAG)
11196             {
11197               if (intel_syntax)
11198                   *obufp++ = 'd';
11199               else
11200                   *obufp++ = 'l';
11201             }
11202           else
11203             *obufp++ = 'w';
11204           if (intel_syntax && !p[1]
11205               && ((rex & REX_W) || (sizeflag & DFLAG)))
11206             *obufp++ = 'e';
11207           if (!(rex & REX_W))
11208             used_prefixes |= (prefixes & PREFIX_DATA);
11209           break;
11210         case 'V':
11211           if (l == 0 && len == 1)
11212             {
11213               if (intel_syntax)
11214                 break;
11215               if (address_mode == mode_64bit && (sizeflag & DFLAG))
11216                 {
11217                   if (sizeflag & SUFFIX_ALWAYS)
11218                     *obufp++ = 'q';
11219                   break;
11220                 }
11221             }
11222           else
11223             {
11224               if (l != 1
11225                   || len != 2
11226                   || last[0] != 'L')
11227                 {
11228                   SAVE_LAST (*p);
11229                   break;
11230                 }
11231
11232               if (rex & REX_W)
11233                 {
11234                   *obufp++ = 'a';
11235                   *obufp++ = 'b';
11236                   *obufp++ = 's';
11237                 }
11238             }
11239           /* Fall through.  */
11240           goto case_S;
11241         case 'S':
11242           if (l == 0 && len == 1)
11243             {
11244 case_S:
11245               if (intel_syntax)
11246                 break;
11247               if (sizeflag & SUFFIX_ALWAYS)
11248                 {
11249                   if (rex & REX_W)
11250                     *obufp++ = 'q';
11251                   else
11252                     {
11253                       if (sizeflag & DFLAG)
11254                         *obufp++ = 'l';
11255                       else
11256                         *obufp++ = 'w';
11257                       used_prefixes |= (prefixes & PREFIX_DATA);
11258                     }
11259                 }
11260             }
11261           else
11262             {
11263               if (l != 1
11264                   || len != 2
11265                   || last[0] != 'L')
11266                 {
11267                   SAVE_LAST (*p);
11268                   break;
11269                 }
11270
11271               if (address_mode == mode_64bit
11272                   && !(prefixes & PREFIX_ADDR))
11273                 {
11274                   *obufp++ = 'a';
11275                   *obufp++ = 'b';
11276                   *obufp++ = 's';
11277                 }
11278
11279               goto case_S;
11280             }
11281           break;
11282         case 'X':
11283           if (l != 0 || len != 1)
11284             {
11285               SAVE_LAST (*p);
11286               break;
11287             }
11288           if (need_vex && vex.prefix)
11289             {
11290               if (vex.prefix == DATA_PREFIX_OPCODE)
11291                 *obufp++ = 'd';
11292               else
11293                 *obufp++ = 's';
11294             }
11295           else if (prefixes & PREFIX_DATA)
11296             *obufp++ = 'd';
11297           else
11298             *obufp++ = 's';
11299           used_prefixes |= (prefixes & PREFIX_DATA);
11300           break;
11301         case 'Y':
11302           if (l == 0 && len == 1)
11303             {
11304               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11305                 break;
11306               if (rex & REX_W)
11307                 {
11308                   USED_REX (REX_W);
11309                   *obufp++ = 'q';
11310                 }
11311               break;
11312             }
11313           else
11314             {
11315               if (l != 1 || len != 2 || last[0] != 'X')
11316                 {
11317                   SAVE_LAST (*p);
11318                   break;
11319                 }
11320               if (!need_vex)
11321                 abort ();
11322               if (intel_syntax
11323                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11324                 break;
11325               switch (vex.length)
11326                 {
11327                 case 128:
11328                   *obufp++ = 'x';
11329                   break;
11330                 case 256:
11331                   *obufp++ = 'y';
11332                   break;
11333                 default:
11334                   abort ();
11335                 }
11336             }
11337           break;
11338         case 'W':
11339           if (l == 0 && len == 1)
11340             {
11341               /* operand size flag for cwtl, cbtw */
11342               USED_REX (REX_W);
11343               if (rex & REX_W)
11344                 {
11345                   if (intel_syntax)
11346                     *obufp++ = 'd';
11347                   else
11348                     *obufp++ = 'l';
11349                 }
11350               else if (sizeflag & DFLAG)
11351                 *obufp++ = 'w';
11352               else
11353                 *obufp++ = 'b';
11354               if (!(rex & REX_W))
11355                 used_prefixes |= (prefixes & PREFIX_DATA);
11356             }
11357           else
11358             {
11359               if (l != 1 || len != 2 || last[0] != 'X')
11360                 {
11361                   SAVE_LAST (*p);
11362                   break;
11363                 }
11364               if (!need_vex)
11365                 abort ();
11366               *obufp++ = vex.w ? 'd': 's';
11367             }
11368           break;
11369         }
11370       alt = 0;
11371     }
11372   *obufp = 0;
11373   mnemonicendp = obufp;
11374   return 0;
11375 }
11376
11377 static void
11378 oappend (const char *s)
11379 {
11380   obufp = stpcpy (obufp, s);
11381 }
11382
11383 static void
11384 append_seg (void)
11385 {
11386   if (prefixes & PREFIX_CS)
11387     {
11388       used_prefixes |= PREFIX_CS;
11389       oappend ("%cs:" + intel_syntax);
11390     }
11391   if (prefixes & PREFIX_DS)
11392     {
11393       used_prefixes |= PREFIX_DS;
11394       oappend ("%ds:" + intel_syntax);
11395     }
11396   if (prefixes & PREFIX_SS)
11397     {
11398       used_prefixes |= PREFIX_SS;
11399       oappend ("%ss:" + intel_syntax);
11400     }
11401   if (prefixes & PREFIX_ES)
11402     {
11403       used_prefixes |= PREFIX_ES;
11404       oappend ("%es:" + intel_syntax);
11405     }
11406   if (prefixes & PREFIX_FS)
11407     {
11408       used_prefixes |= PREFIX_FS;
11409       oappend ("%fs:" + intel_syntax);
11410     }
11411   if (prefixes & PREFIX_GS)
11412     {
11413       used_prefixes |= PREFIX_GS;
11414       oappend ("%gs:" + intel_syntax);
11415     }
11416 }
11417
11418 static void
11419 OP_indirE (int bytemode, int sizeflag)
11420 {
11421   if (!intel_syntax)
11422     oappend ("*");
11423   OP_E (bytemode, sizeflag);
11424 }
11425
11426 static void
11427 print_operand_value (char *buf, int hex, bfd_vma disp)
11428 {
11429   if (address_mode == mode_64bit)
11430     {
11431       if (hex)
11432         {
11433           char tmp[30];
11434           int i;
11435           buf[0] = '0';
11436           buf[1] = 'x';
11437           sprintf_vma (tmp, disp);
11438           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11439           strcpy (buf + 2, tmp + i);
11440         }
11441       else
11442         {
11443           bfd_signed_vma v = disp;
11444           char tmp[30];
11445           int i;
11446           if (v < 0)
11447             {
11448               *(buf++) = '-';
11449               v = -disp;
11450               /* Check for possible overflow on 0x8000000000000000.  */
11451               if (v < 0)
11452                 {
11453                   strcpy (buf, "9223372036854775808");
11454                   return;
11455                 }
11456             }
11457           if (!v)
11458             {
11459               strcpy (buf, "0");
11460               return;
11461             }
11462
11463           i = 0;
11464           tmp[29] = 0;
11465           while (v)
11466             {
11467               tmp[28 - i] = (v % 10) + '0';
11468               v /= 10;
11469               i++;
11470             }
11471           strcpy (buf, tmp + 29 - i);
11472         }
11473     }
11474   else
11475     {
11476       if (hex)
11477         sprintf (buf, "0x%x", (unsigned int) disp);
11478       else
11479         sprintf (buf, "%d", (int) disp);
11480     }
11481 }
11482
11483 /* Put DISP in BUF as signed hex number.  */
11484
11485 static void
11486 print_displacement (char *buf, bfd_vma disp)
11487 {
11488   bfd_signed_vma val = disp;
11489   char tmp[30];
11490   int i, j = 0;
11491
11492   if (val < 0)
11493     {
11494       buf[j++] = '-';
11495       val = -disp;
11496
11497       /* Check for possible overflow.  */
11498       if (val < 0)
11499         {
11500           switch (address_mode)
11501             {
11502             case mode_64bit:
11503               strcpy (buf + j, "0x8000000000000000");
11504               break;
11505             case mode_32bit:
11506               strcpy (buf + j, "0x80000000");
11507               break;
11508             case mode_16bit:
11509               strcpy (buf + j, "0x8000");
11510               break;
11511             }
11512           return;
11513         }
11514     }
11515
11516   buf[j++] = '0';
11517   buf[j++] = 'x';
11518
11519   sprintf_vma (tmp, (bfd_vma) val);
11520   for (i = 0; tmp[i] == '0'; i++)
11521     continue;
11522   if (tmp[i] == '\0')
11523     i--;
11524   strcpy (buf + j, tmp + i);
11525 }
11526
11527 static void
11528 intel_operand_size (int bytemode, int sizeflag)
11529 {
11530   switch (bytemode)
11531     {
11532     case b_mode:
11533     case b_swap_mode:
11534     case dqb_mode:
11535       oappend ("BYTE PTR ");
11536       break;
11537     case w_mode:
11538     case dqw_mode:
11539       oappend ("WORD PTR ");
11540       break;
11541     case stack_v_mode:
11542       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11543         {
11544           oappend ("QWORD PTR ");
11545           used_prefixes |= (prefixes & PREFIX_DATA);
11546           break;
11547         }
11548       /* FALLTHRU */
11549     case v_mode:
11550     case v_swap_mode:
11551     case dq_mode:
11552       USED_REX (REX_W);
11553       if (rex & REX_W)
11554         oappend ("QWORD PTR ");
11555       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11556         oappend ("DWORD PTR ");
11557       else
11558         oappend ("WORD PTR ");
11559       used_prefixes |= (prefixes & PREFIX_DATA);
11560       break;
11561     case z_mode:
11562       if ((rex & REX_W) || (sizeflag & DFLAG))
11563         *obufp++ = 'D';
11564       oappend ("WORD PTR ");
11565       if (!(rex & REX_W))
11566         used_prefixes |= (prefixes & PREFIX_DATA);
11567       break;
11568     case a_mode:
11569       if (sizeflag & DFLAG)
11570         oappend ("QWORD PTR ");
11571       else
11572         oappend ("DWORD PTR ");
11573       used_prefixes |= (prefixes & PREFIX_DATA);
11574       break;
11575     case d_mode:
11576     case d_swap_mode:
11577     case dqd_mode:
11578       oappend ("DWORD PTR ");
11579       break;
11580     case q_mode:
11581     case q_swap_mode:
11582       oappend ("QWORD PTR ");
11583       break;
11584     case m_mode:
11585       if (address_mode == mode_64bit)
11586         oappend ("QWORD PTR ");
11587       else
11588         oappend ("DWORD PTR ");
11589       break;
11590     case f_mode:
11591       if (sizeflag & DFLAG)
11592         oappend ("FWORD PTR ");
11593       else
11594         oappend ("DWORD PTR ");
11595       used_prefixes |= (prefixes & PREFIX_DATA);
11596       break;
11597     case t_mode:
11598       oappend ("TBYTE PTR ");
11599       break;
11600     case x_mode:
11601     case x_swap_mode:
11602       if (need_vex)
11603         {
11604           switch (vex.length)
11605             {
11606             case 128:
11607               oappend ("XMMWORD PTR ");
11608               break;
11609             case 256:
11610               oappend ("YMMWORD PTR ");
11611               break;
11612             default:
11613               abort ();
11614             }
11615         }
11616       else
11617         oappend ("XMMWORD PTR ");
11618       break;
11619     case xmm_mode:
11620       oappend ("XMMWORD PTR ");
11621       break;
11622     case xmmq_mode:
11623       if (!need_vex)
11624         abort ();
11625
11626       switch (vex.length)
11627         {
11628         case 128:
11629           oappend ("QWORD PTR ");
11630           break;
11631         case 256:
11632           oappend ("XMMWORD PTR ");
11633           break;
11634         default:
11635           abort ();
11636         }
11637       break;
11638     case ymmq_mode:
11639       if (!need_vex)
11640         abort ();
11641
11642       switch (vex.length)
11643         {
11644         case 128:
11645           oappend ("QWORD PTR ");
11646           break;
11647         case 256:
11648           oappend ("YMMWORD PTR ");
11649           break;
11650         default:
11651           abort ();
11652         }
11653       break;
11654     case o_mode:
11655       oappend ("OWORD PTR ");
11656       break;
11657     case vex_w_dq_mode:
11658       if (!need_vex)
11659         abort ();
11660
11661       if (vex.w)
11662         oappend ("QWORD PTR ");
11663       else
11664         oappend ("DWORD PTR ");
11665       break;
11666     default:
11667       break;
11668     }
11669 }
11670
11671 static void
11672 OP_E_register (int bytemode, int sizeflag)
11673 {
11674   int reg = modrm.rm;
11675   const char **names;
11676
11677   USED_REX (REX_B);
11678   if ((rex & REX_B))
11679     reg += 8;
11680
11681   if ((sizeflag & SUFFIX_ALWAYS)
11682       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11683     swap_operand ();
11684
11685   switch (bytemode)
11686     {
11687     case b_mode:
11688     case b_swap_mode:
11689       USED_REX (0);
11690       if (rex)
11691         names = names8rex;
11692       else
11693         names = names8;
11694       break;
11695     case w_mode:
11696       names = names16;
11697       break;
11698     case d_mode:
11699       names = names32;
11700       break;
11701     case q_mode:
11702       names = names64;
11703       break;
11704     case m_mode:
11705       names = address_mode == mode_64bit ? names64 : names32;
11706       break;
11707     case stack_v_mode:
11708       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11709         {
11710           names = names64;
11711           used_prefixes |= (prefixes & PREFIX_DATA);
11712           break;
11713         }
11714       bytemode = v_mode;
11715       /* FALLTHRU */
11716     case v_mode:
11717     case v_swap_mode:
11718     case dq_mode:
11719     case dqb_mode:
11720     case dqd_mode:
11721     case dqw_mode:
11722       USED_REX (REX_W);
11723       if (rex & REX_W)
11724         names = names64;
11725       else if ((sizeflag & DFLAG)
11726                || (bytemode != v_mode
11727                    && bytemode != v_swap_mode))
11728         names = names32;
11729       else
11730         names = names16;
11731       used_prefixes |= (prefixes & PREFIX_DATA);
11732       break;
11733     case 0:
11734       return;
11735     default:
11736       oappend (INTERNAL_DISASSEMBLER_ERROR);
11737       return;
11738     }
11739   oappend (names[reg]);
11740 }
11741
11742 static void
11743 OP_E_memory (int bytemode, int sizeflag)
11744 {
11745   bfd_vma disp = 0;
11746   int add = (rex & REX_B) ? 8 : 0;
11747   int riprel = 0;
11748
11749   USED_REX (REX_B);
11750   if (intel_syntax)
11751     intel_operand_size (bytemode, sizeflag);
11752   append_seg ();
11753
11754   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11755     {
11756       /* 32/64 bit address mode */
11757       int havedisp;
11758       int havesib;
11759       int havebase;
11760       int haveindex;
11761       int needindex;
11762       int base, rbase;
11763       int index = 0;
11764       int scale = 0;
11765
11766       havesib = 0;
11767       havebase = 1;
11768       haveindex = 0;
11769       base = modrm.rm;
11770
11771       if (base == 4)
11772         {
11773           havesib = 1;
11774           FETCH_DATA (the_info, codep + 1);
11775           index = (*codep >> 3) & 7;
11776           scale = (*codep >> 6) & 3;
11777           base = *codep & 7;
11778           USED_REX (REX_X);
11779           if (rex & REX_X)
11780             index += 8;
11781           haveindex = index != 4;
11782           codep++;
11783         }
11784       rbase = base + add;
11785
11786       switch (modrm.mod)
11787         {
11788         case 0:
11789           if (base == 5)
11790             {
11791               havebase = 0;
11792               if (address_mode == mode_64bit && !havesib)
11793                 riprel = 1;
11794               disp = get32s ();
11795             }
11796           break;
11797         case 1:
11798           FETCH_DATA (the_info, codep + 1);
11799           disp = *codep++;
11800           if ((disp & 0x80) != 0)
11801             disp -= 0x100;
11802           break;
11803         case 2:
11804           disp = get32s ();
11805           break;
11806         }
11807
11808       /* In 32bit mode, we need index register to tell [offset] from
11809          [eiz*1 + offset].  */
11810       needindex = (havesib
11811                    && !havebase
11812                    && !haveindex
11813                    && address_mode == mode_32bit);
11814       havedisp = (havebase
11815                   || needindex
11816                   || (havesib && (haveindex || scale != 0)));
11817
11818       if (!intel_syntax)
11819         if (modrm.mod != 0 || base == 5)
11820           {
11821             if (havedisp || riprel)
11822               print_displacement (scratchbuf, disp);
11823             else
11824               print_operand_value (scratchbuf, 1, disp);
11825             oappend (scratchbuf);
11826             if (riprel)
11827               {
11828                 set_op (disp, 1);
11829                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11830               }
11831           }
11832
11833       if (havebase || haveindex || riprel)
11834         used_prefixes |= PREFIX_ADDR;
11835
11836       if (havedisp || (intel_syntax && riprel))
11837         {
11838           *obufp++ = open_char;
11839           if (intel_syntax && riprel)
11840             {
11841               set_op (disp, 1);
11842               oappend (sizeflag & AFLAG ? "rip" : "eip");
11843             }
11844           *obufp = '\0';
11845           if (havebase)
11846             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11847                      ? names64[rbase] : names32[rbase]);
11848           if (havesib)
11849             {
11850               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11851                  print index to tell base + index from base.  */
11852               if (scale != 0
11853                   || needindex
11854                   || haveindex
11855                   || (havebase && base != ESP_REG_NUM))
11856                 {
11857                   if (!intel_syntax || havebase)
11858                     {
11859                       *obufp++ = separator_char;
11860                       *obufp = '\0';
11861                     }
11862                   if (haveindex)
11863                     oappend (address_mode == mode_64bit
11864                              && (sizeflag & AFLAG)
11865                              ? names64[index] : names32[index]);
11866                   else
11867                     oappend (address_mode == mode_64bit
11868                              && (sizeflag & AFLAG)
11869                              ? index64 : index32);
11870
11871                   *obufp++ = scale_char;
11872                   *obufp = '\0';
11873                   sprintf (scratchbuf, "%d", 1 << scale);
11874                   oappend (scratchbuf);
11875                 }
11876             }
11877           if (intel_syntax
11878               && (disp || modrm.mod != 0 || base == 5))
11879             {
11880               if (!havedisp || (bfd_signed_vma) disp >= 0)
11881                 {
11882                   *obufp++ = '+';
11883                   *obufp = '\0';
11884                 }
11885               else if (modrm.mod != 1 && disp != -disp)
11886                 {
11887                   *obufp++ = '-';
11888                   *obufp = '\0';
11889                   disp = - (bfd_signed_vma) disp;
11890                 }
11891
11892               if (havedisp)
11893                 print_displacement (scratchbuf, disp);
11894               else
11895                 print_operand_value (scratchbuf, 1, disp);
11896               oappend (scratchbuf);
11897             }
11898
11899           *obufp++ = close_char;
11900           *obufp = '\0';
11901         }
11902       else if (intel_syntax)
11903         {
11904           if (modrm.mod != 0 || base == 5)
11905             {
11906               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11907                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11908                 ;
11909               else
11910                 {
11911                   oappend (names_seg[ds_reg - es_reg]);
11912                   oappend (":");
11913                 }
11914               print_operand_value (scratchbuf, 1, disp);
11915               oappend (scratchbuf);
11916             }
11917         }
11918     }
11919   else
11920     { /* 16 bit address mode */
11921       switch (modrm.mod)
11922         {
11923         case 0:
11924           if (modrm.rm == 6)
11925             {
11926               disp = get16 ();
11927               if ((disp & 0x8000) != 0)
11928                 disp -= 0x10000;
11929             }
11930           break;
11931         case 1:
11932           FETCH_DATA (the_info, codep + 1);
11933           disp = *codep++;
11934           if ((disp & 0x80) != 0)
11935             disp -= 0x100;
11936           break;
11937         case 2:
11938           disp = get16 ();
11939           if ((disp & 0x8000) != 0)
11940             disp -= 0x10000;
11941           break;
11942         }
11943
11944       if (!intel_syntax)
11945         if (modrm.mod != 0 || modrm.rm == 6)
11946           {
11947             print_displacement (scratchbuf, disp);
11948             oappend (scratchbuf);
11949           }
11950
11951       if (modrm.mod != 0 || modrm.rm != 6)
11952         {
11953           *obufp++ = open_char;
11954           *obufp = '\0';
11955           oappend (index16[modrm.rm]);
11956           if (intel_syntax
11957               && (disp || modrm.mod != 0 || modrm.rm == 6))
11958             {
11959               if ((bfd_signed_vma) disp >= 0)
11960                 {
11961                   *obufp++ = '+';
11962                   *obufp = '\0';
11963                 }
11964               else if (modrm.mod != 1)
11965                 {
11966                   *obufp++ = '-';
11967                   *obufp = '\0';
11968                   disp = - (bfd_signed_vma) disp;
11969                 }
11970
11971               print_displacement (scratchbuf, disp);
11972               oappend (scratchbuf);
11973             }
11974
11975           *obufp++ = close_char;
11976           *obufp = '\0';
11977         }
11978       else if (intel_syntax)
11979         {
11980           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11981                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11982             ;
11983           else
11984             {
11985               oappend (names_seg[ds_reg - es_reg]);
11986               oappend (":");
11987             }
11988           print_operand_value (scratchbuf, 1, disp & 0xffff);
11989           oappend (scratchbuf);
11990         }
11991     }
11992 }
11993
11994 static void
11995 OP_E_extended (int bytemode, int sizeflag)
11996 {
11997   /* Skip mod/rm byte.  */
11998   MODRM_CHECK;
11999   codep++;
12000
12001   if (modrm.mod == 3)
12002     OP_E_register (bytemode, sizeflag);
12003   else
12004     OP_E_memory (bytemode, sizeflag);
12005 }
12006
12007 static void
12008 OP_E (int bytemode, int sizeflag)
12009 {
12010   OP_E_extended (bytemode, sizeflag);
12011 }
12012
12013
12014 static void
12015 OP_G (int bytemode, int sizeflag)
12016 {
12017   int add = 0;
12018   USED_REX (REX_R);
12019   if (rex & REX_R)
12020     add += 8;
12021   switch (bytemode)
12022     {
12023     case b_mode:
12024       USED_REX (0);
12025       if (rex)
12026         oappend (names8rex[modrm.reg + add]);
12027       else
12028         oappend (names8[modrm.reg + add]);
12029       break;
12030     case w_mode:
12031       oappend (names16[modrm.reg + add]);
12032       break;
12033     case d_mode:
12034       oappend (names32[modrm.reg + add]);
12035       break;
12036     case q_mode:
12037       oappend (names64[modrm.reg + add]);
12038       break;
12039     case v_mode:
12040     case dq_mode:
12041     case dqb_mode:
12042     case dqd_mode:
12043     case dqw_mode:
12044       USED_REX (REX_W);
12045       if (rex & REX_W)
12046         oappend (names64[modrm.reg + add]);
12047       else if ((sizeflag & DFLAG) || bytemode != v_mode)
12048         oappend (names32[modrm.reg + add]);
12049       else
12050         oappend (names16[modrm.reg + add]);
12051       used_prefixes |= (prefixes & PREFIX_DATA);
12052       break;
12053     case m_mode:
12054       if (address_mode == mode_64bit)
12055         oappend (names64[modrm.reg + add]);
12056       else
12057         oappend (names32[modrm.reg + add]);
12058       break;
12059     default:
12060       oappend (INTERNAL_DISASSEMBLER_ERROR);
12061       break;
12062     }
12063 }
12064
12065 static bfd_vma
12066 get64 (void)
12067 {
12068   bfd_vma x;
12069 #ifdef BFD64
12070   unsigned int a;
12071   unsigned int b;
12072
12073   FETCH_DATA (the_info, codep + 8);
12074   a = *codep++ & 0xff;
12075   a |= (*codep++ & 0xff) << 8;
12076   a |= (*codep++ & 0xff) << 16;
12077   a |= (*codep++ & 0xff) << 24;
12078   b = *codep++ & 0xff;
12079   b |= (*codep++ & 0xff) << 8;
12080   b |= (*codep++ & 0xff) << 16;
12081   b |= (*codep++ & 0xff) << 24;
12082   x = a + ((bfd_vma) b << 32);
12083 #else
12084   abort ();
12085   x = 0;
12086 #endif
12087   return x;
12088 }
12089
12090 static bfd_signed_vma
12091 get32 (void)
12092 {
12093   bfd_signed_vma x = 0;
12094
12095   FETCH_DATA (the_info, codep + 4);
12096   x = *codep++ & (bfd_signed_vma) 0xff;
12097   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12098   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12099   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12100   return x;
12101 }
12102
12103 static bfd_signed_vma
12104 get32s (void)
12105 {
12106   bfd_signed_vma x = 0;
12107
12108   FETCH_DATA (the_info, codep + 4);
12109   x = *codep++ & (bfd_signed_vma) 0xff;
12110   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
12111   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
12112   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
12113
12114   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
12115
12116   return x;
12117 }
12118
12119 static int
12120 get16 (void)
12121 {
12122   int x = 0;
12123
12124   FETCH_DATA (the_info, codep + 2);
12125   x = *codep++ & 0xff;
12126   x |= (*codep++ & 0xff) << 8;
12127   return x;
12128 }
12129
12130 static void
12131 set_op (bfd_vma op, int riprel)
12132 {
12133   op_index[op_ad] = op_ad;
12134   if (address_mode == mode_64bit)
12135     {
12136       op_address[op_ad] = op;
12137       op_riprel[op_ad] = riprel;
12138     }
12139   else
12140     {
12141       /* Mask to get a 32-bit address.  */
12142       op_address[op_ad] = op & 0xffffffff;
12143       op_riprel[op_ad] = riprel & 0xffffffff;
12144     }
12145 }
12146
12147 static void
12148 OP_REG (int code, int sizeflag)
12149 {
12150   const char *s;
12151   int add;
12152   USED_REX (REX_B);
12153   if (rex & REX_B)
12154     add = 8;
12155   else
12156     add = 0;
12157
12158   switch (code)
12159     {
12160     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12161     case sp_reg: case bp_reg: case si_reg: case di_reg:
12162       s = names16[code - ax_reg + add];
12163       break;
12164     case es_reg: case ss_reg: case cs_reg:
12165     case ds_reg: case fs_reg: case gs_reg:
12166       s = names_seg[code - es_reg + add];
12167       break;
12168     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12169     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12170       USED_REX (0);
12171       if (rex)
12172         s = names8rex[code - al_reg + add];
12173       else
12174         s = names8[code - al_reg];
12175       break;
12176     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12177     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12178       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12179         {
12180           s = names64[code - rAX_reg + add];
12181           break;
12182         }
12183       code += eAX_reg - rAX_reg;
12184       /* Fall through.  */
12185     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12186     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12187       USED_REX (REX_W);
12188       if (rex & REX_W)
12189         s = names64[code - eAX_reg + add];
12190       else if (sizeflag & DFLAG)
12191         s = names32[code - eAX_reg + add];
12192       else
12193         s = names16[code - eAX_reg + add];
12194       used_prefixes |= (prefixes & PREFIX_DATA);
12195       break;
12196     default:
12197       s = INTERNAL_DISASSEMBLER_ERROR;
12198       break;
12199     }
12200   oappend (s);
12201 }
12202
12203 static void
12204 OP_IMREG (int code, int sizeflag)
12205 {
12206   const char *s;
12207
12208   switch (code)
12209     {
12210     case indir_dx_reg:
12211       if (intel_syntax)
12212         s = "dx";
12213       else
12214         s = "(%dx)";
12215       break;
12216     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12217     case sp_reg: case bp_reg: case si_reg: case di_reg:
12218       s = names16[code - ax_reg];
12219       break;
12220     case es_reg: case ss_reg: case cs_reg:
12221     case ds_reg: case fs_reg: case gs_reg:
12222       s = names_seg[code - es_reg];
12223       break;
12224     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12225     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12226       USED_REX (0);
12227       if (rex)
12228         s = names8rex[code - al_reg];
12229       else
12230         s = names8[code - al_reg];
12231       break;
12232     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12233     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12234       USED_REX (REX_W);
12235       if (rex & REX_W)
12236         s = names64[code - eAX_reg];
12237       else if (sizeflag & DFLAG)
12238         s = names32[code - eAX_reg];
12239       else
12240         s = names16[code - eAX_reg];
12241       used_prefixes |= (prefixes & PREFIX_DATA);
12242       break;
12243     case z_mode_ax_reg:
12244       if ((rex & REX_W) || (sizeflag & DFLAG))
12245         s = *names32;
12246       else
12247         s = *names16;
12248       if (!(rex & REX_W))
12249         used_prefixes |= (prefixes & PREFIX_DATA);
12250       break;
12251     default:
12252       s = INTERNAL_DISASSEMBLER_ERROR;
12253       break;
12254     }
12255   oappend (s);
12256 }
12257
12258 static void
12259 OP_I (int bytemode, int sizeflag)
12260 {
12261   bfd_signed_vma op;
12262   bfd_signed_vma mask = -1;
12263
12264   switch (bytemode)
12265     {
12266     case b_mode:
12267       FETCH_DATA (the_info, codep + 1);
12268       op = *codep++;
12269       mask = 0xff;
12270       break;
12271     case q_mode:
12272       if (address_mode == mode_64bit)
12273         {
12274           op = get32s ();
12275           break;
12276         }
12277       /* Fall through.  */
12278     case v_mode:
12279       USED_REX (REX_W);
12280       if (rex & REX_W)
12281         op = get32s ();
12282       else if (sizeflag & DFLAG)
12283         {
12284           op = get32 ();
12285           mask = 0xffffffff;
12286         }
12287       else
12288         {
12289           op = get16 ();
12290           mask = 0xfffff;
12291         }
12292       used_prefixes |= (prefixes & PREFIX_DATA);
12293       break;
12294     case w_mode:
12295       mask = 0xfffff;
12296       op = get16 ();
12297       break;
12298     case const_1_mode:
12299       if (intel_syntax)
12300         oappend ("1");
12301       return;
12302     default:
12303       oappend (INTERNAL_DISASSEMBLER_ERROR);
12304       return;
12305     }
12306
12307   op &= mask;
12308   scratchbuf[0] = '$';
12309   print_operand_value (scratchbuf + 1, 1, op);
12310   oappend (scratchbuf + intel_syntax);
12311   scratchbuf[0] = '\0';
12312 }
12313
12314 static void
12315 OP_I64 (int bytemode, int sizeflag)
12316 {
12317   bfd_signed_vma op;
12318   bfd_signed_vma mask = -1;
12319
12320   if (address_mode != mode_64bit)
12321     {
12322       OP_I (bytemode, sizeflag);
12323       return;
12324     }
12325
12326   switch (bytemode)
12327     {
12328     case b_mode:
12329       FETCH_DATA (the_info, codep + 1);
12330       op = *codep++;
12331       mask = 0xff;
12332       break;
12333     case v_mode:
12334       USED_REX (REX_W);
12335       if (rex & REX_W)
12336         op = get64 ();
12337       else if (sizeflag & DFLAG)
12338         {
12339           op = get32 ();
12340           mask = 0xffffffff;
12341         }
12342       else
12343         {
12344           op = get16 ();
12345           mask = 0xfffff;
12346         }
12347       used_prefixes |= (prefixes & PREFIX_DATA);
12348       break;
12349     case w_mode:
12350       mask = 0xfffff;
12351       op = get16 ();
12352       break;
12353     default:
12354       oappend (INTERNAL_DISASSEMBLER_ERROR);
12355       return;
12356     }
12357
12358   op &= mask;
12359   scratchbuf[0] = '$';
12360   print_operand_value (scratchbuf + 1, 1, op);
12361   oappend (scratchbuf + intel_syntax);
12362   scratchbuf[0] = '\0';
12363 }
12364
12365 static void
12366 OP_sI (int bytemode, int sizeflag)
12367 {
12368   bfd_signed_vma op;
12369   bfd_signed_vma mask = -1;
12370
12371   switch (bytemode)
12372     {
12373     case b_mode:
12374       FETCH_DATA (the_info, codep + 1);
12375       op = *codep++;
12376       if ((op & 0x80) != 0)
12377         op -= 0x100;
12378       mask = 0xffffffff;
12379       break;
12380     case v_mode:
12381       USED_REX (REX_W);
12382       if (rex & REX_W)
12383         op = get32s ();
12384       else if (sizeflag & DFLAG)
12385         {
12386           op = get32s ();
12387           mask = 0xffffffff;
12388         }
12389       else
12390         {
12391           mask = 0xffffffff;
12392           op = get16 ();
12393           if ((op & 0x8000) != 0)
12394             op -= 0x10000;
12395         }
12396       used_prefixes |= (prefixes & PREFIX_DATA);
12397       break;
12398     case w_mode:
12399       op = get16 ();
12400       mask = 0xffffffff;
12401       if ((op & 0x8000) != 0)
12402         op -= 0x10000;
12403       break;
12404     default:
12405       oappend (INTERNAL_DISASSEMBLER_ERROR);
12406       return;
12407     }
12408
12409   scratchbuf[0] = '$';
12410   print_operand_value (scratchbuf + 1, 1, op);
12411   oappend (scratchbuf + intel_syntax);
12412 }
12413
12414 static void
12415 OP_J (int bytemode, int sizeflag)
12416 {
12417   bfd_vma disp;
12418   bfd_vma mask = -1;
12419   bfd_vma segment = 0;
12420
12421   switch (bytemode)
12422     {
12423     case b_mode:
12424       FETCH_DATA (the_info, codep + 1);
12425       disp = *codep++;
12426       if ((disp & 0x80) != 0)
12427         disp -= 0x100;
12428       break;
12429     case v_mode:
12430       if ((sizeflag & DFLAG) || (rex & REX_W))
12431         disp = get32s ();
12432       else
12433         {
12434           disp = get16 ();
12435           if ((disp & 0x8000) != 0)
12436             disp -= 0x10000;
12437           /* In 16bit mode, address is wrapped around at 64k within
12438              the same segment.  Otherwise, a data16 prefix on a jump
12439              instruction means that the pc is masked to 16 bits after
12440              the displacement is added!  */
12441           mask = 0xffff;
12442           if ((prefixes & PREFIX_DATA) == 0)
12443             segment = ((start_pc + codep - start_codep)
12444                        & ~((bfd_vma) 0xffff));
12445         }
12446       used_prefixes |= (prefixes & PREFIX_DATA);
12447       break;
12448     default:
12449       oappend (INTERNAL_DISASSEMBLER_ERROR);
12450       return;
12451     }
12452   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12453   set_op (disp, 0);
12454   print_operand_value (scratchbuf, 1, disp);
12455   oappend (scratchbuf);
12456 }
12457
12458 static void
12459 OP_SEG (int bytemode, int sizeflag)
12460 {
12461   if (bytemode == w_mode)
12462     oappend (names_seg[modrm.reg]);
12463   else
12464     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12465 }
12466
12467 static void
12468 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12469 {
12470   int seg, offset;
12471
12472   if (sizeflag & DFLAG)
12473     {
12474       offset = get32 ();
12475       seg = get16 ();
12476     }
12477   else
12478     {
12479       offset = get16 ();
12480       seg = get16 ();
12481     }
12482   used_prefixes |= (prefixes & PREFIX_DATA);
12483   if (intel_syntax)
12484     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12485   else
12486     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12487   oappend (scratchbuf);
12488 }
12489
12490 static void
12491 OP_OFF (int bytemode, int sizeflag)
12492 {
12493   bfd_vma off;
12494
12495   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12496     intel_operand_size (bytemode, sizeflag);
12497   append_seg ();
12498
12499   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12500     off = get32 ();
12501   else
12502     off = get16 ();
12503
12504   if (intel_syntax)
12505     {
12506       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12507                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12508         {
12509           oappend (names_seg[ds_reg - es_reg]);
12510           oappend (":");
12511         }
12512     }
12513   print_operand_value (scratchbuf, 1, off);
12514   oappend (scratchbuf);
12515 }
12516
12517 static void
12518 OP_OFF64 (int bytemode, int sizeflag)
12519 {
12520   bfd_vma off;
12521
12522   if (address_mode != mode_64bit
12523       || (prefixes & PREFIX_ADDR))
12524     {
12525       OP_OFF (bytemode, sizeflag);
12526       return;
12527     }
12528
12529   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12530     intel_operand_size (bytemode, sizeflag);
12531   append_seg ();
12532
12533   off = get64 ();
12534
12535   if (intel_syntax)
12536     {
12537       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12538                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12539         {
12540           oappend (names_seg[ds_reg - es_reg]);
12541           oappend (":");
12542         }
12543     }
12544   print_operand_value (scratchbuf, 1, off);
12545   oappend (scratchbuf);
12546 }
12547
12548 static void
12549 ptr_reg (int code, int sizeflag)
12550 {
12551   const char *s;
12552
12553   *obufp++ = open_char;
12554   used_prefixes |= (prefixes & PREFIX_ADDR);
12555   if (address_mode == mode_64bit)
12556     {
12557       if (!(sizeflag & AFLAG))
12558         s = names32[code - eAX_reg];
12559       else
12560         s = names64[code - eAX_reg];
12561     }
12562   else if (sizeflag & AFLAG)
12563     s = names32[code - eAX_reg];
12564   else
12565     s = names16[code - eAX_reg];
12566   oappend (s);
12567   *obufp++ = close_char;
12568   *obufp = 0;
12569 }
12570
12571 static void
12572 OP_ESreg (int code, int sizeflag)
12573 {
12574   if (intel_syntax)
12575     {
12576       switch (codep[-1])
12577         {
12578         case 0x6d:      /* insw/insl */
12579           intel_operand_size (z_mode, sizeflag);
12580           break;
12581         case 0xa5:      /* movsw/movsl/movsq */
12582         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12583         case 0xab:      /* stosw/stosl */
12584         case 0xaf:      /* scasw/scasl */
12585           intel_operand_size (v_mode, sizeflag);
12586           break;
12587         default:
12588           intel_operand_size (b_mode, sizeflag);
12589         }
12590     }
12591   oappend ("%es:" + intel_syntax);
12592   ptr_reg (code, sizeflag);
12593 }
12594
12595 static void
12596 OP_DSreg (int code, int sizeflag)
12597 {
12598   if (intel_syntax)
12599     {
12600       switch (codep[-1])
12601         {
12602         case 0x6f:      /* outsw/outsl */
12603           intel_operand_size (z_mode, sizeflag);
12604           break;
12605         case 0xa5:      /* movsw/movsl/movsq */
12606         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12607         case 0xad:      /* lodsw/lodsl/lodsq */
12608           intel_operand_size (v_mode, sizeflag);
12609           break;
12610         default:
12611           intel_operand_size (b_mode, sizeflag);
12612         }
12613     }
12614   if ((prefixes
12615        & (PREFIX_CS
12616           | PREFIX_DS
12617           | PREFIX_SS
12618           | PREFIX_ES
12619           | PREFIX_FS
12620           | PREFIX_GS)) == 0)
12621     prefixes |= PREFIX_DS;
12622   append_seg ();
12623   ptr_reg (code, sizeflag);
12624 }
12625
12626 static void
12627 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12628 {
12629   int add;
12630   if (rex & REX_R)
12631     {
12632       USED_REX (REX_R);
12633       add = 8;
12634     }
12635   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12636     {
12637       lock_prefix = NULL;
12638       used_prefixes |= PREFIX_LOCK;
12639       add = 8;
12640     }
12641   else
12642     add = 0;
12643   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12644   oappend (scratchbuf + intel_syntax);
12645 }
12646
12647 static void
12648 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12649 {
12650   int add;
12651   USED_REX (REX_R);
12652   if (rex & REX_R)
12653     add = 8;
12654   else
12655     add = 0;
12656   if (intel_syntax)
12657     sprintf (scratchbuf, "db%d", modrm.reg + add);
12658   else
12659     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12660   oappend (scratchbuf);
12661 }
12662
12663 static void
12664 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12665 {
12666   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12667   oappend (scratchbuf + intel_syntax);
12668 }
12669
12670 static void
12671 OP_R (int bytemode, int sizeflag)
12672 {
12673   if (modrm.mod == 3)
12674     OP_E (bytemode, sizeflag);
12675   else
12676     BadOp ();
12677 }
12678
12679 static void
12680 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12681 {
12682   used_prefixes |= (prefixes & PREFIX_DATA);
12683   if (prefixes & PREFIX_DATA)
12684     {
12685       int add;
12686       USED_REX (REX_R);
12687       if (rex & REX_R)
12688         add = 8;
12689       else
12690         add = 0;
12691       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12692     }
12693   else
12694     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12695   oappend (scratchbuf + intel_syntax);
12696 }
12697
12698 static void
12699 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12700 {
12701   int add;
12702   USED_REX (REX_R);
12703   if (rex & REX_R)
12704     add = 8;
12705   else
12706     add = 0;
12707   if (need_vex && bytemode != xmm_mode)
12708     {
12709       switch (vex.length)
12710         {
12711         case 128:
12712           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12713           break;
12714         case 256:
12715           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12716           break;
12717         default:
12718           abort ();
12719         }
12720     }
12721   else
12722     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12723   oappend (scratchbuf + intel_syntax);
12724 }
12725
12726 static void
12727 OP_EM (int bytemode, int sizeflag)
12728 {
12729   if (modrm.mod != 3)
12730     {
12731       if (intel_syntax
12732           && (bytemode == v_mode || bytemode == v_swap_mode))
12733         {
12734           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12735           used_prefixes |= (prefixes & PREFIX_DATA);
12736         }
12737       OP_E (bytemode, sizeflag);
12738       return;
12739     }
12740
12741   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12742     swap_operand ();
12743
12744   /* Skip mod/rm byte.  */
12745   MODRM_CHECK;
12746   codep++;
12747   used_prefixes |= (prefixes & PREFIX_DATA);
12748   if (prefixes & PREFIX_DATA)
12749     {
12750       int add;
12751
12752       USED_REX (REX_B);
12753       if (rex & REX_B)
12754         add = 8;
12755       else
12756         add = 0;
12757       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12758     }
12759   else
12760     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12761   oappend (scratchbuf + intel_syntax);
12762 }
12763
12764 /* cvt* are the only instructions in sse2 which have
12765    both SSE and MMX operands and also have 0x66 prefix
12766    in their opcode. 0x66 was originally used to differentiate
12767    between SSE and MMX instruction(operands). So we have to handle the
12768    cvt* separately using OP_EMC and OP_MXC */
12769 static void
12770 OP_EMC (int bytemode, int sizeflag)
12771 {
12772   if (modrm.mod != 3)
12773     {
12774       if (intel_syntax && bytemode == v_mode)
12775         {
12776           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12777           used_prefixes |= (prefixes & PREFIX_DATA);
12778         }
12779       OP_E (bytemode, sizeflag);
12780       return;
12781     }
12782
12783   /* Skip mod/rm byte.  */
12784   MODRM_CHECK;
12785   codep++;
12786   used_prefixes |= (prefixes & PREFIX_DATA);
12787   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12788   oappend (scratchbuf + intel_syntax);
12789 }
12790
12791 static void
12792 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12793 {
12794   used_prefixes |= (prefixes & PREFIX_DATA);
12795   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12796   oappend (scratchbuf + intel_syntax);
12797 }
12798
12799 static void
12800 OP_EX (int bytemode, int sizeflag)
12801 {
12802   int add;
12803
12804   /* Skip mod/rm byte.  */
12805   MODRM_CHECK;
12806   codep++;
12807
12808   if (modrm.mod != 3)
12809     {
12810       OP_E_memory (bytemode, sizeflag);
12811       return;
12812     }
12813
12814   USED_REX (REX_B);
12815   if (rex & REX_B)
12816     add = 8;
12817   else
12818     add = 0;
12819
12820   if ((sizeflag & SUFFIX_ALWAYS)
12821       && (bytemode == x_swap_mode
12822           || bytemode == d_swap_mode
12823           || bytemode == q_swap_mode))
12824     swap_operand ();
12825
12826   if (need_vex
12827       && bytemode != xmm_mode
12828       && bytemode != xmmq_mode)
12829     {
12830       switch (vex.length)
12831         {
12832         case 128:
12833           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12834           break;
12835         case 256:
12836           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12837           break;
12838         default:
12839           abort ();
12840         }
12841     }
12842   else
12843     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12844   oappend (scratchbuf + intel_syntax);
12845 }
12846
12847 static void
12848 OP_MS (int bytemode, int sizeflag)
12849 {
12850   if (modrm.mod == 3)
12851     OP_EM (bytemode, sizeflag);
12852   else
12853     BadOp ();
12854 }
12855
12856 static void
12857 OP_XS (int bytemode, int sizeflag)
12858 {
12859   if (modrm.mod == 3)
12860     OP_EX (bytemode, sizeflag);
12861   else
12862     BadOp ();
12863 }
12864
12865 static void
12866 OP_M (int bytemode, int sizeflag)
12867 {
12868   if (modrm.mod == 3)
12869     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12870     BadOp ();
12871   else
12872     OP_E (bytemode, sizeflag);
12873 }
12874
12875 static void
12876 OP_0f07 (int bytemode, int sizeflag)
12877 {
12878   if (modrm.mod != 3 || modrm.rm != 0)
12879     BadOp ();
12880   else
12881     OP_E (bytemode, sizeflag);
12882 }
12883
12884 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12885    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12886
12887 static void
12888 NOP_Fixup1 (int bytemode, int sizeflag)
12889 {
12890   if ((prefixes & PREFIX_DATA) != 0
12891       || (rex != 0
12892           && rex != 0x48
12893           && address_mode == mode_64bit))
12894     OP_REG (bytemode, sizeflag);
12895   else
12896     strcpy (obuf, "nop");
12897 }
12898
12899 static void
12900 NOP_Fixup2 (int bytemode, int sizeflag)
12901 {
12902   if ((prefixes & PREFIX_DATA) != 0
12903       || (rex != 0
12904           && rex != 0x48
12905           && address_mode == mode_64bit))
12906     OP_IMREG (bytemode, sizeflag);
12907 }
12908
12909 static const char *const Suffix3DNow[] = {
12910 /* 00 */        NULL,           NULL,           NULL,           NULL,
12911 /* 04 */        NULL,           NULL,           NULL,           NULL,
12912 /* 08 */        NULL,           NULL,           NULL,           NULL,
12913 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12914 /* 10 */        NULL,           NULL,           NULL,           NULL,
12915 /* 14 */        NULL,           NULL,           NULL,           NULL,
12916 /* 18 */        NULL,           NULL,           NULL,           NULL,
12917 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12918 /* 20 */        NULL,           NULL,           NULL,           NULL,
12919 /* 24 */        NULL,           NULL,           NULL,           NULL,
12920 /* 28 */        NULL,           NULL,           NULL,           NULL,
12921 /* 2C */        NULL,           NULL,           NULL,           NULL,
12922 /* 30 */        NULL,           NULL,           NULL,           NULL,
12923 /* 34 */        NULL,           NULL,           NULL,           NULL,
12924 /* 38 */        NULL,           NULL,           NULL,           NULL,
12925 /* 3C */        NULL,           NULL,           NULL,           NULL,
12926 /* 40 */        NULL,           NULL,           NULL,           NULL,
12927 /* 44 */        NULL,           NULL,           NULL,           NULL,
12928 /* 48 */        NULL,           NULL,           NULL,           NULL,
12929 /* 4C */        NULL,           NULL,           NULL,           NULL,
12930 /* 50 */        NULL,           NULL,           NULL,           NULL,
12931 /* 54 */        NULL,           NULL,           NULL,           NULL,
12932 /* 58 */        NULL,           NULL,           NULL,           NULL,
12933 /* 5C */        NULL,           NULL,           NULL,           NULL,
12934 /* 60 */        NULL,           NULL,           NULL,           NULL,
12935 /* 64 */        NULL,           NULL,           NULL,           NULL,
12936 /* 68 */        NULL,           NULL,           NULL,           NULL,
12937 /* 6C */        NULL,           NULL,           NULL,           NULL,
12938 /* 70 */        NULL,           NULL,           NULL,           NULL,
12939 /* 74 */        NULL,           NULL,           NULL,           NULL,
12940 /* 78 */        NULL,           NULL,           NULL,           NULL,
12941 /* 7C */        NULL,           NULL,           NULL,           NULL,
12942 /* 80 */        NULL,           NULL,           NULL,           NULL,
12943 /* 84 */        NULL,           NULL,           NULL,           NULL,
12944 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12945 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12946 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12947 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12948 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12949 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12950 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12951 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12952 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12953 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12954 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12955 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12956 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12957 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12958 /* C0 */        NULL,           NULL,           NULL,           NULL,
12959 /* C4 */        NULL,           NULL,           NULL,           NULL,
12960 /* C8 */        NULL,           NULL,           NULL,           NULL,
12961 /* CC */        NULL,           NULL,           NULL,           NULL,
12962 /* D0 */        NULL,           NULL,           NULL,           NULL,
12963 /* D4 */        NULL,           NULL,           NULL,           NULL,
12964 /* D8 */        NULL,           NULL,           NULL,           NULL,
12965 /* DC */        NULL,           NULL,           NULL,           NULL,
12966 /* E0 */        NULL,           NULL,           NULL,           NULL,
12967 /* E4 */        NULL,           NULL,           NULL,           NULL,
12968 /* E8 */        NULL,           NULL,           NULL,           NULL,
12969 /* EC */        NULL,           NULL,           NULL,           NULL,
12970 /* F0 */        NULL,           NULL,           NULL,           NULL,
12971 /* F4 */        NULL,           NULL,           NULL,           NULL,
12972 /* F8 */        NULL,           NULL,           NULL,           NULL,
12973 /* FC */        NULL,           NULL,           NULL,           NULL,
12974 };
12975
12976 static void
12977 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12978 {
12979   const char *mnemonic;
12980
12981   FETCH_DATA (the_info, codep + 1);
12982   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12983      place where an 8-bit immediate would normally go.  ie. the last
12984      byte of the instruction.  */
12985   obufp = mnemonicendp;
12986   mnemonic = Suffix3DNow[*codep++ & 0xff];
12987   if (mnemonic)
12988     oappend (mnemonic);
12989   else
12990     {
12991       /* Since a variable sized modrm/sib chunk is between the start
12992          of the opcode (0x0f0f) and the opcode suffix, we need to do
12993          all the modrm processing first, and don't know until now that
12994          we have a bad opcode.  This necessitates some cleaning up.  */
12995       op_out[0][0] = '\0';
12996       op_out[1][0] = '\0';
12997       BadOp ();
12998     }
12999   mnemonicendp = obufp;
13000 }
13001
13002 static struct op simd_cmp_op[] =
13003 {
13004   { STRING_COMMA_LEN ("eq") },
13005   { STRING_COMMA_LEN ("lt") },
13006   { STRING_COMMA_LEN ("le") },
13007   { STRING_COMMA_LEN ("unord") },
13008   { STRING_COMMA_LEN ("neq") },
13009   { STRING_COMMA_LEN ("nlt") },
13010   { STRING_COMMA_LEN ("nle") },
13011   { STRING_COMMA_LEN ("ord") }
13012 };
13013
13014 static void
13015 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13016 {
13017   unsigned int cmp_type;
13018
13019   FETCH_DATA (the_info, codep + 1);
13020   cmp_type = *codep++ & 0xff;
13021   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13022     {
13023       char suffix [3];
13024       char *p = mnemonicendp - 2;
13025       suffix[0] = p[0];
13026       suffix[1] = p[1];
13027       suffix[2] = '\0';
13028       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13029       mnemonicendp += simd_cmp_op[cmp_type].len;
13030     }
13031   else
13032     {
13033       /* We have a reserved extension byte.  Output it directly.  */
13034       scratchbuf[0] = '$';
13035       print_operand_value (scratchbuf + 1, 1, cmp_type);
13036       oappend (scratchbuf + intel_syntax);
13037       scratchbuf[0] = '\0';
13038     }
13039 }
13040
13041 static void
13042 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
13043           int sizeflag ATTRIBUTE_UNUSED)
13044 {
13045   /* mwait %eax,%ecx  */
13046   if (!intel_syntax)
13047     {
13048       const char **names = (address_mode == mode_64bit
13049                             ? names64 : names32);
13050       strcpy (op_out[0], names[0]);
13051       strcpy (op_out[1], names[1]);
13052       two_source_ops = 1;
13053     }
13054   /* Skip mod/rm byte.  */
13055   MODRM_CHECK;
13056   codep++;
13057 }
13058
13059 static void
13060 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13061             int sizeflag ATTRIBUTE_UNUSED)
13062 {
13063   /* monitor %eax,%ecx,%edx"  */
13064   if (!intel_syntax)
13065     {
13066       const char **op1_names;
13067       const char **names = (address_mode == mode_64bit
13068                             ? names64 : names32);
13069
13070       if (!(prefixes & PREFIX_ADDR))
13071         op1_names = (address_mode == mode_16bit
13072                      ? names16 : names);
13073       else
13074         {
13075           /* Remove "addr16/addr32".  */
13076           addr_prefix = NULL;
13077           op1_names = (address_mode != mode_32bit
13078                        ? names32 : names16);
13079           used_prefixes |= PREFIX_ADDR;
13080         }
13081       strcpy (op_out[0], op1_names[0]);
13082       strcpy (op_out[1], names[1]);
13083       strcpy (op_out[2], names[2]);
13084       two_source_ops = 1;
13085     }
13086   /* Skip mod/rm byte.  */
13087   MODRM_CHECK;
13088   codep++;
13089 }
13090
13091 static void
13092 BadOp (void)
13093 {
13094   /* Throw away prefixes and 1st. opcode byte.  */
13095   codep = insn_codep + 1;
13096   oappend ("(bad)");
13097 }
13098
13099 static void
13100 REP_Fixup (int bytemode, int sizeflag)
13101 {
13102   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13103      lods and stos.  */
13104   if (prefixes & PREFIX_REPZ)
13105     repz_prefix = "rep ";
13106
13107   switch (bytemode)
13108     {
13109     case al_reg:
13110     case eAX_reg:
13111     case indir_dx_reg:
13112       OP_IMREG (bytemode, sizeflag);
13113       break;
13114     case eDI_reg:
13115       OP_ESreg (bytemode, sizeflag);
13116       break;
13117     case eSI_reg:
13118       OP_DSreg (bytemode, sizeflag);
13119       break;
13120     default:
13121       abort ();
13122       break;
13123     }
13124 }
13125
13126 static void
13127 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13128 {
13129   USED_REX (REX_W);
13130   if (rex & REX_W)
13131     {
13132       /* Change cmpxchg8b to cmpxchg16b.  */
13133       char *p = mnemonicendp - 2;
13134       mnemonicendp = stpcpy (p, "16b");
13135       bytemode = o_mode;
13136     }
13137   OP_M (bytemode, sizeflag);
13138 }
13139
13140 static void
13141 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13142 {
13143   if (need_vex)
13144     {
13145       switch (vex.length)
13146         {
13147         case 128:
13148           sprintf (scratchbuf, "%%xmm%d", reg);
13149           break;
13150         case 256:
13151           sprintf (scratchbuf, "%%ymm%d", reg);
13152           break;
13153         default:
13154           abort ();
13155         }
13156     }
13157   else
13158     sprintf (scratchbuf, "%%xmm%d", reg);
13159   oappend (scratchbuf + intel_syntax);
13160 }
13161
13162 static void
13163 CRC32_Fixup (int bytemode, int sizeflag)
13164 {
13165   /* Add proper suffix to "crc32".  */
13166   char *p = mnemonicendp;
13167
13168   switch (bytemode)
13169     {
13170     case b_mode:
13171       if (intel_syntax)
13172         goto skip;
13173
13174       *p++ = 'b';
13175       break;
13176     case v_mode:
13177       if (intel_syntax)
13178         goto skip;
13179
13180       USED_REX (REX_W);
13181       if (rex & REX_W)
13182         *p++ = 'q';
13183       else if (sizeflag & DFLAG)
13184         *p++ = 'l';
13185       else
13186         *p++ = 'w';
13187       used_prefixes |= (prefixes & PREFIX_DATA);
13188       break;
13189     default:
13190       oappend (INTERNAL_DISASSEMBLER_ERROR);
13191       break;
13192     }
13193   mnemonicendp = p;
13194   *p = '\0';
13195
13196 skip:
13197   if (modrm.mod == 3)
13198     {
13199       int add;
13200
13201       /* Skip mod/rm byte.  */
13202       MODRM_CHECK;
13203       codep++;
13204
13205       USED_REX (REX_B);
13206       add = (rex & REX_B) ? 8 : 0;
13207       if (bytemode == b_mode)
13208         {
13209           USED_REX (0);
13210           if (rex)
13211             oappend (names8rex[modrm.rm + add]);
13212           else
13213             oappend (names8[modrm.rm + add]);
13214         }
13215       else
13216         {
13217           USED_REX (REX_W);
13218           if (rex & REX_W)
13219             oappend (names64[modrm.rm + add]);
13220           else if ((prefixes & PREFIX_DATA))
13221             oappend (names16[modrm.rm + add]);
13222           else
13223             oappend (names32[modrm.rm + add]);
13224         }
13225     }
13226   else
13227     OP_E (bytemode, sizeflag);
13228 }
13229
13230 /* Display the destination register operand for instructions with
13231    VEX. */
13232
13233 static void
13234 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13235 {
13236   if (!need_vex)
13237     abort ();
13238
13239   if (!need_vex_reg)
13240     return;
13241
13242   switch (vex.length)
13243     {
13244     case 128:
13245       switch (bytemode)
13246         {
13247         case vex_mode:
13248         case vex128_mode:
13249           break;
13250         default:
13251           abort ();
13252           return;
13253         }
13254
13255       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13256       break;
13257     case 256:
13258       switch (bytemode)
13259         {
13260         case vex_mode:
13261         case vex256_mode:
13262           break;
13263         default:
13264           abort ();
13265           return;
13266         }
13267
13268       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13269       break;
13270     default:
13271       abort ();
13272       break;
13273     }
13274   oappend (scratchbuf + intel_syntax);
13275 }
13276
13277 /* Get the VEX immediate byte without moving codep.  */
13278
13279 static unsigned char
13280 get_vex_imm8 (int sizeflag)
13281 {
13282   int bytes_before_imm = 0;
13283
13284   /* Skip mod/rm byte.   */
13285   MODRM_CHECK;
13286   codep++;
13287
13288   if (modrm.mod != 3)
13289     {
13290       /* There are SIB/displacement bytes.  */
13291       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13292         {
13293           /* 32/64 bit address mode */
13294           int base = modrm.rm;
13295
13296           /* Check SIB byte.  */
13297           if (base == 4)
13298             {
13299               FETCH_DATA (the_info, codep + 1);
13300               base = *codep & 7;
13301               bytes_before_imm++;
13302             }
13303
13304           switch (modrm.mod)
13305             {
13306             case 0:
13307               /* When modrm.rm == 5 or modrm.rm == 4 and base in
13308                  SIB == 5, there is a 4 byte displacement.  */
13309               if (base != 5)
13310                 /* No displacement. */
13311                 break;
13312             case 2:
13313               /* 4 byte displacement.  */
13314               bytes_before_imm += 4;
13315               break;
13316             case 1:
13317               /* 1 byte displacement.  */
13318               bytes_before_imm++;
13319               break;
13320             }
13321         }
13322       else
13323         { /* 16 bit address mode */
13324           switch (modrm.mod)
13325             {
13326             case 0:
13327               /* When modrm.rm == 6, there is a 2 byte displacement.  */
13328               if (modrm.rm != 6)
13329                 /* No displacement. */
13330                 break;
13331             case 2:
13332               /* 2 byte displacement.  */
13333               bytes_before_imm += 2;
13334               break;
13335             case 1:
13336               /* 1 byte displacement.  */
13337               bytes_before_imm++;
13338               break;
13339             }
13340         }
13341     }
13342
13343   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13344   return codep [bytes_before_imm];
13345 }
13346
13347 static void
13348 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13349 {
13350   if (reg == -1 && modrm.mod != 3)
13351     {
13352       OP_E_memory (bytemode, sizeflag);
13353       return;
13354     }
13355   else
13356     {
13357       if (reg == -1)
13358         {
13359           reg = modrm.rm;
13360           USED_REX (REX_B);
13361           if (rex & REX_B)
13362             reg += 8;
13363         }
13364       else if (reg > 7 && address_mode != mode_64bit)
13365         BadOp ();
13366     }
13367
13368   switch (vex.length)
13369     {
13370     case 128:
13371       sprintf (scratchbuf, "%%xmm%d", reg);
13372       break;
13373     case 256:
13374       sprintf (scratchbuf, "%%ymm%d", reg);
13375       break;
13376     default:
13377       abort ();
13378     }
13379   oappend (scratchbuf + intel_syntax);
13380 }
13381
13382 static void
13383 OP_EX_VexW (int bytemode, int sizeflag)
13384 {
13385   int reg = -1;
13386
13387   if (!vex_w_done)
13388     {
13389       vex_w_done = 1;
13390       if (vex.w)
13391         reg = get_vex_imm8 (sizeflag) >> 4;
13392     }
13393   else
13394     {
13395       if (!vex.w)
13396         reg = get_vex_imm8 (sizeflag) >> 4;
13397     }
13398
13399   OP_EX_VexReg (bytemode, sizeflag, reg);
13400 }
13401
13402 static void
13403 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13404              int sizeflag ATTRIBUTE_UNUSED)
13405 {
13406   /* Skip the immediate byte and check for invalid bits.  */
13407   FETCH_DATA (the_info, codep + 1);
13408   if (*codep++ & 0xf)
13409     BadOp ();
13410 }
13411
13412 static void
13413 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13414 {
13415   int reg;
13416   FETCH_DATA (the_info, codep + 1);
13417   reg = *codep++;
13418
13419   if (bytemode != x_mode)
13420     abort ();
13421
13422   if (reg & 0xf)
13423       BadOp ();
13424
13425   reg >>= 4;
13426   if (reg > 7 && address_mode != mode_64bit)
13427     BadOp ();
13428
13429   switch (vex.length)
13430     {
13431     case 128:
13432       sprintf (scratchbuf, "%%xmm%d", reg);
13433       break;
13434     case 256:
13435       sprintf (scratchbuf, "%%ymm%d", reg);
13436       break;
13437     default:
13438       abort ();
13439     }
13440   oappend (scratchbuf + intel_syntax);
13441 }
13442
13443 static void
13444 OP_XMM_VexW (int bytemode, int sizeflag)
13445 {
13446   /* Turn off the REX.W bit since it is used for swapping operands
13447      now.  */
13448   rex &= ~REX_W;
13449   OP_XMM (bytemode, sizeflag);
13450 }
13451
13452 static void
13453 OP_EX_Vex (int bytemode, int sizeflag)
13454 {
13455   if (modrm.mod != 3)
13456     {
13457       if (vex.register_specifier != 0)
13458         BadOp ();
13459       need_vex_reg = 0;
13460     }
13461   OP_EX (bytemode, sizeflag);
13462 }
13463
13464 static void
13465 OP_XMM_Vex (int bytemode, int sizeflag)
13466 {
13467   if (modrm.mod != 3)
13468     {
13469       if (vex.register_specifier != 0)
13470         BadOp ();
13471       need_vex_reg = 0;
13472     }
13473   OP_XMM (bytemode, sizeflag);
13474 }
13475
13476 static void
13477 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13478 {
13479   switch (vex.length)
13480     {
13481     case 128:
13482       mnemonicendp = stpcpy (obuf, "vzeroupper");
13483       break;
13484     case 256:
13485       mnemonicendp = stpcpy (obuf, "vzeroall");
13486       break;
13487     default:
13488       abort ();
13489     }
13490 }
13491
13492 static struct op vex_cmp_op[] =
13493 {
13494   { STRING_COMMA_LEN ("eq") },
13495   { STRING_COMMA_LEN ("lt") },
13496   { STRING_COMMA_LEN ("le") },
13497   { STRING_COMMA_LEN ("unord") },
13498   { STRING_COMMA_LEN ("neq") },
13499   { STRING_COMMA_LEN ("nlt") },
13500   { STRING_COMMA_LEN ("nle") },
13501   { STRING_COMMA_LEN ("ord") },
13502   { STRING_COMMA_LEN ("eq_uq") },
13503   { STRING_COMMA_LEN ("nge") },
13504   { STRING_COMMA_LEN ("ngt") },
13505   { STRING_COMMA_LEN ("false") },
13506   { STRING_COMMA_LEN ("neq_oq") },
13507   { STRING_COMMA_LEN ("ge") },
13508   { STRING_COMMA_LEN ("gt") },
13509   { STRING_COMMA_LEN ("true") },
13510   { STRING_COMMA_LEN ("eq_os") },
13511   { STRING_COMMA_LEN ("lt_oq") },
13512   { STRING_COMMA_LEN ("le_oq") },
13513   { STRING_COMMA_LEN ("unord_s") },
13514   { STRING_COMMA_LEN ("neq_us") },
13515   { STRING_COMMA_LEN ("nlt_uq") },
13516   { STRING_COMMA_LEN ("nle_uq") },
13517   { STRING_COMMA_LEN ("ord_s") },
13518   { STRING_COMMA_LEN ("eq_us") },
13519   { STRING_COMMA_LEN ("nge_uq") },
13520   { STRING_COMMA_LEN ("ngt_uq") },
13521   { STRING_COMMA_LEN ("false_os") },
13522   { STRING_COMMA_LEN ("neq_os") },
13523   { STRING_COMMA_LEN ("ge_oq") },
13524   { STRING_COMMA_LEN ("gt_oq") },
13525   { STRING_COMMA_LEN ("true_us") },
13526 };
13527
13528 static void
13529 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13530 {
13531   unsigned int cmp_type;
13532
13533   FETCH_DATA (the_info, codep + 1);
13534   cmp_type = *codep++ & 0xff;
13535   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13536     {
13537       char suffix [3];
13538       char *p = mnemonicendp - 2;
13539       suffix[0] = p[0];
13540       suffix[1] = p[1];
13541       suffix[2] = '\0';
13542       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13543       mnemonicendp += vex_cmp_op[cmp_type].len;
13544     }
13545   else
13546     {
13547       /* We have a reserved extension byte.  Output it directly.  */
13548       scratchbuf[0] = '$';
13549       print_operand_value (scratchbuf + 1, 1, cmp_type);
13550       oappend (scratchbuf + intel_syntax);
13551       scratchbuf[0] = '\0';
13552     }
13553 }
13554
13555 static const struct op pclmul_op[] =
13556 {
13557   { STRING_COMMA_LEN ("lql") },
13558   { STRING_COMMA_LEN ("hql") },
13559   { STRING_COMMA_LEN ("lqh") },
13560   { STRING_COMMA_LEN ("hqh") }
13561 };
13562
13563 static void
13564 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13565               int sizeflag ATTRIBUTE_UNUSED)
13566 {
13567   unsigned int pclmul_type;
13568
13569   FETCH_DATA (the_info, codep + 1);
13570   pclmul_type = *codep++ & 0xff;
13571   switch (pclmul_type)
13572     {
13573     case 0x10:
13574       pclmul_type = 2;
13575       break;
13576     case 0x11:
13577       pclmul_type = 3;
13578       break;
13579     default:
13580       break;
13581     }
13582   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13583     {
13584       char suffix [4];
13585       char *p = mnemonicendp - 3;
13586       suffix[0] = p[0];
13587       suffix[1] = p[1];
13588       suffix[2] = p[2];
13589       suffix[3] = '\0';
13590       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13591       mnemonicendp += pclmul_op[pclmul_type].len;
13592     }
13593   else
13594     {
13595       /* We have a reserved extension byte.  Output it directly.  */
13596       scratchbuf[0] = '$';
13597       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13598       oappend (scratchbuf + intel_syntax);
13599       scratchbuf[0] = '\0';
13600     }
13601 }
13602
13603 static void
13604 MOVBE_Fixup (int bytemode, int sizeflag)
13605 {
13606   /* Add proper suffix to "movbe".  */
13607   char *p = mnemonicendp;
13608
13609   switch (bytemode)
13610     {
13611     case v_mode:
13612       if (intel_syntax)
13613         goto skip;
13614
13615       USED_REX (REX_W);
13616       if (sizeflag & SUFFIX_ALWAYS)
13617         {
13618           if (rex & REX_W)
13619             *p++ = 'q';
13620           else if (sizeflag & DFLAG)
13621             *p++ = 'l';
13622           else
13623             *p++ = 'w';
13624         }
13625       used_prefixes |= (prefixes & PREFIX_DATA);
13626       break;
13627     default:
13628       oappend (INTERNAL_DISASSEMBLER_ERROR);
13629       break;
13630     }
13631   mnemonicendp = p;
13632   *p = '\0';
13633
13634 skip:
13635   OP_M (bytemode, sizeflag);
13636 }
13637
13638 static void
13639 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13640 {
13641   int reg;
13642   const char **names;
13643
13644   /* Skip mod/rm byte.  */
13645   MODRM_CHECK;
13646   codep++;
13647
13648   if (vex.w)
13649     names = names64;
13650   else if (vex.length == 256)
13651     names = names32;
13652   else
13653     names = names16;
13654
13655   reg = modrm.rm;
13656   USED_REX (REX_B);
13657   if (rex & REX_B)
13658     reg += 8;
13659
13660   oappend (names[reg]);
13661 }
13662
13663 static void
13664 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13665 {
13666   const char **names;
13667
13668   if (vex.w)
13669     names = names64;
13670   else if (vex.length == 256)
13671     names = names32;
13672   else
13673     names = names16;
13674
13675   oappend (names[vex.register_specifier]);
13676 }
13677
13678 static void
13679 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
13680 {
13681   if (vex.w || vex.length == 256)
13682     OP_I (q_mode, sizeflag);
13683   else
13684     OP_I (w_mode, sizeflag);
13685 }
13686