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gas/opcodes: blackfin: move dsp mac func defines to common header
[binutils.git] / opcodes / bfin-dis.c
blob85b793cb7436f6ef965380167a4f0dea97418032
1 /* Disassemble ADI Blackfin Instructions.
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4
5 This file is part of libopcodes.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include <stdio.h>
23 #include <stdlib.h>
24 #include <string.h>
25
26 #include "opcode/bfin.h"
27
28 #ifndef PRINTF
29 #define PRINTF printf
30 #endif
31
32 #ifndef EXIT
33 #define EXIT exit
34 #endif
35
36 typedef long TIword;
37
38 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
39 #define XFIELD(w,p,s) (((w) & ((1 << (s)) - 1) << (p)) >> (p))
40 #define SIGNEXTEND(v, n) ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
41 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
42
43 #include "dis-asm.h"
44
45 typedef unsigned int bu32;
46
47 static char comment = 0;
48 static char parallel = 0;
49
50 typedef enum
51 {
52 c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
53 c_imm4, c_uimm4s4, c_uimm4s4d, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_imm5d, c_uimm5, c_imm6,
54 c_imm7, c_imm7d, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
55 c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_imm16d, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
56 c_uimm16s4d, c_uimm16, c_pcrel24, c_uimm32, c_imm32, c_huimm32, c_huimm32e,
57 } const_forms_t;
58
59 static const struct
60 {
61 const char *name;
62 const int nbits;
63 const char reloc;
64 const char issigned;
65 const char pcrel;
66 const char scale;
67 const char offset;
68 const char negative;
69 const char positive;
70 const char decimal;
71 const char leading;
72 const char exact;
73 } constant_formats[] =
74 {
75 { "0", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
76 { "1", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
77 { "4", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
78 { "2", 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
79 { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
80 { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
81 { "imm3", 3, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
82 { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
83 { "imm4", 4, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
84 { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0},
85 { "uimm4s4d", 4, 0, 0, 0, 2, 0, 0, 1, 1, 0, 0},
86 { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
87 { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0},
88 { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0, 0, 0, 0},
89 { "imm5", 5, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
90 { "imm5d", 5, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0},
91 { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
92 { "imm6", 6, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
93 { "imm7", 7, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
94 { "imm7d", 7, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
95 { "imm8", 8, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
96 { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
97 { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
98 { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
99 { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0},
100 { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0},
101 { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
102 { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
103 { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0, 0, 0, 0},
104 { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
105 { "imm16", 16, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0},
106 { "imm16d", 16, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
107 { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
108 { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
109 { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0},
110 { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0},
111 { "uimm16s4d", 16, 0, 0, 0, 2, 0, 0, 0, 1, 0, 0},
112 { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
113 { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0},
114 { "uimm32", 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
115 { "imm32", 32, 0, 1, 0, 0, 0, 0, 0, 1, 3, 0},
116 { "huimm32", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0},
117 { "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
118 };
119
120 static const char *
121 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info *outf)
122 {
123 static char buf[60];
124
125 if (constant_formats[cf].reloc)
126 {
127 bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
128 : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
129 if (constant_formats[cf].pcrel)
130 ea += pc;
131
132 /* truncate to 32-bits for proper symbol lookup/matching */
133 ea = (bu32)ea;
134
135 if (outf->symbol_at_address_func (ea, outf) || !constant_formats[cf].exact)
136 {
137 outf->print_address_func (ea, outf);
138 return "";
139 }
140 else
141 {
142 sprintf (buf, "%lx", (unsigned long) x);
143 return buf;
144 }
145 }
146
147 /* Negative constants have an implied sign bit. */
148 if (constant_formats[cf].negative)
149 {
150 int nb = constant_formats[cf].nbits + 1;
151
152 x = x | (1 << constant_formats[cf].nbits);
153 x = SIGNEXTEND (x, nb);
154 }
155 else
156 x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
157
158 if (constant_formats[cf].offset)
159 x += constant_formats[cf].offset;
160
161 if (constant_formats[cf].scale)
162 x <<= constant_formats[cf].scale;
163
164 if (constant_formats[cf].decimal)
165 {
166 if (constant_formats[cf].leading)
167 {
168 char ps[10];
169 sprintf (ps, "%%%ii", constant_formats[cf].leading);
170 sprintf (buf, ps, x);
171 }
172 else
173 sprintf (buf, "%li", x);
174 }
175 else
176 {
177 if (constant_formats[cf].issigned && x < 0)
178 sprintf (buf, "-0x%x", abs (x));
179 else
180 sprintf (buf, "0x%lx", (unsigned long) x);
181 }
182
183 return buf;
184 }
185
186 static bu32
187 fmtconst_val (const_forms_t cf, unsigned int x, unsigned int pc)
188 {
189 if (0 && constant_formats[cf].reloc)
190 {
191 bu32 ea = (((constant_formats[cf].pcrel
192 ? SIGNEXTEND (x, constant_formats[cf].nbits)
193 : x) + constant_formats[cf].offset)
194 << constant_formats[cf].scale);
195 if (constant_formats[cf].pcrel)
196 ea += pc;
197
198 return ea;
199 }
200
201 /* Negative constants have an implied sign bit. */
202 if (constant_formats[cf].negative)
203 {
204 int nb = constant_formats[cf].nbits + 1;
205 x = x | (1 << constant_formats[cf].nbits);
206 x = SIGNEXTEND (x, nb);
207 }
208 else if (constant_formats[cf].issigned)
209 x = SIGNEXTEND (x, constant_formats[cf].nbits);
210
211 x += constant_formats[cf].offset;
212 x <<= constant_formats[cf].scale;
213
214 return x;
215 }
216
217 enum machine_registers
218 {
219 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
220 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
221 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
222 REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
223 REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
224 REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
225 REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
226 REG_L2, REG_L3,
227 REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
228 REG_AQ, REG_V, REG_VS,
229 REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
230 REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
231 REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
232 REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
233 REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
234 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
235 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
236 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
237 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
238 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
239 REG_AC0_COPY, REG_V_COPY, REG_RND_MOD,
240 REG_LASTREG,
241 };
242
243 enum reg_class
244 {
245 rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
246 rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
247 rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
248 rc_sysregs3, rc_allregs,
249 LIM_REG_CLASSES
250 };
251
252 static const char * const reg_names[] =
253 {
254 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
255 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
256 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
257 "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
258 "P4", "P5", "SP", "FP", "A0.X", "A1.X", "A0.W", "A1.W",
259 "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
260 "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
261 "L2", "L3",
262 "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
263 "AQ", "V", "VS",
264 "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
265 "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
266 "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
267 "RETE", "EMUDAT",
268 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
269 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
270 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
271 "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
272 "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
273 "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
274 "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
275 "AC0_COPY", "V_COPY", "RND_MOD",
276 "LASTREG",
277 0
278 };
279
280 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
281
282 /* RL(0..7). */
283 static const enum machine_registers decode_dregs_lo[] =
284 {
285 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
286 };
287
288 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
289
290 /* RH(0..7). */
291 static const enum machine_registers decode_dregs_hi[] =
292 {
293 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
294 };
295
296 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
297
298 /* R(0..7). */
299 static const enum machine_registers decode_dregs[] =
300 {
301 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
302 };
303
304 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
305
306 /* R BYTE(0..7). */
307 static const enum machine_registers decode_dregs_byte[] =
308 {
309 REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
310 };
311
312 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
313
314 /* P(0..5) SP FP. */
315 static const enum machine_registers decode_pregs[] =
316 {
317 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
318 };
319
320 #define pregs(x) REGNAME (decode_pregs[(x) & 7])
321 #define spfp(x) REGNAME (decode_spfp[(x) & 1])
322 #define dregs_hilo(x,i) REGNAME (decode_dregs_hilo[((i) << 3)|x])
323 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
324 #define accum_word(x) REGNAME (decode_accum_word[(x) & 1])
325 #define accum(x) REGNAME (decode_accum[(x) & 1])
326
327 /* I(0..3). */
328 static const enum machine_registers decode_iregs[] =
329 {
330 REG_I0, REG_I1, REG_I2, REG_I3,
331 };
332
333 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
334
335 /* M(0..3). */
336 static const enum machine_registers decode_mregs[] =
337 {
338 REG_M0, REG_M1, REG_M2, REG_M3,
339 };
340
341 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
342 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
343 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
344
345 /* dregs pregs. */
346 static const enum machine_registers decode_dpregs[] =
347 {
348 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
349 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
350 };
351
352 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
353
354 /* [dregs pregs]. */
355 static const enum machine_registers decode_gregs[] =
356 {
357 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
358 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
359 };
360
361 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
362
363 /* [dregs pregs (iregs mregs) (bregs lregs)]. */
364 static const enum machine_registers decode_regs[] =
365 {
366 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
367 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
368 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
369 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
370 };
371
372 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
373
374 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half]. */
375 static const enum machine_registers decode_regs_lo[] =
376 {
377 REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
378 REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
379 REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
380 REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
381 };
382
383 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
384 /* [dregs pregs (iregs mregs) (bregs lregs) High Half]. */
385 static const enum machine_registers decode_regs_hi[] =
386 {
387 REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
388 REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
389 REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
390 REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
391 };
392
393 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
394
395 static const enum machine_registers decode_statbits[] =
396 {
397 REG_AZ, REG_AN, REG_AC0_COPY, REG_V_COPY,
398 REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
399 REG_RND_MOD, REG_LASTREG, REG_LASTREG, REG_LASTREG,
400 REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
401 REG_AV0, REG_AV0S, REG_AV1, REG_AV1S,
402 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
403 REG_V, REG_VS, REG_LASTREG, REG_LASTREG,
404 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
405 };
406
407 #define statbits(x) REGNAME (decode_statbits[(x) & 31])
408
409 /* LC0 LC1. */
410 static const enum machine_registers decode_counters[] =
411 {
412 REG_LC0, REG_LC1,
413 };
414
415 #define counters(x) REGNAME (decode_counters[(x) & 1])
416 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
417
418 /* [dregs pregs (iregs mregs) (bregs lregs)
419 dregs2_sysregs1 open sysregs2 sysregs3]. */
420 static const enum machine_registers decode_allregs[] =
421 {
422 REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
423 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
424 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
425 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
426 REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
427 REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
428 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
429 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
430 REG_LASTREG,
431 };
432
433 #define IS_DREG(g,r) ((g) == 0 && (r) < 8)
434 #define IS_PREG(g,r) ((g) == 1 && (r) < 8)
435 #define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4)
436 #define IS_GENREG(g,r) ((((g) == 0 || (g) == 1) && (r) < 8) || IS_AREG (g, r))
437 #define IS_DAGREG(g,r) (((g) == 2 || (g) == 3) && (r) < 8)
438 #define IS_SYSREG(g,r) \
439 (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7)
440 #define IS_RESERVEDREG(g,r) \
441 (((r) > 7) || ((g) == 4 && ((r) == 4 || (r) == 5)) || (g) == 5)
442
443 #define allreg(r,g) (!IS_RESERVEDREG (g, r))
444 #define mostreg(r,g) (!(IS_DREG (g, r) || IS_PREG (g, r) || IS_RESERVEDREG (g, r)))
445
446 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
447 #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf)
448 #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf)
449 #define pcrel4(x) fmtconst (c_pcrel4, x, pc, outf)
450 #define pcrel8(x) fmtconst (c_pcrel8, x, pc, outf)
451 #define pcrel8s4(x) fmtconst (c_pcrel8s4, x, pc, outf)
452 #define pcrel10(x) fmtconst (c_pcrel10, x, pc, outf)
453 #define pcrel12(x) fmtconst (c_pcrel12, x, pc, outf)
454 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
455 #define rimm16(x) fmtconst (c_rimm16, x, 0, outf)
456 #define huimm16(x) fmtconst (c_huimm16, x, 0, outf)
457 #define imm16(x) fmtconst (c_imm16, x, 0, outf)
458 #define imm16d(x) fmtconst (c_imm16d, x, 0, outf)
459 #define uimm2(x) fmtconst (c_uimm2, x, 0, outf)
460 #define uimm3(x) fmtconst (c_uimm3, x, 0, outf)
461 #define luimm16(x) fmtconst (c_luimm16, x, 0, outf)
462 #define uimm4(x) fmtconst (c_uimm4, x, 0, outf)
463 #define uimm5(x) fmtconst (c_uimm5, x, 0, outf)
464 #define imm16s2(x) fmtconst (c_imm16s2, x, 0, outf)
465 #define uimm8(x) fmtconst (c_uimm8, x, 0, outf)
466 #define imm16s4(x) fmtconst (c_imm16s4, x, 0, outf)
467 #define uimm4s2(x) fmtconst (c_uimm4s2, x, 0, outf)
468 #define uimm4s4(x) fmtconst (c_uimm4s4, x, 0, outf)
469 #define uimm4s4d(x) fmtconst (c_uimm4s4d, x, 0, outf)
470 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
471 #define imm3(x) fmtconst (c_imm3, x, 0, outf)
472 #define imm4(x) fmtconst (c_imm4, x, 0, outf)
473 #define uimm8s4(x) fmtconst (c_uimm8s4, x, 0, outf)
474 #define imm5(x) fmtconst (c_imm5, x, 0, outf)
475 #define imm5d(x) fmtconst (c_imm5d, x, 0, outf)
476 #define imm6(x) fmtconst (c_imm6, x, 0, outf)
477 #define imm7(x) fmtconst (c_imm7, x, 0, outf)
478 #define imm7d(x) fmtconst (c_imm7d, x, 0, outf)
479 #define imm8(x) fmtconst (c_imm8, x, 0, outf)
480 #define pcrel24(x) fmtconst (c_pcrel24, x, pc, outf)
481 #define uimm16(x) fmtconst (c_uimm16, x, 0, outf)
482 #define uimm32(x) fmtconst (c_uimm32, x, 0, outf)
483 #define imm32(x) fmtconst (c_imm32, x, 0, outf)
484 #define huimm32(x) fmtconst (c_huimm32, x, 0, outf)
485 #define huimm32e(x) fmtconst (c_huimm32e, x, 0, outf)
486 #define imm7_val(x) fmtconst_val (c_imm7, x, 0)
487 #define imm16_val(x) fmtconst_val (c_uimm16, x, 0)
488 #define luimm16_val(x) fmtconst_val (c_luimm16, x, 0)
489
490 /* (arch.pm)arch_disassembler_functions. */
491 #ifndef OUTS
492 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
493 #endif
494
495 static void
496 amod0 (int s0, int x0, disassemble_info *outf)
497 {
498 if (s0 == 1 && x0 == 0)
499 OUTS (outf, " (S)");
500 else if (s0 == 0 && x0 == 1)
501 OUTS (outf, " (CO)");
502 else if (s0 == 1 && x0 == 1)
503 OUTS (outf, " (SCO)");
504 }
505
506 static void
507 amod1 (int s0, int x0, disassemble_info *outf)
508 {
509 if (s0 == 0 && x0 == 0)
510 OUTS (outf, " (NS)");
511 else if (s0 == 1 && x0 == 0)
512 OUTS (outf, " (S)");
513 }
514
515 static void
516 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
517 {
518 if (s0 == 1 && x0 == 0 && aop0 == 0)
519 OUTS (outf, " (S)");
520 else if (s0 == 0 && x0 == 1 && aop0 == 0)
521 OUTS (outf, " (CO)");
522 else if (s0 == 1 && x0 == 1 && aop0 == 0)
523 OUTS (outf, " (SCO)");
524 else if (s0 == 0 && x0 == 0 && aop0 == 2)
525 OUTS (outf, " (ASR)");
526 else if (s0 == 1 && x0 == 0 && aop0 == 2)
527 OUTS (outf, " (S, ASR)");
528 else if (s0 == 0 && x0 == 1 && aop0 == 2)
529 OUTS (outf, " (CO, ASR)");
530 else if (s0 == 1 && x0 == 1 && aop0 == 2)
531 OUTS (outf, " (SCO, ASR)");
532 else if (s0 == 0 && x0 == 0 && aop0 == 3)
533 OUTS (outf, " (ASL)");
534 else if (s0 == 1 && x0 == 0 && aop0 == 3)
535 OUTS (outf, " (S, ASL)");
536 else if (s0 == 0 && x0 == 1 && aop0 == 3)
537 OUTS (outf, " (CO, ASL)");
538 else if (s0 == 1 && x0 == 1 && aop0 == 3)
539 OUTS (outf, " (SCO, ASL)");
540 }
541
542 static void
543 searchmod (int r0, disassemble_info *outf)
544 {
545 if (r0 == 0)
546 OUTS (outf, "GT");
547 else if (r0 == 1)
548 OUTS (outf, "GE");
549 else if (r0 == 2)
550 OUTS (outf, "LT");
551 else if (r0 == 3)
552 OUTS (outf, "LE");
553 }
554
555 static void
556 aligndir (int r0, disassemble_info *outf)
557 {
558 if (r0 == 1)
559 OUTS (outf, " (R)");
560 }
561
562 static int
563 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
564 {
565 const char *s0, *s1;
566
567 if (h0)
568 s0 = dregs_hi (src0);
569 else
570 s0 = dregs_lo (src0);
571
572 if (h1)
573 s1 = dregs_hi (src1);
574 else
575 s1 = dregs_lo (src1);
576
577 OUTS (outf, s0);
578 OUTS (outf, " * ");
579 OUTS (outf, s1);
580 return 0;
581 }
582
583 static int
584 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
585 {
586 const char *a;
587 const char *sop = "<unknown op>";
588
589 if (which)
590 a = "A1";
591 else
592 a = "A0";
593
594 if (op == 3)
595 {
596 OUTS (outf, a);
597 return 0;
598 }
599
600 switch (op)
601 {
602 case 0: sop = " = "; break;
603 case 1: sop = " += "; break;
604 case 2: sop = " -= "; break;
605 default: break;
606 }
607
608 OUTS (outf, a);
609 OUTS (outf, sop);
610 decode_multfunc (h0, h1, src0, src1, outf);
611
612 return 0;
613 }
614
615 static void
616 decode_optmode (int mod, int MM, disassemble_info *outf)
617 {
618 if (mod == 0 && MM == 0)
619 return;
620
621 OUTS (outf, " (");
622
623 if (MM && !mod)
624 {
625 OUTS (outf, "M)");
626 return;
627 }
628
629 if (MM)
630 OUTS (outf, "M, ");
631
632 if (mod == M_S2RND)
633 OUTS (outf, "S2RND");
634 else if (mod == M_T)
635 OUTS (outf, "T");
636 else if (mod == M_W32)
637 OUTS (outf, "W32");
638 else if (mod == M_FU)
639 OUTS (outf, "FU");
640 else if (mod == M_TFU)
641 OUTS (outf, "TFU");
642 else if (mod == M_IS)
643 OUTS (outf, "IS");
644 else if (mod == M_ISS2)
645 OUTS (outf, "ISS2");
646 else if (mod == M_IH)
647 OUTS (outf, "IH");
648 else if (mod == M_IU)
649 OUTS (outf, "IU");
650 else
651 abort ();
652
653 OUTS (outf, ")");
654 }
655
656 struct saved_state
657 {
658 bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4];
659 bu32 a0x, a0w, a1x, a1w;
660 bu32 lt[2], lc[2], lb[2];
661 int ac0, ac0_copy, ac1, an, aq;
662 int av0, av0s, av1, av1s, az, cc, v, v_copy, vs;
663 int rnd_mod;
664 int v_internal;
665 bu32 pc, rets;
666
667 int ticks;
668 int insts;
669
670 int exception;
671
672 int end_of_registers;
673
674 int msize;
675 unsigned char *memory;
676 unsigned long bfd_mach;
677 } saved_state;
678
679 #define DREG(x) (saved_state.dpregs[x])
680 #define GREG(x,i) DPREG ((x) | (i << 3))
681 #define DPREG(x) (saved_state.dpregs[x])
682 #define DREG(x) (saved_state.dpregs[x])
683 #define PREG(x) (saved_state.dpregs[x + 8])
684 #define SPREG PREG (6)
685 #define FPREG PREG (7)
686 #define IREG(x) (saved_state.iregs[x])
687 #define MREG(x) (saved_state.mregs[x])
688 #define BREG(x) (saved_state.bregs[x])
689 #define LREG(x) (saved_state.lregs[x])
690 #define A0XREG (saved_state.a0x)
691 #define A0WREG (saved_state.a0w)
692 #define A1XREG (saved_state.a1x)
693 #define A1WREG (saved_state.a1w)
694 #define CCREG (saved_state.cc)
695 #define LC0REG (saved_state.lc[0])
696 #define LT0REG (saved_state.lt[0])
697 #define LB0REG (saved_state.lb[0])
698 #define LC1REG (saved_state.lc[1])
699 #define LT1REG (saved_state.lt[1])
700 #define LB1REG (saved_state.lb[1])
701 #define RETSREG (saved_state.rets)
702 #define PCREG (saved_state.pc)
703
704 static bu32 *
705 get_allreg (int grp, int reg)
706 {
707 int fullreg = (grp << 3) | reg;
708 /* REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
709 REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
710 REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
711 REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
712 REG_A0x, REG_A0w, REG_A1x, REG_A1w, , , REG_ASTAT, REG_RETS,
713 , , , , , , , ,
714 REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES,
715 REG_CYCLES2,
716 REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE,
717 REG_LASTREG */
718 switch (fullreg >> 2)
719 {
720 case 0: case 1: return &DREG (reg); break;
721 case 2: case 3: return &PREG (reg); break;
722 case 4: return &IREG (reg & 3); break;
723 case 5: return &MREG (reg & 3); break;
724 case 6: return &BREG (reg & 3); break;
725 case 7: return &LREG (reg & 3); break;
726 default:
727 switch (fullreg)
728 {
729 case 32: return &saved_state.a0x;
730 case 33: return &saved_state.a0w;
731 case 34: return &saved_state.a1x;
732 case 35: return &saved_state.a1w;
733 case 39: return &saved_state.rets;
734 case 48: return &LC0REG;
735 case 49: return &LT0REG;
736 case 50: return &LB0REG;
737 case 51: return &LC1REG;
738 case 52: return &LT1REG;
739 case 53: return &LB1REG;
740 }
741 return 0;
742 }
743 }
744
745 static int
746 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
747 {
748 /* ProgCtrl
749 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
750 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
751 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
752 int poprnd = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
753 int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
754
755 if (prgfunc == 0 && poprnd == 0)
756 OUTS (outf, "NOP");
757 else if (parallel)
758 return 0;
759 else if (prgfunc == 1 && poprnd == 0)
760 OUTS (outf, "RTS");
761 else if (prgfunc == 1 && poprnd == 1)
762 OUTS (outf, "RTI");
763 else if (prgfunc == 1 && poprnd == 2)
764 OUTS (outf, "RTX");
765 else if (prgfunc == 1 && poprnd == 3)
766 OUTS (outf, "RTN");
767 else if (prgfunc == 1 && poprnd == 4)
768 OUTS (outf, "RTE");
769 else if (prgfunc == 2 && poprnd == 0)
770 OUTS (outf, "IDLE");
771 else if (prgfunc == 2 && poprnd == 3)
772 OUTS (outf, "CSYNC");
773 else if (prgfunc == 2 && poprnd == 4)
774 OUTS (outf, "SSYNC");
775 else if (prgfunc == 2 && poprnd == 5)
776 OUTS (outf, "EMUEXCPT");
777 else if (prgfunc == 3 && IS_DREG (0, poprnd))
778 {
779 OUTS (outf, "CLI ");
780 OUTS (outf, dregs (poprnd));
781 }
782 else if (prgfunc == 4 && IS_DREG (0, poprnd))
783 {
784 OUTS (outf, "STI ");
785 OUTS (outf, dregs (poprnd));
786 }
787 else if (prgfunc == 5 && IS_PREG (1, poprnd))
788 {
789 OUTS (outf, "JUMP (");
790 OUTS (outf, pregs (poprnd));
791 OUTS (outf, ")");
792 }
793 else if (prgfunc == 6 && IS_PREG (1, poprnd))
794 {
795 OUTS (outf, "CALL (");
796 OUTS (outf, pregs (poprnd));
797 OUTS (outf, ")");
798 }
799 else if (prgfunc == 7 && IS_PREG (1, poprnd))
800 {
801 OUTS (outf, "CALL (PC + ");
802 OUTS (outf, pregs (poprnd));
803 OUTS (outf, ")");
804 }
805 else if (prgfunc == 8 && IS_PREG (1, poprnd))
806 {
807 OUTS (outf, "JUMP (PC + ");
808 OUTS (outf, pregs (poprnd));
809 OUTS (outf, ")");
810 }
811 else if (prgfunc == 9)
812 {
813 OUTS (outf, "RAISE ");
814 OUTS (outf, uimm4 (poprnd));
815 }
816 else if (prgfunc == 10)
817 {
818 OUTS (outf, "EXCPT ");
819 OUTS (outf, uimm4 (poprnd));
820 }
821 else if (prgfunc == 11 && IS_PREG (1, poprnd) && poprnd <= 5)
822 {
823 OUTS (outf, "TESTSET (");
824 OUTS (outf, pregs (poprnd));
825 OUTS (outf, ")");
826 }
827 else
828 return 0;
829 return 2;
830 }
831
832 static int
833 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
834 {
835 /* CaCTRL
836 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
837 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
838 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
839 int a = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
840 int op = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
841 int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
842
843 if (parallel)
844 return 0;
845
846 if (a == 0 && op == 0)
847 {
848 OUTS (outf, "PREFETCH[");
849 OUTS (outf, pregs (reg));
850 OUTS (outf, "]");
851 }
852 else if (a == 0 && op == 1)
853 {
854 OUTS (outf, "FLUSHINV[");
855 OUTS (outf, pregs (reg));
856 OUTS (outf, "]");
857 }
858 else if (a == 0 && op == 2)
859 {
860 OUTS (outf, "FLUSH[");
861 OUTS (outf, pregs (reg));
862 OUTS (outf, "]");
863 }
864 else if (a == 0 && op == 3)
865 {
866 OUTS (outf, "IFLUSH[");
867 OUTS (outf, pregs (reg));
868 OUTS (outf, "]");
869 }
870 else if (a == 1 && op == 0)
871 {
872 OUTS (outf, "PREFETCH[");
873 OUTS (outf, pregs (reg));
874 OUTS (outf, "++]");
875 }
876 else if (a == 1 && op == 1)
877 {
878 OUTS (outf, "FLUSHINV[");
879 OUTS (outf, pregs (reg));
880 OUTS (outf, "++]");
881 }
882 else if (a == 1 && op == 2)
883 {
884 OUTS (outf, "FLUSH[");
885 OUTS (outf, pregs (reg));
886 OUTS (outf, "++]");
887 }
888 else if (a == 1 && op == 3)
889 {
890 OUTS (outf, "IFLUSH[");
891 OUTS (outf, pregs (reg));
892 OUTS (outf, "++]");
893 }
894 else
895 return 0;
896 return 2;
897 }
898
899 static int
900 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
901 {
902 /* PushPopReg
903 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
904 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
905 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
906 int W = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
907 int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
908 int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
909
910 if (parallel)
911 return 0;
912
913 if (W == 0 && mostreg (reg, grp))
914 {
915 OUTS (outf, allregs (reg, grp));
916 OUTS (outf, " = [SP++]");
917 }
918 else if (W == 1 && allreg (reg, grp) && !(grp == 1 && reg == 6))
919 {
920 OUTS (outf, "[--SP] = ");
921 OUTS (outf, allregs (reg, grp));
922 }
923 else
924 return 0;
925 return 2;
926 }
927
928 static int
929 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
930 {
931 /* PushPopMultiple
932 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
933 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
934 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
935 int p = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
936 int d = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
937 int W = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
938 int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
939 int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
940
941 if (parallel)
942 return 0;
943
944 if (pr > 5)
945 return 0;
946
947 if (W == 1 && d == 1 && p == 1)
948 {
949 OUTS (outf, "[--SP] = (R7:");
950 OUTS (outf, imm5d (dr));
951 OUTS (outf, ", P5:");
952 OUTS (outf, imm5d (pr));
953 OUTS (outf, ")");
954 }
955 else if (W == 1 && d == 1 && p == 0 && pr == 0)
956 {
957 OUTS (outf, "[--SP] = (R7:");
958 OUTS (outf, imm5d (dr));
959 OUTS (outf, ")");
960 }
961 else if (W == 1 && d == 0 && p == 1 && dr == 0)
962 {
963 OUTS (outf, "[--SP] = (P5:");
964 OUTS (outf, imm5d (pr));
965 OUTS (outf, ")");
966 }
967 else if (W == 0 && d == 1 && p == 1)
968 {
969 OUTS (outf, "(R7:");
970 OUTS (outf, imm5d (dr));
971 OUTS (outf, ", P5:");
972 OUTS (outf, imm5d (pr));
973 OUTS (outf, ") = [SP++]");
974 }
975 else if (W == 0 && d == 1 && p == 0 && pr == 0)
976 {
977 OUTS (outf, "(R7:");
978 OUTS (outf, imm5d (dr));
979 OUTS (outf, ") = [SP++]");
980 }
981 else if (W == 0 && d == 0 && p == 1 && dr == 0)
982 {
983 OUTS (outf, "(P5:");
984 OUTS (outf, imm5d (pr));
985 OUTS (outf, ") = [SP++]");
986 }
987 else
988 return 0;
989 return 2;
990 }
991
992 static int
993 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
994 {
995 /* ccMV
996 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
997 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
998 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
999 int s = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
1000 int d = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
1001 int T = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
1002 int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
1003 int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
1004
1005 if (parallel)
1006 return 0;
1007
1008 if (T == 1)
1009 {
1010 OUTS (outf, "IF CC ");
1011 OUTS (outf, gregs (dst, d));
1012 OUTS (outf, " = ");
1013 OUTS (outf, gregs (src, s));
1014 }
1015 else if (T == 0)
1016 {
1017 OUTS (outf, "IF !CC ");
1018 OUTS (outf, gregs (dst, d));
1019 OUTS (outf, " = ");
1020 OUTS (outf, gregs (src, s));
1021 }
1022 else
1023 return 0;
1024 return 2;
1025 }
1026
1027 static int
1028 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
1029 {
1030 /* CCflag
1031 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1032 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1033 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1034 int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
1035 int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
1036 int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
1037 int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
1038 int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
1039
1040 if (parallel)
1041 return 0;
1042
1043 if (opc == 0 && I == 0 && G == 0)
1044 {
1045 OUTS (outf, "CC = ");
1046 OUTS (outf, dregs (x));
1047 OUTS (outf, " == ");
1048 OUTS (outf, dregs (y));
1049 }
1050 else if (opc == 1 && I == 0 && G == 0)
1051 {
1052 OUTS (outf, "CC = ");
1053 OUTS (outf, dregs (x));
1054 OUTS (outf, " < ");
1055 OUTS (outf, dregs (y));
1056 }
1057 else if (opc == 2 && I == 0 && G == 0)
1058 {
1059 OUTS (outf, "CC = ");
1060 OUTS (outf, dregs (x));
1061 OUTS (outf, " <= ");
1062 OUTS (outf, dregs (y));
1063 }
1064 else if (opc == 3 && I == 0 && G == 0)
1065 {
1066 OUTS (outf, "CC = ");
1067 OUTS (outf, dregs (x));
1068 OUTS (outf, " < ");
1069 OUTS (outf, dregs (y));
1070 OUTS (outf, " (IU)");
1071 }
1072 else if (opc == 4 && I == 0 && G == 0)
1073 {
1074 OUTS (outf, "CC = ");
1075 OUTS (outf, dregs (x));
1076 OUTS (outf, " <= ");
1077 OUTS (outf, dregs (y));
1078 OUTS (outf, " (IU)");
1079 }
1080 else if (opc == 0 && I == 1 && G == 0)
1081 {
1082 OUTS (outf, "CC = ");
1083 OUTS (outf, dregs (x));
1084 OUTS (outf, " == ");
1085 OUTS (outf, imm3 (y));
1086 }
1087 else if (opc == 1 && I == 1 && G == 0)
1088 {
1089 OUTS (outf, "CC = ");
1090 OUTS (outf, dregs (x));
1091 OUTS (outf, " < ");
1092 OUTS (outf, imm3 (y));
1093 }
1094 else if (opc == 2 && I == 1 && G == 0)
1095 {
1096 OUTS (outf, "CC = ");
1097 OUTS (outf, dregs (x));
1098 OUTS (outf, " <= ");
1099 OUTS (outf, imm3 (y));
1100 }
1101 else if (opc == 3 && I == 1 && G == 0)
1102 {
1103 OUTS (outf, "CC = ");
1104 OUTS (outf, dregs (x));
1105 OUTS (outf, " < ");
1106 OUTS (outf, uimm3 (y));
1107 OUTS (outf, " (IU)");
1108 }
1109 else if (opc == 4 && I == 1 && G == 0)
1110 {
1111 OUTS (outf, "CC = ");
1112 OUTS (outf, dregs (x));
1113 OUTS (outf, " <= ");
1114 OUTS (outf, uimm3 (y));
1115 OUTS (outf, " (IU)");
1116 }
1117 else if (opc == 0 && I == 0 && G == 1)
1118 {
1119 OUTS (outf, "CC = ");
1120 OUTS (outf, pregs (x));
1121 OUTS (outf, " == ");
1122 OUTS (outf, pregs (y));
1123 }
1124 else if (opc == 1 && I == 0 && G == 1)
1125 {
1126 OUTS (outf, "CC = ");
1127 OUTS (outf, pregs (x));
1128 OUTS (outf, " < ");
1129 OUTS (outf, pregs (y));
1130 }
1131 else if (opc == 2 && I == 0 && G == 1)
1132 {
1133 OUTS (outf, "CC = ");
1134 OUTS (outf, pregs (x));
1135 OUTS (outf, " <= ");
1136 OUTS (outf, pregs (y));
1137 }
1138 else if (opc == 3 && I == 0 && G == 1)
1139 {
1140 OUTS (outf, "CC = ");
1141 OUTS (outf, pregs (x));
1142 OUTS (outf, " < ");
1143 OUTS (outf, pregs (y));
1144 OUTS (outf, " (IU)");
1145 }
1146 else if (opc == 4 && I == 0 && G == 1)
1147 {
1148 OUTS (outf, "CC = ");
1149 OUTS (outf, pregs (x));
1150 OUTS (outf, " <= ");
1151 OUTS (outf, pregs (y));
1152 OUTS (outf, " (IU)");
1153 }
1154 else if (opc == 0 && I == 1 && G == 1)
1155 {
1156 OUTS (outf, "CC = ");
1157 OUTS (outf, pregs (x));
1158 OUTS (outf, " == ");
1159 OUTS (outf, imm3 (y));
1160 }
1161 else if (opc == 1 && I == 1 && G == 1)
1162 {
1163 OUTS (outf, "CC = ");
1164 OUTS (outf, pregs (x));
1165 OUTS (outf, " < ");
1166 OUTS (outf, imm3 (y));
1167 }
1168 else if (opc == 2 && I == 1 && G == 1)
1169 {
1170 OUTS (outf, "CC = ");
1171 OUTS (outf, pregs (x));
1172 OUTS (outf, " <= ");
1173 OUTS (outf, imm3 (y));
1174 }
1175 else if (opc == 3 && I == 1 && G == 1)
1176 {
1177 OUTS (outf, "CC = ");
1178 OUTS (outf, pregs (x));
1179 OUTS (outf, " < ");
1180 OUTS (outf, uimm3 (y));
1181 OUTS (outf, " (IU)");
1182 }
1183 else if (opc == 4 && I == 1 && G == 1)
1184 {
1185 OUTS (outf, "CC = ");
1186 OUTS (outf, pregs (x));
1187 OUTS (outf, " <= ");
1188 OUTS (outf, uimm3 (y));
1189 OUTS (outf, " (IU)");
1190 }
1191 else if (opc == 5 && I == 0 && G == 0 && x == 0 && y == 0)
1192 OUTS (outf, "CC = A0 == A1");
1193
1194 else if (opc == 6 && I == 0 && G == 0 && x == 0 && y == 0)
1195 OUTS (outf, "CC = A0 < A1");
1196
1197 else if (opc == 7 && I == 0 && G == 0 && x == 0 && y == 0)
1198 OUTS (outf, "CC = A0 <= A1");
1199
1200 else
1201 return 0;
1202 return 2;
1203 }
1204
1205 static int
1206 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
1207 {
1208 /* CC2dreg
1209 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1210 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1211 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1212 int op = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
1213 int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
1214
1215 if (parallel)
1216 return 0;
1217
1218 if (op == 0)
1219 {
1220 OUTS (outf, dregs (reg));
1221 OUTS (outf, " = CC");
1222 }
1223 else if (op == 1)
1224 {
1225 OUTS (outf, "CC = ");
1226 OUTS (outf, dregs (reg));
1227 }
1228 else if (op == 3 && reg == 0)
1229 OUTS (outf, "CC = !CC");
1230 else
1231 return 0;
1232
1233 return 2;
1234 }
1235
1236 static int
1237 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
1238 {
1239 /* CC2stat
1240 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1241 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1242 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1243 int D = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
1244 int op = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
1245 int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
1246
1247 const char *bitname = statbits (cbit);
1248
1249 if (parallel)
1250 return 0;
1251
1252 if (decode_statbits[cbit] == REG_LASTREG)
1253 {
1254 /* All ASTAT bits except CC may be operated on in hardware, but may
1255 not have a dedicated insn, so still decode "valid" insns. */
1256 static char bitnames[64];
1257 if (cbit != 5)
1258 sprintf (bitnames, "ASTAT[%i /* unused bit */]", cbit);
1259 else
1260 return 0;
1261
1262 bitname = bitnames;
1263 }
1264
1265 if (op == 0 && D == 0)
1266 {
1267 OUTS (outf, "CC = ");
1268 OUTS (outf, bitname);
1269 }
1270 else if (op == 1 && D == 0)
1271 {
1272 OUTS (outf, "CC |= ");
1273 OUTS (outf, bitname);
1274 }
1275 else if (op == 2 && D == 0)
1276 {
1277 OUTS (outf, "CC &= ");
1278 OUTS (outf, bitname);
1279 }
1280 else if (op == 3 && D == 0)
1281 {
1282 OUTS (outf, "CC ^= ");
1283 OUTS (outf, bitname);
1284 }
1285 else if (op == 0 && D == 1)
1286 {
1287 OUTS (outf, bitname);
1288 OUTS (outf, " = CC");
1289 }
1290 else if (op == 1 && D == 1)
1291 {
1292 OUTS (outf, bitname);
1293 OUTS (outf, " |= CC");
1294 }
1295 else if (op == 2 && D == 1)
1296 {
1297 OUTS (outf, bitname);
1298 OUTS (outf, " &= CC");
1299 }
1300 else if (op == 3 && D == 1)
1301 {
1302 OUTS (outf, bitname);
1303 OUTS (outf, " ^= CC");
1304 }
1305 else
1306 return 0;
1307
1308 return 2;
1309 }
1310
1311 static int
1312 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1313 {
1314 /* BRCC
1315 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1316 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
1317 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1318 int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
1319 int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
1320 int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
1321
1322 if (parallel)
1323 return 0;
1324
1325 if (T == 1 && B == 1)
1326 {
1327 OUTS (outf, "IF CC JUMP 0x");
1328 OUTS (outf, pcrel10 (offset));
1329 OUTS (outf, " (BP)");
1330 }
1331 else if (T == 0 && B == 1)
1332 {
1333 OUTS (outf, "IF !CC JUMP 0x");
1334 OUTS (outf, pcrel10 (offset));
1335 OUTS (outf, " (BP)");
1336 }
1337 else if (T == 1)
1338 {
1339 OUTS (outf, "IF CC JUMP 0x");
1340 OUTS (outf, pcrel10 (offset));
1341 }
1342 else if (T == 0)
1343 {
1344 OUTS (outf, "IF !CC JUMP 0x");
1345 OUTS (outf, pcrel10 (offset));
1346 }
1347 else
1348 return 0;
1349
1350 return 2;
1351 }
1352
1353 static int
1354 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
1355 {
1356 /* UJUMP
1357 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1358 | 0 | 0 | 1 | 0 |.offset........................................|
1359 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1360 int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
1361
1362 if (parallel)
1363 return 0;
1364
1365 OUTS (outf, "JUMP.S 0x");
1366 OUTS (outf, pcrel12 (offset));
1367 return 2;
1368 }
1369
1370 static int
1371 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
1372 {
1373 /* REGMV
1374 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1375 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1376 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1377 int gs = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
1378 int gd = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
1379 int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
1380 int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
1381
1382 /* Reserved slots cannot be a src/dst. */
1383 if (IS_RESERVEDREG (gs, src) || IS_RESERVEDREG (gd, dst))
1384 goto invalid_move;
1385
1386 /* Standard register moves */
1387 if ((gs < 2) || /* Dregs/Pregs as source */
1388 (gd < 2) || /* Dregs/Pregs as dest */
1389 (gs == 4 && src < 4) || /* Accumulators as source */
1390 (gd == 4 && dst < 4 && (gs < 4)) || /* Accumulators as dest */
1391 (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) || /* EMUDAT as src */
1392 (gd == 7 && dst == 7)) /* EMUDAT as dest */
1393 goto valid_move;
1394
1395 /* dareg = dareg (IMBL) */
1396 if (gs < 4 && gd < 4)
1397 goto valid_move;
1398
1399 /* USP can be src to sysregs, but not dagregs. */
1400 if ((gs == 7 && src == 0) && (gd >= 4))
1401 goto valid_move;
1402
1403 /* USP can move between genregs (only check Accumulators). */
1404 if (((gs == 7 && src == 0) && (gd == 4 && dst < 4)) ||
1405 ((gd == 7 && dst == 0) && (gs == 4 && src < 4)))
1406 goto valid_move;
1407
1408 /* Still here ? Invalid reg pair. */
1409 invalid_move:
1410 return 0;
1411
1412 valid_move:
1413 OUTS (outf, allregs (dst, gd));
1414 OUTS (outf, " = ");
1415 OUTS (outf, allregs (src, gs));
1416 return 2;
1417 }
1418
1419 static int
1420 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
1421 {
1422 /* ALU2op
1423 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1424 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
1425 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1426 int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
1427 int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
1428 int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
1429
1430 if (opc == 0)
1431 {
1432 OUTS (outf, dregs (dst));
1433 OUTS (outf, " >>>= ");
1434 OUTS (outf, dregs (src));
1435 }
1436 else if (opc == 1)
1437 {
1438 OUTS (outf, dregs (dst));
1439 OUTS (outf, " >>= ");
1440 OUTS (outf, dregs (src));
1441 }
1442 else if (opc == 2)
1443 {
1444 OUTS (outf, dregs (dst));
1445 OUTS (outf, " <<= ");
1446 OUTS (outf, dregs (src));
1447 }
1448 else if (opc == 3)
1449 {
1450 OUTS (outf, dregs (dst));
1451 OUTS (outf, " *= ");
1452 OUTS (outf, dregs (src));
1453 }
1454 else if (opc == 4)
1455 {
1456 OUTS (outf, dregs (dst));
1457 OUTS (outf, " = (");
1458 OUTS (outf, dregs (dst));
1459 OUTS (outf, " + ");
1460 OUTS (outf, dregs (src));
1461 OUTS (outf, ") << 0x1");
1462 }
1463 else if (opc == 5)
1464 {
1465 OUTS (outf, dregs (dst));
1466 OUTS (outf, " = (");
1467 OUTS (outf, dregs (dst));
1468 OUTS (outf, " + ");
1469 OUTS (outf, dregs (src));
1470 OUTS (outf, ") << 0x2");
1471 }
1472 else if (opc == 8)
1473 {
1474 OUTS (outf, "DIVQ (");
1475 OUTS (outf, dregs (dst));
1476 OUTS (outf, ", ");
1477 OUTS (outf, dregs (src));
1478 OUTS (outf, ")");
1479 }
1480 else if (opc == 9)
1481 {
1482 OUTS (outf, "DIVS (");
1483 OUTS (outf, dregs (dst));
1484 OUTS (outf, ", ");
1485 OUTS (outf, dregs (src));
1486 OUTS (outf, ")");
1487 }
1488 else if (opc == 10)
1489 {
1490 OUTS (outf, dregs (dst));
1491 OUTS (outf, " = ");
1492 OUTS (outf, dregs_lo (src));
1493 OUTS (outf, " (X)");
1494 }
1495 else if (opc == 11)
1496 {
1497 OUTS (outf, dregs (dst));
1498 OUTS (outf, " = ");
1499 OUTS (outf, dregs_lo (src));
1500 OUTS (outf, " (Z)");
1501 }
1502 else if (opc == 12)
1503 {
1504 OUTS (outf, dregs (dst));
1505 OUTS (outf, " = ");
1506 OUTS (outf, dregs_byte (src));
1507 OUTS (outf, " (X)");
1508 }
1509 else if (opc == 13)
1510 {
1511 OUTS (outf, dregs (dst));
1512 OUTS (outf, " = ");
1513 OUTS (outf, dregs_byte (src));
1514 OUTS (outf, " (Z)");
1515 }
1516 else if (opc == 14)
1517 {
1518 OUTS (outf, dregs (dst));
1519 OUTS (outf, " = -");
1520 OUTS (outf, dregs (src));
1521 }
1522 else if (opc == 15)
1523 {
1524 OUTS (outf, dregs (dst));
1525 OUTS (outf, " =~ ");
1526 OUTS (outf, dregs (src));
1527 }
1528 else
1529 return 0;
1530
1531 return 2;
1532 }
1533
1534 static int
1535 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
1536 {
1537 /* PTR2op
1538 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1539 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1540 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1541 int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
1542 int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
1543 int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
1544
1545 if (opc == 0)
1546 {
1547 OUTS (outf, pregs (dst));
1548 OUTS (outf, " -= ");
1549 OUTS (outf, pregs (src));
1550 }
1551 else if (opc == 1)
1552 {
1553 OUTS (outf, pregs (dst));
1554 OUTS (outf, " = ");
1555 OUTS (outf, pregs (src));
1556 OUTS (outf, " << 0x2");
1557 }
1558 else if (opc == 3)
1559 {
1560 OUTS (outf, pregs (dst));
1561 OUTS (outf, " = ");
1562 OUTS (outf, pregs (src));
1563 OUTS (outf, " >> 0x2");
1564 }
1565 else if (opc == 4)
1566 {
1567 OUTS (outf, pregs (dst));
1568 OUTS (outf, " = ");
1569 OUTS (outf, pregs (src));
1570 OUTS (outf, " >> 0x1");
1571 }
1572 else if (opc == 5)
1573 {
1574 OUTS (outf, pregs (dst));
1575 OUTS (outf, " += ");
1576 OUTS (outf, pregs (src));
1577 OUTS (outf, " (BREV)");
1578 }
1579 else if (opc == 6)
1580 {
1581 OUTS (outf, pregs (dst));
1582 OUTS (outf, " = (");
1583 OUTS (outf, pregs (dst));
1584 OUTS (outf, " + ");
1585 OUTS (outf, pregs (src));
1586 OUTS (outf, ") << 0x1");
1587 }
1588 else if (opc == 7)
1589 {
1590 OUTS (outf, pregs (dst));
1591 OUTS (outf, " = (");
1592 OUTS (outf, pregs (dst));
1593 OUTS (outf, " + ");
1594 OUTS (outf, pregs (src));
1595 OUTS (outf, ") << 0x2");
1596 }
1597 else
1598 return 0;
1599
1600 return 2;
1601 }
1602
1603 static int
1604 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
1605 {
1606 /* LOGI2op
1607 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1608 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
1609 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1610 int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
1611 int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
1612 int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
1613
1614 if (parallel)
1615 return 0;
1616
1617 if (opc == 0)
1618 {
1619 OUTS (outf, "CC = !BITTST (");
1620 OUTS (outf, dregs (dst));
1621 OUTS (outf, ", ");
1622 OUTS (outf, uimm5 (src));
1623 OUTS (outf, ");\t\t/* bit");
1624 OUTS (outf, imm7d (src));
1625 OUTS (outf, " */");
1626 comment = 1;
1627 }
1628 else if (opc == 1)
1629 {
1630 OUTS (outf, "CC = BITTST (");
1631 OUTS (outf, dregs (dst));
1632 OUTS (outf, ", ");
1633 OUTS (outf, uimm5 (src));
1634 OUTS (outf, ");\t\t/* bit");
1635 OUTS (outf, imm7d (src));
1636 OUTS (outf, " */");
1637 comment = 1;
1638 }
1639 else if (opc == 2)
1640 {
1641 OUTS (outf, "BITSET (");
1642 OUTS (outf, dregs (dst));
1643 OUTS (outf, ", ");
1644 OUTS (outf, uimm5 (src));
1645 OUTS (outf, ");\t\t/* bit");
1646 OUTS (outf, imm7d (src));
1647 OUTS (outf, " */");
1648 comment = 1;
1649 }
1650 else if (opc == 3)
1651 {
1652 OUTS (outf, "BITTGL (");
1653 OUTS (outf, dregs (dst));
1654 OUTS (outf, ", ");
1655 OUTS (outf, uimm5 (src));
1656 OUTS (outf, ");\t\t/* bit");
1657 OUTS (outf, imm7d (src));
1658 OUTS (outf, " */");
1659 comment = 1;
1660 }
1661 else if (opc == 4)
1662 {
1663 OUTS (outf, "BITCLR (");
1664 OUTS (outf, dregs (dst));
1665 OUTS (outf, ", ");
1666 OUTS (outf, uimm5 (src));
1667 OUTS (outf, ");\t\t/* bit");
1668 OUTS (outf, imm7d (src));
1669 OUTS (outf, " */");
1670 comment = 1;
1671 }
1672 else if (opc == 5)
1673 {
1674 OUTS (outf, dregs (dst));
1675 OUTS (outf, " >>>= ");
1676 OUTS (outf, uimm5 (src));
1677 }
1678 else if (opc == 6)
1679 {
1680 OUTS (outf, dregs (dst));
1681 OUTS (outf, " >>= ");
1682 OUTS (outf, uimm5 (src));
1683 }
1684 else if (opc == 7)
1685 {
1686 OUTS (outf, dregs (dst));
1687 OUTS (outf, " <<= ");
1688 OUTS (outf, uimm5 (src));
1689 }
1690 else
1691 return 0;
1692
1693 return 2;
1694 }
1695
1696 static int
1697 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
1698 {
1699 /* COMP3op
1700 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1701 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1702 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1703 int opc = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
1704 int dst = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
1705 int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
1706 int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
1707
1708 if (opc == 5 && src1 == src0)
1709 {
1710 OUTS (outf, pregs (dst));
1711 OUTS (outf, " = ");
1712 OUTS (outf, pregs (src0));
1713 OUTS (outf, " << 0x1");
1714 }
1715 else if (opc == 1)
1716 {
1717 OUTS (outf, dregs (dst));
1718 OUTS (outf, " = ");
1719 OUTS (outf, dregs (src0));
1720 OUTS (outf, " - ");
1721 OUTS (outf, dregs (src1));
1722 }
1723 else if (opc == 2)
1724 {
1725 OUTS (outf, dregs (dst));
1726 OUTS (outf, " = ");
1727 OUTS (outf, dregs (src0));
1728 OUTS (outf, " & ");
1729 OUTS (outf, dregs (src1));
1730 }
1731 else if (opc == 3)
1732 {
1733 OUTS (outf, dregs (dst));
1734 OUTS (outf, " = ");
1735 OUTS (outf, dregs (src0));
1736 OUTS (outf, " | ");
1737 OUTS (outf, dregs (src1));
1738 }
1739 else if (opc == 4)
1740 {
1741 OUTS (outf, dregs (dst));
1742 OUTS (outf, " = ");
1743 OUTS (outf, dregs (src0));
1744 OUTS (outf, " ^ ");
1745 OUTS (outf, dregs (src1));
1746 }
1747 else if (opc == 5)
1748 {
1749 OUTS (outf, pregs (dst));
1750 OUTS (outf, " = ");
1751 OUTS (outf, pregs (src0));
1752 OUTS (outf, " + ");
1753 OUTS (outf, pregs (src1));
1754 }
1755 else if (opc == 6)
1756 {
1757 OUTS (outf, pregs (dst));
1758 OUTS (outf, " = ");
1759 OUTS (outf, pregs (src0));
1760 OUTS (outf, " + (");
1761 OUTS (outf, pregs (src1));
1762 OUTS (outf, " << 0x1)");
1763 }
1764 else if (opc == 7)
1765 {
1766 OUTS (outf, pregs (dst));
1767 OUTS (outf, " = ");
1768 OUTS (outf, pregs (src0));
1769 OUTS (outf, " + (");
1770 OUTS (outf, pregs (src1));
1771 OUTS (outf, " << 0x2)");
1772 }
1773 else if (opc == 0)
1774 {
1775 OUTS (outf, dregs (dst));
1776 OUTS (outf, " = ");
1777 OUTS (outf, dregs (src0));
1778 OUTS (outf, " + ");
1779 OUTS (outf, dregs (src1));
1780 }
1781 else
1782 return 0;
1783
1784 return 2;
1785 }
1786
1787 static int
1788 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
1789 {
1790 /* COMPI2opD
1791 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1792 | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
1793 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1794 int op = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
1795 int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
1796 int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
1797
1798 bu32 *pval = get_allreg (0, dst);
1799
1800 if (parallel)
1801 return 0;
1802
1803 /* Since we don't have 32-bit immediate loads, we allow the disassembler
1804 to combine them, so it prints out the right values.
1805 Here we keep track of the registers. */
1806 if (op == 0)
1807 {
1808 *pval = imm7_val (src);
1809 if (src & 0x40)
1810 *pval |= 0xFFFFFF80;
1811 else
1812 *pval &= 0x7F;
1813 }
1814
1815 if (op == 0)
1816 {
1817 OUTS (outf, dregs (dst));
1818 OUTS (outf, " = ");
1819 OUTS (outf, imm7 (src));
1820 OUTS (outf, " (X);\t\t/*\t\t");
1821 OUTS (outf, dregs (dst));
1822 OUTS (outf, "=");
1823 OUTS (outf, uimm32 (*pval));
1824 OUTS (outf, "(");
1825 OUTS (outf, imm32 (*pval));
1826 OUTS (outf, ") */");
1827 comment = 1;
1828 }
1829 else if (op == 1)
1830 {
1831 OUTS (outf, dregs (dst));
1832 OUTS (outf, " += ");
1833 OUTS (outf, imm7 (src));
1834 OUTS (outf, ";\t\t/* (");
1835 OUTS (outf, imm7d (src));
1836 OUTS (outf, ") */");
1837 comment = 1;
1838 }
1839 else
1840 return 0;
1841
1842 return 2;
1843 }
1844
1845 static int
1846 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
1847 {
1848 /* COMPI2opP
1849 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1850 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1851 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1852 int op = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
1853 int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
1854 int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
1855
1856 bu32 *pval = get_allreg (1, dst);
1857
1858 if (parallel)
1859 return 0;
1860
1861 if (op == 0)
1862 {
1863 *pval = imm7_val (src);
1864 if (src & 0x40)
1865 *pval |= 0xFFFFFF80;
1866 else
1867 *pval &= 0x7F;
1868 }
1869
1870 if (op == 0)
1871 {
1872 OUTS (outf, pregs (dst));
1873 OUTS (outf, " = ");
1874 OUTS (outf, imm7 (src));
1875 OUTS (outf, " (X);\t\t/*\t\t");
1876 OUTS (outf, pregs (dst));
1877 OUTS (outf, "=");
1878 OUTS (outf, uimm32 (*pval));
1879 OUTS (outf, "(");
1880 OUTS (outf, imm32 (*pval));
1881 OUTS (outf, ") */");
1882 comment = 1;
1883 }
1884 else if (op == 1)
1885 {
1886 OUTS (outf, pregs (dst));
1887 OUTS (outf, " += ");
1888 OUTS (outf, imm7 (src));
1889 OUTS (outf, ";\t\t/* (");
1890 OUTS (outf, imm7d (src));
1891 OUTS (outf, ") */");
1892 comment = 1;
1893 }
1894 else
1895 return 0;
1896
1897 return 2;
1898 }
1899
1900 static int
1901 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
1902 {
1903 /* LDSTpmod
1904 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1905 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
1906 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
1907 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
1908 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
1909 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
1910 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
1911 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
1912
1913 if (aop == 1 && W == 0 && idx == ptr)
1914 {
1915 OUTS (outf, dregs_lo (reg));
1916 OUTS (outf, " = W[");
1917 OUTS (outf, pregs (ptr));
1918 OUTS (outf, "]");
1919 }
1920 else if (aop == 2 && W == 0 && idx == ptr)
1921 {
1922 OUTS (outf, dregs_hi (reg));
1923 OUTS (outf, " = W[");
1924 OUTS (outf, pregs (ptr));
1925 OUTS (outf, "]");
1926 }
1927 else if (aop == 1 && W == 1 && idx == ptr)
1928 {
1929 OUTS (outf, "W[");
1930 OUTS (outf, pregs (ptr));
1931 OUTS (outf, "] = ");
1932 OUTS (outf, dregs_lo (reg));
1933 }
1934 else if (aop == 2 && W == 1 && idx == ptr)
1935 {
1936 OUTS (outf, "W[");
1937 OUTS (outf, pregs (ptr));
1938 OUTS (outf, "] = ");
1939 OUTS (outf, dregs_hi (reg));
1940 }
1941 else if (aop == 0 && W == 0)
1942 {
1943 OUTS (outf, dregs (reg));
1944 OUTS (outf, " = [");
1945 OUTS (outf, pregs (ptr));
1946 OUTS (outf, " ++ ");
1947 OUTS (outf, pregs (idx));
1948 OUTS (outf, "]");
1949 }
1950 else if (aop == 1 && W == 0)
1951 {
1952 OUTS (outf, dregs_lo (reg));
1953 OUTS (outf, " = W[");
1954 OUTS (outf, pregs (ptr));
1955 OUTS (outf, " ++ ");
1956 OUTS (outf, pregs (idx));
1957 OUTS (outf, "]");
1958 }
1959 else if (aop == 2 && W == 0)
1960 {
1961 OUTS (outf, dregs_hi (reg));
1962 OUTS (outf, " = W[");
1963 OUTS (outf, pregs (ptr));
1964 OUTS (outf, " ++ ");
1965 OUTS (outf, pregs (idx));
1966 OUTS (outf, "]");
1967 }
1968 else if (aop == 3 && W == 0)
1969 {
1970 OUTS (outf, dregs (reg));
1971 OUTS (outf, " = W[");
1972 OUTS (outf, pregs (ptr));
1973 OUTS (outf, " ++ ");
1974 OUTS (outf, pregs (idx));
1975 OUTS (outf, "] (Z)");
1976 }
1977 else if (aop == 3 && W == 1)
1978 {
1979 OUTS (outf, dregs (reg));
1980 OUTS (outf, " = W[");
1981 OUTS (outf, pregs (ptr));
1982 OUTS (outf, " ++ ");
1983 OUTS (outf, pregs (idx));
1984 OUTS (outf, "] (X)");
1985 }
1986 else if (aop == 0 && W == 1)
1987 {
1988 OUTS (outf, "[");
1989 OUTS (outf, pregs (ptr));
1990 OUTS (outf, " ++ ");
1991 OUTS (outf, pregs (idx));
1992 OUTS (outf, "] = ");
1993 OUTS (outf, dregs (reg));
1994 }
1995 else if (aop == 1 && W == 1)
1996 {
1997 OUTS (outf, "W[");
1998 OUTS (outf, pregs (ptr));
1999 OUTS (outf, " ++ ");
2000 OUTS (outf, pregs (idx));
2001 OUTS (outf, "] = ");
2002 OUTS (outf, dregs_lo (reg));
2003 }
2004 else if (aop == 2 && W == 1)
2005 {
2006 OUTS (outf, "W[");
2007 OUTS (outf, pregs (ptr));
2008 OUTS (outf, " ++ ");
2009 OUTS (outf, pregs (idx));
2010 OUTS (outf, "] = ");
2011 OUTS (outf, dregs_hi (reg));
2012 }
2013 else
2014 return 0;
2015
2016 return 2;
2017 }
2018
2019 static int
2020 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
2021 {
2022 /* dagMODim
2023 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2024 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2025 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2026 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2027 int m = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
2028 int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
2029 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2030
2031 if (op == 0 && br == 1)
2032 {
2033 OUTS (outf, iregs (i));
2034 OUTS (outf, " += ");
2035 OUTS (outf, mregs (m));
2036 OUTS (outf, " (BREV)");
2037 }
2038 else if (op == 0)
2039 {
2040 OUTS (outf, iregs (i));
2041 OUTS (outf, " += ");
2042 OUTS (outf, mregs (m));
2043 }
2044 else if (op == 1 && br == 0)
2045 {
2046 OUTS (outf, iregs (i));
2047 OUTS (outf, " -= ");
2048 OUTS (outf, mregs (m));
2049 }
2050 else
2051 return 0;
2052
2053 return 2;
2054 }
2055
2056 static int
2057 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
2058 {
2059 /* dagMODik
2060 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2061 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2062 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2063 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2064 int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
2065
2066 if (op == 0)
2067 {
2068 OUTS (outf, iregs (i));
2069 OUTS (outf, " += 0x2");
2070 }
2071 else if (op == 1)
2072 {
2073 OUTS (outf, iregs (i));
2074 OUTS (outf, " -= 0x2");
2075 }
2076 else if (op == 2)
2077 {
2078 OUTS (outf, iregs (i));
2079 OUTS (outf, " += 0x4");
2080 }
2081 else if (op == 3)
2082 {
2083 OUTS (outf, iregs (i));
2084 OUTS (outf, " -= 0x4");
2085 }
2086 else
2087 return 0;
2088
2089 if (! parallel )
2090 {
2091 OUTS (outf, ";\t\t/* ( ");
2092 if (op == 0 || op == 1)
2093 OUTS (outf, "2");
2094 else if (op == 2 || op == 3)
2095 OUTS (outf, "4");
2096 OUTS (outf, ") */");
2097 comment = 1;
2098 }
2099
2100 return 2;
2101 }
2102
2103 static int
2104 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
2105 {
2106 /* dspLDST
2107 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2108 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2109 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2110 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2111 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2112 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2113 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2114 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2115
2116 if (aop == 0 && W == 0 && m == 0)
2117 {
2118 OUTS (outf, dregs (reg));
2119 OUTS (outf, " = [");
2120 OUTS (outf, iregs (i));
2121 OUTS (outf, "++]");
2122 }
2123 else if (aop == 0 && W == 0 && m == 1)
2124 {
2125 OUTS (outf, dregs_lo (reg));
2126 OUTS (outf, " = W[");
2127 OUTS (outf, iregs (i));
2128 OUTS (outf, "++]");
2129 }
2130 else if (aop == 0 && W == 0 && m == 2)
2131 {
2132 OUTS (outf, dregs_hi (reg));
2133 OUTS (outf, " = W[");
2134 OUTS (outf, iregs (i));
2135 OUTS (outf, "++]");
2136 }
2137 else if (aop == 1 && W == 0 && m == 0)
2138 {
2139 OUTS (outf, dregs (reg));
2140 OUTS (outf, " = [");
2141 OUTS (outf, iregs (i));
2142 OUTS (outf, "--]");
2143 }
2144 else if (aop == 1 && W == 0 && m == 1)
2145 {
2146 OUTS (outf, dregs_lo (reg));
2147 OUTS (outf, " = W[");
2148 OUTS (outf, iregs (i));
2149 OUTS (outf, "--]");
2150 }
2151 else if (aop == 1 && W == 0 && m == 2)
2152 {
2153 OUTS (outf, dregs_hi (reg));
2154 OUTS (outf, " = W[");
2155 OUTS (outf, iregs (i));
2156 OUTS (outf, "--]");
2157 }
2158 else if (aop == 2 && W == 0 && m == 0)
2159 {
2160 OUTS (outf, dregs (reg));
2161 OUTS (outf, " = [");
2162 OUTS (outf, iregs (i));
2163 OUTS (outf, "]");
2164 }
2165 else if (aop == 2 && W == 0 && m == 1)
2166 {
2167 OUTS (outf, dregs_lo (reg));
2168 OUTS (outf, " = W[");
2169 OUTS (outf, iregs (i));
2170 OUTS (outf, "]");
2171 }
2172 else if (aop == 2 && W == 0 && m == 2)
2173 {
2174 OUTS (outf, dregs_hi (reg));
2175 OUTS (outf, " = W[");
2176 OUTS (outf, iregs (i));
2177 OUTS (outf, "]");
2178 }
2179 else if (aop == 0 && W == 1 && m == 0)
2180 {
2181 OUTS (outf, "[");
2182 OUTS (outf, iregs (i));
2183 OUTS (outf, "++] = ");
2184 OUTS (outf, dregs (reg));
2185 }
2186 else if (aop == 0 && W == 1 && m == 1)
2187 {
2188 OUTS (outf, "W[");
2189 OUTS (outf, iregs (i));
2190 OUTS (outf, "++] = ");
2191 OUTS (outf, dregs_lo (reg));
2192 }
2193 else if (aop == 0 && W == 1 && m == 2)
2194 {
2195 OUTS (outf, "W[");
2196 OUTS (outf, iregs (i));
2197 OUTS (outf, "++] = ");
2198 OUTS (outf, dregs_hi (reg));
2199 }
2200 else if (aop == 1 && W == 1 && m == 0)
2201 {
2202 OUTS (outf, "[");
2203 OUTS (outf, iregs (i));
2204 OUTS (outf, "--] = ");
2205 OUTS (outf, dregs (reg));
2206 }
2207 else if (aop == 1 && W == 1 && m == 1)
2208 {
2209 OUTS (outf, "W[");
2210 OUTS (outf, iregs (i));
2211 OUTS (outf, "--] = ");
2212 OUTS (outf, dregs_lo (reg));
2213 }
2214 else if (aop == 1 && W == 1 && m == 2)
2215 {
2216 OUTS (outf, "W[");
2217 OUTS (outf, iregs (i));
2218 OUTS (outf, "--] = ");
2219 OUTS (outf, dregs_hi (reg));
2220 }
2221 else if (aop == 2 && W == 1 && m == 0)
2222 {
2223 OUTS (outf, "[");
2224 OUTS (outf, iregs (i));
2225 OUTS (outf, "] = ");
2226 OUTS (outf, dregs (reg));
2227 }
2228 else if (aop == 2 && W == 1 && m == 1)
2229 {
2230 OUTS (outf, "W[");
2231 OUTS (outf, iregs (i));
2232 OUTS (outf, "] = ");
2233 OUTS (outf, dregs_lo (reg));
2234 }
2235 else if (aop == 2 && W == 1 && m == 2)
2236 {
2237 OUTS (outf, "W[");
2238 OUTS (outf, iregs (i));
2239 OUTS (outf, "] = ");
2240 OUTS (outf, dregs_hi (reg));
2241 }
2242 else if (aop == 3 && W == 0)
2243 {
2244 OUTS (outf, dregs (reg));
2245 OUTS (outf, " = [");
2246 OUTS (outf, iregs (i));
2247 OUTS (outf, " ++ ");
2248 OUTS (outf, mregs (m));
2249 OUTS (outf, "]");
2250 }
2251 else if (aop == 3 && W == 1)
2252 {
2253 OUTS (outf, "[");
2254 OUTS (outf, iregs (i));
2255 OUTS (outf, " ++ ");
2256 OUTS (outf, mregs (m));
2257 OUTS (outf, "] = ");
2258 OUTS (outf, dregs (reg));
2259 }
2260 else
2261 return 0;
2262
2263 return 2;
2264 }
2265
2266 static int
2267 decode_LDST_0 (TIword iw0, disassemble_info *outf)
2268 {
2269 /* LDST
2270 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2271 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2272 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2273 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2274 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2275 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2276 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2277 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2278 int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
2279
2280 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2281 {
2282 OUTS (outf, dregs (reg));
2283 OUTS (outf, " = [");
2284 OUTS (outf, pregs (ptr));
2285 OUTS (outf, "++]");
2286 }
2287 else if (aop == 0 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2288 {
2289 OUTS (outf, pregs (reg));
2290 OUTS (outf, " = [");
2291 OUTS (outf, pregs (ptr));
2292 OUTS (outf, "++]");
2293 }
2294 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2295 {
2296 OUTS (outf, dregs (reg));
2297 OUTS (outf, " = W[");
2298 OUTS (outf, pregs (ptr));
2299 OUTS (outf, "++] (Z)");
2300 }
2301 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2302 {
2303 OUTS (outf, dregs (reg));
2304 OUTS (outf, " = W[");
2305 OUTS (outf, pregs (ptr));
2306 OUTS (outf, "++] (X)");
2307 }
2308 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2309 {
2310 OUTS (outf, dregs (reg));
2311 OUTS (outf, " = B[");
2312 OUTS (outf, pregs (ptr));
2313 OUTS (outf, "++] (Z)");
2314 }
2315 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2316 {
2317 OUTS (outf, dregs (reg));
2318 OUTS (outf, " = B[");
2319 OUTS (outf, pregs (ptr));
2320 OUTS (outf, "++] (X)");
2321 }
2322 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2323 {
2324 OUTS (outf, dregs (reg));
2325 OUTS (outf, " = [");
2326 OUTS (outf, pregs (ptr));
2327 OUTS (outf, "--]");
2328 }
2329 else if (aop == 1 && sz == 0 && Z == 1 && W == 0 && reg != ptr)
2330 {
2331 OUTS (outf, pregs (reg));
2332 OUTS (outf, " = [");
2333 OUTS (outf, pregs (ptr));
2334 OUTS (outf, "--]");
2335 }
2336 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2337 {
2338 OUTS (outf, dregs (reg));
2339 OUTS (outf, " = W[");
2340 OUTS (outf, pregs (ptr));
2341 OUTS (outf, "--] (Z)");
2342 }
2343 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2344 {
2345 OUTS (outf, dregs (reg));
2346 OUTS (outf, " = W[");
2347 OUTS (outf, pregs (ptr));
2348 OUTS (outf, "--] (X)");
2349 }
2350 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2351 {
2352 OUTS (outf, dregs (reg));
2353 OUTS (outf, " = B[");
2354 OUTS (outf, pregs (ptr));
2355 OUTS (outf, "--] (Z)");
2356 }
2357 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2358 {
2359 OUTS (outf, dregs (reg));
2360 OUTS (outf, " = B[");
2361 OUTS (outf, pregs (ptr));
2362 OUTS (outf, "--] (X)");
2363 }
2364 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2365 {
2366 OUTS (outf, dregs (reg));
2367 OUTS (outf, " = [");
2368 OUTS (outf, pregs (ptr));
2369 OUTS (outf, "]");
2370 }
2371 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2372 {
2373 OUTS (outf, pregs (reg));
2374 OUTS (outf, " = [");
2375 OUTS (outf, pregs (ptr));
2376 OUTS (outf, "]");
2377 }
2378 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2379 {
2380 OUTS (outf, dregs (reg));
2381 OUTS (outf, " = W[");
2382 OUTS (outf, pregs (ptr));
2383 OUTS (outf, "] (Z)");
2384 }
2385 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2386 {
2387 OUTS (outf, dregs (reg));
2388 OUTS (outf, " = W[");
2389 OUTS (outf, pregs (ptr));
2390 OUTS (outf, "] (X)");
2391 }
2392 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2393 {
2394 OUTS (outf, dregs (reg));
2395 OUTS (outf, " = B[");
2396 OUTS (outf, pregs (ptr));
2397 OUTS (outf, "] (Z)");
2398 }
2399 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2400 {
2401 OUTS (outf, dregs (reg));
2402 OUTS (outf, " = B[");
2403 OUTS (outf, pregs (ptr));
2404 OUTS (outf, "] (X)");
2405 }
2406 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2407 {
2408 OUTS (outf, "[");
2409 OUTS (outf, pregs (ptr));
2410 OUTS (outf, "++] = ");
2411 OUTS (outf, dregs (reg));
2412 }
2413 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2414 {
2415 OUTS (outf, "[");
2416 OUTS (outf, pregs (ptr));
2417 OUTS (outf, "++] = ");
2418 OUTS (outf, pregs (reg));
2419 }
2420 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2421 {
2422 OUTS (outf, "W[");
2423 OUTS (outf, pregs (ptr));
2424 OUTS (outf, "++] = ");
2425 OUTS (outf, dregs (reg));
2426 }
2427 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2428 {
2429 OUTS (outf, "B[");
2430 OUTS (outf, pregs (ptr));
2431 OUTS (outf, "++] = ");
2432 OUTS (outf, dregs (reg));
2433 }
2434 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2435 {
2436 OUTS (outf, "[");
2437 OUTS (outf, pregs (ptr));
2438 OUTS (outf, "--] = ");
2439 OUTS (outf, dregs (reg));
2440 }
2441 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2442 {
2443 OUTS (outf, "[");
2444 OUTS (outf, pregs (ptr));
2445 OUTS (outf, "--] = ");
2446 OUTS (outf, pregs (reg));
2447 }
2448 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2449 {
2450 OUTS (outf, "W[");
2451 OUTS (outf, pregs (ptr));
2452 OUTS (outf, "--] = ");
2453 OUTS (outf, dregs (reg));
2454 }
2455 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2456 {
2457 OUTS (outf, "B[");
2458 OUTS (outf, pregs (ptr));
2459 OUTS (outf, "--] = ");
2460 OUTS (outf, dregs (reg));
2461 }
2462 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2463 {
2464 OUTS (outf, "[");
2465 OUTS (outf, pregs (ptr));
2466 OUTS (outf, "] = ");
2467 OUTS (outf, dregs (reg));
2468 }
2469 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2470 {
2471 OUTS (outf, "[");
2472 OUTS (outf, pregs (ptr));
2473 OUTS (outf, "] = ");
2474 OUTS (outf, pregs (reg));
2475 }
2476 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2477 {
2478 OUTS (outf, "W[");
2479 OUTS (outf, pregs (ptr));
2480 OUTS (outf, "] = ");
2481 OUTS (outf, dregs (reg));
2482 }
2483 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2484 {
2485 OUTS (outf, "B[");
2486 OUTS (outf, pregs (ptr));
2487 OUTS (outf, "] = ");
2488 OUTS (outf, dregs (reg));
2489 }
2490 else
2491 return 0;
2492
2493 return 2;
2494 }
2495
2496 static int
2497 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
2498 {
2499 /* LDSTiiFP
2500 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2501 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2502 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2503 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2504 int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
2505 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2506
2507 if (W == 0)
2508 {
2509 OUTS (outf, dpregs (reg));
2510 OUTS (outf, " = [FP ");
2511 OUTS (outf, negimm5s4 (offset));
2512 OUTS (outf, "]");
2513 }
2514 else if (W == 1)
2515 {
2516 OUTS (outf, "[FP ");
2517 OUTS (outf, negimm5s4 (offset));
2518 OUTS (outf, "] = ");
2519 OUTS (outf, dpregs (reg));
2520 }
2521 else
2522 return 0;
2523
2524 return 2;
2525 }
2526
2527 static int
2528 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
2529 {
2530 /* LDSTii
2531 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2532 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2533 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2534 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2535 int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
2536 int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
2537 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2538 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2539
2540 if (W == 0 && op == 0)
2541 {
2542 OUTS (outf, dregs (reg));
2543 OUTS (outf, " = [");
2544 OUTS (outf, pregs (ptr));
2545 OUTS (outf, " + ");
2546 OUTS (outf, uimm4s4 (offset));
2547 OUTS (outf, "]");
2548 }
2549 else if (W == 0 && op == 1)
2550 {
2551 OUTS (outf, dregs (reg));
2552 OUTS (outf, " = W[");
2553 OUTS (outf, pregs (ptr));
2554 OUTS (outf, " + ");
2555 OUTS (outf, uimm4s2 (offset));
2556 OUTS (outf, "] (Z)");
2557 }
2558 else if (W == 0 && op == 2)
2559 {
2560 OUTS (outf, dregs (reg));
2561 OUTS (outf, " = W[");
2562 OUTS (outf, pregs (ptr));
2563 OUTS (outf, " + ");
2564 OUTS (outf, uimm4s2 (offset));
2565 OUTS (outf, "] (X)");
2566 }
2567 else if (W == 0 && op == 3)
2568 {
2569 OUTS (outf, pregs (reg));
2570 OUTS (outf, " = [");
2571 OUTS (outf, pregs (ptr));
2572 OUTS (outf, " + ");
2573 OUTS (outf, uimm4s4 (offset));
2574 OUTS (outf, "]");
2575 }
2576 else if (W == 1 && op == 0)
2577 {
2578 OUTS (outf, "[");
2579 OUTS (outf, pregs (ptr));
2580 OUTS (outf, " + ");
2581 OUTS (outf, uimm4s4 (offset));
2582 OUTS (outf, "] = ");
2583 OUTS (outf, dregs (reg));
2584 }
2585 else if (W == 1 && op == 1)
2586 {
2587 OUTS (outf, "W[");
2588 OUTS (outf, pregs (ptr));
2589 OUTS (outf, " + ");
2590 OUTS (outf, uimm4s2 (offset));
2591 OUTS (outf, "] = ");
2592 OUTS (outf, dregs (reg));
2593 }
2594 else if (W == 1 && op == 3)
2595 {
2596 OUTS (outf, "[");
2597 OUTS (outf, pregs (ptr));
2598 OUTS (outf, " + ");
2599 OUTS (outf, uimm4s4 (offset));
2600 OUTS (outf, "] = ");
2601 OUTS (outf, pregs (reg));
2602 }
2603 else
2604 return 0;
2605
2606 return 2;
2607 }
2608
2609 static int
2610 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2611 {
2612 /* LoopSetup
2613 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2614 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
2615 |.reg...........| - | - |.eoffset...............................|
2616 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2617 int c = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
2618 int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
2619 int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
2620 int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
2621 int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
2622
2623 if (parallel)
2624 return 0;
2625
2626 if (rop == 0)
2627 {
2628 OUTS (outf, "LSETUP");
2629 OUTS (outf, "(0x");
2630 OUTS (outf, pcrel4 (soffset));
2631 OUTS (outf, ", 0x");
2632 OUTS (outf, lppcrel10 (eoffset));
2633 OUTS (outf, ") ");
2634 OUTS (outf, counters (c));
2635 }
2636 else if (rop == 1)
2637 {
2638 OUTS (outf, "LSETUP");
2639 OUTS (outf, "(0x");
2640 OUTS (outf, pcrel4 (soffset));
2641 OUTS (outf, ", 0x");
2642 OUTS (outf, lppcrel10 (eoffset));
2643 OUTS (outf, ") ");
2644 OUTS (outf, counters (c));
2645 OUTS (outf, " = ");
2646 OUTS (outf, pregs (reg));
2647 }
2648 else if (rop == 3)
2649 {
2650 OUTS (outf, "LSETUP");
2651 OUTS (outf, "(0x");
2652 OUTS (outf, pcrel4 (soffset));
2653 OUTS (outf, ", 0x");
2654 OUTS (outf, lppcrel10 (eoffset));
2655 OUTS (outf, ") ");
2656 OUTS (outf, counters (c));
2657 OUTS (outf, " = ");
2658 OUTS (outf, pregs (reg));
2659 OUTS (outf, " >> 0x1");
2660 }
2661 else
2662 return 0;
2663
2664 return 4;
2665 }
2666
2667 static int
2668 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2669 {
2670 /* LDIMMhalf
2671 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2672 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
2673 |.hword.........................................................|
2674 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2675 int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
2676 int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
2677 int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
2678 int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
2679 int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
2680 int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
2681
2682 bu32 *pval = get_allreg (grp, reg);
2683
2684 if (parallel)
2685 return 0;
2686
2687 /* Since we don't have 32-bit immediate loads, we allow the disassembler
2688 to combine them, so it prints out the right values.
2689 Here we keep track of the registers. */
2690 if (H == 0 && S == 1 && Z == 0)
2691 {
2692 /* regs = imm16 (x) */
2693 *pval = imm16_val (hword);
2694 if (hword & 0x8000)
2695 *pval |= 0xFFFF0000;
2696 else
2697 *pval &= 0xFFFF;
2698 }
2699 else if (H == 0 && S == 0 && Z == 1)
2700 {
2701 /* regs = luimm16 (Z) */
2702 *pval = luimm16_val (hword);
2703 *pval &= 0xFFFF;
2704 }
2705 else if (H == 0 && S == 0 && Z == 0)
2706 {
2707 /* regs_lo = luimm16 */
2708 *pval &= 0xFFFF0000;
2709 *pval |= luimm16_val (hword);
2710 }
2711 else if (H == 1 && S == 0 && Z == 0)
2712 {
2713 /* regs_hi = huimm16 */
2714 *pval &= 0xFFFF;
2715 *pval |= luimm16_val (hword) << 16;
2716 }
2717
2718 /* Here we do the disassembly */
2719 if (grp == 0 && H == 0 && S == 0 && Z == 0)
2720 {
2721 OUTS (outf, dregs_lo (reg));
2722 OUTS (outf, " = ");
2723 OUTS (outf, uimm16 (hword));
2724 }
2725 else if (grp == 0 && H == 1 && S == 0 && Z == 0)
2726 {
2727 OUTS (outf, dregs_hi (reg));
2728 OUTS (outf, " = ");
2729 OUTS (outf, uimm16 (hword));
2730 }
2731 else if (grp == 0 && H == 0 && S == 1 && Z == 0)
2732 {
2733 OUTS (outf, dregs (reg));
2734 OUTS (outf, " = ");
2735 OUTS (outf, imm16 (hword));
2736 OUTS (outf, " (X)");
2737 }
2738 else if (H == 0 && S == 1 && Z == 0)
2739 {
2740 OUTS (outf, regs (reg, grp));
2741 OUTS (outf, " = ");
2742 OUTS (outf, imm16 (hword));
2743 OUTS (outf, " (X)");
2744 }
2745 else if (H == 0 && S == 0 && Z == 1)
2746 {
2747 OUTS (outf, regs (reg, grp));
2748 OUTS (outf, " = ");
2749 OUTS (outf, uimm16 (hword));
2750 OUTS (outf, " (Z)");
2751 }
2752 else if (H == 0 && S == 0 && Z == 0)
2753 {
2754 OUTS (outf, regs_lo (reg, grp));
2755 OUTS (outf, " = ");
2756 OUTS (outf, uimm16 (hword));
2757 }
2758 else if (H == 1 && S == 0 && Z == 0)
2759 {
2760 OUTS (outf, regs_hi (reg, grp));
2761 OUTS (outf, " = ");
2762 OUTS (outf, uimm16 (hword));
2763 }
2764 else
2765 return 0;
2766
2767 /* And we print out the 32-bit value if it is a pointer. */
2768 if (S == 0 && Z == 0)
2769 {
2770 OUTS (outf, ";\t\t/* (");
2771 OUTS (outf, imm16d (hword));
2772 OUTS (outf, ")\t");
2773
2774 /* If it is an MMR, don't print the symbol. */
2775 if (*pval < 0xFFC00000 && grp == 1)
2776 {
2777 OUTS (outf, regs (reg, grp));
2778 OUTS (outf, "=0x");
2779 OUTS (outf, huimm32e (*pval));
2780 }
2781 else
2782 {
2783 OUTS (outf, regs (reg, grp));
2784 OUTS (outf, "=0x");
2785 OUTS (outf, huimm32e (*pval));
2786 OUTS (outf, "(");
2787 OUTS (outf, imm32 (*pval));
2788 OUTS (outf, ")");
2789 }
2790
2791 OUTS (outf, " */");
2792 comment = 1;
2793 }
2794 if (S == 1 || Z == 1)
2795 {
2796 OUTS (outf, ";\t\t/*\t\t");
2797 OUTS (outf, regs (reg, grp));
2798 OUTS (outf, "=0x");
2799 OUTS (outf, huimm32e (*pval));
2800 OUTS (outf, "(");
2801 OUTS (outf, imm32 (*pval));
2802 OUTS (outf, ") */");
2803 comment = 1;
2804 }
2805 return 4;
2806 }
2807
2808 static int
2809 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
2810 {
2811 /* CALLa
2812 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2813 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
2814 |.lsw...........................................................|
2815 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2816 int S = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
2817 int lsw = ((iw1 >> 0) & 0xffff);
2818 int msw = ((iw0 >> 0) & 0xff);
2819
2820 if (parallel)
2821 return 0;
2822
2823 if (S == 1)
2824 OUTS (outf, "CALL 0x");
2825 else if (S == 0)
2826 OUTS (outf, "JUMP.L 0x");
2827 else
2828 return 0;
2829
2830 OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
2831 return 4;
2832 }
2833
2834 static int
2835 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2836 {
2837 /* LDSTidxI
2838 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2839 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
2840 |.offset........................................................|
2841 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2842 int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
2843 int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
2844 int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
2845 int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
2846 int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
2847 int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
2848
2849 if (W == 0 && sz == 0 && Z == 0)
2850 {
2851 OUTS (outf, dregs (reg));
2852 OUTS (outf, " = [");
2853 OUTS (outf, pregs (ptr));
2854 OUTS (outf, " + ");
2855 OUTS (outf, imm16s4 (offset));
2856 OUTS (outf, "]");
2857 }
2858 else if (W == 0 && sz == 0 && Z == 1)
2859 {
2860 OUTS (outf, pregs (reg));
2861 OUTS (outf, " = [");
2862 OUTS (outf, pregs (ptr));
2863 OUTS (outf, " + ");
2864 OUTS (outf, imm16s4 (offset));
2865 OUTS (outf, "]");
2866 }
2867 else if (W == 0 && sz == 1 && Z == 0)
2868 {
2869 OUTS (outf, dregs (reg));
2870 OUTS (outf, " = W[");
2871 OUTS (outf, pregs (ptr));
2872 OUTS (outf, " + ");
2873 OUTS (outf, imm16s2 (offset));
2874 OUTS (outf, "] (Z)");
2875 }
2876 else if (W == 0 && sz == 1 && Z == 1)
2877 {
2878 OUTS (outf, dregs (reg));
2879 OUTS (outf, " = W[");
2880 OUTS (outf, pregs (ptr));
2881 OUTS (outf, " + ");
2882 OUTS (outf, imm16s2 (offset));
2883 OUTS (outf, "] (X)");
2884 }
2885 else if (W == 0 && sz == 2 && Z == 0)
2886 {
2887 OUTS (outf, dregs (reg));
2888 OUTS (outf, " = B[");
2889 OUTS (outf, pregs (ptr));
2890 OUTS (outf, " + ");
2891 OUTS (outf, imm16 (offset));
2892 OUTS (outf, "] (Z)");
2893 }
2894 else if (W == 0 && sz == 2 && Z == 1)
2895 {
2896 OUTS (outf, dregs (reg));
2897 OUTS (outf, " = B[");
2898 OUTS (outf, pregs (ptr));
2899 OUTS (outf, " + ");
2900 OUTS (outf, imm16 (offset));
2901 OUTS (outf, "] (X)");
2902 }
2903 else if (W == 1 && sz == 0 && Z == 0)
2904 {
2905 OUTS (outf, "[");
2906 OUTS (outf, pregs (ptr));
2907 OUTS (outf, " + ");
2908 OUTS (outf, imm16s4 (offset));
2909 OUTS (outf, "] = ");
2910 OUTS (outf, dregs (reg));
2911 }
2912 else if (W == 1 && sz == 0 && Z == 1)
2913 {
2914 OUTS (outf, "[");
2915 OUTS (outf, pregs (ptr));
2916 OUTS (outf, " + ");
2917 OUTS (outf, imm16s4 (offset));
2918 OUTS (outf, "] = ");
2919 OUTS (outf, pregs (reg));
2920 }
2921 else if (W == 1 && sz == 1 && Z == 0)
2922 {
2923 OUTS (outf, "W[");
2924 OUTS (outf, pregs (ptr));
2925 OUTS (outf, " + ");
2926 OUTS (outf, imm16s2 (offset));
2927 OUTS (outf, "] = ");
2928 OUTS (outf, dregs (reg));
2929 }
2930 else if (W == 1 && sz == 2 && Z == 0)
2931 {
2932 OUTS (outf, "B[");
2933 OUTS (outf, pregs (ptr));
2934 OUTS (outf, " + ");
2935 OUTS (outf, imm16 (offset));
2936 OUTS (outf, "] = ");
2937 OUTS (outf, dregs (reg));
2938 }
2939 else
2940 return 0;
2941
2942 return 4;
2943 }
2944
2945 static int
2946 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2947 {
2948 /* linkage
2949 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2950 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
2951 |.framesize.....................................................|
2952 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2953 int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
2954 int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
2955
2956 if (parallel)
2957 return 0;
2958
2959 if (R == 0)
2960 {
2961 OUTS (outf, "LINK ");
2962 OUTS (outf, uimm16s4 (framesize));
2963 OUTS (outf, ";\t\t/* (");
2964 OUTS (outf, uimm16s4d (framesize));
2965 OUTS (outf, ") */");
2966 comment = 1;
2967 }
2968 else if (R == 1)
2969 OUTS (outf, "UNLINK");
2970 else
2971 return 0;
2972
2973 return 4;
2974 }
2975
2976 static int
2977 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
2978 {
2979 /* dsp32mac
2980 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2981 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2982 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2983 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2984 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2985 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2986 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2987 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
2988 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2989 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2990 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
2991 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
2992 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2993 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
2994 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
2995 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2996 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
2997 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
2998
2999 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
3000 return 0;
3001
3002 if (op1 == 3 && MM)
3003 return 0;
3004
3005 if ((w1 || w0) && mmod == M_W32)
3006 return 0;
3007
3008 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
3009 return 0;
3010
3011 if (w1 == 1 || op1 != 3)
3012 {
3013 if (w1)
3014 OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
3015
3016 if (op1 == 3)
3017 OUTS (outf, " = A1");
3018 else
3019 {
3020 if (w1)
3021 OUTS (outf, " = (");
3022 decode_macfunc (1, op1, h01, h11, src0, src1, outf);
3023 if (w1)
3024 OUTS (outf, ")");
3025 }
3026
3027 if (w0 == 1 || op0 != 3)
3028 {
3029 if (MM)
3030 OUTS (outf, " (M)");
3031 MM = 0;
3032 OUTS (outf, ", ");
3033 }
3034 }
3035
3036 if (w0 == 1 || op0 != 3)
3037 {
3038 if (w0)
3039 OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
3040
3041 if (op0 == 3)
3042 OUTS (outf, " = A0");
3043 else
3044 {
3045 if (w0)
3046 OUTS (outf, " = (");
3047 decode_macfunc (0, op0, h00, h10, src0, src1, outf);
3048 if (w0)
3049 OUTS (outf, ")");
3050 }
3051 }
3052
3053 decode_optmode (mmod, MM, outf);
3054
3055 return 4;
3056 }
3057
3058 static int
3059 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3060 {
3061 /* dsp32mult
3062 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3063 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
3064 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
3065 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3066 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
3067 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
3068 int MM = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
3069 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
3070 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
3071 int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
3072 int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
3073 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
3074 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
3075 int h00 = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
3076 int h11 = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
3077 int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
3078
3079 if (w1 == 0 && w0 == 0)
3080 return 0;
3081
3082 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
3083 return 0;
3084
3085 if (w1)
3086 {
3087 OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
3088 OUTS (outf, " = ");
3089 decode_multfunc (h01, h11, src0, src1, outf);
3090
3091 if (w0)
3092 {
3093 if (MM)
3094 OUTS (outf, " (M)");
3095 MM = 0;
3096 OUTS (outf, ", ");
3097 }
3098 }
3099
3100 if (w0)
3101 {
3102 OUTS (outf, dregs (dst));
3103 OUTS (outf, " = ");
3104 decode_multfunc (h00, h10, src0, src1, outf);
3105 }
3106
3107 decode_optmode (mmod, MM, outf);
3108 return 4;
3109 }
3110
3111 static int
3112 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3113 {
3114 /* dsp32alu
3115 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3116 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
3117 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
3118 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3119 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
3120 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
3121 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
3122 int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
3123 int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
3124 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
3125 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
3126 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
3127 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
3128
3129 if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
3130 {
3131 OUTS (outf, "A0.L = ");
3132 OUTS (outf, dregs_lo (src0));
3133 }
3134 else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
3135 {
3136 OUTS (outf, "A1.H = ");
3137 OUTS (outf, dregs_hi (src0));
3138 }
3139 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
3140 {
3141 OUTS (outf, "A1.L = ");
3142 OUTS (outf, dregs_lo (src0));
3143 }
3144 else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
3145 {
3146 OUTS (outf, "A0.H = ");
3147 OUTS (outf, dregs_hi (src0));
3148 }
3149 else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
3150 {
3151 OUTS (outf, dregs_hi (dst0));
3152 OUTS (outf, " = ");
3153 OUTS (outf, dregs (src0));
3154 OUTS (outf, " - ");
3155 OUTS (outf, dregs (src1));
3156 OUTS (outf, " (RND20)");
3157 }
3158 else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
3159 {
3160 OUTS (outf, dregs_hi (dst0));
3161 OUTS (outf, " = ");
3162 OUTS (outf, dregs (src0));
3163 OUTS (outf, " + ");
3164 OUTS (outf, dregs (src1));
3165 OUTS (outf, " (RND20)");
3166 }
3167 else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
3168 {
3169 OUTS (outf, dregs_lo (dst0));
3170 OUTS (outf, " = ");
3171 OUTS (outf, dregs (src0));
3172 OUTS (outf, " - ");
3173 OUTS (outf, dregs (src1));
3174 OUTS (outf, " (RND12)");
3175 }
3176 else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
3177 {
3178 OUTS (outf, dregs_lo (dst0));
3179 OUTS (outf, " = ");
3180 OUTS (outf, dregs (src0));
3181 OUTS (outf, " + ");
3182 OUTS (outf, dregs (src1));
3183 OUTS (outf, " (RND12)");
3184 }
3185 else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
3186 {
3187 OUTS (outf, dregs_lo (dst0));
3188 OUTS (outf, " = ");
3189 OUTS (outf, dregs (src0));
3190 OUTS (outf, " - ");
3191 OUTS (outf, dregs (src1));
3192 OUTS (outf, " (RND20)");
3193 }
3194 else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
3195 {
3196 OUTS (outf, dregs_hi (dst0));
3197 OUTS (outf, " = ");
3198 OUTS (outf, dregs (src0));
3199 OUTS (outf, " + ");
3200 OUTS (outf, dregs (src1));
3201 OUTS (outf, " (RND12)");
3202 }
3203 else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
3204 {
3205 OUTS (outf, dregs_lo (dst0));
3206 OUTS (outf, " = ");
3207 OUTS (outf, dregs (src0));
3208 OUTS (outf, " + ");
3209 OUTS (outf, dregs (src1));
3210 OUTS (outf, " (RND20)");
3211 }
3212 else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
3213 {
3214 OUTS (outf, dregs_hi (dst0));
3215 OUTS (outf, " = ");
3216 OUTS (outf, dregs (src0));
3217 OUTS (outf, " - ");
3218 OUTS (outf, dregs (src1));
3219 OUTS (outf, " (RND12)");
3220 }
3221 else if (HL == 1 && aop == 0 && aopcde == 2)
3222 {
3223 OUTS (outf, dregs_hi (dst0));
3224 OUTS (outf, " = ");
3225 OUTS (outf, dregs_lo (src0));
3226 OUTS (outf, " + ");
3227 OUTS (outf, dregs_lo (src1));
3228 amod1 (s, x, outf);
3229 }
3230 else if (HL == 1 && aop == 1 && aopcde == 2)
3231 {
3232 OUTS (outf, dregs_hi (dst0));
3233 OUTS (outf, " = ");
3234 OUTS (outf, dregs_lo (src0));
3235 OUTS (outf, " + ");
3236 OUTS (outf, dregs_hi (src1));
3237 amod1 (s, x, outf);
3238 }
3239 else if (HL == 1 && aop == 2 && aopcde == 2)
3240 {
3241 OUTS (outf, dregs_hi (dst0));
3242 OUTS (outf, " = ");
3243 OUTS (outf, dregs_hi (src0));
3244 OUTS (outf, " + ");
3245 OUTS (outf, dregs_lo (src1));
3246 amod1 (s, x, outf);
3247 }
3248 else if (HL == 1 && aop == 3 && aopcde == 2)
3249 {
3250 OUTS (outf, dregs_hi (dst0));
3251 OUTS (outf, " = ");
3252 OUTS (outf, dregs_hi (src0));
3253 OUTS (outf, " + ");
3254 OUTS (outf, dregs_hi (src1));
3255 amod1 (s, x, outf);
3256 }
3257 else if (HL == 0 && aop == 0 && aopcde == 3)
3258 {
3259 OUTS (outf, dregs_lo (dst0));
3260 OUTS (outf, " = ");
3261 OUTS (outf, dregs_lo (src0));
3262 OUTS (outf, " - ");
3263 OUTS (outf, dregs_lo (src1));
3264 amod1 (s, x, outf);
3265 }
3266 else if (HL == 0 && aop == 1 && aopcde == 3)
3267 {
3268 OUTS (outf, dregs_lo (dst0));
3269 OUTS (outf, " = ");
3270 OUTS (outf, dregs_lo (src0));
3271 OUTS (outf, " - ");
3272 OUTS (outf, dregs_hi (src1));
3273 amod1 (s, x, outf);
3274 }
3275 else if (HL == 0 && aop == 3 && aopcde == 2)
3276 {
3277 OUTS (outf, dregs_lo (dst0));
3278 OUTS (outf, " = ");
3279 OUTS (outf, dregs_hi (src0));
3280 OUTS (outf, " + ");
3281 OUTS (outf, dregs_hi (src1));
3282 amod1 (s, x, outf);
3283 }
3284 else if (HL == 1 && aop == 0 && aopcde == 3)
3285 {
3286 OUTS (outf, dregs_hi (dst0));
3287 OUTS (outf, " = ");
3288 OUTS (outf, dregs_lo (src0));
3289 OUTS (outf, " - ");
3290 OUTS (outf, dregs_lo (src1));
3291 amod1 (s, x, outf);
3292 }
3293 else if (HL == 1 && aop == 1 && aopcde == 3)
3294 {
3295 OUTS (outf, dregs_hi (dst0));
3296 OUTS (outf, " = ");
3297 OUTS (outf, dregs_lo (src0));
3298 OUTS (outf, " - ");
3299 OUTS (outf, dregs_hi (src1));
3300 amod1 (s, x, outf);
3301 }
3302 else if (HL == 1 && aop == 2 && aopcde == 3)
3303 {
3304 OUTS (outf, dregs_hi (dst0));
3305 OUTS (outf, " = ");
3306 OUTS (outf, dregs_hi (src0));
3307 OUTS (outf, " - ");
3308 OUTS (outf, dregs_lo (src1));
3309 amod1 (s, x, outf);
3310 }
3311 else if (HL == 1 && aop == 3 && aopcde == 3)
3312 {
3313 OUTS (outf, dregs_hi (dst0));
3314 OUTS (outf, " = ");
3315 OUTS (outf, dregs_hi (src0));
3316 OUTS (outf, " - ");
3317 OUTS (outf, dregs_hi (src1));
3318 amod1 (s, x, outf);
3319 }
3320 else if (HL == 0 && aop == 2 && aopcde == 2)
3321 {
3322 OUTS (outf, dregs_lo (dst0));
3323 OUTS (outf, " = ");
3324 OUTS (outf, dregs_hi (src0));
3325 OUTS (outf, " + ");
3326 OUTS (outf, dregs_lo (src1));
3327 amod1 (s, x, outf);
3328 }
3329 else if (HL == 0 && aop == 1 && aopcde == 2)
3330 {
3331 OUTS (outf, dregs_lo (dst0));
3332 OUTS (outf, " = ");
3333 OUTS (outf, dregs_lo (src0));
3334 OUTS (outf, " + ");
3335 OUTS (outf, dregs_hi (src1));
3336 amod1 (s, x, outf);
3337 }
3338 else if (HL == 0 && aop == 2 && aopcde == 3)
3339 {
3340 OUTS (outf, dregs_lo (dst0));
3341 OUTS (outf, " = ");
3342 OUTS (outf, dregs_hi (src0));
3343 OUTS (outf, " - ");
3344 OUTS (outf, dregs_lo (src1));
3345 amod1 (s, x, outf);
3346 }
3347 else if (HL == 0 && aop == 3 && aopcde == 3)
3348 {
3349 OUTS (outf, dregs_lo (dst0));
3350 OUTS (outf, " = ");
3351 OUTS (outf, dregs_hi (src0));
3352 OUTS (outf, " - ");
3353 OUTS (outf, dregs_hi (src1));
3354 amod1 (s, x, outf);
3355 }
3356 else if (HL == 0 && aop == 0 && aopcde == 2)
3357 {
3358 OUTS (outf, dregs_lo (dst0));
3359 OUTS (outf, " = ");
3360 OUTS (outf, dregs_lo (src0));
3361 OUTS (outf, " + ");
3362 OUTS (outf, dregs_lo (src1));
3363 amod1 (s, x, outf);
3364 }
3365 else if (aop == 0 && aopcde == 9 && s == 1)
3366 {
3367 OUTS (outf, "A0 = ");
3368 OUTS (outf, dregs (src0));
3369 }
3370 else if (aop == 3 && aopcde == 11 && s == 0)
3371 OUTS (outf, "A0 -= A1");
3372
3373 else if (aop == 3 && aopcde == 11 && s == 1)
3374 OUTS (outf, "A0 -= A1 (W32)");
3375
3376 else if (aop == 3 && aopcde == 22 && HL == 1)
3377 {
3378 OUTS (outf, dregs (dst0));
3379 OUTS (outf, " = BYTEOP2M (");
3380 OUTS (outf, dregs (src0 + 1));
3381 OUTS (outf, ":");
3382 OUTS (outf, imm5d (src0));
3383 OUTS (outf, ", ");
3384 OUTS (outf, dregs (src1 + 1));
3385 OUTS (outf, ":");
3386 OUTS (outf, imm5d (src1));
3387 OUTS (outf, ") (TH");
3388 if (s == 1)
3389 OUTS (outf, ", R)");
3390 else
3391 OUTS (outf, ")");
3392 }
3393 else if (aop == 3 && aopcde == 22 && HL == 0)
3394 {
3395 OUTS (outf, dregs (dst0));
3396 OUTS (outf, " = BYTEOP2M (");
3397 OUTS (outf, dregs (src0 + 1));
3398 OUTS (outf, ":");
3399 OUTS (outf, imm5d (src0));
3400 OUTS (outf, ", ");
3401 OUTS (outf, dregs (src1 + 1));
3402 OUTS (outf, ":");
3403 OUTS (outf, imm5d (src1));
3404 OUTS (outf, ") (TL");
3405 if (s == 1)
3406 OUTS (outf, ", R)");
3407 else
3408 OUTS (outf, ")");
3409 }
3410 else if (aop == 2 && aopcde == 22 && HL == 1)
3411 {
3412 OUTS (outf, dregs (dst0));
3413 OUTS (outf, " = BYTEOP2M (");
3414 OUTS (outf, dregs (src0 + 1));
3415 OUTS (outf, ":");
3416 OUTS (outf, imm5d (src0));
3417 OUTS (outf, ", ");
3418 OUTS (outf, dregs (src1 + 1));
3419 OUTS (outf, ":");
3420 OUTS (outf, imm5d (src1));
3421 OUTS (outf, ") (RNDH");
3422 if (s == 1)
3423 OUTS (outf, ", R)");
3424 else
3425 OUTS (outf, ")");
3426 }
3427 else if (aop == 2 && aopcde == 22 && HL == 0)
3428 {
3429 OUTS (outf, dregs (dst0));
3430 OUTS (outf, " = BYTEOP2M (");
3431 OUTS (outf, dregs (src0 + 1));
3432 OUTS (outf, ":");
3433 OUTS (outf, imm5d (src0));
3434 OUTS (outf, ", ");
3435 OUTS (outf, dregs (src1 + 1));
3436 OUTS (outf, ":");
3437 OUTS (outf, imm5d (src1));
3438 OUTS (outf, ") (RNDL");
3439 if (s == 1)
3440 OUTS (outf, ", R)");
3441 else
3442 OUTS (outf, ")");
3443 }
3444 else if (aop == 1 && aopcde == 22 && HL == 1)
3445 {
3446 OUTS (outf, dregs (dst0));
3447 OUTS (outf, " = BYTEOP2P (");
3448 OUTS (outf, dregs (src0 + 1));
3449 OUTS (outf, ":");
3450 OUTS (outf, imm5d (src0));
3451 OUTS (outf, ", ");
3452 OUTS (outf, dregs (src1 + 1));
3453 OUTS (outf, ":");
3454 OUTS (outf, imm5d (src1));
3455 OUTS (outf, ") (TH");
3456 if (s == 1)
3457 OUTS (outf, ", R)");
3458 else
3459 OUTS (outf, ")");
3460 }
3461 else if (aop == 1 && aopcde == 22 && HL == 0)
3462 {
3463 OUTS (outf, dregs (dst0));
3464 OUTS (outf, " = BYTEOP2P (");
3465 OUTS (outf, dregs (src0 + 1));
3466 OUTS (outf, ":");
3467 OUTS (outf, imm5d (src0));
3468 OUTS (outf, ", ");
3469 OUTS (outf, dregs (src1 + 1));
3470 OUTS (outf, ":");
3471 OUTS (outf, imm5d (src1));
3472 OUTS (outf, ") (TL");
3473 if (s == 1)
3474 OUTS (outf, ", R)");
3475 else
3476 OUTS (outf, ")");
3477 }
3478 else if (aop == 0 && aopcde == 22 && HL == 1)
3479 {
3480 OUTS (outf, dregs (dst0));
3481 OUTS (outf, " = BYTEOP2P (");
3482 OUTS (outf, dregs (src0 + 1));
3483 OUTS (outf, ":");
3484 OUTS (outf, imm5d (src0));
3485 OUTS (outf, ", ");
3486 OUTS (outf, dregs (src1 + 1));
3487 OUTS (outf, ":");
3488 OUTS (outf, imm5d (src1));
3489 OUTS (outf, ") (RNDH");
3490 if (s == 1)
3491 OUTS (outf, ", R)");
3492 else
3493 OUTS (outf, ")");
3494 }
3495 else if (aop == 0 && aopcde == 22 && HL == 0)
3496 {
3497 OUTS (outf, dregs (dst0));
3498 OUTS (outf, " = BYTEOP2P (");
3499 OUTS (outf, dregs (src0 + 1));
3500 OUTS (outf, ":");
3501 OUTS (outf, imm5d (src0));
3502 OUTS (outf, ", ");
3503 OUTS (outf, dregs (src1 + 1));
3504 OUTS (outf, ":");
3505 OUTS (outf, imm5d (src1));
3506 OUTS (outf, ") (RNDL");
3507 if (s == 1)
3508 OUTS (outf, ", R)");
3509 else
3510 OUTS (outf, ")");
3511 }
3512 else if (aop == 0 && s == 0 && aopcde == 8)
3513 OUTS (outf, "A0 = 0");
3514
3515 else if (aop == 0 && s == 1 && aopcde == 8)
3516 OUTS (outf, "A0 = A0 (S)");
3517
3518 else if (aop == 1 && s == 0 && aopcde == 8)
3519 OUTS (outf, "A1 = 0");
3520
3521 else if (aop == 1 && s == 1 && aopcde == 8)
3522 OUTS (outf, "A1 = A1 (S)");
3523
3524 else if (aop == 2 && s == 0 && aopcde == 8)
3525 OUTS (outf, "A1 = A0 = 0");
3526
3527 else if (aop == 2 && s == 1 && aopcde == 8)
3528 OUTS (outf, "A1 = A1 (S), A0 = A0 (S)");
3529
3530 else if (aop == 3 && s == 0 && aopcde == 8)
3531 OUTS (outf, "A0 = A1");
3532
3533 else if (aop == 3 && s == 1 && aopcde == 8)
3534 OUTS (outf, "A1 = A0");
3535
3536 else if (aop == 1 && aopcde == 9 && s == 0)
3537 {
3538 OUTS (outf, "A0.X = ");
3539 OUTS (outf, dregs_lo (src0));
3540 }
3541 else if (aop == 1 && HL == 0 && aopcde == 11)
3542 {
3543 OUTS (outf, dregs_lo (dst0));
3544 OUTS (outf, " = (A0 += A1)");
3545 }
3546 else if (aop == 3 && HL == 0 && aopcde == 16)
3547 OUTS (outf, "A1 = ABS A0, A0 = ABS A0");
3548
3549 else if (aop == 0 && aopcde == 23 && HL == 1)
3550 {
3551 OUTS (outf, dregs (dst0));
3552 OUTS (outf, " = BYTEOP3P (");
3553 OUTS (outf, dregs (src0 + 1));
3554 OUTS (outf, ":");
3555 OUTS (outf, imm5d (src0));
3556 OUTS (outf, ", ");
3557 OUTS (outf, dregs (src1 + 1));
3558 OUTS (outf, ":");
3559 OUTS (outf, imm5d (src1));
3560 OUTS (outf, ") (HI");
3561 if (s == 1)
3562 OUTS (outf, ", R)");
3563 else
3564 OUTS (outf, ")");
3565 }
3566 else if (aop == 3 && aopcde == 9 && s == 0)
3567 {
3568 OUTS (outf, "A1.X = ");
3569 OUTS (outf, dregs_lo (src0));
3570 }
3571 else if (aop == 1 && HL == 1 && aopcde == 16)
3572 OUTS (outf, "A1 = ABS A1");
3573
3574 else if (aop == 0 && HL == 1 && aopcde == 16)
3575 OUTS (outf, "A1 = ABS A0");
3576
3577 else if (aop == 2 && aopcde == 9 && s == 1)
3578 {
3579 OUTS (outf, "A1 = ");
3580 OUTS (outf, dregs (src0));
3581 }
3582 else if (HL == 0 && aop == 3 && aopcde == 12)
3583 {
3584 OUTS (outf, dregs_lo (dst0));
3585 OUTS (outf, " = ");
3586 OUTS (outf, dregs (src0));
3587 OUTS (outf, " (RND)");
3588 }
3589 else if (aop == 1 && HL == 0 && aopcde == 16)
3590 OUTS (outf, "A0 = ABS A1");
3591
3592 else if (aop == 0 && HL == 0 && aopcde == 16)
3593 OUTS (outf, "A0 = ABS A0");
3594
3595 else if (aop == 3 && HL == 0 && aopcde == 15)
3596 {
3597 OUTS (outf, dregs (dst0));
3598 OUTS (outf, " = -");
3599 OUTS (outf, dregs (src0));
3600 OUTS (outf, " (V)");
3601 }
3602 else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
3603 {
3604 OUTS (outf, dregs (dst0));
3605 OUTS (outf, " = -");
3606 OUTS (outf, dregs (src0));
3607 OUTS (outf, " (S)");
3608 }
3609 else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
3610 {
3611 OUTS (outf, dregs (dst0));
3612 OUTS (outf, " = -");
3613 OUTS (outf, dregs (src0));
3614 OUTS (outf, " (NS)");
3615 }
3616 else if (aop == 1 && HL == 1 && aopcde == 11)
3617 {
3618 OUTS (outf, dregs_hi (dst0));
3619 OUTS (outf, " = (A0 += A1)");
3620 }
3621 else if (aop == 2 && aopcde == 11 && s == 0)
3622 OUTS (outf, "A0 += A1");
3623
3624 else if (aop == 2 && aopcde == 11 && s == 1)
3625 OUTS (outf, "A0 += A1 (W32)");
3626
3627 else if (aop == 3 && HL == 0 && aopcde == 14)
3628 OUTS (outf, "A1 = -A1, A0 = -A0");
3629
3630 else if (HL == 1 && aop == 3 && aopcde == 12)
3631 {
3632 OUTS (outf, dregs_hi (dst0));
3633 OUTS (outf, " = ");
3634 OUTS (outf, dregs (src0));
3635 OUTS (outf, " (RND)");
3636 }
3637 else if (aop == 0 && aopcde == 23 && HL == 0)
3638 {
3639 OUTS (outf, dregs (dst0));
3640 OUTS (outf, " = BYTEOP3P (");
3641 OUTS (outf, dregs (src0 + 1));
3642 OUTS (outf, ":");
3643 OUTS (outf, imm5d (src0));
3644 OUTS (outf, ", ");
3645 OUTS (outf, dregs (src1 + 1));
3646 OUTS (outf, ":");
3647 OUTS (outf, imm5d (src1));
3648 OUTS (outf, ") (LO");
3649 if (s == 1)
3650 OUTS (outf, ", R)");
3651 else
3652 OUTS (outf, ")");
3653 }
3654 else if (aop == 0 && HL == 0 && aopcde == 14)
3655 OUTS (outf, "A0 = -A0");
3656
3657 else if (aop == 1 && HL == 0 && aopcde == 14)
3658 OUTS (outf, "A0 = -A1");
3659
3660 else if (aop == 0 && HL == 1 && aopcde == 14)
3661 OUTS (outf, "A1 = -A0");
3662
3663 else if (aop == 1 && HL == 1 && aopcde == 14)
3664 OUTS (outf, "A1 = -A1");
3665
3666 else if (aop == 0 && aopcde == 12)
3667 {
3668 OUTS (outf, dregs_hi (dst0));
3669 OUTS (outf, " = ");
3670 OUTS (outf, dregs_lo (dst0));
3671 OUTS (outf, " = SIGN (");
3672 OUTS (outf, dregs_hi (src0));
3673 OUTS (outf, ") * ");
3674 OUTS (outf, dregs_hi (src1));
3675 OUTS (outf, " + SIGN (");
3676 OUTS (outf, dregs_lo (src0));
3677 OUTS (outf, ") * ");
3678 OUTS (outf, dregs_lo (src1));
3679 }
3680 else if (aop == 2 && aopcde == 0)
3681 {
3682 OUTS (outf, dregs (dst0));
3683 OUTS (outf, " = ");
3684 OUTS (outf, dregs (src0));
3685 OUTS (outf, " -|+ ");
3686 OUTS (outf, dregs (src1));
3687 amod0 (s, x, outf);
3688 }
3689 else if (aop == 1 && aopcde == 12)
3690 {
3691 OUTS (outf, dregs (dst1));
3692 OUTS (outf, " = A1.L + A1.H, ");
3693 OUTS (outf, dregs (dst0));
3694 OUTS (outf, " = A0.L + A0.H");
3695 }
3696 else if (aop == 2 && aopcde == 4)
3697 {
3698 OUTS (outf, dregs (dst1));
3699 OUTS (outf, " = ");
3700 OUTS (outf, dregs (src0));
3701 OUTS (outf, " + ");
3702 OUTS (outf, dregs (src1));
3703 OUTS (outf, ", ");
3704 OUTS (outf, dregs (dst0));
3705 OUTS (outf, " = ");
3706 OUTS (outf, dregs (src0));
3707 OUTS (outf, " - ");
3708 OUTS (outf, dregs (src1));
3709 amod1 (s, x, outf);
3710 }
3711 else if (HL == 0 && aopcde == 1)
3712 {
3713 OUTS (outf, dregs (dst1));
3714 OUTS (outf, " = ");
3715 OUTS (outf, dregs (src0));
3716 OUTS (outf, " +|+ ");
3717 OUTS (outf, dregs (src1));
3718 OUTS (outf, ", ");
3719 OUTS (outf, dregs (dst0));
3720 OUTS (outf, " = ");
3721 OUTS (outf, dregs (src0));
3722 OUTS (outf, " -|- ");
3723 OUTS (outf, dregs (src1));
3724 amod0amod2 (s, x, aop, outf);
3725 }
3726 else if (aop == 0 && aopcde == 11)
3727 {
3728 OUTS (outf, dregs (dst0));
3729 OUTS (outf, " = (A0 += A1)");
3730 }
3731 else if (aop == 0 && aopcde == 10)
3732 {
3733 OUTS (outf, dregs_lo (dst0));
3734 OUTS (outf, " = A0.X");
3735 }
3736 else if (aop == 1 && aopcde == 10)
3737 {
3738 OUTS (outf, dregs_lo (dst0));
3739 OUTS (outf, " = A1.X");
3740 }
3741 else if (aop == 1 && aopcde == 0)
3742 {
3743 OUTS (outf, dregs (dst0));
3744 OUTS (outf, " = ");
3745 OUTS (outf, dregs (src0));
3746 OUTS (outf, " +|- ");
3747 OUTS (outf, dregs (src1));
3748 amod0 (s, x, outf);
3749 }
3750 else if (aop == 3 && aopcde == 0)
3751 {
3752 OUTS (outf, dregs (dst0));
3753 OUTS (outf, " = ");
3754 OUTS (outf, dregs (src0));
3755 OUTS (outf, " -|- ");
3756 OUTS (outf, dregs (src1));
3757 amod0 (s, x, outf);
3758 }
3759 else if (aop == 1 && aopcde == 4)
3760 {
3761 OUTS (outf, dregs (dst0));
3762 OUTS (outf, " = ");
3763 OUTS (outf, dregs (src0));
3764 OUTS (outf, " - ");
3765 OUTS (outf, dregs (src1));
3766 amod1 (s, x, outf);
3767 }
3768 else if (aop == 0 && aopcde == 17)
3769 {
3770 OUTS (outf, dregs (dst1));
3771 OUTS (outf, " = A1 + A0, ");
3772 OUTS (outf, dregs (dst0));
3773 OUTS (outf, " = A1 - A0");
3774 amod1 (s, x, outf);
3775 }
3776 else if (aop == 1 && aopcde == 17)
3777 {
3778 OUTS (outf, dregs (dst1));
3779 OUTS (outf, " = A0 + A1, ");
3780 OUTS (outf, dregs (dst0));
3781 OUTS (outf, " = A0 - A1");
3782 amod1 (s, x, outf);
3783 }
3784 else if (aop == 0 && aopcde == 18)
3785 {
3786 OUTS (outf, "SAA (");
3787 OUTS (outf, dregs (src0 + 1));
3788 OUTS (outf, ":");
3789 OUTS (outf, imm5d (src0));
3790 OUTS (outf, ", ");
3791 OUTS (outf, dregs (src1 + 1));
3792 OUTS (outf, ":");
3793 OUTS (outf, imm5d (src1));
3794 OUTS (outf, ")");
3795 aligndir (s, outf);
3796 }
3797 else if (aop == 3 && aopcde == 18)
3798 OUTS (outf, "DISALGNEXCPT");
3799
3800 else if (aop == 0 && aopcde == 20)
3801 {
3802 OUTS (outf, dregs (dst0));
3803 OUTS (outf, " = BYTEOP1P (");
3804 OUTS (outf, dregs (src0 + 1));
3805 OUTS (outf, ":");
3806 OUTS (outf, imm5d (src0));
3807 OUTS (outf, ", ");
3808 OUTS (outf, dregs (src1 + 1));
3809 OUTS (outf, ":");
3810 OUTS (outf, imm5d (src1));
3811 OUTS (outf, ")");
3812 aligndir (s, outf);
3813 }
3814 else if (aop == 1 && aopcde == 20)
3815 {
3816 OUTS (outf, dregs (dst0));
3817 OUTS (outf, " = BYTEOP1P (");
3818 OUTS (outf, dregs (src0 + 1));
3819 OUTS (outf, ":");
3820 OUTS (outf, imm5d (src0));
3821 OUTS (outf, ", ");
3822 OUTS (outf, dregs (src1 + 1));
3823 OUTS (outf, ":");
3824 OUTS (outf, imm5d (src1));
3825 OUTS (outf, ") (T");
3826 if (s == 1)
3827 OUTS (outf, ", R)");
3828 else
3829 OUTS (outf, ")");
3830 }
3831 else if (aop == 0 && aopcde == 21)
3832 {
3833 OUTS (outf, "(");
3834 OUTS (outf, dregs (dst1));
3835 OUTS (outf, ", ");
3836 OUTS (outf, dregs (dst0));
3837 OUTS (outf, ") = BYTEOP16P (");
3838 OUTS (outf, dregs (src0 + 1));
3839 OUTS (outf, ":");
3840 OUTS (outf, imm5d (src0));
3841 OUTS (outf, ", ");
3842 OUTS (outf, dregs (src1 + 1));
3843 OUTS (outf, ":");
3844 OUTS (outf, imm5d (src1));
3845 OUTS (outf, ")");
3846 aligndir (s, outf);
3847 }
3848 else if (aop == 1 && aopcde == 21)
3849 {
3850 OUTS (outf, "(");
3851 OUTS (outf, dregs (dst1));
3852 OUTS (outf, ", ");
3853 OUTS (outf, dregs (dst0));
3854 OUTS (outf, ") = BYTEOP16M (");
3855 OUTS (outf, dregs (src0 + 1));
3856 OUTS (outf, ":");
3857 OUTS (outf, imm5d (src0));
3858 OUTS (outf, ", ");
3859 OUTS (outf, dregs (src1 + 1));
3860 OUTS (outf, ":");
3861 OUTS (outf, imm5d (src1));
3862 OUTS (outf, ")");
3863 aligndir (s, outf);
3864 }
3865 else if (aop == 2 && aopcde == 7)
3866 {
3867 OUTS (outf, dregs (dst0));
3868 OUTS (outf, " = ABS ");
3869 OUTS (outf, dregs (src0));
3870 }
3871 else if (aop == 1 && aopcde == 7)
3872 {
3873 OUTS (outf, dregs (dst0));
3874 OUTS (outf, " = MIN (");
3875 OUTS (outf, dregs (src0));
3876 OUTS (outf, ", ");
3877 OUTS (outf, dregs (src1));
3878 OUTS (outf, ")");
3879 }
3880 else if (aop == 0 && aopcde == 7)
3881 {
3882 OUTS (outf, dregs (dst0));
3883 OUTS (outf, " = MAX (");
3884 OUTS (outf, dregs (src0));
3885 OUTS (outf, ", ");
3886 OUTS (outf, dregs (src1));
3887 OUTS (outf, ")");
3888 }
3889 else if (aop == 2 && aopcde == 6)
3890 {
3891 OUTS (outf, dregs (dst0));
3892 OUTS (outf, " = ABS ");
3893 OUTS (outf, dregs (src0));
3894 OUTS (outf, " (V)");
3895 }
3896 else if (aop == 1 && aopcde == 6)
3897 {
3898 OUTS (outf, dregs (dst0));
3899 OUTS (outf, " = MIN (");
3900 OUTS (outf, dregs (src0));
3901 OUTS (outf, ", ");
3902 OUTS (outf, dregs (src1));
3903 OUTS (outf, ") (V)");
3904 }
3905 else if (aop == 0 && aopcde == 6)
3906 {
3907 OUTS (outf, dregs (dst0));
3908 OUTS (outf, " = MAX (");
3909 OUTS (outf, dregs (src0));
3910 OUTS (outf, ", ");
3911 OUTS (outf, dregs (src1));
3912 OUTS (outf, ") (V)");
3913 }
3914 else if (HL == 1 && aopcde == 1)
3915 {
3916 OUTS (outf, dregs (dst1));
3917 OUTS (outf, " = ");
3918 OUTS (outf, dregs (src0));
3919 OUTS (outf, " +|- ");
3920 OUTS (outf, dregs (src1));
3921 OUTS (outf, ", ");
3922 OUTS (outf, dregs (dst0));
3923 OUTS (outf, " = ");
3924 OUTS (outf, dregs (src0));
3925 OUTS (outf, " -|+ ");
3926 OUTS (outf, dregs (src1));
3927 amod0amod2 (s, x, aop, outf);
3928 }
3929 else if (aop == 0 && aopcde == 4)
3930 {
3931 OUTS (outf, dregs (dst0));
3932 OUTS (outf, " = ");
3933 OUTS (outf, dregs (src0));
3934 OUTS (outf, " + ");
3935 OUTS (outf, dregs (src1));
3936 amod1 (s, x, outf);
3937 }
3938 else if (aop == 0 && aopcde == 0)
3939 {
3940 OUTS (outf, dregs (dst0));
3941 OUTS (outf, " = ");
3942 OUTS (outf, dregs (src0));
3943 OUTS (outf, " +|+ ");
3944 OUTS (outf, dregs (src1));
3945 amod0 (s, x, outf);
3946 }
3947 else if (aop == 0 && aopcde == 24)
3948 {
3949 OUTS (outf, dregs (dst0));
3950 OUTS (outf, " = BYTEPACK (");
3951 OUTS (outf, dregs (src0));
3952 OUTS (outf, ", ");
3953 OUTS (outf, dregs (src1));
3954 OUTS (outf, ")");
3955 }
3956 else if (aop == 1 && aopcde == 24)
3957 {
3958 OUTS (outf, "(");
3959 OUTS (outf, dregs (dst1));
3960 OUTS (outf, ", ");
3961 OUTS (outf, dregs (dst0));
3962 OUTS (outf, ") = BYTEUNPACK ");
3963 OUTS (outf, dregs (src0 + 1));
3964 OUTS (outf, ":");
3965 OUTS (outf, imm5d (src0));
3966 aligndir (s, outf);
3967 }
3968 else if (aopcde == 13)
3969 {
3970 OUTS (outf, "(");
3971 OUTS (outf, dregs (dst1));
3972 OUTS (outf, ", ");
3973 OUTS (outf, dregs (dst0));
3974 OUTS (outf, ") = SEARCH ");
3975 OUTS (outf, dregs (src0));
3976 OUTS (outf, " (");
3977 searchmod (aop, outf);
3978 OUTS (outf, ")");
3979 }
3980 else
3981 return 0;
3982
3983 return 4;
3984 }
3985
3986 static int
3987 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
3988 {
3989 /* dsp32shift
3990 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
3991 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
3992 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
3993 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
3994 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
3995 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
3996 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
3997 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
3998 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
3999 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
4000 const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
4001
4002 if (HLs == 0 && sop == 0 && sopcde == 0)
4003 {
4004 OUTS (outf, dregs_lo (dst0));
4005 OUTS (outf, " = ASHIFT ");
4006 OUTS (outf, dregs_lo (src1));
4007 OUTS (outf, " BY ");
4008 OUTS (outf, dregs_lo (src0));
4009 }
4010 else if (HLs == 1 && sop == 0 && sopcde == 0)
4011 {
4012 OUTS (outf, dregs_lo (dst0));
4013 OUTS (outf, " = ASHIFT ");
4014 OUTS (outf, dregs_hi (src1));
4015 OUTS (outf, " BY ");
4016 OUTS (outf, dregs_lo (src0));
4017 }
4018 else if (HLs == 2 && sop == 0 && sopcde == 0)
4019 {
4020 OUTS (outf, dregs_hi (dst0));
4021 OUTS (outf, " = ASHIFT ");
4022 OUTS (outf, dregs_lo (src1));
4023 OUTS (outf, " BY ");
4024 OUTS (outf, dregs_lo (src0));
4025 }
4026 else if (HLs == 3 && sop == 0 && sopcde == 0)
4027 {
4028 OUTS (outf, dregs_hi (dst0));
4029 OUTS (outf, " = ASHIFT ");
4030 OUTS (outf, dregs_hi (src1));
4031 OUTS (outf, " BY ");
4032 OUTS (outf, dregs_lo (src0));
4033 }
4034 else if (HLs == 0 && sop == 1 && sopcde == 0)
4035 {
4036 OUTS (outf, dregs_lo (dst0));
4037 OUTS (outf, " = ASHIFT ");
4038 OUTS (outf, dregs_lo (src1));
4039 OUTS (outf, " BY ");
4040 OUTS (outf, dregs_lo (src0));
4041 OUTS (outf, " (S)");
4042 }
4043 else if (HLs == 1 && sop == 1 && sopcde == 0)
4044 {
4045 OUTS (outf, dregs_lo (dst0));
4046 OUTS (outf, " = ASHIFT ");
4047 OUTS (outf, dregs_hi (src1));
4048 OUTS (outf, " BY ");
4049 OUTS (outf, dregs_lo (src0));
4050 OUTS (outf, " (S)");
4051 }
4052 else if (HLs == 2 && sop == 1 && sopcde == 0)
4053 {
4054 OUTS (outf, dregs_hi (dst0));
4055 OUTS (outf, " = ASHIFT ");
4056 OUTS (outf, dregs_lo (src1));
4057 OUTS (outf, " BY ");
4058 OUTS (outf, dregs_lo (src0));
4059 OUTS (outf, " (S)");
4060 }
4061 else if (HLs == 3 && sop == 1 && sopcde == 0)
4062 {
4063 OUTS (outf, dregs_hi (dst0));
4064 OUTS (outf, " = ASHIFT ");
4065 OUTS (outf, dregs_hi (src1));
4066 OUTS (outf, " BY ");
4067 OUTS (outf, dregs_lo (src0));
4068 OUTS (outf, " (S)");
4069 }
4070 else if (sop == 2 && sopcde == 0)
4071 {
4072 OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
4073 OUTS (outf, " = LSHIFT ");
4074 OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
4075 OUTS (outf, " BY ");
4076 OUTS (outf, dregs_lo (src0));
4077 }
4078 else if (sop == 0 && sopcde == 3)
4079 {
4080 OUTS (outf, acc01);
4081 OUTS (outf, " = ASHIFT ");
4082 OUTS (outf, acc01);
4083 OUTS (outf, " BY ");
4084 OUTS (outf, dregs_lo (src0));
4085 }
4086 else if (sop == 1 && sopcde == 3)
4087 {
4088 OUTS (outf, acc01);
4089 OUTS (outf, " = LSHIFT ");
4090 OUTS (outf, acc01);
4091 OUTS (outf, " BY ");
4092 OUTS (outf, dregs_lo (src0));
4093 }
4094 else if (sop == 2 && sopcde == 3)
4095 {
4096 OUTS (outf, acc01);
4097 OUTS (outf, " = ROT ");
4098 OUTS (outf, acc01);
4099 OUTS (outf, " BY ");
4100 OUTS (outf, dregs_lo (src0));
4101 }
4102 else if (sop == 3 && sopcde == 3)
4103 {
4104 OUTS (outf, dregs (dst0));
4105 OUTS (outf, " = ROT ");
4106 OUTS (outf, dregs (src1));
4107 OUTS (outf, " BY ");
4108 OUTS (outf, dregs_lo (src0));
4109 }
4110 else if (sop == 1 && sopcde == 1)
4111 {
4112 OUTS (outf, dregs (dst0));
4113 OUTS (outf, " = ASHIFT ");
4114 OUTS (outf, dregs (src1));
4115 OUTS (outf, " BY ");
4116 OUTS (outf, dregs_lo (src0));
4117 OUTS (outf, " (V, S)");
4118 }
4119 else if (sop == 0 && sopcde == 1)
4120 {
4121 OUTS (outf, dregs (dst0));
4122 OUTS (outf, " = ASHIFT ");
4123 OUTS (outf, dregs (src1));
4124 OUTS (outf, " BY ");
4125 OUTS (outf, dregs_lo (src0));
4126 OUTS (outf, " (V)");
4127 }
4128 else if (sop == 0 && sopcde == 2)
4129 {
4130 OUTS (outf, dregs (dst0));
4131 OUTS (outf, " = ASHIFT ");
4132 OUTS (outf, dregs (src1));
4133 OUTS (outf, " BY ");
4134 OUTS (outf, dregs_lo (src0));
4135 }
4136 else if (sop == 1 && sopcde == 2)
4137 {
4138 OUTS (outf, dregs (dst0));
4139 OUTS (outf, " = ASHIFT ");
4140 OUTS (outf, dregs (src1));
4141 OUTS (outf, " BY ");
4142 OUTS (outf, dregs_lo (src0));
4143 OUTS (outf, " (S)");
4144 }
4145 else if (sop == 2 && sopcde == 2)
4146 {
4147 OUTS (outf, dregs (dst0));
4148 OUTS (outf, " = LSHIFT ");
4149 OUTS (outf, dregs (src1));
4150 OUTS (outf, " BY ");
4151 OUTS (outf, dregs_lo (src0));
4152 }
4153 else if (sop == 3 && sopcde == 2)
4154 {
4155 OUTS (outf, dregs (dst0));
4156 OUTS (outf, " = ROT ");
4157 OUTS (outf, dregs (src1));
4158 OUTS (outf, " BY ");
4159 OUTS (outf, dregs_lo (src0));
4160 }
4161 else if (sop == 2 && sopcde == 1)
4162 {
4163 OUTS (outf, dregs (dst0));
4164 OUTS (outf, " = LSHIFT ");
4165 OUTS (outf, dregs (src1));
4166 OUTS (outf, " BY ");
4167 OUTS (outf, dregs_lo (src0));
4168 OUTS (outf, " (V)");
4169 }
4170 else if (sop == 0 && sopcde == 4)
4171 {
4172 OUTS (outf, dregs (dst0));
4173 OUTS (outf, " = PACK (");
4174 OUTS (outf, dregs_lo (src1));
4175 OUTS (outf, ", ");
4176 OUTS (outf, dregs_lo (src0));
4177 OUTS (outf, ")");
4178 }
4179 else if (sop == 1 && sopcde == 4)
4180 {
4181 OUTS (outf, dregs (dst0));
4182 OUTS (outf, " = PACK (");
4183 OUTS (outf, dregs_lo (src1));
4184 OUTS (outf, ", ");
4185 OUTS (outf, dregs_hi (src0));
4186 OUTS (outf, ")");
4187 }
4188 else if (sop == 2 && sopcde == 4)
4189 {
4190 OUTS (outf, dregs (dst0));
4191 OUTS (outf, " = PACK (");
4192 OUTS (outf, dregs_hi (src1));
4193 OUTS (outf, ", ");
4194 OUTS (outf, dregs_lo (src0));
4195 OUTS (outf, ")");
4196 }
4197 else if (sop == 3 && sopcde == 4)
4198 {
4199 OUTS (outf, dregs (dst0));
4200 OUTS (outf, " = PACK (");
4201 OUTS (outf, dregs_hi (src1));
4202 OUTS (outf, ", ");
4203 OUTS (outf, dregs_hi (src0));
4204 OUTS (outf, ")");
4205 }
4206 else if (sop == 0 && sopcde == 5)
4207 {
4208 OUTS (outf, dregs_lo (dst0));
4209 OUTS (outf, " = SIGNBITS ");
4210 OUTS (outf, dregs (src1));
4211 }
4212 else if (sop == 1 && sopcde == 5)
4213 {
4214 OUTS (outf, dregs_lo (dst0));
4215 OUTS (outf, " = SIGNBITS ");
4216 OUTS (outf, dregs_lo (src1));
4217 }
4218 else if (sop == 2 && sopcde == 5)
4219 {
4220 OUTS (outf, dregs_lo (dst0));
4221 OUTS (outf, " = SIGNBITS ");
4222 OUTS (outf, dregs_hi (src1));
4223 }
4224 else if (sop == 0 && sopcde == 6)
4225 {
4226 OUTS (outf, dregs_lo (dst0));
4227 OUTS (outf, " = SIGNBITS A0");
4228 }
4229 else if (sop == 1 && sopcde == 6)
4230 {
4231 OUTS (outf, dregs_lo (dst0));
4232 OUTS (outf, " = SIGNBITS A1");
4233 }
4234 else if (sop == 3 && sopcde == 6)
4235 {
4236 OUTS (outf, dregs_lo (dst0));
4237 OUTS (outf, " = ONES ");
4238 OUTS (outf, dregs (src1));
4239 }
4240 else if (sop == 0 && sopcde == 7)
4241 {
4242 OUTS (outf, dregs_lo (dst0));
4243 OUTS (outf, " = EXPADJ (");
4244 OUTS (outf, dregs (src1));
4245 OUTS (outf, ", ");
4246 OUTS (outf, dregs_lo (src0));
4247 OUTS (outf, ")");
4248 }
4249 else if (sop == 1 && sopcde == 7)
4250 {
4251 OUTS (outf, dregs_lo (dst0));
4252 OUTS (outf, " = EXPADJ (");
4253 OUTS (outf, dregs (src1));
4254 OUTS (outf, ", ");
4255 OUTS (outf, dregs_lo (src0));
4256 OUTS (outf, ") (V)");
4257 }
4258 else if (sop == 2 && sopcde == 7)
4259 {
4260 OUTS (outf, dregs_lo (dst0));
4261 OUTS (outf, " = EXPADJ (");
4262 OUTS (outf, dregs_lo (src1));
4263 OUTS (outf, ", ");
4264 OUTS (outf, dregs_lo (src0));
4265 OUTS (outf, ")");
4266 }
4267 else if (sop == 3 && sopcde == 7)
4268 {
4269 OUTS (outf, dregs_lo (dst0));
4270 OUTS (outf, " = EXPADJ (");
4271 OUTS (outf, dregs_hi (src1));
4272 OUTS (outf, ", ");
4273 OUTS (outf, dregs_lo (src0));
4274 OUTS (outf, ")");
4275 }
4276 else if (sop == 0 && sopcde == 8)
4277 {
4278 OUTS (outf, "BITMUX (");
4279 OUTS (outf, dregs (src0));
4280 OUTS (outf, ", ");
4281 OUTS (outf, dregs (src1));
4282 OUTS (outf, ", A0) (ASR)");
4283 }
4284 else if (sop == 1 && sopcde == 8)
4285 {
4286 OUTS (outf, "BITMUX (");
4287 OUTS (outf, dregs (src0));
4288 OUTS (outf, ", ");
4289 OUTS (outf, dregs (src1));
4290 OUTS (outf, ", A0) (ASL)");
4291 }
4292 else if (sop == 0 && sopcde == 9)
4293 {
4294 OUTS (outf, dregs_lo (dst0));
4295 OUTS (outf, " = VIT_MAX (");
4296 OUTS (outf, dregs (src1));
4297 OUTS (outf, ") (ASL)");
4298 }
4299 else if (sop == 1 && sopcde == 9)
4300 {
4301 OUTS (outf, dregs_lo (dst0));
4302 OUTS (outf, " = VIT_MAX (");
4303 OUTS (outf, dregs (src1));
4304 OUTS (outf, ") (ASR)");
4305 }
4306 else if (sop == 2 && sopcde == 9)
4307 {
4308 OUTS (outf, dregs (dst0));
4309 OUTS (outf, " = VIT_MAX (");
4310 OUTS (outf, dregs (src1));
4311 OUTS (outf, ", ");
4312 OUTS (outf, dregs (src0));
4313 OUTS (outf, ") (ASL)");
4314 }
4315 else if (sop == 3 && sopcde == 9)
4316 {
4317 OUTS (outf, dregs (dst0));
4318 OUTS (outf, " = VIT_MAX (");
4319 OUTS (outf, dregs (src1));
4320 OUTS (outf, ", ");
4321 OUTS (outf, dregs (src0));
4322 OUTS (outf, ") (ASR)");
4323 }
4324 else if (sop == 0 && sopcde == 10)
4325 {
4326 OUTS (outf, dregs (dst0));
4327 OUTS (outf, " = EXTRACT (");
4328 OUTS (outf, dregs (src1));
4329 OUTS (outf, ", ");
4330 OUTS (outf, dregs_lo (src0));
4331 OUTS (outf, ") (Z)");
4332 }
4333 else if (sop == 1 && sopcde == 10)
4334 {
4335 OUTS (outf, dregs (dst0));
4336 OUTS (outf, " = EXTRACT (");
4337 OUTS (outf, dregs (src1));
4338 OUTS (outf, ", ");
4339 OUTS (outf, dregs_lo (src0));
4340 OUTS (outf, ") (X)");
4341 }
4342 else if (sop == 2 && sopcde == 10)
4343 {
4344 OUTS (outf, dregs (dst0));
4345 OUTS (outf, " = DEPOSIT (");
4346 OUTS (outf, dregs (src1));
4347 OUTS (outf, ", ");
4348 OUTS (outf, dregs (src0));
4349 OUTS (outf, ")");
4350 }
4351 else if (sop == 3 && sopcde == 10)
4352 {
4353 OUTS (outf, dregs (dst0));
4354 OUTS (outf, " = DEPOSIT (");
4355 OUTS (outf, dregs (src1));
4356 OUTS (outf, ", ");
4357 OUTS (outf, dregs (src0));
4358 OUTS (outf, ") (X)");
4359 }
4360 else if (sop == 0 && sopcde == 11)
4361 {
4362 OUTS (outf, dregs_lo (dst0));
4363 OUTS (outf, " = CC = BXORSHIFT (A0, ");
4364 OUTS (outf, dregs (src0));
4365 OUTS (outf, ")");
4366 }
4367 else if (sop == 1 && sopcde == 11)
4368 {
4369 OUTS (outf, dregs_lo (dst0));
4370 OUTS (outf, " = CC = BXOR (A0, ");
4371 OUTS (outf, dregs (src0));
4372 OUTS (outf, ")");
4373 }
4374 else if (sop == 0 && sopcde == 12)
4375 OUTS (outf, "A0 = BXORSHIFT (A0, A1, CC)");
4376
4377 else if (sop == 1 && sopcde == 12)
4378 {
4379 OUTS (outf, dregs_lo (dst0));
4380 OUTS (outf, " = CC = BXOR (A0, A1, CC)");
4381 }
4382 else if (sop == 0 && sopcde == 13)
4383 {
4384 OUTS (outf, dregs (dst0));
4385 OUTS (outf, " = ALIGN8 (");
4386 OUTS (outf, dregs (src1));
4387 OUTS (outf, ", ");
4388 OUTS (outf, dregs (src0));
4389 OUTS (outf, ")");
4390 }
4391 else if (sop == 1 && sopcde == 13)
4392 {
4393 OUTS (outf, dregs (dst0));
4394 OUTS (outf, " = ALIGN16 (");
4395 OUTS (outf, dregs (src1));
4396 OUTS (outf, ", ");
4397 OUTS (outf, dregs (src0));
4398 OUTS (outf, ")");
4399 }
4400 else if (sop == 2 && sopcde == 13)
4401 {
4402 OUTS (outf, dregs (dst0));
4403 OUTS (outf, " = ALIGN24 (");
4404 OUTS (outf, dregs (src1));
4405 OUTS (outf, ", ");
4406 OUTS (outf, dregs (src0));
4407 OUTS (outf, ")");
4408 }
4409 else
4410 return 0;
4411
4412 return 4;
4413 }
4414
4415 static int
4416 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4417 {
4418 /* dsp32shiftimm
4419 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4420 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
4421 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
4422 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4423 int src1 = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
4424 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
4425 int bit8 = ((iw1 >> 8) & 0x1);
4426 int immag = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4427 int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
4428 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
4429 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
4430 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
4431
4432
4433 if (sop == 0 && sopcde == 0)
4434 {
4435 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4436 OUTS (outf, " = ");
4437 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4438 OUTS (outf, " >>> ");
4439 OUTS (outf, uimm4 (newimmag));
4440 }
4441 else if (sop == 1 && sopcde == 0 && bit8 == 0)
4442 {
4443 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4444 OUTS (outf, " = ");
4445 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4446 OUTS (outf, " << ");
4447 OUTS (outf, uimm4 (immag));
4448 OUTS (outf, " (S)");
4449 }
4450 else if (sop == 1 && sopcde == 0 && bit8 == 1)
4451 {
4452 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4453 OUTS (outf, " = ");
4454 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4455 OUTS (outf, " >>> ");
4456 OUTS (outf, uimm4 (newimmag));
4457 OUTS (outf, " (S)");
4458 }
4459 else if (sop == 2 && sopcde == 0 && bit8 == 0)
4460 {
4461 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4462 OUTS (outf, " = ");
4463 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4464 OUTS (outf, " << ");
4465 OUTS (outf, uimm4 (immag));
4466 }
4467 else if (sop == 2 && sopcde == 0 && bit8 == 1)
4468 {
4469 OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
4470 OUTS (outf, " = ");
4471 OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
4472 OUTS (outf, " >> ");
4473 OUTS (outf, uimm4 (newimmag));
4474 }
4475 else if (sop == 2 && sopcde == 3 && HLs == 1)
4476 {
4477 OUTS (outf, "A1 = ROT A1 BY ");
4478 OUTS (outf, imm6 (immag));
4479 }
4480 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
4481 {
4482 OUTS (outf, "A0 = A0 << ");
4483 OUTS (outf, uimm5 (immag));
4484 }
4485 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
4486 {
4487 OUTS (outf, "A0 = A0 >>> ");
4488 OUTS (outf, uimm5 (newimmag));
4489 }
4490 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
4491 {
4492 OUTS (outf, "A1 = A1 << ");
4493 OUTS (outf, uimm5 (immag));
4494 }
4495 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
4496 {
4497 OUTS (outf, "A1 = A1 >>> ");
4498 OUTS (outf, uimm5 (newimmag));
4499 }
4500 else if (sop == 1 && sopcde == 3 && HLs == 0)
4501 {
4502 OUTS (outf, "A0 = A0 >> ");
4503 OUTS (outf, uimm5 (newimmag));
4504 }
4505 else if (sop == 1 && sopcde == 3 && HLs == 1)
4506 {
4507 OUTS (outf, "A1 = A1 >> ");
4508 OUTS (outf, uimm5 (newimmag));
4509 }
4510 else if (sop == 2 && sopcde == 3 && HLs == 0)
4511 {
4512 OUTS (outf, "A0 = ROT A0 BY ");
4513 OUTS (outf, imm6 (immag));
4514 }
4515 else if (sop == 1 && sopcde == 1 && bit8 == 0)
4516 {
4517 OUTS (outf, dregs (dst0));
4518 OUTS (outf, " = ");
4519 OUTS (outf, dregs (src1));
4520 OUTS (outf, " << ");
4521 OUTS (outf, uimm5 (immag));
4522 OUTS (outf, " (V, S)");
4523 }
4524 else if (sop == 1 && sopcde == 1 && bit8 == 1)
4525 {
4526 OUTS (outf, dregs (dst0));
4527 OUTS (outf, " = ");
4528 OUTS (outf, dregs (src1));
4529 OUTS (outf, " >>> ");
4530 OUTS (outf, imm5 (-immag));
4531 OUTS (outf, " (V, S)");
4532 }
4533 else if (sop == 2 && sopcde == 1 && bit8 == 1)
4534 {
4535 OUTS (outf, dregs (dst0));
4536 OUTS (outf, " = ");
4537 OUTS (outf, dregs (src1));
4538 OUTS (outf, " >> ");
4539 OUTS (outf, uimm5 (newimmag));
4540 OUTS (outf, " (V)");
4541 }
4542 else if (sop == 2 && sopcde == 1 && bit8 == 0)
4543 {
4544 OUTS (outf, dregs (dst0));
4545 OUTS (outf, " = ");
4546 OUTS (outf, dregs (src1));
4547 OUTS (outf, " << ");
4548 OUTS (outf, imm5 (immag));
4549 OUTS (outf, " (V)");
4550 }
4551 else if (sop == 0 && sopcde == 1)
4552 {
4553 OUTS (outf, dregs (dst0));
4554 OUTS (outf, " = ");
4555 OUTS (outf, dregs (src1));
4556 OUTS (outf, " >>> ");
4557 OUTS (outf, uimm5 (newimmag));
4558 OUTS (outf, " (V)");
4559 }
4560 else if (sop == 1 && sopcde == 2)
4561 {
4562 OUTS (outf, dregs (dst0));
4563 OUTS (outf, " = ");
4564 OUTS (outf, dregs (src1));
4565 OUTS (outf, " << ");
4566 OUTS (outf, uimm5 (immag));
4567 OUTS (outf, " (S)");
4568 }
4569 else if (sop == 2 && sopcde == 2 && bit8 == 1)
4570 {
4571 OUTS (outf, dregs (dst0));
4572 OUTS (outf, " = ");
4573 OUTS (outf, dregs (src1));
4574 OUTS (outf, " >> ");
4575 OUTS (outf, uimm5 (newimmag));
4576 }
4577 else if (sop == 2 && sopcde == 2 && bit8 == 0)
4578 {
4579 OUTS (outf, dregs (dst0));
4580 OUTS (outf, " = ");
4581 OUTS (outf, dregs (src1));
4582 OUTS (outf, " << ");
4583 OUTS (outf, uimm5 (immag));
4584 }
4585 else if (sop == 3 && sopcde == 2)
4586 {
4587 OUTS (outf, dregs (dst0));
4588 OUTS (outf, " = ROT ");
4589 OUTS (outf, dregs (src1));
4590 OUTS (outf, " BY ");
4591 OUTS (outf, imm6 (immag));
4592 }
4593 else if (sop == 0 && sopcde == 2)
4594 {
4595 OUTS (outf, dregs (dst0));
4596 OUTS (outf, " = ");
4597 OUTS (outf, dregs (src1));
4598 OUTS (outf, " >>> ");
4599 OUTS (outf, uimm5 (newimmag));
4600 }
4601 else
4602 return 0;
4603
4604 return 4;
4605 }
4606
4607 static int
4608 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
4609 {
4610 /* pseudoDEBUG
4611 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4612 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
4613 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4614 int fn = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
4615 int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
4616 int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
4617
4618 if (parallel)
4619 return 0;
4620
4621 if (reg == 0 && fn == 3)
4622 OUTS (outf, "DBG A0");
4623
4624 else if (reg == 1 && fn == 3)
4625 OUTS (outf, "DBG A1");
4626
4627 else if (reg == 3 && fn == 3)
4628 OUTS (outf, "ABORT");
4629
4630 else if (reg == 4 && fn == 3)
4631 OUTS (outf, "HLT");
4632
4633 else if (reg == 5 && fn == 3)
4634 OUTS (outf, "DBGHALT");
4635
4636 else if (reg == 6 && fn == 3)
4637 {
4638 OUTS (outf, "DBGCMPLX (");
4639 OUTS (outf, dregs (grp));
4640 OUTS (outf, ")");
4641 }
4642 else if (reg == 7 && fn == 3)
4643 OUTS (outf, "DBG");
4644
4645 else if (grp == 0 && fn == 2)
4646 {
4647 OUTS (outf, "OUTC ");
4648 OUTS (outf, dregs (reg));
4649 }
4650 else if (fn == 0)
4651 {
4652 OUTS (outf, "DBG ");
4653 OUTS (outf, allregs (reg, grp));
4654 }
4655 else if (fn == 1)
4656 {
4657 OUTS (outf, "PRNT");
4658 OUTS (outf, allregs (reg, grp));
4659 }
4660 else
4661 return 0;
4662
4663 return 2;
4664 }
4665
4666 static int
4667 decode_pseudoOChar_0 (TIword iw0, disassemble_info *outf)
4668 {
4669 /* psedoOChar
4670 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4671 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
4672 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4673 int ch = ((iw0 >> PseudoChr_ch_bits) & PseudoChr_ch_mask);
4674
4675 if (parallel)
4676 return 0;
4677
4678 OUTS (outf, "OUTC ");
4679 OUTS (outf, uimm8 (ch));
4680
4681 return 2;
4682 }
4683
4684 static int
4685 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
4686 {
4687 /* pseudodbg_assert
4688 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
4689 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
4690 |.expected......................................................|
4691 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
4692 int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
4693 int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
4694 int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
4695 int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
4696
4697 if (parallel)
4698 return 0;
4699
4700 if (dbgop == 0)
4701 {
4702 OUTS (outf, "DBGA (");
4703 OUTS (outf, regs_lo (regtest, grp));
4704 OUTS (outf, ", ");
4705 OUTS (outf, uimm16 (expected));
4706 OUTS (outf, ")");
4707 }
4708 else if (dbgop == 1)
4709 {
4710 OUTS (outf, "DBGA (");
4711 OUTS (outf, regs_hi (regtest, grp));
4712 OUTS (outf, ", ");
4713 OUTS (outf, uimm16 (expected));
4714 OUTS (outf, ")");
4715 }
4716 else if (dbgop == 2)
4717 {
4718 OUTS (outf, "DBGAL (");
4719 OUTS (outf, allregs (regtest, grp));
4720 OUTS (outf, ", ");
4721 OUTS (outf, uimm16 (expected));
4722 OUTS (outf, ")");
4723 }
4724 else if (dbgop == 3)
4725 {
4726 OUTS (outf, "DBGAH (");
4727 OUTS (outf, allregs (regtest, grp));
4728 OUTS (outf, ", ");
4729 OUTS (outf, uimm16 (expected));
4730 OUTS (outf, ")");
4731 }
4732 else
4733 return 0;
4734 return 4;
4735 }
4736
4737 static int
4738 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4739 {
4740 bfd_byte buf[4];
4741 TIword iw0;
4742 TIword iw1;
4743 int status;
4744 int rv = 0;
4745
4746 status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
4747 /* FIXME */
4748 (void) status;
4749 status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
4750 /* FIXME */
4751 (void) status;
4752
4753 iw0 = bfd_getl16 (buf);
4754 iw1 = bfd_getl16 (buf + 2);
4755
4756 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
4757 {
4758 if (parallel)
4759 {
4760 OUTS (outf, "ILLEGAL");
4761 return 0;
4762 }
4763 OUTS (outf, "MNOP");
4764 return 4;
4765 }
4766 else if ((iw0 & 0xff00) == 0x0000)
4767 rv = decode_ProgCtrl_0 (iw0, outf);
4768 else if ((iw0 & 0xffc0) == 0x0240)
4769 rv = decode_CaCTRL_0 (iw0, outf);
4770 else if ((iw0 & 0xff80) == 0x0100)
4771 rv = decode_PushPopReg_0 (iw0, outf);
4772 else if ((iw0 & 0xfe00) == 0x0400)
4773 rv = decode_PushPopMultiple_0 (iw0, outf);
4774 else if ((iw0 & 0xfe00) == 0x0600)
4775 rv = decode_ccMV_0 (iw0, outf);
4776 else if ((iw0 & 0xf800) == 0x0800)
4777 rv = decode_CCflag_0 (iw0, outf);
4778 else if ((iw0 & 0xffe0) == 0x0200)
4779 rv = decode_CC2dreg_0 (iw0, outf);
4780 else if ((iw0 & 0xff00) == 0x0300)
4781 rv = decode_CC2stat_0 (iw0, outf);
4782 else if ((iw0 & 0xf000) == 0x1000)
4783 rv = decode_BRCC_0 (iw0, pc, outf);
4784 else if ((iw0 & 0xf000) == 0x2000)
4785 rv = decode_UJUMP_0 (iw0, pc, outf);
4786 else if ((iw0 & 0xf000) == 0x3000)
4787 rv = decode_REGMV_0 (iw0, outf);
4788 else if ((iw0 & 0xfc00) == 0x4000)
4789 rv = decode_ALU2op_0 (iw0, outf);
4790 else if ((iw0 & 0xfe00) == 0x4400)
4791 rv = decode_PTR2op_0 (iw0, outf);
4792 else if ((iw0 & 0xf800) == 0x4800)
4793 rv = decode_LOGI2op_0 (iw0, outf);
4794 else if ((iw0 & 0xf000) == 0x5000)
4795 rv = decode_COMP3op_0 (iw0, outf);
4796 else if ((iw0 & 0xf800) == 0x6000)
4797 rv = decode_COMPI2opD_0 (iw0, outf);
4798 else if ((iw0 & 0xf800) == 0x6800)
4799 rv = decode_COMPI2opP_0 (iw0, outf);
4800 else if ((iw0 & 0xf000) == 0x8000)
4801 rv = decode_LDSTpmod_0 (iw0, outf);
4802 else if ((iw0 & 0xff60) == 0x9e60)
4803 rv = decode_dagMODim_0 (iw0, outf);
4804 else if ((iw0 & 0xfff0) == 0x9f60)
4805 rv = decode_dagMODik_0 (iw0, outf);
4806 else if ((iw0 & 0xfc00) == 0x9c00)
4807 rv = decode_dspLDST_0 (iw0, outf);
4808 else if ((iw0 & 0xf000) == 0x9000)
4809 rv = decode_LDST_0 (iw0, outf);
4810 else if ((iw0 & 0xfc00) == 0xb800)
4811 rv = decode_LDSTiiFP_0 (iw0, outf);
4812 else if ((iw0 & 0xe000) == 0xA000)
4813 rv = decode_LDSTii_0 (iw0, outf);
4814 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
4815 rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
4816 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
4817 rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
4818 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
4819 rv = decode_CALLa_0 (iw0, iw1, pc, outf);
4820 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
4821 rv = decode_LDSTidxI_0 (iw0, iw1, outf);
4822 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
4823 rv = decode_linkage_0 (iw0, iw1, outf);
4824 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
4825 rv = decode_dsp32mac_0 (iw0, iw1, outf);
4826 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
4827 rv = decode_dsp32mult_0 (iw0, iw1, outf);
4828 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
4829 rv = decode_dsp32alu_0 (iw0, iw1, outf);
4830 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
4831 rv = decode_dsp32shift_0 (iw0, iw1, outf);
4832 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
4833 rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
4834 else if ((iw0 & 0xff00) == 0xf800)
4835 rv = decode_pseudoDEBUG_0 (iw0, outf);
4836 else if ((iw0 & 0xFF00) == 0xF900)
4837 rv = decode_pseudoOChar_0 (iw0, outf);
4838 else if ((iw0 & 0xFF00) == 0xf000 && (iw1 & 0x0000) == 0x0000)
4839 rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
4840
4841 if (rv == 0)
4842 OUTS (outf, "ILLEGAL");
4843
4844 return rv;
4845 }
4846
4847
4848 int
4849 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
4850 {
4851 bfd_byte buf[2];
4852 unsigned short iw0;
4853 int status;
4854 int count = 0;
4855
4856 status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
4857 /* FIXME */
4858 (void) status;
4859 iw0 = bfd_getl16 (buf);
4860
4861 count += _print_insn_bfin (pc, outf);
4862
4863 /* Proper display of multiple issue instructions. */
4864
4865 if (count == 4 && (iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
4866 && ((iw0 & 0xe800) != 0xe800 /* Not Linkage. */ ))
4867 {
4868 int legal = 1;
4869 int len;
4870
4871 parallel = 1;
4872 outf->fprintf_func (outf->stream, " || ");
4873 len = _print_insn_bfin (pc + 4, outf);
4874 outf->fprintf_func (outf->stream, " || ");
4875 if (len != 2)
4876 legal = 0;
4877 len = _print_insn_bfin (pc + 6, outf);
4878 if (len != 2)
4879 legal = 0;
4880
4881 if (legal)
4882 count = 8;
4883 else
4884 {
4885 outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
4886 comment = 1;
4887 count = 0;
4888 }
4889 parallel = 0;
4890 }
4891
4892 if (!comment)
4893 outf->fprintf_func (outf->stream, ";");
4894
4895 if (count == 0)
4896 return 2;
4897
4898 comment = 0;
4899
4900 return count;
4901 }
git-cvsimport of binutils cvsroot