gas/config/bfin-parse.y

   1 /* bfin-parse.y  ADI Blackfin parser
   2    Copyright 2005, 2006, 2007, 2008, 2009, 2010
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21 %{
  22
  23 #include "as.h"
  24 #include <obstack.h>
  25
  26 #include "bfin-aux.h"  /* Opcode generating auxiliaries.  */
  27 #include "libbfd.h"
  28 #include "elf/common.h"
  29 #include "elf/bfin.h"
  30
  31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
  32         bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
  33
  34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
  35         bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
  36                            dst, src0, src1, w0)
  37
  38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
  39         bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
  40                             dst, src0, src1, w0)
  41
  42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls)  \
  43         bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
  44
  45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls)  \
  46         bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
  47
  48 #define LDIMMHALF_R(reg, h, s, z, hword) \
  49         bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
  50
  51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
  52         bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
  53
  54 #define LDSTIDXI(ptr, reg, w, sz, z, offset)  \
  55         bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
  56
  57 #define LDST(ptr, reg, aop, sz, z, w)  \
  58         bfin_gen_ldst (ptr, reg, aop, sz, z, w)
  59
  60 #define LDSTII(ptr, reg, offset, w, op)  \
  61         bfin_gen_ldstii (ptr, reg, offset, w, op)
  62
  63 #define DSPLDST(i, m, reg, aop, w) \
  64         bfin_gen_dspldst (i, reg, aop, w, m)
  65
  66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
  67         bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
  68
  69 #define LDSTIIFP(offset, reg, w)  \
  70         bfin_gen_ldstiifp (reg, offset, w)
  71
  72 #define LOGI2OP(dst, src, opc) \
  73         bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
  74
  75 #define ALU2OP(dst, src, opc)  \
  76         bfin_gen_alu2op (dst, src, opc)
  77
  78 #define BRCC(t, b, offset) \
  79         bfin_gen_brcc (t, b, offset)
  80
  81 #define UJUMP(offset) \
  82         bfin_gen_ujump (offset)
  83
  84 #define PROGCTRL(prgfunc, poprnd) \
  85         bfin_gen_progctrl (prgfunc, poprnd)
  86
  87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
  88         bfin_gen_pushpopmultiple (dr, pr, d, p, w)
  89
  90 #define PUSHPOPREG(reg, w) \
  91         bfin_gen_pushpopreg (reg, w)
  92
  93 #define CALLA(addr, s)  \
  94         bfin_gen_calla (addr, s)
  95
  96 #define LINKAGE(r, framesize) \
  97         bfin_gen_linkage (r, framesize)
  98
  99 #define COMPI2OPD(dst, src, op)  \
 100         bfin_gen_compi2opd (dst, src, op)
 101
 102 #define COMPI2OPP(dst, src, op)  \
 103         bfin_gen_compi2opp (dst, src, op)
 104
 105 #define DAGMODIK(i, op)  \
 106         bfin_gen_dagmodik (i, op)
 107
 108 #define DAGMODIM(i, m, op, br)  \
 109         bfin_gen_dagmodim (i, m, op, br)
 110
 111 #define COMP3OP(dst, src0, src1, opc)   \
 112         bfin_gen_comp3op (src0, src1, dst, opc)
 113
 114 #define PTR2OP(dst, src, opc)   \
 115         bfin_gen_ptr2op (dst, src, opc)
 116
 117 #define CCFLAG(x, y, opc, i, g)  \
 118         bfin_gen_ccflag (x, y, opc, i, g)
 119
 120 #define CCMV(src, dst, t) \
 121         bfin_gen_ccmv (src, dst, t)
 122
 123 #define CACTRL(reg, a, op) \
 124         bfin_gen_cactrl (reg, a, op)
 125
 126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
 127         bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
 128
 129 #define HL2(r1, r0)  (IS_H (r1) << 1 | IS_H (r0))
 130 #define IS_RANGE(bits, expr, sign, mul)    \
 131         value_match(expr, bits, sign, mul, 1)
 132 #define IS_URANGE(bits, expr, sign, mul)    \
 133         value_match(expr, bits, sign, mul, 0)
 134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
 135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
 136 #define IS_IMM(expr, bits)  value_match (expr, bits, 0, 1, 1)
 137 #define IS_UIMM(expr, bits)  value_match (expr, bits, 0, 1, 0)
 138
 139 #define IS_PCREL4(expr) \
 140         (value_match (expr, 4, 0, 2, 0))
 141
 142 #define IS_LPPCREL10(expr) \
 143         (value_match (expr, 10, 0, 2, 0))
 144
 145 #define IS_PCREL10(expr) \
 146         (value_match (expr, 10, 0, 2, 1))
 147
 148 #define IS_PCREL12(expr) \
 149         (value_match (expr, 12, 0, 2, 1))
 150
 151 #define IS_PCREL24(expr) \
 152         (value_match (expr, 24, 0, 2, 1))
 153
 154
 155 static int value_match (Expr_Node *, int, int, int, int);
 156
 157 extern FILE *errorf;
 158 extern INSTR_T insn;
 159
 160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
 161 static Expr_Node *unary  (Expr_Op_Type, Expr_Node *);
 162
 163 static void notethat (char *, ...);
 164
 165 char *current_inputline;
 166 extern char *yytext;
 167 int yyerror (char *);
 168
 169 void error (char *format, ...)
 170 {
 171     va_list ap;
 172     static char buffer[2000];
 173
 174     va_start (ap, format);
 175     vsprintf (buffer, format, ap);
 176     va_end (ap);
 177
 178     as_bad ("%s", buffer);
 179 }
 180
 181 int
 182 yyerror (char *msg)
 183 {
 184   if (msg[0] == '\0')
 185     error ("%s", msg);
 186
 187   else if (yytext[0] != ';')
 188     error ("%s. Input text was %s.", msg, yytext);
 189   else
 190     error ("%s.", msg);
 191
 192   return -1;
 193 }
 194
 195 static int
 196 in_range_p (Expr_Node *exp, int from, int to, unsigned int mask)
 197 {
 198   int val = EXPR_VALUE (exp);
 199   if (exp->type != Expr_Node_Constant)
 200     return 0;
 201   if (val < from || val > to)
 202     return 0;
 203   return (val & mask) == 0;
 204 }
 205
 206 extern int yylex (void);
 207
 208 #define imm3(x) EXPR_VALUE (x)
 209 #define imm4(x) EXPR_VALUE (x)
 210 #define uimm4(x) EXPR_VALUE (x)
 211 #define imm5(x) EXPR_VALUE (x)
 212 #define uimm5(x) EXPR_VALUE (x)
 213 #define imm6(x) EXPR_VALUE (x)
 214 #define imm7(x) EXPR_VALUE (x)
 215 #define uimm8(x) EXPR_VALUE (x)
 216 #define imm16(x) EXPR_VALUE (x)
 217 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
 218 #define uimm16(x) EXPR_VALUE (x)
 219
 220 /* Return true if a value is inside a range.  */
 221 #define IN_RANGE(x, low, high) \
 222   (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
 223
 224 /* Auxiliary functions.  */
 225
 226 static int
 227 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
 228 {
 229   if (!IS_DREG (*reg1))
 230     {
 231       yyerror ("Dregs expected");
 232       return 0;
 233     }
 234
 235   if (reg1->regno != 1 && reg1->regno != 3)
 236     {
 237       yyerror ("Bad register pair");
 238       return 0;
 239     }
 240
 241   if (imm7 (reg2) != reg1->regno - 1)
 242     {
 243       yyerror ("Bad register pair");
 244       return 0;
 245     }
 246
 247   reg1->regno--;
 248   return 1;
 249 }
 250
 251 static int
 252 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
 253 {
 254   if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
 255       || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
 256     return yyerror ("Source multiplication register mismatch");
 257
 258   return 0;
 259 }
 260
 261
 262 /* Check mac option.  */
 263
 264 static int
 265 check_macfunc_option (Macfunc *a, Opt_mode *opt)
 266 {
 267   /* Default option is always valid.  */
 268   if (opt->mod == 0)
 269     return 0;
 270
 271   if ((a->w == 1 && a->P == 1
 272        && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
 273        && opt->mod != M_S2RND && opt->mod != M_ISS2)
 274       || (a->w == 1 && a->P == 0
 275           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
 276           && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
 277           && opt->mod != M_ISS2 && opt->mod != M_IH)
 278       || (a->w == 0 && a->P == 0
 279           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
 280     return -1;
 281
 282   return 0;
 283 }
 284
 285 /* Check (vector) mac funcs and ops.  */
 286
 287 static int
 288 check_macfuncs (Macfunc *aa, Opt_mode *opa,
 289                 Macfunc *ab, Opt_mode *opb)
 290 {
 291   /* Variables for swapping.  */
 292   Macfunc mtmp;
 293   Opt_mode otmp;
 294
 295   /* The option mode should be put at the end of the second instruction
 296      of the vector except M, which should follow MAC1 instruction.  */
 297   if (opa->mod != 0)
 298     return yyerror ("Bad opt mode");
 299
 300   /* If a0macfunc comes before a1macfunc, swap them.  */
 301
 302   if (aa->n == 0)
 303     {
 304       /*  (M) is not allowed here.  */
 305       if (opa->MM != 0)
 306         return yyerror ("(M) not allowed with A0MAC");
 307       if (ab->n != 1)
 308         return yyerror ("Vector AxMACs can't be same");
 309
 310       mtmp = *aa; *aa = *ab; *ab = mtmp;
 311       otmp = *opa; *opa = *opb; *opb = otmp;
 312     }
 313   else
 314     {
 315       if (opb->MM != 0)
 316         return yyerror ("(M) not allowed with A0MAC");
 317       if (ab->n != 0)
 318         return yyerror ("Vector AxMACs can't be same");
 319     }
 320
 321   /*  If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
 322   assignment_or_macfuncs.  */
 323   if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
 324       && (ab->op == 0 || ab->op == 1 || ab->op == 2))
 325     {
 326       if (check_multiply_halfregs (aa, ab) < 0)
 327         return -1;
 328     }
 329   else
 330     {
 331       /*  Only one of the assign_macfuncs has a half reg multiply
 332       Evil trick: Just 'OR' their source register codes:
 333       We can do that, because we know they were initialized to 0
 334       in the rules that don't use multiply_halfregs.  */
 335       aa->s0.regno |= (ab->s0.regno & CODE_MASK);
 336       aa->s1.regno |= (ab->s1.regno & CODE_MASK);
 337     }
 338
 339   if (aa->w == ab->w  && aa->P != ab->P)
 340     {
 341       return yyerror ("macfuncs must differ");
 342       if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
 343         return yyerror ("Destination Dregs must differ by one");
 344     }
 345
 346   /* Make sure mod flags get ORed, too.  */
 347   opb->mod |= opa->mod;
 348
 349   /* Check option.  */
 350   if (check_macfunc_option (aa, opb) < 0
 351       && check_macfunc_option (ab, opb) < 0)
 352     return yyerror ("bad option");
 353
 354   /* Make sure first macfunc has got both P flags ORed.  */
 355   aa->P |= ab->P;
 356
 357   return 0;
 358 }
 359
 360
 361 static int
 362 is_group1 (INSTR_T x)
 363 {
 364   /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii.  */
 365   if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
 366     return 1;
 367
 368   return 0;
 369 }
 370
 371 static int
 372 is_group2 (INSTR_T x)
 373 {
 374   if ((((x->value & 0xfc00) == 0x9c00)  /* dspLDST.  */
 375        && !((x->value & 0xfde0) == 0x9c60)  /* dagMODim.  */
 376        && !((x->value & 0xfde0) == 0x9ce0)  /* dagMODim with bit rev.  */
 377        && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik.  */
 378       || (x->value == 0x0000))
 379     return 1;
 380   return 0;
 381 }
 382
 383 static int
 384 is_store (INSTR_T x)
 385 {
 386   if (!x)
 387     return 0;
 388
 389   if ((x->value & 0xf000) == 0x8000)
 390     {
 391       int aop = ((x->value >> 9) & 0x3);
 392       int w = ((x->value >> 11) & 0x1);
 393       if (!w || aop == 3)
 394         return 0;
 395       return 1;
 396     }
 397
 398   if (((x->value & 0xFF60) == 0x9E60) ||  /* dagMODim_0 */
 399       ((x->value & 0xFFF0) == 0x9F60))    /* dagMODik_0 */
 400     return 0;
 401
 402   /* decode_dspLDST_0 */
 403   if ((x->value & 0xFC00) == 0x9C00)
 404     {
 405       int w = ((x->value >> 9) & 0x1);
 406       if (w)
 407         return 1;
 408     }
 409
 410   return 0;
 411 }
 412
 413 static INSTR_T
 414 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
 415 {
 416   int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
 417   int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
 418   int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
 419
 420   if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
 421     yyerror ("resource conflict in multi-issue instruction");
 422
 423   /* Anomaly 05000074 */
 424   if (ENABLE_AC_05000074
 425       && dsp32 != NULL && dsp16_grp1 != NULL
 426       && (dsp32->value & 0xf780) == 0xc680
 427       && ((dsp16_grp1->value & 0xfe40) == 0x9240
 428           || (dsp16_grp1->value & 0xfe08) == 0xba08
 429           || (dsp16_grp1->value & 0xfc00) == 0xbc00))
 430     yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
 431 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
 432
 433   if (is_store (dsp16_grp1) && is_store (dsp16_grp2))
 434     yyerror ("Only one instruction in multi-issue instruction can be a store");
 435
 436   return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
 437 }
 438
 439 %}
 440
 441 %union {
 442   INSTR_T instr;
 443   Expr_Node *expr;
 444   SYMBOL_T symbol;
 445   long value;
 446   Register reg;
 447   Macfunc macfunc;
 448   struct { int r0; int s0; int x0; int aop; } modcodes;
 449   struct { int r0; } r0;
 450   Opt_mode mod;
 451 }
 452
 453
 454 /* Tokens.  */
 455
 456 /* Vector Specific.  */
 457 %token BYTEOP16P BYTEOP16M
 458 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
 459 %token BYTEUNPACK BYTEPACK
 460 %token PACK
 461 %token SAA
 462 %token ALIGN8 ALIGN16 ALIGN24
 463 %token VIT_MAX
 464 %token EXTRACT DEPOSIT EXPADJ SEARCH
 465 %token ONES SIGN SIGNBITS
 466
 467 /* Stack.  */
 468 %token LINK UNLINK
 469
 470 /* Registers.  */
 471 %token REG
 472 %token PC
 473 %token CCREG BYTE_DREG
 474 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
 475 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
 476 %token HALF_REG
 477
 478 /* Progctrl.  */
 479 %token NOP
 480 %token RTI RTS RTX RTN RTE
 481 %token HLT IDLE
 482 %token STI CLI
 483 %token CSYNC SSYNC
 484 %token EMUEXCPT
 485 %token RAISE EXCPT
 486 %token LSETUP
 487 %token LOOP
 488 %token LOOP_BEGIN
 489 %token LOOP_END
 490 %token DISALGNEXCPT
 491 %token JUMP JUMP_DOT_S JUMP_DOT_L
 492 %token CALL
 493
 494 /* Emulator only.  */
 495 %token ABORT
 496
 497 /* Operators.  */
 498 %token NOT TILDA BANG
 499 %token AMPERSAND BAR
 500 %token PERCENT
 501 %token CARET
 502 %token BXOR
 503
 504 %token MINUS PLUS STAR SLASH
 505 %token NEG
 506 %token MIN MAX ABS
 507 %token DOUBLE_BAR
 508 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
 509 %token _MINUS_MINUS _PLUS_PLUS
 510
 511 /* Shift/rotate ops.  */
 512 %token SHIFT LSHIFT ASHIFT BXORSHIFT
 513 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
 514 %token ROT
 515 %token LESS_LESS GREATER_GREATER
 516 %token _GREATER_GREATER_GREATER
 517 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
 518 %token DIVS DIVQ
 519
 520 /* In place operators.  */
 521 %token ASSIGN _STAR_ASSIGN
 522 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
 523 %token _MINUS_ASSIGN _PLUS_ASSIGN
 524
 525 /* Assignments, comparisons.  */
 526 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
 527 %token GE LT LE GT
 528 %token LESS_THAN
 529
 530 /* Cache.  */
 531 %token FLUSHINV FLUSH
 532 %token IFLUSH PREFETCH
 533
 534 /* Misc.  */
 535 %token PRNT
 536 %token OUTC
 537 %token WHATREG
 538 %token TESTSET
 539
 540 /* Modifiers.  */
 541 %token ASL ASR
 542 %token B W
 543 %token NS S CO SCO
 544 %token TH TL
 545 %token BP
 546 %token BREV
 547 %token X Z
 548 %token M MMOD
 549 %token R RND RNDL RNDH RND12 RND20
 550 %token V
 551 %token LO HI
 552
 553 /* Bit ops.  */
 554 %token BITTGL BITCLR BITSET BITTST BITMUX
 555
 556 /* Debug.  */
 557 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
 558
 559 /* Semantic auxiliaries.  */
 560
 561 %token IF COMMA BY
 562 %token COLON SEMICOLON
 563 %token RPAREN LPAREN LBRACK RBRACK
 564 %token STATUS_REG
 565 %token MNOP
 566 %token SYMBOL NUMBER
 567 %token GOT GOT17M4 FUNCDESC_GOT17M4
 568 %token AT PLTPC
 569
 570 /* Types.  */
 571 %type <instr> asm
 572 %type <value> MMOD
 573 %type <mod> opt_mode
 574
 575 %type <value> NUMBER
 576 %type <r0> aligndir
 577 %type <modcodes> byteop_mod
 578 %type <reg> a_assign
 579 %type <reg> a_plusassign
 580 %type <reg> a_minusassign
 581 %type <macfunc> multiply_halfregs
 582 %type <macfunc> assign_macfunc
 583 %type <macfunc> a_macfunc
 584 %type <expr> expr_1
 585 %type <instr> asm_1
 586 %type <r0> vmod
 587 %type <modcodes> vsmod
 588 %type <modcodes> ccstat
 589 %type <r0> cc_op
 590 %type <reg> CCREG
 591 %type <reg> reg_with_postinc
 592 %type <reg> reg_with_predec
 593
 594 %type <r0> searchmod
 595 %type <expr> symbol
 596 %type <symbol> SYMBOL
 597 %type <expr> eterm
 598 %type <reg> REG
 599 %type <reg> BYTE_DREG
 600 %type <reg> REG_A_DOUBLE_ZERO
 601 %type <reg> REG_A_DOUBLE_ONE
 602 %type <reg> REG_A
 603 %type <reg> STATUS_REG
 604 %type <expr> expr
 605 %type <r0> xpmod
 606 %type <r0> xpmod1
 607 %type <modcodes> smod
 608 %type <modcodes> b3_op
 609 %type <modcodes> rnd_op
 610 %type <modcodes> post_op
 611 %type <reg> HALF_REG
 612 %type <r0> iu_or_nothing
 613 %type <r0> plus_minus
 614 %type <r0> asr_asl
 615 %type <r0> asr_asl_0
 616 %type <modcodes> sco
 617 %type <modcodes> amod0
 618 %type <modcodes> amod1
 619 %type <modcodes> amod2
 620 %type <r0> op_bar_op
 621 %type <r0> w32_or_nothing
 622 %type <r0> c_align
 623 %type <r0> min_max
 624 %type <expr> got
 625 %type <expr> got_or_expr
 626 %type <expr> pltpc
 627 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
 628
 629 /* Precedence rules.  */
 630 %left BAR
 631 %left CARET
 632 %left AMPERSAND
 633 %left LESS_LESS GREATER_GREATER
 634 %left PLUS MINUS
 635 %left STAR SLASH PERCENT
 636
 637 %right ASSIGN
 638
 639 %right TILDA BANG
 640 %start statement
 641 %%
 642 statement:
 643         | asm
 644         {
 645           insn = $1;
 646           if (insn == (INSTR_T) 0)
 647             return NO_INSN_GENERATED;
 648           else if (insn == (INSTR_T) - 1)
 649             return SEMANTIC_ERROR;
 650           else
 651             return INSN_GENERATED;
 652         }
 653         ;
 654
 655 asm: asm_1 SEMICOLON
 656         /* Parallel instructions.  */
 657         | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
 658         {
 659           if (($1->value & 0xf800) == 0xc000)
 660             {
 661               if (is_group1 ($3) && is_group2 ($5))
 662                 $$ = gen_multi_instr_1 ($1, $3, $5);
 663               else if (is_group2 ($3) && is_group1 ($5))
 664                 $$ = gen_multi_instr_1 ($1, $5, $3);
 665               else
 666                 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
 667             }
 668           else if (($3->value & 0xf800) == 0xc000)
 669             {
 670               if (is_group1 ($1) && is_group2 ($5))
 671                 $$ = gen_multi_instr_1 ($3, $1, $5);
 672               else if (is_group2 ($1) && is_group1 ($5))
 673                 $$ = gen_multi_instr_1 ($3, $5, $1);
 674               else
 675                 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
 676             }
 677           else if (($5->value & 0xf800) == 0xc000)
 678             {
 679               if (is_group1 ($1) && is_group2 ($3))
 680                 $$ = gen_multi_instr_1 ($5, $1, $3);
 681               else if (is_group2 ($1) && is_group1 ($3))
 682                 $$ = gen_multi_instr_1 ($5, $3, $1);
 683               else
 684                 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
 685             }
 686           else
 687             error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
 688         }
 689
 690         | asm_1 DOUBLE_BAR asm_1 SEMICOLON
 691         {
 692           if (($1->value & 0xf800) == 0xc000)
 693             {
 694               if (is_group1 ($3))
 695                 $$ = gen_multi_instr_1 ($1, $3, 0);
 696               else if (is_group2 ($3))
 697                 $$ = gen_multi_instr_1 ($1, 0, $3);
 698               else
 699                 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
 700             }
 701           else if (($3->value & 0xf800) == 0xc000)
 702             {
 703               if (is_group1 ($1))
 704                 $$ = gen_multi_instr_1 ($3, $1, 0);
 705               else if (is_group2 ($1))
 706                 $$ = gen_multi_instr_1 ($3, 0, $1);
 707               else
 708                 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
 709             }
 710           else if (is_group1 ($1) && is_group2 ($3))
 711               $$ = gen_multi_instr_1 (0, $1, $3);
 712           else if (is_group2 ($1) && is_group1 ($3))
 713             $$ = gen_multi_instr_1 (0, $3, $1);
 714           else
 715             return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
 716         }
 717         | error
 718         {
 719         $$ = 0;
 720         yyerror ("");
 721         yyerrok;
 722         }
 723         ;
 724
 725 /* DSPMAC.  */
 726
 727 asm_1:
 728         MNOP
 729         {
 730           $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
 731         }
 732         | assign_macfunc opt_mode
 733         {
 734           int op0, op1;
 735           int w0 = 0, w1 = 0;
 736           int h00, h10, h01, h11;
 737
 738           if (check_macfunc_option (&$1, &$2) < 0)
 739             return yyerror ("bad option");
 740
 741           if ($1.n == 0)
 742             {
 743               if ($2.MM)
 744                 return yyerror ("(m) not allowed with a0 unit");
 745               op1 = 3;
 746               op0 = $1.op;
 747               w1 = 0;
 748               w0 = $1.w;
 749               h00 = IS_H ($1.s0);
 750               h10 = IS_H ($1.s1);
 751               h01 = h11 = 0;
 752             }
 753           else
 754             {
 755               op1 = $1.op;
 756               op0 = 3;
 757               w1 = $1.w;
 758               w0 = 0;
 759               h00 = h10 = 0;
 760               h01 = IS_H ($1.s0);
 761               h11 = IS_H ($1.s1);
 762             }
 763           $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
 764                          &$1.dst, op0, &$1.s0, &$1.s1, w0);
 765         }
 766
 767
 768 /* VECTOR MACs.  */
 769
 770         | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
 771         {
 772           Register *dst;
 773
 774           if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
 775             return -1;
 776           notethat ("assign_macfunc (.), assign_macfunc (.)\n");
 777
 778           if ($1.w)
 779             dst = &$1.dst;
 780           else
 781             dst = &$4.dst;
 782
 783           $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
 784                          IS_H ($1.s0),  IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
 785                          dst, $4.op, &$1.s0, &$1.s1, $4.w);
 786         }
 787
 788 /* DSPALU.  */
 789
 790         | DISALGNEXCPT
 791         {
 792           notethat ("dsp32alu: DISALGNEXCPT\n");
 793           $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
 794         }
 795         | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
 796         {
 797           if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
 798             {
 799               notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
 800               $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
 801             }
 802           else
 803             return yyerror ("Register mismatch");
 804         }
 805         | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
 806         {
 807           if (!IS_A1 ($4) && IS_A1 ($5))
 808             {
 809               notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
 810               $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
 811             }
 812           else
 813             return yyerror ("Register mismatch");
 814         }
 815         | A_ZERO_DOT_H ASSIGN HALF_REG
 816         {
 817           notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
 818           $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
 819         }
 820         | A_ONE_DOT_H ASSIGN HALF_REG
 821         {
 822           notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
 823           $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
 824         }
 825         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
 826           COLON expr COMMA REG COLON expr RPAREN aligndir
 827         {
 828           if (!IS_DREG ($2) || !IS_DREG ($4))
 829             return yyerror ("Dregs expected");
 830           else if (!valid_dreg_pair (&$9, $11))
 831             return yyerror ("Bad dreg pair");
 832           else if (!valid_dreg_pair (&$13, $15))
 833             return yyerror ("Bad dreg pair");
 834           else
 835             {
 836               notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (aligndir)\n");
 837               $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
 838             }
 839         }
 840
 841         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
 842           REG COLON expr RPAREN aligndir
 843         {
 844           if (!IS_DREG ($2) || !IS_DREG ($4))
 845             return yyerror ("Dregs expected");
 846           else if (!valid_dreg_pair (&$9, $11))
 847             return yyerror ("Bad dreg pair");
 848           else if (!valid_dreg_pair (&$13, $15))
 849             return yyerror ("Bad dreg pair");
 850           else
 851             {
 852               notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
 853               $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
 854             }
 855         }
 856
 857         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
 858         {
 859           if (!IS_DREG ($2) || !IS_DREG ($4))
 860             return yyerror ("Dregs expected");
 861           else if (!valid_dreg_pair (&$8, $10))
 862             return yyerror ("Bad dreg pair");
 863           else
 864             {
 865               notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
 866               $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
 867             }
 868         }
 869         | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
 870         {
 871           if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
 872             {
 873               notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
 874               $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
 875             }
 876           else
 877             return yyerror ("Register mismatch");
 878         }
 879         | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
 880           REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
 881         {
 882           if (IS_DREG ($1) && IS_DREG ($7))
 883             {
 884               notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h  \n");
 885               $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
 886             }
 887           else
 888             return yyerror ("Register mismatch");
 889         }
 890
 891
 892         | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
 893         {
 894           if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 895               && IS_A1 ($9) && !IS_A1 ($11))
 896             {
 897               notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
 898               $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
 899
 900             }
 901           else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 902                    && !IS_A1 ($9) && IS_A1 ($11))
 903             {
 904               notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
 905               $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
 906             }
 907           else
 908             return yyerror ("Register mismatch");
 909         }
 910
 911         | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
 912         {
 913           if ($4.r0 == $10.r0)
 914             return yyerror ("Operators must differ");
 915
 916           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
 917               && REG_SAME ($3, $9) && REG_SAME ($5, $11))
 918             {
 919               notethat ("dsp32alu: dregs = dregs + dregs,"
 920                        "dregs = dregs - dregs (amod1)\n");
 921               $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
 922             }
 923           else
 924             return yyerror ("Register mismatch");
 925         }
 926
 927 /*  Bar Operations.  */
 928
 929         | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
 930         {
 931           if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
 932             return yyerror ("Differing source registers");
 933
 934           if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
 935             return yyerror ("Dregs expected");
 936
 937
 938           if ($4.r0 == 1 && $10.r0 == 2)
 939             {
 940               notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
 941               $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
 942             }
 943           else if ($4.r0 == 0 && $10.r0 == 3)
 944             {
 945               notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
 946               $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
 947             }
 948           else
 949             return yyerror ("Bar operand mismatch");
 950         }
 951
 952         | REG ASSIGN ABS REG vmod
 953         {
 954           int op;
 955
 956           if (IS_DREG ($1) && IS_DREG ($4))
 957             {
 958               if ($5.r0)
 959                 {
 960                   notethat ("dsp32alu: dregs = ABS dregs (v)\n");
 961                   op = 6;
 962                 }
 963               else
 964                 {
 965                   /* Vector version of ABS.  */
 966                   notethat ("dsp32alu: dregs = ABS dregs\n");
 967                   op = 7;
 968                 }
 969               $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
 970             }
 971           else
 972             return yyerror ("Dregs expected");
 973         }
 974         | a_assign ABS REG_A
 975         {
 976           notethat ("dsp32alu: Ax = ABS Ax\n");
 977           $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
 978         }
 979         | A_ZERO_DOT_L ASSIGN HALF_REG
 980         {
 981           if (IS_DREG_L ($3))
 982             {
 983               notethat ("dsp32alu: A0.l = reg_half\n");
 984               $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
 985             }
 986           else
 987             return yyerror ("A0.l = Rx.l expected");
 988         }
 989         | A_ONE_DOT_L ASSIGN HALF_REG
 990         {
 991           if (IS_DREG_L ($3))
 992             {
 993               notethat ("dsp32alu: A1.l = reg_half\n");
 994               $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
 995             }
 996           else
 997             return yyerror ("A1.l = Rx.l expected");
 998         }
 999
1000         | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
1001         {
1002           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1003             {
1004               notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
1005               $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
1006             }
1007           else
1008             return yyerror ("Dregs expected");
1009         }
1010
1011         | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
1012         {
1013           if (!IS_DREG ($1))
1014             return yyerror ("Dregs expected");
1015           else if (!valid_dreg_pair (&$5, $7))
1016             return yyerror ("Bad dreg pair");
1017           else if (!valid_dreg_pair (&$9, $11))
1018             return yyerror ("Bad dreg pair");
1019           else
1020             {
1021               notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1022               $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
1023             }
1024         }
1025         | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1026         {
1027           if (!IS_DREG ($1))
1028             return yyerror ("Dregs expected");
1029           else if (!valid_dreg_pair (&$5, $7))
1030             return yyerror ("Bad dreg pair");
1031           else if (!valid_dreg_pair (&$9, $11))
1032             return yyerror ("Bad dreg pair");
1033           else
1034             {
1035               notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1036               $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1037             }
1038         }
1039
1040         | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1041           rnd_op
1042         {
1043           if (!IS_DREG ($1))
1044             return yyerror ("Dregs expected");
1045           else if (!valid_dreg_pair (&$5, $7))
1046             return yyerror ("Bad dreg pair");
1047           else if (!valid_dreg_pair (&$9, $11))
1048             return yyerror ("Bad dreg pair");
1049           else
1050             {
1051               notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1052               $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1053             }
1054         }
1055
1056         | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1057           rnd_op
1058         {
1059           if (!IS_DREG ($1))
1060             return yyerror ("Dregs expected");
1061           else if (!valid_dreg_pair (&$5, $7))
1062             return yyerror ("Bad dreg pair");
1063           else if (!valid_dreg_pair (&$9, $11))
1064             return yyerror ("Bad dreg pair");
1065           else
1066             {
1067               notethat ("dsp32alu: dregs = BYTEOP2M (dregs_pair , dregs_pair ) (rnd_op)\n");
1068               $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop + 2);
1069             }
1070         }
1071
1072         | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1073           b3_op
1074         {
1075           if (!IS_DREG ($1))
1076             return yyerror ("Dregs expected");
1077           else if (!valid_dreg_pair (&$5, $7))
1078             return yyerror ("Bad dreg pair");
1079           else if (!valid_dreg_pair (&$9, $11))
1080             return yyerror ("Bad dreg pair");
1081           else
1082             {
1083               notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1084               $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1085             }
1086         }
1087
1088         | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1089         {
1090           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1091             {
1092               notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1093               $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1094             }
1095           else
1096             return yyerror ("Dregs expected");
1097         }
1098
1099         | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1100           HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1101         {
1102           if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1103             {
1104               notethat ("dsp32alu:      dregs_hi = dregs_lo ="
1105                        "SIGN (dregs_hi) * dregs_hi + "
1106                        "SIGN (dregs_lo) * dregs_lo \n");
1107
1108                 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1109             }
1110           else
1111             return yyerror ("Dregs expected");
1112         }
1113         | REG ASSIGN REG plus_minus REG amod1
1114         {
1115           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1116             {
1117               if ($6.aop == 0)
1118                 {
1119                   /* No saturation flag specified, generate the 16 bit variant.  */
1120                   notethat ("COMP3op: dregs = dregs +- dregs\n");
1121                   $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1122                 }
1123               else
1124                 {
1125                  /* Saturation flag specified, generate the 32 bit variant.  */
1126                  notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1127                  $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1128                 }
1129             }
1130           else
1131             if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1132               {
1133                 notethat ("COMP3op: pregs = pregs + pregs\n");
1134                 $$ = COMP3OP (&$1, &$3, &$5, 5);
1135               }
1136             else
1137               return yyerror ("Dregs expected");
1138         }
1139         | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1140         {
1141           int op;
1142
1143           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1144             {
1145               if ($9.r0)
1146                 op = 6;
1147               else
1148                 op = 7;
1149
1150               notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1151               $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1152             }
1153           else
1154             return yyerror ("Dregs expected");
1155         }
1156
1157         | a_assign MINUS REG_A
1158         {
1159           notethat ("dsp32alu: Ax = - Ax\n");
1160           $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1161         }
1162         | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1163         {
1164           notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1165           $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1166                          $6.s0, $6.x0, HL2 ($3, $5));
1167         }
1168         | a_assign a_assign expr
1169         {
1170           if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1171             {
1172               notethat ("dsp32alu: A1 = A0 = 0\n");
1173               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1174             }
1175           else
1176             return yyerror ("Bad value, 0 expected");
1177         }
1178
1179         /* Saturating.  */
1180         | a_assign REG_A LPAREN S RPAREN
1181         {
1182           if (REG_SAME ($1, $2))
1183             {
1184               notethat ("dsp32alu: Ax = Ax (S)\n");
1185               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1186             }
1187           else
1188             return yyerror ("Registers must be equal");
1189         }
1190
1191         | HALF_REG ASSIGN REG LPAREN RND RPAREN
1192         {
1193           if (IS_DREG ($3))
1194             {
1195               notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1196               $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1197             }
1198           else
1199             return yyerror ("Dregs expected");
1200         }
1201
1202         | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1203         {
1204           if (IS_DREG ($3) && IS_DREG ($5))
1205             {
1206               notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1207               $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1208             }
1209           else
1210             return yyerror ("Dregs expected");
1211         }
1212
1213         | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1214         {
1215           if (IS_DREG ($3) && IS_DREG ($5))
1216             {
1217               notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1218               $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1219             }
1220           else
1221             return yyerror ("Dregs expected");
1222         }
1223
1224         | a_assign REG_A
1225         {
1226           if (!REG_SAME ($1, $2))
1227             {
1228               notethat ("dsp32alu: An = Am\n");
1229               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1230             }
1231           else
1232             return yyerror ("Accu reg arguments must differ");
1233         }
1234
1235         | a_assign REG
1236         {
1237           if (IS_DREG ($2))
1238             {
1239               notethat ("dsp32alu: An = dregs\n");
1240               $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1241             }
1242           else
1243             return yyerror ("Dregs expected");
1244         }
1245
1246         | REG ASSIGN HALF_REG xpmod
1247         {
1248           if (!IS_H ($3))
1249             {
1250               if ($1.regno == REG_A0x && IS_DREG ($3))
1251                 {
1252                   notethat ("dsp32alu: A0.x = dregs_lo\n");
1253                   $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1254                 }
1255               else if ($1.regno == REG_A1x && IS_DREG ($3))
1256                 {
1257                   notethat ("dsp32alu: A1.x = dregs_lo\n");
1258                   $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1259                 }
1260               else if (IS_DREG ($1) && IS_DREG ($3))
1261                 {
1262                   notethat ("ALU2op: dregs = dregs_lo\n");
1263                   $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1264                 }
1265               else
1266                 return yyerror ("Register mismatch");
1267             }
1268           else
1269             return yyerror ("Low reg expected");
1270         }
1271
1272         | HALF_REG ASSIGN expr
1273         {
1274           notethat ("LDIMMhalf: pregs_half = imm16\n");
1275
1276           if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1277               && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1278             return yyerror ("Wrong register for load immediate");
1279
1280           if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1281             return yyerror ("Constant out of range");
1282
1283           $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1284         }
1285
1286         | a_assign expr
1287         {
1288           notethat ("dsp32alu: An = 0\n");
1289
1290           if (imm7 ($2) != 0)
1291             return yyerror ("0 expected");
1292
1293           $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1294         }
1295
1296         | REG ASSIGN expr xpmod1
1297         {
1298           if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1299               && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1300             return yyerror ("Wrong register for load immediate");
1301
1302           if ($4.r0 == 0)
1303             {
1304               /* 7 bit immediate value if possible.
1305                  We will check for that constant value for efficiency
1306                  If it goes to reloc, it will be 16 bit.  */
1307               if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1308                 {
1309                   notethat ("COMPI2opD: dregs = imm7 (x) \n");
1310                   $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1311                 }
1312               else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1313                 {
1314                   notethat ("COMPI2opP: pregs = imm7 (x)\n");
1315                   $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1316                 }
1317               else
1318                 {
1319                   if (IS_CONST ($3) && !IS_IMM ($3, 16))
1320                     return yyerror ("Immediate value out of range");
1321
1322                   notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1323                   /* reg, H, S, Z.   */
1324                   $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1325                 }
1326             }
1327           else
1328             {
1329               /* (z) There is no 7 bit zero extended instruction.
1330               If the expr is a relocation, generate it.   */
1331
1332               if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1333                 return yyerror ("Immediate value out of range");
1334
1335               notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1336               /* reg, H, S, Z.  */
1337               $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1338             }
1339         }
1340
1341         | HALF_REG ASSIGN REG
1342         {
1343           if (IS_H ($1))
1344             return yyerror ("Low reg expected");
1345
1346           if (IS_DREG ($1) && $3.regno == REG_A0x)
1347             {
1348               notethat ("dsp32alu: dregs_lo = A0.x\n");
1349               $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1350             }
1351           else if (IS_DREG ($1) && $3.regno == REG_A1x)
1352             {
1353               notethat ("dsp32alu: dregs_lo = A1.x\n");
1354               $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1355             }
1356           else
1357             return yyerror ("Register mismatch");
1358         }
1359
1360         | REG ASSIGN REG op_bar_op REG amod0
1361         {
1362           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1363             {
1364               notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1365               $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1366             }
1367           else
1368             return yyerror ("Register mismatch");
1369         }
1370
1371         | REG ASSIGN BYTE_DREG xpmod
1372         {
1373           if (IS_DREG ($1) && IS_DREG ($3))
1374             {
1375               notethat ("ALU2op: dregs = dregs_byte\n");
1376               $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1377             }
1378           else
1379             return yyerror ("Register mismatch");
1380         }
1381
1382         | a_assign ABS REG_A COMMA a_assign ABS REG_A
1383         {
1384           if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1385             {
1386               notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1387               $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1388             }
1389           else
1390             return yyerror ("Register mismatch");
1391         }
1392
1393         | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1394         {
1395           if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1396             {
1397               notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1398               $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1399             }
1400           else
1401             return yyerror ("Register mismatch");
1402         }
1403
1404         | a_minusassign REG_A w32_or_nothing
1405         {
1406           if (!IS_A1 ($1) && IS_A1 ($2))
1407             {
1408               notethat ("dsp32alu: A0 -= A1\n");
1409               $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1410             }
1411           else
1412             return yyerror ("Register mismatch");
1413         }
1414
1415         | REG _MINUS_ASSIGN expr
1416         {
1417           if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1418             {
1419               notethat ("dagMODik: iregs -= 4\n");
1420               $$ = DAGMODIK (&$1, 3);
1421             }
1422           else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1423             {
1424               notethat ("dagMODik: iregs -= 2\n");
1425               $$ = DAGMODIK (&$1, 1);
1426             }
1427           else
1428             return yyerror ("Register or value mismatch");
1429         }
1430
1431         | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1432         {
1433           if (IS_IREG ($1) && IS_MREG ($3))
1434             {
1435               notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1436               /* i, m, op, br.  */
1437               $$ = DAGMODIM (&$1, &$3, 0, 1);
1438             }
1439           else if (IS_PREG ($1) && IS_PREG ($3))
1440             {
1441               notethat ("PTR2op: pregs += pregs (BREV )\n");
1442               $$ = PTR2OP (&$1, &$3, 5);
1443             }
1444           else
1445             return yyerror ("Register mismatch");
1446         }
1447
1448         | REG _MINUS_ASSIGN REG
1449         {
1450           if (IS_IREG ($1) && IS_MREG ($3))
1451             {
1452               notethat ("dagMODim: iregs -= mregs\n");
1453               $$ = DAGMODIM (&$1, &$3, 1, 0);
1454             }
1455           else if (IS_PREG ($1) && IS_PREG ($3))
1456             {
1457               notethat ("PTR2op: pregs -= pregs\n");
1458               $$ = PTR2OP (&$1, &$3, 0);
1459             }
1460           else
1461             return yyerror ("Register mismatch");
1462         }
1463
1464         | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1465         {
1466           if (!IS_A1 ($1) && IS_A1 ($3))
1467             {
1468               notethat ("dsp32alu: A0 += A1 (W32)\n");
1469               $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1470             }
1471           else
1472             return yyerror ("Register mismatch");
1473         }
1474
1475         | REG _PLUS_ASSIGN REG
1476         {
1477           if (IS_IREG ($1) && IS_MREG ($3))
1478             {
1479               notethat ("dagMODim: iregs += mregs\n");
1480               $$ = DAGMODIM (&$1, &$3, 0, 0);
1481             }
1482           else
1483             return yyerror ("iregs += mregs expected");
1484         }
1485
1486         | REG _PLUS_ASSIGN expr
1487         {
1488           if (IS_IREG ($1))
1489             {
1490               if (EXPR_VALUE ($3) == 4)
1491                 {
1492                   notethat ("dagMODik: iregs += 4\n");
1493                   $$ = DAGMODIK (&$1, 2);
1494                 }
1495               else if (EXPR_VALUE ($3) == 2)
1496                 {
1497                   notethat ("dagMODik: iregs += 2\n");
1498                   $$ = DAGMODIK (&$1, 0);
1499                 }
1500               else
1501                 return yyerror ("iregs += [ 2 | 4 ");
1502             }
1503           else if (IS_PREG ($1) && IS_IMM ($3, 7))
1504             {
1505               notethat ("COMPI2opP: pregs += imm7\n");
1506               $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1507             }
1508           else if (IS_DREG ($1) && IS_IMM ($3, 7))
1509             {
1510               notethat ("COMPI2opD: dregs += imm7\n");
1511               $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1512             }
1513           else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1514             return yyerror ("Immediate value out of range");
1515           else
1516             return yyerror ("Register mismatch");
1517         }
1518
1519         | REG _STAR_ASSIGN REG
1520         {
1521           if (IS_DREG ($1) && IS_DREG ($3))
1522             {
1523               notethat ("ALU2op: dregs *= dregs\n");
1524               $$ = ALU2OP (&$1, &$3, 3);
1525             }
1526           else
1527             return yyerror ("Register mismatch");
1528         }
1529
1530         | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1531         {
1532           if (!valid_dreg_pair (&$3, $5))
1533             return yyerror ("Bad dreg pair");
1534           else if (!valid_dreg_pair (&$7, $9))
1535             return yyerror ("Bad dreg pair");
1536           else
1537             {
1538               notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1539               $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1540             }
1541         }
1542
1543         | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1544         {
1545           if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1546             {
1547               notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1548               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1549             }
1550           else
1551             return yyerror ("Register mismatch");
1552         }
1553
1554         | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1555         {
1556           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1557               && REG_SAME ($1, $4))
1558             {
1559               if (EXPR_VALUE ($9) == 1)
1560                 {
1561                   notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1562                   $$ = ALU2OP (&$1, &$6, 4);
1563                 }
1564               else if (EXPR_VALUE ($9) == 2)
1565                 {
1566                   notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1567                   $$ = ALU2OP (&$1, &$6, 5);
1568                 }
1569               else
1570                 return yyerror ("Bad shift value");
1571             }
1572           else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1573                    && REG_SAME ($1, $4))
1574             {
1575               if (EXPR_VALUE ($9) == 1)
1576                 {
1577                   notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1578                   $$ = PTR2OP (&$1, &$6, 6);
1579                 }
1580               else if (EXPR_VALUE ($9) == 2)
1581                 {
1582                   notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1583                   $$ = PTR2OP (&$1, &$6, 7);
1584                 }
1585               else
1586                 return yyerror ("Bad shift value");
1587             }
1588           else
1589             return yyerror ("Register mismatch");
1590         }
1591
1592 /*  COMP3 CCFLAG.  */
1593         | REG ASSIGN REG BAR REG
1594         {
1595           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1596             {
1597               notethat ("COMP3op: dregs = dregs | dregs\n");
1598               $$ = COMP3OP (&$1, &$3, &$5, 3);
1599             }
1600           else
1601             return yyerror ("Dregs expected");
1602         }
1603         | REG ASSIGN REG CARET REG
1604         {
1605           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1606             {
1607               notethat ("COMP3op: dregs = dregs ^ dregs\n");
1608               $$ = COMP3OP (&$1, &$3, &$5, 4);
1609             }
1610           else
1611             return yyerror ("Dregs expected");
1612         }
1613         | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1614         {
1615           if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1616             {
1617               if (EXPR_VALUE ($8) == 1)
1618                 {
1619                   notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1620                   $$ = COMP3OP (&$1, &$3, &$6, 6);
1621                 }
1622               else if (EXPR_VALUE ($8) == 2)
1623                 {
1624                   notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1625                   $$ = COMP3OP (&$1, &$3, &$6, 7);
1626                 }
1627               else
1628                   return yyerror ("Bad shift value");
1629             }
1630           else
1631             return yyerror ("Dregs expected");
1632         }
1633         | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1634         {
1635           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1636             {
1637               notethat ("CCflag: CC = A0 == A1\n");
1638               $$ = CCFLAG (0, 0, 5, 0, 0);
1639             }
1640           else
1641             return yyerror ("AREGs are in bad order or same");
1642         }
1643         | CCREG ASSIGN REG_A LESS_THAN REG_A
1644         {
1645           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1646             {
1647               notethat ("CCflag: CC = A0 < A1\n");
1648               $$ = CCFLAG (0, 0, 6, 0, 0);
1649             }
1650           else
1651             return yyerror ("AREGs are in bad order or same");
1652         }
1653         | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1654         {
1655           if ((IS_DREG ($3) && IS_DREG ($5))
1656               || (IS_PREG ($3) && IS_PREG ($5)))
1657             {
1658               notethat ("CCflag: CC = dpregs < dpregs\n");
1659               $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1660             }
1661           else
1662             return yyerror ("Bad register in comparison");
1663         }
1664         | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1665         {
1666           if (!IS_DREG ($3) && !IS_PREG ($3))
1667             return yyerror ("Bad register in comparison");
1668
1669           if (($6.r0 == 1 && IS_IMM ($5, 3))
1670               || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1671             {
1672               notethat ("CCflag: CC = dpregs < (u)imm3\n");
1673               $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1674             }
1675           else
1676             return yyerror ("Bad constant value");
1677         }
1678         | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1679         {
1680           if ((IS_DREG ($3) && IS_DREG ($5))
1681               || (IS_PREG ($3) && IS_PREG ($5)))
1682             {
1683               notethat ("CCflag: CC = dpregs == dpregs\n");
1684               $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1685             }
1686           else
1687             return yyerror ("Bad register in comparison");
1688         }
1689         | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1690         {
1691           if (!IS_DREG ($3) && !IS_PREG ($3))
1692             return yyerror ("Bad register in comparison");
1693
1694           if (IS_IMM ($5, 3))
1695             {
1696               notethat ("CCflag: CC = dpregs == imm3\n");
1697               $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1698             }
1699           else
1700             return yyerror ("Bad constant range");
1701         }
1702         | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1703         {
1704           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1705             {
1706               notethat ("CCflag: CC = A0 <= A1\n");
1707               $$ = CCFLAG (0, 0, 7, 0, 0);
1708             }
1709           else
1710             return yyerror ("AREGs are in bad order or same");
1711         }
1712         | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1713         {
1714           if ((IS_DREG ($3) && IS_DREG ($5))
1715               || (IS_PREG ($3) && IS_PREG ($5)))
1716             {
1717               notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1718               $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1719                            1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1720             }
1721           else
1722             return yyerror ("Bad register in comparison");
1723         }
1724         | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1725         {
1726           if (!IS_DREG ($3) && !IS_PREG ($3))
1727             return yyerror ("Bad register in comparison");
1728
1729           if (($6.r0 == 1 && IS_IMM ($5, 3))
1730               || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1731             {
1732               notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1733               $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1734             }
1735           else
1736             return yyerror ("Bad constant value");
1737         }
1738
1739         | REG ASSIGN REG AMPERSAND REG
1740         {
1741           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1742             {
1743               notethat ("COMP3op: dregs = dregs & dregs\n");
1744               $$ = COMP3OP (&$1, &$3, &$5, 2);
1745             }
1746           else
1747             return yyerror ("Dregs expected");
1748         }
1749
1750         | ccstat
1751         {
1752           notethat ("CC2stat operation\n");
1753           $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1754         }
1755
1756         | REG ASSIGN REG
1757         {
1758           if ((IS_GENREG ($1) && IS_GENREG ($3))
1759               || (IS_GENREG ($1) && IS_DAGREG ($3))
1760               || (IS_DAGREG ($1) && IS_GENREG ($3))
1761               || (IS_DAGREG ($1) && IS_DAGREG ($3))
1762               || (IS_GENREG ($1) && $3.regno == REG_USP)
1763               || ($1.regno == REG_USP && IS_GENREG ($3))
1764               || ($1.regno == REG_USP && $3.regno == REG_USP)
1765               || (IS_DREG ($1) && IS_SYSREG ($3))
1766               || (IS_PREG ($1) && IS_SYSREG ($3))
1767               || (IS_SYSREG ($1) && IS_GENREG ($3))
1768               || (IS_ALLREG ($1) && IS_EMUDAT ($3))
1769               || (IS_EMUDAT ($1) && IS_ALLREG ($3))
1770               || (IS_SYSREG ($1) && $3.regno == REG_USP))
1771             {
1772               $$ = bfin_gen_regmv (&$3, &$1);
1773             }
1774           else
1775             return yyerror ("Unsupported register move");
1776         }
1777
1778         | CCREG ASSIGN REG
1779         {
1780           if (IS_DREG ($3))
1781             {
1782               notethat ("CC2dreg: CC = dregs\n");
1783               $$ = bfin_gen_cc2dreg (1, &$3);
1784             }
1785           else
1786             return yyerror ("Only 'CC = Dreg' supported");
1787         }
1788
1789         | REG ASSIGN CCREG
1790         {
1791           if (IS_DREG ($1))
1792             {
1793               notethat ("CC2dreg: dregs = CC\n");
1794               $$ = bfin_gen_cc2dreg (0, &$1);
1795             }
1796           else
1797             return yyerror ("Only 'Dreg = CC' supported");
1798         }
1799
1800         | CCREG _ASSIGN_BANG CCREG
1801         {
1802           notethat ("CC2dreg: CC =! CC\n");
1803           $$ = bfin_gen_cc2dreg (3, 0);
1804         }
1805
1806 /* DSPMULT.  */
1807
1808         | HALF_REG ASSIGN multiply_halfregs opt_mode
1809         {
1810           notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1811
1812           if (!IS_H ($1) && $4.MM)
1813             return yyerror ("(M) not allowed with MAC0");
1814
1815           if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1816               && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1817               && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1818             return yyerror ("bad option.");
1819
1820           if (IS_H ($1))
1821             {
1822               $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1823                               IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1824                               &$1, 0, &$3.s0, &$3.s1, 0);
1825             }
1826           else
1827             {
1828               $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1829                               0, 0, IS_H ($3.s0), IS_H ($3.s1),
1830                               &$1, 0, &$3.s0, &$3.s1, 1);
1831             }
1832         }
1833
1834         | REG ASSIGN multiply_halfregs opt_mode
1835         {
1836           /* Odd registers can use (M).  */
1837           if (!IS_DREG ($1))
1838             return yyerror ("Dreg expected");
1839
1840           if (IS_EVEN ($1) && $4.MM)
1841             return yyerror ("(M) not allowed with MAC0");
1842
1843           if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1844               && $4.mod != M_S2RND && $4.mod != M_ISS2)
1845             return yyerror ("bad option");
1846
1847           if (!IS_EVEN ($1))
1848             {
1849               notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1850
1851               $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1852                               IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1853                               &$1, 0, &$3.s0, &$3.s1, 0);
1854             }
1855           else
1856             {
1857               notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1858               $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1859                               0, 0, IS_H ($3.s0), IS_H ($3.s1),
1860                               &$1,  0, &$3.s0, &$3.s1, 1);
1861             }
1862         }
1863
1864         | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1865           HALF_REG ASSIGN multiply_halfregs opt_mode
1866         {
1867           if (!IS_DREG ($1) || !IS_DREG ($6))
1868             return yyerror ("Dregs expected");
1869
1870           if (!IS_HCOMPL($1, $6))
1871             return yyerror ("Dest registers mismatch");
1872
1873           if (check_multiply_halfregs (&$3, &$8) < 0)
1874             return -1;
1875
1876           if ((!IS_H ($1) && $4.MM)
1877               || (!IS_H ($6) && $9.MM))
1878             return yyerror ("(M) not allowed with MAC0");
1879
1880           notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1881                     "dregs_lo = multiply_halfregs opt_mode\n");
1882
1883           if (IS_H ($1))
1884             $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1885                             IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1886                             &$1, 0, &$3.s0, &$3.s1, 1);
1887           else
1888             $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1889                             IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1890                             &$1, 0, &$3.s0, &$3.s1, 1);
1891         }
1892
1893         | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1894         {
1895           if (!IS_DREG ($1) || !IS_DREG ($6))
1896             return yyerror ("Dregs expected");
1897
1898           if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1899               || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1900             return yyerror ("Dest registers mismatch");
1901
1902           if (check_multiply_halfregs (&$3, &$8) < 0)
1903             return -1;
1904
1905           if ((IS_EVEN ($1) && $4.MM)
1906               || (IS_EVEN ($6) && $9.MM))
1907             return yyerror ("(M) not allowed with MAC0");
1908
1909           notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1910                    "dregs = multiply_halfregs opt_mode\n");
1911
1912           if (IS_EVEN ($1))
1913             $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1914                             IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1915                             &$1, 0, &$3.s0, &$3.s1, 1);
1916           else
1917             $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1918                             IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1919                             &$1, 0, &$3.s0, &$3.s1, 1);
1920         }
1921
1922 \f
1923 /* SHIFTs.  */
1924         | a_assign ASHIFT REG_A BY HALF_REG
1925         {
1926           if (!REG_SAME ($1, $3))
1927             return yyerror ("Aregs must be same");
1928
1929           if (IS_DREG ($5) && !IS_H ($5))
1930             {
1931               notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1932               $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1933             }
1934           else
1935             return yyerror ("Dregs expected");
1936         }
1937
1938         | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1939         {
1940           if (IS_DREG ($6) && !IS_H ($6))
1941             {
1942               notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1943               $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1944             }
1945           else
1946             return yyerror ("Dregs expected");
1947         }
1948
1949         | a_assign REG_A LESS_LESS expr
1950         {
1951           if (!REG_SAME ($1, $2))
1952             return yyerror ("Aregs must be same");
1953
1954           if (IS_UIMM ($4, 5))
1955             {
1956               notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1957               $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1958             }
1959           else
1960             return yyerror ("Bad shift value");
1961         }
1962
1963         | REG ASSIGN REG LESS_LESS expr vsmod
1964         {
1965           if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1966             {
1967               if ($6.r0)
1968                 {
1969                   /*  Vector?  */
1970                   notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1971                   $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1972                 }
1973               else
1974                 {
1975                   notethat ("dsp32shiftimm: dregs =  dregs << uimm5 (.)\n");
1976                   $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1977                 }
1978             }
1979           else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1980             {
1981               if (EXPR_VALUE ($5) == 2)
1982                 {
1983                   notethat ("PTR2op: pregs = pregs << 2\n");
1984                   $$ = PTR2OP (&$1, &$3, 1);
1985                 }
1986               else if (EXPR_VALUE ($5) == 1)
1987                 {
1988                   notethat ("COMP3op: pregs = pregs << 1\n");
1989                   $$ = COMP3OP (&$1, &$3, &$3, 5);
1990                 }
1991               else
1992                 return yyerror ("Bad shift value");
1993             }
1994           else
1995             return yyerror ("Bad shift value or register");
1996         }
1997         | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1998         {
1999           if (IS_UIMM ($5, 4))
2000             {
2001               if ($6.s0)
2002                 {
2003                   notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
2004                   $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
2005                 }
2006               else
2007                 {
2008                   notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
2009                   $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
2010                 }
2011             }
2012           else
2013             return yyerror ("Bad shift value");
2014         }
2015         | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
2016         {
2017           int op;
2018
2019           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
2020             {
2021               if ($7.r0)
2022                 {
2023                   op = 1;
2024                   notethat ("dsp32shift: dregs = ASHIFT dregs BY "
2025                            "dregs_lo (V, .)\n");
2026                 }
2027               else
2028                 {
2029
2030                   op = 2;
2031                   notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
2032                 }
2033               $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
2034             }
2035           else
2036             return yyerror ("Dregs expected");
2037         }
2038
2039 /*  EXPADJ.  */
2040         | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2041         {
2042           if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2043             {
2044               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2045               $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2046             }
2047           else
2048             return yyerror ("Bad shift value or register");
2049         }
2050
2051
2052         | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2053         {
2054           if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2055             {
2056               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2057               $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2058             }
2059           else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2060             {
2061               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2062               $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2063             }
2064           else
2065             return yyerror ("Bad shift value or register");
2066         }
2067
2068 /* DEPOSIT.  */
2069
2070         | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2071         {
2072           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2073             {
2074               notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2075               $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2076             }
2077           else
2078             return yyerror ("Register mismatch");
2079         }
2080
2081         | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2082         {
2083           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2084             {
2085               notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2086               $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2087             }
2088           else
2089             return yyerror ("Register mismatch");
2090         }
2091
2092         | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2093         {
2094           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2095             {
2096               notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2097               $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2098             }
2099           else
2100             return yyerror ("Register mismatch");
2101         }
2102
2103         | a_assign REG_A _GREATER_GREATER_GREATER expr
2104         {
2105           if (!REG_SAME ($1, $2))
2106             return yyerror ("Aregs must be same");
2107
2108           if (IS_UIMM ($4, 5))
2109             {
2110               notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2111               $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2112             }
2113           else
2114             return yyerror ("Shift value range error");
2115         }
2116         | a_assign LSHIFT REG_A BY HALF_REG
2117         {
2118           if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2119             {
2120               notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2121               $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2122             }
2123           else
2124             return yyerror ("Register mismatch");
2125         }
2126
2127         | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2128         {
2129           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2130             {
2131               notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2132               $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2133             }
2134           else
2135             return yyerror ("Register mismatch");
2136         }
2137
2138         | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2139         {
2140           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2141             {
2142               notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2143               $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2144             }
2145           else
2146             return yyerror ("Register mismatch");
2147         }
2148
2149         | REG ASSIGN SHIFT REG BY HALF_REG
2150         {
2151           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2152             {
2153               notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2154               $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2155             }
2156           else
2157             return yyerror ("Register mismatch");
2158         }
2159
2160         | a_assign REG_A GREATER_GREATER expr
2161         {
2162           if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2163             {
2164               notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2165               $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2166             }
2167           else
2168             return yyerror ("Accu register expected");
2169         }
2170
2171         | REG ASSIGN REG GREATER_GREATER expr vmod
2172         {
2173           if ($6.r0 == 1)
2174             {
2175               if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2176                 {
2177                   notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2178                   $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2179                 }
2180               else
2181                 return yyerror ("Register mismatch");
2182             }
2183           else
2184             {
2185               if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2186                 {
2187                   notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2188                   $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2189                 }
2190               else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2191                 {
2192                   notethat ("PTR2op: pregs = pregs >> 2\n");
2193                   $$ = PTR2OP (&$1, &$3, 3);
2194                 }
2195               else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2196                 {
2197                   notethat ("PTR2op: pregs = pregs >> 1\n");
2198                   $$ = PTR2OP (&$1, &$3, 4);
2199                 }
2200               else
2201                 return yyerror ("Register mismatch");
2202             }
2203         }
2204         | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2205         {
2206           if (IS_UIMM ($5, 5))
2207             {
2208               notethat ("dsp32shiftimm:  dregs_half =  dregs_half >> uimm5\n");
2209               $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2210             }
2211           else
2212             return yyerror ("Register mismatch");
2213         }
2214         | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2215         {
2216           if (IS_UIMM ($5, 5))
2217             {
2218               notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2219               $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2220                                   $6.s0, HL2 ($1, $3));
2221             }
2222           else
2223             return yyerror ("Register or modifier mismatch");
2224         }
2225
2226
2227         | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2228         {
2229           if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2230             {
2231               if ($6.r0)
2232                 {
2233                   /* Vector?  */
2234                   notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (V, .)\n");
2235                   $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2236                 }
2237               else
2238                 {
2239                   notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (.)\n");
2240                   $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2241                 }
2242             }
2243           else
2244             return yyerror ("Register mismatch");
2245         }
2246
2247         | HALF_REG ASSIGN ONES REG
2248         {
2249           if (IS_DREG_L ($1) && IS_DREG ($4))
2250             {
2251               notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2252               $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2253             }
2254           else
2255             return yyerror ("Register mismatch");
2256         }
2257
2258         | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2259         {
2260           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2261             {
2262               notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2263               $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2264             }
2265           else
2266             return yyerror ("Register mismatch");
2267         }
2268
2269         | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2270         {
2271           if (IS_DREG ($1)
2272               && $7.regno == REG_A0
2273               && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2274             {
2275               notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2276               $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2277             }
2278           else
2279             return yyerror ("Register mismatch");
2280         }
2281
2282         | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2283         {
2284           if (IS_DREG ($1)
2285               && $7.regno == REG_A0
2286               && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2287             {
2288               notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2289               $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2290             }
2291           else
2292             return yyerror ("Register mismatch");
2293         }
2294
2295         | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2296         {
2297           if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2298             {
2299               notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2300               $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2301             }
2302           else
2303             return yyerror ("Register mismatch");
2304         }
2305
2306         | a_assign ROT REG_A BY HALF_REG
2307         {
2308           if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2309             {
2310               notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2311               $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2312             }
2313           else
2314             return yyerror ("Register mismatch");
2315         }
2316
2317         | REG ASSIGN ROT REG BY HALF_REG
2318         {
2319           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2320             {
2321               notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2322               $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2323             }
2324           else
2325             return yyerror ("Register mismatch");
2326         }
2327
2328         | a_assign ROT REG_A BY expr
2329         {
2330           if (IS_IMM ($5, 6))
2331             {
2332               notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2333               $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2334             }
2335           else
2336             return yyerror ("Register mismatch");
2337         }
2338
2339         | REG ASSIGN ROT REG BY expr
2340         {
2341           if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2342             {
2343               $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2344             }
2345           else
2346             return yyerror ("Register mismatch");
2347         }
2348
2349         | HALF_REG ASSIGN SIGNBITS REG_A
2350         {
2351           if (IS_DREG_L ($1))
2352             {
2353               notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2354               $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2355             }
2356           else
2357             return yyerror ("Register mismatch");
2358         }
2359
2360         | HALF_REG ASSIGN SIGNBITS REG
2361         {
2362           if (IS_DREG_L ($1) && IS_DREG ($4))
2363             {
2364               notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2365               $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2366             }
2367           else
2368             return yyerror ("Register mismatch");
2369         }
2370
2371         | HALF_REG ASSIGN SIGNBITS HALF_REG
2372         {
2373           if (IS_DREG_L ($1))
2374             {
2375               notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2376               $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2377             }
2378           else
2379             return yyerror ("Register mismatch");
2380         }
2381
2382         /* The ASR bit is just inverted here. */
2383         | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2384         {
2385           if (IS_DREG_L ($1) && IS_DREG ($5))
2386             {
2387               notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2388               $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2389             }
2390           else
2391             return yyerror ("Register mismatch");
2392         }
2393
2394         | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2395         {
2396           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2397             {
2398               notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2399               $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2400             }
2401           else
2402             return yyerror ("Register mismatch");
2403         }
2404
2405         | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2406         {
2407           if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2408             {
2409               notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2410               $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2411             }
2412           else
2413             return yyerror ("Register mismatch");
2414         }
2415
2416         | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2417         {
2418           if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2419             {
2420               notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2421               $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2422             }
2423           else
2424             return yyerror ("Dregs expected");
2425         }
2426
2427
2428 /* LOGI2op:     BITCLR (dregs, uimm5).  */
2429         | BITCLR LPAREN REG COMMA expr RPAREN
2430         {
2431           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2432             {
2433               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2434               $$ = LOGI2OP ($3, uimm5 ($5), 4);
2435             }
2436           else
2437             return yyerror ("Register mismatch");
2438         }
2439
2440 /* LOGI2op:     BITSET (dregs, uimm5).  */
2441         | BITSET LPAREN REG COMMA expr RPAREN
2442         {
2443           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2444             {
2445               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2446               $$ = LOGI2OP ($3, uimm5 ($5), 2);
2447             }
2448           else
2449             return yyerror ("Register mismatch");
2450         }
2451
2452 /* LOGI2op:     BITTGL (dregs, uimm5).  */
2453         | BITTGL LPAREN REG COMMA expr RPAREN
2454         {
2455           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2456             {
2457               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2458               $$ = LOGI2OP ($3, uimm5 ($5), 3);
2459             }
2460           else
2461             return yyerror ("Register mismatch");
2462         }
2463
2464         | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2465         {
2466           if (IS_DREG ($5) && IS_UIMM ($7, 5))
2467             {
2468               notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2469               $$ = LOGI2OP ($5, uimm5 ($7), 0);
2470             }
2471           else
2472             return yyerror ("Register mismatch or value error");
2473         }
2474
2475         | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2476         {
2477           if (IS_DREG ($5) && IS_UIMM ($7, 5))
2478             {
2479               notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2480               $$ = LOGI2OP ($5, uimm5 ($7), 1);
2481             }
2482           else
2483             return yyerror ("Register mismatch or value error");
2484         }
2485
2486         | IF BANG CCREG REG ASSIGN REG
2487         {
2488           if ((IS_DREG ($4) || IS_PREG ($4))
2489               && (IS_DREG ($6) || IS_PREG ($6)))
2490             {
2491               notethat ("ccMV: IF ! CC gregs = gregs\n");
2492               $$ = CCMV (&$6, &$4, 0);
2493             }
2494           else
2495             return yyerror ("Register mismatch");
2496         }
2497
2498         | IF CCREG REG ASSIGN REG
2499         {
2500           if ((IS_DREG ($5) || IS_PREG ($5))
2501               && (IS_DREG ($3) || IS_PREG ($3)))
2502             {
2503               notethat ("ccMV: IF CC gregs = gregs\n");
2504               $$ = CCMV (&$5, &$3, 1);
2505             }
2506           else
2507             return yyerror ("Register mismatch");
2508         }
2509
2510         | IF BANG CCREG JUMP expr
2511         {
2512           if (IS_PCREL10 ($5))
2513             {
2514               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2515               $$ = BRCC (0, 0, $5);
2516             }
2517           else
2518             return yyerror ("Bad jump offset");
2519         }
2520
2521         | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2522         {
2523           if (IS_PCREL10 ($5))
2524             {
2525               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2526               $$ = BRCC (0, 1, $5);
2527             }
2528           else
2529             return yyerror ("Bad jump offset");
2530         }
2531
2532         | IF CCREG JUMP expr
2533         {
2534           if (IS_PCREL10 ($4))
2535             {
2536               notethat ("BRCC: IF CC JUMP  pcrel11m2\n");
2537               $$ = BRCC (1, 0, $4);
2538             }
2539           else
2540             return yyerror ("Bad jump offset");
2541         }
2542
2543         | IF CCREG JUMP expr LPAREN BP RPAREN
2544         {
2545           if (IS_PCREL10 ($4))
2546             {
2547               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2548               $$ = BRCC (1, 1, $4);
2549             }
2550           else
2551             return yyerror ("Bad jump offset");
2552         }
2553         | NOP
2554         {
2555           notethat ("ProgCtrl: NOP\n");
2556           $$ = PROGCTRL (0, 0);
2557         }
2558
2559         | RTS
2560         {
2561           notethat ("ProgCtrl: RTS\n");
2562           $$ = PROGCTRL (1, 0);
2563         }
2564
2565         | RTI
2566         {
2567           notethat ("ProgCtrl: RTI\n");
2568           $$ = PROGCTRL (1, 1);
2569         }
2570
2571         | RTX
2572         {
2573           notethat ("ProgCtrl: RTX\n");
2574           $$ = PROGCTRL (1, 2);
2575         }
2576
2577         | RTN
2578         {
2579           notethat ("ProgCtrl: RTN\n");
2580           $$ = PROGCTRL (1, 3);
2581         }
2582
2583         | RTE
2584         {
2585           notethat ("ProgCtrl: RTE\n");
2586           $$ = PROGCTRL (1, 4);
2587         }
2588
2589         | IDLE
2590         {
2591           notethat ("ProgCtrl: IDLE\n");
2592           $$ = PROGCTRL (2, 0);
2593         }
2594
2595         | CSYNC
2596         {
2597           notethat ("ProgCtrl: CSYNC\n");
2598           $$ = PROGCTRL (2, 3);
2599         }
2600
2601         | SSYNC
2602         {
2603           notethat ("ProgCtrl: SSYNC\n");
2604           $$ = PROGCTRL (2, 4);
2605         }
2606
2607         | EMUEXCPT
2608         {
2609           notethat ("ProgCtrl: EMUEXCPT\n");
2610           $$ = PROGCTRL (2, 5);
2611         }
2612
2613         | CLI REG
2614         {
2615           if (IS_DREG ($2))
2616             {
2617               notethat ("ProgCtrl: CLI dregs\n");
2618               $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2619             }
2620           else
2621             return yyerror ("Dreg expected for CLI");
2622         }
2623
2624         | STI REG
2625         {
2626           if (IS_DREG ($2))
2627             {
2628               notethat ("ProgCtrl: STI dregs\n");
2629               $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2630             }
2631           else
2632             return yyerror ("Dreg expected for STI");
2633         }
2634
2635         | JUMP LPAREN REG RPAREN
2636         {
2637           if (IS_PREG ($3))
2638             {
2639               notethat ("ProgCtrl: JUMP (pregs )\n");
2640               $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2641             }
2642           else
2643             return yyerror ("Bad register for indirect jump");
2644         }
2645
2646         | CALL LPAREN REG RPAREN
2647         {
2648           if (IS_PREG ($3))
2649             {
2650               notethat ("ProgCtrl: CALL (pregs )\n");
2651               $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2652             }
2653           else
2654             return yyerror ("Bad register for indirect call");
2655         }
2656
2657         | CALL LPAREN PC PLUS REG RPAREN
2658         {
2659           if (IS_PREG ($5))
2660             {
2661               notethat ("ProgCtrl: CALL (PC + pregs )\n");
2662               $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2663             }
2664           else
2665             return yyerror ("Bad register for indirect call");
2666         }
2667
2668         | JUMP LPAREN PC PLUS REG RPAREN
2669         {
2670           if (IS_PREG ($5))
2671             {
2672               notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2673               $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2674             }
2675           else
2676             return yyerror ("Bad register for indirect jump");
2677         }
2678
2679         | RAISE expr
2680         {
2681           if (IS_UIMM ($2, 4))
2682             {
2683               notethat ("ProgCtrl: RAISE uimm4\n");
2684               $$ = PROGCTRL (9, uimm4 ($2));
2685             }
2686           else
2687             return yyerror ("Bad value for RAISE");
2688         }
2689
2690         | EXCPT expr
2691         {
2692                 notethat ("ProgCtrl: EMUEXCPT\n");
2693                 $$ = PROGCTRL (10, uimm4 ($2));
2694         }
2695
2696         | TESTSET LPAREN REG RPAREN
2697         {
2698           if (IS_PREG ($3))
2699             {
2700               if ($3.regno == REG_SP || $3.regno == REG_FP)
2701                 return yyerror ("Bad register for TESTSET");
2702
2703               notethat ("ProgCtrl: TESTSET (pregs )\n");
2704               $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2705             }
2706           else
2707             return yyerror ("Preg expected");
2708         }
2709
2710         | JUMP expr
2711         {
2712           if (IS_PCREL12 ($2))
2713             {
2714               notethat ("UJUMP: JUMP pcrel12\n");
2715               $$ = UJUMP ($2);
2716             }
2717           else
2718             return yyerror ("Bad value for relative jump");
2719         }
2720
2721         | JUMP_DOT_S expr
2722         {
2723           if (IS_PCREL12 ($2))
2724             {
2725               notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2726               $$ = UJUMP($2);
2727             }
2728           else
2729             return yyerror ("Bad value for relative jump");
2730         }
2731
2732         | JUMP_DOT_L expr
2733         {
2734           if (IS_PCREL24 ($2))
2735             {
2736               notethat ("CALLa: jump.l pcrel24\n");
2737               $$ = CALLA ($2, 0);
2738             }
2739           else
2740             return yyerror ("Bad value for long jump");
2741         }
2742
2743         | JUMP_DOT_L pltpc
2744         {
2745           if (IS_PCREL24 ($2))
2746             {
2747               notethat ("CALLa: jump.l pcrel24\n");
2748               $$ = CALLA ($2, 2);
2749             }
2750           else
2751             return yyerror ("Bad value for long jump");
2752         }
2753
2754         | CALL expr
2755         {
2756           if (IS_PCREL24 ($2))
2757             {
2758               notethat ("CALLa: CALL pcrel25m2\n");
2759               $$ = CALLA ($2, 1);
2760             }
2761           else
2762             return yyerror ("Bad call address");
2763         }
2764         | CALL pltpc
2765         {
2766           if (IS_PCREL24 ($2))
2767             {
2768               notethat ("CALLa: CALL pcrel25m2\n");
2769               $$ = CALLA ($2, 2);
2770             }
2771           else
2772             return yyerror ("Bad call address");
2773         }
2774
2775 /* ALU2ops.  */
2776 /* ALU2op:      DIVQ (dregs, dregs).  */
2777         | DIVQ LPAREN REG COMMA REG RPAREN
2778         {
2779           if (IS_DREG ($3) && IS_DREG ($5))
2780             $$ = ALU2OP (&$3, &$5, 8);
2781           else
2782             return yyerror ("Bad registers for DIVQ");
2783         }
2784
2785         | DIVS LPAREN REG COMMA REG RPAREN
2786         {
2787           if (IS_DREG ($3) && IS_DREG ($5))
2788             $$ = ALU2OP (&$3, &$5, 9);
2789           else
2790             return yyerror ("Bad registers for DIVS");
2791         }
2792
2793         | REG ASSIGN MINUS REG vsmod
2794         {
2795           if (IS_DREG ($1) && IS_DREG ($4))
2796             {
2797               if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2798                 {
2799                   notethat ("ALU2op: dregs = - dregs\n");
2800                   $$ = ALU2OP (&$1, &$4, 14);
2801                 }
2802               else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2803                 {
2804                   notethat ("dsp32alu: dregs = - dregs (.)\n");
2805                   $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2806                 }
2807               else
2808                 {
2809                   notethat ("dsp32alu: dregs = - dregs (.)\n");
2810                   $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2811                 }
2812             }
2813           else
2814             return yyerror ("Dregs expected");
2815         }
2816
2817         | REG ASSIGN TILDA REG
2818         {
2819           if (IS_DREG ($1) && IS_DREG ($4))
2820             {
2821               notethat ("ALU2op: dregs = ~dregs\n");
2822               $$ = ALU2OP (&$1, &$4, 15);
2823             }
2824           else
2825             return yyerror ("Dregs expected");
2826         }
2827
2828         | REG _GREATER_GREATER_ASSIGN REG
2829         {
2830           if (IS_DREG ($1) && IS_DREG ($3))
2831             {
2832               notethat ("ALU2op: dregs >>= dregs\n");
2833               $$ = ALU2OP (&$1, &$3, 1);
2834             }
2835           else
2836             return yyerror ("Dregs expected");
2837         }
2838
2839         | REG _GREATER_GREATER_ASSIGN expr
2840         {
2841           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2842             {
2843               notethat ("LOGI2op: dregs >>= uimm5\n");
2844               $$ = LOGI2OP ($1, uimm5 ($3), 6);
2845             }
2846           else
2847             return yyerror ("Dregs expected or value error");
2848         }
2849
2850         | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2851         {
2852           if (IS_DREG ($1) && IS_DREG ($3))
2853             {
2854               notethat ("ALU2op: dregs >>>= dregs\n");
2855               $$ = ALU2OP (&$1, &$3, 0);
2856             }
2857           else
2858             return yyerror ("Dregs expected");
2859         }
2860
2861         | REG _LESS_LESS_ASSIGN REG
2862         {
2863           if (IS_DREG ($1) && IS_DREG ($3))
2864             {
2865               notethat ("ALU2op: dregs <<= dregs\n");
2866               $$ = ALU2OP (&$1, &$3, 2);
2867             }
2868           else
2869             return yyerror ("Dregs expected");
2870         }
2871
2872         | REG _LESS_LESS_ASSIGN expr
2873         {
2874           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2875             {
2876               notethat ("LOGI2op: dregs <<= uimm5\n");
2877               $$ = LOGI2OP ($1, uimm5 ($3), 7);
2878             }
2879           else
2880             return yyerror ("Dregs expected or const value error");
2881         }
2882
2883
2884         | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2885         {
2886           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2887             {
2888               notethat ("LOGI2op: dregs >>>= uimm5\n");
2889               $$ = LOGI2OP ($1, uimm5 ($3), 5);
2890             }
2891           else
2892             return yyerror ("Dregs expected");
2893         }
2894
2895 /* Cache Control.  */
2896
2897         | FLUSH LBRACK REG RBRACK
2898         {
2899           notethat ("CaCTRL: FLUSH [ pregs ]\n");
2900           if (IS_PREG ($3))
2901             $$ = CACTRL (&$3, 0, 2);
2902           else
2903             return yyerror ("Bad register(s) for FLUSH");
2904         }
2905
2906         | FLUSH reg_with_postinc
2907         {
2908           if (IS_PREG ($2))
2909             {
2910               notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2911               $$ = CACTRL (&$2, 1, 2);
2912             }
2913           else
2914             return yyerror ("Bad register(s) for FLUSH");
2915         }
2916
2917         | FLUSHINV LBRACK REG RBRACK
2918         {
2919           if (IS_PREG ($3))
2920             {
2921               notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2922               $$ = CACTRL (&$3, 0, 1);
2923             }
2924           else
2925             return yyerror ("Bad register(s) for FLUSH");
2926         }
2927
2928         | FLUSHINV reg_with_postinc
2929         {
2930           if (IS_PREG ($2))
2931             {
2932               notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2933               $$ = CACTRL (&$2, 1, 1);
2934             }
2935           else
2936             return yyerror ("Bad register(s) for FLUSH");
2937         }
2938
2939 /* CaCTRL:      IFLUSH [pregs].  */
2940         | IFLUSH LBRACK REG RBRACK
2941         {
2942           if (IS_PREG ($3))
2943             {
2944               notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2945               $$ = CACTRL (&$3, 0, 3);
2946             }
2947           else
2948             return yyerror ("Bad register(s) for FLUSH");
2949         }
2950
2951         | IFLUSH reg_with_postinc
2952         {
2953           if (IS_PREG ($2))
2954             {
2955               notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2956               $$ = CACTRL (&$2, 1, 3);
2957             }
2958           else
2959             return yyerror ("Bad register(s) for FLUSH");
2960         }
2961
2962         | PREFETCH LBRACK REG RBRACK
2963         {
2964           if (IS_PREG ($3))
2965             {
2966               notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2967               $$ = CACTRL (&$3, 0, 0);
2968             }
2969           else
2970             return yyerror ("Bad register(s) for PREFETCH");
2971         }
2972
2973         | PREFETCH reg_with_postinc
2974         {
2975           if (IS_PREG ($2))
2976             {
2977               notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2978               $$ = CACTRL (&$2, 1, 0);
2979             }
2980           else
2981             return yyerror ("Bad register(s) for PREFETCH");
2982         }
2983
2984 /* LOAD/STORE.  */
2985 /* LDST:        B [ pregs <post_op> ] = dregs.  */
2986
2987         | B LBRACK REG post_op RBRACK ASSIGN REG
2988         {
2989           if (!IS_DREG ($7))
2990             return yyerror ("Dreg expected for source operand");
2991           if (!IS_PREG ($3))
2992             return yyerror ("Preg expected in address");
2993
2994           notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2995           $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2996         }
2997
2998 /* LDSTidxI:    B [ pregs + imm16 ] = dregs.  */
2999         | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
3000         {
3001           Expr_Node *tmp = $5;
3002
3003           if (!IS_DREG ($8))
3004             return yyerror ("Dreg expected for source operand");
3005           if (!IS_PREG ($3))
3006             return yyerror ("Preg expected in address");
3007
3008           if (IS_RELOC ($5))
3009             return yyerror ("Plain symbol used as offset");
3010
3011           if ($4.r0)
3012             tmp = unary (Expr_Op_Type_NEG, tmp);
3013
3014           if (in_range_p (tmp, -32768, 32767, 0))
3015             {
3016               notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
3017               $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
3018             }
3019           else
3020             return yyerror ("Displacement out of range");
3021         }
3022
3023
3024 /* LDSTii:      W [ pregs + uimm4s2 ] = dregs.  */
3025         | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
3026         {
3027           Expr_Node *tmp = $5;
3028
3029           if (!IS_DREG ($8))
3030             return yyerror ("Dreg expected for source operand");
3031           if (!IS_PREG ($3))
3032             return yyerror ("Preg expected in address");
3033
3034           if ($4.r0)
3035             tmp = unary (Expr_Op_Type_NEG, tmp);
3036
3037           if (IS_RELOC ($5))
3038             return yyerror ("Plain symbol used as offset");
3039
3040           if (in_range_p (tmp, 0, 30, 1))
3041             {
3042               notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3043               $$ = LDSTII (&$3, &$8, tmp, 1, 1);
3044             }
3045           else if (in_range_p (tmp, -65536, 65535, 1))
3046             {
3047               notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3048               $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3049             }
3050           else
3051             return yyerror ("Displacement out of range");
3052         }
3053
3054 /* LDST:        W [ pregs <post_op> ] = dregs.  */
3055         | W LBRACK REG post_op RBRACK ASSIGN REG
3056         {
3057           if (!IS_DREG ($7))
3058             return yyerror ("Dreg expected for source operand");
3059           if (!IS_PREG ($3))
3060             return yyerror ("Preg expected in address");
3061
3062           notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3063           $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3064         }
3065
3066         | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3067         {
3068           if (!IS_DREG ($7))
3069             return yyerror ("Dreg expected for source operand");
3070           if ($4.x0 == 2)
3071             {
3072               if (!IS_IREG ($3) && !IS_PREG ($3))
3073                 return yyerror ("Ireg or Preg expected in address");
3074             }
3075           else if (!IS_IREG ($3))
3076             return yyerror ("Ireg expected in address");
3077
3078           if (IS_IREG ($3))
3079             {
3080               notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3081               $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3082             }
3083           else
3084             {
3085               notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3086               $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3087             }
3088         }
3089
3090 /* LDSTiiFP:    [ FP - const ] = dpregs.  */
3091         | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3092         {
3093           Expr_Node *tmp = $4;
3094           int ispreg = IS_PREG ($7);
3095
3096           if (!IS_PREG ($2))
3097             return yyerror ("Preg expected in address");
3098
3099           if (!IS_DREG ($7) && !ispreg)
3100             return yyerror ("Preg expected for source operand");
3101
3102           if ($3.r0)
3103             tmp = unary (Expr_Op_Type_NEG, tmp);
3104
3105           if (IS_RELOC ($4))
3106             return yyerror ("Plain symbol used as offset");
3107
3108           if (in_range_p (tmp, 0, 63, 3))
3109             {
3110               notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3111               $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3112             }
3113           else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3114             {
3115               notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3116               tmp = unary (Expr_Op_Type_NEG, tmp);
3117               $$ = LDSTIIFP (tmp, &$7, 1);
3118             }
3119           else if (in_range_p (tmp, -131072, 131071, 3))
3120             {
3121               notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3122               $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3123             }
3124           else
3125             return yyerror ("Displacement out of range");
3126         }
3127
3128         | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3129         {
3130           Expr_Node *tmp = $7;
3131           if (!IS_DREG ($1))
3132             return yyerror ("Dreg expected for destination operand");
3133           if (!IS_PREG ($5))
3134             return yyerror ("Preg expected in address");
3135
3136           if ($6.r0)
3137             tmp = unary (Expr_Op_Type_NEG, tmp);
3138
3139           if (IS_RELOC ($7))
3140             return yyerror ("Plain symbol used as offset");
3141
3142           if (in_range_p (tmp, 0, 30, 1))
3143             {
3144               notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3145               $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3146             }
3147           else if (in_range_p (tmp, -65536, 65535, 1))
3148             {
3149               notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3150               $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3151             }
3152           else
3153             return yyerror ("Displacement out of range");
3154         }
3155
3156         | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3157         {
3158           if (!IS_DREG ($1))
3159             return yyerror ("Dreg expected for source operand");
3160           if ($6.x0 == 2)
3161             {
3162               if (!IS_IREG ($5) && !IS_PREG ($5))
3163                 return yyerror ("Ireg or Preg expected in address");
3164             }
3165           else if (!IS_IREG ($5))
3166             return yyerror ("Ireg expected in address");
3167
3168           if (IS_IREG ($5))
3169             {
3170               notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3171               $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3172             }
3173           else
3174             {
3175               notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3176               $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3177             }
3178         }
3179
3180
3181         | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3182         {
3183           if (!IS_DREG ($1))
3184             return yyerror ("Dreg expected for destination operand");
3185           if (!IS_PREG ($5))
3186             return yyerror ("Preg expected in address");
3187
3188           notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3189           $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3190         }
3191
3192         | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3193         {
3194           if (!IS_DREG ($1))
3195             return yyerror ("Dreg expected for destination operand");
3196           if (!IS_PREG ($5) || !IS_PREG ($7))
3197             return yyerror ("Preg expected in address");
3198
3199           notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3200           $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3201         }
3202
3203         | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3204         {
3205           if (!IS_DREG ($1))
3206             return yyerror ("Dreg expected for destination operand");
3207           if (!IS_PREG ($5) || !IS_PREG ($7))
3208             return yyerror ("Preg expected in address");
3209
3210           notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3211           $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3212         }
3213
3214         | LBRACK REG post_op RBRACK ASSIGN REG
3215         {
3216           if (!IS_IREG ($2) && !IS_PREG ($2))
3217             return yyerror ("Ireg or Preg expected in address");
3218           else if (IS_IREG ($2) && !IS_DREG ($6))
3219             return yyerror ("Dreg expected for source operand");
3220           else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3221             return yyerror ("Dreg or Preg expected for source operand");
3222
3223           if (IS_IREG ($2))
3224             {
3225               notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3226               $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3227             }
3228           else if (IS_DREG ($6))
3229             {
3230               notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3231               $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3232             }
3233           else
3234             {
3235               notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3236               $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3237             }
3238         }
3239
3240         | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3241         {
3242           if (!IS_DREG ($7))
3243             return yyerror ("Dreg expected for source operand");
3244
3245           if (IS_IREG ($2) && IS_MREG ($4))
3246             {
3247               notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3248               $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3249             }
3250           else if (IS_PREG ($2) && IS_PREG ($4))
3251             {
3252               notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3253               $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3254             }
3255           else
3256             return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3257         }
3258
3259         | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3260         {
3261           if (!IS_DREG ($8))
3262             return yyerror ("Dreg expected for source operand");
3263
3264           if (IS_PREG ($3) && IS_PREG ($5))
3265             {
3266               notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3267               $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3268             }
3269           else
3270             return yyerror ("Preg ++ Preg expected in address");
3271         }
3272
3273         | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3274         {
3275           Expr_Node *tmp = $7;
3276           if (!IS_DREG ($1))
3277             return yyerror ("Dreg expected for destination operand");
3278           if (!IS_PREG ($5))
3279             return yyerror ("Preg expected in address");
3280
3281           if ($6.r0)
3282             tmp = unary (Expr_Op_Type_NEG, tmp);
3283
3284           if (IS_RELOC ($7))
3285             return yyerror ("Plain symbol used as offset");
3286
3287           if (in_range_p (tmp, -32768, 32767, 0))
3288             {
3289               notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3290                        $9.r0 ? 'X' : 'Z');
3291               $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3292             }
3293           else
3294             return yyerror ("Displacement out of range");
3295         }
3296
3297         | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3298         {
3299           if (!IS_DREG ($1))
3300             return yyerror ("Dreg expected for destination operand");
3301           if (!IS_PREG ($5))
3302             return yyerror ("Preg expected in address");
3303
3304           notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3305                     $8.r0 ? 'X' : 'Z');
3306           $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3307         }
3308
3309         | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3310         {
3311           if (!IS_DREG ($1))
3312             return yyerror ("Dreg expected for destination operand");
3313
3314           if (IS_IREG ($4) && IS_MREG ($6))
3315             {
3316               notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3317               $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3318             }
3319           else if (IS_PREG ($4) && IS_PREG ($6))
3320             {
3321               notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3322               $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3323             }
3324           else
3325             return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3326         }
3327
3328         | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3329         {
3330           Expr_Node *tmp = $6;
3331           int ispreg = IS_PREG ($1);
3332           int isgot = IS_RELOC($6);
3333
3334           if (!IS_PREG ($4))
3335             return yyerror ("Preg expected in address");
3336
3337           if (!IS_DREG ($1) && !ispreg)
3338             return yyerror ("Dreg or Preg expected for destination operand");
3339
3340           if (tmp->type == Expr_Node_Reloc
3341               && strcmp (tmp->value.s_value,
3342                          "_current_shared_library_p5_offset_") != 0)
3343             return yyerror ("Plain symbol used as offset");
3344
3345           if ($5.r0)
3346             tmp = unary (Expr_Op_Type_NEG, tmp);
3347
3348           if (isgot)
3349             {
3350               notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3351               $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3352             }
3353           else if (in_range_p (tmp, 0, 63, 3))
3354             {
3355               notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3356               $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3357             }
3358           else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3359             {
3360               notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3361               tmp = unary (Expr_Op_Type_NEG, tmp);
3362               $$ = LDSTIIFP (tmp, &$1, 0);
3363             }
3364           else if (in_range_p (tmp, -131072, 131071, 3))
3365             {
3366               notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3367               $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3368
3369             }
3370           else
3371             return yyerror ("Displacement out of range");
3372         }
3373
3374         | REG ASSIGN LBRACK REG post_op RBRACK
3375         {
3376           if (!IS_IREG ($4) && !IS_PREG ($4))
3377             return yyerror ("Ireg or Preg expected in address");
3378           else if (IS_IREG ($4) && !IS_DREG ($1))
3379             return yyerror ("Dreg expected in destination operand");
3380           else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3381                    && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3382             return yyerror ("Dreg or Preg expected in destination operand");
3383
3384           if (IS_IREG ($4))
3385             {
3386               notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3387               $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3388             }
3389           else if (IS_DREG ($1))
3390             {
3391               notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3392               $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3393             }
3394           else if (IS_PREG ($1))
3395             {
3396               if (REG_SAME ($1, $4) && $5.x0 != 2)
3397                 return yyerror ("Pregs can't be same");
3398
3399               notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3400               $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3401             }
3402           else
3403             {
3404               notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3405               $$ = PUSHPOPREG (&$1, 0);
3406             }
3407         }
3408
3409
3410 /*  PushPopMultiple.  */
3411         | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3412         {
3413           if ($1.regno != REG_SP)
3414             yyerror ("Stack Pointer expected");
3415           if ($4.regno == REG_R7
3416               && IN_RANGE ($6, 0, 7)
3417               && $8.regno == REG_P5
3418               && IN_RANGE ($10, 0, 5))
3419             {
3420               notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3421               $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3422             }
3423           else
3424             return yyerror ("Bad register for PushPopMultiple");
3425         }
3426
3427         | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3428         {
3429           if ($1.regno != REG_SP)
3430             yyerror ("Stack Pointer expected");
3431
3432           if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3433             {
3434               notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3435               $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3436             }
3437           else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3438             {
3439               notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3440               $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3441             }
3442           else
3443             return yyerror ("Bad register for PushPopMultiple");
3444         }
3445
3446         | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3447         {
3448           if ($11.regno != REG_SP)
3449             yyerror ("Stack Pointer expected");
3450           if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3451               && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3452             {
3453               notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3454               $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3455             }
3456           else
3457             return yyerror ("Bad register range for PushPopMultiple");
3458         }
3459
3460         | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3461         {
3462           if ($7.regno != REG_SP)
3463             yyerror ("Stack Pointer expected");
3464
3465           if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3466             {
3467               notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3468               $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3469             }
3470           else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3471             {
3472               notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3473               $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3474             }
3475           else
3476             return yyerror ("Bad register range for PushPopMultiple");
3477         }
3478
3479         | reg_with_predec ASSIGN REG
3480         {
3481           if ($1.regno != REG_SP)
3482             yyerror ("Stack Pointer expected");
3483
3484           if (IS_ALLREG ($3))
3485             {
3486               notethat ("PushPopReg: [ -- SP ] = allregs\n");
3487               $$ = PUSHPOPREG (&$3, 1);
3488             }
3489           else
3490             return yyerror ("Bad register for PushPopReg");
3491         }
3492
3493 /* Linkage.  */
3494
3495         | LINK expr
3496         {
3497           if (IS_URANGE (16, $2, 0, 4))
3498             $$ = LINKAGE (0, uimm16s4 ($2));
3499           else
3500             return yyerror ("Bad constant for LINK");
3501         }
3502
3503         | UNLINK
3504         {
3505                 notethat ("linkage: UNLINK\n");
3506                 $$ = LINKAGE (1, 0);
3507         }
3508
3509
3510 /* LSETUP.  */
3511
3512         | LSETUP LPAREN expr COMMA expr RPAREN REG
3513         {
3514           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3515             {
3516               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3517               $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3518             }
3519           else
3520             return yyerror ("Bad register or values for LSETUP");
3521
3522         }
3523         | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3524         {
3525           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3526               && IS_PREG ($9) && IS_CREG ($7))
3527             {
3528               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3529               $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3530             }
3531           else
3532             return yyerror ("Bad register or values for LSETUP");
3533         }
3534
3535         | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3536         {
3537           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3538               && IS_PREG ($9) && IS_CREG ($7)
3539               && EXPR_VALUE ($11) == 1)
3540             {
3541               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3542               $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3543             }
3544           else
3545             return yyerror ("Bad register or values for LSETUP");
3546         }
3547
3548 /* LOOP.  */
3549         | LOOP expr REG
3550         {
3551           if (!IS_RELOC ($2))
3552             return yyerror ("Invalid expression in loop statement");
3553           if (!IS_CREG ($3))
3554             return yyerror ("Invalid loop counter register");
3555         $$ = bfin_gen_loop ($2, &$3, 0, 0);
3556         }
3557         | LOOP expr REG ASSIGN REG
3558         {
3559           if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3560             {
3561               notethat ("Loop: LOOP expr counters = pregs\n");
3562               $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3563             }
3564           else
3565             return yyerror ("Bad register or values for LOOP");
3566         }
3567         | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3568         {
3569           if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3570             {
3571               notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3572               $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3573             }
3574           else
3575             return yyerror ("Bad register or values for LOOP");
3576         }
3577
3578 /* LOOP_BEGIN.  */
3579         | LOOP_BEGIN NUMBER
3580         {
3581           Expr_Node_Value val;
3582           val.i_value = $2;
3583           Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3584           bfin_loop_attempt_create_label (tmp, 1);
3585           if (!IS_RELOC (tmp))
3586             return yyerror ("Invalid expression in LOOP_BEGIN statement");
3587           bfin_loop_beginend (tmp, 1);
3588           $$ = 0;
3589         }
3590         | LOOP_BEGIN expr
3591         {
3592           if (!IS_RELOC ($2))
3593             return yyerror ("Invalid expression in LOOP_BEGIN statement");
3594
3595           bfin_loop_beginend ($2, 1);
3596           $$ = 0;
3597         }
3598
3599 /* LOOP_END.  */
3600         | LOOP_END NUMBER
3601         {
3602           Expr_Node_Value val;
3603           val.i_value = $2;
3604           Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3605           bfin_loop_attempt_create_label (tmp, 1);
3606           if (!IS_RELOC (tmp))
3607             return yyerror ("Invalid expression in LOOP_END statement");
3608           bfin_loop_beginend (tmp, 0);
3609           $$ = 0;
3610         }
3611         | LOOP_END expr
3612         {
3613           if (!IS_RELOC ($2))
3614             return yyerror ("Invalid expression in LOOP_END statement");
3615
3616           bfin_loop_beginend ($2, 0);
3617           $$ = 0;
3618         }
3619
3620 /* pseudoDEBUG.  */
3621
3622         | ABORT
3623         {
3624           notethat ("psedoDEBUG: ABORT\n");
3625           $$ = bfin_gen_pseudodbg (3, 3, 0);
3626         }
3627
3628         | DBG
3629         {
3630           notethat ("pseudoDEBUG: DBG\n");
3631           $$ = bfin_gen_pseudodbg (3, 7, 0);
3632         }
3633         | DBG REG_A
3634         {
3635           notethat ("pseudoDEBUG: DBG REG_A\n");
3636           $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3637         }
3638         | DBG REG
3639         {
3640           notethat ("pseudoDEBUG: DBG allregs\n");
3641           $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, ($2.regno & CLASS_MASK) >> 4);
3642         }
3643
3644         | DBGCMPLX LPAREN REG RPAREN
3645         {
3646           if (!IS_DREG ($3))
3647             return yyerror ("Dregs expected");
3648           notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3649           $$ = bfin_gen_pseudodbg (3, 6, ($3.regno & CODE_MASK) >> 4);
3650         }
3651
3652         | DBGHALT
3653         {
3654           notethat ("psedoDEBUG: DBGHALT\n");
3655           $$ = bfin_gen_pseudodbg (3, 5, 0);
3656         }
3657
3658         | HLT
3659         {
3660           notethat ("psedoDEBUG: HLT\n");
3661           $$ = bfin_gen_pseudodbg (3, 4, 0);
3662         }
3663
3664         | DBGA LPAREN HALF_REG COMMA expr RPAREN
3665         {
3666           notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
3667           $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3668         }
3669
3670         | DBGAH LPAREN REG COMMA expr RPAREN
3671         {
3672           notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
3673           $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3674         }
3675
3676         | DBGAL LPAREN REG COMMA expr RPAREN
3677         {
3678           notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
3679           $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3680         }
3681
3682         | OUTC expr
3683         {
3684           if (!IS_UIMM ($2, 8))
3685             return yyerror ("Constant out of range");
3686           notethat ("psedodbg_assert: OUTC uimm8\n");
3687           $$ = bfin_gen_pseudochr (uimm8 ($2));
3688         }
3689
3690         | OUTC REG
3691         {
3692           if (!IS_DREG ($2))
3693             return yyerror ("Dregs expected");
3694           notethat ("psedodbg_assert: OUTC dreg\n");
3695           $$ = bfin_gen_pseudodbg (2, $2.regno & CODE_MASK, 0);
3696         }
3697
3698 ;
3699
3700 /*  AUX RULES.  */
3701
3702 /*  Register rules.  */
3703
3704 REG_A:  REG_A_DOUBLE_ZERO
3705         {
3706         $$ = $1;
3707         }
3708         | REG_A_DOUBLE_ONE
3709         {
3710         $$ = $1;
3711         }
3712         ;
3713
3714
3715 /*  Modifiers. */
3716
3717 opt_mode:
3718         {
3719         $$.MM = 0;
3720         $$.mod = 0;
3721         }
3722         | LPAREN M COMMA MMOD RPAREN
3723         {
3724         $$.MM = 1;
3725         $$.mod = $4;
3726         }
3727         | LPAREN MMOD COMMA M RPAREN
3728         {
3729         $$.MM = 1;
3730         $$.mod = $2;
3731         }
3732         | LPAREN MMOD RPAREN
3733         {
3734         $$.MM = 0;
3735         $$.mod = $2;
3736         }
3737         | LPAREN M RPAREN
3738         {
3739         $$.MM = 1;
3740         $$.mod = 0;
3741         }
3742         ;
3743
3744 asr_asl: LPAREN ASL RPAREN
3745         {
3746         $$.r0 = 1;
3747         }
3748         | LPAREN ASR RPAREN
3749         {
3750         $$.r0 = 0;
3751         }
3752         ;
3753
3754 sco:
3755         {
3756         $$.s0 = 0;
3757         $$.x0 = 0;
3758         }
3759         | S
3760         {
3761         $$.s0 = 1;
3762         $$.x0 = 0;
3763         }
3764         | CO
3765         {
3766         $$.s0 = 0;
3767         $$.x0 = 1;
3768         }
3769         | SCO
3770         {
3771         $$.s0 = 1;
3772         $$.x0 = 1;
3773         }
3774         ;
3775
3776 asr_asl_0:
3777         ASL
3778         {
3779         $$.r0 = 1;
3780         }
3781         | ASR
3782         {
3783         $$.r0 = 0;
3784         }
3785         ;
3786
3787 amod0:
3788         {
3789         $$.s0 = 0;
3790         $$.x0 = 0;
3791         }
3792         | LPAREN sco RPAREN
3793         {
3794         $$.s0 = $2.s0;
3795         $$.x0 = $2.x0;
3796         }
3797         ;
3798
3799 amod1:
3800         {
3801         $$.s0 = 0;
3802         $$.x0 = 0;
3803         $$.aop = 0;
3804         }
3805         | LPAREN NS RPAREN
3806         {
3807         $$.s0 = 0;
3808         $$.x0 = 0;
3809         $$.aop = 1;
3810         }
3811         | LPAREN S RPAREN
3812         {
3813         $$.s0 = 1;
3814         $$.x0 = 0;
3815         $$.aop = 1;
3816         }
3817         ;
3818
3819 amod2:
3820         {
3821         $$.r0 = 0;
3822         $$.s0 = 0;
3823         $$.x0 = 0;
3824         }
3825         | LPAREN asr_asl_0 RPAREN
3826         {
3827         $$.r0 = 2 + $2.r0;
3828         $$.s0 = 0;
3829         $$.x0 = 0;
3830         }
3831         | LPAREN sco RPAREN
3832         {
3833         $$.r0 = 0;
3834         $$.s0 = $2.s0;
3835         $$.x0 = $2.x0;
3836         }
3837         | LPAREN asr_asl_0 COMMA sco RPAREN
3838         {
3839         $$.r0 = 2 + $2.r0;
3840         $$.s0 = $4.s0;
3841         $$.x0 = $4.x0;
3842         }
3843         | LPAREN sco COMMA asr_asl_0 RPAREN
3844         {
3845         $$.r0 = 2 + $4.r0;
3846         $$.s0 = $2.s0;
3847         $$.x0 = $2.x0;
3848         }
3849         ;
3850
3851 xpmod:
3852         {
3853         $$.r0 = 0;
3854         }
3855         | LPAREN Z RPAREN
3856         {
3857         $$.r0 = 0;
3858         }
3859         | LPAREN X RPAREN
3860         {
3861         $$.r0 = 1;
3862         }
3863         ;
3864
3865 xpmod1:
3866         {
3867         $$.r0 = 0;
3868         }
3869         | LPAREN X RPAREN
3870         {
3871         $$.r0 = 0;
3872         }
3873         | LPAREN Z RPAREN
3874         {
3875         $$.r0 = 1;
3876         }
3877         ;
3878
3879 vsmod:
3880         {
3881         $$.r0 = 0;
3882         $$.s0 = 0;
3883         $$.aop = 0;
3884         }
3885         | LPAREN NS RPAREN
3886         {
3887         $$.r0 = 0;
3888         $$.s0 = 0;
3889         $$.aop = 3;
3890         }
3891         | LPAREN S RPAREN
3892         {
3893         $$.r0 = 0;
3894         $$.s0 = 1;
3895         $$.aop = 3;
3896         }
3897         | LPAREN V RPAREN
3898         {
3899         $$.r0 = 1;
3900         $$.s0 = 0;
3901         $$.aop = 3;
3902         }
3903         | LPAREN V COMMA S RPAREN
3904         {
3905         $$.r0 = 1;
3906         $$.s0 = 1;
3907         }
3908         | LPAREN S COMMA V RPAREN
3909         {
3910         $$.r0 = 1;
3911         $$.s0 = 1;
3912         }
3913         ;
3914
3915 vmod:
3916         {
3917         $$.r0 = 0;
3918         }
3919         | LPAREN V RPAREN
3920         {
3921         $$.r0 = 1;
3922         }
3923         ;
3924
3925 smod:
3926         {
3927         $$.s0 = 0;
3928         }
3929         | LPAREN S RPAREN
3930         {
3931         $$.s0 = 1;
3932         }
3933         ;
3934
3935 searchmod:
3936           GE
3937         {
3938         $$.r0 = 1;
3939         }
3940         | GT
3941         {
3942         $$.r0 = 0;
3943         }
3944         | LE
3945         {
3946         $$.r0 = 3;
3947         }
3948         | LT
3949         {
3950         $$.r0 = 2;
3951         }
3952         ;
3953
3954 aligndir:
3955         {
3956         $$.r0 = 0;
3957         }
3958         | LPAREN R RPAREN
3959         {
3960         $$.r0 = 1;
3961         }
3962         ;
3963
3964 byteop_mod:
3965         LPAREN R RPAREN
3966         {
3967         $$.r0 = 0;
3968         $$.s0 = 1;
3969         }
3970         | LPAREN MMOD RPAREN
3971         {
3972         if ($2 != M_T)
3973           return yyerror ("Bad modifier");
3974         $$.r0 = 1;
3975         $$.s0 = 0;
3976         }
3977         | LPAREN MMOD COMMA R RPAREN
3978         {
3979         if ($2 != M_T)
3980           return yyerror ("Bad modifier");
3981         $$.r0 = 1;
3982         $$.s0 = 1;
3983         }
3984         | LPAREN R COMMA MMOD RPAREN
3985         {
3986         if ($4 != M_T)
3987           return yyerror ("Bad modifier");
3988         $$.r0 = 1;
3989         $$.s0 = 1;
3990         }
3991         ;
3992
3993
3994
3995 c_align:
3996         ALIGN8
3997         {
3998         $$.r0 = 0;
3999         }
4000         | ALIGN16
4001         {
4002         $$.r0 = 1;
4003         }
4004         | ALIGN24
4005         {
4006         $$.r0 = 2;
4007         }
4008         ;
4009
4010 w32_or_nothing:
4011         {
4012         $$.r0 = 0;
4013         }
4014         | LPAREN MMOD RPAREN
4015         {
4016           if ($2 == M_W32)
4017             $$.r0 = 1;
4018           else
4019             return yyerror ("Only (W32) allowed");
4020         }
4021         ;
4022
4023 iu_or_nothing:
4024         {
4025         $$.r0 = 1;
4026         }
4027         | LPAREN MMOD RPAREN
4028         {
4029           if ($2 == M_IU)
4030             $$.r0 = 3;
4031           else
4032             return yyerror ("(IU) expected");
4033         }
4034         ;
4035
4036 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
4037         {
4038         $$ = $3;
4039         }
4040         ;
4041
4042 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
4043         {
4044         $$ = $2;
4045         }
4046         ;
4047
4048 /* Operators.  */
4049
4050 min_max:
4051         MIN
4052         {
4053         $$.r0 = 1;
4054         }
4055         | MAX
4056         {
4057         $$.r0 = 0;
4058         }
4059         ;
4060
4061 op_bar_op:
4062         _PLUS_BAR_PLUS
4063         {
4064         $$.r0 = 0;
4065         }
4066         | _PLUS_BAR_MINUS
4067         {
4068         $$.r0 = 1;
4069         }
4070         | _MINUS_BAR_PLUS
4071         {
4072         $$.r0 = 2;
4073         }
4074         | _MINUS_BAR_MINUS
4075         {
4076         $$.r0 = 3;
4077         }
4078         ;
4079
4080 plus_minus:
4081         PLUS
4082         {
4083         $$.r0 = 0;
4084         }
4085         | MINUS
4086         {
4087         $$.r0 = 1;
4088         }
4089         ;
4090
4091 rnd_op:
4092         LPAREN RNDH RPAREN
4093         {
4094           $$.r0 = 1;    /* HL.  */
4095           $$.s0 = 0;    /* s.  */
4096           $$.x0 = 0;    /* x.  */
4097           $$.aop = 0;   /* aop.  */
4098         }
4099
4100         | LPAREN TH RPAREN
4101         {
4102           $$.r0 = 1;    /* HL.  */
4103           $$.s0 = 0;    /* s.  */
4104           $$.x0 = 0;    /* x.  */
4105           $$.aop = 1;   /* aop.  */
4106         }
4107
4108         | LPAREN RNDL RPAREN
4109         {
4110           $$.r0 = 0;    /* HL.  */
4111           $$.s0 = 0;    /* s.  */
4112           $$.x0 = 0;    /* x.  */
4113           $$.aop = 0;   /* aop.  */
4114         }
4115
4116         | LPAREN TL RPAREN
4117         {
4118           $$.r0 = 0;    /* HL.  */
4119           $$.s0 = 0;    /* s.  */
4120           $$.x0 = 0;    /* x.  */
4121           $$.aop = 1;
4122         }
4123
4124         | LPAREN RNDH COMMA R RPAREN
4125         {
4126           $$.r0 = 1;    /* HL.  */
4127           $$.s0 = 1;    /* s.  */
4128           $$.x0 = 0;    /* x.  */
4129           $$.aop = 0;   /* aop.  */
4130         }
4131         | LPAREN TH COMMA R RPAREN
4132         {
4133           $$.r0 = 1;    /* HL.  */
4134           $$.s0 = 1;    /* s.  */
4135           $$.x0 = 0;    /* x.  */
4136           $$.aop = 1;   /* aop.  */
4137         }
4138         | LPAREN RNDL COMMA R RPAREN
4139         {
4140           $$.r0 = 0;    /* HL.  */
4141           $$.s0 = 1;    /* s.  */
4142           $$.x0 = 0;    /* x.  */
4143           $$.aop = 0;   /* aop.  */
4144         }
4145
4146         | LPAREN TL COMMA R RPAREN
4147         {
4148           $$.r0 = 0;    /* HL.  */
4149           $$.s0 = 1;    /* s.  */
4150           $$.x0 = 0;    /* x.  */
4151           $$.aop = 1;   /* aop.  */
4152         }
4153         ;
4154
4155 b3_op:
4156         LPAREN LO RPAREN
4157         {
4158           $$.s0 = 0;    /* s.  */
4159           $$.x0 = 0;    /* HL.  */
4160         }
4161         | LPAREN HI RPAREN
4162         {
4163           $$.s0 = 0;    /* s.  */
4164           $$.x0 = 1;    /* HL.  */
4165         }
4166         | LPAREN LO COMMA R RPAREN
4167         {
4168           $$.s0 = 1;    /* s.  */
4169           $$.x0 = 0;    /* HL.  */
4170         }
4171         | LPAREN HI COMMA R RPAREN
4172         {
4173           $$.s0 = 1;    /* s.  */
4174           $$.x0 = 1;    /* HL.  */
4175         }
4176         ;
4177
4178 post_op:
4179         {
4180         $$.x0 = 2;
4181         }
4182         | _PLUS_PLUS
4183         {
4184         $$.x0 = 0;
4185         }
4186         | _MINUS_MINUS
4187         {
4188         $$.x0 = 1;
4189         }
4190         ;
4191
4192 /* Assignments, Macfuncs.  */
4193
4194 a_assign:
4195         REG_A ASSIGN
4196         {
4197         $$ = $1;
4198         }
4199         ;
4200
4201 a_minusassign:
4202         REG_A _MINUS_ASSIGN
4203         {
4204         $$ = $1;
4205         }
4206         ;
4207
4208 a_plusassign:
4209         REG_A _PLUS_ASSIGN
4210         {
4211         $$ = $1;
4212         }
4213         ;
4214
4215 assign_macfunc:
4216         REG ASSIGN REG_A
4217         {
4218           if (IS_A1 ($3) && IS_EVEN ($1))
4219             return yyerror ("Cannot move A1 to even register");
4220           else if (!IS_A1 ($3) && !IS_EVEN ($1))
4221             return yyerror ("Cannot move A0 to odd register");
4222
4223           $$.w = 1;
4224           $$.P = 1;
4225           $$.n = IS_A1 ($3);
4226           $$.op = 3;
4227           $$.dst = $1;
4228           $$.s0.regno = 0;
4229           $$.s1.regno = 0;
4230         }
4231         | a_macfunc
4232         {
4233           $$ = $1;
4234           $$.w = 0; $$.P = 0;
4235           $$.dst.regno = 0;
4236         }
4237         | REG ASSIGN LPAREN a_macfunc RPAREN
4238         {
4239           if ($4.n && IS_EVEN ($1))
4240             return yyerror ("Cannot move A1 to even register");
4241           else if (!$4.n && !IS_EVEN ($1))
4242             return yyerror ("Cannot move A0 to odd register");
4243
4244           $$ = $4;
4245           $$.w = 1;
4246           $$.P = 1;
4247           $$.dst = $1;
4248         }
4249
4250         | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4251         {
4252           if ($4.n && !IS_H ($1))
4253             return yyerror ("Cannot move A1 to low half of register");
4254           else if (!$4.n && IS_H ($1))
4255             return yyerror ("Cannot move A0 to high half of register");
4256
4257           $$ = $4;
4258           $$.w = 1;
4259           $$.P = 0;
4260           $$.dst = $1;
4261         }
4262
4263         | HALF_REG ASSIGN REG_A
4264         {
4265           if (IS_A1 ($3) && !IS_H ($1))
4266             return yyerror ("Cannot move A1 to low half of register");
4267           else if (!IS_A1 ($3) && IS_H ($1))
4268             return yyerror ("Cannot move A0 to high half of register");
4269
4270           $$.w = 1;
4271           $$.P = 0;
4272           $$.n = IS_A1 ($3);
4273           $$.op = 3;
4274           $$.dst = $1;
4275           $$.s0.regno = 0;
4276           $$.s1.regno = 0;
4277         }
4278         ;
4279
4280 a_macfunc:
4281         a_assign multiply_halfregs
4282         {
4283           $$.n = IS_A1 ($1);
4284           $$.op = 0;
4285           $$.s0 = $2.s0;
4286           $$.s1 = $2.s1;
4287         }
4288         | a_plusassign multiply_halfregs
4289         {
4290           $$.n = IS_A1 ($1);
4291           $$.op = 1;
4292           $$.s0 = $2.s0;
4293           $$.s1 = $2.s1;
4294         }
4295         | a_minusassign multiply_halfregs
4296         {
4297           $$.n = IS_A1 ($1);
4298           $$.op = 2;
4299           $$.s0 = $2.s0;
4300           $$.s1 = $2.s1;
4301         }
4302         ;
4303
4304 multiply_halfregs:
4305         HALF_REG STAR HALF_REG
4306         {
4307           if (IS_DREG ($1) && IS_DREG ($3))
4308             {
4309               $$.s0 = $1;
4310               $$.s1 = $3;
4311             }
4312           else
4313             return yyerror ("Dregs expected");
4314         }
4315         ;
4316
4317 cc_op:
4318         ASSIGN
4319         {
4320         $$.r0 = 0;
4321         }
4322         | _BAR_ASSIGN
4323         {
4324         $$.r0 = 1;
4325         }
4326         | _AMPERSAND_ASSIGN
4327         {
4328         $$.r0 = 2;
4329         }
4330         | _CARET_ASSIGN
4331         {
4332         $$.r0 = 3;
4333         }
4334         ;
4335
4336 ccstat:
4337         CCREG cc_op STATUS_REG
4338         {
4339           $$.r0 = $3.regno;
4340           $$.x0 = $2.r0;
4341           $$.s0 = 0;
4342         }
4343         | CCREG cc_op V
4344         {
4345           $$.r0 = 0x18;
4346           $$.x0 = $2.r0;
4347           $$.s0 = 0;
4348         }
4349         | STATUS_REG cc_op CCREG
4350         {
4351           $$.r0 = $1.regno;
4352           $$.x0 = $2.r0;
4353           $$.s0 = 1;
4354         }
4355         | V cc_op CCREG
4356         {
4357           $$.r0 = 0x18;
4358           $$.x0 = $2.r0;
4359           $$.s0 = 1;
4360         }
4361         ;
4362
4363 /* Expressions and Symbols.  */
4364
4365 symbol: SYMBOL
4366         {
4367         Expr_Node_Value val;
4368         val.s_value = S_GET_NAME($1);
4369         $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4370         }
4371         ;
4372
4373 any_gotrel:
4374         GOT
4375         { $$ = BFD_RELOC_BFIN_GOT; }
4376         | GOT17M4
4377         { $$ = BFD_RELOC_BFIN_GOT17M4; }
4378         | FUNCDESC_GOT17M4
4379         { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4380         ;
4381
4382 got:    symbol AT any_gotrel
4383         {
4384         Expr_Node_Value val;
4385         val.i_value = $3;
4386         $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4387         }
4388         ;
4389
4390 got_or_expr:    got
4391         {
4392         $$ = $1;
4393         }
4394         | expr
4395         {
4396         $$ = $1;
4397         }
4398         ;
4399
4400 pltpc :
4401         symbol AT PLTPC
4402         {
4403         $$ = $1;
4404         }
4405         ;
4406
4407 eterm: NUMBER
4408         {
4409         Expr_Node_Value val;
4410         val.i_value = $1;
4411         $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4412         }
4413         | symbol
4414         {
4415         $$ = $1;
4416         }
4417         | LPAREN expr_1 RPAREN
4418         {
4419         $$ = $2;
4420         }
4421         | TILDA expr_1
4422         {
4423         $$ = unary (Expr_Op_Type_COMP, $2);
4424         }
4425         | MINUS expr_1 %prec TILDA
4426         {
4427         $$ = unary (Expr_Op_Type_NEG, $2);
4428         }
4429         ;
4430
4431 expr: expr_1
4432         {
4433         $$ = $1;
4434         }
4435         ;
4436
4437 expr_1: expr_1 STAR expr_1
4438         {
4439         $$ = binary (Expr_Op_Type_Mult, $1, $3);
4440         }
4441         | expr_1 SLASH expr_1
4442         {
4443         $$ = binary (Expr_Op_Type_Div, $1, $3);
4444         }
4445         | expr_1 PERCENT expr_1
4446         {
4447         $$ = binary (Expr_Op_Type_Mod, $1, $3);
4448         }
4449         | expr_1 PLUS expr_1
4450         {
4451         $$ = binary (Expr_Op_Type_Add, $1, $3);
4452         }
4453         | expr_1 MINUS expr_1
4454         {
4455         $$ = binary (Expr_Op_Type_Sub, $1, $3);
4456         }
4457         | expr_1 LESS_LESS expr_1
4458         {
4459         $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4460         }
4461         | expr_1 GREATER_GREATER expr_1
4462         {
4463         $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4464         }
4465         | expr_1 AMPERSAND expr_1
4466         {
4467         $$ = binary (Expr_Op_Type_BAND, $1, $3);
4468         }
4469         | expr_1 CARET expr_1
4470         {
4471         $$ = binary (Expr_Op_Type_LOR, $1, $3);
4472         }
4473         | expr_1 BAR expr_1
4474         {
4475         $$ = binary (Expr_Op_Type_BOR, $1, $3);
4476         }
4477         | eterm
4478         {
4479         $$ = $1;
4480         }
4481         ;
4482
4483
4484 %%
4485
4486 EXPR_T
4487 mkexpr (int x, SYMBOL_T s)
4488 {
4489   EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4490   e->value = x;
4491   EXPR_SYMBOL(e) = s;
4492   return e;
4493 }
4494
4495 static int
4496 value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
4497 {
4498   int umax = (1 << sz) - 1;
4499   int min = -1 << (sz - 1);
4500   int max = (1 << (sz - 1)) - 1;
4501
4502   int v = (EXPR_VALUE (exp)) & 0xffffffff;
4503
4504   if ((v % mul) != 0)
4505     {
4506       error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4507       return 0;
4508     }
4509
4510   v /= mul;
4511
4512   if (sign)
4513     v = -v;
4514
4515   if (issigned)
4516     {
4517       if (v >= min && v <= max) return 1;
4518
4519 #ifdef DEBUG
4520       fprintf(stderr, "signed value %lx out of range\n", v * mul);
4521 #endif
4522       return 0;
4523     }
4524   if (v <= umax && v >= 0)
4525     return 1;
4526 #ifdef DEBUG
4527   fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4528 #endif
4529   return 0;
4530 }
4531
4532 /* Return the expression structure that allows symbol operations.
4533    If the left and right children are constants, do the operation.  */
4534 static Expr_Node *
4535 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4536 {
4537   Expr_Node_Value val;
4538
4539   if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4540     {
4541       switch (op)
4542         {
4543         case Expr_Op_Type_Add:
4544           x->value.i_value += y->value.i_value;
4545           break;
4546         case Expr_Op_Type_Sub:
4547           x->value.i_value -= y->value.i_value;
4548           break;
4549         case Expr_Op_Type_Mult:
4550           x->value.i_value *= y->value.i_value;
4551           break;
4552         case Expr_Op_Type_Div:
4553           if (y->value.i_value == 0)
4554             error ("Illegal Expression:  Division by zero.");
4555           else
4556             x->value.i_value /= y->value.i_value;
4557           break;
4558         case Expr_Op_Type_Mod:
4559           x->value.i_value %= y->value.i_value;
4560           break;
4561         case Expr_Op_Type_Lshift:
4562           x->value.i_value <<= y->value.i_value;
4563           break;
4564         case Expr_Op_Type_Rshift:
4565           x->value.i_value >>= y->value.i_value;
4566           break;
4567         case Expr_Op_Type_BAND:
4568           x->value.i_value &= y->value.i_value;
4569           break;
4570         case Expr_Op_Type_BOR:
4571           x->value.i_value |= y->value.i_value;
4572           break;
4573         case Expr_Op_Type_BXOR:
4574           x->value.i_value ^= y->value.i_value;
4575           break;
4576         case Expr_Op_Type_LAND:
4577           x->value.i_value = x->value.i_value && y->value.i_value;
4578           break;
4579         case Expr_Op_Type_LOR:
4580           x->value.i_value = x->value.i_value || y->value.i_value;
4581           break;
4582
4583         default:
4584           error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4585         }
4586       return x;
4587     }
4588   /* Canonicalize order to EXPR OP CONSTANT.  */
4589   if (x->type == Expr_Node_Constant)
4590     {
4591       Expr_Node *t = x;
4592       x = y;
4593       y = t;
4594     }
4595   /* Canonicalize subtraction of const to addition of negated const.  */
4596   if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4597     {
4598       op = Expr_Op_Type_Add;
4599       y->value.i_value = -y->value.i_value;
4600     }
4601   if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4602       && x->Right_Child->type == Expr_Node_Constant)
4603     {
4604       if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4605         {
4606           x->Right_Child->value.i_value += y->value.i_value;
4607           return x;
4608         }
4609     }
4610
4611   /* Create a new expression structure.  */
4612   val.op_value = op;
4613   return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4614 }
4615
4616 static Expr_Node *
4617 unary (Expr_Op_Type op, Expr_Node *x)
4618 {
4619   if (x->type == Expr_Node_Constant)
4620     {
4621       switch (op)
4622         {
4623         case Expr_Op_Type_NEG:
4624           x->value.i_value = -x->value.i_value;
4625           break;
4626         case Expr_Op_Type_COMP:
4627           x->value.i_value = ~x->value.i_value;
4628           break;
4629         default:
4630           error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4631         }
4632       return x;
4633     }
4634   else
4635     {
4636       /* Create a new expression structure.  */
4637       Expr_Node_Value val;
4638       val.op_value = op;
4639       return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4640     }
4641 }
4642
4643 int debug_codeselection = 0;
4644 static void
4645 notethat (char *format, ...)
4646 {
4647   va_list ap;
4648   va_start (ap, format);
4649   if (debug_codeselection)
4650     {
4651       vfprintf (errorf, format, ap);
4652     }
4653   va_end (ap);
4654 }
4655
4656 #ifdef TEST
4657 main (int argc, char **argv)
4658 {
4659   yyparse();
4660 }
4661 #endif
4662