sim: Clock timings fixed
[avr-sim.git] / devices / at89s52
blob0a3bd99a1fb2465c4d53f295366057d4adc4bf71
1 <?xml version="1.0"?>
2 <!DOCTYPE device SYSTEM "device.dtd">
3 <device>
4 <memory>
5 <flash size="8192"/>
6 <iospace start="" stop=""/>
7 <sram size=""/>
8 <eram size=""/>
9 </memory>
10 <ioregisters>
11 <ioreg name="PINA" address="0x16"/>
12 <ioreg name="DDRA" address="0x17"/>
13 <ioreg name="PORTA" address="0x18"/>
14 </ioregisters>
15 <hardware>
16 <!--Everything after this needs editing!!!-->
17 <module class="LOCKBIT">
18 <registers name="LOCKBIT" memspace="LOCKBIT">
19 <reg size="1" name="LOCKBIT" offset="0x00">
20 <bitfield name="LB" mask="0x1C" text="Memory Lock" icon="" enum="ENUM_LB"/>
21 </reg>
22 </registers>
23 </module>
24 <module class="PORTA">
25 <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
26 <reg size="1" name="PORTA" offset="0x38" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
27 <reg size="1" name="DDRA" offset="0x37" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
28 <reg size="1" name="PINA" offset="0x36" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
29 </registers>
30 </module>
31 </hardware>
32 </device>