16 * @brief Manages hardware and interrupts
18 * The bus contains the list of all hardware and serves as
19 * a clock for the hardware (working on CPU ticks).
20 * Hardware can register callbacks within a number of ticks.
22 * It also encapsulates the functionality related to
23 * handling the state of interrupts.
25 class Bus
: public sim::Clock
<Hardware
> {
32 * Reset the bus and all hardware on it.
37 * Adds a bit of hardware to the bus
39 void addHardware(Hardware
*hw
);
42 * Check whether the hardware is holding the CPU.
43 * \warning call this only once per CPU tick!
48 static const unsigned int intVectorsSize
= 28;
51 * Post the interrupt with vector \e vector
53 void raiseInterrupt(unsigned int vector
);
56 * Unpost the interrupt with vector \e vector
58 void clearInterrupt(unsigned int vector
);
62 * Returns the pending interrupt with highest priority.
64 unsigned int pendingInterrupt() const;
67 * Checks whether an interrupt is pending.
69 bool isInterruptPending() const;
72 * Returns the memory address associated with the vector.
74 unsigned int interruptVectorAddress(unsigned int vector
) const;
77 * Notifies the hardware associated with this interrupt
78 * that the handler is about to be invoked.
80 void beforeInvokeInterrupt(unsigned int vector
);
84 * Add an interrupt vector.
86 void addInterrupt(unsigned int vector
, unsigned int address
,
90 * Hardware can claim an interrupt, this means that it is
91 * responsible for raising an interrupt. It will from then
92 * on be notified before an interrupt vector is executed.
94 void claimInterrupt(unsigned int vector
, Hardware
*hw
);
97 std::list
<Hardware
*> hardware
;
102 IntVect(unsigned int addr
, const std::string
& name
)
103 : address(addr
), name(name
), hw(0) {}
104 unsigned int address
;
108 typedef std::vector
< IntVect
> InterruptTable
;
111 InterruptTable intVectors
;
112 unsigned int irqPending
;
115 inline void Bus::addHardware(Hardware
*hw
) {
116 hardware
.push_back( hw
);
119 inline void Bus::raiseInterrupt(unsigned int vector
) {
120 irqPending
|= (1<<vector
);
123 inline void Bus::clearInterrupt(unsigned int vector
) {
124 irqPending
&= ~(1<<vector
);
127 inline bool Bus::isInterruptPending() const {
128 return irqPending
!= 0;
131 inline unsigned int Bus::pendingInterrupt() const {
133 for(vector
= 0; vector
< Bus::intVectorsSize
; ++vector
)
134 if( (irqPending
& (1<<vector
)) != 0 )
140 inline unsigned int Bus::interruptVectorAddress(unsigned int vector
) const {
141 return intVectors
[vector
].address
;