| blob | 7ee0d50bbf7e3f4ab5fdb57657aeb0e1dffb70c9 |
1 diff --git a/NEWS b/NEWS
2 index ea92bcf..61866b0 100644
3 --- a/NEWS
4 +++ b/NEWS
5 @@ -2,9 +2,9 @@ Release 2.15.0 (2011-04-14)
6 ==============================
7 We are pleased to announce this major release of the xf86-video-intel
8 driver, roughly on schedule at 3 months since 2.14.0. With the many bug
9 -fixes in this release, we encourage everyone to upgrade to 2.14.
10 +fixes in this release, we encourage everyone to upgrade to 2.15.
12 -The priority for this quarter has been simply to unexciting and stabilise
13 +The priority for this quarter has been simply to be unexciting and stabilise
14 the driver further, seeking to capitalise upon the improvements elsewhere
15 in the stack.
17 diff --git a/configure.ac b/configure.ac
18 index fd5a3cf..9449e56 100644
19 --- a/configure.ac
20 +++ b/configure.ac
21 @@ -77,9 +77,7 @@ AC_ARG_WITH(xorg-module-dir,
22 [moduledir="$libdir/xorg/modules"])
24 AC_ARG_ENABLE(dri, AS_HELP_STRING([--disable-dri],
25 - [Disable DRI support [[default=auto]]]),
26 - [DRI="$enableval"],
27 - [DRI=auto])
28 + [Disable DRI support [[default=auto]]]))
30 AC_ARG_ENABLE(xvmc, AS_HELP_STRING([--disable-xvmc],
31 [Disable XvMC support [[default=yes]]]),
32 @@ -106,40 +104,48 @@ XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
33 # Obtain compiler/linker options for the driver dependencies
34 PKG_CHECK_MODULES(XORG, [xorg-server >= 1.6 xproto fontsproto $REQUIRED_MODULES])
35 PKG_CHECK_MODULES(DRM, [libdrm >= 2.4.23])
36 +PKG_CHECK_MODULES(DRI, [xf86driproto], , DRI=no)
37 PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
39 sdkdir=`$PKG_CONFIG --variable=sdkdir xorg-server`
41 -save_CFLAGS="$CFLAGS"
42 -CFLAGS="$XORG_CFLAGS $DRI_CFLAGS $DRM_CFLAGS"
43 -CPPFLAGS="$XORG_CFLAGS $DRI_CFLAGS $DRM_CFLAGS"
44 -AC_MSG_CHECKING([whether to include DRI support])
45 -if test x$DRI != xno; then
46 - AC_CHECK_FILE([${sdkdir}/dri.h],
47 - [have_dri_h="yes"], [have_dri_h="no"])
48 - AC_CHECK_FILE([${sdkdir}/sarea.h],
49 - [have_sarea_h="yes"], [have_sarea_h="no"])
50 - AC_CHECK_FILE([${sdkdir}/dristruct.h],
51 - [have_dristruct_h="yes"], [have_dristruct_h="no"])
52 +if test "x$enable_dri" != "xno"; then
53 + save_CFLAGS="$CFLAGS"
54 + save_CPPFLAGS="$CPPFLAGS"
55 + CFLAGS="$XORG_CFLAGS $DRI_CFLAGS $DRM_CFLAGS"
56 + CPPFLAGS="$XORG_CFLAGS $DRI_CFLAGS $DRM_CFLAGS"
57 + AC_CHECK_HEADERS([dri.h sarea.h dristruct.h],, [DRI=no],
58 + [/* for dri.h */
59 + #include <xf86str.h>
60 + /* for dristruct.h */
61 + #include <xorg-server.h>
62 + #ifdef HAVE_DRI_H
63 + # include <dri.h>
64 + #endif
65 + #ifdef HAVE_SAREA_H
66 + # include <sarea.h>
67 + #endif
68 + ])
69 + CFLAGS="$save_CFLAGS $DEBUGFLAGS"
70 + CPPFLAGS="$save_CPPFLAGS"
71 +else
72 + DRI=no
73 fi
74 +
75 AC_MSG_CHECKING([whether to include DRI support])
76 -if test x$DRI = xauto; then
77 - if test "$have_dri_h" = yes -a \
78 - "$have_sarea_h" = yes -a \
79 - "$have_dristruct_h" = yes; then
80 - DRI="yes"
81 - else
82 - DRI="no"
83 - fi
84 -fi
85 -AC_MSG_RESULT([$DRI])
86 -CFLAGS="$save_CFLAGS $DEBUGFLAGS"
87 +AC_MSG_RESULT([${DRI-yes}])
89 -AM_CONDITIONAL(DRI, test x$DRI = xyes)
90 -if test "$DRI" = yes; then
91 - PKG_CHECK_MODULES(DRI, [xf86driproto])
92 +AM_CONDITIONAL(DRI, test x$DRI != xno)
93 +if test "x$DRI" != "xno"; then
94 AC_DEFINE(XF86DRI,1,[Enable DRI driver support])
95 AC_DEFINE(XF86DRI_DEVEL,1,[Enable developmental DRI driver support])
96 +else
97 + DRI_CFLAGS=""
98 + DRI_LIBS=""
99 +
100 + if test "x$enable_dri" = "xyes"; then
101 + AC_MSG_ERROR([DRI requested but prerequisites not found])
102 + fi
103 fi
105 if test "$XVMC" = yes; then
106 diff --git a/src/i965_render.c b/src/i965_render.c
107 index bfcd3f2..b76107d 100644
108 --- a/src/i965_render.c
109 +++ b/src/i965_render.c
110 @@ -182,6 +182,10 @@ i965_check_composite(int op,
111 int width, int height)
112 {
113 ScrnInfoPtr scrn = xf86Screens[dest_picture->pDrawable->pScreen->myNum];
114 + intel_screen_private *intel = intel_get_screen_private(scrn);
115 +
116 + if (IS_GEN7(intel))
117 + return FALSE;
119 /* Check for unsupported compositing operations. */
120 if (op >= sizeof(i965_blend_op) / sizeof(i965_blend_op[0])) {
121 diff --git a/src/i965_video.c b/src/i965_video.c
122 index c757681..53a9394 100644
123 --- a/src/i965_video.c
124 +++ b/src/i965_video.c
125 @@ -1210,7 +1210,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
126 intel_batch_submit(scrn);
127 }
129 - intel_batch_start_atomic(scrn, 100);
130 + intel_batch_start_atomic(scrn, 150);
132 i965_emit_video_setup(scrn, surface_state_binding_table_bo, n_src_surf, pixmap);
134 diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c
135 index 289ed2b..d0a41aa 100644
136 --- a/src/intel_batchbuffer.c
137 +++ b/src/intel_batchbuffer.c
138 @@ -175,13 +175,6 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn)
139 intel_batch_do_flush(scrn);
140 }
142 -static Bool intel_batch_needs_flush(intel_screen_private *intel)
143 -{
144 - ScreenPtr screen = intel->scrn->pScreen;
145 - PixmapPtr pixmap = screen->GetScreenPixmap(screen);
146 - return intel_get_pixmap_private(pixmap)->batch_write;
147 -}
148 -
149 void intel_batch_submit(ScrnInfoPtr scrn)
150 {
151 intel_screen_private *intel = intel_get_screen_private(scrn);
152 @@ -218,7 +211,9 @@ void intel_batch_submit(ScrnInfoPtr scrn)
153 ret = drm_intel_bo_mrb_exec(intel->batch_bo,
154 intel->batch_used*4,
155 NULL, 0, 0xffffffff,
156 - IS_GEN6(intel) ? intel->current_batch: I915_EXEC_DEFAULT);
157 + (HAS_BLT(intel) ?
158 + intel->current_batch:
159 + I915_EXEC_DEFAULT));
160 }
162 if (ret != 0) {
163 @@ -241,8 +236,6 @@ void intel_batch_submit(ScrnInfoPtr scrn)
164 }
165 }
167 - intel->needs_flush |= intel_batch_needs_flush(intel);
168 -
169 while (!list_is_empty(&intel->batch_pixmaps)) {
170 struct intel_pixmap *entry;
172 diff --git a/src/intel_batchbuffer.h b/src/intel_batchbuffer.h
173 index 605932a..f5f118e 100644
174 --- a/src/intel_batchbuffer.h
175 +++ b/src/intel_batchbuffer.h
176 @@ -50,14 +50,14 @@ static inline int intel_vertex_space(intel_screen_private *intel)
177 }
179 static inline void
180 -intel_batch_require_space(ScrnInfoPtr scrn, intel_screen_private *intel, unsigned int sz)
181 +intel_batch_require_space(ScrnInfoPtr scrn, intel_screen_private *intel, int sz)
182 {
183 assert(sz < intel->batch_bo->size - 8);
184 if (intel_batch_space(intel) < sz)
185 intel_batch_submit(scrn);
186 }
188 -static inline void intel_batch_start_atomic(ScrnInfoPtr scrn, unsigned int sz)
189 +static inline void intel_batch_start_atomic(ScrnInfoPtr scrn, int sz)
190 {
191 intel_screen_private *intel = intel_get_screen_private(scrn);
193 @@ -137,6 +137,8 @@ intel_batch_mark_pixmap_domains(intel_screen_private *intel,
195 priv->batch_write |= write_domain != 0;
196 priv->busy = 1;
197 +
198 + intel->needs_flush |= write_domain != 0;
199 }
201 static inline void
202 diff --git a/src/intel_display.c b/src/intel_display.c
203 index b6592c4..b55b110 100644
204 --- a/src/intel_display.c
205 +++ b/src/intel_display.c
206 @@ -1607,7 +1607,7 @@ Bool intel_mode_pre_init(ScrnInfoPtr scrn, int fd, int cpp)
207 gp.value = &has_flipping;
208 (void)drmCommandWriteRead(intel->drmSubFD, DRM_I915_GETPARAM, &gp,
209 sizeof(gp));
210 - if (has_flipping) {
211 + if (has_flipping && intel->swapbuffers_wait) {
212 xf86DrvMsg(scrn->scrnIndex, X_INFO,
213 "Kernel page flipping support detected, enabling\n");
214 intel->use_pageflipping = TRUE;
215 diff --git a/src/intel_dri.c b/src/intel_dri.c
216 index a39b512..48d0f56 100644
217 --- a/src/intel_dri.c
218 +++ b/src/intel_dri.c
219 @@ -182,6 +182,8 @@ static PixmapPtr fixup_shadow(DrawablePtr drawable, PixmapPtr pixmap)
220 /* And redirect the pixmap to the new bo (for 3D). */
221 intel_set_pixmap_private(old, priv);
222 old->refcnt++;
223 +
224 + intel_get_screen_private(xf86Screens[screen->myNum])->needs_flush = TRUE;
225 return old;
226 }
228 @@ -425,7 +427,7 @@ I830DRI2CopyRegion(DrawablePtr drawable, RegionPtr pRegion,
230 /* Wait for the scanline to be outside the region to be copied */
231 if (pixmap_is_scanout(get_drawable_pixmap(dst)) &&
232 - intel->swapbuffers_wait) {
233 + intel->swapbuffers_wait && INTEL_INFO(intel)->gen < 60) {
234 BoxPtr box;
235 BoxRec crtcbox;
236 int y1, y2;
237 diff --git a/src/intel_driver.c b/src/intel_driver.c
238 index e867351..8666421 100644
239 --- a/src/intel_driver.c
240 +++ b/src/intel_driver.c
241 @@ -84,7 +84,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
242 */
244 typedef enum {
245 - OPTION_ACCELMETHOD,
246 OPTION_DRI,
247 OPTION_VIDEO_KEY,
248 OPTION_COLOR_KEY,
249 @@ -105,7 +104,6 @@ typedef enum {
250 } I830Opts;
252 static OptionInfoRec I830Options[] = {
253 - {OPTION_ACCELMETHOD, "AccelMethod", OPTV_ANYSTR, {0}, FALSE},
254 {OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, TRUE},
255 {OPTION_COLOR_KEY, "ColorKey", OPTV_INTEGER, {0}, FALSE},
256 {OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE},
257 @@ -328,10 +326,10 @@ static void intel_check_dri_option(ScrnInfoPtr scrn)
258 if (!xf86ReturnOptValBool(intel->Options, OPTION_DRI, TRUE))
259 intel->directRenderingType = DRI_DISABLED;
261 - if (scrn->depth != 16 && scrn->depth != 24) {
262 + if (scrn->depth != 16 && scrn->depth != 24 && scrn->depth != 30) {
263 xf86DrvMsg(scrn->scrnIndex, X_CONFIG,
264 "DRI is disabled because it "
265 - "runs only at depths 16 and 24.\n");
266 + "runs only at depths 16, 24, and 30.\n");
267 intel->directRenderingType = DRI_DISABLED;
268 }
269 }
270 @@ -586,6 +584,7 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags)
271 case 15:
272 case 16:
273 case 24:
274 + case 30:
275 break;
276 default:
277 xf86DrvMsg(scrn->scrnIndex, X_ERROR,
278 @@ -658,8 +657,6 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags)
279 intel->swapbuffers_wait = xf86ReturnOptValBool(intel->Options,
280 OPTION_SWAPBUFFERS_WAIT,
281 TRUE);
282 - if (IS_GEN6(intel))
283 - intel->swapbuffers_wait = FALSE;
285 xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "Framebuffer %s\n",
286 intel->tiling & INTEL_TILING_FB ? "tiled" : "linear");
287 diff --git a/src/intel_driver.h b/src/intel_driver.h
288 index 2e72177..4a584fe 100644
289 --- a/src/intel_driver.h
290 +++ b/src/intel_driver.h
291 @@ -184,6 +184,13 @@
292 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
293 #define PCI_CHIP_SANDYBRIDGE_BRIDGE_S 0x0108 /* Server */
294 #define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A
295 +
296 +#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156
297 +#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
298 +#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152
299 +#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162
300 +#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
301 +
302 #endif
304 #define I85X_CAPID 0x44
305 @@ -209,6 +216,7 @@
306 #define IS_GEN4(intel) IS_GENx(intel, 4)
307 #define IS_GEN5(intel) IS_GENx(intel, 5)
308 #define IS_GEN6(intel) IS_GENx(intel, 6)
309 +#define IS_GEN7(intel) IS_GENx(intel, 7)
311 /* Some chips have specific errata (or limits) that we need to workaround. */
312 #define IS_I830(intel) (DEVICE_ID((intel)->PciInfo) == PCI_CHIP_I830_M)
313 @@ -222,6 +230,7 @@
315 /* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
316 #define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 40)
317 +#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 60)
319 extern SymTabRec *intel_chipsets;
321 diff --git a/src/intel_module.c b/src/intel_module.c
322 index 8416544..9468e72 100644
323 --- a/src/intel_module.c
324 +++ b/src/intel_module.c
325 @@ -39,6 +39,8 @@
327 #include <xf86drmMode.h>
329 +static struct intel_device_info *chipset_info;
330 +
331 static const struct intel_device_info intel_i81x_info = {
332 .gen = 10,
333 };
334 @@ -71,329 +73,148 @@ static const struct intel_device_info intel_sandybridge_info = {
335 .gen = 60,
336 };
338 +static const struct intel_device_info intel_ivybridge_info = {
339 + .gen = 70,
340 +};
341 +
342 static const SymTabRec _intel_chipsets[] = {
343 - {PCI_CHIP_I810, "i810"},
344 - {PCI_CHIP_I810_DC100, "i810-dc100"},
345 - {PCI_CHIP_I810_E, "i810e"},
346 - {PCI_CHIP_I815, "i815"},
347 - {PCI_CHIP_I830_M, "i830M"},
348 - {PCI_CHIP_845_G, "845G"},
349 - {PCI_CHIP_I854, "854"},
350 - {PCI_CHIP_I855_GM, "852GM/855GM"},
351 - {PCI_CHIP_I865_G, "865G"},
352 - {PCI_CHIP_I915_G, "915G"},
353 - {PCI_CHIP_E7221_G, "E7221 (i915)"},
354 - {PCI_CHIP_I915_GM, "915GM"},
355 - {PCI_CHIP_I945_G, "945G"},
356 - {PCI_CHIP_I945_GM, "945GM"},
357 - {PCI_CHIP_I945_GME, "945GME"},
358 - {PCI_CHIP_PINEVIEW_M, "Pineview GM"},
359 - {PCI_CHIP_PINEVIEW_G, "Pineview G"},
360 - {PCI_CHIP_I965_G, "965G"},
361 - {PCI_CHIP_G35_G, "G35"},
362 - {PCI_CHIP_I965_Q, "965Q"},
363 - {PCI_CHIP_I946_GZ, "946GZ"},
364 - {PCI_CHIP_I965_GM, "965GM"},
365 - {PCI_CHIP_I965_GME, "965GME/GLE"},
366 - {PCI_CHIP_G33_G, "G33"},
367 - {PCI_CHIP_Q35_G, "Q35"},
368 - {PCI_CHIP_Q33_G, "Q33"},
369 - {PCI_CHIP_GM45_GM, "GM45"},
370 - {PCI_CHIP_G45_E_G, "4 Series"},
371 - {PCI_CHIP_G45_G, "G45/G43"},
372 - {PCI_CHIP_Q45_G, "Q45/Q43"},
373 - {PCI_CHIP_G41_G, "G41"},
374 - {PCI_CHIP_B43_G, "B43"},
375 - {PCI_CHIP_B43_G1, "B43"},
376 - {PCI_CHIP_IRONLAKE_D_G, "Clarkdale"},
377 - {PCI_CHIP_IRONLAKE_M_G, "Arrandale"},
378 - {PCI_CHIP_SANDYBRIDGE_GT1, "Sandybridge" },
379 - {PCI_CHIP_SANDYBRIDGE_GT2, "Sandybridge" },
380 - {PCI_CHIP_SANDYBRIDGE_GT2_PLUS, "Sandybridge" },
381 - {PCI_CHIP_SANDYBRIDGE_M_GT1, "Sandybridge" },
382 - {PCI_CHIP_SANDYBRIDGE_M_GT2, "Sandybridge" },
383 - {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, "Sandybridge" },
384 - {PCI_CHIP_SANDYBRIDGE_S_GT, "Sandybridge" },
385 - {-1, NULL}
386 + {PCI_CHIP_I810, "i810"},
387 + {PCI_CHIP_I810_DC100, "i810-dc100"},
388 + {PCI_CHIP_I810_E, "i810e"},
389 + {PCI_CHIP_I815, "i815"},
390 + {PCI_CHIP_I830_M, "i830M"},
391 + {PCI_CHIP_845_G, "845G"},
392 + {PCI_CHIP_I854, "854"},
393 + {PCI_CHIP_I855_GM, "852GM/855GM"},
394 + {PCI_CHIP_I865_G, "865G"},
395 + {PCI_CHIP_I915_G, "915G"},
396 + {PCI_CHIP_E7221_G, "E7221 (i915)"},
397 + {PCI_CHIP_I915_GM, "915GM"},
398 + {PCI_CHIP_I945_G, "945G"},
399 + {PCI_CHIP_I945_GM, "945GM"},
400 + {PCI_CHIP_I945_GME, "945GME"},
401 + {PCI_CHIP_PINEVIEW_M, "Pineview GM"},
402 + {PCI_CHIP_PINEVIEW_G, "Pineview G"},
403 + {PCI_CHIP_I965_G, "965G"},
404 + {PCI_CHIP_G35_G, "G35"},
405 + {PCI_CHIP_I965_Q, "965Q"},
406 + {PCI_CHIP_I946_GZ, "946GZ"},
407 + {PCI_CHIP_I965_GM, "965GM"},
408 + {PCI_CHIP_I965_GME, "965GME/GLE"},
409 + {PCI_CHIP_G33_G, "G33"},
410 + {PCI_CHIP_Q35_G, "Q35"},
411 + {PCI_CHIP_Q33_G, "Q33"},
412 + {PCI_CHIP_GM45_GM, "GM45"},
413 + {PCI_CHIP_G45_E_G, "4 Series"},
414 + {PCI_CHIP_G45_G, "G45/G43"},
415 + {PCI_CHIP_Q45_G, "Q45/Q43"},
416 + {PCI_CHIP_G41_G, "G41"},
417 + {PCI_CHIP_B43_G, "B43"},
418 + {PCI_CHIP_B43_G1, "B43"},
419 + {PCI_CHIP_IRONLAKE_D_G, "Clarkdale"},
420 + {PCI_CHIP_IRONLAKE_M_G, "Arrandale"},
421 + {PCI_CHIP_SANDYBRIDGE_GT1, "Sandybridge Desktop (GT1)" },
422 + {PCI_CHIP_SANDYBRIDGE_GT2, "Sandybridge Desktop (GT2)" },
423 + {PCI_CHIP_SANDYBRIDGE_GT2_PLUS, "Sandybridge Desktop (GT2+)" },
424 + {PCI_CHIP_SANDYBRIDGE_M_GT1, "Sandybridge Mobile (GT1)" },
425 + {PCI_CHIP_SANDYBRIDGE_M_GT2, "Sandybridge Mobile (GT2)" },
426 + {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, "Sandybridge Mobile (GT2+)" },
427 + {PCI_CHIP_SANDYBRIDGE_S_GT, "Sandybridge Server" },
428 + {PCI_CHIP_IVYBRIDGE_M_GT1, "Ivybridge Mobile (GT1)" },
429 + {PCI_CHIP_IVYBRIDGE_M_GT2, "Ivybridge Mobile (GT2)" },
430 + {PCI_CHIP_IVYBRIDGE_D_GT1, "Ivybridge Desktop (GT1)" },
431 + {PCI_CHIP_IVYBRIDGE_D_GT2, "Ivybridge Desktop (GT2)" },
432 + {PCI_CHIP_IVYBRIDGE_S_GT1, "Ivybridge Server" },
433 + {-1, NULL}
434 };
435 SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
437 #define INTEL_DEVICE_MATCH(d,i) \
438 -{ 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) }
439 + { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (intptr_t)(i) }
441 static const struct pci_id_match intel_device_match[] = {
442 - INTEL_DEVICE_MATCH (PCI_CHIP_I810, 0 ),
443 - INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, 0 ),
444 - INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, 0 ),
445 - INTEL_DEVICE_MATCH (PCI_CHIP_I815, 0 ),
446 - INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, 0 ),
447 - INTEL_DEVICE_MATCH (PCI_CHIP_845_G, 0 ),
448 - INTEL_DEVICE_MATCH (PCI_CHIP_I854, 0 ),
449 - INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, 0 ),
450 - INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, 0 ),
451 - INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, 0 ),
452 - INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, 0 ),
453 - INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, 0 ),
454 - INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ),
455 - INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
456 - INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
457 - INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, 0 ),
458 - INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, 0 ),
459 - INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
460 - INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
461 - INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
462 - INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ),
463 - INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ),
464 - INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, 0 ),
465 - INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
466 - INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
467 - INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
468 - INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ),
469 - INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, 0 ),
470 - INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
471 - INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
472 - INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ),
473 - INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ),
474 - INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, 0 ),
475 - INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, 0 ),
476 - INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, 0 ),
477 - INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, 0 ),
478 - INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, 0 ),
479 - INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, 0 ),
480 - INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, 0 ),
481 - INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, 0 ),
482 - INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, 0 ),
483 - { 0, 0, 0 },
484 -};
485 -
486 -static PciChipsets intel_pci_chipsets[] = {
487 - {PCI_CHIP_I810, PCI_CHIP_I810, NULL},
488 - {PCI_CHIP_I810_DC100, PCI_CHIP_I810_DC100, NULL},
489 - {PCI_CHIP_I810_E, PCI_CHIP_I810_E, NULL},
490 - {PCI_CHIP_I815, PCI_CHIP_I815, NULL},
491 - {PCI_CHIP_I830_M, PCI_CHIP_I830_M, NULL},
492 - {PCI_CHIP_845_G, PCI_CHIP_845_G, NULL},
493 - {PCI_CHIP_I854, PCI_CHIP_I854, NULL},
494 - {PCI_CHIP_I855_GM, PCI_CHIP_I855_GM, NULL},
495 - {PCI_CHIP_I865_G, PCI_CHIP_I865_G, NULL},
496 - {PCI_CHIP_I915_G, PCI_CHIP_I915_G, NULL},
497 - {PCI_CHIP_E7221_G, PCI_CHIP_E7221_G, NULL},
498 - {PCI_CHIP_I915_GM, PCI_CHIP_I915_GM, NULL},
499 - {PCI_CHIP_I945_G, PCI_CHIP_I945_G, NULL},
500 - {PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, NULL},
501 - {PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, NULL},
502 - {PCI_CHIP_PINEVIEW_M, PCI_CHIP_PINEVIEW_M, NULL},
503 - {PCI_CHIP_PINEVIEW_G, PCI_CHIP_PINEVIEW_G, NULL},
504 - {PCI_CHIP_I965_G, PCI_CHIP_I965_G, NULL},
505 - {PCI_CHIP_G35_G, PCI_CHIP_G35_G, NULL},
506 - {PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, NULL},
507 - {PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, NULL},
508 - {PCI_CHIP_I965_GM, PCI_CHIP_I965_GM, NULL},
509 - {PCI_CHIP_I965_GME, PCI_CHIP_I965_GME, NULL},
510 - {PCI_CHIP_G33_G, PCI_CHIP_G33_G, NULL},
511 - {PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, NULL},
512 - {PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, NULL},
513 - {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, NULL},
514 - {PCI_CHIP_G45_E_G, PCI_CHIP_G45_E_G, NULL},
515 - {PCI_CHIP_G45_G, PCI_CHIP_G45_G, NULL},
516 - {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, NULL},
517 - {PCI_CHIP_G41_G, PCI_CHIP_G41_G, NULL},
518 - {PCI_CHIP_B43_G, PCI_CHIP_B43_G, NULL},
519 - {PCI_CHIP_IRONLAKE_D_G, PCI_CHIP_IRONLAKE_D_G, NULL},
520 - {PCI_CHIP_IRONLAKE_M_G, PCI_CHIP_IRONLAKE_M_G, NULL},
521 - {PCI_CHIP_SANDYBRIDGE_GT1, PCI_CHIP_SANDYBRIDGE_GT1, NULL},
522 - {PCI_CHIP_SANDYBRIDGE_GT2, PCI_CHIP_SANDYBRIDGE_GT2, NULL},
523 - {PCI_CHIP_SANDYBRIDGE_GT2_PLUS, PCI_CHIP_SANDYBRIDGE_GT2_PLUS, NULL},
524 - {PCI_CHIP_SANDYBRIDGE_M_GT1, PCI_CHIP_SANDYBRIDGE_M_GT1, NULL},
525 - {PCI_CHIP_SANDYBRIDGE_M_GT2, PCI_CHIP_SANDYBRIDGE_M_GT2, NULL},
526 - {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, NULL},
527 - {PCI_CHIP_SANDYBRIDGE_S_GT, PCI_CHIP_SANDYBRIDGE_S_GT, NULL},
528 - {-1, -1, NULL }
529 + INTEL_DEVICE_MATCH (PCI_CHIP_I810, &intel_i81x_info ),
530 + INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, &intel_i81x_info ),
531 + INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, &intel_i81x_info ),
532 + INTEL_DEVICE_MATCH (PCI_CHIP_I815, &intel_i81x_info ),
533 +
534 + INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, &intel_i8xx_info ),
535 + INTEL_DEVICE_MATCH (PCI_CHIP_845_G, &intel_i8xx_info ),
536 + INTEL_DEVICE_MATCH (PCI_CHIP_I854, &intel_i8xx_info ),
537 + INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, &intel_i8xx_info ),
538 + INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, &intel_i8xx_info ),
539 +
540 + INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ),
541 + INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ),
542 + INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ),
543 + INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i915_info ),
544 + INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i915_info ),
545 + INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i915_info ),
546 +
547 + INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ),
548 + INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ),
549 + INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ),
550 + INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ),
551 + /* Another marketing win: Q35 is another g33 device not a gen4 part
552 + * like its G35 brethren.
553 + */
554 + INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ),
555 +
556 + INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ),
557 + INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ),
558 + INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ),
559 + INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ),
560 + INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ),
561 + INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ),
562 +
563 + INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ),
564 + INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ),
565 + INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ),
566 + INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ),
567 + INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ),
568 + INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ),
569 + INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ),
570 +
571 + INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ),
572 + INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ),
573 +
574 + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ),
575 + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ),
576 + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ),
577 + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ),
578 + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ),
579 + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ),
580 + INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ),
581 +
582 + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ),
583 + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ),
584 + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ),
585 + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ),
586 + INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
587 +
588 + { 0, 0, 0 },
589 };
591 void intel_detect_chipset(ScrnInfoPtr scrn,
592 struct pci_device *pci,
593 struct intel_chipset *chipset)
594 {
595 - uint32_t capid;
596 -
597 - switch (DEVICE_ID(pci)) {
598 - case PCI_CHIP_I810:
599 - chipset->name = "i810";
600 - chipset->info = &intel_i81x_info;
601 - break;
602 - case PCI_CHIP_I810_DC100:
603 - chipset->name = "i810-dc100";
604 - chipset->info = &intel_i81x_info;
605 - break;
606 - case PCI_CHIP_I810_E:
607 - chipset->name = "i810e";
608 - chipset->info = &intel_i81x_info;
609 - break;
610 - case PCI_CHIP_I815:
611 - chipset->name = "i815";
612 - chipset->info = &intel_i81x_info;
613 - break;
614 - case PCI_CHIP_I830_M:
615 - chipset->name = "830M";
616 - chipset->info = &intel_i8xx_info;
617 - break;
618 - case PCI_CHIP_845_G:
619 - chipset->name = "845G";
620 - chipset->info = &intel_i8xx_info;
621 - break;
622 - case PCI_CHIP_I854:
623 - chipset->name = "854";
624 - chipset->info = &intel_i8xx_info;
625 - break;
626 - case PCI_CHIP_I855_GM:
627 - /* Check capid register to find the chipset variant */
628 - pci_device_cfg_read_u32(pci, &capid, I85X_CAPID);
629 - chipset->variant =
630 - (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
631 - switch (chipset->variant) {
632 - case I855_GM:
633 - chipset->name = "855GM";
634 - break;
635 - case I855_GME:
636 - chipset->name = "855GME";
637 - break;
638 - case I852_GM:
639 - chipset->name = "852GM";
640 - break;
641 - case I852_GME:
642 - chipset->name = "852GME";
643 - break;
644 - default:
645 - xf86DrvMsg(scrn->scrnIndex, X_INFO,
646 - "Unknown 852GM/855GM variant: 0x%x)\n",
647 - chipset->variant);
648 - chipset->name = "852GM/855GM (unknown variant)";
649 - break;
650 + int i;
651 +
652 + chipset->info = chipset_info;
653 +
654 + for (i = 0; intel_chipsets[i].name != NULL; i++) {
655 + if (DEVICE_ID(pci) == intel_chipsets[i].token) {
656 + chipset->name = intel_chipsets[i].name;
657 + break;
658 + }
659 + }
660 + if (intel_chipsets[i].name == NULL) {
661 + chipset->name = "unknown chipset";
662 }
663 - chipset->info = &intel_i8xx_info;
664 - break;
665 - case PCI_CHIP_I865_G:
666 - chipset->name = "865G";
667 - chipset->info = &intel_i8xx_info;
668 - break;
669 - case PCI_CHIP_I915_G:
670 - chipset->name = "915G";
671 - chipset->info = &intel_i915_info;
672 - break;
673 - case PCI_CHIP_E7221_G:
674 - chipset->name = "E7221 (i915)";
675 - chipset->info = &intel_i915_info;
676 - break;
677 - case PCI_CHIP_I915_GM:
678 - chipset->name = "915GM";
679 - chipset->info = &intel_i915_info;
680 - break;
681 - case PCI_CHIP_I945_G:
682 - chipset->name = "945G";
683 - chipset->info = &intel_i915_info;
684 - break;
685 - case PCI_CHIP_I945_GM:
686 - chipset->name = "945GM";
687 - chipset->info = &intel_i915_info;
688 - break;
689 - case PCI_CHIP_I945_GME:
690 - chipset->name = "945GME";
691 - chipset->info = &intel_i915_info;
692 - break;
693 - case PCI_CHIP_PINEVIEW_M:
694 - chipset->name = "Pineview GM";
695 - chipset->info = &intel_g33_info;
696 - break;
697 - case PCI_CHIP_PINEVIEW_G:
698 - chipset->name = "Pineview G";
699 - chipset->info = &intel_g33_info;
700 - break;
701 - case PCI_CHIP_I965_G:
702 - chipset->name = "965G";
703 - chipset->info = &intel_i965_info;
704 - break;
705 - case PCI_CHIP_G35_G:
706 - chipset->name = "G35";
707 - chipset->info = &intel_i965_info;
708 - break;
709 - case PCI_CHIP_I965_Q:
710 - chipset->name = "965Q";
711 - chipset->info = &intel_i965_info;
712 - break;
713 - case PCI_CHIP_I946_GZ:
714 - chipset->name = "946GZ";
715 - chipset->info = &intel_i965_info;
716 - break;
717 - case PCI_CHIP_I965_GM:
718 - chipset->name = "965GM";
719 - chipset->info = &intel_i965_info;
720 - break;
721 - case PCI_CHIP_I965_GME:
722 - chipset->name = "965GME/GLE";
723 - chipset->info = &intel_i965_info;
724 - break;
725 - case PCI_CHIP_G33_G:
726 - chipset->name = "G33";
727 - chipset->info = &intel_g33_info;
728 - break;
729 - case PCI_CHIP_Q35_G:
730 - chipset->name = "Q35";
731 - chipset->info = &intel_g33_info;
732 - break;
733 - case PCI_CHIP_Q33_G:
734 - chipset->name = "Q33";
735 - chipset->info = &intel_g33_info;
736 - break;
737 - case PCI_CHIP_GM45_GM:
738 - chipset->name = "GM45";
739 - chipset->info = &intel_g4x_info;
740 - break;
741 - case PCI_CHIP_G45_E_G:
742 - chipset->name = "4 Series";
743 - chipset->info = &intel_g4x_info;
744 - break;
745 - case PCI_CHIP_G45_G:
746 - chipset->name = "G45/G43";
747 - chipset->info = &intel_g4x_info;
748 - break;
749 - case PCI_CHIP_Q45_G:
750 - chipset->name = "Q45/Q43";
751 - chipset->info = &intel_g4x_info;
752 - break;
753 - case PCI_CHIP_G41_G:
754 - chipset->name = "G41";
755 - chipset->info = &intel_g4x_info;
756 - break;
757 - case PCI_CHIP_B43_G:
758 - chipset->name = "B43";
759 - chipset->info = &intel_g4x_info;
760 - break;
761 - case PCI_CHIP_IRONLAKE_D_G:
762 - chipset->name = "Clarkdale";
763 - chipset->info = &intel_ironlake_info;
764 - break;
765 - case PCI_CHIP_IRONLAKE_M_G:
766 - chipset->name = "Arrandale";
767 - chipset->info = &intel_ironlake_info;
768 - break;
769 - case PCI_CHIP_SANDYBRIDGE_GT1:
770 - case PCI_CHIP_SANDYBRIDGE_GT2:
771 - case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
772 - case PCI_CHIP_SANDYBRIDGE_M_GT1:
773 - case PCI_CHIP_SANDYBRIDGE_M_GT2:
774 - case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
775 - case PCI_CHIP_SANDYBRIDGE_S_GT:
776 - chipset->name = "Sandybridge";
777 - chipset->info = &intel_sandybridge_info;
778 - break;
779 - default:
780 - chipset->name = "unknown chipset";
781 - break;
782 - }
783 -
784 - xf86DrvMsg(scrn->scrnIndex, X_INFO,
785 - "Integrated Graphics Chipset: Intel(R) %s\n", chipset->name);
786 +
787 + xf86DrvMsg(scrn->scrnIndex, X_INFO,
788 + "Integrated Graphics Chipset: Intel(R) %s\n", chipset->name);
789 }
791 /*
792 @@ -404,30 +225,30 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
793 */
794 static void intel_identify(int flags)
795 {
796 - xf86PrintChipsets(INTEL_NAME,
797 - "Driver for Intel Integrated Graphics Chipsets",
798 - intel_chipsets);
799 + xf86PrintChipsets(INTEL_NAME,
800 + "Driver for Intel Integrated Graphics Chipsets",
801 + intel_chipsets);
802 }
804 static Bool intel_driver_func(ScrnInfoPtr pScrn,
805 xorgDriverFuncOp op,
806 pointer ptr)
807 {
808 - xorgHWFlags *flag;
809 + xorgHWFlags *flag;
811 - switch (op) {
812 - case GET_REQUIRED_HW_INTERFACES:
813 - flag = (CARD32*)ptr;
814 + switch (op) {
815 + case GET_REQUIRED_HW_INTERFACES:
816 + flag = (CARD32*)ptr;
817 #ifdef KMS_ONLY
818 - (*flag) = 0;
819 + (*flag) = 0;
820 #else
821 - (*flag) = HW_IO | HW_MMIO;
822 + (*flag) = HW_IO | HW_MMIO;
823 #endif
824 - return TRUE;
825 - default:
826 - /* Unknown or deprecated function */
827 - return FALSE;
828 - }
829 + return TRUE;
830 + default:
831 + /* Unknown or deprecated function */
832 + return FALSE;
833 + }
834 }
836 static Bool has_kernel_mode_setting(struct pci_device *dev)
837 @@ -458,55 +279,65 @@ static Bool has_kernel_mode_setting(struct pci_device *dev)
838 * Setup the dispatch table for the rest of the driver functions.
839 *
840 */
841 -static Bool intel_pci_probe (DriverPtr driver,
842 - int entity_num,
843 - struct pci_device *device,
844 - intptr_t match_data)
845 +static Bool intel_pci_probe(DriverPtr driver,
846 + int entity_num,
847 + struct pci_device *device,
848 + intptr_t match_data)
849 {
850 - ScrnInfoPtr scrn;
851 + ScrnInfoPtr scrn;
852 + PciChipsets intel_pci_chipsets[ARRAY_SIZE(intel_chipsets)];
853 + int i;
854 +
855 + chipset_info = (void *)match_data;
857 - if (!has_kernel_mode_setting(device)) {
858 + if (!has_kernel_mode_setting(device)) {
859 #if KMS_ONLY
860 - return FALSE;
861 + return FALSE;
862 #else
863 - switch (DEVICE_ID(device)) {
864 - case PCI_CHIP_I810:
865 - case PCI_CHIP_I810_DC100:
866 - case PCI_CHIP_I810_E:
867 - case PCI_CHIP_I815:
868 - break;
869 - default:
870 - return FALSE;
871 - }
872 + switch (DEVICE_ID(device)) {
873 + case PCI_CHIP_I810:
874 + case PCI_CHIP_I810_DC100:
875 + case PCI_CHIP_I810_E:
876 + case PCI_CHIP_I815:
877 + break;
878 + default:
879 + return FALSE;
880 + }
881 #endif
882 - }
883 + }
885 - scrn = xf86ConfigPciEntity(NULL, 0, entity_num, intel_pci_chipsets,
886 - NULL, NULL, NULL, NULL, NULL);
887 - if (scrn != NULL) {
888 - scrn->driverVersion = INTEL_VERSION;
889 - scrn->driverName = INTEL_DRIVER_NAME;
890 - scrn->name = INTEL_NAME;
891 - scrn->Probe = NULL;
892 + for (i = 0; i < ARRAY_SIZE(intel_chipsets); i++) {
893 + intel_pci_chipsets[i].numChipset = intel_chipsets[i].token;
894 + intel_pci_chipsets[i].PCIid = intel_chipsets[i].token;
895 + intel_pci_chipsets[i].dummy = NULL;
896 + }
897 +
898 + scrn = xf86ConfigPciEntity(NULL, 0, entity_num, intel_pci_chipsets,
899 + NULL, NULL, NULL, NULL, NULL);
900 + if (scrn != NULL) {
901 + scrn->driverVersion = INTEL_VERSION;
902 + scrn->driverName = INTEL_DRIVER_NAME;
903 + scrn->name = INTEL_NAME;
904 + scrn->Probe = NULL;
906 #if KMS_ONLY
907 - intel_init_scrn(scrn);
908 + intel_init_scrn(scrn);
909 #else
910 - switch (DEVICE_ID(device)) {
911 - case PCI_CHIP_I810:
912 - case PCI_CHIP_I810_DC100:
913 - case PCI_CHIP_I810_E:
914 - case PCI_CHIP_I815:
915 - lg_i810_init(scrn);
916 - break;
917 -
918 - default:
919 - intel_init_scrn(scrn);
920 - break;
921 - }
922 + switch (DEVICE_ID(device)) {
923 + case PCI_CHIP_I810:
924 + case PCI_CHIP_I810_DC100:
925 + case PCI_CHIP_I810_E:
926 + case PCI_CHIP_I815:
927 + lg_i810_init(scrn);
928 + break;
929 +
930 + default:
931 + intel_init_scrn(scrn);
932 + break;
933 + }
934 #endif
935 - }
936 - return scrn != NULL;
937 + }
938 + return scrn != NULL;
939 }
941 #ifdef XFree86LOADER
942 @@ -514,16 +345,16 @@ static Bool intel_pci_probe (DriverPtr driver,
943 static MODULESETUPPROTO(intel_setup);
945 static XF86ModuleVersionInfo intel_version = {
946 - "intel",
947 - MODULEVENDORSTRING,
948 - MODINFOSTRING1,
949 - MODINFOSTRING2,
950 - XORG_VERSION_CURRENT,
951 - INTEL_VERSION_MAJOR, INTEL_VERSION_MINOR, INTEL_VERSION_PATCH,
952 - ABI_CLASS_VIDEODRV,
953 - ABI_VIDEODRV_VERSION,
954 - MOD_CLASS_VIDEODRV,
955 - {0, 0, 0, 0}
956 + "intel",
957 + MODULEVENDORSTRING,
958 + MODINFOSTRING1,
959 + MODINFOSTRING2,
960 + XORG_VERSION_CURRENT,
961 + INTEL_VERSION_MAJOR, INTEL_VERSION_MINOR, INTEL_VERSION_PATCH,
962 + ABI_CLASS_VIDEODRV,
963 + ABI_VIDEODRV_VERSION,
964 + MOD_CLASS_VIDEODRV,
965 + {0, 0, 0, 0}
966 };
968 static const OptionInfoRec *
969 @@ -546,16 +377,16 @@ intel_available_options(int chipid, int busid)
970 }
972 static DriverRec intel = {
973 - INTEL_VERSION,
974 - INTEL_DRIVER_NAME,
975 - intel_identify,
976 - NULL,
977 - intel_available_options,
978 - NULL,
979 - 0,
980 - intel_driver_func,
981 - intel_device_match,
982 - intel_pci_probe
983 + INTEL_VERSION,
984 + INTEL_DRIVER_NAME,
985 + intel_identify,
986 + NULL,
987 + intel_available_options,
988 + NULL,
989 + 0,
990 + intel_driver_func,
991 + intel_device_match,
992 + intel_pci_probe
993 };
995 static pointer intel_setup(pointer module,
996 @@ -563,24 +394,24 @@ static pointer intel_setup(pointer module,
997 int *errmaj,
998 int *errmin)
999 {
1000 - static Bool setupDone = 0;
1001 -
1002 - /* This module should be loaded only once, but check to be sure.
1003 - */
1004 - if (!setupDone) {
1005 - setupDone = 1;
1006 - xf86AddDriver(&intel, module, HaveDriverFuncs);
1007 -
1008 - /*
1009 - * The return value must be non-NULL on success even though there
1010 - * is no TearDownProc.
1011 - */
1012 - return (pointer) 1;
1013 - } else {
1014 - if (errmaj)
1015 - *errmaj = LDR_ONCEONLY;
1016 - return NULL;
1017 - }
1018 + static Bool setupDone = 0;
1019 +
1020 + /* This module should be loaded only once, but check to be sure.
1021 + */
1022 + if (!setupDone) {
1023 + setupDone = 1;
1024 + xf86AddDriver(&intel, module, HaveDriverFuncs);
1025 +
1026 + /*
1027 + * The return value must be non-NULL on success even though there
1028 + * is no TearDownProc.
1029 + */
1030 + return (pointer) 1;
1031 + } else {
1032 + if (errmaj)
1033 + *errmaj = LDR_ONCEONLY;
1034 + return NULL;
1035 + }
1036 }
1038 _X_EXPORT XF86ModuleData intelModuleData = { &intel_version, intel_setup, NULL };
1039 diff --git a/src/intel_video.c b/src/intel_video.c
1040 index 499614f..021ca5f 100644
1041 --- a/src/intel_video.c
1042 +++ b/src/intel_video.c
1043 @@ -1599,6 +1599,7 @@ I830PutImageTextured(ScrnInfoPtr scrn,
1044 pixmap);
1045 }
1047 + intel_get_screen_private(scrn)->needs_flush = TRUE;
1048 DamageDamageRegion(drawable, clipBoxes);
1050 return Success;