4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "pixel_ops.h"
30 #include "qemu-timer.h"
34 //#define DEBUG_VGA_MEM
35 //#define DEBUG_VGA_REG
37 //#define DEBUG_BOCHS_VBE
39 /* force some bits to zero */
40 const uint8_t sr_mask
[8] = {
51 const uint8_t gr_mask
[16] = {
70 #define cbswap_32(__x) \
72 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
73 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
74 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
75 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
77 #ifdef HOST_WORDS_BIGENDIAN
78 #define PAT(x) cbswap_32(x)
83 #ifdef HOST_WORDS_BIGENDIAN
89 #ifdef HOST_WORDS_BIGENDIAN
90 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
92 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
95 static const uint32_t mask16
[16] = {
116 #ifdef HOST_WORDS_BIGENDIAN
119 #define PAT(x) cbswap_32(x)
122 static const uint32_t dmask16
[16] = {
141 static const uint32_t dmask4
[4] = {
148 static uint32_t expand4
[256];
149 static uint16_t expand2
[256];
150 static uint8_t expand4to8
[16];
152 static void vga_screen_dump(void *opaque
, const char *filename
);
153 static char *screen_dump_filename
;
154 static DisplayChangeListener
*screen_dump_dcl
;
156 static void vga_dumb_update_retrace_info(VGAState
*s
)
161 static void vga_precise_update_retrace_info(VGAState
*s
)
164 int hretr_start_char
;
165 int hretr_skew_chars
;
169 int vretr_start_line
;
172 int div2
, sldiv2
, dots
;
175 const int clk_hz
[] = {25175000, 28322000, 25175000, 25175000};
176 int64_t chars_per_sec
;
177 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
179 htotal_chars
= s
->cr
[0x00] + 5;
180 hretr_start_char
= s
->cr
[0x04];
181 hretr_skew_chars
= (s
->cr
[0x05] >> 5) & 3;
182 hretr_end_char
= s
->cr
[0x05] & 0x1f;
184 vtotal_lines
= (s
->cr
[0x06]
185 | (((s
->cr
[0x07] & 1) | ((s
->cr
[0x07] >> 4) & 2)) << 8)) + 2
187 vretr_start_line
= s
->cr
[0x10]
188 | ((((s
->cr
[0x07] >> 2) & 1) | ((s
->cr
[0x07] >> 6) & 2)) << 8)
190 vretr_end_line
= s
->cr
[0x11] & 0xf;
193 div2
= (s
->cr
[0x17] >> 2) & 1;
194 sldiv2
= (s
->cr
[0x17] >> 3) & 1;
196 clocking_mode
= (s
->sr
[0x01] >> 3) & 1;
197 clock_sel
= (s
->msr
>> 2) & 3;
198 dots
= (s
->msr
& 1) ? 8 : 9;
200 chars_per_sec
= clk_hz
[clock_sel
] / dots
;
202 htotal_chars
<<= clocking_mode
;
204 r
->total_chars
= vtotal_lines
* htotal_chars
;
206 r
->ticks_per_char
= ticks_per_sec
/ (r
->total_chars
* r
->freq
);
208 r
->ticks_per_char
= ticks_per_sec
/ chars_per_sec
;
211 r
->vstart
= vretr_start_line
;
212 r
->vend
= r
->vstart
+ vretr_end_line
+ 1;
214 r
->hstart
= hretr_start_char
+ hretr_skew_chars
;
215 r
->hend
= r
->hstart
+ hretr_end_char
+ 1;
216 r
->htotal
= htotal_chars
;
228 "div2 = %d sldiv2 = %d\n"
229 "clocking_mode = %d\n"
230 "clock_sel = %d %d\n"
232 "ticks/char = %lld\n"
234 (double) ticks_per_sec
/ (r
->ticks_per_char
* r
->total_chars
),
252 static uint8_t vga_precise_retrace(VGAState
*s
)
254 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
255 uint8_t val
= s
->st01
& ~(ST01_V_RETRACE
| ST01_DISP_ENABLE
);
257 if (r
->total_chars
) {
258 int cur_line
, cur_line_char
, cur_char
;
261 cur_tick
= qemu_get_clock(vm_clock
);
263 cur_char
= (cur_tick
/ r
->ticks_per_char
) % r
->total_chars
;
264 cur_line
= cur_char
/ r
->htotal
;
266 if (cur_line
>= r
->vstart
&& cur_line
<= r
->vend
) {
267 val
|= ST01_V_RETRACE
| ST01_DISP_ENABLE
;
269 cur_line_char
= cur_char
% r
->htotal
;
270 if (cur_line_char
>= r
->hstart
&& cur_line_char
<= r
->hend
) {
271 val
|= ST01_DISP_ENABLE
;
277 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
281 static uint8_t vga_dumb_retrace(VGAState
*s
)
283 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
286 static uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
288 VGAState
*s
= opaque
;
291 /* check port range access depending on color/monochrome mode */
292 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
)) ||
293 (addr
>= 0x3d0 && addr
<= 0x3df && !(s
->msr
& MSR_COLOR_EMULATION
))) {
298 if (s
->ar_flip_flop
== 0) {
305 index
= s
->ar_index
& 0x1f;
318 val
= s
->sr
[s
->sr_index
];
320 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
327 val
= s
->dac_write_index
;
330 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
331 if (++s
->dac_sub_index
== 3) {
332 s
->dac_sub_index
= 0;
346 val
= s
->gr
[s
->gr_index
];
348 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
357 val
= s
->cr
[s
->cr_index
];
359 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
364 /* just toggle to fool polling */
365 val
= s
->st01
= s
->retrace(s
);
373 #if defined(DEBUG_VGA)
374 printf("VGA: read addr=0x%04x data=0x%02x\n", addr
, val
);
379 static void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
381 VGAState
*s
= opaque
;
384 /* check port range access depending on color/monochrome mode */
385 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
)) ||
386 (addr
>= 0x3d0 && addr
<= 0x3df && !(s
->msr
& MSR_COLOR_EMULATION
)))
390 printf("VGA: write addr=0x%04x data=0x%02x\n", addr
, val
);
395 if (s
->ar_flip_flop
== 0) {
399 index
= s
->ar_index
& 0x1f;
402 s
->ar
[index
] = val
& 0x3f;
405 s
->ar
[index
] = val
& ~0x10;
411 s
->ar
[index
] = val
& ~0xc0;
414 s
->ar
[index
] = val
& ~0xf0;
417 s
->ar
[index
] = val
& ~0xf0;
423 s
->ar_flip_flop
^= 1;
426 s
->msr
= val
& ~0x10;
427 s
->update_retrace_info(s
);
430 s
->sr_index
= val
& 7;
434 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
436 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
437 if (s
->sr_index
== 1) s
->update_retrace_info(s
);
440 s
->dac_read_index
= val
;
441 s
->dac_sub_index
= 0;
445 s
->dac_write_index
= val
;
446 s
->dac_sub_index
= 0;
450 s
->dac_cache
[s
->dac_sub_index
] = val
;
451 if (++s
->dac_sub_index
== 3) {
452 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
453 s
->dac_sub_index
= 0;
454 s
->dac_write_index
++;
458 s
->gr_index
= val
& 0x0f;
462 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
464 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
473 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
475 /* handle CR0-7 protection */
476 if ((s
->cr
[0x11] & 0x80) && s
->cr_index
<= 7) {
477 /* can always write bit 4 of CR7 */
478 if (s
->cr_index
== 7)
479 s
->cr
[7] = (s
->cr
[7] & ~0x10) | (val
& 0x10);
482 switch(s
->cr_index
) {
483 case 0x01: /* horizontal display end */
488 case 0x12: /* vertical display end */
489 s
->cr
[s
->cr_index
] = val
;
492 s
->cr
[s
->cr_index
] = val
;
496 switch(s
->cr_index
) {
504 s
->update_retrace_info(s
);
515 #ifdef CONFIG_BOCHS_VBE
516 static uint32_t vbe_ioport_read_index(void *opaque
, uint32_t addr
)
518 VGAState
*s
= opaque
;
524 static uint32_t vbe_ioport_read_data(void *opaque
, uint32_t addr
)
526 VGAState
*s
= opaque
;
529 if (s
->vbe_index
<= VBE_DISPI_INDEX_NB
) {
530 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_GETCAPS
) {
531 switch(s
->vbe_index
) {
532 /* XXX: do not hardcode ? */
533 case VBE_DISPI_INDEX_XRES
:
534 val
= VBE_DISPI_MAX_XRES
;
536 case VBE_DISPI_INDEX_YRES
:
537 val
= VBE_DISPI_MAX_YRES
;
539 case VBE_DISPI_INDEX_BPP
:
540 val
= VBE_DISPI_MAX_BPP
;
543 val
= s
->vbe_regs
[s
->vbe_index
];
547 val
= s
->vbe_regs
[s
->vbe_index
];
552 #ifdef DEBUG_BOCHS_VBE
553 printf("VBE: read index=0x%x val=0x%x\n", s
->vbe_index
, val
);
558 static void vbe_ioport_write_index(void *opaque
, uint32_t addr
, uint32_t val
)
560 VGAState
*s
= opaque
;
564 static void vbe_ioport_write_data(void *opaque
, uint32_t addr
, uint32_t val
)
566 VGAState
*s
= opaque
;
568 if (s
->vbe_index
<= VBE_DISPI_INDEX_NB
) {
569 #ifdef DEBUG_BOCHS_VBE
570 printf("VBE: write index=0x%x val=0x%x\n", s
->vbe_index
, val
);
572 switch(s
->vbe_index
) {
573 case VBE_DISPI_INDEX_ID
:
574 if (val
== VBE_DISPI_ID0
||
575 val
== VBE_DISPI_ID1
||
576 val
== VBE_DISPI_ID2
||
577 val
== VBE_DISPI_ID3
||
578 val
== VBE_DISPI_ID4
) {
579 s
->vbe_regs
[s
->vbe_index
] = val
;
582 case VBE_DISPI_INDEX_XRES
:
583 if ((val
<= VBE_DISPI_MAX_XRES
) && ((val
& 7) == 0)) {
584 s
->vbe_regs
[s
->vbe_index
] = val
;
587 case VBE_DISPI_INDEX_YRES
:
588 if (val
<= VBE_DISPI_MAX_YRES
) {
589 s
->vbe_regs
[s
->vbe_index
] = val
;
592 case VBE_DISPI_INDEX_BPP
:
595 if (val
== 4 || val
== 8 || val
== 15 ||
596 val
== 16 || val
== 24 || val
== 32) {
597 s
->vbe_regs
[s
->vbe_index
] = val
;
600 case VBE_DISPI_INDEX_BANK
:
601 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4) {
602 val
&= (s
->vbe_bank_mask
>> 2);
604 val
&= s
->vbe_bank_mask
;
606 s
->vbe_regs
[s
->vbe_index
] = val
;
607 s
->bank_offset
= (val
<< 16);
609 case VBE_DISPI_INDEX_ENABLE
:
610 if ((val
& VBE_DISPI_ENABLED
) &&
611 !(s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
)) {
612 int h
, shift_control
;
614 s
->vbe_regs
[VBE_DISPI_INDEX_VIRT_WIDTH
] =
615 s
->vbe_regs
[VBE_DISPI_INDEX_XRES
];
616 s
->vbe_regs
[VBE_DISPI_INDEX_VIRT_HEIGHT
] =
617 s
->vbe_regs
[VBE_DISPI_INDEX_YRES
];
618 s
->vbe_regs
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
619 s
->vbe_regs
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
621 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4)
622 s
->vbe_line_offset
= s
->vbe_regs
[VBE_DISPI_INDEX_XRES
] >> 1;
624 s
->vbe_line_offset
= s
->vbe_regs
[VBE_DISPI_INDEX_XRES
] *
625 ((s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] + 7) >> 3);
626 s
->vbe_start_addr
= 0;
628 /* clear the screen (should be done in BIOS) */
629 if (!(val
& VBE_DISPI_NOCLEARMEM
)) {
630 memset(s
->vram_ptr
, 0,
631 s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] * s
->vbe_line_offset
);
634 /* we initialize the VGA graphic mode (should be done
636 s
->gr
[0x06] = (s
->gr
[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
637 s
->cr
[0x17] |= 3; /* no CGA modes */
638 s
->cr
[0x13] = s
->vbe_line_offset
>> 3;
640 s
->cr
[0x01] = (s
->vbe_regs
[VBE_DISPI_INDEX_XRES
] >> 3) - 1;
641 /* height (only meaningful if < 1024) */
642 h
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] - 1;
644 s
->cr
[0x07] = (s
->cr
[0x07] & ~0x42) |
645 ((h
>> 7) & 0x02) | ((h
>> 3) & 0x40);
646 /* line compare to 1023 */
651 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4) {
653 s
->sr
[0x01] &= ~8; /* no double line */
656 s
->sr
[4] |= 0x08; /* set chain 4 mode */
657 s
->sr
[2] |= 0x0f; /* activate all planes */
659 s
->gr
[0x05] = (s
->gr
[0x05] & ~0x60) | (shift_control
<< 5);
660 s
->cr
[0x09] &= ~0x9f; /* no double scan */
662 /* XXX: the bios should do that */
665 s
->dac_8bit
= (val
& VBE_DISPI_8BIT_DAC
) > 0;
666 s
->vbe_regs
[s
->vbe_index
] = val
;
668 case VBE_DISPI_INDEX_VIRT_WIDTH
:
670 int w
, h
, line_offset
;
672 if (val
< s
->vbe_regs
[VBE_DISPI_INDEX_XRES
])
675 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4)
676 line_offset
= w
>> 1;
678 line_offset
= w
* ((s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] + 7) >> 3);
679 h
= s
->vram_size
/ line_offset
;
680 /* XXX: support weird bochs semantics ? */
681 if (h
< s
->vbe_regs
[VBE_DISPI_INDEX_YRES
])
683 s
->vbe_regs
[VBE_DISPI_INDEX_VIRT_WIDTH
] = w
;
684 s
->vbe_regs
[VBE_DISPI_INDEX_VIRT_HEIGHT
] = h
;
685 s
->vbe_line_offset
= line_offset
;
688 case VBE_DISPI_INDEX_X_OFFSET
:
689 case VBE_DISPI_INDEX_Y_OFFSET
:
692 s
->vbe_regs
[s
->vbe_index
] = val
;
693 s
->vbe_start_addr
= s
->vbe_line_offset
* s
->vbe_regs
[VBE_DISPI_INDEX_Y_OFFSET
];
694 x
= s
->vbe_regs
[VBE_DISPI_INDEX_X_OFFSET
];
695 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4)
696 s
->vbe_start_addr
+= x
>> 1;
698 s
->vbe_start_addr
+= x
* ((s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] + 7) >> 3);
699 s
->vbe_start_addr
>>= 2;
709 /* called for accesses between 0xa0000 and 0xc0000 */
710 uint32_t vga_mem_readb(void *opaque
, target_phys_addr_t addr
)
712 VGAState
*s
= opaque
;
713 int memory_map_mode
, plane
;
716 /* convert to VGA memory offset */
717 memory_map_mode
= (s
->gr
[6] >> 2) & 3;
719 switch(memory_map_mode
) {
725 addr
+= s
->bank_offset
;
740 if (s
->sr
[4] & 0x08) {
741 /* chain 4 mode : simplest access */
742 ret
= s
->vram_ptr
[addr
];
743 } else if (s
->gr
[5] & 0x10) {
744 /* odd/even mode (aka text mode mapping) */
745 plane
= (s
->gr
[4] & 2) | (addr
& 1);
746 ret
= s
->vram_ptr
[((addr
& ~1) << 1) | plane
];
748 /* standard VGA latched access */
749 s
->latch
= ((uint32_t *)s
->vram_ptr
)[addr
];
751 if (!(s
->gr
[5] & 0x08)) {
754 ret
= GET_PLANE(s
->latch
, plane
);
757 ret
= (s
->latch
^ mask16
[s
->gr
[2]]) & mask16
[s
->gr
[7]];
766 static uint32_t vga_mem_readw(void *opaque
, target_phys_addr_t addr
)
769 #ifdef TARGET_WORDS_BIGENDIAN
770 v
= vga_mem_readb(opaque
, addr
) << 8;
771 v
|= vga_mem_readb(opaque
, addr
+ 1);
773 v
= vga_mem_readb(opaque
, addr
);
774 v
|= vga_mem_readb(opaque
, addr
+ 1) << 8;
779 static uint32_t vga_mem_readl(void *opaque
, target_phys_addr_t addr
)
782 #ifdef TARGET_WORDS_BIGENDIAN
783 v
= vga_mem_readb(opaque
, addr
) << 24;
784 v
|= vga_mem_readb(opaque
, addr
+ 1) << 16;
785 v
|= vga_mem_readb(opaque
, addr
+ 2) << 8;
786 v
|= vga_mem_readb(opaque
, addr
+ 3);
788 v
= vga_mem_readb(opaque
, addr
);
789 v
|= vga_mem_readb(opaque
, addr
+ 1) << 8;
790 v
|= vga_mem_readb(opaque
, addr
+ 2) << 16;
791 v
|= vga_mem_readb(opaque
, addr
+ 3) << 24;
796 /* called for accesses between 0xa0000 and 0xc0000 */
797 void vga_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
799 VGAState
*s
= opaque
;
800 int memory_map_mode
, plane
, write_mode
, b
, func_select
, mask
;
801 uint32_t write_mask
, bit_mask
, set_mask
;
804 printf("vga: [0x" TARGET_FMT_plx
"] = 0x%02x\n", addr
, val
);
806 /* convert to VGA memory offset */
807 memory_map_mode
= (s
->gr
[6] >> 2) & 3;
809 switch(memory_map_mode
) {
815 addr
+= s
->bank_offset
;
830 if (s
->sr
[4] & 0x08) {
831 /* chain 4 mode : simplest access */
834 if (s
->sr
[2] & mask
) {
835 s
->vram_ptr
[addr
] = val
;
837 printf("vga: chain4: [0x" TARGET_FMT_plx
"]\n", addr
);
839 s
->plane_updated
|= mask
; /* only used to detect font change */
840 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
842 } else if (s
->gr
[5] & 0x10) {
843 /* odd/even mode (aka text mode mapping) */
844 plane
= (s
->gr
[4] & 2) | (addr
& 1);
846 if (s
->sr
[2] & mask
) {
847 addr
= ((addr
& ~1) << 1) | plane
;
848 s
->vram_ptr
[addr
] = val
;
850 printf("vga: odd/even: [0x" TARGET_FMT_plx
"]\n", addr
);
852 s
->plane_updated
|= mask
; /* only used to detect font change */
853 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
856 /* standard VGA latched access */
857 write_mode
= s
->gr
[5] & 3;
863 val
= ((val
>> b
) | (val
<< (8 - b
))) & 0xff;
867 /* apply set/reset mask */
868 set_mask
= mask16
[s
->gr
[1]];
869 val
= (val
& ~set_mask
) | (mask16
[s
->gr
[0]] & set_mask
);
876 val
= mask16
[val
& 0x0f];
882 val
= (val
>> b
) | (val
<< (8 - b
));
884 bit_mask
= s
->gr
[8] & val
;
885 val
= mask16
[s
->gr
[0]];
889 /* apply logical operation */
890 func_select
= s
->gr
[3] >> 3;
891 switch(func_select
) {
911 bit_mask
|= bit_mask
<< 8;
912 bit_mask
|= bit_mask
<< 16;
913 val
= (val
& bit_mask
) | (s
->latch
& ~bit_mask
);
916 /* mask data according to sr[2] */
918 s
->plane_updated
|= mask
; /* only used to detect font change */
919 write_mask
= mask16
[mask
];
920 ((uint32_t *)s
->vram_ptr
)[addr
] =
921 (((uint32_t *)s
->vram_ptr
)[addr
] & ~write_mask
) |
924 printf("vga: latch: [0x" TARGET_FMT_plx
"] mask=0x%08x val=0x%08x\n",
925 addr
* 4, write_mask
, val
);
927 cpu_physical_memory_set_dirty(s
->vram_offset
+ (addr
<< 2));
931 static void vga_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
933 #ifdef TARGET_WORDS_BIGENDIAN
934 vga_mem_writeb(opaque
, addr
, (val
>> 8) & 0xff);
935 vga_mem_writeb(opaque
, addr
+ 1, val
& 0xff);
937 vga_mem_writeb(opaque
, addr
, val
& 0xff);
938 vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
942 static void vga_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
944 #ifdef TARGET_WORDS_BIGENDIAN
945 vga_mem_writeb(opaque
, addr
, (val
>> 24) & 0xff);
946 vga_mem_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
947 vga_mem_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
948 vga_mem_writeb(opaque
, addr
+ 3, val
& 0xff);
950 vga_mem_writeb(opaque
, addr
, val
& 0xff);
951 vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
952 vga_mem_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
953 vga_mem_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
957 typedef void vga_draw_glyph8_func(uint8_t *d
, int linesize
,
958 const uint8_t *font_ptr
, int h
,
959 uint32_t fgcol
, uint32_t bgcol
);
960 typedef void vga_draw_glyph9_func(uint8_t *d
, int linesize
,
961 const uint8_t *font_ptr
, int h
,
962 uint32_t fgcol
, uint32_t bgcol
, int dup9
);
963 typedef void vga_draw_line_func(VGAState
*s1
, uint8_t *d
,
964 const uint8_t *s
, int width
);
967 #include "vga_template.h"
970 #include "vga_template.h"
974 #include "vga_template.h"
977 #include "vga_template.h"
981 #include "vga_template.h"
984 #include "vga_template.h"
988 #include "vga_template.h"
990 static unsigned int rgb_to_pixel8_dup(unsigned int r
, unsigned int g
, unsigned b
)
993 col
= rgb_to_pixel8(r
, g
, b
);
999 static unsigned int rgb_to_pixel15_dup(unsigned int r
, unsigned int g
, unsigned b
)
1002 col
= rgb_to_pixel15(r
, g
, b
);
1007 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r
, unsigned int g
,
1011 col
= rgb_to_pixel15bgr(r
, g
, b
);
1016 static unsigned int rgb_to_pixel16_dup(unsigned int r
, unsigned int g
, unsigned b
)
1019 col
= rgb_to_pixel16(r
, g
, b
);
1024 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r
, unsigned int g
,
1028 col
= rgb_to_pixel16bgr(r
, g
, b
);
1033 static unsigned int rgb_to_pixel32_dup(unsigned int r
, unsigned int g
, unsigned b
)
1036 col
= rgb_to_pixel32(r
, g
, b
);
1040 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r
, unsigned int g
, unsigned b
)
1043 col
= rgb_to_pixel32bgr(r
, g
, b
);
1047 /* return true if the palette was modified */
1048 static int update_palette16(VGAState
*s
)
1051 uint32_t v
, col
, *palette
;
1054 palette
= s
->last_palette
;
1055 for(i
= 0; i
< 16; i
++) {
1057 if (s
->ar
[0x10] & 0x80)
1058 v
= ((s
->ar
[0x14] & 0xf) << 4) | (v
& 0xf);
1060 v
= ((s
->ar
[0x14] & 0xc) << 4) | (v
& 0x3f);
1062 col
= s
->rgb_to_pixel(c6_to_8(s
->palette
[v
]),
1063 c6_to_8(s
->palette
[v
+ 1]),
1064 c6_to_8(s
->palette
[v
+ 2]));
1065 if (col
!= palette
[i
]) {
1073 /* return true if the palette was modified */
1074 static int update_palette256(VGAState
*s
)
1077 uint32_t v
, col
, *palette
;
1080 palette
= s
->last_palette
;
1082 for(i
= 0; i
< 256; i
++) {
1084 col
= s
->rgb_to_pixel(s
->palette
[v
],
1088 col
= s
->rgb_to_pixel(c6_to_8(s
->palette
[v
]),
1089 c6_to_8(s
->palette
[v
+ 1]),
1090 c6_to_8(s
->palette
[v
+ 2]));
1092 if (col
!= palette
[i
]) {
1101 static void vga_get_offsets(VGAState
*s
,
1102 uint32_t *pline_offset
,
1103 uint32_t *pstart_addr
,
1104 uint32_t *pline_compare
)
1106 uint32_t start_addr
, line_offset
, line_compare
;
1107 #ifdef CONFIG_BOCHS_VBE
1108 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
) {
1109 line_offset
= s
->vbe_line_offset
;
1110 start_addr
= s
->vbe_start_addr
;
1111 line_compare
= 65535;
1115 /* compute line_offset in bytes */
1116 line_offset
= s
->cr
[0x13];
1119 /* starting address */
1120 start_addr
= s
->cr
[0x0d] | (s
->cr
[0x0c] << 8);
1123 line_compare
= s
->cr
[0x18] |
1124 ((s
->cr
[0x07] & 0x10) << 4) |
1125 ((s
->cr
[0x09] & 0x40) << 3);
1127 *pline_offset
= line_offset
;
1128 *pstart_addr
= start_addr
;
1129 *pline_compare
= line_compare
;
1132 /* update start_addr and line_offset. Return TRUE if modified */
1133 static int update_basic_params(VGAState
*s
)
1136 uint32_t start_addr
, line_offset
, line_compare
;
1140 s
->get_offsets(s
, &line_offset
, &start_addr
, &line_compare
);
1142 if (line_offset
!= s
->line_offset
||
1143 start_addr
!= s
->start_addr
||
1144 line_compare
!= s
->line_compare
) {
1145 s
->line_offset
= line_offset
;
1146 s
->start_addr
= start_addr
;
1147 s
->line_compare
= line_compare
;
1155 static inline int get_depth_index(DisplayState
*s
)
1157 switch(ds_get_bits_per_pixel(s
)) {
1166 if (is_surface_bgr(s
->surface
))
1173 static vga_draw_glyph8_func
*vga_draw_glyph8_table
[NB_DEPTHS
] = {
1183 static vga_draw_glyph8_func
*vga_draw_glyph16_table
[NB_DEPTHS
] = {
1185 vga_draw_glyph16_16
,
1186 vga_draw_glyph16_16
,
1187 vga_draw_glyph16_32
,
1188 vga_draw_glyph16_32
,
1189 vga_draw_glyph16_16
,
1190 vga_draw_glyph16_16
,
1193 static vga_draw_glyph9_func
*vga_draw_glyph9_table
[NB_DEPTHS
] = {
1203 static const uint8_t cursor_glyph
[32 * 4] = {
1204 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1205 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1206 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1207 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1208 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1209 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1212 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1213 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1214 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1215 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1216 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1217 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1218 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1219 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1222 static void vga_get_text_resolution(VGAState
*s
, int *pwidth
, int *pheight
,
1223 int *pcwidth
, int *pcheight
)
1225 int width
, cwidth
, height
, cheight
;
1227 /* total width & height */
1228 cheight
= (s
->cr
[9] & 0x1f) + 1;
1230 if (!(s
->sr
[1] & 0x01))
1232 if (s
->sr
[1] & 0x08)
1233 cwidth
= 16; /* NOTE: no 18 pixel wide */
1234 width
= (s
->cr
[0x01] + 1);
1235 if (s
->cr
[0x06] == 100) {
1236 /* ugly hack for CGA 160x100x16 - explain me the logic */
1239 height
= s
->cr
[0x12] |
1240 ((s
->cr
[0x07] & 0x02) << 7) |
1241 ((s
->cr
[0x07] & 0x40) << 3);
1242 height
= (height
+ 1) / cheight
;
1248 *pcheight
= cheight
;
1251 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r
, unsigned int g
, unsigned b
);
1253 static rgb_to_pixel_dup_func
*rgb_to_pixel_dup_table
[NB_DEPTHS
] = {
1258 rgb_to_pixel32bgr_dup
,
1259 rgb_to_pixel15bgr_dup
,
1260 rgb_to_pixel16bgr_dup
,
1271 static void vga_draw_text(VGAState
*s
, int full_update
)
1273 int cx
, cy
, cheight
, cw
, ch
, cattr
, height
, width
, ch_attr
;
1274 int cx_min
, cx_max
, linesize
, x_incr
;
1275 uint32_t offset
, fgcol
, bgcol
, v
, cursor_offset
;
1276 uint8_t *d1
, *d
, *src
, *s1
, *dest
, *cursor_ptr
;
1277 const uint8_t *font_ptr
, *font_base
[2];
1278 int dup9
, line_offset
, depth_index
;
1280 uint32_t *ch_attr_ptr
;
1281 vga_draw_glyph8_func
*vga_draw_glyph8
;
1282 vga_draw_glyph9_func
*vga_draw_glyph9
;
1284 /* compute font data address (in plane 2) */
1286 offset
= (((v
>> 4) & 1) | ((v
<< 1) & 6)) * 8192 * 4 + 2;
1287 if (offset
!= s
->font_offsets
[0]) {
1288 s
->font_offsets
[0] = offset
;
1291 font_base
[0] = s
->vram_ptr
+ offset
;
1293 offset
= (((v
>> 5) & 1) | ((v
>> 1) & 6)) * 8192 * 4 + 2;
1294 font_base
[1] = s
->vram_ptr
+ offset
;
1295 if (offset
!= s
->font_offsets
[1]) {
1296 s
->font_offsets
[1] = offset
;
1299 if (s
->plane_updated
& (1 << 2)) {
1300 /* if the plane 2 was modified since the last display, it
1301 indicates the font may have been modified */
1302 s
->plane_updated
= 0;
1305 full_update
|= update_basic_params(s
);
1307 line_offset
= s
->line_offset
;
1308 s1
= s
->vram_ptr
+ (s
->start_addr
* 4);
1310 vga_get_text_resolution(s
, &width
, &height
, &cw
, &cheight
);
1311 x_incr
= cw
* ((ds_get_bits_per_pixel(s
->ds
) + 7) >> 3);
1312 if ((height
* width
) > CH_ATTR_SIZE
) {
1313 /* better than nothing: exit if transient size is too big */
1317 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1318 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
|| s
->last_depth
) {
1319 s
->last_scr_width
= width
* cw
;
1320 s
->last_scr_height
= height
* cheight
;
1321 qemu_console_resize(s
->ds
, s
->last_scr_width
, s
->last_scr_height
);
1323 s
->last_width
= width
;
1324 s
->last_height
= height
;
1325 s
->last_ch
= cheight
;
1330 rgb_to_pixel_dup_table
[get_depth_index(s
->ds
)];
1331 full_update
|= update_palette16(s
);
1332 palette
= s
->last_palette
;
1333 x_incr
= cw
* ((ds_get_bits_per_pixel(s
->ds
) + 7) >> 3);
1335 cursor_offset
= ((s
->cr
[0x0e] << 8) | s
->cr
[0x0f]) - s
->start_addr
;
1336 if (cursor_offset
!= s
->cursor_offset
||
1337 s
->cr
[0xa] != s
->cursor_start
||
1338 s
->cr
[0xb] != s
->cursor_end
) {
1339 /* if the cursor position changed, we update the old and new
1341 if (s
->cursor_offset
< CH_ATTR_SIZE
)
1342 s
->last_ch_attr
[s
->cursor_offset
] = -1;
1343 if (cursor_offset
< CH_ATTR_SIZE
)
1344 s
->last_ch_attr
[cursor_offset
] = -1;
1345 s
->cursor_offset
= cursor_offset
;
1346 s
->cursor_start
= s
->cr
[0xa];
1347 s
->cursor_end
= s
->cr
[0xb];
1349 cursor_ptr
= s
->vram_ptr
+ (s
->start_addr
+ cursor_offset
) * 4;
1351 depth_index
= get_depth_index(s
->ds
);
1353 vga_draw_glyph8
= vga_draw_glyph16_table
[depth_index
];
1355 vga_draw_glyph8
= vga_draw_glyph8_table
[depth_index
];
1356 vga_draw_glyph9
= vga_draw_glyph9_table
[depth_index
];
1358 dest
= ds_get_data(s
->ds
);
1359 linesize
= ds_get_linesize(s
->ds
);
1360 ch_attr_ptr
= s
->last_ch_attr
;
1361 for(cy
= 0; cy
< height
; cy
++) {
1366 for(cx
= 0; cx
< width
; cx
++) {
1367 ch_attr
= *(uint16_t *)src
;
1368 if (full_update
|| ch_attr
!= *ch_attr_ptr
) {
1373 *ch_attr_ptr
= ch_attr
;
1374 #ifdef HOST_WORDS_BIGENDIAN
1376 cattr
= ch_attr
& 0xff;
1378 ch
= ch_attr
& 0xff;
1379 cattr
= ch_attr
>> 8;
1381 font_ptr
= font_base
[(cattr
>> 3) & 1];
1382 font_ptr
+= 32 * 4 * ch
;
1383 bgcol
= palette
[cattr
>> 4];
1384 fgcol
= palette
[cattr
& 0x0f];
1386 vga_draw_glyph8(d1
, linesize
,
1387 font_ptr
, cheight
, fgcol
, bgcol
);
1390 if (ch
>= 0xb0 && ch
<= 0xdf && (s
->ar
[0x10] & 0x04))
1392 vga_draw_glyph9(d1
, linesize
,
1393 font_ptr
, cheight
, fgcol
, bgcol
, dup9
);
1395 if (src
== cursor_ptr
&&
1396 !(s
->cr
[0x0a] & 0x20)) {
1397 int line_start
, line_last
, h
;
1398 /* draw the cursor */
1399 line_start
= s
->cr
[0x0a] & 0x1f;
1400 line_last
= s
->cr
[0x0b] & 0x1f;
1401 /* XXX: check that */
1402 if (line_last
> cheight
- 1)
1403 line_last
= cheight
- 1;
1404 if (line_last
>= line_start
&& line_start
< cheight
) {
1405 h
= line_last
- line_start
+ 1;
1406 d
= d1
+ linesize
* line_start
;
1408 vga_draw_glyph8(d
, linesize
,
1409 cursor_glyph
, h
, fgcol
, bgcol
);
1411 vga_draw_glyph9(d
, linesize
,
1412 cursor_glyph
, h
, fgcol
, bgcol
, 1);
1422 dpy_update(s
->ds
, cx_min
* cw
, cy
* cheight
,
1423 (cx_max
- cx_min
+ 1) * cw
, cheight
);
1425 dest
+= linesize
* cheight
;
1444 static vga_draw_line_func
*vga_draw_line_table
[NB_DEPTHS
* VGA_DRAW_LINE_NB
] = {
1454 vga_draw_line2d2_16
,
1455 vga_draw_line2d2_16
,
1456 vga_draw_line2d2_32
,
1457 vga_draw_line2d2_32
,
1458 vga_draw_line2d2_16
,
1459 vga_draw_line2d2_16
,
1470 vga_draw_line4d2_16
,
1471 vga_draw_line4d2_16
,
1472 vga_draw_line4d2_32
,
1473 vga_draw_line4d2_32
,
1474 vga_draw_line4d2_16
,
1475 vga_draw_line4d2_16
,
1478 vga_draw_line8d2_16
,
1479 vga_draw_line8d2_16
,
1480 vga_draw_line8d2_32
,
1481 vga_draw_line8d2_32
,
1482 vga_draw_line8d2_16
,
1483 vga_draw_line8d2_16
,
1497 vga_draw_line15_32bgr
,
1498 vga_draw_line15_15bgr
,
1499 vga_draw_line15_16bgr
,
1505 vga_draw_line16_32bgr
,
1506 vga_draw_line16_15bgr
,
1507 vga_draw_line16_16bgr
,
1513 vga_draw_line24_32bgr
,
1514 vga_draw_line24_15bgr
,
1515 vga_draw_line24_16bgr
,
1521 vga_draw_line32_32bgr
,
1522 vga_draw_line32_15bgr
,
1523 vga_draw_line32_16bgr
,
1526 static int vga_get_bpp(VGAState
*s
)
1529 #ifdef CONFIG_BOCHS_VBE
1530 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
) {
1531 ret
= s
->vbe_regs
[VBE_DISPI_INDEX_BPP
];
1540 static void vga_get_resolution(VGAState
*s
, int *pwidth
, int *pheight
)
1544 #ifdef CONFIG_BOCHS_VBE
1545 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
) {
1546 width
= s
->vbe_regs
[VBE_DISPI_INDEX_XRES
];
1547 height
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
];
1551 width
= (s
->cr
[0x01] + 1) * 8;
1552 height
= s
->cr
[0x12] |
1553 ((s
->cr
[0x07] & 0x02) << 7) |
1554 ((s
->cr
[0x07] & 0x40) << 3);
1555 height
= (height
+ 1);
1561 void vga_invalidate_scanlines(VGAState
*s
, int y1
, int y2
)
1564 if (y1
>= VGA_MAX_HEIGHT
)
1566 if (y2
>= VGA_MAX_HEIGHT
)
1567 y2
= VGA_MAX_HEIGHT
;
1568 for(y
= y1
; y
< y2
; y
++) {
1569 s
->invalidated_y_table
[y
>> 5] |= 1 << (y
& 0x1f);
1573 static void vga_sync_dirty_bitmap(VGAState
*s
)
1576 cpu_physical_sync_dirty_bitmap(s
->map_addr
, s
->map_end
);
1578 if (s
->lfb_vram_mapped
) {
1579 cpu_physical_sync_dirty_bitmap(isa_mem_base
+ 0xa0000, 0xa8000);
1580 cpu_physical_sync_dirty_bitmap(isa_mem_base
+ 0xa8000, 0xb0000);
1587 static void vga_draw_graphic(VGAState
*s
, int full_update
)
1589 int y1
, y
, update
, linesize
, y_start
, double_scan
, mask
, depth
;
1590 int width
, height
, shift_control
, line_offset
, bwidth
, bits
;
1591 ram_addr_t page0
, page1
, page_min
, page_max
;
1592 int disp_width
, multi_scan
, multi_run
;
1594 uint32_t v
, addr1
, addr
;
1595 vga_draw_line_func
*vga_draw_line
;
1597 full_update
|= update_basic_params(s
);
1600 vga_sync_dirty_bitmap(s
);
1602 s
->get_resolution(s
, &width
, &height
);
1605 shift_control
= (s
->gr
[0x05] >> 5) & 3;
1606 double_scan
= (s
->cr
[0x09] >> 7);
1607 if (shift_control
!= 1) {
1608 multi_scan
= (((s
->cr
[0x09] & 0x1f) + 1) << double_scan
) - 1;
1610 /* in CGA modes, multi_scan is ignored */
1611 /* XXX: is it correct ? */
1612 multi_scan
= double_scan
;
1614 multi_run
= multi_scan
;
1615 if (shift_control
!= s
->shift_control
||
1616 double_scan
!= s
->double_scan
) {
1618 s
->shift_control
= shift_control
;
1619 s
->double_scan
= double_scan
;
1622 if (shift_control
== 0) {
1623 if (s
->sr
[0x01] & 8) {
1626 } else if (shift_control
== 1) {
1627 if (s
->sr
[0x01] & 8) {
1632 depth
= s
->get_bpp(s
);
1633 if (s
->line_offset
!= s
->last_line_offset
||
1634 disp_width
!= s
->last_width
||
1635 height
!= s
->last_height
||
1636 s
->last_depth
!= depth
) {
1637 #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1638 if (depth
== 16 || depth
== 32) {
1642 qemu_free_displaysurface(s
->ds
);
1643 s
->ds
->surface
= qemu_create_displaysurface_from(disp_width
, height
, depth
,
1645 s
->vram_ptr
+ (s
->start_addr
* 4));
1646 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1647 s
->ds
->surface
->pf
= qemu_different_endianness_pixelformat(depth
);
1651 qemu_console_resize(s
->ds
, disp_width
, height
);
1653 s
->last_scr_width
= disp_width
;
1654 s
->last_scr_height
= height
;
1655 s
->last_width
= disp_width
;
1656 s
->last_height
= height
;
1657 s
->last_line_offset
= s
->line_offset
;
1658 s
->last_depth
= depth
;
1660 } else if (is_buffer_shared(s
->ds
->surface
) &&
1661 (full_update
|| s
->ds
->surface
->data
!= s
->vram_ptr
+ (s
->start_addr
* 4))) {
1662 s
->ds
->surface
->data
= s
->vram_ptr
+ (s
->start_addr
* 4);
1667 rgb_to_pixel_dup_table
[get_depth_index(s
->ds
)];
1669 if (shift_control
== 0) {
1670 full_update
|= update_palette16(s
);
1671 if (s
->sr
[0x01] & 8) {
1672 v
= VGA_DRAW_LINE4D2
;
1677 } else if (shift_control
== 1) {
1678 full_update
|= update_palette16(s
);
1679 if (s
->sr
[0x01] & 8) {
1680 v
= VGA_DRAW_LINE2D2
;
1686 switch(s
->get_bpp(s
)) {
1689 full_update
|= update_palette256(s
);
1690 v
= VGA_DRAW_LINE8D2
;
1694 full_update
|= update_palette256(s
);
1699 v
= VGA_DRAW_LINE15
;
1703 v
= VGA_DRAW_LINE16
;
1707 v
= VGA_DRAW_LINE24
;
1711 v
= VGA_DRAW_LINE32
;
1716 vga_draw_line
= vga_draw_line_table
[v
* NB_DEPTHS
+ get_depth_index(s
->ds
)];
1718 if (!is_buffer_shared(s
->ds
->surface
) && s
->cursor_invalidate
)
1719 s
->cursor_invalidate(s
);
1721 line_offset
= s
->line_offset
;
1723 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1724 width
, height
, v
, line_offset
, s
->cr
[9], s
->cr
[0x17], s
->line_compare
, s
->sr
[0x01]);
1726 addr1
= (s
->start_addr
* 4);
1727 bwidth
= (width
* bits
+ 7) / 8;
1731 d
= ds_get_data(s
->ds
);
1732 linesize
= ds_get_linesize(s
->ds
);
1734 for(y
= 0; y
< height
; y
++) {
1736 if (!(s
->cr
[0x17] & 1)) {
1738 /* CGA compatibility handling */
1739 shift
= 14 + ((s
->cr
[0x17] >> 6) & 1);
1740 addr
= (addr
& ~(1 << shift
)) | ((y1
& 1) << shift
);
1742 if (!(s
->cr
[0x17] & 2)) {
1743 addr
= (addr
& ~0x8000) | ((y1
& 2) << 14);
1745 page0
= s
->vram_offset
+ (addr
& TARGET_PAGE_MASK
);
1746 page1
= s
->vram_offset
+ ((addr
+ bwidth
- 1) & TARGET_PAGE_MASK
);
1747 update
= full_update
|
1748 cpu_physical_memory_get_dirty(page0
, VGA_DIRTY_FLAG
) |
1749 cpu_physical_memory_get_dirty(page1
, VGA_DIRTY_FLAG
);
1750 if ((page1
- page0
) > TARGET_PAGE_SIZE
) {
1751 /* if wide line, can use another page */
1752 update
|= cpu_physical_memory_get_dirty(page0
+ TARGET_PAGE_SIZE
,
1755 /* explicit invalidation for the hardware cursor */
1756 update
|= (s
->invalidated_y_table
[y
>> 5] >> (y
& 0x1f)) & 1;
1760 if (page0
< page_min
)
1762 if (page1
> page_max
)
1764 if (!(is_buffer_shared(s
->ds
->surface
))) {
1765 vga_draw_line(s
, d
, s
->vram_ptr
+ addr
, width
);
1766 if (s
->cursor_draw_line
)
1767 s
->cursor_draw_line(s
, d
, y
);
1771 /* flush to display */
1772 dpy_update(s
->ds
, 0, y_start
,
1773 disp_width
, y
- y_start
);
1778 mask
= (s
->cr
[0x17] & 3) ^ 3;
1779 if ((y1
& mask
) == mask
)
1780 addr1
+= line_offset
;
1782 multi_run
= multi_scan
;
1786 /* line compare acts on the displayed lines */
1787 if (y
== s
->line_compare
)
1792 /* flush to display */
1793 dpy_update(s
->ds
, 0, y_start
,
1794 disp_width
, y
- y_start
);
1796 /* reset modified pages */
1797 if (page_max
>= page_min
) {
1798 cpu_physical_memory_reset_dirty(page_min
, page_max
+ TARGET_PAGE_SIZE
,
1801 memset(s
->invalidated_y_table
, 0, ((height
+ 31) >> 5) * 4);
1804 static void vga_draw_blank(VGAState
*s
, int full_update
)
1811 if (s
->last_scr_width
<= 0 || s
->last_scr_height
<= 0)
1815 rgb_to_pixel_dup_table
[get_depth_index(s
->ds
)];
1816 if (ds_get_bits_per_pixel(s
->ds
) == 8)
1817 val
= s
->rgb_to_pixel(0, 0, 0);
1820 w
= s
->last_scr_width
* ((ds_get_bits_per_pixel(s
->ds
) + 7) >> 3);
1821 d
= ds_get_data(s
->ds
);
1822 for(i
= 0; i
< s
->last_scr_height
; i
++) {
1824 d
+= ds_get_linesize(s
->ds
);
1826 dpy_update(s
->ds
, 0, 0,
1827 s
->last_scr_width
, s
->last_scr_height
);
1830 #define GMODE_TEXT 0
1831 #define GMODE_GRAPH 1
1832 #define GMODE_BLANK 2
1834 static void vga_update_display(void *opaque
)
1836 VGAState
*s
= (VGAState
*)opaque
;
1837 int full_update
, graphic_mode
;
1839 if (ds_get_bits_per_pixel(s
->ds
) == 0) {
1842 full_update
= s
->full_update
;
1844 if (!(s
->ar_index
& 0x20)) {
1845 graphic_mode
= GMODE_BLANK
;
1847 graphic_mode
= s
->gr
[6] & 1;
1849 if (graphic_mode
!= s
->graphic_mode
) {
1850 s
->graphic_mode
= graphic_mode
;
1853 switch(graphic_mode
) {
1855 vga_draw_text(s
, full_update
);
1858 vga_draw_graphic(s
, full_update
);
1862 vga_draw_blank(s
, full_update
);
1868 /* force a full display refresh */
1869 static void vga_invalidate_display(void *opaque
)
1871 VGAState
*s
= (VGAState
*)opaque
;
1876 void vga_reset(void *opaque
)
1878 VGAState
*s
= (VGAState
*) opaque
;
1884 s
->lfb_vram_mapped
= 0;
1888 memset(s
->sr
, '\0', sizeof(s
->sr
));
1890 memset(s
->gr
, '\0', sizeof(s
->gr
));
1892 memset(s
->ar
, '\0', sizeof(s
->ar
));
1893 s
->ar_flip_flop
= 0;
1895 memset(s
->cr
, '\0', sizeof(s
->cr
));
1901 s
->dac_sub_index
= 0;
1902 s
->dac_read_index
= 0;
1903 s
->dac_write_index
= 0;
1904 memset(s
->dac_cache
, '\0', sizeof(s
->dac_cache
));
1906 memset(s
->palette
, '\0', sizeof(s
->palette
));
1908 #ifdef CONFIG_BOCHS_VBE
1910 memset(s
->vbe_regs
, '\0', sizeof(s
->vbe_regs
));
1911 s
->vbe_regs
[VBE_DISPI_INDEX_ID
] = VBE_DISPI_ID0
;
1912 s
->vbe_start_addr
= 0;
1913 s
->vbe_line_offset
= 0;
1914 s
->vbe_bank_mask
= (s
->vram_size
>> 16) - 1;
1916 memset(s
->font_offsets
, '\0', sizeof(s
->font_offsets
));
1917 s
->graphic_mode
= -1; /* force full update */
1918 s
->shift_control
= 0;
1921 s
->line_compare
= 0;
1923 s
->plane_updated
= 0;
1928 s
->last_scr_width
= 0;
1929 s
->last_scr_height
= 0;
1930 s
->cursor_start
= 0;
1932 s
->cursor_offset
= 0;
1933 memset(s
->invalidated_y_table
, '\0', sizeof(s
->invalidated_y_table
));
1934 memset(s
->last_palette
, '\0', sizeof(s
->last_palette
));
1935 memset(s
->last_ch_attr
, '\0', sizeof(s
->last_ch_attr
));
1936 switch (vga_retrace_method
) {
1937 case VGA_RETRACE_DUMB
:
1939 case VGA_RETRACE_PRECISE
:
1940 memset(&s
->retrace_info
, 0, sizeof (s
->retrace_info
));
1945 #define TEXTMODE_X(x) ((x) % width)
1946 #define TEXTMODE_Y(x) ((x) / width)
1947 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1948 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1949 /* relay text rendering to the display driver
1950 * instead of doing a full vga_update_display() */
1951 static void vga_update_text(void *opaque
, console_ch_t
*chardata
)
1953 VGAState
*s
= (VGAState
*) opaque
;
1954 int graphic_mode
, i
, cursor_offset
, cursor_visible
;
1955 int cw
, cheight
, width
, height
, size
, c_min
, c_max
;
1957 console_ch_t
*dst
, val
;
1958 char msg_buffer
[80];
1959 int full_update
= 0;
1961 if (!(s
->ar_index
& 0x20)) {
1962 graphic_mode
= GMODE_BLANK
;
1964 graphic_mode
= s
->gr
[6] & 1;
1966 if (graphic_mode
!= s
->graphic_mode
) {
1967 s
->graphic_mode
= graphic_mode
;
1970 if (s
->last_width
== -1) {
1975 switch (graphic_mode
) {
1977 /* TODO: update palette */
1978 full_update
|= update_basic_params(s
);
1980 /* total width & height */
1981 cheight
= (s
->cr
[9] & 0x1f) + 1;
1983 if (!(s
->sr
[1] & 0x01))
1985 if (s
->sr
[1] & 0x08)
1986 cw
= 16; /* NOTE: no 18 pixel wide */
1987 width
= (s
->cr
[0x01] + 1);
1988 if (s
->cr
[0x06] == 100) {
1989 /* ugly hack for CGA 160x100x16 - explain me the logic */
1992 height
= s
->cr
[0x12] |
1993 ((s
->cr
[0x07] & 0x02) << 7) |
1994 ((s
->cr
[0x07] & 0x40) << 3);
1995 height
= (height
+ 1) / cheight
;
1998 size
= (height
* width
);
1999 if (size
> CH_ATTR_SIZE
) {
2003 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Text mode",
2008 if (width
!= s
->last_width
|| height
!= s
->last_height
||
2009 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
) {
2010 s
->last_scr_width
= width
* cw
;
2011 s
->last_scr_height
= height
* cheight
;
2012 s
->ds
->surface
->width
= width
;
2013 s
->ds
->surface
->height
= height
;
2015 s
->last_width
= width
;
2016 s
->last_height
= height
;
2017 s
->last_ch
= cheight
;
2022 /* Update "hardware" cursor */
2023 cursor_offset
= ((s
->cr
[0x0e] << 8) | s
->cr
[0x0f]) - s
->start_addr
;
2024 if (cursor_offset
!= s
->cursor_offset
||
2025 s
->cr
[0xa] != s
->cursor_start
||
2026 s
->cr
[0xb] != s
->cursor_end
|| full_update
) {
2027 cursor_visible
= !(s
->cr
[0xa] & 0x20);
2028 if (cursor_visible
&& cursor_offset
< size
&& cursor_offset
>= 0)
2030 TEXTMODE_X(cursor_offset
),
2031 TEXTMODE_Y(cursor_offset
));
2033 dpy_cursor(s
->ds
, -1, -1);
2034 s
->cursor_offset
= cursor_offset
;
2035 s
->cursor_start
= s
->cr
[0xa];
2036 s
->cursor_end
= s
->cr
[0xb];
2039 src
= (uint32_t *) s
->vram_ptr
+ s
->start_addr
;
2043 for (i
= 0; i
< size
; src
++, dst
++, i
++)
2044 console_write_ch(dst
, VMEM2CHTYPE(*src
));
2046 dpy_update(s
->ds
, 0, 0, width
, height
);
2050 for (i
= 0; i
< size
; src
++, dst
++, i
++) {
2051 console_write_ch(&val
, VMEM2CHTYPE(*src
));
2059 for (; i
< size
; src
++, dst
++, i
++) {
2060 console_write_ch(&val
, VMEM2CHTYPE(*src
));
2067 if (c_min
<= c_max
) {
2068 i
= TEXTMODE_Y(c_min
);
2069 dpy_update(s
->ds
, 0, i
, width
, TEXTMODE_Y(c_max
) - i
+ 1);
2078 s
->get_resolution(s
, &width
, &height
);
2079 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Graphic mode",
2087 snprintf(msg_buffer
, sizeof(msg_buffer
), "VGA Blank mode");
2091 /* Display a message */
2093 s
->last_height
= height
= 3;
2094 dpy_cursor(s
->ds
, -1, -1);
2095 s
->ds
->surface
->width
= s
->last_width
;
2096 s
->ds
->surface
->height
= height
;
2099 for (dst
= chardata
, i
= 0; i
< s
->last_width
* height
; i
++)
2100 console_write_ch(dst
++, ' ');
2102 size
= strlen(msg_buffer
);
2103 width
= (s
->last_width
- size
) / 2;
2104 dst
= chardata
+ s
->last_width
+ width
;
2105 for (i
= 0; i
< size
; i
++)
2106 console_write_ch(dst
++, 0x00200100 | msg_buffer
[i
]);
2108 dpy_update(s
->ds
, 0, 0, s
->last_width
, height
);
2111 static CPUReadMemoryFunc
*vga_mem_read
[3] = {
2117 static CPUWriteMemoryFunc
*vga_mem_write
[3] = {
2123 static void vga_save(QEMUFile
*f
, void *opaque
)
2125 VGAState
*s
= opaque
;
2129 pci_device_save(s
->pci_dev
, f
);
2131 qemu_put_be32s(f
, &s
->latch
);
2132 qemu_put_8s(f
, &s
->sr_index
);
2133 qemu_put_buffer(f
, s
->sr
, 8);
2134 qemu_put_8s(f
, &s
->gr_index
);
2135 qemu_put_buffer(f
, s
->gr
, 16);
2136 qemu_put_8s(f
, &s
->ar_index
);
2137 qemu_put_buffer(f
, s
->ar
, 21);
2138 qemu_put_be32(f
, s
->ar_flip_flop
);
2139 qemu_put_8s(f
, &s
->cr_index
);
2140 qemu_put_buffer(f
, s
->cr
, 256);
2141 qemu_put_8s(f
, &s
->msr
);
2142 qemu_put_8s(f
, &s
->fcr
);
2143 qemu_put_byte(f
, s
->st00
);
2144 qemu_put_8s(f
, &s
->st01
);
2146 qemu_put_8s(f
, &s
->dac_state
);
2147 qemu_put_8s(f
, &s
->dac_sub_index
);
2148 qemu_put_8s(f
, &s
->dac_read_index
);
2149 qemu_put_8s(f
, &s
->dac_write_index
);
2150 qemu_put_buffer(f
, s
->dac_cache
, 3);
2151 qemu_put_buffer(f
, s
->palette
, 768);
2153 qemu_put_be32(f
, s
->bank_offset
);
2154 #ifdef CONFIG_BOCHS_VBE
2155 qemu_put_byte(f
, 1);
2156 qemu_put_be16s(f
, &s
->vbe_index
);
2157 for(i
= 0; i
< VBE_DISPI_INDEX_NB
; i
++)
2158 qemu_put_be16s(f
, &s
->vbe_regs
[i
]);
2159 qemu_put_be32s(f
, &s
->vbe_start_addr
);
2160 qemu_put_be32s(f
, &s
->vbe_line_offset
);
2161 qemu_put_be32s(f
, &s
->vbe_bank_mask
);
2163 qemu_put_byte(f
, 0);
2167 static int vga_load(QEMUFile
*f
, void *opaque
, int version_id
)
2169 VGAState
*s
= opaque
;
2175 if (s
->pci_dev
&& version_id
>= 2) {
2176 ret
= pci_device_load(s
->pci_dev
, f
);
2181 qemu_get_be32s(f
, &s
->latch
);
2182 qemu_get_8s(f
, &s
->sr_index
);
2183 qemu_get_buffer(f
, s
->sr
, 8);
2184 qemu_get_8s(f
, &s
->gr_index
);
2185 qemu_get_buffer(f
, s
->gr
, 16);
2186 qemu_get_8s(f
, &s
->ar_index
);
2187 qemu_get_buffer(f
, s
->ar
, 21);
2188 s
->ar_flip_flop
=qemu_get_be32(f
);
2189 qemu_get_8s(f
, &s
->cr_index
);
2190 qemu_get_buffer(f
, s
->cr
, 256);
2191 qemu_get_8s(f
, &s
->msr
);
2192 qemu_get_8s(f
, &s
->fcr
);
2193 qemu_get_8s(f
, &s
->st00
);
2194 qemu_get_8s(f
, &s
->st01
);
2196 qemu_get_8s(f
, &s
->dac_state
);
2197 qemu_get_8s(f
, &s
->dac_sub_index
);
2198 qemu_get_8s(f
, &s
->dac_read_index
);
2199 qemu_get_8s(f
, &s
->dac_write_index
);
2200 qemu_get_buffer(f
, s
->dac_cache
, 3);
2201 qemu_get_buffer(f
, s
->palette
, 768);
2203 s
->bank_offset
=qemu_get_be32(f
);
2204 is_vbe
= qemu_get_byte(f
);
2205 #ifdef CONFIG_BOCHS_VBE
2208 qemu_get_be16s(f
, &s
->vbe_index
);
2209 for(i
= 0; i
< VBE_DISPI_INDEX_NB
; i
++)
2210 qemu_get_be16s(f
, &s
->vbe_regs
[i
]);
2211 qemu_get_be32s(f
, &s
->vbe_start_addr
);
2212 qemu_get_be32s(f
, &s
->vbe_line_offset
);
2213 qemu_get_be32s(f
, &s
->vbe_bank_mask
);
2220 s
->graphic_mode
= -1;
2224 typedef struct PCIVGAState
{
2229 void vga_dirty_log_start(VGAState
*s
)
2231 if (kvm_enabled() && s
->map_addr
)
2232 kvm_log_start(s
->map_addr
, s
->map_end
- s
->map_addr
);
2234 if (kvm_enabled() && s
->lfb_vram_mapped
) {
2235 kvm_log_start(isa_mem_base
+ 0xa0000, 0x8000);
2236 kvm_log_start(isa_mem_base
+ 0xa8000, 0x8000);
2240 static void vga_map(PCIDevice
*pci_dev
, int region_num
,
2241 uint32_t addr
, uint32_t size
, int type
)
2243 PCIVGAState
*d
= (PCIVGAState
*)pci_dev
;
2244 VGAState
*s
= &d
->vga_state
;
2245 if (region_num
== PCI_ROM_SLOT
) {
2246 cpu_register_physical_memory(addr
, s
->bios_size
, s
->bios_offset
);
2248 cpu_register_physical_memory(addr
, s
->vram_size
, s
->vram_offset
);
2250 s
->map_end
= addr
+ s
->vram_size
;
2251 vga_dirty_log_start(s
);
2255 void vga_common_init(VGAState
*s
, int vga_ram_size
)
2259 for(i
= 0;i
< 256; i
++) {
2261 for(j
= 0; j
< 8; j
++) {
2262 v
|= ((i
>> j
) & 1) << (j
* 4);
2267 for(j
= 0; j
< 4; j
++) {
2268 v
|= ((i
>> (2 * j
)) & 3) << (j
* 4);
2272 for(i
= 0; i
< 16; i
++) {
2274 for(j
= 0; j
< 4; j
++) {
2277 v
|= b
<< (2 * j
+ 1);
2282 s
->vram_offset
= qemu_ram_alloc(vga_ram_size
);
2283 s
->vram_ptr
= qemu_get_ram_ptr(s
->vram_offset
);
2284 s
->vram_size
= vga_ram_size
;
2285 s
->get_bpp
= vga_get_bpp
;
2286 s
->get_offsets
= vga_get_offsets
;
2287 s
->get_resolution
= vga_get_resolution
;
2288 s
->update
= vga_update_display
;
2289 s
->invalidate
= vga_invalidate_display
;
2290 s
->screen_dump
= vga_screen_dump
;
2291 s
->text_update
= vga_update_text
;
2292 switch (vga_retrace_method
) {
2293 case VGA_RETRACE_DUMB
:
2294 s
->retrace
= vga_dumb_retrace
;
2295 s
->update_retrace_info
= vga_dumb_update_retrace_info
;
2298 case VGA_RETRACE_PRECISE
:
2299 s
->retrace
= vga_precise_retrace
;
2300 s
->update_retrace_info
= vga_precise_update_retrace_info
;
2306 /* used by both ISA and PCI */
2307 void vga_init(VGAState
*s
)
2311 qemu_register_reset(vga_reset
, s
);
2312 register_savevm("vga", 0, 2, vga_save
, vga_load
, s
);
2314 register_ioport_write(0x3c0, 16, 1, vga_ioport_write
, s
);
2316 register_ioport_write(0x3b4, 2, 1, vga_ioport_write
, s
);
2317 register_ioport_write(0x3d4, 2, 1, vga_ioport_write
, s
);
2318 register_ioport_write(0x3ba, 1, 1, vga_ioport_write
, s
);
2319 register_ioport_write(0x3da, 1, 1, vga_ioport_write
, s
);
2321 register_ioport_read(0x3c0, 16, 1, vga_ioport_read
, s
);
2323 register_ioport_read(0x3b4, 2, 1, vga_ioport_read
, s
);
2324 register_ioport_read(0x3d4, 2, 1, vga_ioport_read
, s
);
2325 register_ioport_read(0x3ba, 1, 1, vga_ioport_read
, s
);
2326 register_ioport_read(0x3da, 1, 1, vga_ioport_read
, s
);
2329 #ifdef CONFIG_BOCHS_VBE
2330 #if defined (TARGET_I386)
2331 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index
, s
);
2332 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data
, s
);
2334 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index
, s
);
2335 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data
, s
);
2337 /* old Bochs IO ports */
2338 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index
, s
);
2339 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data
, s
);
2341 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index
, s
);
2342 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data
, s
);
2344 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index
, s
);
2345 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data
, s
);
2347 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index
, s
);
2348 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data
, s
);
2350 #endif /* CONFIG_BOCHS_VBE */
2352 vga_io_memory
= cpu_register_io_memory(vga_mem_read
, vga_mem_write
, s
);
2353 cpu_register_physical_memory(isa_mem_base
+ 0x000a0000, 0x20000,
2355 qemu_register_coalesced_mmio(isa_mem_base
+ 0x000a0000, 0x20000);
2358 /* Memory mapped interface */
2359 static uint32_t vga_mm_readb (void *opaque
, target_phys_addr_t addr
)
2361 VGAState
*s
= opaque
;
2363 return vga_ioport_read(s
, addr
>> s
->it_shift
) & 0xff;
2366 static void vga_mm_writeb (void *opaque
,
2367 target_phys_addr_t addr
, uint32_t value
)
2369 VGAState
*s
= opaque
;
2371 vga_ioport_write(s
, addr
>> s
->it_shift
, value
& 0xff);
2374 static uint32_t vga_mm_readw (void *opaque
, target_phys_addr_t addr
)
2376 VGAState
*s
= opaque
;
2378 return vga_ioport_read(s
, addr
>> s
->it_shift
) & 0xffff;
2381 static void vga_mm_writew (void *opaque
,
2382 target_phys_addr_t addr
, uint32_t value
)
2384 VGAState
*s
= opaque
;
2386 vga_ioport_write(s
, addr
>> s
->it_shift
, value
& 0xffff);
2389 static uint32_t vga_mm_readl (void *opaque
, target_phys_addr_t addr
)
2391 VGAState
*s
= opaque
;
2393 return vga_ioport_read(s
, addr
>> s
->it_shift
);
2396 static void vga_mm_writel (void *opaque
,
2397 target_phys_addr_t addr
, uint32_t value
)
2399 VGAState
*s
= opaque
;
2401 vga_ioport_write(s
, addr
>> s
->it_shift
, value
);
2404 static CPUReadMemoryFunc
*vga_mm_read_ctrl
[] = {
2410 static CPUWriteMemoryFunc
*vga_mm_write_ctrl
[] = {
2416 static void vga_mm_init(VGAState
*s
, target_phys_addr_t vram_base
,
2417 target_phys_addr_t ctrl_base
, int it_shift
)
2419 int s_ioport_ctrl
, vga_io_memory
;
2421 s
->it_shift
= it_shift
;
2422 s_ioport_ctrl
= cpu_register_io_memory(vga_mm_read_ctrl
, vga_mm_write_ctrl
, s
);
2423 vga_io_memory
= cpu_register_io_memory(vga_mem_read
, vga_mem_write
, s
);
2425 register_savevm("vga", 0, 2, vga_save
, vga_load
, s
);
2427 cpu_register_physical_memory(ctrl_base
, 0x100000, s_ioport_ctrl
);
2429 cpu_register_physical_memory(vram_base
+ 0x000a0000, 0x20000, vga_io_memory
);
2430 qemu_register_coalesced_mmio(vram_base
+ 0x000a0000, 0x20000);
2433 int isa_vga_init(void)
2437 s
= qemu_mallocz(sizeof(VGAState
));
2439 vga_common_init(s
, VGA_RAM_SIZE
);
2442 s
->ds
= graphic_console_init(s
->update
, s
->invalidate
,
2443 s
->screen_dump
, s
->text_update
, s
);
2445 #ifdef CONFIG_BOCHS_VBE
2446 /* XXX: use optimized standard vga accesses */
2447 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS
,
2448 VGA_RAM_SIZE
, s
->vram_offset
);
2453 int isa_vga_mm_init(target_phys_addr_t vram_base
,
2454 target_phys_addr_t ctrl_base
, int it_shift
)
2458 s
= qemu_mallocz(sizeof(VGAState
));
2460 vga_common_init(s
, VGA_RAM_SIZE
);
2461 vga_mm_init(s
, vram_base
, ctrl_base
, it_shift
);
2463 s
->ds
= graphic_console_init(s
->update
, s
->invalidate
,
2464 s
->screen_dump
, s
->text_update
, s
);
2466 #ifdef CONFIG_BOCHS_VBE
2467 /* XXX: use optimized standard vga accesses */
2468 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS
,
2469 VGA_RAM_SIZE
, s
->vram_offset
);
2474 static void pci_vga_write_config(PCIDevice
*d
,
2475 uint32_t address
, uint32_t val
, int len
)
2477 PCIVGAState
*pvs
= container_of(d
, PCIVGAState
, dev
);
2478 VGAState
*s
= &pvs
->vga_state
;
2480 pci_default_write_config(d
, address
, val
, len
);
2481 if (s
->map_addr
&& pvs
->dev
.io_regions
[0].addr
== -1)
2485 static void pci_vga_initfn(PCIDevice
*dev
)
2487 PCIVGAState
*d
= DO_UPCAST(PCIVGAState
, dev
, dev
);
2488 VGAState
*s
= &d
->vga_state
;
2489 uint8_t *pci_conf
= d
->dev
.config
;
2491 // vga + console init
2492 vga_common_init(s
, VGA_RAM_SIZE
);
2494 s
->pci_dev
= &d
->dev
;
2495 s
->ds
= graphic_console_init(s
->update
, s
->invalidate
,
2496 s
->screen_dump
, s
->text_update
, s
);
2498 // dummy VGA (same as Bochs ID)
2499 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_QEMU
);
2500 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_QEMU_VGA
);
2501 pci_config_set_class(pci_conf
, PCI_CLASS_DISPLAY_VGA
);
2502 pci_conf
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
2504 /* XXX: VGA_RAM_SIZE must be a power of two */
2505 pci_register_bar(&d
->dev
, 0, VGA_RAM_SIZE
,
2506 PCI_ADDRESS_SPACE_MEM_PREFETCH
, vga_map
);
2509 unsigned int bios_total_size
;
2510 /* must be a power of two */
2511 bios_total_size
= 1;
2512 while (bios_total_size
< s
->bios_size
)
2513 bios_total_size
<<= 1;
2514 pci_register_bar(&d
->dev
, PCI_ROM_SLOT
, bios_total_size
,
2515 PCI_ADDRESS_SPACE_MEM_PREFETCH
, vga_map
);
2519 int pci_vga_init(PCIBus
*bus
,
2520 unsigned long vga_bios_offset
, int vga_bios_size
)
2524 dev
= pci_create("VGA", NULL
);
2525 qdev_prop_set_uint32(&dev
->qdev
, "bios-offset", vga_bios_offset
);
2526 qdev_prop_set_uint32(&dev
->qdev
, "bios-size", vga_bios_offset
);
2527 qdev_init(&dev
->qdev
);
2532 static PCIDeviceInfo vga_info
= {
2534 .qdev
.size
= sizeof(PCIVGAState
),
2535 .init
= pci_vga_initfn
,
2536 .config_write
= pci_vga_write_config
,
2537 .qdev
.props
= (Property
[]) {
2538 DEFINE_PROP_HEX32("bios-offset", PCIVGAState
, vga_state
.bios_offset
, 0),
2539 DEFINE_PROP_HEX32("bios-size", PCIVGAState
, vga_state
.bios_size
, 0),
2540 DEFINE_PROP_END_OF_LIST(),
2544 static void vga_register(void)
2546 pci_qdev_register(&vga_info
);
2548 device_init(vga_register
);
2550 /********************************************************/
2551 /* vga screen dump */
2553 static void vga_save_dpy_update(DisplayState
*ds
,
2554 int x
, int y
, int w
, int h
)
2556 if (screen_dump_filename
) {
2557 ppm_save(screen_dump_filename
, ds
->surface
);
2558 screen_dump_filename
= NULL
;
2562 static void vga_save_dpy_resize(DisplayState
*s
)
2566 static void vga_save_dpy_refresh(DisplayState
*s
)
2570 int ppm_save(const char *filename
, struct DisplaySurface
*ds
)
2578 f
= fopen(filename
, "wb");
2581 fprintf(f
, "P6\n%d %d\n%d\n",
2582 ds
->width
, ds
->height
, 255);
2584 for(y
= 0; y
< ds
->height
; y
++) {
2586 for(x
= 0; x
< ds
->width
; x
++) {
2587 if (ds
->pf
.bits_per_pixel
== 32)
2590 v
= (uint32_t) (*(uint16_t *)d
);
2591 r
= ((v
>> ds
->pf
.rshift
) & ds
->pf
.rmax
) * 256 /
2593 g
= ((v
>> ds
->pf
.gshift
) & ds
->pf
.gmax
) * 256 /
2595 b
= ((v
>> ds
->pf
.bshift
) & ds
->pf
.bmax
) * 256 /
2600 d
+= ds
->pf
.bytes_per_pixel
;
2608 static DisplayChangeListener
* vga_screen_dump_init(DisplayState
*ds
)
2610 DisplayChangeListener
*dcl
;
2612 dcl
= qemu_mallocz(sizeof(DisplayChangeListener
));
2613 dcl
->dpy_update
= vga_save_dpy_update
;
2614 dcl
->dpy_resize
= vga_save_dpy_resize
;
2615 dcl
->dpy_refresh
= vga_save_dpy_refresh
;
2616 register_displaychangelistener(ds
, dcl
);
2620 /* save the vga display in a PPM image even if no display is
2622 static void vga_screen_dump(void *opaque
, const char *filename
)
2624 VGAState
*s
= (VGAState
*)opaque
;
2626 if (!screen_dump_dcl
)
2627 screen_dump_dcl
= vga_screen_dump_init(s
->ds
);
2629 screen_dump_filename
= (char *)filename
;
2630 vga_invalidate_display(s
);