hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sun4m.h"
  26 #include "monitor.h"
  27 #include "sysbus.h"
  28
  29 //#define DEBUG_IRQ_COUNT
  30 //#define DEBUG_IRQ
  31
  32 #ifdef DEBUG_IRQ
  33 #define DPRINTF(fmt, ...)                                       \
  34     do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define DPRINTF(fmt, ...)
  37 #endif
  38
  39 /*
  40  * Registers of interrupt controller in sun4m.
  41  *
  42  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  43  * produced as NCR89C105. See
  44  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  45  *
  46  * There is a system master controller and one for each cpu.
  47  *
  48  */
  49
  50 #define MAX_CPUS 16
  51 #define MAX_PILS 16
  52
  53 struct SLAVIO_INTCTLState;
  54
  55 typedef struct SLAVIO_CPUINTCTLState {
  56     uint32_t intreg_pending;
  57     struct SLAVIO_INTCTLState *master;
  58     uint32_t cpu;
  59 } SLAVIO_CPUINTCTLState;
  60
  61 typedef struct SLAVIO_INTCTLState {
  62     SysBusDevice busdev;
  63     uint32_t intregm_pending;
  64     uint32_t intregm_disabled;
  65     uint32_t target_cpu;
  66 #ifdef DEBUG_IRQ_COUNT
  67     uint64_t irq_count[32];
  68 #endif
  69     qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
  70     uint32_t cputimer_lbit, cputimer_mbit;
  71     uint32_t cputimer_bit;
  72     uint32_t pil_out[MAX_CPUS];
  73     SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
  74 } SLAVIO_INTCTLState;
  75
  76 #define INTCTL_MAXADDR 0xf
  77 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  78 #define INTCTLM_SIZE 0x14
  79 #define MASTER_IRQ_MASK ~0x0fa2007f
  80 #define MASTER_DISABLE 0x80000000
  81 #define CPU_SOFTIRQ_MASK 0xfffe0000
  82 #define CPU_IRQ_INT15_IN 0x0004000
  83 #define CPU_IRQ_INT15_MASK 0x80000000
  84
  85 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
  86
  87 // per-cpu interrupt controller
  88 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  89 {
  90     SLAVIO_CPUINTCTLState *s = opaque;
  91     uint32_t saddr, ret;
  92
  93     saddr = addr >> 2;
  94     switch (saddr) {
  95     case 0:
  96         ret = s->intreg_pending;
  97         break;
  98     default:
  99         ret = 0;
 100         break;
 101     }
 102     DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
 103
 104     return ret;
 105 }
 106
 107 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
 108                                      uint32_t val)
 109 {
 110     SLAVIO_CPUINTCTLState *s = opaque;
 111     uint32_t saddr;
 112
 113     saddr = addr >> 2;
 114     DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
 115     switch (saddr) {
 116     case 1: // clear pending softints
 117         if (val & CPU_IRQ_INT15_IN)
 118             val |= CPU_IRQ_INT15_MASK;
 119         val &= CPU_SOFTIRQ_MASK;
 120         s->intreg_pending &= ~val;
 121         slavio_check_interrupts(s->master, 1);
 122         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
 123                 s->intreg_pending);
 124         break;
 125     case 2: // set softint
 126         val &= CPU_SOFTIRQ_MASK;
 127         s->intreg_pending |= val;
 128         slavio_check_interrupts(s->master, 1);
 129         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
 130                 s->intreg_pending);
 131         break;
 132     default:
 133         break;
 134     }
 135 }
 136
 137 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
 138     NULL,
 139     NULL,
 140     slavio_intctl_mem_readl,
 141 };
 142
 143 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 144     NULL,
 145     NULL,
 146     slavio_intctl_mem_writel,
 147 };
 148
 149 // master system interrupt controller
 150 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 151 {
 152     SLAVIO_INTCTLState *s = opaque;
 153     uint32_t saddr, ret;
 154
 155     saddr = addr >> 2;
 156     switch (saddr) {
 157     case 0:
 158         ret = s->intregm_pending & ~MASTER_DISABLE;
 159         break;
 160     case 1:
 161         ret = s->intregm_disabled & MASTER_IRQ_MASK;
 162         break;
 163     case 4:
 164         ret = s->target_cpu;
 165         break;
 166     default:
 167         ret = 0;
 168         break;
 169     }
 170     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
 171
 172     return ret;
 173 }
 174
 175 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
 176                                       uint32_t val)
 177 {
 178     SLAVIO_INTCTLState *s = opaque;
 179     uint32_t saddr;
 180
 181     saddr = addr >> 2;
 182     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
 183     switch (saddr) {
 184     case 2: // clear (enable)
 185         // Force clear unused bits
 186         val &= MASTER_IRQ_MASK;
 187         s->intregm_disabled &= ~val;
 188         DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
 189                 s->intregm_disabled);
 190         slavio_check_interrupts(s, 1);
 191         break;
 192     case 3: // set (disable, clear pending)
 193         // Force clear unused bits
 194         val &= MASTER_IRQ_MASK;
 195         s->intregm_disabled |= val;
 196         s->intregm_pending &= ~val;
 197         slavio_check_interrupts(s, 1);
 198         DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
 199                 s->intregm_disabled);
 200         break;
 201     case 4:
 202         s->target_cpu = val & (MAX_CPUS - 1);
 203         slavio_check_interrupts(s, 1);
 204         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 205         break;
 206     default:
 207         break;
 208     }
 209 }
 210
 211 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
 212     NULL,
 213     NULL,
 214     slavio_intctlm_mem_readl,
 215 };
 216
 217 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
 218     NULL,
 219     NULL,
 220     slavio_intctlm_mem_writel,
 221 };
 222
 223 void slavio_pic_info(Monitor *mon, DeviceState *dev)
 224 {
 225     SysBusDevice *sd;
 226     SLAVIO_INTCTLState *s;
 227     int i;
 228
 229     sd = sysbus_from_qdev(dev);
 230     s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
 231     for (i = 0; i < MAX_CPUS; i++) {
 232         monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
 233                        s->slaves[i].intreg_pending);
 234     }
 235     monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
 236                    s->intregm_pending, s->intregm_disabled);
 237 }
 238
 239 void slavio_irq_info(Monitor *mon, DeviceState *dev)
 240 {
 241 #ifndef DEBUG_IRQ_COUNT
 242     monitor_printf(mon, "irq statistic code not compiled.\n");
 243 #else
 244     SysBusDevice *sd;
 245     SLAVIO_INTCTLState *s;
 246     int i;
 247     int64_t count;
 248
 249     sd = sysbus_from_qdev(dev);
 250     s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
 251     monitor_printf(mon, "IRQ statistics:\n");
 252     for (i = 0; i < 32; i++) {
 253         count = s->irq_count[i];
 254         if (count > 0)
 255             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 256     }
 257 #endif
 258 }
 259
 260 static const uint32_t intbit_to_level[] = {
 261     2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
 262     6, 0, 4, 10, 8, 0, 11, 0,   0, 0, 0, 0, 15, 0, 15, 0,
 263 };
 264
 265 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
 266 {
 267     uint32_t pending = s->intregm_pending, pil_pending;
 268     unsigned int i, j;
 269
 270     pending &= ~s->intregm_disabled;
 271
 272     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
 273     for (i = 0; i < MAX_CPUS; i++) {
 274         pil_pending = 0;
 275         if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
 276             (i == s->target_cpu)) {
 277             for (j = 0; j < 32; j++) {
 278                 if (pending & (1 << j))
 279                     pil_pending |= 1 << intbit_to_level[j];
 280             }
 281         }
 282         pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
 283
 284         if (set_irqs) {
 285             for (j = 0; j < MAX_PILS; j++) {
 286                 if (pil_pending & (1 << j)) {
 287                     if (!(s->pil_out[i] & (1 << j))) {
 288                         qemu_irq_raise(s->cpu_irqs[i][j]);
 289                     }
 290                 } else {
 291                     if (s->pil_out[i] & (1 << j)) {
 292                         qemu_irq_lower(s->cpu_irqs[i][j]);
 293                     }
 294                 }
 295             }
 296         }
 297         s->pil_out[i] = pil_pending;
 298     }
 299 }
 300
 301 /*
 302  * "irq" here is the bit number in the system interrupt register to
 303  * separate serial and keyboard interrupts sharing a level.
 304  */
 305 static void slavio_set_irq(void *opaque, int irq, int level)
 306 {
 307     SLAVIO_INTCTLState *s = opaque;
 308     uint32_t mask = 1 << irq;
 309     uint32_t pil = intbit_to_level[irq];
 310
 311     DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
 312             level);
 313     if (pil > 0) {
 314         if (level) {
 315 #ifdef DEBUG_IRQ_COUNT
 316             s->irq_count[pil]++;
 317 #endif
 318             s->intregm_pending |= mask;
 319             s->slaves[s->target_cpu].intreg_pending |= 1 << pil;
 320         } else {
 321             s->intregm_pending &= ~mask;
 322             s->slaves[s->target_cpu].intreg_pending &= ~(1 << pil);
 323         }
 324         slavio_check_interrupts(s, 1);
 325     }
 326 }
 327
 328 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 329 {
 330     SLAVIO_INTCTLState *s = opaque;
 331
 332     DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
 333
 334     if (level) {
 335         s->intregm_pending |= s->cputimer_mbit;
 336         s->slaves[cpu].intreg_pending |= s->cputimer_lbit;
 337     } else {
 338         s->intregm_pending &= ~s->cputimer_mbit;
 339         s->slaves[cpu].intreg_pending &= ~s->cputimer_lbit;
 340     }
 341
 342     slavio_check_interrupts(s, 1);
 343 }
 344
 345 static void slavio_set_irq_all(void *opaque, int irq, int level)
 346 {
 347     if (irq < 32) {
 348         slavio_set_irq(opaque, irq, level);
 349     } else {
 350         slavio_set_timer_irq_cpu(opaque, irq - 32, level);
 351     }
 352 }
 353
 354 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 355 {
 356     SLAVIO_INTCTLState *s = opaque;
 357     int i;
 358
 359     for (i = 0; i < MAX_CPUS; i++) {
 360         qemu_put_be32s(f, &s->slaves[i].intreg_pending);
 361     }
 362     qemu_put_be32s(f, &s->intregm_pending);
 363     qemu_put_be32s(f, &s->intregm_disabled);
 364     qemu_put_be32s(f, &s->target_cpu);
 365 }
 366
 367 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
 368 {
 369     SLAVIO_INTCTLState *s = opaque;
 370     int i;
 371
 372     if (version_id != 1)
 373         return -EINVAL;
 374
 375     for (i = 0; i < MAX_CPUS; i++) {
 376         qemu_get_be32s(f, &s->slaves[i].intreg_pending);
 377     }
 378     qemu_get_be32s(f, &s->intregm_pending);
 379     qemu_get_be32s(f, &s->intregm_disabled);
 380     qemu_get_be32s(f, &s->target_cpu);
 381     slavio_check_interrupts(s, 0);
 382     return 0;
 383 }
 384
 385 static void slavio_intctl_reset(void *opaque)
 386 {
 387     SLAVIO_INTCTLState *s = opaque;
 388     int i;
 389
 390     for (i = 0; i < MAX_CPUS; i++) {
 391         s->slaves[i].intreg_pending = 0;
 392     }
 393     s->intregm_disabled = ~MASTER_IRQ_MASK;
 394     s->intregm_pending = 0;
 395     s->target_cpu = 0;
 396     slavio_check_interrupts(s, 0);
 397 }
 398
 399 static void slavio_intctl_init1(SysBusDevice *dev)
 400 {
 401     SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
 402     int io_memory;
 403     unsigned int i, j;
 404
 405     qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
 406     io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
 407                                        slavio_intctlm_mem_write, s);
 408     sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
 409     s->cputimer_mbit = 1 << s->cputimer_bit;
 410     s->cputimer_lbit = 1 << intbit_to_level[s->cputimer_bit];
 411
 412     for (i = 0; i < MAX_CPUS; i++) {
 413         for (j = 0; j < MAX_PILS; j++) {
 414             sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
 415         }
 416         io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
 417                                            slavio_intctl_mem_write,
 418                                            &s->slaves[i]);
 419         sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
 420         s->slaves[i].cpu = i;
 421         s->slaves[i].master = s;
 422     }
 423     register_savevm("slavio_intctl", -1, 1, slavio_intctl_save,
 424                     slavio_intctl_load, s);
 425     qemu_register_reset(slavio_intctl_reset, s);
 426     slavio_intctl_reset(s);
 427 }
 428
 429 static SysBusDeviceInfo slavio_intctl_info = {
 430     .init = slavio_intctl_init1,
 431     .qdev.name  = "slavio_intctl",
 432     .qdev.size  = sizeof(SLAVIO_INTCTLState),
 433     .qdev.props = (Property[]) {
 434         DEFINE_PROP_UINT32("cputimer_bit", SLAVIO_INTCTLState, cputimer_bit, 0),
 435         DEFINE_PROP_END_OF_LIST(),
 436     }
 437 };
 438
 439 static void slavio_intctl_register_devices(void)
 440 {
 441     sysbus_register_withprop(&slavio_intctl_info);
 442 }
 443
 444 device_init(slavio_intctl_register_devices)