hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "ppc.h"
  33 #include "boards.h"
  34 #include "qemu-log.h"
  35
  36 //#define HARD_DEBUG_PPC_IO
  37 //#define DEBUG_PPC_IO
  38
  39 /* SMP is not enabled, for now */
  40 #define MAX_CPUS 1
  41
  42 #define MAX_IDE_BUS 2
  43
  44 #define BIOS_SIZE (1024 * 1024)
  45 #define BIOS_FILENAME "ppc_rom.bin"
  46 #define KERNEL_LOAD_ADDR 0x01000000
  47 #define INITRD_LOAD_ADDR 0x01800000
  48
  49 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  50 #define DEBUG_PPC_IO
  51 #endif
  52
  53 #if defined (HARD_DEBUG_PPC_IO)
  54 #define PPC_IO_DPRINTF(fmt, ...)                         \
  55 do {                                                     \
  56     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  57         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  58     } else {                                             \
  59         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  60     }                                                    \
  61 } while (0)
  62 #elif defined (DEBUG_PPC_IO)
  63 #define PPC_IO_DPRINTF(fmt, ...) \
  64 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  65 #else
  66 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  67 #endif
  68
  69 /* Constants for devices init */
  70 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  71 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  72 static const int ide_irq[2] = { 13, 13 };
  73
  74 #define NE2000_NB_MAX 6
  75
  76 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  77 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  78
  79 //static PITState *pit;
  80
  81 /* ISA IO ports bridge */
  82 #define PPC_IO_BASE 0x80000000
  83
  84 #if 0
  85 /* Speaker port 0x61 */
  86 static int speaker_data_on;
  87 static int dummy_refresh_clock;
  88 #endif
  89
  90 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  91 {
  92 #if 0
  93     speaker_data_on = (val >> 1) & 1;
  94     pit_set_gate(pit, 2, val & 1);
  95 #endif
  96 }
  97
  98 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
  99 {
 100 #if 0
 101     int out;
 102     out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
 103     dummy_refresh_clock ^= 1;
 104     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
 105         (dummy_refresh_clock << 4);
 106 #endif
 107     return 0;
 108 }
 109
 110 /* PCI intack register */
 111 /* Read-only register (?) */
 112 static void _PPC_intack_write (void *opaque,
 113                                target_phys_addr_t addr, uint32_t value)
 114 {
 115 #if 0
 116     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 117            value);
 118 #endif
 119 }
 120
 121 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
 122 {
 123     uint32_t retval = 0;
 124
 125     if ((addr & 0xf) == 0)
 126         retval = pic_intack_read(isa_pic);
 127 #if 0
 128     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 129            retval);
 130 #endif
 131
 132     return retval;
 133 }
 134
 135 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 136 {
 137     return _PPC_intack_read(addr);
 138 }
 139
 140 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 141 {
 142 #ifdef TARGET_WORDS_BIGENDIAN
 143     return bswap16(_PPC_intack_read(addr));
 144 #else
 145     return _PPC_intack_read(addr);
 146 #endif
 147 }
 148
 149 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 150 {
 151 #ifdef TARGET_WORDS_BIGENDIAN
 152     return bswap32(_PPC_intack_read(addr));
 153 #else
 154     return _PPC_intack_read(addr);
 155 #endif
 156 }
 157
 158 static CPUWriteMemoryFunc *PPC_intack_write[] = {
 159     &_PPC_intack_write,
 160     &_PPC_intack_write,
 161     &_PPC_intack_write,
 162 };
 163
 164 static CPUReadMemoryFunc *PPC_intack_read[] = {
 165     &PPC_intack_readb,
 166     &PPC_intack_readw,
 167     &PPC_intack_readl,
 168 };
 169
 170 /* PowerPC control and status registers */
 171 #if 0 // Not used
 172 static struct {
 173     /* IDs */
 174     uint32_t veni_devi;
 175     uint32_t revi;
 176     /* Control and status */
 177     uint32_t gcsr;
 178     uint32_t xcfr;
 179     uint32_t ct32;
 180     uint32_t mcsr;
 181     /* General purpose registers */
 182     uint32_t gprg[6];
 183     /* Exceptions */
 184     uint32_t feen;
 185     uint32_t fest;
 186     uint32_t fema;
 187     uint32_t fecl;
 188     uint32_t eeen;
 189     uint32_t eest;
 190     uint32_t eecl;
 191     uint32_t eeint;
 192     uint32_t eemck0;
 193     uint32_t eemck1;
 194     /* Error diagnostic */
 195 } XCSR;
 196
 197 static void PPC_XCSR_writeb (void *opaque,
 198                              target_phys_addr_t addr, uint32_t value)
 199 {
 200     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 201            value);
 202 }
 203
 204 static void PPC_XCSR_writew (void *opaque,
 205                              target_phys_addr_t addr, uint32_t value)
 206 {
 207 #ifdef TARGET_WORDS_BIGENDIAN
 208     value = bswap16(value);
 209 #endif
 210     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 211            value);
 212 }
 213
 214 static void PPC_XCSR_writel (void *opaque,
 215                              target_phys_addr_t addr, uint32_t value)
 216 {
 217 #ifdef TARGET_WORDS_BIGENDIAN
 218     value = bswap32(value);
 219 #endif
 220     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 221            value);
 222 }
 223
 224 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 225 {
 226     uint32_t retval = 0;
 227
 228     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 229            retval);
 230
 231     return retval;
 232 }
 233
 234 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 235 {
 236     uint32_t retval = 0;
 237
 238     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 239            retval);
 240 #ifdef TARGET_WORDS_BIGENDIAN
 241     retval = bswap16(retval);
 242 #endif
 243
 244     return retval;
 245 }
 246
 247 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 248 {
 249     uint32_t retval = 0;
 250
 251     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 252            retval);
 253 #ifdef TARGET_WORDS_BIGENDIAN
 254     retval = bswap32(retval);
 255 #endif
 256
 257     return retval;
 258 }
 259
 260 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
 261     &PPC_XCSR_writeb,
 262     &PPC_XCSR_writew,
 263     &PPC_XCSR_writel,
 264 };
 265
 266 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
 267     &PPC_XCSR_readb,
 268     &PPC_XCSR_readw,
 269     &PPC_XCSR_readl,
 270 };
 271 #endif
 272
 273 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 274 typedef struct sysctrl_t {
 275     qemu_irq reset_irq;
 276     m48t59_t *nvram;
 277     uint8_t state;
 278     uint8_t syscontrol;
 279     uint8_t fake_io[2];
 280     int contiguous_map;
 281     int endian;
 282 } sysctrl_t;
 283
 284 enum {
 285     STATE_HARDFILE = 0x01,
 286 };
 287
 288 static sysctrl_t *sysctrl;
 289
 290 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 291 {
 292     sysctrl_t *sysctrl = opaque;
 293
 294     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 295                    val);
 296     sysctrl->fake_io[addr - 0x0398] = val;
 297 }
 298
 299 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 300 {
 301     sysctrl_t *sysctrl = opaque;
 302
 303     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 304                    sysctrl->fake_io[addr - 0x0398]);
 305     return sysctrl->fake_io[addr - 0x0398];
 306 }
 307
 308 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 309 {
 310     sysctrl_t *sysctrl = opaque;
 311
 312     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 313                    addr - PPC_IO_BASE, val);
 314     switch (addr) {
 315     case 0x0092:
 316         /* Special port 92 */
 317         /* Check soft reset asked */
 318         if (val & 0x01) {
 319             qemu_irq_raise(sysctrl->reset_irq);
 320         } else {
 321             qemu_irq_lower(sysctrl->reset_irq);
 322         }
 323         /* Check LE mode */
 324         if (val & 0x02) {
 325             sysctrl->endian = 1;
 326         } else {
 327             sysctrl->endian = 0;
 328         }
 329         break;
 330     case 0x0800:
 331         /* Motorola CPU configuration register : read-only */
 332         break;
 333     case 0x0802:
 334         /* Motorola base module feature register : read-only */
 335         break;
 336     case 0x0803:
 337         /* Motorola base module status register : read-only */
 338         break;
 339     case 0x0808:
 340         /* Hardfile light register */
 341         if (val & 1)
 342             sysctrl->state |= STATE_HARDFILE;
 343         else
 344             sysctrl->state &= ~STATE_HARDFILE;
 345         break;
 346     case 0x0810:
 347         /* Password protect 1 register */
 348         if (sysctrl->nvram != NULL)
 349             m48t59_toggle_lock(sysctrl->nvram, 1);
 350         break;
 351     case 0x0812:
 352         /* Password protect 2 register */
 353         if (sysctrl->nvram != NULL)
 354             m48t59_toggle_lock(sysctrl->nvram, 2);
 355         break;
 356     case 0x0814:
 357         /* L2 invalidate register */
 358         //        tlb_flush(first_cpu, 1);
 359         break;
 360     case 0x081C:
 361         /* system control register */
 362         sysctrl->syscontrol = val & 0x0F;
 363         break;
 364     case 0x0850:
 365         /* I/O map type register */
 366         sysctrl->contiguous_map = val & 0x01;
 367         break;
 368     default:
 369         printf("ERROR: unaffected IO port write: %04" PRIx32
 370                " => %02" PRIx32"\n", addr, val);
 371         break;
 372     }
 373 }
 374
 375 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 376 {
 377     sysctrl_t *sysctrl = opaque;
 378     uint32_t retval = 0xFF;
 379
 380     switch (addr) {
 381     case 0x0092:
 382         /* Special port 92 */
 383         retval = 0x00;
 384         break;
 385     case 0x0800:
 386         /* Motorola CPU configuration register */
 387         retval = 0xEF; /* MPC750 */
 388         break;
 389     case 0x0802:
 390         /* Motorola Base module feature register */
 391         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 392         break;
 393     case 0x0803:
 394         /* Motorola base module status register */
 395         retval = 0xE0; /* Standard MPC750 */
 396         break;
 397     case 0x080C:
 398         /* Equipment present register:
 399          *  no L2 cache
 400          *  no upgrade processor
 401          *  no cards in PCI slots
 402          *  SCSI fuse is bad
 403          */
 404         retval = 0x3C;
 405         break;
 406     case 0x0810:
 407         /* Motorola base module extended feature register */
 408         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 409         break;
 410     case 0x0814:
 411         /* L2 invalidate: don't care */
 412         break;
 413     case 0x0818:
 414         /* Keylock */
 415         retval = 0x00;
 416         break;
 417     case 0x081C:
 418         /* system control register
 419          * 7 - 6 / 1 - 0: L2 cache enable
 420          */
 421         retval = sysctrl->syscontrol;
 422         break;
 423     case 0x0823:
 424         /* */
 425         retval = 0x03; /* no L2 cache */
 426         break;
 427     case 0x0850:
 428         /* I/O map type register */
 429         retval = sysctrl->contiguous_map;
 430         break;
 431     default:
 432         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 433         break;
 434     }
 435     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 436                    addr - PPC_IO_BASE, retval);
 437
 438     return retval;
 439 }
 440
 441 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 442                                                  target_phys_addr_t addr)
 443 {
 444     if (sysctrl->contiguous_map == 0) {
 445         /* 64 KB contiguous space for IOs */
 446         addr &= 0xFFFF;
 447     } else {
 448         /* 8 MB non-contiguous space for IOs */
 449         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 450     }
 451
 452     return addr;
 453 }
 454
 455 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 456                                 uint32_t value)
 457 {
 458     sysctrl_t *sysctrl = opaque;
 459
 460     addr = prep_IO_address(sysctrl, addr);
 461     cpu_outb(NULL, addr, value);
 462 }
 463
 464 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 465 {
 466     sysctrl_t *sysctrl = opaque;
 467     uint32_t ret;
 468
 469     addr = prep_IO_address(sysctrl, addr);
 470     ret = cpu_inb(NULL, addr);
 471
 472     return ret;
 473 }
 474
 475 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 476                                 uint32_t value)
 477 {
 478     sysctrl_t *sysctrl = opaque;
 479
 480     addr = prep_IO_address(sysctrl, addr);
 481 #ifdef TARGET_WORDS_BIGENDIAN
 482     value = bswap16(value);
 483 #endif
 484     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 485     cpu_outw(NULL, addr, value);
 486 }
 487
 488 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 489 {
 490     sysctrl_t *sysctrl = opaque;
 491     uint32_t ret;
 492
 493     addr = prep_IO_address(sysctrl, addr);
 494     ret = cpu_inw(NULL, addr);
 495 #ifdef TARGET_WORDS_BIGENDIAN
 496     ret = bswap16(ret);
 497 #endif
 498     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 499
 500     return ret;
 501 }
 502
 503 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 504                                 uint32_t value)
 505 {
 506     sysctrl_t *sysctrl = opaque;
 507
 508     addr = prep_IO_address(sysctrl, addr);
 509 #ifdef TARGET_WORDS_BIGENDIAN
 510     value = bswap32(value);
 511 #endif
 512     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 513     cpu_outl(NULL, addr, value);
 514 }
 515
 516 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 517 {
 518     sysctrl_t *sysctrl = opaque;
 519     uint32_t ret;
 520
 521     addr = prep_IO_address(sysctrl, addr);
 522     ret = cpu_inl(NULL, addr);
 523 #ifdef TARGET_WORDS_BIGENDIAN
 524     ret = bswap32(ret);
 525 #endif
 526     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 527
 528     return ret;
 529 }
 530
 531 static CPUWriteMemoryFunc *PPC_prep_io_write[] = {
 532     &PPC_prep_io_writeb,
 533     &PPC_prep_io_writew,
 534     &PPC_prep_io_writel,
 535 };
 536
 537 static CPUReadMemoryFunc *PPC_prep_io_read[] = {
 538     &PPC_prep_io_readb,
 539     &PPC_prep_io_readw,
 540     &PPC_prep_io_readl,
 541 };
 542
 543 #define NVRAM_SIZE        0x2000
 544
 545 /* PowerPC PREP hardware initialisation */
 546 static void ppc_prep_init (ram_addr_t ram_size,
 547                            const char *boot_device,
 548                            const char *kernel_filename,
 549                            const char *kernel_cmdline,
 550                            const char *initrd_filename,
 551                            const char *cpu_model)
 552 {
 553     CPUState *env = NULL, *envs[MAX_CPUS];
 554     char *filename;
 555     nvram_t nvram;
 556     m48t59_t *m48t59;
 557     int PPC_io_memory;
 558     int linux_boot, i, nb_nics1, bios_size;
 559     ram_addr_t ram_offset, bios_offset;
 560     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 561     PCIBus *pci_bus;
 562     qemu_irq *i8259;
 563     int ppc_boot_device;
 564     DriveInfo *dinfo;
 565     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 566     BlockDriverState *fd[MAX_FD];
 567
 568     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 569
 570     linux_boot = (kernel_filename != NULL);
 571
 572     /* init CPUs */
 573     if (cpu_model == NULL)
 574         cpu_model = "default";
 575     for (i = 0; i < smp_cpus; i++) {
 576         env = cpu_init(cpu_model);
 577         if (!env) {
 578             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 579             exit(1);
 580         }
 581         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 582             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 583             cpu_ppc_tb_init(env, 7812500UL);
 584         } else {
 585             /* Set time-base frequency to 100 Mhz */
 586             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 587         }
 588         qemu_register_reset(&cpu_ppc_reset, env);
 589         envs[i] = env;
 590     }
 591
 592     /* allocate RAM */
 593     ram_offset = qemu_ram_alloc(ram_size);
 594     cpu_register_physical_memory(0, ram_size, ram_offset);
 595
 596     /* allocate and load BIOS */
 597     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 598     if (bios_name == NULL)
 599         bios_name = BIOS_FILENAME;
 600     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 601     if (filename) {
 602         bios_size = get_image_size(filename);
 603     } else {
 604         bios_size = -1;
 605     }
 606     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 607         target_phys_addr_t bios_addr;
 608         bios_size = (bios_size + 0xfff) & ~0xfff;
 609         bios_addr = (uint32_t)(-bios_size);
 610         cpu_register_physical_memory(bios_addr, bios_size,
 611                                      bios_offset | IO_MEM_ROM);
 612         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 613     }
 614     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 615         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 616     }
 617     if (filename) {
 618         qemu_free(filename);
 619     }
 620     if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
 621         hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
 622     }
 623
 624     if (linux_boot) {
 625         kernel_base = KERNEL_LOAD_ADDR;
 626         /* now we can load the kernel */
 627         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 628                                           ram_size - kernel_base);
 629         if (kernel_size < 0) {
 630             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 631             exit(1);
 632         }
 633         /* load initrd */
 634         if (initrd_filename) {
 635             initrd_base = INITRD_LOAD_ADDR;
 636             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 637                                               ram_size - initrd_base);
 638             if (initrd_size < 0) {
 639                 hw_error("qemu: could not load initial ram disk '%s'\n",
 640                           initrd_filename);
 641             }
 642         } else {
 643             initrd_base = 0;
 644             initrd_size = 0;
 645         }
 646         ppc_boot_device = 'm';
 647     } else {
 648         kernel_base = 0;
 649         kernel_size = 0;
 650         initrd_base = 0;
 651         initrd_size = 0;
 652         ppc_boot_device = '\0';
 653         /* For now, OHW cannot boot from the network. */
 654         for (i = 0; boot_device[i] != '\0'; i++) {
 655             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 656                 ppc_boot_device = boot_device[i];
 657                 break;
 658             }
 659         }
 660         if (ppc_boot_device == '\0') {
 661             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 662             exit(1);
 663         }
 664     }
 665
 666     isa_mem_base = 0xc0000000;
 667     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 668         hw_error("Only 6xx bus is supported on PREP machine\n");
 669     }
 670     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 671     pci_bus = pci_prep_init(i8259);
 672     //    pci_bus = i440fx_init();
 673     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 674     PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
 675                                            PPC_prep_io_write, sysctrl);
 676     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 677
 678     /* init basic PC hardware */
 679     pci_vga_init(pci_bus, 0, 0);
 680     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 681     //    pit = pit_init(0x40, i8259[0]);
 682     rtc_init(0x70, i8259[8], 2000);
 683
 684     serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
 685     nb_nics1 = nb_nics;
 686     if (nb_nics1 > NE2000_NB_MAX)
 687         nb_nics1 = NE2000_NB_MAX;
 688     for(i = 0; i < nb_nics1; i++) {
 689         if (nd_table[i].model == NULL) {
 690             nd_table[i].model = "ne2k_isa";
 691         }
 692         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 693             isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
 694         } else {
 695             pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
 696         }
 697     }
 698
 699     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 700         fprintf(stderr, "qemu: too many IDE bus\n");
 701         exit(1);
 702     }
 703
 704     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 705         dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 706         hd[i] = dinfo ? dinfo->bdrv : NULL;
 707     }
 708
 709     for(i = 0; i < MAX_IDE_BUS; i++) {
 710         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 711                      hd[2 * i],
 712                      hd[2 * i + 1]);
 713     }
 714     i8042_init(i8259[1], i8259[12], 0x60);
 715     DMA_init(1);
 716     //    SB16_init();
 717
 718     for(i = 0; i < MAX_FD; i++) {
 719         dinfo = drive_get(IF_FLOPPY, 0, i);
 720         fd[i] = dinfo ? dinfo->bdrv : NULL;
 721     }
 722     fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
 723
 724     /* Register speaker port */
 725     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 726     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 727     /* Register fake IO ports for PREP */
 728     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 729     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 730     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 731     /* System control ports */
 732     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 733     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 734     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 735     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 736     /* PCI intack location */
 737     PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
 738                                            PPC_intack_write, NULL);
 739     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 740     /* PowerPC control and status register group */
 741 #if 0
 742     PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
 743                                            NULL);
 744     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 745 #endif
 746
 747     if (usb_enabled) {
 748         usb_ohci_init_pci(pci_bus, 3, -1);
 749     }
 750
 751     m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 752     if (m48t59 == NULL)
 753         return;
 754     sysctrl->nvram = m48t59;
 755
 756     /* Initialise NVRAM */
 757     nvram.opaque = m48t59;
 758     nvram.read_fn = &m48t59_read;
 759     nvram.write_fn = &m48t59_write;
 760     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 761                          kernel_base, kernel_size,
 762                          kernel_cmdline,
 763                          initrd_base, initrd_size,
 764                          /* XXX: need an option to load a NVRAM image */
 765                          0,
 766                          graphic_width, graphic_height, graphic_depth);
 767
 768     /* Special port to get debug messages from Open-Firmware */
 769     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 770 }
 771
 772 static QEMUMachine prep_machine = {
 773     .name = "prep",
 774     .desc = "PowerPC PREP platform",
 775     .init = ppc_prep_init,
 776     .max_cpus = MAX_CPUS,
 777 };
 778
 779 static void prep_machine_init(void)
 780 {
 781     qemu_register_machine(&prep_machine);
 782 }
 783
 784 machine_init(prep_machine_init);