hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int bus_num;
  40     int devfn_min;
  41     pci_set_irq_fn set_irq;
  42     pci_map_irq_fn map_irq;
  43     uint32_t config_reg; /* XXX: suppress */
  44     /* low level pic */
  45     SetIRQFunc *low_set_irq;
  46     qemu_irq *irq_opaque;
  47     PCIDevice *devices[256];
  48     PCIDevice *parent_dev;
  49     PCIBus *next;
  50     /* The bus IRQ state is the logical OR of the connected devices.
  51        Keep a count of the number of devices with raised IRQs.  */
  52     int nirq;
  53     int *irq_count;
  54 };
  55
  56 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  57
  58 static struct BusInfo pci_bus_info = {
  59     .name       = "PCI",
  60     .size       = sizeof(PCIBus),
  61     .print_dev  = pcibus_dev_print,
  62     .props      = (Property[]) {
  63         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  64         DEFINE_PROP_END_OF_LIST()
  65     }
  66 };
  67
  68 static void pci_update_mappings(PCIDevice *d);
  69 static void pci_set_irq(void *opaque, int irq_num, int level);
  70
  71 target_phys_addr_t pci_mem_base;
  72 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  73 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  74 static PCIBus *first_bus;
  75
  76 static void pcibus_save(QEMUFile *f, void *opaque)
  77 {
  78     PCIBus *bus = (PCIBus *)opaque;
  79     int i;
  80
  81     qemu_put_be32(f, bus->nirq);
  82     for (i = 0; i < bus->nirq; i++)
  83         qemu_put_be32(f, bus->irq_count[i]);
  84 }
  85
  86 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  87 {
  88     PCIBus *bus = (PCIBus *)opaque;
  89     int i, nirq;
  90
  91     if (version_id != 1)
  92         return -EINVAL;
  93
  94     nirq = qemu_get_be32(f);
  95     if (bus->nirq != nirq) {
  96         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  97                 nirq, bus->nirq);
  98         return -EINVAL;
  99     }
 100
 101     for (i = 0; i < nirq; i++)
 102         bus->irq_count[i] = qemu_get_be32(f);
 103
 104     return 0;
 105 }
 106
 107 static void pci_bus_reset(void *opaque)
 108 {
 109     PCIBus *bus = (PCIBus *)opaque;
 110     int i;
 111
 112     for (i = 0; i < bus->nirq; i++) {
 113         bus->irq_count[i] = 0;
 114     }
 115     for (i = 0; i < 256; i++) {
 116         if (bus->devices[i])
 117             memset(bus->devices[i]->irq_state, 0,
 118                    sizeof(bus->devices[i]->irq_state));
 119     }
 120 }
 121
 122 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 123                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 124                          qemu_irq *pic, int devfn_min, int nirq)
 125 {
 126     PCIBus *bus;
 127     static int nbus = 0;
 128
 129     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
 130     bus->set_irq = set_irq;
 131     bus->map_irq = map_irq;
 132     bus->irq_opaque = pic;
 133     bus->devfn_min = devfn_min;
 134     bus->nirq = nirq;
 135     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 136     bus->next = first_bus;
 137     first_bus = bus;
 138     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 139     qemu_register_reset(pci_bus_reset, bus);
 140     return bus;
 141 }
 142
 143 static PCIBus *pci_register_secondary_bus(PCIDevice *dev,
 144                                           pci_map_irq_fn map_irq,
 145                                           const char *name)
 146 {
 147     PCIBus *bus;
 148
 149     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, &dev->qdev, name));
 150     bus->map_irq = map_irq;
 151     bus->parent_dev = dev;
 152     bus->next = dev->bus->next;
 153     dev->bus->next = bus;
 154     return bus;
 155 }
 156
 157 int pci_bus_num(PCIBus *s)
 158 {
 159     return s->bus_num;
 160 }
 161
 162 void pci_device_save(PCIDevice *s, QEMUFile *f)
 163 {
 164     int i;
 165
 166     qemu_put_be32(f, 2); /* PCI device version */
 167     qemu_put_buffer(f, s->config, 256);
 168     for (i = 0; i < 4; i++)
 169         qemu_put_be32(f, s->irq_state[i]);
 170 }
 171
 172 int pci_device_load(PCIDevice *s, QEMUFile *f)
 173 {
 174     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 175     uint32_t version_id;
 176     int i;
 177
 178     version_id = qemu_get_be32(f);
 179     if (version_id > 2)
 180         return -EINVAL;
 181     qemu_get_buffer(f, config, sizeof config);
 182     for (i = 0; i < sizeof config; ++i)
 183         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 184             return -EINVAL;
 185     memcpy(s->config, config, sizeof config);
 186
 187     pci_update_mappings(s);
 188
 189     if (version_id >= 2)
 190         for (i = 0; i < 4; i ++)
 191             s->irq_state[i] = qemu_get_be32(f);
 192     return 0;
 193 }
 194
 195 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 196 {
 197     uint16_t *id;
 198
 199     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 200     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 201     id[1] = cpu_to_le16(pci_default_sub_device_id);
 202     return 0;
 203 }
 204
 205 /*
 206  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 207  */
 208 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 209 {
 210     const char *p;
 211     char *e;
 212     unsigned long val;
 213     unsigned long dom = 0, bus = 0;
 214     unsigned slot = 0;
 215
 216     p = addr;
 217     val = strtoul(p, &e, 16);
 218     if (e == p)
 219         return -1;
 220     if (*e == ':') {
 221         bus = val;
 222         p = e + 1;
 223         val = strtoul(p, &e, 16);
 224         if (e == p)
 225             return -1;
 226         if (*e == ':') {
 227             dom = bus;
 228             bus = val;
 229             p = e + 1;
 230             val = strtoul(p, &e, 16);
 231             if (e == p)
 232                 return -1;
 233         }
 234     }
 235
 236     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 237         return -1;
 238
 239     slot = val;
 240
 241     if (*e)
 242         return -1;
 243
 244     /* Note: QEMU doesn't implement domains other than 0 */
 245     if (dom != 0 || pci_find_bus(bus) == NULL)
 246         return -1;
 247
 248     *domp = dom;
 249     *busp = bus;
 250     *slotp = slot;
 251     return 0;
 252 }
 253
 254 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 255                      unsigned *slotp)
 256 {
 257     /* strip legacy tag */
 258     if (!strncmp(addr, "pci_addr=", 9)) {
 259         addr += 9;
 260     }
 261     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 262         monitor_printf(mon, "Invalid pci address\n");
 263         return -1;
 264     }
 265     return 0;
 266 }
 267
 268 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 269 {
 270     int dom, bus;
 271     unsigned slot;
 272
 273     if (!devaddr) {
 274         *devfnp = -1;
 275         return pci_find_bus(0);
 276     }
 277
 278     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 279         return NULL;
 280     }
 281
 282     *devfnp = slot << 3;
 283     return pci_find_bus(bus);
 284 }
 285
 286 static void pci_init_cmask(PCIDevice *dev)
 287 {
 288     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 289     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 290     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 291     dev->cmask[PCI_REVISION_ID] = 0xff;
 292     dev->cmask[PCI_CLASS_PROG] = 0xff;
 293     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 294     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 295     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 296 }
 297
 298 static void pci_init_wmask(PCIDevice *dev)
 299 {
 300     int i;
 301     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 302     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 303     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 304                               | PCI_COMMAND_MASTER;
 305     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 306         dev->wmask[i] = 0xff;
 307 }
 308
 309 /* -1 for devfn means auto assign */
 310 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 311                                          const char *name, int devfn,
 312                                          PCIConfigReadFunc *config_read,
 313                                          PCIConfigWriteFunc *config_write)
 314 {
 315     if (devfn < 0) {
 316         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 317             if (!bus->devices[devfn])
 318                 goto found;
 319         }
 320         return NULL;
 321     found: ;
 322     } else if (bus->devices[devfn]) {
 323         return NULL;
 324     }
 325     pci_dev->bus = bus;
 326     pci_dev->devfn = devfn;
 327     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 328     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 329     pci_set_default_subsystem_id(pci_dev);
 330     pci_init_cmask(pci_dev);
 331     pci_init_wmask(pci_dev);
 332
 333     if (!config_read)
 334         config_read = pci_default_read_config;
 335     if (!config_write)
 336         config_write = pci_default_write_config;
 337     pci_dev->config_read = config_read;
 338     pci_dev->config_write = config_write;
 339     bus->devices[devfn] = pci_dev;
 340     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 341     return pci_dev;
 342 }
 343
 344 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 345                                int instance_size, int devfn,
 346                                PCIConfigReadFunc *config_read,
 347                                PCIConfigWriteFunc *config_write)
 348 {
 349     PCIDevice *pci_dev;
 350
 351     pci_dev = qemu_mallocz(instance_size);
 352     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 353                                      config_read, config_write);
 354     return pci_dev;
 355 }
 356 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 357 {
 358     return addr + pci_mem_base;
 359 }
 360
 361 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 362 {
 363     PCIIORegion *r;
 364     int i;
 365
 366     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 367         r = &pci_dev->io_regions[i];
 368         if (!r->size || r->addr == -1)
 369             continue;
 370         if (r->type == PCI_ADDRESS_SPACE_IO) {
 371             isa_unassign_ioport(r->addr, r->size);
 372         } else {
 373             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 374                                                      r->size,
 375                                                      IO_MEM_UNASSIGNED);
 376         }
 377     }
 378 }
 379
 380 int pci_unregister_device(PCIDevice *pci_dev)
 381 {
 382     int ret = 0;
 383
 384     if (pci_dev->unregister)
 385         ret = pci_dev->unregister(pci_dev);
 386     if (ret)
 387         return ret;
 388
 389     pci_unregister_io_regions(pci_dev);
 390
 391     qemu_free_irqs(pci_dev->irq);
 392     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 393     qdev_free(&pci_dev->qdev);
 394     return 0;
 395 }
 396
 397 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 398                             uint32_t size, int type,
 399                             PCIMapIORegionFunc *map_func)
 400 {
 401     PCIIORegion *r;
 402     uint32_t addr;
 403     uint32_t wmask;
 404
 405     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 406         return;
 407
 408     if (size & (size-1)) {
 409         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 410                     "type=0x%x, size=0x%x\n", type, size);
 411         exit(1);
 412     }
 413
 414     r = &pci_dev->io_regions[region_num];
 415     r->addr = -1;
 416     r->size = size;
 417     r->type = type;
 418     r->map_func = map_func;
 419
 420     wmask = ~(size - 1);
 421     if (region_num == PCI_ROM_SLOT) {
 422         addr = 0x30;
 423         /* ROM enable bit is writeable */
 424         wmask |= 1;
 425     } else {
 426         addr = 0x10 + region_num * 4;
 427     }
 428     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 429     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 430     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 431 }
 432
 433 static void pci_update_mappings(PCIDevice *d)
 434 {
 435     PCIIORegion *r;
 436     int cmd, i;
 437     uint32_t last_addr, new_addr, config_ofs;
 438
 439     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 440     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 441         r = &d->io_regions[i];
 442         if (i == PCI_ROM_SLOT) {
 443             config_ofs = 0x30;
 444         } else {
 445             config_ofs = 0x10 + i * 4;
 446         }
 447         if (r->size != 0) {
 448             if (r->type & PCI_ADDRESS_SPACE_IO) {
 449                 if (cmd & PCI_COMMAND_IO) {
 450                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 451                                                          config_ofs));
 452                     new_addr = new_addr & ~(r->size - 1);
 453                     last_addr = new_addr + r->size - 1;
 454                     /* NOTE: we have only 64K ioports on PC */
 455                     if (last_addr <= new_addr || new_addr == 0 ||
 456                         last_addr >= 0x10000) {
 457                         new_addr = -1;
 458                     }
 459                 } else {
 460                     new_addr = -1;
 461                 }
 462             } else {
 463                 if (cmd & PCI_COMMAND_MEMORY) {
 464                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 465                                                          config_ofs));
 466                     /* the ROM slot has a specific enable bit */
 467                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 468                         goto no_mem_map;
 469                     new_addr = new_addr & ~(r->size - 1);
 470                     last_addr = new_addr + r->size - 1;
 471                     /* NOTE: we do not support wrapping */
 472                     /* XXX: as we cannot support really dynamic
 473                        mappings, we handle specific values as invalid
 474                        mappings. */
 475                     if (last_addr <= new_addr || new_addr == 0 ||
 476                         last_addr == -1) {
 477                         new_addr = -1;
 478                     }
 479                 } else {
 480                 no_mem_map:
 481                     new_addr = -1;
 482                 }
 483             }
 484             /* now do the real mapping */
 485             if (new_addr != r->addr) {
 486                 if (r->addr != -1) {
 487                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 488                         int class;
 489                         /* NOTE: specific hack for IDE in PC case:
 490                            only one byte must be mapped. */
 491                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 492                         if (class == 0x0101 && r->size == 4) {
 493                             isa_unassign_ioport(r->addr + 2, 1);
 494                         } else {
 495                             isa_unassign_ioport(r->addr, r->size);
 496                         }
 497                     } else {
 498                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 499                                                      r->size,
 500                                                      IO_MEM_UNASSIGNED);
 501                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 502                     }
 503                 }
 504                 r->addr = new_addr;
 505                 if (r->addr != -1) {
 506                     r->map_func(d, i, r->addr, r->size, r->type);
 507                 }
 508             }
 509         }
 510     }
 511 }
 512
 513 uint32_t pci_default_read_config(PCIDevice *d,
 514                                  uint32_t address, int len)
 515 {
 516     uint32_t val;
 517
 518     switch(len) {
 519     default:
 520     case 4:
 521         if (address <= 0xfc) {
 522             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 523             break;
 524         }
 525         /* fall through */
 526     case 2:
 527         if (address <= 0xfe) {
 528             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 529             break;
 530         }
 531         /* fall through */
 532     case 1:
 533         val = d->config[address];
 534         break;
 535     }
 536     return val;
 537 }
 538
 539 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 540 {
 541     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 542     int i;
 543
 544     /* not efficient, but simple */
 545     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 546     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 547         uint8_t wmask = d->wmask[addr];
 548         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 549     }
 550     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 551         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 552             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 553         pci_update_mappings(d);
 554 }
 555
 556 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 557 {
 558     PCIBus *s = opaque;
 559     PCIDevice *pci_dev;
 560     int config_addr, bus_num;
 561
 562 #if 0
 563     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 564                 addr, val, len);
 565 #endif
 566     bus_num = (addr >> 16) & 0xff;
 567     while (s && s->bus_num != bus_num)
 568         s = s->next;
 569     if (!s)
 570         return;
 571     pci_dev = s->devices[(addr >> 8) & 0xff];
 572     if (!pci_dev)
 573         return;
 574     config_addr = addr & 0xff;
 575     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 576                 pci_dev->name, config_addr, val, len);
 577     pci_dev->config_write(pci_dev, config_addr, val, len);
 578 }
 579
 580 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 581 {
 582     PCIBus *s = opaque;
 583     PCIDevice *pci_dev;
 584     int config_addr, bus_num;
 585     uint32_t val;
 586
 587     bus_num = (addr >> 16) & 0xff;
 588     while (s && s->bus_num != bus_num)
 589         s= s->next;
 590     if (!s)
 591         goto fail;
 592     pci_dev = s->devices[(addr >> 8) & 0xff];
 593     if (!pci_dev) {
 594     fail:
 595         switch(len) {
 596         case 1:
 597             val = 0xff;
 598             break;
 599         case 2:
 600             val = 0xffff;
 601             break;
 602         default:
 603         case 4:
 604             val = 0xffffffff;
 605             break;
 606         }
 607         goto the_end;
 608     }
 609     config_addr = addr & 0xff;
 610     val = pci_dev->config_read(pci_dev, config_addr, len);
 611     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 612                 pci_dev->name, config_addr, val, len);
 613  the_end:
 614 #if 0
 615     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 616                 addr, val, len);
 617 #endif
 618     return val;
 619 }
 620
 621 /***********************************************************/
 622 /* generic PCI irq support */
 623
 624 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 625 static void pci_set_irq(void *opaque, int irq_num, int level)
 626 {
 627     PCIDevice *pci_dev = (PCIDevice *)opaque;
 628     PCIBus *bus;
 629     int change;
 630
 631     change = level - pci_dev->irq_state[irq_num];
 632     if (!change)
 633         return;
 634
 635     pci_dev->irq_state[irq_num] = level;
 636     for (;;) {
 637         bus = pci_dev->bus;
 638         irq_num = bus->map_irq(pci_dev, irq_num);
 639         if (bus->set_irq)
 640             break;
 641         pci_dev = bus->parent_dev;
 642     }
 643     bus->irq_count[irq_num] += change;
 644     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 645 }
 646
 647 /***********************************************************/
 648 /* monitor info on PCI */
 649
 650 typedef struct {
 651     uint16_t class;
 652     const char *desc;
 653 } pci_class_desc;
 654
 655 static const pci_class_desc pci_class_descriptions[] =
 656 {
 657     { 0x0100, "SCSI controller"},
 658     { 0x0101, "IDE controller"},
 659     { 0x0102, "Floppy controller"},
 660     { 0x0103, "IPI controller"},
 661     { 0x0104, "RAID controller"},
 662     { 0x0106, "SATA controller"},
 663     { 0x0107, "SAS controller"},
 664     { 0x0180, "Storage controller"},
 665     { 0x0200, "Ethernet controller"},
 666     { 0x0201, "Token Ring controller"},
 667     { 0x0202, "FDDI controller"},
 668     { 0x0203, "ATM controller"},
 669     { 0x0280, "Network controller"},
 670     { 0x0300, "VGA controller"},
 671     { 0x0301, "XGA controller"},
 672     { 0x0302, "3D controller"},
 673     { 0x0380, "Display controller"},
 674     { 0x0400, "Video controller"},
 675     { 0x0401, "Audio controller"},
 676     { 0x0402, "Phone"},
 677     { 0x0480, "Multimedia controller"},
 678     { 0x0500, "RAM controller"},
 679     { 0x0501, "Flash controller"},
 680     { 0x0580, "Memory controller"},
 681     { 0x0600, "Host bridge"},
 682     { 0x0601, "ISA bridge"},
 683     { 0x0602, "EISA bridge"},
 684     { 0x0603, "MC bridge"},
 685     { 0x0604, "PCI bridge"},
 686     { 0x0605, "PCMCIA bridge"},
 687     { 0x0606, "NUBUS bridge"},
 688     { 0x0607, "CARDBUS bridge"},
 689     { 0x0608, "RACEWAY bridge"},
 690     { 0x0680, "Bridge"},
 691     { 0x0c03, "USB controller"},
 692     { 0, NULL}
 693 };
 694
 695 static void pci_info_device(PCIDevice *d)
 696 {
 697     Monitor *mon = cur_mon;
 698     int i, class;
 699     PCIIORegion *r;
 700     const pci_class_desc *desc;
 701
 702     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 703                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 704     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 705     monitor_printf(mon, "    ");
 706     desc = pci_class_descriptions;
 707     while (desc->desc && class != desc->class)
 708         desc++;
 709     if (desc->desc) {
 710         monitor_printf(mon, "%s", desc->desc);
 711     } else {
 712         monitor_printf(mon, "Class %04x", class);
 713     }
 714     monitor_printf(mon, ": PCI device %04x:%04x\n",
 715            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 716            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 717
 718     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 719         monitor_printf(mon, "      IRQ %d.\n",
 720                        d->config[PCI_INTERRUPT_LINE]);
 721     }
 722     if (class == 0x0604) {
 723         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 724     }
 725     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 726         r = &d->io_regions[i];
 727         if (r->size != 0) {
 728             monitor_printf(mon, "      BAR%d: ", i);
 729             if (r->type & PCI_ADDRESS_SPACE_IO) {
 730                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 731                                r->addr, r->addr + r->size - 1);
 732             } else {
 733                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 734                                r->addr, r->addr + r->size - 1);
 735             }
 736         }
 737     }
 738     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 739     if (class == 0x0604 && d->config[0x19] != 0) {
 740         pci_for_each_device(d->config[0x19], pci_info_device);
 741     }
 742 }
 743
 744 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 745 {
 746     PCIBus *bus = first_bus;
 747     PCIDevice *d;
 748     int devfn;
 749
 750     while (bus && bus->bus_num != bus_num)
 751         bus = bus->next;
 752     if (bus) {
 753         for(devfn = 0; devfn < 256; devfn++) {
 754             d = bus->devices[devfn];
 755             if (d)
 756                 fn(d);
 757         }
 758     }
 759 }
 760
 761 void pci_info(Monitor *mon)
 762 {
 763     pci_for_each_device(0, pci_info_device);
 764 }
 765
 766 PCIDevice *pci_create(const char *name, const char *devaddr)
 767 {
 768     PCIBus *bus;
 769     int devfn;
 770     DeviceState *dev;
 771
 772     bus = pci_get_bus_devfn(&devfn, devaddr);
 773     if (!bus) {
 774         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 775                 devaddr, name);
 776         exit(1);
 777     }
 778
 779     dev = qdev_create(&bus->qbus, name);
 780     qdev_prop_set_uint32(dev, "addr", devfn);
 781     return (PCIDevice *)dev;
 782 }
 783
 784 static const char * const pci_nic_models[] = {
 785     "ne2k_pci",
 786     "i82551",
 787     "i82557b",
 788     "i82559er",
 789     "rtl8139",
 790     "e1000",
 791     "pcnet",
 792     "virtio",
 793     NULL
 794 };
 795
 796 static const char * const pci_nic_names[] = {
 797     "ne2k_pci",
 798     "i82551",
 799     "i82557b",
 800     "i82559er",
 801     "rtl8139",
 802     "e1000",
 803     "pcnet",
 804     "virtio-net-pci",
 805     NULL
 806 };
 807
 808 /* Initialize a PCI NIC.  */
 809 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 810                         const char *default_devaddr)
 811 {
 812     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 813     PCIDevice *pci_dev;
 814     DeviceState *dev;
 815     int i;
 816
 817     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 818
 819     for (i = 0; pci_nic_models[i]; i++) {
 820         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 821             pci_dev = pci_create(pci_nic_names[i], devaddr);
 822             dev = &pci_dev->qdev;
 823             if (nd->id)
 824                 dev->id = qemu_strdup(nd->id);
 825             dev->nd = nd;
 826             qdev_init(dev);
 827             nd->private = dev;
 828             return pci_dev;
 829         }
 830     }
 831
 832     return NULL;
 833 }
 834
 835 typedef struct {
 836     PCIDevice dev;
 837     PCIBus *bus;
 838 } PCIBridge;
 839
 840 static void pci_bridge_write_config(PCIDevice *d,
 841                              uint32_t address, uint32_t val, int len)
 842 {
 843     PCIBridge *s = (PCIBridge *)d;
 844
 845     pci_default_write_config(d, address, val, len);
 846     s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
 847 }
 848
 849 PCIBus *pci_find_bus(int bus_num)
 850 {
 851     PCIBus *bus = first_bus;
 852
 853     while (bus && bus->bus_num != bus_num)
 854         bus = bus->next;
 855
 856     return bus;
 857 }
 858
 859 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 860 {
 861     PCIBus *bus = pci_find_bus(bus_num);
 862
 863     if (!bus)
 864         return NULL;
 865
 866     return bus->devices[PCI_DEVFN(slot, function)];
 867 }
 868
 869 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 870                         pci_map_irq_fn map_irq, const char *name)
 871 {
 872     PCIBridge *s;
 873     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 874                                          devfn, NULL, pci_bridge_write_config);
 875
 876     pci_config_set_vendor_id(s->dev.config, vid);
 877     pci_config_set_device_id(s->dev.config, did);
 878
 879     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 880     s->dev.config[0x05] = 0x00;
 881     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 882     s->dev.config[0x07] = 0x00; // status = fast devsel
 883     s->dev.config[0x08] = 0x00; // revision
 884     s->dev.config[0x09] = 0x00; // programming i/f
 885     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 886     s->dev.config[0x0D] = 0x10; // latency_timer
 887     s->dev.config[PCI_HEADER_TYPE] =
 888         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 889     s->dev.config[0x1E] = 0xa0; // secondary status
 890
 891     s->bus = pci_register_secondary_bus(&s->dev, map_irq, name);
 892     return s->bus;
 893 }
 894
 895 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 896 {
 897     PCIDevice *pci_dev = (PCIDevice *)qdev;
 898     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 899     PCIBus *bus;
 900     int devfn;
 901
 902     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 903     devfn = pci_dev->devfn;
 904     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
 905                                      info->config_read, info->config_write);
 906     assert(pci_dev);
 907     info->init(pci_dev);
 908 }
 909
 910 void pci_qdev_register(PCIDeviceInfo *info)
 911 {
 912     info->qdev.init = pci_qdev_init;
 913     info->qdev.bus_info = &pci_bus_info;
 914     qdev_register(&info->qdev);
 915 }
 916
 917 void pci_qdev_register_many(PCIDeviceInfo *info)
 918 {
 919     while (info->qdev.name) {
 920         pci_qdev_register(info);
 921         info++;
 922     }
 923 }
 924
 925 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 926 {
 927     DeviceState *dev;
 928
 929     dev = qdev_create(&bus->qbus, name);
 930     qdev_prop_set_uint32(dev, "addr", devfn);
 931     qdev_init(dev);
 932
 933     return (PCIDevice *)dev;
 934 }
 935
 936 static int pci_find_space(PCIDevice *pdev, uint8_t size)
 937 {
 938     int offset = PCI_CONFIG_HEADER_SIZE;
 939     int i;
 940     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 941         if (pdev->used[i])
 942             offset = i + 1;
 943         else if (i - offset + 1 == size)
 944             return offset;
 945     return 0;
 946 }
 947
 948 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
 949                                         uint8_t *prev_p)
 950 {
 951     uint8_t next, prev;
 952
 953     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
 954         return 0;
 955
 956     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
 957          prev = next + PCI_CAP_LIST_NEXT)
 958         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
 959             break;
 960
 961     if (prev_p)
 962         *prev_p = prev;
 963     return next;
 964 }
 965
 966 /* Reserve space and add capability to the linked list in pci config space */
 967 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 968 {
 969     uint8_t offset = pci_find_space(pdev, size);
 970     uint8_t *config = pdev->config + offset;
 971     if (!offset)
 972         return -ENOSPC;
 973     config[PCI_CAP_LIST_ID] = cap_id;
 974     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
 975     pdev->config[PCI_CAPABILITY_LIST] = offset;
 976     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
 977     memset(pdev->used + offset, 0xFF, size);
 978     /* Make capability read-only by default */
 979     memset(pdev->wmask + offset, 0, size);
 980     /* Check capability by default */
 981     memset(pdev->cmask + offset, 0xFF, size);
 982     return offset;
 983 }
 984
 985 /* Unlink capability from the pci config space. */
 986 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 987 {
 988     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
 989     if (!offset)
 990         return;
 991     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
 992     /* Make capability writeable again */
 993     memset(pdev->wmask + offset, 0xff, size);
 994     /* Clear cmask as device-specific registers can't be checked */
 995     memset(pdev->cmask + offset, 0, size);
 996     memset(pdev->used + offset, 0, size);
 997
 998     if (!pdev->config[PCI_CAPABILITY_LIST])
 999         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1000 }
1001
1002 /* Reserve space for capability at a known offset (to call after load). */
1003 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1004 {
1005     memset(pdev->used + offset, 0xff, size);
1006 }
1007
1008 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1009 {
1010     return pci_find_capability_list(pdev, cap_id, NULL);
1011 }
1012
1013 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1014 {
1015     PCIDevice *d = (PCIDevice *)dev;
1016     const pci_class_desc *desc;
1017     char ctxt[64];
1018     PCIIORegion *r;
1019     int i, class;
1020
1021     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1022     desc = pci_class_descriptions;
1023     while (desc->desc && class != desc->class)
1024         desc++;
1025     if (desc->desc) {
1026         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1027     } else {
1028         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1029     }
1030
1031     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1032                    "pci id %04x:%04x (sub %04x:%04x)\n",
1033                    indent, "", ctxt,
1034                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1035                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1036                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1037                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1038                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1039     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1040         r = &d->io_regions[i];
1041         if (!r->size)
1042             continue;
1043         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1044                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1045                        r->addr, r->addr + r->size - 1);
1046     }
1047 }