simple-FreeRTOS-demo application is created
[armadillo_firmware.git] / simple-FreeRTOS-demo / boot.s
blob480c8e40e717268c5d1a04d6c080fc54090bd4e1
1 /* Sample initialization file */
3 .extern main
4 .extern exit
6 .text
7 .code 32
10 .align 0
12 .extern __bss_beg__
13 .extern __bss_end__
14 .extern __stack_end__
15 .extern __data_beg__
16 .extern __data_end__
17 .extern __data+beg_src__
19 .global start
20 .global endless_loop
22 /* Stack Sizes */
23 .set UND_STACK_SIZE, 0x00000004
24 .set ABT_STACK_SIZE, 0x00000004
25 .set FIQ_STACK_SIZE, 0x00000004
26 .set IRQ_STACK_SIZE, 0X00000400
27 .set SVC_STACK_SIZE, 0x00000400
29 /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
30 .set MODE_USR, 0x10 /* User Mode */
31 .set MODE_FIQ, 0x11 /* FIQ Mode */
32 .set MODE_IRQ, 0x12 /* IRQ Mode */
33 .set MODE_SVC, 0x13 /* Supervisor Mode */
34 .set MODE_ABT, 0x17 /* Abort Mode */
35 .set MODE_UND, 0x1B /* Undefined Mode */
36 .set MODE_SYS, 0x1F /* System Mode */
38 .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
39 .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
42 start:
43 _start:
44 _mainCRTStartup:
46 /* Setup a stack for each mode - note that this only sets up a usable stack
47 for system/user, SWI and IRQ modes. Also each mode is setup with
48 interrupts initially disabled. */
49 ldr r0, .LC6
50 msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
51 mov sp, r0
52 sub r0, r0, #UND_STACK_SIZE
53 msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
54 mov sp, r0
55 sub r0, r0, #ABT_STACK_SIZE
56 msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
57 mov sp, r0
58 sub r0, r0, #FIQ_STACK_SIZE
59 msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
60 mov sp, r0
61 sub r0, r0, #IRQ_STACK_SIZE
62 msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
63 mov sp, r0
64 sub r0, r0, #SVC_STACK_SIZE
65 msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
66 mov sp, r0
68 /* We want to start in supervisor mode. Operation will switch to system
69 mode when the first task starts. */
70 msr CPSR_c, #MODE_SVC|I_BIT|F_BIT
72 /* Clear BSS. */
74 mov a2, #0 /* Fill value */
75 mov fp, a2 /* Null frame pointer */
76 mov r7, a2 /* Null frame pointer for Thumb */
78 ldr r1, .LC1 /* Start of memory block */
79 ldr r3, .LC2 /* End of memory block */
80 subs r3, r3, r1 /* Length of block */
81 beq .end_clear_loop
82 mov r2, #0
84 .clear_loop:
85 strb r2, [r1], #1
86 subs r3, r3, #1
87 bgt .clear_loop
89 .end_clear_loop:
91 /* Initialise data. */
93 ldr r1, .LC3 /* Start of memory block */
94 ldr r2, .LC4 /* End of memory block */
95 ldr r3, .LC5
96 subs r3, r3, r1 /* Length of block */
97 beq .end_set_loop
99 .set_loop:
100 ldrb r4, [r2], #1
101 strb r4, [r1], #1
102 subs r3, r3, #1
103 bgt .set_loop
105 .end_set_loop:
107 mov r0, #0 /* no arguments */
108 mov r1, #0 /* no argv either */
110 bl main
112 endless_loop:
113 b endless_loop
116 .align 0
118 .LC1:
119 .word __bss_beg__
120 .LC2:
121 .word __bss_end__
122 .LC3:
123 .word __data_beg__
124 .LC4:
125 .word __data_beg_src__
126 .LC5:
127 .word __data_end__
128 .LC6:
129 .word __stack_end__
132 /* Setup vector table. Note that undf, pabt, dabt, fiq just execute
133 a null loop. */
135 .section .startup,"ax"
136 .code 32
137 .align 0
139 b _start /* reset - _start */
140 ldr pc, _undf /* undefined - _undf */
141 ldr pc, _swi /* SWI - _swi */
142 ldr pc, _pabt /* program abort - _pabt */
143 ldr pc, _dabt /* data abort - _dabt */
144 nop /* reserved */
145 ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */
146 ldr pc, _fiq /* FIQ - _fiq */
148 _undf: .word __undf /* undefined */
149 _swi: .word vPortYieldProcessor /* SWI */
150 _pabt: .word __pabt /* program abort */
151 _dabt: .word __dabt /* data abort */
152 _fiq: .word __fiq /* FIQ */
154 __undf: b . /* undefined */
155 __pabt: b . /* program abort */
156 __dabt: b . /* data abort */
157 __fiq: b . /* FIQ */