FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c

   1 /*
   2     FreeRTOS V6.0.5 - Copyright (C) 2010 Real Time Engineers Ltd.
   3
   4     ***************************************************************************
   5     *                                                                         *
   6     * If you are:                                                             *
   7     *                                                                         *
   8     *    + New to FreeRTOS,                                                   *
   9     *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
  10     *    + Looking for basic training,                                        *
  11     *    + Wanting to improve your FreeRTOS skills and productivity           *
  12     *                                                                         *
  13     * then take a look at the FreeRTOS eBook                                  *
  14     *                                                                         *
  15     *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
  16     *                  http://www.FreeRTOS.org/Documentation                  *
  17     *                                                                         *
  18     * A pdf reference manual is also available.  Both are usually delivered   *
  19     * to your inbox within 20 minutes to two hours when purchased between 8am *
  20     * and 8pm GMT (although please allow up to 24 hours in case of            *
  21     * exceptional circumstances).  Thank you for your support!                *
  22     *                                                                         *
  23     ***************************************************************************
  24
  25     This file is part of the FreeRTOS distribution.
  26
  27     FreeRTOS is free software; you can redistribute it and/or modify it under
  28     the terms of the GNU General Public License (version 2) as published by the
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
  30     ***NOTE*** The exception to the GPL is included to allow you to distribute
  31     a combined work that includes FreeRTOS without being obliged to provide the
  32     source code for proprietary components outside of the FreeRTOS kernel.
  33     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
  34     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  35     FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  36     more details. You should have received a copy of the GNU General Public
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained
  39     by writing to Richard Barry, contact details for whom are available on the
  40     FreeRTOS WEB site.
  41
  42     1 tab == 4 spaces!
  43
  44     http://www.FreeRTOS.org - Documentation, latest information, license and
  45     contact details.
  46
  47     http://www.SafeRTOS.com - A version that is certified for use in safety
  48     critical systems.
  49
  50     http://www.OpenRTOS.com - Commercial support, development, porting,
  51     licensing and training services.
  52 */
  53
  54
  55 /*-----------------------------------------------------------
  56  * Components that can be compiled to either ARM or THUMB mode are
  57  * contained in port.c  The ISR routines, which can only be compiled
  58  * to ARM mode, are contained in this file.
  59  *----------------------------------------------------------*/
  60
  61 /*
  62         Changes from V2.5.2
  63
  64         + The critical section management functions have been changed.  These no
  65           longer modify the stack and are safe to use at all optimisation levels.
  66           The functions are now also the same for both ARM and THUMB modes.
  67
  68         Changes from V2.6.0
  69
  70         + Removed the 'static' from the definition of vNonPreemptiveTick() to
  71           allow the demo to link when using the cooperative scheduler.
  72
  73         Changes from V3.2.4
  74
  75         + The assembler statements are now included in a single asm block rather
  76           than each line having its own asm block.
  77 */
  78
  79
  80 /* Scheduler includes. */
  81 #include "FreeRTOS.h"
  82
  83 /* Constants required to handle interrupts. */
  84 #define portTIMER_MATCH_ISR_BIT         ( ( unsigned char ) 0x01 )
  85 #define portCLEAR_VIC_INTERRUPT         ( ( unsigned long ) 0 )
  86
  87 /* Constants required to handle critical sections. */
  88 #define portNO_CRITICAL_NESTING         ( ( unsigned long ) 0 )
  89 volatile unsigned long ulCriticalNesting = 9999UL;
  90
  91 /*-----------------------------------------------------------*/
  92
  93 /* ISR to handle manual context switches (from a call to taskYIELD()). */
  94 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
  95
  96 /*
  97  * The scheduler can only be started from ARM mode, hence the inclusion of this
  98  * function here.
  99  */
 100 void vPortISRStartFirstTask( void );
 101 /*-----------------------------------------------------------*/
 102
 103 void vPortISRStartFirstTask( void )
 104 {
 105         /* Simply start the scheduler.  This is included here as it can only be
 106         called from ARM mode. */
 107         portRESTORE_CONTEXT();
 108 }
 109 /*-----------------------------------------------------------*/
 110
 111 /*
 112  * Called by portYIELD() or taskYIELD() to manually force a context switch.
 113  *
 114  * When a context switch is performed from the task level the saved task
 115  * context is made to look as if it occurred from within the tick ISR.  This
 116  * way the same restore context function can be used when restoring the context
 117  * saved from the ISR or that saved from a call to vPortYieldProcessor.
 118  */
 119 void vPortYieldProcessor( void )
 120 {
 121         /* Within an IRQ ISR the link register has an offset from the true return
 122         address, but an SWI ISR does not.  Add the offset manually so the same
 123         ISR return code can be used in both cases. */
 124         __asm volatile ( "ADD           LR, LR, #4" );
 125
 126         /* Perform the context switch.  First save the context of the current task. */
 127         portSAVE_CONTEXT();
 128
 129         /* Find the highest priority task that is ready to run. */
 130         __asm volatile ( "bl vTaskSwitchContext" );
 131
 132         /* Restore the context of the new task. */
 133         portRESTORE_CONTEXT();
 134 }
 135 /*-----------------------------------------------------------*/
 136
 137 /*
 138  * The ISR used for the scheduler tick.
 139  */
 140 void vTickISR( void ) __attribute__((naked));
 141 void vTickISR( void )
 142 {
 143         /* Save the context of the interrupted task. */
 144         portSAVE_CONTEXT();
 145
 146         /* Increment the RTOS tick count, then look for the highest priority
 147         task that is ready to run. */
 148         __asm volatile( "bl vTaskIncrementTick" );
 149
 150         #if configUSE_PREEMPTION == 1
 151                 __asm volatile( "bl vTaskSwitchContext" );
 152         #endif
 153
 154         /* Ready for the next interrupt. */
 155         T0_IR = portTIMER_MATCH_ISR_BIT;
 156         VICVectAddr = portCLEAR_VIC_INTERRUPT;
 157
 158         /* Restore the context of the new task. */
 159         portRESTORE_CONTEXT();
 160 }
 161 /*-----------------------------------------------------------*/
 162
 163 /*
 164  * The interrupt management utilities can only be called from ARM mode.  When
 165  * THUMB_INTERWORK is defined the utilities are defined as functions here to
 166  * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
 167  * the utilities are defined as macros in portmacro.h - as per other ports.
 168  */
 169 #ifdef THUMB_INTERWORK
 170
 171         void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
 172         void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
 173
 174         void vPortDisableInterruptsFromThumb( void )
 175         {
 176                 __asm volatile (
 177                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */
 178                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */
 179                         "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */
 180                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */
 181                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */
 182                         "BX             R14" );                                 /* Return back to thumb.                                        */
 183         }
 184
 185         void vPortEnableInterruptsFromThumb( void )
 186         {
 187                 __asm volatile (
 188                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */
 189                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */
 190                         "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */
 191                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */
 192                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */
 193                         "BX             R14" );                                 /* Return back to thumb.                                        */
 194         }
 195
 196 #endif /* THUMB_INTERWORK */
 197
 198 /* The code generated by the GCC compiler uses the stack in different ways at
 199 different optimisation levels.  The interrupt flags can therefore not always
 200 be saved to the stack.  Instead the critical section nesting level is stored
 201 in a variable, which is then saved as part of the stack context. */
 202 void vPortEnterCritical( void )
 203 {
 204         /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */
 205         __asm volatile (
 206                 "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */
 207                 "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */
 208                 "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */
 209                 "MSR    CPSR, R0                        \n\t"   /* Write back modified value.                   */
 210                 "LDMIA  SP!, {R0}" );                           /* Pop R0.                                                              */
 211
 212         /* Now interrupts are disabled ulCriticalNesting can be accessed
 213         directly.  Increment ulCriticalNesting to keep a count of how many times
 214         portENTER_CRITICAL() has been called. */
 215         ulCriticalNesting++;
 216 }
 217
 218 void vPortExitCritical( void )
 219 {
 220         if( ulCriticalNesting > portNO_CRITICAL_NESTING )
 221         {
 222                 /* Decrement the nesting count as we are leaving a critical section. */
 223                 ulCriticalNesting--;
 224
 225                 /* If the nesting level has reached zero then interrupts should be
 226                 re-enabled. */
 227                 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
 228                 {
 229                         /* Enable interrupts as per portEXIT_CRITICAL().                                        */
 230                         __asm volatile (
 231                                 "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */
 232                                 "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */
 233                                 "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */
 234                                 "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */
 235                                 "LDMIA  SP!, {R0}" );                   /* Pop R0.                                              */
 236                 }
 237         }
 238 }