FreeRTOS/Common/ethernet/lwIP_130/contrib/port/FreeRTOS/ColdFire/eth_phy.h

   1 /*!
   2  * \file    eth.h
   3  * \brief   Definitions for Ethernet Physical Layer Interface
   4  * \version $Revision: 1.3 $
   5  * \author  Michael Norman
   6  */
   7
   8 #ifndef _ETH_PHY_H
   9 #define _ETH_PHY_H
  10
  11 /*******************************************************************/
  12
  13 int
  14 eth_phy_autoneg(int phy_addr, MII_SPEED speed, MII_DUPLEX duplex);
  15
  16 int
  17 eth_phy_manual(int phy_addr, MII_SPEED speed, MII_DUPLEX duplex, int loop);
  18
  19 int
  20 eth_phy_get_speed(int, int*);
  21
  22 int
  23 eth_phy_get_duplex(int, int*);
  24
  25 int
  26 eth_phy_reg_dump(int);
  27
  28 /*******************************************************************/
  29
  30 /* MII Register Addresses */
  31 #define PHY_BMCR                                    (0x00)
  32 #define PHY_BMSR                    (0x01)
  33 #define PHY_PHYIDR1                                 (0x02)
  34 #define PHY_PHYIDR2                                 (0x03)
  35 #define PHY_ANAR                                    (0x04)
  36 #define PHY_ANLPAR                          (0x05)
  37
  38 /* Bit definitions and macros for PHY_CTRL */
  39 #define PHY_BMCR_RESET                  (0x8000)
  40 #define PHY_BMCR_LOOP                       (0x4000)
  41 #define PHY_BMCR_SPEED                  (0x2000)
  42 #define PHY_BMCR_AN_ENABLE                  (0x1000)
  43 #define PHY_BMCR_POWERDOWN          (0x0800)
  44 #define PHY_BMCR_ISOLATE                (0x0400)
  45 #define PHY_BMCR_AN_RESTART             (0x0200)
  46 #define PHY_BMCR_FDX                        (0x0100)
  47 #define PHY_BMCR_COL_TEST               (0x0080)
  48
  49 /* Bit definitions and macros for PHY_STAT */
  50 #define PHY_BMSR_100BT4             (0x8000)
  51 #define PHY_BMSR_100BTX_FDX         (0x4000)
  52 #define PHY_BMSR_100BTX             (0x2000)
  53 #define PHY_BMSR_10BT_FDX           (0x1000)
  54 #define PHY_BMSR_10BT               (0x0800)
  55 #define PHY_BMSR_NO_PREAMBLE        (0x0040)
  56 #define PHY_BMSR_AN_COMPLETE        (0x0020)
  57 #define PHY_BMSR_REMOTE_FAULT       (0x0010)
  58 #define PHY_BMSR_AN_ABILITY         (0x0008)
  59 #define PHY_BMSR_LINK               (0x0004)
  60 #define PHY_BMSR_JABBER             (0x0002)
  61 #define PHY_BMSR_EXTENDED           (0x0001)
  62
  63 /* Bit definitions and macros for PHY_AN_ADV */
  64 #define PHY_ANAR_NEXT_PAGE          (0x8001)
  65 #define PHY_ANAR_REM_FAULT              (0x2001)
  66 #define PHY_ANAR_PAUSE                  (0x0401)
  67 #define PHY_ANAR_100BT4                 (0x0201)
  68 #define PHY_ANAR_100BTX_FDX             (0x0101)
  69 #define PHY_ANAR_100BTX                 (0x0081)
  70 #define PHY_ANAR_10BT_FDX                   (0x0041)
  71 #define PHY_ANAR_10BT                   (0x0021)
  72 #define PHY_ANAR_802_3                  (0x0001)
  73
  74 /* Bit definitions and macros for PHY_AN_LINK_PAR */
  75 #define PHY_ANLPAR_NEXT_PAGE        (0x8000)
  76 #define PHY_ANLPAR_ACK              (0x4000)
  77 #define PHY_ANLPAR_REM_FAULT        (0x2000)
  78 #define PHY_ANLPAR_PAUSE                    (0x0400)
  79 #define PHY_ANLPAR_100BT4                   (0x0200)
  80 #define PHY_ANLPAR_100BTX_FDX       (0x0100)
  81 #define PHY_ANLPAR_100BTX                   (0x0080)
  82 #define PHY_ANLPAR_10BTX_FDX        (0x0040)
  83 #define PHY_ANLPAR_10BT                 (0x0020)
  84
  85 /*******************************************************************/
  86
  87 #endif  /* _ETH_PHY_H */