ethernetgmii: updated port layout for missing pins

[ana-net.git] / microblaze / ethernetgmii / system.mhs

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.2 Build EDK_O.61xd
# Mon Jan  9 16:09:41 2012
# Target Board:  xilinx.com ml605 Rev D
# Family:    virtex6
# Device:    xc6vlx240t
# Package:   ff1156
# Speed Grade:  -1
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT ddr_memory_we_n = ddr_memory_we_n, DIR = O
 PORT ddr_memory_ras_n = ddr_memory_ras_n, DIR = O
 PORT ddr_memory_odt = ddr_memory_odt, DIR = O
 PORT ddr_memory_dqs_n = ddr_memory_dqs_n, DIR = IO, VEC = [0:0]
 PORT ddr_memory_dqs = ddr_memory_dqs, DIR = IO, VEC = [0:0]
 PORT ddr_memory_dq = ddr_memory_dq, DIR = IO, VEC = [7:0]
 PORT ddr_memory_dm = ddr_memory_dm, DIR = O, VEC = [0:0]
 PORT ddr_memory_ddr3_rst = ddr_memory_ddr3_rst, DIR = O
 PORT ddr_memory_cs_n = ddr_memory_cs_n, DIR = O
 PORT ddr_memory_clk_n = ddr_memory_clk_n, DIR = O
 PORT ddr_memory_clk = ddr_memory_clk, DIR = O
 PORT ddr_memory_cke = ddr_memory_cke, DIR = O
 PORT ddr_memory_cas_n = ddr_memory_cas_n, DIR = O
 PORT ddr_memory_ba = ddr_memory_ba, DIR = O, VEC = [2:0]
 PORT ddr_memory_addr = ddr_memory_addr, DIR = O, VEC = [12:0]
 PORT SysACE_WEN = SysACE_WEN, DIR = O
 PORT SysACE_OEN = SysACE_OEN, DIR = O
 PORT SysACE_MPIRQ = SysACE_MPIRQ, DIR = I
 PORT SysACE_MPD = SysACE_MPD, DIR = IO, VEC = [7:0]
 PORT SysACE_MPA = SysACE_MPA, DIR = O, VEC = [6:0]
 PORT SysACE_CLK = SysACE_CLK, DIR = I
 PORT SysACE_CEN = SysACE_CEN, DIR = O
 PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
 PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT Push_Buttons_5Bits_TRI_I = Push_Buttons_5Bits_TRI_I, DIR = I, VEC = [0:4]
 PORT Linear_Flash_we_n = Linear_Flash_we_n, DIR = O
 PORT Linear_Flash_oe_n = Linear_Flash_oe_n, DIR = O
 PORT Linear_Flash_data = Linear_Flash_data, DIR = IO, VEC = [0:15]
 PORT Linear_Flash_ce_n = Linear_Flash_ce_n, DIR = O
 PORT Linear_Flash_address = Linear_Flash_address, DIR = O, VEC = [0:23]
 PORT LEDs_Positions_TRI_O = LEDs_Positions_TRI_O, DIR = O, VEC = [0:4]
 PORT LEDs_8Bits_TRI_O = LEDs_8Bits_TRI_O, DIR = O, VEC = [0:7]
 PORT IIC_SFP_SDA = IIC_SFP_SDA, DIR = IO
 PORT IIC_SFP_SCL = IIC_SFP_SCL, DIR = IO
 PORT IIC_FMC_SDA = IIC_FMC_SDA, DIR = IO
 PORT IIC_FMC_SCL = IIC_FMC_SCL, DIR = IO
 PORT IIC_EEPROM_SDA = IIC_EEPROM_SDA, DIR = IO
 PORT IIC_EEPROM_SCL = IIC_EEPROM_SCL, DIR = IO
 PORT IIC_DVI_SDA = IIC_DVI_SDA, DIR = IO
 PORT IIC_DVI_SCL = IIC_DVI_SCL, DIR = IO
 PORT DIP_Switches_8Bits_TRI_I = DIP_Switches_8Bits_TRI_I, DIR = I, VEC = [0:7]
 PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
 PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
 PORT ETHERNET_MDIO = ETHERNET_MDIO, DIR = IO
 PORT ETHERNET_MDC = ETHERNET_MDC, DIR = O
 PORT ETHERNET_TX_ER = ETHERNET_TX_ER, DIR = O
 PORT ETHERNET_TXD = ETHERNET_TXD, DIR = O, VEC = [7:0]
 PORT ETHERNET_TX_EN = ETHERNET_TX_EN, DIR = O
 PORT ETHERNET_MII_TX_CLK = ETHERNET_MII_TX_CLK, DIR = I
 PORT ETHERNET_TX_CLK = ETHERNET_TX_CLK, DIR = O
 PORT ETHERNET_RXD = ETHERNET_RXD, DIR = I, VEC = [7:0]
 PORT ETHERNET_RX_ER = ETHERNET_RX_ER, DIR = I
 PORT ETHERNET_RX_CLK = ETHERNET_RX_CLK, DIR = I
 PORT ETHERNET_RX_DV = ETHERNET_RX_DV, DIR = I
 PORT ETHERNET_PHY_RST_N = ETHERNET_PHY_RST_N, DIR = O


BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Slowest_sync_clk = clk_100_0000MHzMMCM0
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN axi_intc
 PARAMETER INSTANCE = microblaze_0_intc
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT IRQ = microblaze_0_interrupt
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT INTR = RS232_Uart_1_Interrupt & IIC_EEPROM_IIC2INTC_Irpt & IIC_DVI_IIC2INTC_Irpt & IIC_FMC_IIC2INTC_Irpt & IIC_SFP_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & axi_timer_0_Interrupt & axi_ethernet_0_INTERRUPT & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHzMMCM0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHzMMCM0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.20.a
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0xc0000000
 PARAMETER C_ICACHE_HIGHADDR = 0xcfffffff
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 16384
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0xc0000000
 PARAMETER C_DCACHE_HIGHADDR = 0xcfffffff
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 16384
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER C_PVR = 2
 PARAMETER C_USE_MMU = 3
 PARAMETER C_MMU_ZONES = 2
 PARAMETER C_ICACHE_LINE_LEN = 8
 PARAMETER C_ICACHE_STREAMS = 1
 PARAMETER C_ICACHE_VICTIMS = 8
 PARAMETER C_DIV_ZERO_EXCEPTION = 1
 PARAMETER C_M_AXI_I_BUS_EXCEPTION = 1
 PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1
 PARAMETER C_ILL_OPCODE_EXCEPTION = 1
 PARAMETER C_OPCODE_0x0_ILLEGAL = 1
 PARAMETER C_UNALIGNED_EXCEPTIONS = 1
 PARAMETER C_USE_HW_MUL = 2
 PARAMETER C_USE_DIV = 1
 BUS_INTERFACE M_AXI_DP = axi4lite_0
 BUS_INTERFACE M_AXI_IP = axi4lite_0
 BUS_INTERFACE M_AXI_DC = axi4_0
 BUS_INTERFACE M_AXI_IC = axi4_0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_100_0000MHzMMCM0
 PORT INTERRUPT = microblaze_0_interrupt
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_UART = 1
 PARAMETER C_BASEADDR = 0x74800000
 PARAMETER C_HIGHADDR = 0x7480ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.02.a
 PARAMETER C_CLKIN_FREQ = 200000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT1_FREQ = 125000000
 PARAMETER C_CLKOUT1_GROUP = NONE
 PARAMETER C_CLKOUT2_FREQ = 200000000
 PARAMETER C_CLKOUT2_GROUP = MMCM0
 PARAMETER C_CLKOUT3_FREQ = 400000000
 PARAMETER C_CLKOUT3_GROUP = MMCM0
 PARAMETER C_CLKOUT4_FREQ = 400000000
 PARAMETER C_CLKOUT4_GROUP = MMCM0
 PARAMETER C_CLKOUT4_BUF = FALSE
 PARAMETER C_CLKOUT4_VARIABLE_PHASE = TRUE
 PARAMETER C_CLKOUT5_FREQ = 50000000
 PARAMETER C_CLKOUT5_GROUP = MMCM0
 PORT RST = RESET
 PORT CLKIN = CLK
 PORT CLKOUT0 = clk_100_0000MHzMMCM0
 PORT CLKOUT2 = clk_200_0000MHzMMCM0
 PORT CLKOUT3 = clk_400_0000MHzMMCM0
 PORT CLKOUT4 = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT CLKOUT5 = clk_50_0000MHzMMCM0
 PORT CLKOUT1 = clk_125_0000MHz
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT PSCLK = clk_100_0000MHzMMCM0
 PORT PSEN = psen
 PORT PSINCDEC = psincdec
 PORT PSDONE = psdone
END

BEGIN axi_timer
 PARAMETER INSTANCE = axi_timer_0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT Interrupt = axi_timer_0_Interrupt
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
 PORT INTERCONNECT_ACLK = clk_100_0000MHzMMCM0
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4_0
 PARAMETER HW_VER = 1.03.a
 PORT interconnect_aclk = clk_100_0000MHzMMCM0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_MEM_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41800000
 PARAMETER C_HIGHADDR = 0x4180ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT SysACE_WEN = SysACE_WEN
 PORT SysACE_OEN = SysACE_OEN
 PORT SysACE_MPIRQ = SysACE_MPIRQ
 PORT SysACE_MPD = SysACE_MPD
 PORT SysACE_MPA = SysACE_MPA
 PORT SysACE_CLK = SysACE_CLK
 PORT SysACE_CEN = SysACE_CEN
 PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT TX = RS232_Uart_1_sout
 PORT RX = RS232_Uart_1_sin
 PORT Interrupt = RS232_Uart_1_Interrupt
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = Linear_Flash_invertor
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_OPERATION = not
 PARAMETER C_SIZE = 1
 PORT Op1 = Linear_Flash_invertor_Op1_Adhoc
 PORT Res = Linear_Flash_ce_n
END

BEGIN axi_emc
 PARAMETER INSTANCE = Linear_Flash
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_TYPE = 2
 PARAMETER C_TCEDV_PS_MEM_0 = 130000
 PARAMETER C_TAVDV_PS_MEM_0 = 130000
 PARAMETER C_THZCE_PS_MEM_0 = 35000
 PARAMETER C_TWC_PS_MEM_0 = 13000
 PARAMETER C_TWP_PS_MEM_0 = 70000
 PARAMETER C_TLZWE_PS_MEM_0 = 35000
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_S_AXI_MEM0_BASEADDR = 0x76000000
 PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x77ffffff
 BUS_INTERFACE S_AXI_MEM = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT RdClk = clk_100_0000MHzMMCM0
 PORT Mem_WEN = Linear_Flash_we_n
 PORT Mem_OEN = Linear_Flash_oe_n
 PORT Mem_CEN = Linear_Flash_invertor_Op1_Adhoc
 PORT Mem_DQ = Linear_Flash_data
 PORT Mem_A = 0b0000000 & Linear_Flash_address & 0b0
END

BEGIN axi_iic
 PARAMETER INSTANCE = IIC_SFP
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_IIC_FREQ = 100000
 PARAMETER C_TEN_BIT_ADR = 0
 PARAMETER C_BASEADDR = 0x40800000
 PARAMETER C_HIGHADDR = 0x4080ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT Sda = IIC_SFP_SDA
 PORT Scl = IIC_SFP_SCL
 PORT IIC2INTC_Irpt = IIC_SFP_IIC2INTC_Irpt
END

BEGIN axi_iic
 PARAMETER INSTANCE = IIC_FMC
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_IIC_FREQ = 100000
 PARAMETER C_TEN_BIT_ADR = 0
 PARAMETER C_BASEADDR = 0x40820000
 PARAMETER C_HIGHADDR = 0x4082ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT Sda = IIC_FMC_SDA
 PORT Scl = IIC_FMC_SCL
 PORT IIC2INTC_Irpt = IIC_FMC_IIC2INTC_Irpt
END

BEGIN axi_iic
 PARAMETER INSTANCE = IIC_EEPROM
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_IIC_FREQ = 100000
 PARAMETER C_TEN_BIT_ADR = 0
 PARAMETER C_BASEADDR = 0x40840000
 PARAMETER C_HIGHADDR = 0x4084ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT Sda = IIC_EEPROM_SDA
 PORT Scl = IIC_EEPROM_SCL
 PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt
END

BEGIN axi_iic
 PARAMETER INSTANCE = IIC_DVI
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_IIC_FREQ = 100000
 PARAMETER C_TEN_BIT_ADR = 0
 PARAMETER C_BASEADDR = 0x40860000
 PARAMETER C_HIGHADDR = 0x4086ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzMMCM0
 PORT Sda = IIC_DVI_SDA
 PORT Scl = IIC_DVI_SCL
 PORT IIC2INTC_Irpt = IIC_DVI_IIC2INTC_Irpt
END

BEGIN axi_v6_ddrx
 PARAMETER INSTANCE = DDR3_SDRAM
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_MEM_PARTNO = MT41J64M16XX-15E
 PARAMETER C_DM_WIDTH = 1
 PARAMETER C_DQS_WIDTH = 1
 PARAMETER C_DQ_WIDTH = 8
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
 PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y8
 PARAMETER C_NDQS_COL0 = 1
 PARAMETER C_NDQS_COL1 = 0
 PARAMETER C_S_AXI_BASEADDR = 0xc0000000
 PARAMETER C_S_AXI_HIGHADDR = 0xcfffffff
 BUS_INTERFACE S_AXI = axi4_0
 PORT ddr_we_n = ddr_memory_we_n
 PORT ddr_ras_n = ddr_memory_ras_n
 PORT ddr_odt = ddr_memory_odt
 PORT ddr_dqs_n = ddr_memory_dqs_n
 PORT ddr_dqs_p = ddr_memory_dqs
 PORT ddr_dq = ddr_memory_dq
 PORT ddr_dm = ddr_memory_dm
 PORT ddr_reset_n = ddr_memory_ddr3_rst
 PORT ddr_cs_n = ddr_memory_cs_n
 PORT ddr_ck_n = ddr_memory_clk_n
 PORT ddr_ck_p = ddr_memory_clk
 PORT ddr_cke = ddr_memory_cke
 PORT ddr_cas_n = ddr_memory_cas_n
 PORT ddr_ba = ddr_memory_ba
 PORT ddr_addr = ddr_memory_addr
 PORT clk_rd_base = clk_400_0000MHzMMCM0_nobuf_varphase
 PORT clk_mem = clk_400_0000MHzMMCM0
 PORT clk = clk_200_0000MHzMMCM0
 PORT clk_ref = clk_200_0000MHzMMCM0
 PORT PD_PSEN = psen
 PORT PD_PSINCDEC = psincdec
 PORT PD_PSDONE = psdone
END

BEGIN axi_ethernet
 PARAMETER INSTANCE = axi_ethernet_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_INCLUDE_IO = 1
 PARAMETER C_TYPE = 2
 PARAMETER C_PHY_TYPE = 1
 PARAMETER C_HALFDUP = 0
 PARAMETER C_TXMEM = 16384
 PARAMETER C_RXMEM = 16384
 PARAMETER C_TXCSUM = 2
 PARAMETER C_RXCSUM = 2
 PARAMETER C_TXVLAN_TRAN = 0
 PARAMETER C_RXVLAN_TRAN = 0
 PARAMETER C_TXVLAN_TAG = 0
 PARAMETER C_RXVLAN_TAG = 0
 PARAMETER C_TXVLAN_STRP = 0
 PARAMETER C_RXVLAN_STRP = 0
 PARAMETER C_MCAST_EXTEND = 0
 PARAMETER C_STATS = 0
 PARAMETER C_AVB = 0
 PARAMETER C_BASEADDR = 0x75440000
 PARAMETER C_HIGHADDR = 0x7547ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE AXI_STR_TXD = ETHERNET_dma_txd
 BUS_INTERFACE AXI_STR_TXC = ETHERNET_dma_txc
 BUS_INTERFACE AXI_STR_RXS = ETHERNET_dma_rxs
 BUS_INTERFACE AXI_STR_RXD = ETHERNET_dma_rxd
 PORT MDIO = ETHERNET_MDIO
 PORT MDC = ETHERNET_MDC
 PORT GMII_TX_ER = ETHERNET_TX_ER
 PORT GMII_TXD = ETHERNET_TXD
 PORT GMII_TX_EN = ETHERNET_TX_EN
 PORT MII_TX_CLK = ETHERNET_MII_TX_CLK
 PORT GMII_TX_CLK = ETHERNET_TX_CLK
 PORT GMII_RXD = ETHERNET_RXD
 PORT GMII_RX_ER = ETHERNET_RX_ER
 PORT GMII_RX_CLK = ETHERNET_RX_CLK
 PORT GMII_RX_DV = ETHERNET_RX_DV
 PORT PHY_RST_N = ETHERNET_PHY_RST_N
 PORT REF_CLK = clk_200_0000MHzMMCM0
 PORT S_AXI_ACLK = clk_50_0000MHzMMCM0
 PORT GTX_CLK = clk_125_0000MHz
 PORT AXI_STR_TXD_ACLK = clk_100_0000MHzMMCM0
 PORT AXI_STR_TXC_ACLK = clk_100_0000MHzMMCM0
 PORT AXI_STR_RXD_ACLK = clk_100_0000MHzMMCM0
 PORT AXI_STR_RXS_ACLK = clk_100_0000MHzMMCM0
 PORT AXI_STR_TXD_ARESETN = AXI_STR_TXD_ARESETN
 PORT AXI_STR_TXC_ARESETN = AXI_STR_TXC_ARESETN
 PORT AXI_STR_RXD_ARESETN = AXI_STR_RXD_ARESETN
 PORT AXI_STR_RXS_ARESETN = AXI_STR_RXS_ARESETN
 PORT INTERRUPT = axi_ethernet_0_INTERRUPT
END

BEGIN axi_dma
 PARAMETER INSTANCE = ETHERNET_dma
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1
 PARAMETER C_SG_USE_STSAPP_LENGTH = 1
 PARAMETER C_INCLUDE_MM2S_DRE = 1
 PARAMETER C_INCLUDE_S2MM_DRE = 1
 PARAMETER C_DLYTMR_RESOLUTION = 1250
 PARAMETER C_PRMRY_IS_ACLK_ASYNC = 0
 PARAMETER C_SG_INCLUDE_STSCNTRL_STRM = 1
 PARAMETER C_SG_LENGTH_WIDTH = 16
 PARAMETER C_INCLUDE_MM2S = 1
 PARAMETER C_INCLUDE_S2MM = 1
 PARAMETER C_BASEADDR = 0x41F00000
 PARAMETER C_HIGHADDR = 0x41F0FFFF
 PARAMETER C_MM2S_BURST_SIZE = 256
 PARAMETER C_S2MM_BURST_SIZE = 256
 BUS_INTERFACE S_AXI_LITE = axi4lite_0
 BUS_INTERFACE M_AXI_SG = axi4_0
 BUS_INTERFACE M_AXI_MM2S = axi4_0
 BUS_INTERFACE M_AXI_S2MM = axi4_0
 BUS_INTERFACE M_AXIS_MM2S = ETHERNET_dma_txd
 BUS_INTERFACE M_AXIS_CNTRL = ETHERNET_dma_txc
 BUS_INTERFACE S_AXIS_STS = ETHERNET_dma_rxs
 BUS_INTERFACE S_AXIS_S2MM = ETHERNET_dma_rxd
 PORT s_axi_lite_aclk = clk_100_0000MHzMMCM0
 PORT m_axi_sg_aclk = clk_100_0000MHzMMCM0
 PORT m_axi_mm2s_aclk = clk_100_0000MHzMMCM0
 PORT m_axi_s2mm_aclk = clk_100_0000MHzMMCM0
 PORT mm2s_prmry_reset_out_n = AXI_STR_TXD_ARESETN
 PORT mm2s_cntrl_reset_out_n = AXI_STR_TXC_ARESETN
 PORT s2mm_prmry_reset_out_n = AXI_STR_RXD_ARESETN
 PORT s2mm_sts_reset_out_n = AXI_STR_RXS_ARESETN
 PORT mm2s_introut = ETHERNET_dma_mm2s_introut
 PORT s2mm_introut = ETHERNET_dma_s2mm_introut
END