| blob | 5e372935b8c600a5bacc6585be7a3b18afc2ff9b |
1 Against net-next, rev 356b95424cfb456e14a59eaa579422ce014c424b
3 Signed-off-by: Ariane Keller <ariane.keller@tik.ee.ethz.ch>
4 Signed-off-by: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
5 ---
6 MAINTAINERS | 6 +
7 drivers/net/ethernet/xilinx/Kconfig | 8 +
8 drivers/net/ethernet/xilinx/Makefile | 2 +
9 drivers/net/ethernet/xilinx/xilinx_axienet.h | 508 +++++++
10 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 1682 +++++++++++++++++++++
11 drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c | 238 +++
12 6 files changed, 2444 insertions(+), 0 deletions(-)
14 diff --git a/MAINTAINERS b/MAINTAINERS
15 index 4babed7..4d0b9f7 100644
16 --- a/MAINTAINERS
17 +++ b/MAINTAINERS
18 @@ -7459,6 +7459,12 @@ S: Supported
19 F: Documentation/filesystems/xfs.txt
20 F: fs/xfs/
22 +XILINX AXI ETHERNET DRIVER
23 +M: Ariane Keller <ariane.keller@tik.ee.ethz.ch>
24 +M: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
25 +S: Maintained
26 +F: drivers/net/ethernet/xilinx/xilinx_axienet*
27 +
28 XILINX SYSTEMACE DRIVER
29 M: Grant Likely <grant.likely@secretlab.ca>
30 W: http://www.secretlab.ca/
31 diff --git a/drivers/net/ethernet/xilinx/Kconfig b/drivers/net/ethernet/xilinx/Kconfig
32 index d5a8260..634e705 100644
33 --- a/drivers/net/ethernet/xilinx/Kconfig
34 +++ b/drivers/net/ethernet/xilinx/Kconfig
35 @@ -25,6 +25,14 @@ config XILINX_EMACLITE
36 ---help---
37 This driver supports the 10/100 Ethernet Lite from Xilinx.
39 +config XILINX_AXI_EMAC
40 + tristate "Xilinx 10/100/1000 AXI Ethernet support"
41 + depends on (PPC32 || MICROBLAZE)
42 + select PHYLIB
43 + ---help---
44 + This driver supports the 10/100/1000 Ethernet from Xilinx for the
45 + AXI bus interface used in Xilinx Virtex FPGAs.
46 +
47 config XILINX_LL_TEMAC
48 tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
49 depends on (PPC || MICROBLAZE)
50 diff --git a/drivers/net/ethernet/xilinx/Makefile b/drivers/net/ethernet/xilinx/Makefile
51 index 5feac73..214205e 100644
52 --- a/drivers/net/ethernet/xilinx/Makefile
53 +++ b/drivers/net/ethernet/xilinx/Makefile
54 @@ -5,3 +5,5 @@
55 ll_temac-objs := ll_temac_main.o ll_temac_mdio.o
56 obj-$(CONFIG_XILINX_LL_TEMAC) += ll_temac.o
57 obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
58 +xilinx_emac-objs := xilinx_axienet_main.o xilinx_axienet_mdio.o
59 +obj-$(CONFIG_XILINX_AXI_EMAC) += xilinx_emac.o
60 diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
61 new file mode 100644
62 index 0000000..cc83af0
63 --- /dev/null
64 +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
65 @@ -0,0 +1,508 @@
66 +/*
67 + * Definitions for Xilinx Axi Ethernet device driver.
68 + *
69 + * Copyright (c) 2009 Secret Lab Technologies, Ltd.
70 + * Copyright (c) 2010 Xilinx, Inc. All rights reserved.
71 + * Copyright (c) 2012 Daniel Borkmann, <daniel.borkmann@tik.ee.ethz.ch>
72 + * Copyright (c) 2012 Ariane Keller, <ariane.keller@tik.ee.ethz.ch>
73 + */
74 +
75 +#ifndef XILINX_AXIENET_H
76 +#define XILINX_AXIENET_H
77 +
78 +#include <linux/netdevice.h>
79 +#include <linux/spinlock.h>
80 +#include <linux/interrupt.h>
81 +
82 +/* Packet size info */
83 +#define XAE_HDR_SIZE 14 /* Size of Ethernet header */
84 +#define XAE_HDR_VLAN_SIZE 18 /* Size of an Ethernet hdr + VLAN */
85 +#define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */
86 +#define XAE_MTU 1500 /* Max MTU of an Ethernet frame */
87 +#define XAE_JUMBO_MTU 9000 /* Max MTU of a jumbo Eth. frame */
88 +
89 +#define XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
90 +#define XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + XAE_HDR_VLAN_SIZE + XAE_TRL_SIZE)
91 +#define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
92 +
93 +/* Configuration options */
94 +
95 +/* Accept all incoming packets. Default: disabled (cleared) */
96 +#define XAE_OPTION_PROMISC (1 << 0)
97 +
98 +/* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
99 +#define XAE_OPTION_JUMBO (1 << 1)
100 +
101 +/* VLAN Rx & Tx frame support. Default: disabled (cleared) */
102 +#define XAE_OPTION_VLAN (1 << 2)
103 +
104 +/* Enable recognition of flow control frames on Rx. Default: enabled (set) */
105 +#define XAE_OPTION_FLOW_CONTROL (1 << 4)
106 +
107 +/* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
108 + * stripped. Default: disabled (set) */
109 +#define XAE_OPTION_FCS_STRIP (1 << 5)
110 +
111 +/* Generate FCS field and add PAD automatically for outgoing frames.
112 + * Default: enabled (set) */
113 +#define XAE_OPTION_FCS_INSERT (1 << 6)
114 +
115 +/* Enable Length/Type error checking for incoming frames. When this option is
116 + * set, the MAC will filter frames that have a mismatched type/length field
117 + * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these
118 + * types of frames are encountered. When this option is cleared, the MAC will
119 + * allow these types of frames to be received. Default: enabled (set) */
120 +#define XAE_OPTION_LENTYPE_ERR (1 << 7)
121 +
122 +/* Enable the transmitter. Default: enabled (set) */
123 +#define XAE_OPTION_TXEN (1 << 11)
124 +
125 +/* Enable the receiver. Default: enabled (set) */
126 +#define XAE_OPTION_RXEN (1 << 12)
127 +
128 +/* Default options set when device is initialized or reset */
129 +#define XAE_OPTION_DEFAULTS \
130 + (XAE_OPTION_TXEN | \
131 + XAE_OPTION_FLOW_CONTROL | \
132 + XAE_OPTION_RXEN)
133 +
134 +/* Axi DMA Register definitions */
135 +
136 +#define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
137 +#define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
138 +#define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
139 +#define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
140 +
141 +#define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
142 +#define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
143 +#define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
144 +#define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
145 +
146 +#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
147 +#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
148 +
149 +#define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */
150 +#define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */
151 +#define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */
152 +#define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */
153 +#define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */
154 +#define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */
155 +#define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */
156 +#define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */
157 +#define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */
158 +#define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */
159 +#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */
160 +#define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */
161 +
162 +#define XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */
163 +#define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */
164 +#define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */
165 +
166 +#define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */
167 +#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
168 +#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
169 +#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
170 +
171 +#define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */
172 +#define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */
173 +
174 +#define XAXIDMA_DELAY_SHIFT 24
175 +#define XAXIDMA_COALESCE_SHIFT 16
176 +
177 +#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
178 +#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
179 +#define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */
180 +#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
181 +
182 +/* Default TX/RX Threshold and waitbound values for SGDMA mode */
183 +#define XAXIDMA_DFT_TX_THRESHOLD 24
184 +#define XAXIDMA_DFT_TX_WAITBOUND 254
185 +#define XAXIDMA_DFT_RX_THRESHOLD 24
186 +#define XAXIDMA_DFT_RX_WAITBOUND 254
187 +
188 +#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
189 +#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
190 +#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
191 +
192 +#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
193 +#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */
194 +#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */
195 +#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */
196 +#define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */
197 +#define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */
198 +#define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
199 +#define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
200 +#define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */
201 +
202 +#define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40
203 +
204 +/* Axi Ethernet registers definition */
205 +#define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */
206 +#define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */
207 +#define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
208 +#define XAE_IS_OFFSET 0x0000000C /* Interrupt status */
209 +#define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */
210 +#define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
211 +#define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */
212 +#define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
213 +#define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */
214 +#define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */
215 +#define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */
216 +#define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */
217 +#define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
218 +#define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */
219 +#define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
220 +#define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */
221 +#define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */
222 +#define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */
223 +#define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */
224 +#define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */
225 +#define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */
226 +#define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */
227 +#define XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */
228 +#define XAE_MDIO_MIS_OFFSET 0x00000600 /* MII Management Interrupt Status */
229 +#define XAE_MDIO_MIP_OFFSET 0x00000620 /* MII Mgmt Interrupt Pending
230 + * register offset */
231 +#define XAE_MDIO_MIE_OFFSET 0x00000640 /* MII Management Interrupt Enable
232 + * register offset */
233 +#define XAE_MDIO_MIC_OFFSET 0x00000660 /* MII Management Interrupt Clear
234 + * register offset. */
235 +#define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */
236 +#define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */
237 +#define XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */
238 +#define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */
239 +#define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */
240 +
241 +#define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
242 +#define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
243 +#define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */
244 +
245 +/* Bit Masks for Axi Ethernet RAF register */
246 +#define XAE_RAF_MCSTREJ_MASK 0x00000002 /* Reject receive multicast
247 + * destination address */
248 +#define XAE_RAF_BCSTREJ_MASK 0x00000004 /* Reject receive broadcast
249 + * destination address */
250 +#define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
251 +#define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
252 +#define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
253 +#define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
254 +#define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */
255 +#define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000 /* Exteneded Multicast
256 + * Filtering mode
257 + */
258 +#define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */
259 +#define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
260 +#define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */
261 +#define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */
262 +#define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/
263 +#define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/
264 +
265 +/* Bit Masks for Axi Ethernet TPF and IFGP registers */
266 +#define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */
267 +#define XAE_IFGP0_IFGP_MASK 0x0000007F /* Transmit inter-frame
268 + * gap adjustment value */
269 +
270 +/* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
271 + * for all 3 registers. */
272 +#define XAE_INT_HARDACSCMPLT_MASK 0x00000001 /* Hard register access
273 + * complete */
274 +#define XAE_INT_AUTONEG_MASK 0x00000002 /* Auto negotiation
275 + * complete */
276 +#define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
277 +#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
278 +#define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
279 +#define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */
280 +#define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */
281 +#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
282 +#define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
283 +#define XAE_INT_ALL_MASK 0x0000003F /* All the ints */
284 +
285 +#define XAE_INT_RECV_ERROR_MASK \
286 + (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK) /* INT bits that
287 + * indicate receive
288 + * errors */
289 +
290 +/* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
291 +#define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */
292 +#define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */
293 +
294 +/* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
295 +#define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */
296 +#define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */
297 +
298 +/* Bit masks for Axi Ethernet RCW1 register */
299 +#define XAE_RCW1_RST_MASK 0x80000000 /* Reset */
300 +#define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
301 +#define XAE_RCW1_FCS_MASK 0x20000000 /* In-Band FCS enable
302 + * (FCS not stripped) */
303 +#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
304 +#define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
305 +#define XAE_RCW1_LT_DIS_MASK 0x02000000 /* Length/type field valid check
306 + * disable */
307 +#define XAE_RCW1_CL_DIS_MASK 0x01000000 /* Control frame Length check
308 + * disable */
309 +#define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF /* Pause frame source address
310 + * bits [47:32]. Bits [31:0] are
311 + * stored in register RCW0 */
312 +
313 +/* Bit masks for Axi Ethernet TC register */
314 +#define XAE_TC_RST_MASK 0x80000000 /* Reset */
315 +#define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
316 +#define XAE_TC_FCS_MASK 0x20000000 /* In-Band FCS enable
317 + * (FCS not generated) */
318 +#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
319 +#define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
320 +#define XAE_TC_IFG_MASK 0x02000000 /* Inter-frame gap adjustment
321 + * enable */
322 +
323 +/* Bit masks for Axi Ethernet FCC register */
324 +#define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
325 +#define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
326 +
327 +/* Bit masks for Axi Ethernet EMMC register */
328 +#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
329 +#define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
330 +#define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
331 +#define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
332 +#define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */
333 +#define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
334 +#define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
335 +#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
336 +#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
337 +#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
338 +
339 +/* Bit masks for Axi Ethernet PHYC register */
340 +#define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/
341 +#define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */
342 +#define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
343 +#define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */
344 +#define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */
345 +#define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */
346 +#define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */
347 +#define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */
348 +#define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */
349 +#define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */
350 +
351 +/* Bit masks for Axi Ethernet MDIO interface MC register */
352 +#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */
353 +#define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */
354 +
355 +/* Bit masks for Axi Ethernet MDIO interface MCR register */
356 +#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
357 +#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
358 +#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
359 +#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
360 +#define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */
361 +#define XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */
362 +#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
363 +#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
364 +#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
365 +#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
366 +
367 +/* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
368 +#define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */
369 +
370 +/* Bit masks for Axi Ethernet UAW1 register */
371 +#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF /* Station address bits
372 + * [47:32]; Station address
373 + * bits [31:0] are stored in
374 + * register UAW0 */
375 +
376 +/* Bit masks for Axi Ethernet FMI register */
377 +#define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
378 +#define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */
379 +
380 +#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
381 +
382 +/* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
383 +#define XAE_PHY_TYPE_MII 0
384 +#define XAE_PHY_TYPE_GMII 1
385 +#define XAE_PHY_TYPE_RGMII_1_3 2
386 +#define XAE_PHY_TYPE_RGMII_2_0 3
387 +#define XAE_PHY_TYPE_SGMII 4
388 +#define XAE_PHY_TYPE_1000BASE_X 5
389 +
390 +#define XAE_MULTICAST_CAM_TABLE_NUM 4 /* Total number of entries in the
391 + * hardware multicast table. */
392 +
393 +/* Axi Ethernet Synthesis features */
394 +#define XAE_FEATURE_PARTIAL_RX_CSUM (1 << 0)
395 +#define XAE_FEATURE_PARTIAL_TX_CSUM (1 << 1)
396 +#define XAE_FEATURE_FULL_RX_CSUM (1 << 2)
397 +#define XAE_FEATURE_FULL_TX_CSUM (1 << 3)
398 +
399 +#define XAE_NO_CSUM_OFFLOAD 0
400 +
401 +#define XAE_FULL_CSUM_STATUS_MASK 0x00000038
402 +#define XAE_IP_UDP_CSUM_VALIDATED 0x00000003
403 +#define XAE_IP_TCP_CSUM_VALIDATED 0x00000002
404 +
405 +#define DELAY_OF_ONE_MILLISEC 1000
406 +
407 +/**
408 + * struct axidma_bd - Axi Dma buffer descriptor layout
409 + * @next: MM2S/S2MM Next Descriptor Pointer
410 + * @reserved1: Reserved and not used
411 + * @phys: MM2S/S2MM Buffer Address
412 + * @reserved2: Reserved and not used
413 + * @reserved3: Reserved and not used
414 + * @reserved4: Reserved and not used
415 + * @cntrl: MM2S/S2MM Control value
416 + * @status: MM2S/S2MM Status value
417 + * @app0: MM2S/S2MM User Application Field 0.
418 + * @app1: MM2S/S2MM User Application Field 1.
419 + * @app2: MM2S/S2MM User Application Field 2.
420 + * @app3: MM2S/S2MM User Application Field 3.
421 + * @app4: MM2S/S2MM User Application Field 4.
422 + * @sw_id_offset: MM2S/S2MM Sw ID
423 + * @reserved5: Reserved and not used
424 + * @reserved6: Reserved and not used
425 + */
426 +struct axidma_bd {
427 + u32 next; /* Physical address of next buffer descriptor */
428 + u32 reserved1;
429 + u32 phys;
430 + u32 reserved2;
431 + u32 reserved3;
432 + u32 reserved4;
433 + u32 cntrl;
434 + u32 status;
435 + u32 app0;
436 + u32 app1; /* TX start << 16 | insert */
437 + u32 app2; /* TX csum seed */
438 + u32 app3;
439 + u32 app4;
440 + u32 sw_id_offset;
441 + u32 reserved5;
442 + u32 reserved6;
443 +};
444 +
445 +/**
446 + * struct axienet_local - axienet private per device data
447 + * @ndev: Pointer for net_device to which it will be attached.
448 + * @dev: Pointer to device structure
449 + * @phy_dev: Pointer to PHY device structure attached to the axienet_local
450 + * @phy_node: Pointer to device node structure
451 + * @mii_bus: Pointer to MII bus structure
452 + * @mdio_irqs: IRQs table for MDIO bus required in mii_bus structure
453 + * @regs: Base address for the axienet_local device address space
454 + * @dma_regs: Base address for the axidma device address space
455 + * @dma_err_tasklet: Tasklet structure to process Axi DMA errors
456 + * @tx_irq: Axidma TX IRQ number
457 + * @rx_irq: Axidma RX IRQ number
458 + * @temac_type: axienet type to identify between soft and hard temac
459 + * @phy_type: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
460 + * @options: AxiEthernet option word
461 + * @last_link: Phy link state in which the PHY was negotiated earlier
462 + * @features: Stores the extended features supported by the axienet hw
463 + * @tx_bd_v: Virtual address of the TX buffer descriptor ring
464 + * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring
465 + * @rx_bd_v: Virtual address of the RX buffer descriptor ring
466 + * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring
467 + * @tx_bd_ci: Stores the index of the Tx buffer descriptor in the ring being
468 + * accessed currently. Used while alloc. BDs before a TX starts
469 + * @tx_bd_tail: Stores the index of the Tx buffer descriptor in the ring being
470 + * accessed currently. Used while processing BDs after the TX
471 + * completed.
472 + * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being
473 + * accessed currently.
474 + * @max_frm_size: Stores the maximum size of the frame that can be that
475 + * Txed/Rxed in the existing hardware. If jumbo option is
476 + * supported, the maximum frame size would be 9k. Else it is
477 + * 1522 bytes (assuming support for basic VLAN)
478 + * @jumbo_support: Stores hardware configuration for jumbo support. If hardware
479 + * can handle jumbo packets, this entry will be 1, else 0.
480 + */
481 +struct axienet_local {
482 + struct net_device *ndev;
483 + struct device *dev;
484 +
485 + /* Connection to PHY device */
486 + struct phy_device *phy_dev; /* Pointer to PHY device */
487 + struct device_node *phy_node;
488 +
489 + /* MDIO bus data */
490 + struct mii_bus *mii_bus; /* MII bus reference */
491 + int mdio_irqs[PHY_MAX_ADDR]; /* IRQs table for MDIO bus */
492 +
493 + /* IO registers, dma functions and IRQs */
494 + void __iomem *regs;
495 + void __iomem *dma_regs;
496 +
497 + struct tasklet_struct dma_err_tasklet;
498 +
499 + int tx_irq;
500 + int rx_irq;
501 + u32 temac_type;
502 + u32 phy_type;
503 +
504 + u32 options; /* Current options word */
505 + u32 last_link;
506 + u32 features;
507 +
508 + /* Buffer descriptors */
509 + struct axidma_bd *tx_bd_v;
510 + dma_addr_t tx_bd_p;
511 + struct axidma_bd *rx_bd_v;
512 + dma_addr_t rx_bd_p;
513 + u32 tx_bd_ci;
514 + u32 tx_bd_tail;
515 + u32 rx_bd_ci;
516 +
517 + u32 max_frm_size;
518 + u32 jumbo_support;
519 +
520 + int csum_offload_on_tx_path;
521 + int csum_offload_on_rx_path;
522 +
523 + u32 coalesce_count_rx;
524 + u32 coalesce_count_tx;
525 +};
526 +
527 +/**
528 + * struct axiethernet_option - Used to set axi ethernet hardware options
529 + * @opt: Option to be set.
530 + * @reg: Register offset to be written for setting the option
531 + * @m_or: Mask to be ORed for setting the option in the register
532 + */
533 +struct axienet_option {
534 + u32 opt;
535 + u32 reg;
536 + u32 m_or;
537 +};
538 +
539 +/**
540 + * axienet_ior - Memory mapped Axi Ethernet register read
541 + * @lp: Pointer to axienet local structure
542 + * @offset: Address offset from the base address of Axi Ethernet core
543 + *
544 + * returns: The contents of the Axi Ethernet register
545 + *
546 + * This function returns the contents of the corresponding register.
547 + */
548 +static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)
549 +{
550 + return in_be32(lp->regs + offset);
551 +}
552 +
553 +/**
554 + * axienet_iow - Memory mapped Axi Ethernet register write
555 + * @lp: Pointer to axienet local structure
556 + * @offset: Address offset from the base address of Axi Ethernet core
557 + * @value: Value to be written into the Axi Ethernet register
558 + *
559 + * This function writes the desired value into the corresponding Axi Ethernet
560 + * register.
561 + */
562 +static inline void axienet_iow(struct axienet_local *lp, off_t offset,
563 + u32 value)
564 +{
565 + out_be32((lp->regs + offset), value);
566 +}
567 +
568 +/* Function prototypes visible in xilinx_axienet_mdio.c for other files */
569 +int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np);
570 +int axienet_mdio_wait_until_ready(struct axienet_local *lp);
571 +void axienet_mdio_teardown(struct axienet_local *lp);
572 +
573 +#endif /* XILINX_AXI_ENET_H */
574 diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
575 new file mode 100644
576 index 0000000..7fe9a1b
577 --- /dev/null
578 +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
579 @@ -0,0 +1,1682 @@
580 +/*
581 + * Xilinx Axi Ethernet device driver
582 + *
583 + * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
584 + * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
585 + * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
586 + * Copyright (c) 2010 Xilinx, Inc. All rights reserved.
587 + * Copyright (c) 2012 Daniel Borkmann, <daniel.borkmann@tik.ee.ethz.ch>
588 + * Copyright (c) 2012 Ariane Keller, <ariane.keller@tik.ee.ethz.ch>
589 + *
590 + * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
591 + * and Spartan6.
592 + *
593 + * TODO:
594 + * - Add Axi Fifo support.
595 + * - Factor out Axi DMA code into separate driver.
596 + * - Test and fix basic multicast filtering.
597 + * - Add support for extended multicast filtering.
598 + * - Test basic VLAN support.
599 + * - Add support for extended VLAN support.
600 + */
601 +
602 +#include <linux/delay.h>
603 +#include <linux/etherdevice.h>
604 +#include <linux/init.h>
605 +#include <linux/module.h>
606 +#include <linux/netdevice.h>
607 +#include <linux/of_mdio.h>
608 +#include <linux/of_platform.h>
609 +#include <linux/of_address.h>
610 +#include <linux/skbuff.h>
611 +#include <linux/spinlock.h>
612 +#include <linux/phy.h>
613 +#include <linux/mii.h>
614 +#include <linux/ethtool.h>
615 +
616 +#include "xilinx_axienet.h"
617 +
618 +/* Descriptors defines for Tx and Rx DMA - 2^n for the best performance */
619 +#define TX_BD_NUM 64
620 +#define RX_BD_NUM 128
621 +
622 +/* Must be shorter than length of ethtool_drvinfo.driver field to fit */
623 +#define DRIVER_NAME "xaxienet"
624 +#define DRIVER_DESCRIPTION "Xilinx Axi Ethernet driver"
625 +#define DRIVER_VERSION "1.00a"
626 +
627 +#define AXIENET_REGS_N 32
628 +
629 +/* Match table for of_platform binding */
630 +static struct of_device_id axienet_of_match[] __devinitdata = {
631 + { .compatible = "xlnx,axi-ethernet-1.00.a", },
632 + { .compatible = "xlnx,axi-ethernet-1.01.a", },
633 + { .compatible = "xlnx,axi-ethernet-2.01.a", },
634 + {},
635 +};
636 +
637 +MODULE_DEVICE_TABLE(of, axienet_of_match);
638 +
639 +/* Option table for setting up Axi Ethernet hardware options */
640 +static struct axienet_option axienet_options[] = {
641 + /* Turn on jumbo packet support for both Rx and Tx */
642 + {
643 + .opt = XAE_OPTION_JUMBO,
644 + .reg = XAE_TC_OFFSET,
645 + .m_or = XAE_TC_JUM_MASK,
646 + }, {
647 + .opt = XAE_OPTION_JUMBO,
648 + .reg = XAE_RCW1_OFFSET,
649 + .m_or = XAE_RCW1_JUM_MASK,
650 + }, { /* Turn on VLAN packet support for both Rx and Tx */
651 + .opt = XAE_OPTION_VLAN,
652 + .reg = XAE_TC_OFFSET,
653 + .m_or = XAE_TC_VLAN_MASK,
654 + }, {
655 + .opt = XAE_OPTION_VLAN,
656 + .reg = XAE_RCW1_OFFSET,
657 + .m_or = XAE_RCW1_VLAN_MASK,
658 + }, { /* Turn on FCS stripping on receive packets */
659 + .opt = XAE_OPTION_FCS_STRIP,
660 + .reg = XAE_RCW1_OFFSET,
661 + .m_or = XAE_RCW1_FCS_MASK,
662 + }, { /* Turn on FCS insertion on transmit packets */
663 + .opt = XAE_OPTION_FCS_INSERT,
664 + .reg = XAE_TC_OFFSET,
665 + .m_or = XAE_TC_FCS_MASK,
666 + }, { /* Turn off length/type field checking on receive packets */
667 + .opt = XAE_OPTION_LENTYPE_ERR,
668 + .reg = XAE_RCW1_OFFSET,
669 + .m_or = XAE_RCW1_LT_DIS_MASK,
670 + }, { /* Turn on Rx flow control */
671 + .opt = XAE_OPTION_FLOW_CONTROL,
672 + .reg = XAE_FCC_OFFSET,
673 + .m_or = XAE_FCC_FCRX_MASK,
674 + }, { /* Turn on Tx flow control */
675 + .opt = XAE_OPTION_FLOW_CONTROL,
676 + .reg = XAE_FCC_OFFSET,
677 + .m_or = XAE_FCC_FCTX_MASK,
678 + }, { /* Turn on promiscuous frame filtering */
679 + .opt = XAE_OPTION_PROMISC,
680 + .reg = XAE_FMI_OFFSET,
681 + .m_or = XAE_FMI_PM_MASK,
682 + }, { /* Enable transmitter */
683 + .opt = XAE_OPTION_TXEN,
684 + .reg = XAE_TC_OFFSET,
685 + .m_or = XAE_TC_TX_MASK,
686 + }, { /* Enable receiver */
687 + .opt = XAE_OPTION_RXEN,
688 + .reg = XAE_RCW1_OFFSET,
689 + .m_or = XAE_RCW1_RX_MASK,
690 + },
691 + {}
692 +};
693 +
694 +/**
695 + * axienet_dma_in32 - Memory mapped Axi DMA register read
696 + * @lp: Pointer to axienet local structure
697 + * @reg: Address offset from the base address of the Axi DMA core
698 + *
699 + * returns: The contents of the Axi DMA register
700 + *
701 + * This function returns the contents of the corresponding Axi DMA register.
702 + */
703 +static inline u32 axienet_dma_in32(struct axienet_local *lp, off_t reg)
704 +{
705 + return in_be32(lp->dma_regs + reg);
706 +}
707 +
708 +/**
709 + * axienet_dma_out32 - Memory mapped Axi DMA register write.
710 + * @lp: Pointer to axienet local structure
711 + * @reg: Address offset from the base address of the Axi DMA core
712 + * @value: Value to be written into the Axi DMA register
713 + *
714 + * This function writes the desired value into the corresponding Axi DMA
715 + * register.
716 + */
717 +static inline void axienet_dma_out32(struct axienet_local *lp,
718 + off_t reg, u32 value)
719 +{
720 + out_be32((lp->dma_regs + reg), value);
721 +}
722 +
723 +/**
724 + * axienet_dma_bd_release - Release buffer descriptor rings
725 + * @ndev: Pointer to the net_device structure
726 + *
727 + * This function is used to release the descriptors allocated in
728 + * axienet_dma_bd_init. axienet_dma_bd_release is called when Axi Ethernet
729 + * driver stop api is called.
730 + */
731 +static void axienet_dma_bd_release(struct net_device *ndev)
732 +{
733 + int i;
734 + struct axienet_local *lp = netdev_priv(ndev);
735 +
736 + for (i = 0; i < RX_BD_NUM; i++) {
737 + dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
738 + lp->max_frm_size, DMA_FROM_DEVICE);
739 + dev_kfree_skb((struct sk_buff *)
740 + (lp->rx_bd_v[i].sw_id_offset));
741 + }
742 +
743 + if (lp->rx_bd_v) {
744 + dma_free_coherent(ndev->dev.parent,
745 + sizeof(*lp->rx_bd_v) * RX_BD_NUM,
746 + lp->rx_bd_v,
747 + lp->rx_bd_p);
748 + }
749 + if (lp->tx_bd_v) {
750 + dma_free_coherent(ndev->dev.parent,
751 + sizeof(*lp->tx_bd_v) * TX_BD_NUM,
752 + lp->tx_bd_v,
753 + lp->tx_bd_p);
754 + }
755 +}
756 +
757 +/**
758 + * axienet_dma_bd_init - Setup buffer descriptor rings for Axi DMA
759 + * @ndev: Pointer to the net_device structure
760 + *
761 + * returns: 0, on success
762 + * -ENOMEM, on failure
763 + *
764 + * This function is called to initialize the Rx and Tx DMA descriptor
765 + * rings. This initializes the descriptors with required default values
766 + * and is called when Axi Ethernet driver reset is called.
767 + */
768 +static int axienet_dma_bd_init(struct net_device *ndev)
769 +{
770 + u32 cr;
771 + int i;
772 + struct sk_buff *skb;
773 + struct axienet_local *lp = netdev_priv(ndev);
774 +
775 + /* Reset the indexes which are used for accessing the BDs */
776 + lp->tx_bd_ci = 0;
777 + lp->tx_bd_tail = 0;
778 + lp->rx_bd_ci = 0;
779 +
780 + /*
781 + * Allocate the Tx and Rx buffer descriptors.
782 + */
783 + lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
784 + sizeof(*lp->tx_bd_v) * TX_BD_NUM,
785 + &lp->tx_bd_p,
786 + GFP_KERNEL);
787 + if (!lp->tx_bd_v) {
788 + dev_err(&ndev->dev, "unable to allocate DMA Tx buffer "
789 + "descriptors");
790 + goto out;
791 + }
792 +
793 + lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
794 + sizeof(*lp->rx_bd_v) * RX_BD_NUM,
795 + &lp->rx_bd_p,
796 + GFP_KERNEL);
797 + if (!lp->rx_bd_v) {
798 + dev_err(&ndev->dev, "unable to allocate DMA Rx buffer "
799 + "descriptors");
800 + goto out;
801 + }
802 +
803 + memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
804 + for (i = 0; i < TX_BD_NUM; i++) {
805 + lp->tx_bd_v[i].next = lp->tx_bd_p +
806 + sizeof(*lp->tx_bd_v) *
807 + ((i + 1) % TX_BD_NUM);
808 + }
809 +
810 + memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
811 + for (i = 0; i < RX_BD_NUM; i++) {
812 + lp->rx_bd_v[i].next = lp->rx_bd_p +
813 + sizeof(*lp->rx_bd_v) *
814 + ((i + 1) % RX_BD_NUM);
815 +
816 + skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
817 + if (!skb) {
818 + dev_err(&ndev->dev, "alloc_skb error %d\n", i);
819 + goto out;
820 + }
821 +
822 + lp->rx_bd_v[i].sw_id_offset = (u32) skb;
823 + lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
824 + skb->data,
825 + lp->max_frm_size,
826 + DMA_FROM_DEVICE);
827 + lp->rx_bd_v[i].cntrl = lp->max_frm_size;
828 + }
829 +
830 + /* Start updating the Rx channel control register */
831 + cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
832 + /* Update the interrupt coalesce count */
833 + cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
834 + ((lp->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
835 + /* Update the delay timer count */
836 + cr = ((cr & ~XAXIDMA_DELAY_MASK) |
837 + (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
838 + /* Enable coalesce, delay timer and error interrupts */
839 + cr |= XAXIDMA_IRQ_ALL_MASK;
840 + /* Write to the Rx channel control register */
841 + axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
842 +
843 + /* Start updating the Tx channel control register */
844 + cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
845 + /* Update the interrupt coalesce count */
846 + cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
847 + ((lp->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
848 + /* Update the delay timer count */
849 + cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
850 + (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
851 + /* Enable coalesce, delay timer and error interrupts */
852 + cr |= XAXIDMA_IRQ_ALL_MASK;
853 + /* Write to the Tx channel control register */
854 + axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
855 +
856 + /* Populate the tail pointer and bring the Rx Axi DMA engine out of
857 + * halted state. This will make the Rx side ready for reception.*/
858 + axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
859 + cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
860 + axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
861 + cr | XAXIDMA_CR_RUNSTOP_MASK);
862 + axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
863 + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
864 +
865 + /* Write to the RS (Run-stop) bit in the Tx channel control register.
866 + * Tx channel is now ready to run. But only after we write to the
867 + * tail pointer register that the Tx channel will start transmitting */
868 + axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
869 + cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
870 + axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
871 + cr | XAXIDMA_CR_RUNSTOP_MASK);
872 +
873 + return 0;
874 +out:
875 + axienet_dma_bd_release(ndev);
876 + return -ENOMEM;
877 +}
878 +
879 +/**
880 + * axienet_set_mac_address - Write the MAC address
881 + * @ndev: Pointer to the net_device structure
882 + * @address: 6 byte Address to be written as MAC address
883 + *
884 + * This function is called to initialize the MAC address of the Axi Ethernet
885 + * core. It writes to the UAW0 and UAW1 registers of the core.
886 + */
887 +static void axienet_set_mac_address(struct net_device *ndev, void *address)
888 +{
889 + struct axienet_local *lp = netdev_priv(ndev);
890 +
891 + if (address)
892 + memcpy(ndev->dev_addr, address, ETH_ALEN);
893 + if (!is_valid_ether_addr(ndev->dev_addr))
894 + random_ether_addr(ndev->dev_addr);
895 +
896 + /* Set up unicast MAC address filter set its mac address */
897 + axienet_iow(lp, XAE_UAW0_OFFSET,
898 + (ndev->dev_addr[0]) |
899 + (ndev->dev_addr[1] << 8) |
900 + (ndev->dev_addr[2] << 16) |
901 + (ndev->dev_addr[3] << 24));
902 + axienet_iow(lp, XAE_UAW1_OFFSET,
903 + (((axienet_ior(lp, XAE_UAW1_OFFSET)) &
904 + ~XAE_UAW1_UNICASTADDR_MASK) |
905 + (ndev->dev_addr[4] |
906 + (ndev->dev_addr[5] << 8))));
907 +}
908 +
909 +/**
910 + * netdev_set_mac_address - Write the MAC address (from outside the driver)
911 + * @ndev: Pointer to the net_device structure
912 + * @p: 6 byte Address to be written as MAC address
913 + *
914 + * returns: 0 for all conditions. Presently, there is no failure case.
915 + *
916 + * This function is called to initialize the MAC address of the Axi Ethernet
917 + * core. It calls the core specific axienet_set_mac_address. This is the
918 + * function that goes into net_device_ops structure entry ndo_set_mac_address.
919 + */
920 +static int netdev_set_mac_address(struct net_device *ndev, void *p)
921 +{
922 + struct sockaddr *addr = p;
923 + axienet_set_mac_address(ndev, addr->sa_data);
924 + return 0;
925 +}
926 +
927 +/**
928 + * axienet_set_multicast_list - Prepare the multicast table
929 + * @ndev: Pointer to the net_device structure
930 + *
931 + * This function is called to initialize the multicast table during
932 + * initialization. The Axi Ethernet basic multicast support has a four-entry
933 + * multicast table which is initialized here. Additionally this function
934 + * goes into the net_device_ops structure entry ndo_set_multicast_list. This
935 + * means whenever the multicast table entries need to be updated this
936 + * function gets called.
937 + */
938 +static void axienet_set_multicast_list(struct net_device *ndev)
939 +{
940 + int i;
941 + u32 reg, af0reg, af1reg;
942 + struct axienet_local *lp = netdev_priv(ndev);
943 +
944 + if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
945 + netdev_mc_count(ndev) > XAE_MULTICAST_CAM_TABLE_NUM) {
946 + /* We must make the kernel realize we had to move into
947 + * promiscuous mode. If it was a promiscuous mode request
948 + * the flag is already set. If not we set it. */
949 + ndev->flags |= IFF_PROMISC;
950 + reg = axienet_ior(lp, XAE_FMI_OFFSET);
951 + reg |= XAE_FMI_PM_MASK;
952 + axienet_iow(lp, XAE_FMI_OFFSET, reg);
953 + dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
954 + } else if (!netdev_mc_empty(ndev)) {
955 + struct netdev_hw_addr *ha;
956 +
957 + i = 0;
958 + netdev_for_each_mc_addr(ha, ndev) {
959 + if (i >= XAE_MULTICAST_CAM_TABLE_NUM)
960 + break;
961 +
962 + af0reg = (ha->addr[0]);
963 + af0reg |= (ha->addr[1] << 8);
964 + af0reg |= (ha->addr[2] << 16);
965 + af0reg |= (ha->addr[3] << 24);
966 +
967 + af1reg = (ha->addr[4]);
968 + af1reg |= (ha->addr[5] << 8);
969 +
970 + reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
971 + reg |= i;
972 +
973 + axienet_iow(lp, XAE_FMI_OFFSET, reg);
974 + axienet_iow(lp, XAE_AF0_OFFSET, af0reg);
975 + axienet_iow(lp, XAE_AF1_OFFSET, af1reg);
976 + i++;
977 + }
978 + } else {
979 + reg = axienet_ior(lp, XAE_FMI_OFFSET);
980 + reg &= ~XAE_FMI_PM_MASK;
981 +
982 + axienet_iow(lp, XAE_FMI_OFFSET, reg);
983 +
984 + for (i = 0; i < XAE_MULTICAST_CAM_TABLE_NUM; i++) {
985 + reg = axienet_ior(lp, XAE_FMI_OFFSET) & 0xFFFFFF00;
986 + reg |= i;
987 +
988 + axienet_iow(lp, XAE_FMI_OFFSET, reg);
989 + axienet_iow(lp, XAE_AF0_OFFSET, 0);
990 + axienet_iow(lp, XAE_AF1_OFFSET, 0);
991 + }
992 +
993 + dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
994 + }
995 +}
996 +
997 +/**
998 + * axienet_setoptions - Set an Axi Ethernet option
999 + * @ndev: Pointer to the net_device structure
1000 + * @options: Option to be enabled/disabled
1001 + *
1002 + * The Axi Ethernet core has multiple features which can be selectively turned
1003 + * on or off. The typical options could be jumbo frame option, basic VLAN
1004 + * option, promiscuous mode option etc. This function is used to set or clear
1005 + * these options in the Axi Ethernet hardware. This is done through
1006 + * axienet_option structure .
1007 + */
1008 +static void axienet_setoptions(struct net_device *ndev, u32 options)
1009 +{
1010 + int reg;
1011 + struct axienet_local *lp = netdev_priv(ndev);
1012 + struct axienet_option *tp = &axienet_options[0];
1013 +
1014 + while (tp->opt) {
1015 + reg = ((axienet_ior(lp, tp->reg)) & ~(tp->m_or));
1016 + if (options & tp->opt)
1017 + reg |= tp->m_or;
1018 + axienet_iow(lp, tp->reg, reg);
1019 + tp++;
1020 + }
1021 +
1022 + lp->options |= options;
1023 +}
1024 +
1025 +static void __axienet_device_reset(struct axienet_local *lp,
1026 + struct device *dev, off_t offset)
1027 +{
1028 + u32 timeout;
1029 + /* Reset Axi DMA. This would reset Axi Ethernet core as well. The reset
1030 + * process of Axi DMA takes a while to complete as all pending
1031 + * commands/transfers will be flushed or completed during this
1032 + * reset process. */
1033 + axienet_dma_out32(lp, offset, XAXIDMA_CR_RESET_MASK);
1034 + timeout = DELAY_OF_ONE_MILLISEC;
1035 + while (axienet_dma_in32(lp, offset) & XAXIDMA_CR_RESET_MASK) {
1036 + udelay(1);
1037 + if (--timeout == 0) {
1038 + dev_err(dev, "axienet_device_reset DMA "
1039 + "reset timeout!\n");
1040 + break;
1041 + }
1042 + }
1043 +}
1044 +
1045 +/**
1046 + * axienet_device_reset - Reset and initialize the Axi Ethernet hardware.
1047 + * @ndev: Pointer to the net_device structure
1048 + *
1049 + * This function is called to reset and initialize the Axi Ethernet core. This
1050 + * is typically called during initialization. It does a reset of the Axi DMA
1051 + * Rx/Tx channels and initializes the Axi DMA BDs. Since Axi DMA reset lines
1052 + * areconnected to Axi Ethernet reset lines, this in turn resets the Axi
1053 + * Ethernet core. No separate hardware reset is done for the Axi Ethernet
1054 + * core.
1055 + */
1056 +static void axienet_device_reset(struct net_device *ndev)
1057 +{
1058 + u32 axienet_status;
1059 + struct axienet_local *lp = netdev_priv(ndev);
1060 +
1061 + __axienet_device_reset(lp, &ndev->dev, XAXIDMA_TX_CR_OFFSET);
1062 + __axienet_device_reset(lp, &ndev->dev, XAXIDMA_RX_CR_OFFSET);
1063 +
1064 + lp->max_frm_size = XAE_MAX_VLAN_FRAME_SIZE;
1065 + lp->options &= (~XAE_OPTION_JUMBO);
1066 +
1067 + if ((ndev->mtu > XAE_MTU) &&
1068 + (ndev->mtu <= XAE_JUMBO_MTU) &&
1069 + (lp->jumbo_support)) {
1070 + lp->max_frm_size = ndev->mtu + XAE_HDR_VLAN_SIZE +
1071 + XAE_TRL_SIZE;
1072 + lp->options |= XAE_OPTION_JUMBO;
1073 + }
1074 +
1075 + if (axienet_dma_bd_init(ndev)) {
1076 + dev_err(&ndev->dev, "axienet_device_reset descriptor "
1077 + "allocation failed\n");
1078 + }
1079 +
1080 + axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
1081 + axienet_status &= ~XAE_RCW1_RX_MASK;
1082 + axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
1083 +
1084 + axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
1085 + if (axienet_status & XAE_INT_RXRJECT_MASK)
1086 + axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
1087 +
1088 + axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
1089 +
1090 + /* Sync default options with HW but leave receiver and
1091 + * transmitter disabled.*/
1092 + axienet_setoptions(ndev, lp->options &
1093 + ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1094 + axienet_set_mac_address(ndev, NULL);
1095 + axienet_set_multicast_list(ndev);
1096 + axienet_setoptions(ndev, lp->options);
1097 +
1098 + ndev->trans_start = jiffies;
1099 +}
1100 +
1101 +/**
1102 + * axienet_adjust_link - Adjust the PHY link speed/duplex.
1103 + * @ndev: Pointer to the net_device structure
1104 + *
1105 + * This function is called to change the speed and duplex setting after
1106 + * auto negotiation is done by the PHY. This is the function that gets
1107 + * registered with the PHY interface through the "of_phy_connect" call.
1108 + */
1109 +static void axienet_adjust_link(struct net_device *ndev)
1110 +{
1111 + u32 emmc_reg;
1112 + u32 link_state;
1113 + u32 setspeed = 1;
1114 + struct axienet_local *lp = netdev_priv(ndev);
1115 + struct phy_device *phy = lp->phy_dev;
1116 +
1117 + link_state = phy->speed | (phy->duplex << 1) | phy->link;
1118 + if (lp->last_link != link_state) {
1119 + if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) {
1120 + if (lp->phy_type == XAE_PHY_TYPE_1000BASE_X)
1121 + setspeed = 0;
1122 + } else {
1123 + if ((phy->speed == SPEED_1000) &&
1124 + (lp->phy_type == XAE_PHY_TYPE_MII))
1125 + setspeed = 0;
1126 + }
1127 +
1128 + if (setspeed == 1) {
1129 + emmc_reg = axienet_ior(lp, XAE_EMMC_OFFSET);
1130 + emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
1131 +
1132 + switch (phy->speed) {
1133 + case SPEED_1000:
1134 + emmc_reg |= XAE_EMMC_LINKSPD_1000;
1135 + break;
1136 + case SPEED_100:
1137 + emmc_reg |= XAE_EMMC_LINKSPD_100;
1138 + break;
1139 + case SPEED_10:
1140 + emmc_reg |= XAE_EMMC_LINKSPD_10;
1141 + break;
1142 + default:
1143 + dev_err(&ndev->dev, "Speed other than 10, 100 "
1144 + "or 1Gbps is not supported\n");
1145 + break;
1146 + }
1147 +
1148 + axienet_iow(lp, XAE_EMMC_OFFSET, emmc_reg);
1149 + lp->last_link = link_state;
1150 + phy_print_status(phy);
1151 + } else {
1152 + dev_err(&ndev->dev, "Error setting Axi Ethernet "
1153 + "mac speed\n");
1154 + }
1155 + }
1156 +}
1157 +
1158 +/**
1159 + * axienet_start_xmit_done - Invoked once a transmit is completed by the
1160 + * Axi DMA Tx channel.
1161 + * @ndev: Pointer to the net_device structure
1162 + *
1163 + * This function is invoked from the Axi DMA Tx isr to notify the completion
1164 + * of transmit operation. It clears fields in the corresponding Tx BDs and
1165 + * unmaps the corresponding buffer so that CPU can regain ownership of the
1166 + * buffer. It finally invokes "netif_wake_queue" to restart transmission if
1167 + * required.
1168 + */
1169 +static void axienet_start_xmit_done(struct net_device *ndev)
1170 +{
1171 + u32 size = 0;
1172 + u32 packets = 0;
1173 + struct axienet_local *lp = netdev_priv(ndev);
1174 + struct axidma_bd *cur_p;
1175 + unsigned int status = 0;
1176 +
1177 + cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
1178 + status = cur_p->status;
1179 + while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
1180 + dma_unmap_single(ndev->dev.parent, cur_p->phys,
1181 + (cur_p->cntrl & XAXIDMA_BD_CTRL_LENGTH_MASK),
1182 + DMA_TO_DEVICE);
1183 + if (cur_p->app4)
1184 + dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
1185 + /*cur_p->phys = 0;*/
1186 + cur_p->app0 = 0;
1187 + cur_p->app1 = 0;
1188 + cur_p->app2 = 0;
1189 + cur_p->app4 = 0;
1190 + cur_p->status = 0;
1191 +
1192 + size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
1193 + packets++;
1194 +
1195 + lp->tx_bd_ci = ++lp->tx_bd_ci % TX_BD_NUM;
1196 + cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
1197 + status = cur_p->status;
1198 + }
1199 +
1200 + ndev->stats.tx_packets += packets;
1201 + ndev->stats.tx_bytes += size;
1202 + netif_wake_queue(ndev);
1203 +}
1204 +
1205 +/**
1206 + * axienet_check_tx_bd_space - Checks if a BD/group of BDs are currently busy
1207 + * @lp: Pointer to the axienet_local structure
1208 + * @num_frag: The number of BDs to check for
1209 + *
1210 + * returns: 0, on success
1211 + * NETDEV_TX_BUSY, if any of the descriptors are not free
1212 + *
1213 + * This function is invoked before BDs are allocated and transmission starts.
1214 + * This function returns 0 if a BD or group of BDs can be allocated for
1215 + * transmission. If the BD or any of the BDs are not free the function
1216 + * returns a busy status. This is invoked from axienet_start_xmit.
1217 + */
1218 +static inline int axienet_check_tx_bd_space(struct axienet_local *lp,
1219 + int num_frag)
1220 +{
1221 + struct axidma_bd *cur_p;
1222 + cur_p = &lp->tx_bd_v[(lp->tx_bd_tail + num_frag) % TX_BD_NUM];
1223 + if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
1224 + return NETDEV_TX_BUSY;
1225 + return 0;
1226 +}
1227 +
1228 +/**
1229 + * axienet_start_xmit - Starts the transmission.
1230 + * @skb: sk_buff pointer that contains data to be Txed.
1231 + * @ndev: Pointer to net_device structure.
1232 + *
1233 + * returns: NETDEV_TX_OK, on success
1234 + * NETDEV_TX_BUSY, if any of the descriptors are not free
1235 + *
1236 + * This function is invoked from upper layers to initiate transmission. The
1237 + * function uses the next available free BDs and populates their fields to
1238 + * start the transmission. Additionally if checksum offloading is supported,
1239 + * it populates AXI Stream Control fields with appropriate values.
1240 + */
1241 +static int axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1242 +{
1243 + u32 ii;
1244 + u32 num_frag;
1245 + u32 csum_start_off;
1246 + u32 csum_index_off;
1247 + skb_frag_t *frag;
1248 + dma_addr_t tail_p;
1249 + struct axienet_local *lp = netdev_priv(ndev);
1250 + struct axidma_bd *cur_p;
1251 +
1252 + num_frag = skb_shinfo(skb)->nr_frags;
1253 + cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
1254 +
1255 + if (axienet_check_tx_bd_space(lp, num_frag)) {
1256 + if (!netif_queue_stopped(ndev))
1257 + netif_stop_queue(ndev);
1258 + return NETDEV_TX_BUSY;
1259 + }
1260 +
1261 + if (skb->ip_summed == CHECKSUM_PARTIAL) {
1262 + if (lp->features & XAE_FEATURE_FULL_TX_CSUM) {
1263 + /* Tx Full Checksum Offload Enabled */
1264 + cur_p->app0 |= 2;
1265 + } else if (lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) {
1266 + csum_start_off = skb_transport_offset(skb);
1267 + csum_index_off = csum_start_off + skb->csum_offset;
1268 + /* Tx Partial Checksum Offload Enabled */
1269 + cur_p->app0 |= 1;
1270 + cur_p->app1 = (csum_start_off << 16) | csum_index_off;
1271 + }
1272 + } else if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1273 + cur_p->app0 |= 2; /* Tx Full Checksum Offload Enabled */
1274 + }
1275 +
1276 + cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
1277 + cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
1278 + skb_headlen(skb), DMA_TO_DEVICE);
1279 +
1280 + for (ii = 0; ii < num_frag; ii++) {
1281 + lp->tx_bd_tail = ++lp->tx_bd_tail % TX_BD_NUM;
1282 + cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
1283 + frag = &skb_shinfo(skb)->frags[ii];
1284 + cur_p->phys = dma_map_single(ndev->dev.parent,
1285 + skb_frag_address(frag),
1286 + skb_frag_size(frag),
1287 + DMA_TO_DEVICE);
1288 + cur_p->cntrl = skb_frag_size(frag);
1289 + }
1290 +
1291 + cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
1292 + cur_p->app4 = (unsigned long)skb;
1293 +
1294 + tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
1295 + /* Start the transfer */
1296 + axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
1297 + lp->tx_bd_tail = ++lp->tx_bd_tail % TX_BD_NUM;
1298 +
1299 + return NETDEV_TX_OK;
1300 +}
1301 +
1302 +/**
1303 + * axienet_recv - Is called from Axi DMA Rx Isr to complete the received
1304 + * BD processing.
1305 + * @ndev: Pointer to net_device structure.
1306 + *
1307 + * This function is invoked from the Axi DMA Rx isr to process the Rx BDs. It
1308 + * does minimal processing and invokes "netif_rx" to complete further
1309 + * processing.
1310 + */
1311 +static void axienet_recv(struct net_device *ndev)
1312 +{
1313 + u32 length;
1314 + u32 csumstatus;
1315 + u32 size = 0;
1316 + u32 packets = 0;
1317 + dma_addr_t tail_p;
1318 + struct axienet_local *lp = netdev_priv(ndev);
1319 + struct sk_buff *skb, *new_skb;
1320 + struct axidma_bd *cur_p;
1321 +
1322 + tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
1323 + cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
1324 +
1325 + while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK)) {
1326 + skb = (struct sk_buff *) (cur_p->sw_id_offset);
1327 + length = cur_p->app4 & 0x0000FFFF;
1328 +
1329 + dma_unmap_single(ndev->dev.parent, cur_p->phys,
1330 + lp->max_frm_size,
1331 + DMA_FROM_DEVICE);
1332 +
1333 + skb_put(skb, length);
1334 + skb->protocol = eth_type_trans(skb, ndev);
1335 + /*skb_checksum_none_assert(skb);*/
1336 + skb->ip_summed = CHECKSUM_NONE;
1337 +
1338 + /* if we're doing Rx csum offload, set it up */
1339 + if (lp->features & XAE_FEATURE_FULL_RX_CSUM) {
1340 + csumstatus = (cur_p->app2 &
1341 + XAE_FULL_CSUM_STATUS_MASK) >> 3;
1342 + if ((csumstatus == XAE_IP_TCP_CSUM_VALIDATED) ||
1343 + (csumstatus == XAE_IP_UDP_CSUM_VALIDATED)) {
1344 + skb->ip_summed = CHECKSUM_UNNECESSARY;
1345 + }
1346 + } else if ((lp->features & XAE_FEATURE_PARTIAL_RX_CSUM) != 0 &&
1347 + skb->protocol == __constant_htons(ETH_P_IP) &&
1348 + skb->len > 64) {
1349 + skb->csum = be32_to_cpu(cur_p->app3 & 0xFFFF);
1350 + skb->ip_summed = CHECKSUM_COMPLETE;
1351 + }
1352 +
1353 + netif_rx(skb);
1354 +
1355 + size += length;
1356 + packets++;
1357 +
1358 + new_skb = netdev_alloc_skb_ip_align(ndev, lp->max_frm_size);
1359 + if (!new_skb) {
1360 + dev_err(&ndev->dev, "no memory for new sk_buff\n");
1361 + return;
1362 + }
1363 + cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
1364 + lp->max_frm_size,
1365 + DMA_FROM_DEVICE);
1366 + cur_p->cntrl = lp->max_frm_size;
1367 + cur_p->status = 0;
1368 + cur_p->sw_id_offset = (u32) new_skb;
1369 +
1370 + lp->rx_bd_ci = ++lp->rx_bd_ci % RX_BD_NUM;
1371 + cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
1372 + }
1373 +
1374 + ndev->stats.rx_packets += packets;
1375 + ndev->stats.rx_bytes += size;
1376 +
1377 + axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
1378 +}
1379 +
1380 +/**
1381 + * axienet_tx_irq - Tx Done Isr.
1382 + * @irq: irq number
1383 + * @_ndev: net_device pointer
1384 + *
1385 + * returns: IRQ_HANDLED for all cases.
1386 + *
1387 + * This is the Axi DMA Tx done Isr. It invokes "axienet_start_xmit_done"
1388 + * to complete the BD processing.
1389 + */
1390 +static irqreturn_t axienet_tx_irq(int irq, void *_ndev)
1391 +{
1392 + u32 cr;
1393 + unsigned int status;
1394 + struct net_device *ndev = _ndev;
1395 + struct axienet_local *lp = netdev_priv(ndev);
1396 +
1397 + status = axienet_dma_in32(lp, XAXIDMA_TX_SR_OFFSET);
1398 + if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
1399 + axienet_start_xmit_done(lp->ndev);
1400 + goto out;
1401 + }
1402 + if (!(status & XAXIDMA_IRQ_ALL_MASK))
1403 + dev_err(&ndev->dev, "No interrupts asserted in Tx path");
1404 + if (status & XAXIDMA_IRQ_ERROR_MASK) {
1405 + dev_err(&ndev->dev, "DMA Tx error 0x%x\n", status);
1406 + dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
1407 + (lp->tx_bd_v[lp->tx_bd_ci]).phys);
1408 +
1409 + cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1410 + /* Disable coalesce, delay timer and error interrupts */
1411 + cr &= (~XAXIDMA_IRQ_ALL_MASK);
1412 + /* Write to the Tx channel control register */
1413 + axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1414 +
1415 + cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1416 + /* Disable coalesce, delay timer and error interrupts */
1417 + cr &= (~XAXIDMA_IRQ_ALL_MASK);
1418 + /* Write to the Rx channel control register */
1419 + axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1420 +
1421 + tasklet_schedule(&lp->dma_err_tasklet);
1422 + }
1423 +out:
1424 + axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, status);
1425 + return IRQ_HANDLED;
1426 +}
1427 +
1428 +/**
1429 + * axienet_rx_irq - Rx Isr.
1430 + * @irq: irq number
1431 + * @_ndev: net_device pointer
1432 + *
1433 + * returns: IRQ_HANDLED for all cases.
1434 + *
1435 + * This is the Axi DMA Rx Isr. It invokes "axienet_recv" to complete the BD
1436 + * processing.
1437 + */
1438 +static irqreturn_t axienet_rx_irq(int irq, void *_ndev)
1439 +{
1440 + u32 cr;
1441 + unsigned int status;
1442 + struct net_device *ndev = _ndev;
1443 + struct axienet_local *lp = netdev_priv(ndev);
1444 +
1445 + status = axienet_dma_in32(lp, XAXIDMA_RX_SR_OFFSET);
1446 + if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
1447 + axienet_recv(lp->ndev);
1448 + goto out;
1449 + }
1450 + if (!(status & XAXIDMA_IRQ_ALL_MASK))
1451 + dev_err(&ndev->dev, "No interrupts asserted in Rx path");
1452 + if (status & XAXIDMA_IRQ_ERROR_MASK) {
1453 + dev_err(&ndev->dev, "DMA Rx error 0x%x\n", status);
1454 + dev_err(&ndev->dev, "Current BD is at: 0x%x\n",
1455 + (lp->rx_bd_v[lp->rx_bd_ci]).phys);
1456 +
1457 + cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1458 + /* Disable coalesce, delay timer and error interrupts */
1459 + cr &= (~XAXIDMA_IRQ_ALL_MASK);
1460 + /* Finally write to the Tx channel control register */
1461 + axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
1462 +
1463 + cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1464 + /* Disable coalesce, delay timer and error interrupts */
1465 + cr &= (~XAXIDMA_IRQ_ALL_MASK);
1466 + /* write to the Rx channel control register */
1467 + axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1468 +
1469 + tasklet_schedule(&lp->dma_err_tasklet);
1470 + }
1471 +out:
1472 + axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, status);
1473 + return IRQ_HANDLED;
1474 +}
1475 +
1476 +/**
1477 + * axienet_open - Driver open routine.
1478 + * @ndev: Pointer to net_device structure
1479 + *
1480 + * returns: 0, on success.
1481 + * -ENODEV, if PHY cannot be connected to
1482 + * non-zero error value on failure
1483 + *
1484 + * This is the driver open routine. It calls phy_start to start the PHY device.
1485 + * It also allocates interrupt service routines, enables the interrupt lines
1486 + * and ISR handling. Axi Ethernet core is reset through Axi DMA core. Buffer
1487 + * descriptors are initialized.
1488 + */
1489 +static int axienet_open(struct net_device *ndev)
1490 +{
1491 + int ret, mdio_mcreg;
1492 + struct axienet_local *lp = netdev_priv(ndev);
1493 +
1494 + dev_dbg(&ndev->dev, "axienet_open()\n");
1495 +
1496 + mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1497 + ret = axienet_mdio_wait_until_ready(lp);
1498 + if (ret < 0)
1499 + return ret;
1500 + /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1501 + * When we do an Axi Ethernet reset, it resets the complete core
1502 + * including the MDIO. If MDIO is not disabled when the reset
1503 + * process is started, MDIO will be broken afterwards. */
1504 + axienet_iow(lp, XAE_MDIO_MC_OFFSET,
1505 + (mdio_mcreg & (~XAE_MDIO_MC_MDIOEN_MASK)));
1506 + axienet_device_reset(ndev);
1507 + /* Enable the MDIO */
1508 + axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
1509 + ret = axienet_mdio_wait_until_ready(lp);
1510 + if (ret < 0)
1511 + return ret;
1512 +
1513 + if (lp->phy_node) {
1514 + lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
1515 + axienet_adjust_link, 0,
1516 + PHY_INTERFACE_MODE_GMII);
1517 + if (!lp->phy_dev) {
1518 + dev_err(lp->dev, "of_phy_connect() failed\n");
1519 + return -ENODEV;
1520 + }
1521 + phy_start(lp->phy_dev);
1522 + }
1523 +
1524 + /* Enable interrupts for Axi DMA Tx */
1525 + ret = request_irq(lp->tx_irq, axienet_tx_irq, 0, ndev->name, ndev);
1526 + if (ret)
1527 + goto err_tx_irq;
1528 + /* Enable interrupts for Axi DMA Rx */
1529 + ret = request_irq(lp->rx_irq, axienet_rx_irq, 0, ndev->name, ndev);
1530 + if (ret)
1531 + goto err_rx_irq;
1532 + /* Enable tasklets for Axi DMA error handling */
1533 + tasklet_enable(&lp->dma_err_tasklet);
1534 + return 0;
1535 +
1536 +err_rx_irq:
1537 + free_irq(lp->tx_irq, ndev);
1538 +err_tx_irq:
1539 + if (lp->phy_dev)
1540 + phy_disconnect(lp->phy_dev);
1541 + lp->phy_dev = NULL;
1542 + dev_err(lp->dev, "request_irq() failed\n");
1543 + return ret;
1544 +}
1545 +
1546 +/**
1547 + * axienet_stop - Driver stop routine.
1548 + * @ndev: Pointer to net_device structure
1549 + *
1550 + * returns: 0, on success.
1551 + *
1552 + * This is the driver stop routine. It calls phy_disconnect to stop the PHY
1553 + * device. It also removes the interrupt handlers and disables the interrupts.
1554 + * The Axi DMA Tx/Rx BDs are released.
1555 + */
1556 +static int axienet_stop(struct net_device *ndev)
1557 +{
1558 + u32 cr;
1559 + struct axienet_local *lp = netdev_priv(ndev);
1560 +
1561 + dev_dbg(&ndev->dev, "axienet_close()\n");
1562 +
1563 + cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1564 + axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
1565 + cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1566 + cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1567 + axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
1568 + cr & (~XAXIDMA_CR_RUNSTOP_MASK));
1569 + axienet_setoptions(ndev, lp->options &
1570 + ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1571 +
1572 + tasklet_disable(&lp->dma_err_tasklet);
1573 +
1574 + free_irq(lp->tx_irq, ndev);
1575 + free_irq(lp->rx_irq, ndev);
1576 +
1577 + if (lp->phy_dev)
1578 + phy_disconnect(lp->phy_dev);
1579 + lp->phy_dev = NULL;
1580 +
1581 + axienet_dma_bd_release(ndev);
1582 + return 0;
1583 +}
1584 +
1585 +/**
1586 + * axienet_change_mtu - Driver change mtu routine.
1587 + * @ndev: Pointer to net_device structure
1588 + * @new_mtu: New mtu value to be applied
1589 + *
1590 + * returns: Always returns 0 (success).
1591 + *
1592 + * This is the change mtu driver routine. It checks if the Axi Ethernet
1593 + * hardware supports jumbo frames before changing the mtu. This can be
1594 + * called only when the device is not up.
1595 + */
1596 +static int axienet_change_mtu(struct net_device *ndev, int new_mtu)
1597 +{
1598 + struct axienet_local *lp = netdev_priv(ndev);
1599 +
1600 + if (netif_running(ndev))
1601 + return -EBUSY;
1602 + if (lp->jumbo_support) {
1603 + if ((new_mtu > XAE_JUMBO_MTU) || (new_mtu < 64))
1604 + return -EINVAL;
1605 + ndev->mtu = new_mtu;
1606 + } else {
1607 + if ((new_mtu > XAE_MTU) || (new_mtu < 64))
1608 + return -EINVAL;
1609 + ndev->mtu = new_mtu;
1610 + }
1611 +
1612 + return 0;
1613 +}
1614 +
1615 +#ifdef CONFIG_NET_POLL_CONTROLLER
1616 +/**
1617 + * axienet_poll_controller - Axi Ethernet poll mechanism.
1618 + * @ndev: Pointer to net_device structure
1619 + *
1620 + * This implements Rx/Tx ISR poll mechanisms. The interrupts are disabled prior
1621 + * to polling the ISRs and are enabled back after the polling is done.
1622 + */
1623 +static void axienet_poll_controller(struct net_device *ndev)
1624 +{
1625 + struct axienet_local *lp = netdev_priv(ndev);
1626 + disable_irq(lp->tx_irq);
1627 + disable_irq(lp->rx_irq);
1628 + axienet_rx_irq(lp->tx_irq, ndev);
1629 + axienet_tx_irq(lp->rx_irq, ndev);
1630 + enable_irq(lp->tx_irq);
1631 + enable_irq(lp->rx_irq);
1632 +}
1633 +#endif
1634 +
1635 +static const struct net_device_ops axienet_netdev_ops = {
1636 + .ndo_open = axienet_open,
1637 + .ndo_stop = axienet_stop,
1638 + .ndo_start_xmit = axienet_start_xmit,
1639 + .ndo_change_mtu = axienet_change_mtu,
1640 + .ndo_set_mac_address = netdev_set_mac_address,
1641 + .ndo_validate_addr = eth_validate_addr,
1642 + .ndo_set_rx_mode = axienet_set_multicast_list,
1643 +#ifdef CONFIG_NET_POLL_CONTROLLER
1644 + .ndo_poll_controller = axienet_poll_controller,
1645 +#endif
1646 +};
1647 +
1648 +/**
1649 + * axienet_ethtools_get_settings - Get Axi Ethernet settings related to PHY.
1650 + * @ndev: Pointer to net_device structure
1651 + * @ecmd: Pointer to ethtool_cmd structure
1652 + *
1653 + * This implements ethtool command for getting PHY settings. If PHY could
1654 + * not be found, the function returns -ENODEV. This function calls the
1655 + * relevant PHY ethtool API to get the PHY settings.
1656 + * Issue "ethtool ethX" under linux prompt to execute this function.
1657 + */
1658 +static int axienet_ethtools_get_settings(struct net_device *ndev,
1659 + struct ethtool_cmd *ecmd)
1660 +{
1661 + struct axienet_local *lp = netdev_priv(ndev);
1662 + struct phy_device *phydev = lp->phy_dev;
1663 + if (!phydev)
1664 + return -ENODEV;
1665 + return phy_ethtool_gset(phydev, ecmd);
1666 +}
1667 +
1668 +/**
1669 + * axienet_ethtools_set_settings - Set PHY settings as passed in the argument.
1670 + * @ndev: Pointer to net_device structure
1671 + * @ecmd: Pointer to ethtool_cmd structure
1672 + *
1673 + * This implements ethtool command for setting various PHY settings. If PHY
1674 + * could not be found, the function returns -ENODEV. This function calls the
1675 + * relevant PHY ethtool API to set the PHY.
1676 + * Issue e.g. "ethtool -s ethX speed 1000" under linux prompt to execute this
1677 + * function.
1678 + */
1679 +static int axienet_ethtools_set_settings(struct net_device *ndev,
1680 + struct ethtool_cmd *ecmd)
1681 +{
1682 + struct axienet_local *lp = netdev_priv(ndev);
1683 + struct phy_device *phydev = lp->phy_dev;
1684 + if (!phydev)
1685 + return -ENODEV;
1686 + return phy_ethtool_sset(phydev, ecmd);
1687 +}
1688 +
1689 +/**
1690 + * axienet_ethtools_get_drvinfo - Get various Axi Ethernet driver information.
1691 + * @ndev: Pointer to net_device structure
1692 + * @ed: Pointer to ethtool_drvinfo structure
1693 + *
1694 + * This implements ethtool command for getting the driver information.
1695 + * Issue "ethtool -i ethX" under linux prompt to execute this function.
1696 + */
1697 +static void axienet_ethtools_get_drvinfo(struct net_device *ndev,
1698 + struct ethtool_drvinfo *ed)
1699 +{
1700 + memset(ed, 0, sizeof(struct ethtool_drvinfo));
1701 + strcpy(ed->driver, DRIVER_NAME);
1702 + strcpy(ed->version, DRIVER_VERSION);
1703 + ed->regdump_len = sizeof(u32) * AXIENET_REGS_N;
1704 +}
1705 +
1706 +/**
1707 + * axienet_ethtools_get_regs_len - Get the total regs length present in the
1708 + * AxiEthernet core.
1709 + * @ndev: Pointer to net_device structure
1710 + *
1711 + * This implements ethtool command for getting the total register length
1712 + * information.
1713 + */
1714 +static int axienet_ethtools_get_regs_len(struct net_device *ndev)
1715 +{
1716 + return sizeof(u32) * AXIENET_REGS_N;
1717 +}
1718 +
1719 +/**
1720 + * axienet_ethtools_get_regs - Dump the contents of all registers present
1721 + * in AxiEthernet core.
1722 + * @ndev: Pointer to net_device structure
1723 + * @regs: Pointer to ethtool_regs structure
1724 + * @ret: Void pointer used to return the contents of the registers.
1725 + *
1726 + * This implements ethtool command for getting the Axi Ethernet register dump.
1727 + * Issue "ethtool -d ethX" to execute this function.
1728 + */
1729 +static void axienet_ethtools_get_regs(struct net_device *ndev,
1730 + struct ethtool_regs *regs, void *ret)
1731 +{
1732 + u32 *data = (u32 *) ret;
1733 + size_t len = sizeof(u32) * AXIENET_REGS_N;
1734 + struct axienet_local *lp = netdev_priv(ndev);
1735 +
1736 + regs->version = 0;
1737 + regs->len = len;
1738 +
1739 + memset(data, 0, len);
1740 + data[0] = axienet_ior(lp, XAE_RAF_OFFSET);
1741 + data[1] = axienet_ior(lp, XAE_TPF_OFFSET);
1742 + data[2] = axienet_ior(lp, XAE_IFGP_OFFSET);
1743 + data[3] = axienet_ior(lp, XAE_IS_OFFSET);
1744 + data[4] = axienet_ior(lp, XAE_IP_OFFSET);
1745 + data[5] = axienet_ior(lp, XAE_IE_OFFSET);
1746 + data[6] = axienet_ior(lp, XAE_TTAG_OFFSET);
1747 + data[7] = axienet_ior(lp, XAE_RTAG_OFFSET);
1748 + data[8] = axienet_ior(lp, XAE_UAWL_OFFSET);
1749 + data[9] = axienet_ior(lp, XAE_UAWU_OFFSET);
1750 + data[10] = axienet_ior(lp, XAE_TPID0_OFFSET);
1751 + data[11] = axienet_ior(lp, XAE_TPID1_OFFSET);
1752 + data[12] = axienet_ior(lp, XAE_PPST_OFFSET);
1753 + data[13] = axienet_ior(lp, XAE_RCW0_OFFSET);
1754 + data[14] = axienet_ior(lp, XAE_RCW1_OFFSET);
1755 + data[15] = axienet_ior(lp, XAE_TC_OFFSET);
1756 + data[16] = axienet_ior(lp, XAE_FCC_OFFSET);
1757 + data[17] = axienet_ior(lp, XAE_EMMC_OFFSET);
1758 + data[18] = axienet_ior(lp, XAE_PHYC_OFFSET);
1759 + data[19] = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1760 + data[20] = axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
1761 + data[21] = axienet_ior(lp, XAE_MDIO_MWD_OFFSET);
1762 + data[22] = axienet_ior(lp, XAE_MDIO_MRD_OFFSET);
1763 + data[23] = axienet_ior(lp, XAE_MDIO_MIS_OFFSET);
1764 + data[24] = axienet_ior(lp, XAE_MDIO_MIP_OFFSET);
1765 + data[25] = axienet_ior(lp, XAE_MDIO_MIE_OFFSET);
1766 + data[26] = axienet_ior(lp, XAE_MDIO_MIC_OFFSET);
1767 + data[27] = axienet_ior(lp, XAE_UAW0_OFFSET);
1768 + data[28] = axienet_ior(lp, XAE_UAW1_OFFSET);
1769 + data[29] = axienet_ior(lp, XAE_FMI_OFFSET);
1770 + data[30] = axienet_ior(lp, XAE_AF0_OFFSET);
1771 + data[31] = axienet_ior(lp, XAE_AF1_OFFSET);
1772 +}
1773 +
1774 +/**
1775 + * axienet_ethtools_get_pauseparam - Get the pause parameter setting for
1776 + * Tx and Rx paths.
1777 + * @ndev: Pointer to net_device structure
1778 + * @epauseparm: Pointer to ethtool_pauseparam structure.
1779 + *
1780 + * This implements ethtool command for getting axi ethernet pause frame
1781 + * setting. Issue "ethtool -a ethX" to execute this function.
1782 + */
1783 +static void
1784 +axienet_ethtools_get_pauseparam(struct net_device *ndev,
1785 + struct ethtool_pauseparam *epauseparm)
1786 +{
1787 + u32 regval;
1788 + struct axienet_local *lp = netdev_priv(ndev);
1789 + epauseparm->autoneg = 0;
1790 + regval = axienet_ior(lp, XAE_FCC_OFFSET);
1791 + epauseparm->tx_pause = regval & XAE_FCC_FCTX_MASK;
1792 + epauseparm->rx_pause = regval & XAE_FCC_FCRX_MASK;
1793 +}
1794 +
1795 +/**
1796 + * axienet_ethtools_set_pauseparam - Set device pause parameter(flow control)
1797 + * settings.
1798 + * @ndev: Pointer to net_device structure
1799 + * @epauseparam:Pointer to ethtool_pauseparam structure
1800 + *
1801 + * This implements ethtool command for enabling flow control on Rx and Tx
1802 + * paths. Issue "ethtool -A ethX tx on|off" under linux prompt to execute this
1803 + * function.
1804 + */
1805 +static int
1806 +axienet_ethtools_set_pauseparam(struct net_device *ndev,
1807 + struct ethtool_pauseparam *epauseparm)
1808 +{
1809 + u32 regval = 0;
1810 + struct axienet_local *lp = netdev_priv(ndev);
1811 +
1812 + if (netif_running(ndev)) {
1813 + printk(KERN_ERR "%s: Please stop netif before applying "
1814 + "configruation\n", ndev->name);
1815 + return -EFAULT;
1816 + }
1817 +
1818 + regval = axienet_ior(lp, XAE_FCC_OFFSET);
1819 + if (epauseparm->tx_pause)
1820 + regval |= XAE_FCC_FCTX_MASK;
1821 + else
1822 + regval &= ~XAE_FCC_FCTX_MASK;
1823 + if (epauseparm->rx_pause)
1824 + regval |= XAE_FCC_FCRX_MASK;
1825 + else
1826 + regval &= ~XAE_FCC_FCRX_MASK;
1827 + axienet_iow(lp, XAE_FCC_OFFSET, regval);
1828 +
1829 + return 0;
1830 +}
1831 +
1832 +/**
1833 + * axienet_ethtools_get_coalesce - Get DMA interrupt coalescing count.
1834 + * @ndev: Pointer to net_device structure
1835 + * @ecoalesce: Pointer to ethtool_coalesce structure
1836 + *
1837 + * This implements ethtool command for getting the DMA interrupt coalescing
1838 + * count on Tx and Rx paths. Issue "ethtool -c ethX" under linux prompt to
1839 + * execute this function.
1840 + */
1841 +static int axienet_ethtools_get_coalesce(struct net_device *ndev,
1842 + struct ethtool_coalesce *ecoalesce)
1843 +{
1844 + u32 regval = 0;
1845 + struct axienet_local *lp = netdev_priv(ndev);
1846 + regval = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1847 + ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1848 + >> XAXIDMA_COALESCE_SHIFT;
1849 + regval = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1850 + ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1851 + >> XAXIDMA_COALESCE_SHIFT;
1852 + return 0;
1853 +}
1854 +
1855 +/**
1856 + * axienet_ethtools_set_coalesce - Set DMA interrupt coalescing count.
1857 + * @ndev: Pointer to net_device structure
1858 + * @ecoalesce: Pointer to ethtool_coalesce structure
1859 + *
1860 + * This implements ethtool command for setting the DMA interrupt coalescing
1861 + * count on Tx and Rx paths. Issue "ethtool -C ethX rx-frames 5" under linux
1862 + * prompt to execute this function.
1863 + */
1864 +static int axienet_ethtools_set_coalesce(struct net_device *ndev,
1865 + struct ethtool_coalesce *ecoalesce)
1866 +{
1867 + struct axienet_local *lp = netdev_priv(ndev);
1868 +
1869 + if (netif_running(ndev)) {
1870 + printk(KERN_ERR "%s: Please stop netif before applying "
1871 + "configruation\n", ndev->name);
1872 + return -EFAULT;
1873 + }
1874 +
1875 + if ((ecoalesce->rx_coalesce_usecs) ||
1876 + (ecoalesce->rx_coalesce_usecs_irq) ||
1877 + (ecoalesce->rx_max_coalesced_frames_irq) ||
1878 + (ecoalesce->tx_coalesce_usecs) ||
1879 + (ecoalesce->tx_coalesce_usecs_irq) ||
1880 + (ecoalesce->tx_max_coalesced_frames_irq) ||
1881 + (ecoalesce->stats_block_coalesce_usecs) ||
1882 + (ecoalesce->use_adaptive_rx_coalesce) ||
1883 + (ecoalesce->use_adaptive_tx_coalesce) ||
1884 + (ecoalesce->pkt_rate_low) ||
1885 + (ecoalesce->rx_coalesce_usecs_low) ||
1886 + (ecoalesce->rx_max_coalesced_frames_low) ||
1887 + (ecoalesce->tx_coalesce_usecs_low) ||
1888 + (ecoalesce->tx_max_coalesced_frames_low) ||
1889 + (ecoalesce->pkt_rate_high) ||
1890 + (ecoalesce->rx_coalesce_usecs_high) ||
1891 + (ecoalesce->rx_max_coalesced_frames_high) ||
1892 + (ecoalesce->tx_coalesce_usecs_high) ||
1893 + (ecoalesce->tx_max_coalesced_frames_high) ||
1894 + (ecoalesce->rate_sample_interval))
1895 + return -EOPNOTSUPP;
1896 + if (ecoalesce->rx_max_coalesced_frames)
1897 + lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1898 + if (ecoalesce->tx_max_coalesced_frames)
1899 + lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1900 +
1901 + return 0;
1902 +}
1903 +
1904 +static struct ethtool_ops axienet_ethtool_ops = {
1905 + .get_settings = axienet_ethtools_get_settings,
1906 + .set_settings = axienet_ethtools_set_settings,
1907 + .get_drvinfo = axienet_ethtools_get_drvinfo,
1908 + .get_regs_len = axienet_ethtools_get_regs_len,
1909 + .get_regs = axienet_ethtools_get_regs,
1910 + .get_link = ethtool_op_get_link,
1911 + .get_pauseparam = axienet_ethtools_get_pauseparam,
1912 + .set_pauseparam = axienet_ethtools_set_pauseparam,
1913 + .get_coalesce = axienet_ethtools_get_coalesce,
1914 + .set_coalesce = axienet_ethtools_set_coalesce,
1915 +};
1916 +
1917 +/**
1918 + * axienet_dma_err_handler - Tasklet handler for Axi DMA Error
1919 + * @data: Data passed
1920 + *
1921 + * Resets the Axi DMA and Axi Ethernet devices, and reconfigures the
1922 + * Tx/Rx BDs.
1923 + */
1924 +static void axienet_dma_err_handler(unsigned long data)
1925 +{
1926 + u32 axienet_status;
1927 + u32 cr, i;
1928 + int mdio_mcreg;
1929 + struct axienet_local *lp = (struct axienet_local *) data;
1930 + struct net_device *ndev = lp->ndev;
1931 + struct axidma_bd *cur_p;
1932 +
1933 + axienet_setoptions(ndev, lp->options &
1934 + ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
1935 + mdio_mcreg = axienet_ior(lp, XAE_MDIO_MC_OFFSET);
1936 + axienet_mdio_wait_until_ready(lp);
1937 + /* Disable the MDIO interface till Axi Ethernet Reset is completed.
1938 + * When we do an Axi Ethernet reset, it resets the complete core
1939 + * including the MDIO. So if MDIO is not disabled when the reset
1940 + * process is started, MDIO will be broken afterwards. */
1941 + axienet_iow(lp, XAE_MDIO_MC_OFFSET, (mdio_mcreg &
1942 + ~XAE_MDIO_MC_MDIOEN_MASK));
1943 +
1944 + __axienet_device_reset(lp, &ndev->dev, XAXIDMA_TX_CR_OFFSET);
1945 + __axienet_device_reset(lp, &ndev->dev, XAXIDMA_RX_CR_OFFSET);
1946 +
1947 + axienet_iow(lp, XAE_MDIO_MC_OFFSET, mdio_mcreg);
1948 + axienet_mdio_wait_until_ready(lp);
1949 +
1950 + for (i = 0; i < TX_BD_NUM; i++) {
1951 + cur_p = &lp->tx_bd_v[i];
1952 + if (cur_p->phys)
1953 + dma_unmap_single(ndev->dev.parent, cur_p->phys,
1954 + (cur_p->cntrl &
1955 + XAXIDMA_BD_CTRL_LENGTH_MASK),
1956 + DMA_TO_DEVICE);
1957 + if (cur_p->app4)
1958 + dev_kfree_skb_irq((struct sk_buff *) cur_p->app4);
1959 + cur_p->phys = 0;
1960 + cur_p->cntrl = 0;
1961 + cur_p->status = 0;
1962 + cur_p->app0 = 0;
1963 + cur_p->app1 = 0;
1964 + cur_p->app2 = 0;
1965 + cur_p->app3 = 0;
1966 + cur_p->app4 = 0;
1967 + cur_p->sw_id_offset = 0;
1968 + }
1969 +
1970 + for (i = 0; i < RX_BD_NUM; i++) {
1971 + cur_p = &lp->rx_bd_v[i];
1972 + cur_p->status = 0;
1973 + cur_p->app0 = 0;
1974 + cur_p->app1 = 0;
1975 + cur_p->app2 = 0;
1976 + cur_p->app3 = 0;
1977 + cur_p->app4 = 0;
1978 + }
1979 +
1980 + lp->tx_bd_ci = 0;
1981 + lp->tx_bd_tail = 0;
1982 + lp->rx_bd_ci = 0;
1983 +
1984 + /* Start updating the Rx channel control register */
1985 + cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
1986 + /* Update the interrupt coalesce count */
1987 + cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
1988 + (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
1989 + /* Update the delay timer count */
1990 + cr = ((cr & ~XAXIDMA_DELAY_MASK) |
1991 + (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
1992 + /* Enable coalesce, delay timer and error interrupts */
1993 + cr |= XAXIDMA_IRQ_ALL_MASK;
1994 + /* Finally write to the Rx channel control register */
1995 + axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr);
1996 +
1997 + /* Start updating the Tx channel control register */
1998 + cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
1999 + /* Update the interrupt coalesce count */
2000 + cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
2001 + (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
2002 + /* Update the delay timer count */
2003 + cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
2004 + (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
2005 + /* Enable coalesce, delay timer and error interrupts */
2006 + cr |= XAXIDMA_IRQ_ALL_MASK;
2007 + /* Finally write to the Tx channel control register */
2008 + axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr);
2009 +
2010 + /* Populate the tail pointer and bring the Rx Axi DMA engine out of
2011 + * halted state. This will make the Rx side ready for reception.*/
2012 + axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
2013 + cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
2014 + axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
2015 + cr | XAXIDMA_CR_RUNSTOP_MASK);
2016 + axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
2017 + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
2018 +
2019 + /* Write to the RS (Run-stop) bit in the Tx channel control register.
2020 + * Tx channel is now ready to run. But only after we write to the
2021 + * tail pointer register that the Tx channel will start transmitting */
2022 + axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
2023 + cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
2024 + axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
2025 + cr | XAXIDMA_CR_RUNSTOP_MASK);
2026 +
2027 + axienet_status = axienet_ior(lp, XAE_RCW1_OFFSET);
2028 + axienet_status &= ~XAE_RCW1_RX_MASK;
2029 + axienet_iow(lp, XAE_RCW1_OFFSET, axienet_status);
2030 +
2031 + axienet_status = axienet_ior(lp, XAE_IP_OFFSET);
2032 + if (axienet_status & XAE_INT_RXRJECT_MASK)
2033 + axienet_iow(lp, XAE_IS_OFFSET, XAE_INT_RXRJECT_MASK);
2034 + axienet_iow(lp, XAE_FCC_OFFSET, XAE_FCC_FCRX_MASK);
2035 +
2036 + /* Sync default options with HW but leave receiver and
2037 + * transmitter disabled.*/
2038 + axienet_setoptions(ndev, lp->options &
2039 + ~(XAE_OPTION_TXEN | XAE_OPTION_RXEN));
2040 + axienet_set_mac_address(ndev, NULL);
2041 + axienet_set_multicast_list(ndev);
2042 + axienet_setoptions(ndev, lp->options);
2043 +}
2044 +
2045 +/**
2046 + * axienet_of_probe - Axi Ethernet probe function.
2047 + * @op: Pointer to platform device structure.
2048 + * @match: Pointer to device id structure
2049 + *
2050 + * returns: 0, on success
2051 + * Non-zero error value on failure.
2052 + *
2053 + * This is the probe routine for Axi Ethernet driver. This is called before
2054 + * any other driver routines are invoked. It allocates and sets up the Ethernet
2055 + * device. Parses through device tree and populates fields of
2056 + * axienet_local. It registers the Ethernet device.
2057 + */
2058 +static int __devinit axienet_of_probe(struct platform_device *op)
2059 +{
2060 + __be32 *p;
2061 + int size, ret = 0;
2062 + struct device_node *np;
2063 + struct axienet_local *lp;
2064 + struct net_device *ndev;
2065 + const void *addr;
2066 +
2067 + ndev = alloc_etherdev(sizeof(*lp));
2068 + if (!ndev) {
2069 + dev_err(&op->dev, "could not allocate device.\n");
2070 + return -ENOMEM;
2071 + }
2072 +
2073 + ether_setup(ndev);
2074 + dev_set_drvdata(&op->dev, ndev);
2075 +
2076 + SET_NETDEV_DEV(ndev, &op->dev);
2077 + ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
2078 + ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
2079 + ndev->netdev_ops = &axienet_netdev_ops;
2080 + ndev->ethtool_ops = &axienet_ethtool_ops;
2081 +
2082 + lp = netdev_priv(ndev);
2083 + lp->ndev = ndev;
2084 + lp->dev = &op->dev;
2085 + lp->options = XAE_OPTION_DEFAULTS;
2086 + /* Map device registers */
2087 + lp->regs = of_iomap(op->dev.of_node, 0);
2088 + if (!lp->regs) {
2089 + dev_err(&op->dev, "could not map Axi Ethernet regs.\n");
2090 + goto nodev;
2091 + }
2092 + /* Setup checksum offload, but default to off if not specified */
2093 + lp->features = 0;
2094 +
2095 + p = (__be32 *) of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
2096 + if (p) {
2097 + switch (be32_to_cpup(p)) {
2098 + case 1:
2099 + lp->csum_offload_on_tx_path =
2100 + XAE_FEATURE_PARTIAL_TX_CSUM;
2101 + lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
2102 + /* Can checksum TCP/UDP over IPv4. */
2103 + ndev->features |= NETIF_F_IP_CSUM;
2104 + break;
2105 + case 2:
2106 + lp->csum_offload_on_tx_path =
2107 + XAE_FEATURE_FULL_TX_CSUM;
2108 + lp->features |= XAE_FEATURE_FULL_TX_CSUM;
2109 + /* Can checksum TCP/UDP over IPv4. */
2110 + ndev->features |= NETIF_F_IP_CSUM;
2111 + break;
2112 + default:
2113 + lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
2114 + }
2115 + }
2116 + p = (__be32 *) of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
2117 + if (p) {
2118 + switch (be32_to_cpup(p)) {
2119 + case 1:
2120 + lp->csum_offload_on_rx_path =
2121 + XAE_FEATURE_PARTIAL_RX_CSUM;
2122 + lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
2123 + break;
2124 + case 2:
2125 + lp->csum_offload_on_rx_path =
2126 + XAE_FEATURE_FULL_RX_CSUM;
2127 + lp->features |= XAE_FEATURE_FULL_RX_CSUM;
2128 + break;
2129 + default:
2130 + lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
2131 + }
2132 + }
2133 + /* For supporting jumbo frames, the Axi Ethernet hardware must have
2134 + * a larger Rx/Tx Memory. Typically, the size must be more than or
2135 + * equal to 16384 bytes, so that we can enable jumbo option and start
2136 + * supporting jumbo frames. Here we check for memory allocated for
2137 + * Rx/Tx in the hardware from the device-tree and accordingly set
2138 + * flags. */
2139 + p = (__be32 *) of_get_property(op->dev.of_node, "xlnx,rxmem", NULL);
2140 + if (p) {
2141 + if ((be32_to_cpup(p)) >= 0x4000)
2142 + lp->jumbo_support = 1;
2143 + }
2144 + p = (__be32 *) of_get_property(op->dev.of_node, "xlnx,temac-type",
2145 + NULL);
2146 + if (p)
2147 + lp->temac_type = be32_to_cpup(p);
2148 + p = (__be32 *) of_get_property(op->dev.of_node, "xlnx,phy-type", NULL);
2149 + if (p)
2150 + lp->phy_type = be32_to_cpup(p);
2151 +
2152 + /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
2153 + np = of_parse_phandle(op->dev.of_node, "axistream-connected", 0);
2154 + if (!np) {
2155 + dev_err(&op->dev, "could not find DMA node\n");
2156 + goto err_iounmap;
2157 + }
2158 + lp->dma_regs = of_iomap(np, 0);
2159 + if (lp->dma_regs) {
2160 + dev_dbg(&op->dev, "MEM base: %p\n", lp->dma_regs);
2161 + } else {
2162 + dev_err(&op->dev, "unable to map DMA registers\n");
2163 + of_node_put(np);
2164 + }
2165 + lp->rx_irq = irq_of_parse_and_map(np, 1);
2166 + lp->tx_irq = irq_of_parse_and_map(np, 0);
2167 + of_node_put(np);
2168 + if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
2169 + dev_err(&op->dev, "could not determine irqs\n");
2170 + ret = -ENOMEM;
2171 + goto err_iounmap_2;
2172 + }
2173 +
2174 + /* Retrieve the MAC address */
2175 + addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
2176 + if ((!addr) || (size != 6)) {
2177 + dev_err(&op->dev, "could not find MAC address\n");
2178 + ret = -ENODEV;
2179 + goto err_iounmap_2;
2180 + }
2181 + axienet_set_mac_address(ndev, (void *) addr);
2182 +
2183 + lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
2184 + lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
2185 +
2186 + lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
2187 + ret = axienet_mdio_setup(lp, op->dev.of_node);
2188 + if (ret)
2189 + dev_warn(&op->dev, "error registering MDIO bus\n");
2190 +
2191 + ret = register_netdev(lp->ndev);
2192 + if (ret) {
2193 + dev_err(lp->dev, "register_netdev() error (%i)\n", ret);
2194 + goto err_iounmap_2;
2195 + }
2196 +
2197 + tasklet_init(&lp->dma_err_tasklet, axienet_dma_err_handler,
2198 + (unsigned long) lp);
2199 + tasklet_disable(&lp->dma_err_tasklet);
2200 +
2201 + return 0;
2202 +
2203 +err_iounmap_2:
2204 + if (lp->dma_regs)
2205 + iounmap(lp->dma_regs);
2206 +err_iounmap:
2207 + iounmap(lp->regs);
2208 +nodev:
2209 + free_netdev(ndev);
2210 + ndev = NULL;
2211 + return ret;
2212 +}
2213 +
2214 +static int __devexit axienet_of_remove(struct platform_device *op)
2215 +{
2216 + struct net_device *ndev = dev_get_drvdata(&op->dev);
2217 + struct axienet_local *lp = netdev_priv(ndev);
2218 +
2219 + axienet_mdio_teardown(lp);
2220 + unregister_netdev(ndev);
2221 +
2222 + if (lp->phy_node)
2223 + of_node_put(lp->phy_node);
2224 + lp->phy_node = NULL;
2225 +
2226 + dev_set_drvdata(&op->dev, NULL);
2227 +
2228 + iounmap(lp->regs);
2229 + if (lp->dma_regs)
2230 + iounmap(lp->dma_regs);
2231 + free_netdev(ndev);
2232 +
2233 + return 0;
2234 +}
2235 +
2236 +static struct platform_driver axienet_of_driver = {
2237 + .probe = axienet_of_probe,
2238 + .remove = __devexit_p(axienet_of_remove),
2239 + .driver = {
2240 + .owner = THIS_MODULE,
2241 + .name = "xilinx_axienet",
2242 + .of_match_table = axienet_of_match,
2243 + },
2244 +};
2245 +
2246 +static int __init axienet_init(void)
2247 +{
2248 + return platform_driver_register(&axienet_of_driver);
2249 +}
2250 +
2251 +static void __exit axienet_exit(void)
2252 +{
2253 + platform_driver_unregister(&axienet_of_driver);
2254 +}
2255 +
2256 +module_init(axienet_init);
2257 +module_exit(axienet_exit);
2258 +
2259 +MODULE_DESCRIPTION("Xilinx Axi Ethernet driver");
2260 +MODULE_AUTHOR("Xilinx");
2261 +MODULE_LICENSE("GPL");
2262 diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
2263 new file mode 100644
2264 index 0000000..d70b6e7
2265 --- /dev/null
2266 +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
2267 @@ -0,0 +1,238 @@
2268 +/*
2269 + * MDIO bus driver for the Xilinx Axi Ethernet device
2270 + *
2271 + * Copyright (c) 2009 Secret Lab Technologies, Ltd.
2272 + * Copyright (c) 2010 Xilinx, Inc. All rights reserved.
2273 + * Copyright (c) 2012 Daniel Borkmann, <daniel.borkmann@tik.ee.ethz.ch>
2274 + * Copyright (c) 2012 Ariane Keller, <ariane.keller@tik.ee.ethz.ch>
2275 + */
2276 +
2277 +#include <linux/of_address.h>
2278 +#include <linux/of_mdio.h>
2279 +#include <linux/jiffies.h>
2280 +
2281 +#include "xilinx_axienet.h"
2282 +
2283 +#define MAX_MDIO_FREQ 2500000 /* 2.5 MHz */
2284 +#define DEFAULT_CLOCK_DIVISOR XAE_MDIO_DIV_DFT
2285 +
2286 +/* Wait till MDIO interface is ready to accept a new transaction.*/
2287 +int axienet_mdio_wait_until_ready(struct axienet_local *lp)
2288 +{
2289 + long end = jiffies + 2;
2290 + while (!(axienet_ior(lp, XAE_MDIO_MCR_OFFSET) &
2291 + XAE_MDIO_MCR_READY_MASK)) {
2292 + if (end - jiffies <= 0) {
2293 + WARN_ON(1);
2294 + return -ETIMEDOUT;
2295 + }
2296 + udelay(1);
2297 + }
2298 + return 0;
2299 +}
2300 +
2301 +/**
2302 + * axienet_mdio_read - MDIO interface read function
2303 + * @bus: Pointer to mii bus structure
2304 + * @phy_id: Address of the PHY device
2305 + * @reg: PHY register to read
2306 + *
2307 + * returns: The register contents on success, -ETIMEDOUT on a timeout
2308 + *
2309 + * Reads the contents of the requested register from the requested PHY
2310 + * address by first writing the details into MCR register. After a while
2311 + * the register MRD is read to obtain the PHY register content.
2312 + */
2313 +static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
2314 +{
2315 + u32 rc;
2316 + int ret;
2317 + struct axienet_local *lp = bus->priv;
2318 +
2319 + ret = axienet_mdio_wait_until_ready(lp);
2320 + if (ret < 0)
2321 + return ret;
2322 +
2323 + axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
2324 + (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
2325 + XAE_MDIO_MCR_PHYAD_MASK) |
2326 + ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
2327 + XAE_MDIO_MCR_REGAD_MASK) |
2328 + XAE_MDIO_MCR_INITIATE_MASK |
2329 + XAE_MDIO_MCR_OP_READ_MASK));
2330 +
2331 + ret = axienet_mdio_wait_until_ready(lp);
2332 + if (ret < 0)
2333 + return ret;
2334 +
2335 + rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF;
2336 +
2337 + dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
2338 + phy_id, reg, rc);
2339 +
2340 + return rc;
2341 +}
2342 +
2343 +/**
2344 + * axienet_mdio_write - MDIO interface write function
2345 + * @bus: Pointer to mii bus structure
2346 + * @phy_id: Address of the PHY device
2347 + * @reg: PHY register to write to
2348 + * @val: Value to be written into the register
2349 + *
2350 + * returns: 0 on success, -ETIMEDOUT on a timeout
2351 + *
2352 + * Writes the value to the requested register by first writing the value
2353 + * into MWD register. The the MCR register is then appropriately setup
2354 + * to finish the write operation.
2355 + */
2356 +static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
2357 + u16 val)
2358 +{
2359 + int ret;
2360 + struct axienet_local *lp = bus->priv;
2361 +
2362 + dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
2363 + phy_id, reg, val);
2364 +
2365 + ret = axienet_mdio_wait_until_ready(lp);
2366 + if (ret < 0)
2367 + return ret;
2368 +
2369 + axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val);
2370 + axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
2371 + (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
2372 + XAE_MDIO_MCR_PHYAD_MASK) |
2373 + ((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
2374 + XAE_MDIO_MCR_REGAD_MASK) |
2375 + XAE_MDIO_MCR_INITIATE_MASK |
2376 + XAE_MDIO_MCR_OP_WRITE_MASK));
2377 +
2378 + ret = axienet_mdio_wait_until_ready(lp);
2379 + if (ret < 0)
2380 + return ret;
2381 + return 0;
2382 +}
2383 +
2384 +/**
2385 + * axienet_mdio_setup - MDIO setup function
2386 + * @lp: Pointer to axienet local data structure.
2387 + * @np: Pointer to device node
2388 + *
2389 + * returns: 0 on success, -ETIMEDOUT on a timeout, -ENOMEM when
2390 + * mdiobus_alloc (to allocate memory for mii bus structure) fails.
2391 + *
2392 + * Sets up the MDIO interface by initializing the MDIO clock and enabling the
2393 + * MDIO interface in hardware. Register the MDIO interface.
2394 + **/
2395 +int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
2396 +{
2397 + int ret;
2398 + u32 clk_div, host_clock;
2399 + u32 *property_p;
2400 + struct mii_bus *bus;
2401 + struct resource res;
2402 + struct device_node *np1;
2403 +
2404 + /* clk_div can be calculated by deriving it from the equation:
2405 + * fMDIO = fHOST / ((1 + clk_div) * 2)
2406 + *
2407 + * Where fMDIO <= 2500000, so we get:
2408 + * fHOST / ((1 + clk_div) * 2) <= 2500000
2409 + *
2410 + * Then we get:
2411 + * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
2412 + *
2413 + * Then we get:
2414 + * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
2415 + *
2416 + * Then we get:
2417 + * 1 / (1 + clk_div) <= (5000000 / fHOST)
2418 + *
2419 + * So:
2420 + * (1 + clk_div) >= (fHOST / 5000000)
2421 + *
2422 + * And finally:
2423 + * clk_div >= (fHOST / 5000000) - 1
2424 + *
2425 + * fHOST can be read from the flattened device tree as property
2426 + * "clock-frequency" from the CPU
2427 + */
2428 +
2429 + np1 = of_find_node_by_name(NULL, "cpu");
2430 + if (!np1) {
2431 + printk(KERN_WARNING "%s(): Could not find CPU device node.",
2432 + __func__);
2433 + printk(KERN_WARNING "Setting MDIO clock divisor to "
2434 + "default %d\n", DEFAULT_CLOCK_DIVISOR);
2435 + clk_div = DEFAULT_CLOCK_DIVISOR;
2436 + goto issue;
2437 + }
2438 + property_p = (u32 *) of_get_property(np1, "clock-frequency", NULL);
2439 + if (!property_p) {
2440 + printk(KERN_WARNING "%s(): Could not find CPU property: "
2441 + "clock-frequency.", __func__);
2442 + printk(KERN_WARNING "Setting MDIO clock divisor to "
2443 + "default %d\n", DEFAULT_CLOCK_DIVISOR);
2444 + clk_div = DEFAULT_CLOCK_DIVISOR;
2445 + goto issue;
2446 + }
2447 +
2448 + host_clock = be32_to_cpup(property_p);
2449 + clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
2450 + /* If there is any remainder from the division of
2451 + * fHOST / (MAX_MDIO_FREQ * 2), then we need to add
2452 + * 1 to the clock divisor or we will surely be above 2.5 MHz */
2453 + if (host_clock % (MAX_MDIO_FREQ * 2))
2454 + clk_div++;
2455 +
2456 + printk(KERN_DEBUG "%s(): Setting MDIO clock divisor to %u based "
2457 + "on %u Hz host clock.\n", __func__, clk_div, host_clock);
2458 +
2459 + of_node_put(np1);
2460 +issue:
2461 + axienet_iow(lp, XAE_MDIO_MC_OFFSET,
2462 + (((u32) clk_div) | XAE_MDIO_MC_MDIOEN_MASK));
2463 +
2464 + ret = axienet_mdio_wait_until_ready(lp);
2465 + if (ret < 0)
2466 + return ret;
2467 +
2468 + bus = mdiobus_alloc();
2469 + if (!bus)
2470 + return -ENOMEM;
2471 +
2472 + np1 = of_get_parent(lp->phy_node);
2473 + of_address_to_resource(np1, 0, &res);
2474 + snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
2475 + (unsigned long long) res.start);
2476 +
2477 + bus->priv = lp;
2478 + bus->name = "Xilinx Axi Ethernet MDIO";
2479 + bus->read = axienet_mdio_read;
2480 + bus->write = axienet_mdio_write;
2481 + bus->parent = lp->dev;
2482 + bus->irq = lp->mdio_irqs; /* preallocated IRQ table */
2483 + lp->mii_bus = bus;
2484 +
2485 + ret = of_mdiobus_register(bus, np1);
2486 + if (ret) {
2487 + mdiobus_free(bus);
2488 + return ret;
2489 + }
2490 + return 0;
2491 +}
2492 +
2493 +/**
2494 + * axienet_mdio_teardown - MDIO remove function
2495 + * @lp: Pointer to axienet local data structure.
2496 + *
2497 + * Unregisters the MDIO and frees any associate memory for mii bus.
2498 + */
2499 +void axienet_mdio_teardown(struct axienet_local *lp)
2500 +{
2501 + mdiobus_unregister(lp->mii_bus);
2502 + kfree(lp->mii_bus->irq);
2503 + mdiobus_free(lp->mii_bus);
2504 + lp->mii_bus = NULL;
2505 +}