microblaze/ethernetgmii/data/DDR3_SDRAM_mig_saved.prj

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <Project NoOfControllers="1" >
   3     <ModuleName>axi_v6_ddrx_0</ModuleName>
   4     <dci_inouts_inputs>1</dci_inouts_inputs>
   5     <dci_outputs>0</dci_outputs>
   6     <Debug_En>OFF</Debug_En>
   7     <TargetFPGA>xc6vlx240t-ff1156/-1</TargetFPGA>
   8     <Version>3.6</Version>
   9     <SystemClock>Differential</SystemClock>
  10     <PinSelectionFlag>TRUE</PinSelectionFlag>
  11     <IODelayHighPerformanceMode>HIGH</IODelayHighPerformanceMode>
  12     <InternalVref>0</InternalVref>
  13     <Controller number="0" >
  14         <MemoryDevice>DDR3_SDRAM/SODIMMs/MT4JSF6464HY-1G1</MemoryDevice>
  15         <TimePeriod>2500</TimePeriod>
  16         <DataWidth>64</DataWidth>
  17         <DeepMemory>1</DeepMemory>
  18         <DataMask>1</DataMask>
  19         <CustomPart>FALSE</CustomPart>
  20         <NewPartName></NewPartName>
  21         <RowAddress>13</RowAddress>
  22         <ColAddress>10</ColAddress>
  23         <BankAddress>3</BankAddress>
  24         <MasterBanks>26,36</MasterBanks>
  25         <TimingParameters>
  26             <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" trfc="110" trp="13.13" tras="37.5" trcd="13.13" />
  27         </TimingParameters>
  28         <ECC>Disabled</ECC>
  29         <DiscreteBankSelections>1</DiscreteBankSelections>
  30         <CaptureClock>36</CaptureClock>
  31         <Ordering>Normal</Ordering>
  32         <PinSelection>
  33             <Pin SignalName="BUFIO:0" PINNumber="C13" SignalGroup="Data" Bank="35" />
  34             <Pin SignalName="BUFIO:1" PINNumber="L13" SignalGroup="Data" Bank="35" />
  35             <Pin SignalName="BUFIO:2" PINNumber="K14" SignalGroup="Data" Bank="35" />
  36             <Pin SignalName="BUFIO:3" PINNumber="F21" SignalGroup="Data" Bank="26" />
  37             <Pin SignalName="BUFIO:4" PINNumber="B20" SignalGroup="Data" Bank="26" />
  38             <Pin SignalName="BUFIO:5" PINNumber="F25" SignalGroup="Data" Bank="25" />
  39             <Pin SignalName="BUFIO:6" PINNumber="C28" SignalGroup="Data" Bank="25" />
  40             <Pin SignalName="BUFIO:7" PINNumber="D24" SignalGroup="Data" Bank="25" />
  41             <Pin SignalName="BUFR:0" PINNumber="M12" SignalGroup="Data" Bank="35" />
  42             <Pin SignalName="BUFR:1" PINNumber="C29" SignalGroup="Data" Bank="25" />
  43             <Pin SignalName="ddr3_addr[0]" PINNumber="L14" SignalGroup="Address" Bank="36" />
  44             <Pin SignalName="ddr3_addr[10]" PINNumber="M16" SignalGroup="Address" Bank="36" />
  45             <Pin SignalName="ddr3_addr[11]" PINNumber="M15" SignalGroup="Address" Bank="36" />
  46             <Pin SignalName="ddr3_addr[12]" PINNumber="H15" SignalGroup="Address" Bank="36" />
  47             <Pin SignalName="ddr3_addr[1]" PINNumber="A16" SignalGroup="Address" Bank="36" />
  48             <Pin SignalName="ddr3_addr[2]" PINNumber="B16" SignalGroup="Address" Bank="36" />
  49             <Pin SignalName="ddr3_addr[3]" PINNumber="E16" SignalGroup="Address" Bank="36" />
  50             <Pin SignalName="ddr3_addr[4]" PINNumber="D16" SignalGroup="Address" Bank="36" />
  51             <Pin SignalName="ddr3_addr[5]" PINNumber="J17" SignalGroup="Address" Bank="36" />
  52             <Pin SignalName="ddr3_addr[6]" PINNumber="A15" SignalGroup="Address" Bank="36" />
  53             <Pin SignalName="ddr3_addr[7]" PINNumber="B15" SignalGroup="Address" Bank="36" />
  54             <Pin SignalName="ddr3_addr[8]" PINNumber="G15" SignalGroup="Address" Bank="36" />
  55             <Pin SignalName="ddr3_addr[9]" PINNumber="F15" SignalGroup="Address" Bank="36" />
  56             <Pin SignalName="ddr3_ba[0]" PINNumber="K19" SignalGroup="Address" Bank="36" />
  57             <Pin SignalName="ddr3_ba[1]" PINNumber="J19" SignalGroup="Address" Bank="36" />
  58             <Pin SignalName="ddr3_ba[2]" PINNumber="L15" SignalGroup="Address" Bank="36" />
  59             <Pin SignalName="ddr3_cas#" PINNumber="C17" SignalGroup="Address" Bank="36" />
  60             <Pin SignalName="ddr3_ck#[0]" PINNumber="H18" SignalGroup="Address" Bank="36" />
  61             <Pin SignalName="ddr3_ck_p[0]" PINNumber="G18" SignalGroup="Address" Bank="36" />
  62             <Pin SignalName="ddr3_cke[0]" PINNumber="M18" SignalGroup="Address" Bank="36" />
  63             <Pin SignalName="ddr3_cs#[0]" PINNumber="K18" SignalGroup="Address" Bank="36" />
  64             <Pin SignalName="ddr3_dm[0]" PINNumber="E11" SignalGroup="Data" Bank="35" />
  65             <Pin SignalName="ddr3_dm[1]" PINNumber="B11" SignalGroup="Data" Bank="35" />
  66             <Pin SignalName="ddr3_dm[2]" PINNumber="E14" SignalGroup="Data" Bank="35" />
  67             <Pin SignalName="ddr3_dm[3]" PINNumber="D19" SignalGroup="Data" Bank="26" />
  68             <Pin SignalName="ddr3_dm[4]" PINNumber="B22" SignalGroup="Data" Bank="26" />
  69             <Pin SignalName="ddr3_dm[5]" PINNumber="A26" SignalGroup="Data" Bank="25" />
  70             <Pin SignalName="ddr3_dm[6]" PINNumber="A29" SignalGroup="Data" Bank="25" />
  71             <Pin SignalName="ddr3_dm[7]" PINNumber="A31" SignalGroup="Data" Bank="25" />
  72             <Pin SignalName="ddr3_dq[0]" PINNumber="J11" SignalGroup="Data" Bank="35" />
  73             <Pin SignalName="ddr3_dq[10]" PINNumber="B13" SignalGroup="Data" Bank="35" />
  74             <Pin SignalName="ddr3_dq[11]" PINNumber="B12" SignalGroup="Data" Bank="35" />
  75             <Pin SignalName="ddr3_dq[12]" PINNumber="G10" SignalGroup="Data" Bank="35" />
  76             <Pin SignalName="ddr3_dq[13]" PINNumber="M11" SignalGroup="Data" Bank="35" />
  77             <Pin SignalName="ddr3_dq[14]" PINNumber="C12" SignalGroup="Data" Bank="35" />
  78             <Pin SignalName="ddr3_dq[15]" PINNumber="A11" SignalGroup="Data" Bank="35" />
  79             <Pin SignalName="ddr3_dq[16]" PINNumber="G11" SignalGroup="Data" Bank="35" />
  80             <Pin SignalName="ddr3_dq[17]" PINNumber="F11" SignalGroup="Data" Bank="35" />
  81             <Pin SignalName="ddr3_dq[18]" PINNumber="D14" SignalGroup="Data" Bank="35" />
  82             <Pin SignalName="ddr3_dq[19]" PINNumber="C14" SignalGroup="Data" Bank="35" />
  83             <Pin SignalName="ddr3_dq[1]" PINNumber="E13" SignalGroup="Data" Bank="35" />
  84             <Pin SignalName="ddr3_dq[20]" PINNumber="G12" SignalGroup="Data" Bank="35" />
  85             <Pin SignalName="ddr3_dq[21]" PINNumber="G13" SignalGroup="Data" Bank="35" />
  86             <Pin SignalName="ddr3_dq[22]" PINNumber="F14" SignalGroup="Data" Bank="35" />
  87             <Pin SignalName="ddr3_dq[23]" PINNumber="H14" SignalGroup="Data" Bank="35" />
  88             <Pin SignalName="ddr3_dq[24]" PINNumber="C19" SignalGroup="Data" Bank="26" />
  89             <Pin SignalName="ddr3_dq[25]" PINNumber="G20" SignalGroup="Data" Bank="26" />
  90             <Pin SignalName="ddr3_dq[26]" PINNumber="E19" SignalGroup="Data" Bank="26" />
  91             <Pin SignalName="ddr3_dq[27]" PINNumber="F20" SignalGroup="Data" Bank="26" />
  92             <Pin SignalName="ddr3_dq[28]" PINNumber="A20" SignalGroup="Data" Bank="26" />
  93             <Pin SignalName="ddr3_dq[29]" PINNumber="A21" SignalGroup="Data" Bank="26" />
  94             <Pin SignalName="ddr3_dq[2]" PINNumber="F13" SignalGroup="Data" Bank="35" />
  95             <Pin SignalName="ddr3_dq[30]" PINNumber="E22" SignalGroup="Data" Bank="26" />
  96             <Pin SignalName="ddr3_dq[31]" PINNumber="E23" SignalGroup="Data" Bank="26" />
  97             <Pin SignalName="ddr3_dq[32]" PINNumber="G21" SignalGroup="Data" Bank="26" />
  98             <Pin SignalName="ddr3_dq[33]" PINNumber="B21" SignalGroup="Data" Bank="26" />
  99             <Pin SignalName="ddr3_dq[34]" PINNumber="A23" SignalGroup="Data" Bank="26" />
 100             <Pin SignalName="ddr3_dq[35]" PINNumber="A24" SignalGroup="Data" Bank="26" />
 101             <Pin SignalName="ddr3_dq[36]" PINNumber="C20" SignalGroup="Data" Bank="26" />
 102             <Pin SignalName="ddr3_dq[37]" PINNumber="D20" SignalGroup="Data" Bank="26" />
 103             <Pin SignalName="ddr3_dq[38]" PINNumber="J20" SignalGroup="Data" Bank="26" />
 104             <Pin SignalName="ddr3_dq[39]" PINNumber="G22" SignalGroup="Data" Bank="26" />
 105             <Pin SignalName="ddr3_dq[3]" PINNumber="K11" SignalGroup="Data" Bank="35" />
 106             <Pin SignalName="ddr3_dq[40]" PINNumber="D26" SignalGroup="Data" Bank="25" />
 107             <Pin SignalName="ddr3_dq[41]" PINNumber="F26" SignalGroup="Data" Bank="25" />
 108             <Pin SignalName="ddr3_dq[42]" PINNumber="B26" SignalGroup="Data" Bank="25" />
 109             <Pin SignalName="ddr3_dq[43]" PINNumber="E26" SignalGroup="Data" Bank="25" />
 110             <Pin SignalName="ddr3_dq[44]" PINNumber="C24" SignalGroup="Data" Bank="25" />
 111             <Pin SignalName="ddr3_dq[45]" PINNumber="D25" SignalGroup="Data" Bank="25" />
 112             <Pin SignalName="ddr3_dq[46]" PINNumber="D27" SignalGroup="Data" Bank="25" />
 113             <Pin SignalName="ddr3_dq[47]" PINNumber="C25" SignalGroup="Data" Bank="25" />
 114             <Pin SignalName="ddr3_dq[48]" PINNumber="C27" SignalGroup="Data" Bank="25" />
 115             <Pin SignalName="ddr3_dq[49]" PINNumber="B28" SignalGroup="Data" Bank="25" />
 116             <Pin SignalName="ddr3_dq[4]" PINNumber="L11" SignalGroup="Data" Bank="35" />
 117             <Pin SignalName="ddr3_dq[50]" PINNumber="D29" SignalGroup="Data" Bank="25" />
 118             <Pin SignalName="ddr3_dq[51]" PINNumber="B27" SignalGroup="Data" Bank="25" />
 119             <Pin SignalName="ddr3_dq[52]" PINNumber="G27" SignalGroup="Data" Bank="25" />
 120             <Pin SignalName="ddr3_dq[53]" PINNumber="A28" SignalGroup="Data" Bank="25" />
 121             <Pin SignalName="ddr3_dq[54]" PINNumber="E24" SignalGroup="Data" Bank="25" />
 122             <Pin SignalName="ddr3_dq[55]" PINNumber="G25" SignalGroup="Data" Bank="25" />
 123             <Pin SignalName="ddr3_dq[56]" PINNumber="F28" SignalGroup="Data" Bank="25" />
 124             <Pin SignalName="ddr3_dq[57]" PINNumber="B31" SignalGroup="Data" Bank="25" />
 125             <Pin SignalName="ddr3_dq[58]" PINNumber="H29" SignalGroup="Data" Bank="25" />
 126             <Pin SignalName="ddr3_dq[59]" PINNumber="H28" SignalGroup="Data" Bank="25" />
 127             <Pin SignalName="ddr3_dq[5]" PINNumber="K13" SignalGroup="Data" Bank="35" />
 128             <Pin SignalName="ddr3_dq[60]" PINNumber="B30" SignalGroup="Data" Bank="25" />
 129             <Pin SignalName="ddr3_dq[61]" PINNumber="A30" SignalGroup="Data" Bank="25" />
 130             <Pin SignalName="ddr3_dq[62]" PINNumber="E29" SignalGroup="Data" Bank="25" />
 131             <Pin SignalName="ddr3_dq[63]" PINNumber="F29" SignalGroup="Data" Bank="25" />
 132             <Pin SignalName="ddr3_dq[6]" PINNumber="K12" SignalGroup="Data" Bank="35" />
 133             <Pin SignalName="ddr3_dq[7]" PINNumber="D11" SignalGroup="Data" Bank="35" />
 134             <Pin SignalName="ddr3_dq[8]" PINNumber="M13" SignalGroup="Data" Bank="35" />
 135             <Pin SignalName="ddr3_dq[9]" PINNumber="J14" SignalGroup="Data" Bank="35" />
 136             <Pin SignalName="ddr3_dqs#[0]" PINNumber="E12" SignalGroup="Data" Bank="35" />
 137             <Pin SignalName="ddr3_dqs#[1]" PINNumber="J12" SignalGroup="Data" Bank="35" />
 138             <Pin SignalName="ddr3_dqs#[2]" PINNumber="A14" SignalGroup="Data" Bank="35" />
 139             <Pin SignalName="ddr3_dqs#[3]" PINNumber="H20" SignalGroup="Data" Bank="26" />
 140             <Pin SignalName="ddr3_dqs#[4]" PINNumber="C23" SignalGroup="Data" Bank="26" />
 141             <Pin SignalName="ddr3_dqs#[5]" PINNumber="A25" SignalGroup="Data" Bank="25" />
 142             <Pin SignalName="ddr3_dqs#[6]" PINNumber="G28" SignalGroup="Data" Bank="25" />
 143             <Pin SignalName="ddr3_dqs#[7]" PINNumber="D30" SignalGroup="Data" Bank="25" />
 144             <Pin SignalName="ddr3_dqs_p[0]" PINNumber="D12" SignalGroup="Data" Bank="35" />
 145             <Pin SignalName="ddr3_dqs_p[1]" PINNumber="H12" SignalGroup="Data" Bank="35" />
 146             <Pin SignalName="ddr3_dqs_p[2]" PINNumber="A13" SignalGroup="Data" Bank="35" />
 147             <Pin SignalName="ddr3_dqs_p[3]" PINNumber="H19" SignalGroup="Data" Bank="26" />
 148             <Pin SignalName="ddr3_dqs_p[4]" PINNumber="B23" SignalGroup="Data" Bank="26" />
 149             <Pin SignalName="ddr3_dqs_p[5]" PINNumber="B25" SignalGroup="Data" Bank="25" />
 150             <Pin SignalName="ddr3_dqs_p[6]" PINNumber="H27" SignalGroup="Data" Bank="25" />
 151             <Pin SignalName="ddr3_dqs_p[7]" PINNumber="C30" SignalGroup="Data" Bank="25" />
 152             <Pin SignalName="ddr3_odt[0]" PINNumber="F18" SignalGroup="Address" Bank="36" />
 153             <Pin SignalName="ddr3_ras#" PINNumber="L19" SignalGroup="Address" Bank="36" />
 154             <Pin SignalName="ddr3_reset#" PINNumber="E18" SignalGroup="Address" Bank="36" />
 155             <Pin SignalName="ddr3_we#" PINNumber="B17" SignalGroup="Address" Bank="36" />
 156         </PinSelection>
 157         <BankSelection>
 158             <Bank SysClk="0" Data="1" name="25" Address="0" wasso="40" />
 159             <Bank SysClk="0" Data="1" name="26" Address="0" wasso="40" />
 160             <Bank SysClk="0" Data="1" name="35" Address="0" wasso="40" />
 161             <Bank SysClk="0" Data="0" name="36" Address="1" wasso="40" />
 162         </BankSelection>
 163         <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
 164         <mrBurstType name="Read Burst Type" >Sequential</mrBurstType>
 165         <mrCasLatency name="CAS Latency" >6</mrCasLatency>
 166         <mrMode name="Mode" >Normal</mrMode>
 167         <mrDllReset name="DLL Reset" >No</mrDllReset>
 168         <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
 169         <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
 170         <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
 171         <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
 172         <emrPosted name="Additive Latency (AL)" >0</emrPosted>
 173         <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
 174         <emrDQS name="TDQS enable" >Enabled</emrDQS>
 175         <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
 176         <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
 177         <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
 178         <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
 179         <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
 180         <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
 181         <PortInterface>AXI</PortInterface>
 182     </Controller>
 183 </Project>