microblaze/data/DDR3_SDRAM_mig_saved.prj

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <Project NoOfControllers="1" >
   3     <ModuleName>DDR3_SDRAM</ModuleName>
   4     <dci_inouts_inputs>1</dci_inouts_inputs>
   5     <dci_outputs>0</dci_outputs>
   6     <Debug_En>OFF</Debug_En>
   7     <TargetFPGA>xc6vlx240t-ff1156/-1</TargetFPGA>
   8     <Version>3.8</Version>
   9     <SystemClock>Differential</SystemClock>
  10     <PinSelectionFlag>TRUE</PinSelectionFlag>
  11     <IODelayHighPerformanceMode>HIGH</IODelayHighPerformanceMode>
  12     <InternalVref>0</InternalVref>
  13     <IdelayGroupName>IODELAY_MIG</IdelayGroupName>
  14     <Controller number="0" >
  15         <MemoryDevice>DDR3_SDRAM/Components/MT41J64M16XX-15E</MemoryDevice>
  16         <TimePeriod>2500</TimePeriod>
  17         <DataWidth>8</DataWidth>
  18         <DeepMemory>1</DeepMemory>
  19         <DataMask>1</DataMask>
  20         <CustomPart>FALSE</CustomPart>
  21         <NewPartName></NewPartName>
  22         <RowAddress>13</RowAddress>
  23         <ColAddress>10</ColAddress>
  24         <BankAddress>3</BankAddress>
  25         <MasterBanks>36</MasterBanks>
  26         <TimingParameters>
  27             <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" trfc="110" trp="13.5" tras="36" trcd="13.5" />
  28         </TimingParameters>
  29         <ECC>Disabled</ECC>
  30         <DiscreteBankSelections>1</DiscreteBankSelections>
  31         <CaptureClock>36</CaptureClock>
  32         <UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
  33         <Ordering>Normal</Ordering>
  34         <PinSelection>
  35             <Pin SignalName="BUFIO:0" PINNumber="C13" SignalGroup="Data" Bank="35" />
  36             <Pin SignalName="BUFR:0" PINNumber="M12" SignalGroup="Data" Bank="35" />
  37             <Pin SignalName="ddr3_addr[0]" PINNumber="L14" SignalGroup="Address" Bank="36" />
  38             <Pin SignalName="ddr3_addr[10]" PINNumber="M16" SignalGroup="Address" Bank="36" />
  39             <Pin SignalName="ddr3_addr[11]" PINNumber="M15" SignalGroup="Address" Bank="36" />
  40             <Pin SignalName="ddr3_addr[12]" PINNumber="H15" SignalGroup="Address" Bank="36" />
  41             <Pin SignalName="ddr3_addr[1]" PINNumber="A16" SignalGroup="Address" Bank="36" />
  42             <Pin SignalName="ddr3_addr[2]" PINNumber="B16" SignalGroup="Address" Bank="36" />
  43             <Pin SignalName="ddr3_addr[3]" PINNumber="E16" SignalGroup="Address" Bank="36" />
  44             <Pin SignalName="ddr3_addr[4]" PINNumber="D16" SignalGroup="Address" Bank="36" />
  45             <Pin SignalName="ddr3_addr[5]" PINNumber="J17" SignalGroup="Address" Bank="36" />
  46             <Pin SignalName="ddr3_addr[6]" PINNumber="A15" SignalGroup="Address" Bank="36" />
  47             <Pin SignalName="ddr3_addr[7]" PINNumber="B15" SignalGroup="Address" Bank="36" />
  48             <Pin SignalName="ddr3_addr[8]" PINNumber="G15" SignalGroup="Address" Bank="36" />
  49             <Pin SignalName="ddr3_addr[9]" PINNumber="F15" SignalGroup="Address" Bank="36" />
  50             <Pin SignalName="ddr3_ba[0]" PINNumber="K19" SignalGroup="Address" Bank="36" />
  51             <Pin SignalName="ddr3_ba[1]" PINNumber="J19" SignalGroup="Address" Bank="36" />
  52             <Pin SignalName="ddr3_ba[2]" PINNumber="L15" SignalGroup="Address" Bank="36" />
  53             <Pin SignalName="ddr3_cas#" PINNumber="C17" SignalGroup="Address" Bank="36" />
  54             <Pin SignalName="ddr3_ck#[0]" PINNumber="H18" SignalGroup="Address" Bank="36" />
  55             <Pin SignalName="ddr3_ck_p[0]" PINNumber="G18" SignalGroup="Address" Bank="36" />
  56             <Pin SignalName="ddr3_cke[0]" PINNumber="M18" SignalGroup="Address" Bank="36" />
  57             <Pin SignalName="ddr3_cs#[0]" PINNumber="K18" SignalGroup="Address" Bank="36" />
  58             <Pin SignalName="ddr3_dm[0]" PINNumber="E11" SignalGroup="Data" Bank="35" />
  59             <Pin SignalName="ddr3_dq[0]" PINNumber="J11" SignalGroup="Data" Bank="35" />
  60             <Pin SignalName="ddr3_dq[1]" PINNumber="E13" SignalGroup="Data" Bank="35" />
  61             <Pin SignalName="ddr3_dq[2]" PINNumber="F13" SignalGroup="Data" Bank="35" />
  62             <Pin SignalName="ddr3_dq[3]" PINNumber="K11" SignalGroup="Data" Bank="35" />
  63             <Pin SignalName="ddr3_dq[4]" PINNumber="L11" SignalGroup="Data" Bank="35" />
  64             <Pin SignalName="ddr3_dq[5]" PINNumber="K13" SignalGroup="Data" Bank="35" />
  65             <Pin SignalName="ddr3_dq[6]" PINNumber="K12" SignalGroup="Data" Bank="35" />
  66             <Pin SignalName="ddr3_dq[7]" PINNumber="D11" SignalGroup="Data" Bank="35" />
  67             <Pin SignalName="ddr3_dqs#[0]" PINNumber="E12" SignalGroup="Data" Bank="35" />
  68             <Pin SignalName="ddr3_dqs_p[0]" PINNumber="D12" SignalGroup="Data" Bank="35" />
  69             <Pin SignalName="ddr3_odt[0]" PINNumber="F18" SignalGroup="Address" Bank="36" />
  70             <Pin SignalName="ddr3_ras#" PINNumber="L19" SignalGroup="Address" Bank="36" />
  71             <Pin SignalName="ddr3_reset#" PINNumber="E18" SignalGroup="Address" Bank="36" />
  72             <Pin SignalName="ddr3_we#" PINNumber="B17" SignalGroup="Address" Bank="36" />
  73         </PinSelection>
  74         <BankSelection>
  75             <Bank SysClk="0" Data="1" name="35" Address="0" wasso="40" />
  76             <Bank SysClk="0" Data="0" name="36" Address="1" wasso="40" />
  77         </BankSelection>
  78         <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
  79         <mrBurstType name="Read Burst Type" >Sequential</mrBurstType>
  80         <mrCasLatency name="CAS Latency" >6</mrCasLatency>
  81         <mrMode name="Mode" >Normal</mrMode>
  82         <mrDllReset name="DLL Reset" >No</mrDllReset>
  83         <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
  84         <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
  85         <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
  86         <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
  87         <emrPosted name="Additive Latency (AL)" >0</emrPosted>
  88         <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
  89         <emrDQS name="TDQS enable" >Enabled</emrDQS>
  90         <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
  91         <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
  92         <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
  93         <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
  94         <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
  95         <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
  96         <PortInterface>AXI</PortInterface>
  97         <AXIParameters>
  98             <C_INTERCONNECT_S_AXI_AR_REGISTER>AUTOMATIC</C_INTERCONNECT_S_AXI_AR_REGISTER>
  99             <C_INTERCONNECT_S_AXI_AW_REGISTER>AUTOMATIC</C_INTERCONNECT_S_AXI_AW_REGISTER>
 100             <C_INTERCONNECT_S_AXI_B_REGISTER>AUTOMATIC</C_INTERCONNECT_S_AXI_B_REGISTER>
 101             <C_INTERCONNECT_S_AXI_MASTERS>microblaze_0.M_AXI_DC &amp; microblaze_0.M_AXI_IC</C_INTERCONNECT_S_AXI_MASTERS>
 102             <C_INTERCONNECT_S_AXI_READ_ACCEPTANCE>4</C_INTERCONNECT_S_AXI_READ_ACCEPTANCE>
 103             <C_INTERCONNECT_S_AXI_READ_FIFO_DEPTH>0</C_INTERCONNECT_S_AXI_READ_FIFO_DEPTH>
 104             <C_INTERCONNECT_S_AXI_R_REGISTER>AUTOMATIC</C_INTERCONNECT_S_AXI_R_REGISTER>
 105             <C_INTERCONNECT_S_AXI_SECURE>0</C_INTERCONNECT_S_AXI_SECURE>
 106             <C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE>4</C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE>
 107             <C_INTERCONNECT_S_AXI_WRITE_FIFO_DEPTH>0</C_INTERCONNECT_S_AXI_WRITE_FIFO_DEPTH>
 108             <C_INTERCONNECT_S_AXI_W_REGISTER>AUTOMATIC</C_INTERCONNECT_S_AXI_W_REGISTER>
 109             <C_S_AXI_ADDR_WIDTH>32</C_S_AXI_ADDR_WIDTH>
 110             <C_S_AXI_BASEADDR>0xc0000000</C_S_AXI_BASEADDR>
 111             <C_S_AXI_DATA_WIDTH>32</C_S_AXI_DATA_WIDTH>
 112             <C_S_AXI_HIGHADDR>0xcfffffff</C_S_AXI_HIGHADDR>
 113             <C_S_AXI_SUPPORTS_NARROW_BURST>Auto</C_S_AXI_SUPPORTS_NARROW_BURST>
 114         </AXIParameters>
 115     </Controller>
 116 </Project>