firmware/rolo.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 Randy D. Wood
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19
  20 #include "config.h"
  21 #include "lcd.h"
  22 #include "lcd-remote.h"
  23 #include "thread.h"
  24 #include "kernel.h"
  25 #include "sprintf.h"
  26 #include "button.h"
  27 #include "file.h"
  28 #include "audio.h"
  29 #include "system.h"
  30 #include "i2c.h"
  31 #include "adc.h"
  32 #include "string.h"
  33 #include "buffer.h"
  34 #include "rolo.h"
  35
  36 #ifdef MI4_FORMAT
  37 #include "crc32-mi4.h"
  38 #undef FIRMWARE_OFFSET_FILE_CRC
  39 #undef FIRMWARE_OFFSET_FILE_DATA
  40 #define FIRMWARE_OFFSET_FILE_CRC     0xC
  41 #define FIRMWARE_OFFSET_FILE_DATA    0x200
  42 #endif
  43
  44 #if !defined(IRIVER_IFP7XX_SERIES) && \
  45     (CONFIG_CPU != PP5002)
  46 /* FIX: this doesn't work on iFP, 3rd Gen ipods */
  47
  48 #define IRQ0_EDGE_TRIGGER 0x80
  49
  50 #ifdef CPU_PP
  51 /* Handle the COP properly - it needs to jump to a function outside SDRAM while
  52  * the new firmware is being loaded, and then jump to the start of SDRAM
  53  * TODO: Use the mailboxes built into the PP processor for this
  54  */
  55
  56 #if NUM_CORES > 1
  57 volatile unsigned char IDATA_ATTR cpu_message = 0;
  58 volatile unsigned char IDATA_ATTR cpu_reply = 0;
  59 extern int cop_idlestackbegin[];
  60
  61 void rolo_restart_cop(void) ICODE_ATTR;
  62 void rolo_restart_cop(void)
  63 {
  64     if (CURRENT_CORE == CPU)
  65     {
  66         /* There should be free thread slots aplenty */
  67         create_thread(rolo_restart_cop, cop_idlestackbegin, IDLE_STACK_SIZE,
  68                       0, "rolo COP" IF_PRIO(, PRIORITY_REALTIME)
  69                       IF_COP(, COP));
  70         return;
  71     }
  72
  73     COP_INT_CLR = -1;
  74
  75     /* Invalidate cache */
  76     invalidate_icache();
  77
  78     /* Disable cache */
  79     CACHE_CTL = CACHE_CTL_DISABLE;
  80
  81     /* Tell the main core that we're ready to reload */
  82     cpu_reply = 1;
  83
  84     /* Wait while RoLo loads the image into SDRAM */
  85     /* TODO: Accept checksum failure gracefully */
  86     while(cpu_message != 1);
  87
  88     /* Acknowledge the CPU and then reload */
  89     cpu_reply = 2;
  90
  91     asm volatile(
  92         "mov   r0, #0x10000000   \n"
  93         "mov   pc, r0            \n"
  94     );
  95 }
  96 #endif /* NUM_CORES > 1 */
  97 #endif /* CPU_PP */
  98
  99 static void rolo_error(const char *text)
 100 {
 101     lcd_clear_display();
 102     lcd_puts(0, 0, "ROLO error:");
 103     lcd_puts_scroll(0, 1, text);
 104     lcd_update();
 105     button_get(true);
 106     button_get(true);
 107     button_get(true);
 108     lcd_stop_scroll();
 109 }
 110
 111 #if CONFIG_CPU == SH7034 || CONFIG_CPU == IMX31L
 112 /* these are in assembler file "descramble.S" for SH7034 */
 113 extern unsigned short descramble(const unsigned char* source,
 114                                  unsigned char* dest, int length);
 115 /* this is in firmware/target/arm/imx31/rolo_restart.S for IMX31 */
 116 extern void rolo_restart(const unsigned char* source, unsigned char* dest,
 117                          int length);
 118 #else
 119
 120 /* explicitly put this code in iram, ICODE_ATTR is defined to be null for some
 121    targets that are low on iram, like the gigabeat F/X */
 122 void rolo_restart(const unsigned char* source, unsigned char* dest,
 123                   long length) __attribute__ ((section(".icode")));
 124 void rolo_restart(const unsigned char* source, unsigned char* dest,
 125                   long length)
 126 {
 127     long i;
 128     unsigned char* localdest = dest;
 129
 130     /* This is the equivalent of a call to memcpy() but this must be done from
 131        iram to avoid overwriting itself and we don't want to depend on memcpy()
 132        always being in iram */
 133     for(i = 0;i < length;i++)
 134         *localdest++ = *source++;
 135
 136 #if defined(CPU_COLDFIRE)
 137     asm (
 138         "movec.l %0,%%vbr    \n"
 139         "move.l  (%0)+,%%sp  \n"
 140         "move.l  (%0),%0     \n"
 141         "jmp     (%0)        \n"
 142         : : "a"(dest)
 143     );
 144 #elif defined(CPU_PP502x)
 145     CPU_INT_CLR = -1;
 146
 147     /* Flush cache */
 148     flush_icache();
 149
 150     /* Disable cache */
 151     CACHE_CTL = CACHE_CTL_DISABLE;
 152
 153     /* Reset the memory mapping registers to zero */
 154     {
 155         volatile unsigned long *mmap_reg;
 156         for (mmap_reg = &MMAP_FIRST; mmap_reg <= &MMAP_LAST; mmap_reg++)
 157             *mmap_reg = 0;
 158     }
 159
 160 #if NUM_CORES > 1
 161     /* Tell the COP it's safe to continue rebooting */
 162     cpu_message = 1;
 163
 164     /* Wait for the COP to tell us it is rebooting */
 165     while(cpu_reply != 2);
 166 #endif
 167
 168     asm volatile(
 169         "mov   r0, #0x10000000   \n"
 170         "mov   pc, r0            \n"
 171     );
 172
 173 #elif defined(CPU_TCC780X) || (CONFIG_CPU == S3C2440)
 174     /* Flush and invalidate caches */
 175     invalidate_icache();
 176
 177     asm volatile(
 178         "mov   pc, %0            \n"
 179         : : "r"(dest)
 180     );
 181 #endif
 182 }
 183 #endif
 184
 185 /* This is assigned in the linker control file */
 186 extern unsigned long loadaddress;
 187
 188 /***************************************************************************
 189  *
 190  * Name: rolo_load_app(char *filename,int scrambled)
 191  * Filename must be a fully defined filename including the path and extension
 192  *
 193  ***************************************************************************/
 194 int rolo_load(const char* filename)
 195 {
 196     int fd;
 197     long length;
 198 #if defined(CPU_COLDFIRE) || defined(CPU_ARM)
 199 #if !defined(MI4_FORMAT)
 200     int i;
 201 #endif
 202     unsigned long checksum,file_checksum;
 203 #else
 204     long file_length;
 205     unsigned short checksum,file_checksum;
 206 #endif
 207     unsigned char* ramstart = (void*)&loadaddress;
 208
 209     lcd_clear_display();
 210     lcd_puts(0, 0, "ROLO...");
 211     lcd_puts(0, 1, "Loading");
 212     lcd_update();
 213 #ifdef HAVE_REMOTE_LCD
 214     lcd_remote_clear_display();
 215     lcd_remote_puts(0, 0, "ROLO...");
 216     lcd_remote_puts(0, 1, "Loading");
 217     lcd_remote_update();
 218 #endif
 219
 220     audio_stop();
 221
 222     fd = open(filename, O_RDONLY);
 223     if(-1 == fd) {
 224         rolo_error("File not found");
 225         return -1;
 226     }
 227
 228     length = filesize(fd) - FIRMWARE_OFFSET_FILE_DATA;
 229
 230 #if defined(CPU_COLDFIRE) || defined(CPU_PP) || (CONFIG_CPU==DM320) \
 231      || defined(CPU_TCC780X) || (CONFIG_CPU==IMX31L) || (CONFIG_CPU == S3C2440)
 232     /* Read and save checksum */
 233     lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
 234     if (read(fd, &file_checksum, 4) != 4) {
 235         rolo_error("Error Reading checksum");
 236         return -1;
 237     }
 238
 239 #if !defined(MI4_FORMAT)
 240     /* Rockbox checksums are big-endian */
 241     file_checksum = betoh32(file_checksum);
 242 #endif
 243
 244 #if defined(CPU_PP) && NUM_CORES > 1
 245     lcd_puts(0, 2, "Waiting for coprocessor...");
 246     lcd_update();
 247     rolo_restart_cop();
 248     /* Wait for COP to be in safe code */
 249     while(cpu_reply != 1);
 250     lcd_puts(0, 2, "                          ");
 251     lcd_update();
 252 #endif
 253
 254     lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
 255
 256     if (read(fd, audiobuf, length) != length) {
 257         rolo_error("Error Reading File");
 258         return -1;
 259     }
 260
 261 #ifdef MI4_FORMAT
 262     /* Check CRC32 to see if we have a valid file */
 263     chksum_crc32gentab();
 264     checksum = chksum_crc32 (audiobuf, length);
 265 #else
 266     checksum = MODEL_NUMBER;
 267
 268     for(i = 0;i < length;i++) {
 269         checksum += audiobuf[i];
 270     }
 271 #endif
 272
 273     /* Verify checksum against file header */
 274     if (checksum != file_checksum) {
 275         rolo_error("Checksum Error");
 276         return -1;
 277     }
 278
 279     lcd_puts(0, 1, "Executing");
 280     lcd_update();
 281 #ifdef HAVE_REMOTE_LCD
 282     lcd_remote_puts(0, 1, "Executing");
 283     lcd_remote_update();
 284 #endif
 285     adc_close();
 286
 287 #ifdef CPU_ARM
 288     /* Should do these together since some ARM version should never have
 289      * FIQ disabled and not IRQ (imx31 errata). */
 290     disable_interrupt(IRQ_FIQ_STATUS);
 291 #else
 292     /* Some targets have a higher disable level than HIGEST_IRQ_LEVEL */
 293     set_irq_level(DISABLE_INTERRUPTS);
 294 #endif
 295
 296 #elif CONFIG_CPU == SH7034
 297     /* Read file length from header and compare to real file length */
 298     lseek(fd, FIRMWARE_OFFSET_FILE_LENGTH, SEEK_SET);
 299     if(read(fd, &file_length, 4) != 4) {
 300         rolo_error("Error Reading File Length");
 301         return -1;
 302     }
 303     if (length != file_length) {
 304         rolo_error("File length mismatch");
 305         return -1;
 306     }
 307
 308     /* Read and save checksum */
 309     lseek(fd, FIRMWARE_OFFSET_FILE_CRC, SEEK_SET);
 310     if (read(fd, &file_checksum, 2) != 2) {
 311         rolo_error("Error Reading checksum");
 312         return -1;
 313     }
 314     lseek(fd, FIRMWARE_OFFSET_FILE_DATA, SEEK_SET);
 315
 316     /* verify that file can be read and descrambled */
 317     if ((audiobuf + (2*length)+4) >= audiobufend) {
 318         rolo_error("Not enough room to load file");
 319         return -1;
 320     }
 321
 322     if (read(fd, &audiobuf[length], length) != (int)length) {
 323         rolo_error("Error Reading File");
 324         return -1;
 325     }
 326
 327     lcd_puts(0, 1, "Descramble");
 328     lcd_update();
 329
 330     checksum = descramble(audiobuf + length, audiobuf, length);
 331
 332     /* Verify checksum against file header */
 333     if (checksum != file_checksum) {
 334         rolo_error("Checksum Error");
 335         return -1;
 336     }
 337
 338     lcd_puts(0, 1, "Executing     ");
 339     lcd_update();
 340
 341     set_irq_level(HIGHEST_IRQ_LEVEL);
 342
 343     /* Calling these 2 initialization routines was necessary to get the
 344        the origional Archos version of the firmware to load and execute. */
 345     system_init();           /* Initialize system for restart */
 346     i2c_init();              /* Init i2c bus - it seems like a good idea */
 347     ICR = IRQ0_EDGE_TRIGGER; /* Make IRQ0 edge triggered */
 348     TSTR = 0xE0;             /* disable all timers */
 349     /* model-specific de-init, needed when flashed */
 350     /* Especially the Archos software is picky about this */
 351 #if defined(ARCHOS_RECORDER) || defined(ARCHOS_RECORDERV2) || \
 352     defined(ARCHOS_FMRECORDER)
 353     PAIOR = 0x0FA0;
 354 #endif
 355 #endif
 356     rolo_restart(audiobuf, ramstart, length);
 357
 358     return 0; /* this is never reached */
 359     (void)checksum; (void)file_checksum;
 360 }
 361 #else  /* !defined(IRIVER_IFP7XX_SERIES) */
 362 int rolo_load(const char* filename)
 363 {
 364     /* dummy */
 365     (void)filename;
 366     return 0;
 367 }
 368
 369 #endif /* !defined(IRIVER_IFP7XX_SERIES) */