firmware/target/arm/usb-drv-pp502x.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id:  $
   9  *
  10  * Driver for ARC USBOTG Device Controller
  11  *
  12  * Copyright (C) 2007 by Björn Stenberg
  13  *
  14  * All files in this archive are subject to the GNU General Public License.
  15  * See the file COPYING in the source tree root for full license agreement.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "system.h"
  23 #include "string.h"
  24 #include "usb_ch9.h"
  25 #include "usb_core.h"
  26 //#define LOGF_ENABLE
  27 #include "logf.h"
  28
  29 /* USB device mode registers (Little Endian) */
  30
  31 #define REG_ID               (*(volatile unsigned int *)(USB_BASE+0x000))
  32 #define REG_HWGENERAL        (*(volatile unsigned int *)(USB_BASE+0x004))
  33 #define REG_HWHOST           (*(volatile unsigned int *)(USB_BASE+0x008))
  34 #define REG_HWDEVICE         (*(volatile unsigned int *)(USB_BASE+0x00c))
  35 #define REG_TXBUF            (*(volatile unsigned int *)(USB_BASE+0x010))
  36 #define REG_RXBUF            (*(volatile unsigned int *)(USB_BASE+0x014))
  37 #define REG_CAPLENGTH        (*(volatile unsigned char*)(USB_BASE+0x100))
  38 #define REG_DCIVERSION       (*(volatile unsigned int *)(USB_BASE+0x120))
  39 #define REG_DCCPARAMS        (*(volatile unsigned int *)(USB_BASE+0x124))
  40 #define REG_USBCMD           (*(volatile unsigned int *)(USB_BASE+0x140))
  41 #define REG_USBSTS           (*(volatile unsigned int *)(USB_BASE+0x144))
  42 #define REG_USBINTR          (*(volatile unsigned int *)(USB_BASE+0x148))
  43 #define REG_FRINDEX          (*(volatile unsigned int *)(USB_BASE+0x14c))
  44 #define REG_DEVICEADDR       (*(volatile unsigned int *)(USB_BASE+0x154))
  45 #define REG_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
  46 #define REG_BURSTSIZE        (*(volatile unsigned int *)(USB_BASE+0x160))
  47 #define REG_CONFIGFLAG       (*(volatile unsigned int *)(USB_BASE+0x180))
  48 #define REG_PORTSC1          (*(volatile unsigned int *)(USB_BASE+0x184))
  49 #define REG_OTGSC            (*(volatile unsigned int *)(USB_BASE+0x1a4))
  50 #define REG_USBMODE          (*(volatile unsigned int *)(USB_BASE+0x1a8))
  51 #define REG_ENDPTSETUPSTAT   (*(volatile unsigned int *)(USB_BASE+0x1ac))
  52 #define REG_ENDPTPRIME       (*(volatile unsigned int *)(USB_BASE+0x1b0))
  53 #define REG_ENDPTFLUSH       (*(volatile unsigned int *)(USB_BASE+0x1b4))
  54 #define REG_ENDPTSTATUS      (*(volatile unsigned int *)(USB_BASE+0x1b8))
  55 #define REG_ENDPTCOMPLETE    (*(volatile unsigned int *)(USB_BASE+0x1bc))
  56 #define REG_ENDPTCTRL0       (*(volatile unsigned int *)(USB_BASE+0x1c0))
  57 #define REG_ENDPTCTRL1       (*(volatile unsigned int *)(USB_BASE+0x1c4))
  58 #define REG_ENDPTCTRL2       (*(volatile unsigned int *)(USB_BASE+0x1c8))
  59 #define REG_ENDPTCTRL(_x_)   (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(_x_)))
  60
  61 /* Frame Index Register Bit Masks */
  62 #define USB_FRINDEX_MASKS                      (0x3fff)
  63
  64 /* USB CMD  Register Bit Masks */
  65 #define USBCMD_RUN                            (0x00000001)
  66 #define USBCMD_CTRL_RESET                     (0x00000002)
  67 #define USBCMD_PERIODIC_SCHEDULE_EN           (0x00000010)
  68 #define USBCMD_ASYNC_SCHEDULE_EN              (0x00000020)
  69 #define USBCMD_INT_AA_DOORBELL                (0x00000040)
  70 #define USBCMD_ASP                            (0x00000300)
  71 #define USBCMD_ASYNC_SCH_PARK_EN              (0x00000800)
  72 #define USBCMD_SUTW                           (0x00002000)
  73 #define USBCMD_ATDTW                          (0x00004000)
  74 #define USBCMD_ITC                            (0x00FF0000)
  75
  76 /* bit 15,3,2 are frame list size */
  77 #define USBCMD_FRAME_SIZE_1024                (0x00000000)
  78 #define USBCMD_FRAME_SIZE_512                 (0x00000004)
  79 #define USBCMD_FRAME_SIZE_256                 (0x00000008)
  80 #define USBCMD_FRAME_SIZE_128                 (0x0000000C)
  81 #define USBCMD_FRAME_SIZE_64                  (0x00008000)
  82 #define USBCMD_FRAME_SIZE_32                  (0x00008004)
  83 #define USBCMD_FRAME_SIZE_16                  (0x00008008)
  84 #define USBCMD_FRAME_SIZE_8                   (0x0000800C)
  85
  86 /* bit 9-8 are async schedule park mode count */
  87 #define USBCMD_ASP_00                         (0x00000000)
  88 #define USBCMD_ASP_01                         (0x00000100)
  89 #define USBCMD_ASP_10                         (0x00000200)
  90 #define USBCMD_ASP_11                         (0x00000300)
  91 #define USBCMD_ASP_BIT_POS                    (8)
  92
  93 /* bit 23-16 are interrupt threshold control */
  94 #define USBCMD_ITC_NO_THRESHOLD               (0x00000000)
  95 #define USBCMD_ITC_1_MICRO_FRM                (0x00010000)
  96 #define USBCMD_ITC_2_MICRO_FRM                (0x00020000)
  97 #define USBCMD_ITC_4_MICRO_FRM                (0x00040000)
  98 #define USBCMD_ITC_8_MICRO_FRM                (0x00080000)
  99 #define USBCMD_ITC_16_MICRO_FRM               (0x00100000)
 100 #define USBCMD_ITC_32_MICRO_FRM               (0x00200000)
 101 #define USBCMD_ITC_64_MICRO_FRM               (0x00400000)
 102 #define USBCMD_ITC_BIT_POS                    (16)
 103
 104 /* USB STS Register Bit Masks */
 105 #define USBSTS_INT                            (0x00000001)
 106 #define USBSTS_ERR                            (0x00000002)
 107 #define USBSTS_PORT_CHANGE                    (0x00000004)
 108 #define USBSTS_FRM_LST_ROLL                   (0x00000008)
 109 #define USBSTS_SYS_ERR                        (0x00000010) /* not used */
 110 #define USBSTS_IAA                            (0x00000020)
 111 #define USBSTS_RESET                          (0x00000040)
 112 #define USBSTS_SOF                            (0x00000080)
 113 #define USBSTS_SUSPEND                        (0x00000100)
 114 #define USBSTS_HC_HALTED                      (0x00001000)
 115 #define USBSTS_RCL                            (0x00002000)
 116 #define USBSTS_PERIODIC_SCHEDULE              (0x00004000)
 117 #define USBSTS_ASYNC_SCHEDULE                 (0x00008000)
 118
 119 /* USB INTR Register Bit Masks */
 120 #define USBINTR_INT_EN                        (0x00000001)
 121 #define USBINTR_ERR_INT_EN                    (0x00000002)
 122 #define USBINTR_PTC_DETECT_EN                 (0x00000004)
 123 #define USBINTR_FRM_LST_ROLL_EN               (0x00000008)
 124 #define USBINTR_SYS_ERR_EN                    (0x00000010)
 125 #define USBINTR_ASYN_ADV_EN                   (0x00000020)
 126 #define USBINTR_RESET_EN                      (0x00000040)
 127 #define USBINTR_SOF_EN                        (0x00000080)
 128 #define USBINTR_DEVICE_SUSPEND                (0x00000100)
 129
 130 /* Device Address bit masks */
 131 #define USBDEVICEADDRESS_MASK                 (0xFE000000)
 132 #define USBDEVICEADDRESS_BIT_POS              (25)
 133
 134 /* endpoint list address bit masks */
 135 #define USB_EP_LIST_ADDRESS_MASK               (0xfffff800)
 136
 137 /* PORTSCX  Register Bit Masks */
 138 #define PORTSCX_CURRENT_CONNECT_STATUS         (0x00000001)
 139 #define PORTSCX_CONNECT_STATUS_CHANGE          (0x00000002)
 140 #define PORTSCX_PORT_ENABLE                    (0x00000004)
 141 #define PORTSCX_PORT_EN_DIS_CHANGE             (0x00000008)
 142 #define PORTSCX_OVER_CURRENT_ACT               (0x00000010)
 143 #define PORTSCX_OVER_CURRENT_CHG               (0x00000020)
 144 #define PORTSCX_PORT_FORCE_RESUME              (0x00000040)
 145 #define PORTSCX_PORT_SUSPEND                   (0x00000080)
 146 #define PORTSCX_PORT_RESET                     (0x00000100)
 147 #define PORTSCX_LINE_STATUS_BITS               (0x00000C00)
 148 #define PORTSCX_PORT_POWER                     (0x00001000)
 149 #define PORTSCX_PORT_INDICTOR_CTRL             (0x0000C000)
 150 #define PORTSCX_PORT_TEST_CTRL                 (0x000F0000)
 151 #define PORTSCX_WAKE_ON_CONNECT_EN             (0x00100000)
 152 #define PORTSCX_WAKE_ON_CONNECT_DIS            (0x00200000)
 153 #define PORTSCX_WAKE_ON_OVER_CURRENT           (0x00400000)
 154 #define PORTSCX_PHY_LOW_POWER_SPD              (0x00800000)
 155 #define PORTSCX_PORT_FORCE_FULL_SPEED          (0x01000000)
 156 #define PORTSCX_PORT_SPEED_MASK                (0x0C000000)
 157 #define PORTSCX_PORT_WIDTH                     (0x10000000)
 158 #define PORTSCX_PHY_TYPE_SEL                   (0xC0000000)
 159
 160 /* bit 11-10 are line status */
 161 #define PORTSCX_LINE_STATUS_SE0                (0x00000000)
 162 #define PORTSCX_LINE_STATUS_JSTATE             (0x00000400)
 163 #define PORTSCX_LINE_STATUS_KSTATE             (0x00000800)
 164 #define PORTSCX_LINE_STATUS_UNDEF              (0x00000C00)
 165 #define PORTSCX_LINE_STATUS_BIT_POS            (10)
 166
 167 /* bit 15-14 are port indicator control */
 168 #define PORTSCX_PIC_OFF                        (0x00000000)
 169 #define PORTSCX_PIC_AMBER                      (0x00004000)
 170 #define PORTSCX_PIC_GREEN                      (0x00008000)
 171 #define PORTSCX_PIC_UNDEF                      (0x0000C000)
 172 #define PORTSCX_PIC_BIT_POS                    (14)
 173
 174 /* bit 19-16 are port test control */
 175 #define PORTSCX_PTC_DISABLE                    (0x00000000)
 176 #define PORTSCX_PTC_JSTATE                     (0x00010000)
 177 #define PORTSCX_PTC_KSTATE                     (0x00020000)
 178 #define PORTSCX_PTC_SE0NAK                     (0x00030000)
 179 #define PORTSCX_PTC_PACKET                     (0x00040000)
 180 #define PORTSCX_PTC_FORCE_EN                   (0x00050000)
 181 #define PORTSCX_PTC_BIT_POS                    (16)
 182
 183 /* bit 27-26 are port speed */
 184 #define PORTSCX_PORT_SPEED_FULL                (0x00000000)
 185 #define PORTSCX_PORT_SPEED_LOW                 (0x04000000)
 186 #define PORTSCX_PORT_SPEED_HIGH                (0x08000000)
 187 #define PORTSCX_PORT_SPEED_UNDEF               (0x0C000000)
 188 #define PORTSCX_SPEED_BIT_POS                  (26)
 189
 190 /* bit 28 is parallel transceiver width for UTMI interface */
 191 #define PORTSCX_PTW                            (0x10000000)
 192 #define PORTSCX_PTW_8BIT                       (0x00000000)
 193 #define PORTSCX_PTW_16BIT                      (0x10000000)
 194
 195 /* bit 31-30 are port transceiver select */
 196 #define PORTSCX_PTS_UTMI                       (0x00000000)
 197 #define PORTSCX_PTS_ULPI                       (0x80000000)
 198 #define PORTSCX_PTS_FSLS                       (0xC0000000)
 199 #define PORTSCX_PTS_BIT_POS                    (30)
 200
 201 /* USB MODE Register Bit Masks */
 202 #define USBMODE_CTRL_MODE_IDLE                (0x00000000)
 203 #define USBMODE_CTRL_MODE_DEVICE              (0x00000002)
 204 #define USBMODE_CTRL_MODE_HOST                (0x00000003)
 205 #define USBMODE_CTRL_MODE_RSV                 (0x00000001)
 206 #define USBMODE_SETUP_LOCK_OFF                (0x00000008)
 207 #define USBMODE_STREAM_DISABLE                (0x00000010)
 208
 209 /* Endpoint Flush Register */
 210 #define EPFLUSH_TX_OFFSET                      (0x00010000)
 211 #define EPFLUSH_RX_OFFSET                      (0x00000000)
 212
 213 /* Endpoint Setup Status bit masks */
 214 #define EPSETUP_STATUS_MASK                   (0x0000003F)
 215 #define EPSETUP_STATUS_EP0                    (0x00000001)
 216
 217 /* ENDPOINTCTRLx  Register Bit Masks */
 218 #define EPCTRL_TX_ENABLE                       (0x00800000)
 219 #define EPCTRL_TX_DATA_TOGGLE_RST              (0x00400000)    /* Not EP0 */
 220 #define EPCTRL_TX_DATA_TOGGLE_INH              (0x00200000)    /* Not EP0 */
 221 #define EPCTRL_TX_TYPE                         (0x000C0000)
 222 #define EPCTRL_TX_DATA_SOURCE                  (0x00020000)    /* Not EP0 */
 223 #define EPCTRL_TX_EP_STALL                     (0x00010000)
 224 #define EPCTRL_RX_ENABLE                       (0x00000080)
 225 #define EPCTRL_RX_DATA_TOGGLE_RST              (0x00000040)    /* Not EP0 */
 226 #define EPCTRL_RX_DATA_TOGGLE_INH              (0x00000020)    /* Not EP0 */
 227 #define EPCTRL_RX_TYPE                         (0x0000000C)
 228 #define EPCTRL_RX_DATA_SINK                    (0x00000002)    /* Not EP0 */
 229 #define EPCTRL_RX_EP_STALL                     (0x00000001)
 230
 231 /* bit 19-18 and 3-2 are endpoint type */
 232 #define EPCTRL_EP_TYPE_CONTROL                 (0)
 233 #define EPCTRL_EP_TYPE_ISO                     (1)
 234 #define EPCTRL_EP_TYPE_BULK                    (2)
 235 #define EPCTRL_EP_TYPE_INTERRUPT               (3)
 236 #define EPCTRL_TX_EP_TYPE_SHIFT                (18)
 237 #define EPCTRL_RX_EP_TYPE_SHIFT                (2)
 238
 239 /* pri_ctrl Register Bit Masks */
 240 #define PRI_CTRL_PRI_LVL1                      (0x0000000C)
 241 #define PRI_CTRL_PRI_LVL0                      (0x00000003)
 242
 243 /* si_ctrl Register Bit Masks */
 244 #define SI_CTRL_ERR_DISABLE                    (0x00000010)
 245 #define SI_CTRL_IDRC_DISABLE                   (0x00000008)
 246 #define SI_CTRL_RD_SAFE_EN                     (0x00000004)
 247 #define SI_CTRL_RD_PREFETCH_DISABLE            (0x00000002)
 248 #define SI_CTRL_RD_PREFEFETCH_VAL              (0x00000001)
 249
 250 /* control Register Bit Masks */
 251 #define USB_CTRL_IOENB                         (0x00000004)
 252 #define USB_CTRL_ULPI_INT0EN                   (0x00000001)
 253
 254 /* OTGSC Register Bit Masks */
 255 #define OTGSC_B_SESSION_VALID                  (0x00000800)
 256
 257 #define QH_MULT_POS                            (30)
 258 #define QH_ZLT_SEL                             (0x20000000)
 259 #define QH_MAX_PKT_LEN_POS                     (16)
 260 #define QH_IOS                                 (0x00008000)
 261 #define QH_NEXT_TERMINATE                      (0x00000001)
 262 #define QH_IOC                                 (0x00008000)
 263 #define QH_MULTO                               (0x00000C00)
 264 #define QH_STATUS_HALT                         (0x00000040)
 265 #define QH_STATUS_ACTIVE                       (0x00000080)
 266 #define EP_QUEUE_CURRENT_OFFSET_MASK         (0x00000FFF)
 267 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK      (0xFFFFFFE0)
 268 #define EP_QUEUE_FRINDEX_MASK                (0x000007FF)
 269 #define EP_MAX_LENGTH_TRANSFER               (0x4000)
 270
 271 #define DTD_NEXT_TERMINATE                   (0x00000001)
 272 #define DTD_IOC                              (0x00008000)
 273 #define DTD_STATUS_ACTIVE                    (0x00000080)
 274 #define DTD_STATUS_HALTED                    (0x00000040)
 275 #define DTD_STATUS_DATA_BUFF_ERR             (0x00000020)
 276 #define DTD_STATUS_TRANSACTION_ERR           (0x00000008)
 277 #define DTD_RESERVED_FIELDS                  (0x80007300)
 278 #define DTD_ADDR_MASK                        (0xFFFFFFE0)
 279 #define DTD_PACKET_SIZE                      (0x7FFF0000)
 280 #define DTD_LENGTH_BIT_POS                   (16)
 281 #define DTD_ERROR_MASK                       (DTD_STATUS_HALTED | \
 282                                                DTD_STATUS_DATA_BUFF_ERR | \
 283                                                DTD_STATUS_TRANSACTION_ERR)
 284
 285 #define DTD_RESERVED_LENGTH_MASK             0x0001ffff
 286 #define DTD_RESERVED_IN_USE                  0x80000000
 287 #define DTD_RESERVED_PIPE_MASK               0x0ff00000
 288 #define DTD_RESERVED_PIPE_OFFSET             20
 289 /*-------------------------------------------------------------------------*/
 290
 291 /* manual: 32.13.2 Endpoint Transfer Descriptor (dTD) */
 292 struct transfer_descriptor {
 293     unsigned int next_td_ptr;           /* Next TD pointer(31-5), T(0) set
 294                                            indicate invalid */
 295     unsigned int size_ioc_sts;          /* Total bytes (30-16), IOC (15),
 296                                            MultO(11-10), STS (7-0)  */
 297     unsigned int buff_ptr0;             /* Buffer pointer Page 0 */
 298     unsigned int buff_ptr1;             /* Buffer pointer Page 1 */
 299     unsigned int buff_ptr2;             /* Buffer pointer Page 2 */
 300     unsigned int buff_ptr3;             /* Buffer pointer Page 3 */
 301     unsigned int buff_ptr4;             /* Buffer pointer Page 4 */
 302     unsigned int reserved;
 303 } __attribute__ ((packed));
 304
 305 static struct transfer_descriptor _td_array[NUM_ENDPOINTS*2] __attribute((aligned (32)));
 306 static struct transfer_descriptor* td_array;
 307
 308 /* manual: 32.13.1 Endpoint Queue Head (dQH) */
 309 struct queue_head {
 310     unsigned int max_pkt_length;    /* Mult(31-30) , Zlt(29) , Max Pkt len
 311                                        and IOS(15) */
 312     unsigned int curr_dtd_ptr;      /* Current dTD Pointer(31-5) */
 313     struct transfer_descriptor dtd; /* dTD overlay */
 314     unsigned int setup_buffer[2];   /* Setup data 8 bytes */
 315     unsigned int reserved;          /* for software use, pointer to the first TD */
 316     unsigned int status;            /* for software use, status of chain in progress */
 317     unsigned int length;            /* for software use, transfered bytes of chain in progress */
 318     unsigned int wait;              /* for softwate use, indicates if the transfer is blocking */
 319 } __attribute__((packed));
 320
 321 static struct queue_head _qh_array[NUM_ENDPOINTS*2] __attribute((aligned (2048)));
 322 static struct queue_head* qh_array;
 323 static struct event_queue transfer_completion_queue[NUM_ENDPOINTS*2];
 324
 325
 326 static const unsigned int pipe2mask[] = {
 327     0x01, 0x010000,
 328     0x02, 0x020000,
 329     0x04, 0x040000,
 330     0x08, 0x080000,
 331     0x10, 0x100000,
 332 };
 333
 334 /*-------------------------------------------------------------------------*/
 335 static void transfer_completed(void);
 336 static void control_received(void);
 337 static int prime_transfer(int endpoint, void* ptr,
 338                           int len, bool send, bool wait);
 339 static void prepare_td(struct transfer_descriptor* td,
 340                        struct transfer_descriptor* previous_td,
 341                        void *ptr, int len,int pipe);
 342 static void bus_reset(void);
 343 static void init_control_queue_heads(void);
 344 static void init_bulk_queue_heads(void);
 345 static void init_endpoints(void);
 346 /*-------------------------------------------------------------------------*/
 347
 348 bool usb_drv_powered(void)
 349 {
 350     return (REG_OTGSC & OTGSC_B_SESSION_VALID) ? true : false;
 351 }
 352
 353 /* manual: 32.14.1 Device Controller Initialization */
 354 void usb_drv_init(void)
 355 {
 356     trigger_cpu_boost();
 357     REG_USBCMD &= ~USBCMD_RUN;
 358     udelay(50000);
 359     REG_USBCMD |= USBCMD_CTRL_RESET;
 360     while (REG_USBCMD & USBCMD_CTRL_RESET);
 361
 362
 363     REG_USBMODE = USBMODE_CTRL_MODE_DEVICE;
 364
 365 #ifndef USE_HIGH_SPEED
 366     /* Force device to full speed */
 367     /* See 32.9.5.9.2 */
 368     REG_PORTSC1 |= PORTSCX_PORT_FORCE_FULL_SPEED;
 369 #endif
 370
 371     td_array = (struct transfer_descriptor*)UNCACHED_ADDR(&_td_array);
 372     qh_array = (struct queue_head*)UNCACHED_ADDR(&_qh_array);
 373     init_control_queue_heads();
 374     memset(td_array, 0, sizeof _td_array);
 375
 376     REG_ENDPOINTLISTADDR = (unsigned int)qh_array;
 377     REG_DEVICEADDR = 0;
 378
 379     /* enable USB interrupts */
 380     REG_USBINTR =
 381         USBINTR_INT_EN |
 382         USBINTR_ERR_INT_EN |
 383         USBINTR_PTC_DETECT_EN |
 384         USBINTR_RESET_EN |
 385         USBINTR_SYS_ERR_EN;
 386
 387     /* enable USB IRQ in CPU */
 388     CPU_INT_EN |= USB_MASK;
 389
 390     /* go go go */
 391     REG_USBCMD |= USBCMD_RUN;
 392
 393
 394     logf("usb_drv_init() finished");
 395     logf("usb id %x", REG_ID);
 396     logf("usb dciversion %x", REG_DCIVERSION);
 397     logf("usb dccparams %x", REG_DCCPARAMS);
 398
 399     /* now a bus reset will occur. see bus_reset() */
 400 }
 401
 402 void usb_drv_exit(void)
 403 {
 404     /* disable interrupts */
 405     REG_USBINTR = 0;
 406
 407     /* stop usb controller */
 408     REG_USBCMD &= ~USBCMD_RUN;
 409
 410     /* TODO : is one of these needed to save power ?
 411     REG_PORTSC1 |= PORTSCX_PHY_LOW_POWER_SPD;
 412     REG_USBCMD |= USBCMD_CTRL_RESET;
 413     */
 414
 415     cancel_cpu_boost();
 416 }
 417
 418 void usb_drv_int(void)
 419 {
 420     unsigned int status = REG_USBSTS;
 421
 422 #if 0
 423     if (status & USBSTS_INT) logf("int: usb ioc");
 424     if (status & USBSTS_ERR) logf("int: usb err");
 425     if (status & USBSTS_PORT_CHANGE) logf("int: portchange");
 426     if (status & USBSTS_RESET) logf("int: reset");
 427     if (status & USBSTS_SYS_ERR) logf("int: syserr");
 428 #endif
 429
 430     /* usb transaction interrupt */
 431     if (status & USBSTS_INT) {
 432         REG_USBSTS |= USBSTS_INT;
 433
 434         /* a control packet? */
 435         if (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0) {
 436             control_received();
 437         }
 438
 439         if (REG_ENDPTCOMPLETE)
 440             transfer_completed();
 441     }
 442
 443     /* error interrupt */
 444     if (status & USBSTS_ERR) {
 445         REG_USBSTS |= USBSTS_ERR;
 446         logf("usb error int");
 447     }
 448
 449     /* reset interrupt */
 450     if (status & USBSTS_RESET) {
 451         REG_USBSTS |= USBSTS_RESET;
 452         bus_reset();
 453         usb_core_bus_reset(); /* tell mom */
 454     }
 455
 456     /* port change */
 457     if (status & USBSTS_PORT_CHANGE) {
 458         REG_USBSTS |= USBSTS_PORT_CHANGE;
 459     }
 460 }
 461
 462 bool usb_drv_stalled(int endpoint,bool in)
 463 {
 464     if(in) {
 465         return ((REG_ENDPTCTRL(endpoint) & EPCTRL_TX_EP_STALL)!=0);
 466     }
 467     else {
 468         return ((REG_ENDPTCTRL(endpoint) & EPCTRL_RX_EP_STALL)!=0);
 469     }
 470
 471 }
 472 void usb_drv_stall(int endpoint, bool stall,bool in)
 473 {
 474     logf("%sstall %d", stall?"":"un", endpoint);
 475
 476     if(in) {
 477         if (stall) {
 478             REG_ENDPTCTRL(endpoint) |= EPCTRL_TX_EP_STALL;
 479         }
 480         else {
 481             REG_ENDPTCTRL(endpoint) &= ~EPCTRL_TX_EP_STALL;
 482         }
 483     }
 484     else {
 485         if (stall) {
 486             REG_ENDPTCTRL(endpoint) |= EPCTRL_RX_EP_STALL;
 487         }
 488         else {
 489             REG_ENDPTCTRL(endpoint) &= ~EPCTRL_RX_EP_STALL;
 490         }
 491     }
 492 }
 493
 494 int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
 495 {
 496     return prime_transfer(endpoint, ptr, length, true, false);
 497 }
 498
 499 int usb_drv_send(int endpoint, void* ptr, int length)
 500 {
 501     return prime_transfer(endpoint, ptr, length, true, true);
 502 }
 503
 504 int usb_drv_recv(int endpoint, void* ptr, int length)
 505 {
 506     //logf("usbrecv(%x, %d)", ptr, length);
 507     return prime_transfer(endpoint, ptr, length, false, false);
 508 }
 509
 510 void usb_drv_wait(int endpoint, bool send)
 511 {
 512     int pipe = endpoint * 2 + (send ? 1 : 0);
 513     struct queue_head* qh = &qh_array[pipe];
 514
 515     while (qh->dtd.size_ioc_sts & QH_STATUS_ACTIVE) {
 516         if (REG_USBSTS & USBSTS_RESET)
 517             break;
 518     }
 519 }
 520
 521 int usb_drv_port_speed(void)
 522 {
 523     return (REG_PORTSC1 & 0x08000000) ? 1 : 0;
 524 }
 525
 526 bool usb_drv_connected(void)
 527 {
 528     return ((REG_PORTSC1 & PORTSCX_CURRENT_CONNECT_STATUS) !=0);
 529 }
 530
 531 void usb_drv_set_address(int address)
 532 {
 533     REG_DEVICEADDR = address << USBDEVICEADDRESS_BIT_POS;
 534     init_bulk_queue_heads();
 535     init_endpoints();
 536 }
 537
 538 void usb_drv_reset_endpoint(int endpoint, bool send)
 539 {
 540     int pipe = endpoint * 2 + (send ? 1 : 0);
 541     unsigned int mask = pipe2mask[pipe];
 542     REG_ENDPTFLUSH = mask;
 543     while (REG_ENDPTFLUSH & mask);
 544 }
 545
 546 void usb_drv_set_test_mode(int mode)
 547 {
 548     switch(mode){
 549         case 0:
 550             REG_PORTSC1 &= ~PORTSCX_PORT_TEST_CTRL;
 551             break;
 552         case 1:
 553             REG_PORTSC1 |= PORTSCX_PTC_JSTATE;
 554             break;
 555         case 2:
 556             REG_PORTSC1 |= PORTSCX_PTC_KSTATE;
 557             break;
 558         case 3:
 559             REG_PORTSC1 |= PORTSCX_PTC_SE0NAK;
 560             break;
 561         case 4:
 562             REG_PORTSC1 |= PORTSCX_PTC_PACKET;
 563             break;
 564         case 5:
 565             REG_PORTSC1 |= PORTSCX_PTC_FORCE_EN;
 566             break;
 567     }
 568     REG_USBCMD &= ~USBCMD_RUN;
 569     udelay(50000);
 570     REG_USBCMD |= USBCMD_CTRL_RESET;
 571     while (REG_USBCMD & USBCMD_CTRL_RESET);
 572     REG_USBCMD |= USBCMD_RUN;
 573 }
 574
 575 /*-------------------------------------------------------------------------*/
 576
 577 /* manual: 32.14.5.2 */
 578 static int prime_transfer(int endpoint, void* ptr, int len, bool send, bool wait)
 579 {
 580     int pipe = endpoint * 2 + (send ? 1 : 0);
 581     unsigned int mask = pipe2mask[pipe];
 582     struct queue_head* qh = &qh_array[pipe];
 583     static long last_tick;
 584     struct transfer_descriptor* new_td;
 585
 586 /*
 587     if (send && endpoint > EP_CONTROL) {
 588         logf("usb: sent %d bytes", len);
 589     }
 590 */
 591     qh->status = 0;
 592     qh->length = 0;
 593     qh->wait   = wait;
 594
 595
 596     new_td=&td_array[pipe];
 597     prepare_td(new_td, 0, ptr, len,pipe);
 598     //logf("starting ep %d %s",endpoint,send?"send":"receive");
 599
 600     qh->dtd.next_td_ptr = (unsigned int)new_td;
 601     qh->dtd.size_ioc_sts &= ~(QH_STATUS_HALT | QH_STATUS_ACTIVE);
 602
 603     REG_ENDPTPRIME |= mask;
 604
 605     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 606         /* 32.14.3.2.2 */
 607         logf("new setup arrived");
 608         return -4;
 609     }
 610
 611     last_tick = current_tick;
 612     while ((REG_ENDPTPRIME & mask)) {
 613         if (REG_USBSTS & USBSTS_RESET)
 614             return -1;
 615
 616         if (TIME_AFTER(current_tick, last_tick + HZ/4)) {
 617             logf("prime timeout");
 618             return -2;
 619         }
 620     }
 621
 622     if (!(REG_ENDPTSTATUS & mask)) {
 623         logf("no prime! %d %d %x", endpoint, pipe, qh->dtd.size_ioc_sts & 0xff );
 624         return -3;
 625     }
 626     if(endpoint == EP_CONTROL && (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0)) {
 627         /* 32.14.3.2.2 */
 628         logf("new setup arrived");
 629         return -4;
 630     }
 631
 632     if (wait) {
 633         /* wait for transfer to finish */
 634         struct queue_event ev;
 635         queue_wait(&transfer_completion_queue[pipe], &ev);
 636         if(qh->status!=0) {
 637             return -5;
 638         }
 639         //logf("all tds done");
 640     }
 641     return 0;
 642 }
 643
 644 void usb_drv_cancel_all_transfers(void)
 645 {
 646     int i;
 647     REG_ENDPTFLUSH = ~0;
 648     while (REG_ENDPTFLUSH);
 649
 650     memset(td_array, 0, sizeof _td_array);
 651     for(i=0;i<NUM_ENDPOINTS*2;i++) {
 652         if(qh_array[i].wait) {
 653             qh_array[i].wait=0;
 654             qh_array[i].status=DTD_STATUS_HALTED;
 655             queue_post(&transfer_completion_queue[i],0, 0);
 656         }
 657     }
 658 }
 659
 660 static void prepare_td(struct transfer_descriptor* td,
 661                        struct transfer_descriptor* previous_td,
 662                        void *ptr, int len,int pipe)
 663 {
 664     //logf("adding a td : %d",len);
 665     memset(td, 0, sizeof(struct transfer_descriptor));
 666     td->next_td_ptr = DTD_NEXT_TERMINATE;
 667     td->size_ioc_sts = (len<< DTD_LENGTH_BIT_POS) |
 668         DTD_STATUS_ACTIVE | DTD_IOC;
 669     td->buff_ptr0 = (unsigned int)ptr;
 670     td->buff_ptr1 = ((unsigned int)ptr & 0xfffff000) + 0x1000;
 671     td->buff_ptr2 = ((unsigned int)ptr & 0xfffff000) + 0x2000;
 672     td->buff_ptr3 = ((unsigned int)ptr & 0xfffff000) + 0x3000;
 673     td->buff_ptr4 = ((unsigned int)ptr & 0xfffff000) + 0x4000;
 674     td->reserved |= DTD_RESERVED_LENGTH_MASK & len;
 675     td->reserved |= DTD_RESERVED_IN_USE;
 676     td->reserved |= (pipe << DTD_RESERVED_PIPE_OFFSET);
 677
 678     if (previous_td != 0) {
 679         previous_td->next_td_ptr=(unsigned int)td;
 680     }
 681 }
 682
 683 static void control_received(void)
 684 {
 685     int i;
 686     /* copy setup data from packet */
 687     static unsigned int tmp[2];
 688     tmp[0] = qh_array[0].setup_buffer[0];
 689     tmp[1] = qh_array[0].setup_buffer[1];
 690
 691     /* acknowledge packet recieved */
 692     REG_ENDPTSETUPSTAT |= EPSETUP_STATUS_EP0;
 693
 694     /* Stop pending control transfers */
 695     for(i=0;i<2;i++) {
 696         if(qh_array[i].wait) {
 697             qh_array[i].wait=0;
 698             qh_array[i].status=DTD_STATUS_HALTED;
 699             queue_post(&transfer_completion_queue[i],0, 0);
 700         }
 701     }
 702
 703     usb_core_control_request((struct usb_ctrlrequest*)tmp);
 704 }
 705
 706 static void transfer_completed(void)
 707 {
 708     int ep;
 709     unsigned int mask = REG_ENDPTCOMPLETE;
 710     REG_ENDPTCOMPLETE |= mask;
 711
 712     for (ep=0; ep<NUM_ENDPOINTS; ep++) {
 713         int dir;
 714         for (dir=0; dir<2; dir++) {
 715             int pipe = ep * 2 + dir;
 716             if (mask & pipe2mask[pipe]) {
 717                 struct queue_head* qh = &qh_array[pipe];
 718                 struct transfer_descriptor *td = &td_array[pipe];
 719
 720                 if(td->size_ioc_sts & DTD_STATUS_ACTIVE) {
 721                     /* TODO this shouldn't happen, but...*/
 722                     break;
 723                 }
 724                 if((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS != 0 && dir==0) {
 725                     /* We got less data than we asked for. */
 726                 }
 727                 qh->length = (td->reserved & DTD_RESERVED_LENGTH_MASK) -
 728                     ((td->size_ioc_sts & DTD_PACKET_SIZE) >> DTD_LENGTH_BIT_POS);
 729                 if(td->size_ioc_sts & DTD_ERROR_MASK) {
 730                     logf("pipe %d err %x", pipe, td->size_ioc_sts & DTD_ERROR_MASK);
 731                     qh->status |= td->size_ioc_sts & DTD_ERROR_MASK;
 732                     /* TODO we need to handle this somehow. Flush the endpoint ? */
 733                 }
 734                 if(qh->wait) {
 735                     qh->wait=0;
 736                     queue_post(&transfer_completion_queue[pipe],0, 0);
 737                 }
 738                 usb_core_transfer_complete(ep, dir, qh->status, qh->length);
 739             }
 740         }
 741     }
 742 }
 743
 744 /* manual: 32.14.2.1 Bus Reset */
 745 static void bus_reset(void)
 746 {
 747     int i;
 748     logf("usb bus_reset");
 749
 750     REG_DEVICEADDR = 0;
 751     REG_ENDPTSETUPSTAT = REG_ENDPTSETUPSTAT;
 752     REG_ENDPTCOMPLETE  = REG_ENDPTCOMPLETE;
 753
 754     for (i=0; i<100; i++) {
 755         if (!REG_ENDPTPRIME)
 756             break;
 757
 758         if (REG_USBSTS & USBSTS_RESET) {
 759             logf("usb: double reset");
 760             return;
 761         }
 762
 763         udelay(100);
 764     }
 765     if (REG_ENDPTPRIME) {
 766         logf("usb: short reset timeout");
 767     }
 768
 769     usb_drv_cancel_all_transfers();
 770
 771     if (!(REG_PORTSC1 & PORTSCX_PORT_RESET)) {
 772         logf("usb: slow reset!");
 773     }
 774 }
 775
 776 /* manual: 32.14.4.1 Queue Head Initialization */
 777 static void init_control_queue_heads(void)
 778 {
 779     int i;
 780     memset(qh_array, 0, sizeof _qh_array);
 781
 782     /*** control ***/
 783     qh_array[EP_CONTROL].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS | QH_IOS;
 784     qh_array[EP_CONTROL].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 785     qh_array[EP_CONTROL+1].max_pkt_length = 64 << QH_MAX_PKT_LEN_POS;
 786     qh_array[EP_CONTROL+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 787
 788     for(i=0;i<2;i++) {
 789         queue_init(&transfer_completion_queue[i], false);
 790     }
 791 }
 792 /* manual: 32.14.4.1 Queue Head Initialization */
 793 static void init_bulk_queue_heads(void)
 794 {
 795     int tx_packetsize;
 796     int rx_packetsize;
 797     int i;
 798
 799     if (usb_drv_port_speed()) {
 800         rx_packetsize = 512;
 801         tx_packetsize = 512;
 802     }
 803     else {
 804         rx_packetsize = 64;
 805         tx_packetsize = 64;
 806     }
 807
 808     /*** bulk ***/
 809     for(i=1;i<NUM_ENDPOINTS;i++) {
 810         qh_array[i*2].max_pkt_length = rx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 811         qh_array[i*2].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 812         qh_array[i*2+1].max_pkt_length = tx_packetsize << QH_MAX_PKT_LEN_POS | QH_ZLT_SEL;
 813         qh_array[i*2+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 814     }
 815     for(i=2;i<NUM_ENDPOINTS*2;i++) {
 816         queue_init(&transfer_completion_queue[i], false);
 817     }
 818 }
 819
 820 static void init_endpoints(void)
 821 {
 822     int i;
 823     /* bulk */
 824     for(i=1;i<NUM_ENDPOINTS;i++) {
 825         REG_ENDPTCTRL(i) =
 826             EPCTRL_RX_DATA_TOGGLE_RST | EPCTRL_RX_ENABLE |
 827             EPCTRL_TX_DATA_TOGGLE_RST | EPCTRL_TX_ENABLE |
 828             (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT) |
 829             (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT);
 830     }
 831 }