Multiprotocol/iface_a7105.h

   1 /*
   2  This project is free software: you can redistribute it and/or modify
   3  it under the terms of the GNU General Public License as published by
   4  the Free Software Foundation, either version 3 of the License, or
   5  (at your option) any later version.
   6
   7  Multiprotocol is distributed in the hope that it will be useful,
   8  but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  GNU General Public License for more details.
  11
  12  You should have received a copy of the GNU General Public License
  13  along with Multiprotocol.  If not, see <http://www.gnu.org/licenses/>.
  14  */
  15
  16 #ifndef _IFACE_A7105_H_
  17 #define _IFACE_A7105_H_
  18
  19 enum A7105_State {
  20     A7105_SLEEP     = 0x80,
  21     A7105_IDLE      = 0x90,
  22     A7105_STANDBY   = 0xA0,
  23     A7105_PLL       = 0xB0,
  24     A7105_RX        = 0xC0,
  25     A7105_TX        = 0xD0,
  26     A7105_RST_WRPTR = 0xE0,
  27     A7105_RST_RDPTR = 0xF0,
  28 };
  29
  30 enum {
  31     A7105_00_MODE         = 0x00,
  32     A7105_01_MODE_CONTROL = 0x01,
  33     A7105_02_CALC         = 0x02,
  34     A7105_03_FIFOI        = 0x03,
  35     A7105_04_FIFOII       = 0x04,
  36     A7105_05_FIFO_DATA    = 0x05,
  37     A7105_06_ID_DATA      = 0x06,
  38     A7105_07_RC_OSC_I     = 0x07,
  39     A7105_08_RC_OSC_II    = 0x08,
  40     A7105_09_RC_OSC_III   = 0x09,
  41     A7105_0A_CK0_PIN      = 0x0A,
  42     A7105_0B_GPIO1_PIN1   = 0x0B,
  43     A7105_0C_GPIO2_PIN_II = 0x0C,
  44     A7105_0D_CLOCK        = 0x0D,
  45     A7105_0E_DATA_RATE    = 0x0E,
  46     A7105_0F_PLL_I        = 0x0F,
  47     A7105_10_PLL_II       = 0x10,
  48     A7105_11_PLL_III      = 0x11,
  49     A7105_12_PLL_IV       = 0x12,
  50     A7105_13_PLL_V        = 0x13,
  51     A7105_14_TX_I         = 0x14,
  52     A7105_15_TX_II        = 0x15,
  53     A7105_16_DELAY_I      = 0x16,
  54     A7105_17_DELAY_II     = 0x17,
  55     A7105_18_RX           = 0x18,
  56     A7105_19_RX_GAIN_I    = 0x19,
  57     A7105_1A_RX_GAIN_II   = 0x1A,
  58     A7105_1B_RX_GAIN_III  = 0x1B,
  59     A7105_1C_RX_GAIN_IV   = 0x1C,
  60     A7105_1D_RSSI_THOLD   = 0x1D,
  61     A7105_1E_ADC          = 0x1E,
  62     A7105_1F_CODE_I       = 0x1F,
  63     A7105_20_CODE_II      = 0x20,
  64     A7105_21_CODE_III     = 0x21,
  65     A7105_22_IF_CALIB_I   = 0x22,
  66     A7105_23_IF_CALIB_II  = 0x23,
  67     A7105_24_VCO_CURCAL   = 0x24,
  68     A7105_25_VCO_SBCAL_I  = 0x25,
  69     A7105_26_VCO_SBCAL_II = 0x26,
  70     A7105_27_BATTERY_DET  = 0x27,
  71     A7105_28_TX_TEST      = 0x28,
  72     A7105_29_RX_DEM_TEST_I  = 0x29,
  73     A7105_2A_RX_DEM_TEST_II = 0x2A,
  74     A7105_2B_CPC          = 0x2B,
  75     A7105_2C_XTAL_TEST    = 0x2C,
  76     A7105_2D_PLL_TEST     = 0x2D,
  77     A7105_2E_VCO_TEST_I   = 0x2E,
  78     A7105_2F_VCO_TEST_II  = 0x2F,
  79     A7105_30_IFAT         = 0x30,
  80     A7105_31_RSCALE       = 0x31,
  81     A7105_32_FILTER_TEST  = 0x32,
  82 };
  83 #define A7105_0F_CHANNEL A7105_0F_PLL_I
  84
  85 enum A7105_MASK {
  86     A7105_MASK_FBCF = 1 << 4,
  87     A7105_MASK_VBCF = 1 << 3,
  88 };
  89
  90 #endif