Multiprotocol/CYRF6936_SPI.ino

   1 /*
   2  This project is free software: you can redistribute it and/or modify
   3  it under the terms of the GNU General Public License as published by
   4  the Free Software Foundation, either version 3 of the License, or
   5  (at your option) any later version.
   6
   7  Multiprotocol is distributed in the hope that it will be useful,
   8  but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  GNU General Public License for more details.
  11
  12  You should have received a copy of the GNU General Public License
  13  along with Multiprotocol.  If not, see <http://www.gnu.org/licenses/>.
  14  */
  15 #ifdef CYRF6936_INSTALLED
  16 #include "iface_cyrf6936.h"
  17
  18 void CYRF_WriteRegister(uint8_t address, uint8_t data)
  19 {
  20         CYRF_CSN_off;
  21         SPI_Write(0x80 | address);
  22         SPI_Write(data);
  23         CYRF_CSN_on;
  24 }
  25
  26 static void CYRF_WriteRegisterMulti(uint8_t address, const uint8_t data[], uint8_t length)
  27 {
  28         uint8_t i;
  29
  30         CYRF_CSN_off;
  31         SPI_Write(0x80 | address);
  32         for(i = 0; i < length; i++)
  33                 SPI_Write(data[i]);
  34         CYRF_CSN_on;
  35 }
  36
  37 static void CYRF_ReadRegisterMulti(uint8_t address, uint8_t data[], uint8_t length)
  38 {
  39         uint8_t i;
  40
  41         CYRF_CSN_off;
  42         SPI_Write(address);
  43         for(i = 0; i < length; i++)
  44                 data[i] = SPI_Read();
  45         CYRF_CSN_on;
  46 }
  47
  48 uint8_t CYRF_ReadRegister(uint8_t address)
  49 {
  50         uint8_t data;
  51         CYRF_CSN_off;
  52         SPI_Write(address);
  53         data = SPI_Read();
  54         CYRF_CSN_on;
  55         return data;
  56 }
  57 //
  58
  59 uint8_t CYRF_Reset()
  60 {
  61 #ifdef CYRF_RST_HI
  62         CYRF_RST_HI;                                                                            //Hardware reset
  63         delayMicroseconds(100);
  64         CYRF_RST_LO;
  65         delayMicroseconds(100);
  66 #endif
  67         CYRF_WriteRegister(CYRF_1D_MODE_OVERRIDE, 0x01);        //Software reset
  68         delayMicroseconds(200);
  69         CYRF_WriteRegister(CYRF_0C_XTAL_CTRL, 0xC0);            //Enable XOUT as GPIO
  70         CYRF_WriteRegister(CYRF_0D_IO_CFG, 0x04);                       //Enable PACTL as GPIO
  71         CYRF_SetTxRxMode(TXRX_OFF);
  72         //Verify the CYRF chip is responding
  73         return (CYRF_ReadRegister(CYRF_10_FRAMING_CFG) == 0xa5);
  74 }
  75
  76 /*
  77 *
  78 */
  79 void CYRF_GetMfgData(uint8_t data[])
  80 {
  81 #ifndef FORCE_CYRF_ID
  82         if(eeprom_read_byte((EE_ADDR)EEPROM_CID_INIT_OFFSET)==0xf0)
  83         {//read Cyrf ID from EEPROM
  84                 for(uint8_t i=0;i<6;i++)
  85                         data[i] = eeprom_read_byte((EE_ADDR)EEPROM_CID_OFFSET+i);
  86         }
  87         else
  88         {//read Cyrf ID and store it EEPROM
  89                 /* Fuses power on */
  90                 CYRF_WriteRegister(CYRF_25_MFG_ID, 0xFF);
  91
  92                 CYRF_ReadRegisterMulti(CYRF_25_MFG_ID, data, 6);
  93                 for(uint8_t i=0;i<6;i++)
  94                         eeprom_write_byte((EE_ADDR)EEPROM_CID_OFFSET+i, data[i]);
  95                 eeprom_write_byte((EE_ADDR)EEPROM_CID_INIT_OFFSET, 0xf0);
  96
  97                 /* Fuses power off */
  98                 CYRF_WriteRegister(CYRF_25_MFG_ID, 0x00);
  99         }
 100 #else
 101         memcpy(data,FORCE_CYRF_ID,6);
 102 #endif
 103 }
 104
 105 /*
 106 * 1 - Tx else Rx
 107 */
 108 void CYRF_SetTxRxMode(uint8_t mode)
 109 {
 110         if(mode==TXRX_OFF)
 111         {
 112                 if( protocol!=PROTO_WFLY && protocol!=PROTO_MLINK )
 113                         CYRF_WriteRegister(CYRF_0F_XACT_CFG, 0x24); // 4=IDLE, 8=TX, C=RX
 114                 CYRF_WriteRegister(CYRF_0E_GPIO_CTRL,0x00); // XOUT=0 PACTL=0
 115         }
 116         else
 117         {
 118                 //Set the post tx/rx state
 119                 if( protocol!=PROTO_WFLY && protocol!=PROTO_MLINK )
 120                         CYRF_WriteRegister(CYRF_0F_XACT_CFG, mode == TX_EN ? 0x28 : 0x2C); // 4=IDLE, 8=TX, C=RX
 121                 if(mode == TX_EN)
 122 #ifdef ORANGE_TX_BLUE
 123                         CYRF_WriteRegister(CYRF_0E_GPIO_CTRL,0x20); // XOUT=1, PACTL=0
 124                 else
 125                         CYRF_WriteRegister(CYRF_0E_GPIO_CTRL,0x80);     // XOUT=0, PACTL=1
 126 #else
 127                         CYRF_WriteRegister(CYRF_0E_GPIO_CTRL,0x80); // XOUT=1, PACTL=0
 128                 else
 129                         CYRF_WriteRegister(CYRF_0E_GPIO_CTRL,0x20);     // XOUT=0, PACTL=1
 130 #endif
 131         }
 132 }
 133 /*
 134 *
 135 */
 136 void CYRF_ConfigRFChannel(uint8_t ch)
 137 {
 138         CYRF_WriteRegister(CYRF_00_CHANNEL,ch);
 139 }
 140
 141 /*
 142 static void CYRF_SetPower_Value(uint8_t power)
 143 {
 144         uint8_t val = CYRF_ReadRegister(CYRF_03_TX_CFG) & 0xF8;
 145         CYRF_WriteRegister(CYRF_03_TX_CFG, val | (power & 0x07));
 146 }
 147 */
 148
 149 void CYRF_SetPower(uint8_t val)
 150 {
 151         uint8_t power=CYRF_BIND_POWER;
 152         if(IS_BIND_DONE)
 153                 #ifdef CYRF6936_ENABLE_LOW_POWER
 154                         power=IS_POWER_FLAG_on?CYRF_HIGH_POWER:CYRF_LOW_POWER;
 155                 #else
 156                         power=CYRF_HIGH_POWER;
 157                 #endif
 158         if(IS_RANGE_FLAG_on)
 159                 power=CYRF_RANGE_POWER;
 160         power|=val;
 161         if(prev_power != power)
 162         {
 163                 CYRF_WriteRegister(CYRF_03_TX_CFG,power);
 164                 prev_power=power;
 165         }
 166
 167         #ifdef USE_CYRF6936_CH15_TUNING
 168                 static uint16_t Channel15=1024;
 169                 if(Channel15!=Channel_data[CH15])
 170                 { // adjust frequency
 171                         Channel15=Channel_data[CH15]+0x155;     // default value is 0x555 = 0x400 + 0x155
 172                         CYRF_WriteRegister(CYRF_1B_TX_OFFSET_LSB, Channel15&0xFF);
 173                         CYRF_WriteRegister(CYRF_1C_TX_OFFSET_MSB, Channel15>>8);
 174                         Channel15-=0x155;
 175                 }
 176         #endif
 177 }
 178
 179 /*
 180 *
 181 */
 182 void CYRF_ConfigCRCSeed(uint16_t crc_seed)
 183 {
 184         CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB,crc_seed & 0xff);
 185         CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB,crc_seed >> 8);
 186 }
 187 /*
 188 * these are the recommended sop codes from Cyrpress
 189 * See "WirelessUSB LP/LPstar and PRoC LP/LPstar Technical Reference Manual"
 190 */
 191 void CYRF_ConfigSOPCode(const uint8_t *sopcodes)
 192 {
 193         //NOTE: This can also be implemented as:
 194         //for(i = 0; i < 8; i++) WriteRegister)0x23, sopcodes[i];
 195         CYRF_WriteRegisterMulti(CYRF_22_SOP_CODE, sopcodes, 8);
 196 }
 197
 198 void CYRF_ConfigDataCode(const uint8_t *datacodes)
 199 {
 200         //NOTE: This can also be implemented as:
 201         //for(i = 0; i < 16; i++) WriteRegister)0x23, datacodes[i];
 202         CYRF_WriteRegisterMulti(CYRF_23_DATA_CODE, datacodes, 16);
 203 }
 204
 205 void CYRF_WritePreamble(uint32_t preamble)
 206 {
 207         CYRF_CSN_off;
 208         SPI_Write(0x80 | 0x24);
 209         SPI_Write(preamble & 0xff);
 210         SPI_Write((preamble >> 8) & 0xff);
 211         SPI_Write((preamble >> 16) & 0xff);
 212         CYRF_CSN_on;
 213 }
 214 /*
 215 *
 216 */
 217 /*static void CYRF_ReadDataPacket(uint8_t dpbuffer[])
 218 {
 219         CYRF_ReadRegisterMulti(CYRF_21_RX_BUFFER, dpbuffer, 0x10);
 220 }
 221 */
 222 void CYRF_ReadDataPacketLen(uint8_t dpbuffer[], uint8_t length)
 223 {
 224     CYRF_ReadRegisterMulti(CYRF_21_RX_BUFFER, dpbuffer, length);
 225 }
 226
 227 static void CYRF_WriteDataPacketLen(const uint8_t dpbuffer[], uint8_t len)
 228 {
 229         CYRF_WriteRegister(CYRF_01_TX_LENGTH, len);
 230         CYRF_WriteRegister(CYRF_02_TX_CTRL, 0x43);      // 0x40
 231         CYRF_WriteRegisterMulti(CYRF_20_TX_BUFFER, dpbuffer, len);
 232         CYRF_WriteRegister(CYRF_02_TX_CTRL, 0x83);      // 0xBF
 233 }
 234
 235 void CYRF_WriteDataPacket(const uint8_t dpbuffer[])
 236 {
 237         CYRF_WriteDataPacketLen(dpbuffer, 16);
 238 }
 239
 240 /*static uint8_t CYRF_ReadRSSI(uint8_t dodummyread)
 241 {
 242         uint8_t result;
 243         if(dodummyread)
 244                 CYRF_ReadRegister(CYRF_13_RSSI);
 245         result = CYRF_ReadRegister(CYRF_13_RSSI);
 246         if(result & 0x80)
 247                 result = CYRF_ReadRegister(CYRF_13_RSSI);
 248         return (result & 0x0F);
 249 }
 250 */
 251 //NOTE: This routine will reset the CRC Seed
 252 void CYRF_FindBestChannels(uint8_t *channels, uint8_t len, uint8_t minspace, uint8_t min, uint8_t max, uint8_t forced)
 253 {
 254         #define NUM_FREQ 80
 255         #define FREQ_OFFSET 4
 256         uint8_t rssi[NUM_FREQ];
 257
 258         if (min < FREQ_OFFSET)
 259                 min = FREQ_OFFSET;
 260         if (max > NUM_FREQ)
 261                 max = NUM_FREQ;
 262
 263         uint8_t i;
 264         int8_t j;
 265         memset(channels, 0, sizeof(uint8_t) * len);
 266         CYRF_ConfigCRCSeed(0x0000);
 267         CYRF_SetTxRxMode(RX_EN);
 268         //Wait for pre-amp to switch from send to receive
 269         delayMilliseconds(1);
 270         for(i = 0; i < NUM_FREQ; i++)
 271         {
 272                 if(((i&1) && forced == FIND_CHANNEL_EVEN) || (!(i&1) && forced == FIND_CHANNEL_ODD))
 273                 {
 274                         rssi[i] = 0xFF;
 275                         continue;
 276                 }
 277                 CYRF_ConfigRFChannel(i);        //protocol==PROTO_LOSI?i|1:i);
 278                 delayMicroseconds(270);                                 //slow channel require 270usec for synthesizer to settle
 279         if( !(CYRF_ReadRegister(CYRF_05_RX_CTRL) & 0x80)) {
 280             CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x80); //Prepare to receive
 281             delayMicroseconds(15);
 282             CYRF_ReadRegister(CYRF_13_RSSI);    //dummy read
 283             delayMicroseconds(15);                              //The conversion can occur as often as once every 12us
 284         }
 285                 rssi[i] = CYRF_ReadRegister(CYRF_13_RSSI)&0x1F;
 286         }
 287
 288         for (i = 0; i < len; i++)
 289         {
 290                 channels[i] = min;
 291                 for (j = min; j < max; j++)
 292                         if (rssi[j] < rssi[channels[i]])
 293                                 channels[i] = j;
 294                 for (j = channels[i] - minspace; j < channels[i] + minspace; j++) {
 295                         //Ensure we don't reuse any channels within minspace of the selected channel again
 296                         if (j < 0 || j >= NUM_FREQ)
 297                                 continue;
 298                         rssi[j] = 0xff;
 299                 }
 300         }
 301         CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20);             // Abort RX operation
 302         CYRF_SetTxRxMode(TX_EN);
 303         CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00);             // Clear abort RX
 304 }
 305
 306 #if defined(DEVO_CYRF6936_INO) || defined(J6PRO_CYRF6936_INO) || defined(TRAXXAS_CYRF6936_INO)
 307 const uint8_t PROGMEM DEVO_j6pro_sopcodes[][8] = {
 308     /* Note these are in order transmitted (LSB 1st) */
 309     {0x3C, 0x37, 0xCC, 0x91, 0xE2, 0xF8, 0xCC, 0x91},
 310     {0x9B, 0xC5, 0xA1, 0x0F, 0xAD, 0x39, 0xA2, 0x0F},
 311     {0xEF, 0x64, 0xB0, 0x2A, 0xD2, 0x8F, 0xB1, 0x2A},
 312     {0x66, 0xCD, 0x7C, 0x50, 0xDD, 0x26, 0x7C, 0x50},
 313     {0x5C, 0xE1, 0xF6, 0x44, 0xAD, 0x16, 0xF6, 0x44},
 314     {0x5A, 0xCC, 0xAE, 0x46, 0xB6, 0x31, 0xAE, 0x46},
 315     {0xA1, 0x78, 0xDC, 0x3C, 0x9E, 0x82, 0xDC, 0x3C},
 316     {0xB9, 0x8E, 0x19, 0x74, 0x6F, 0x65, 0x18, 0x74},
 317     {0xDF, 0xB1, 0xC0, 0x49, 0x62, 0xDF, 0xC1, 0x49},
 318     {0x97, 0xE5, 0x14, 0x72, 0x7F, 0x1A, 0x14, 0x72},
 319 #if defined(J6PRO_CYRF6936_INO) || defined(TRAXXAS_CYRF6936_INO)
 320     {0x82, 0xC7, 0x90, 0x36, 0x21, 0x03, 0xFF, 0x17},
 321     {0xE2, 0xF8, 0xCC, 0x91, 0x3C, 0x37, 0xCC, 0x91}, //Note: the '03' was '9E' in the Cypress recommended table
 322     {0xAD, 0x39, 0xA2, 0x0F, 0x9B, 0xC5, 0xA1, 0x0F}, //The following are the same as the 1st 8 above,
 323     {0xD2, 0x8F, 0xB1, 0x2A, 0xEF, 0x64, 0xB0, 0x2A}, //but with the upper and lower word swapped
 324     {0xDD, 0x26, 0x7C, 0x50, 0x66, 0xCD, 0x7C, 0x50},
 325     {0xAD, 0x16, 0xF6, 0x44, 0x5C, 0xE1, 0xF6, 0x44},
 326     {0xB6, 0x31, 0xAE, 0x46, 0x5A, 0xCC, 0xAE, 0x46},
 327     {0x9E, 0x82, 0xDC, 0x3C, 0xA1, 0x78, 0xDC, 0x3C},
 328     {0x6F, 0x65, 0x18, 0x74, 0xB9, 0x8E, 0x19, 0x74},
 329     {0x62, 0xDF, 0xC1, 0x49, 0xDF, 0xB1, 0xC0, 0x49}, //j6pro bind
 330 #endif
 331 };
 332 #endif
 333
 334 static void __attribute__((unused)) CYRF_PROGMEM_ConfigSOPCode(const uint8_t *data)
 335 {
 336         uint8_t code[8];
 337         //debug("SOP:");
 338         for(uint8_t i=0;i<8;i++)
 339         {
 340                 code[i]=pgm_read_byte_near(&data[i]);
 341                 //debug(" %02X",code[i]);
 342         }
 343         //debugln("");
 344         CYRF_ConfigSOPCode(code);
 345 }
 346
 347 //CYRF GFSK 1Mb functions
 348 const uint8_t PROGMEM CYRF_GFSK1M_init_vals[][2] = {
 349         {CYRF_02_TX_CTRL, 0x00},                // transmit err & complete interrupts disabled
 350         {CYRF_05_RX_CTRL, 0x00},                // receive err & complete interrupts disabled
 351         {CYRF_28_CLK_EN, 0x02},                 // Force Receive Clock Enable, MUST be set
 352         {CYRF_32_AUTO_CAL_TIME, 0x3c},  // must be set to 3C
 353         {CYRF_35_AUTOCAL_OFFSET, 0x14}, // must be  set to 14
 354         {CYRF_06_RX_CFG, 0x48},                 // LNA manual control, Rx Fast Turn Mode Enable
 355         {CYRF_1B_TX_OFFSET_LSB, 0x00},  // Tx frequency offset LSB
 356         {CYRF_1C_TX_OFFSET_MSB, 0x00},  // Tx frequency offset MSB
 357         {CYRF_0F_XACT_CFG, 0x24},               // Force End State, transaction end state = idle
 358         {CYRF_03_TX_CFG, 0x00},                 // GFSK mode
 359         {CYRF_12_DATA64_THOLD, 0x0a},   // 64 Chip Data PN Code Correlator Threshold = 10
 360         {CYRF_0F_XACT_CFG, 0x04},               // Transaction End State = idle
 361         {CYRF_39_ANALOG_CTRL, 0x01},    // synth setting time for all channels is the same as for slow channels
 362         {CYRF_0F_XACT_CFG, 0x24},               //Force IDLE
 363         {CYRF_29_RX_ABORT, 0x00},               //Clear RX abort
 364         {CYRF_12_DATA64_THOLD, 0x0a},   //set pn correlation threshold
 365         {CYRF_10_FRAMING_CFG, 0x4a},    //set sop len and threshold
 366         {CYRF_29_RX_ABORT, 0x0f},               //Clear RX abort?
 367         {CYRF_03_TX_CFG, 0x00},                 // GFSK mode
 368         {CYRF_10_FRAMING_CFG, 0x4a},    // 0b11000000 //set sop len and threshold
 369         {CYRF_1F_TX_OVERRIDE, 0x04},    //disable tx CRC
 370         {CYRF_1E_RX_OVERRIDE, 0x14},    //disable rx crc
 371         {CYRF_14_EOP_CTRL, 0x00},               //set EOP sync == 0
 372 };
 373 static void __attribute__((unused)) CYRF_GFSK1M_Init(uint8_t payload_length, uint8_t preamble_len)
 374 {
 375         for(uint8_t i = 0; i < sizeof(CYRF_GFSK1M_init_vals) / 2; i++)
 376                 CYRF_WriteRegister(pgm_read_byte_near(&CYRF_GFSK1M_init_vals[i][0]), pgm_read_byte_near(&CYRF_GFSK1M_init_vals[i][1]));
 377
 378
 379         CYRF_WriteRegister(CYRF_01_TX_LENGTH, payload_length);
 380
 381         CYRF_WritePreamble(0xAAAA00 | preamble_len);
 382
 383         CYRF_SetPower(0x00);
 384
 385         CYRF_SetTxRxMode(TX_EN);
 386 }
 387 static void __attribute__((unused)) CYRF_GFSK1M_SendPayload(uint8_t *buffer, uint8_t len)
 388 {
 389         uint8_t send=len>16 ? 16 : len;
 390         CYRF_WriteRegister(CYRF_02_TX_CTRL, 0x40);
 391         CYRF_WriteRegisterMulti(CYRF_20_TX_BUFFER, buffer, send);                       // Fill the buffer with 16 bytes max
 392         CYRF_WriteRegister(CYRF_02_TX_CTRL, 0x80);                                                      // Start send
 393         buffer += send;
 394         len -= send;
 395
 396         while(len>8)
 397         {
 398                 while((CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS)&0x10) == 0);    // Wait that half of the buffer is empty
 399                 CYRF_WriteRegisterMulti(CYRF_20_TX_BUFFER, buffer, 8);                  // Add 8 bytes to the buffer
 400                 buffer+=8;
 401                 len-=8;
 402         }
 403
 404         if(len)
 405         {
 406                 while((CYRF_ReadRegister(CYRF_04_TX_IRQ_STATUS)&0x10) == 0);    // Wait that half of the buffer is empty
 407                 CYRF_WriteRegisterMulti(CYRF_20_TX_BUFFER, buffer, len);                // Add the remaining bytes to the buffer
 408         }
 409 }
 410 #define CYRF_GFSK1M_SetPower() CYRF_SetPower(0x00)
 411 #endif