External Wishbone bus and serial input/output registers
[AtosmChip.git] / clock.v
blob849b95667144b9d7d75af1b52631e023883cbc20
1 // Atosm Chip
2 // Copyright (C) 2008 Tomasz Malesinski <tmal@mimuw.edu.pl>
3 //
4 // This program is free software; you can redistribute it and/or modify
5 // it under the terms of the GNU General Public License as published by
6 // the Free Software Foundation; either version 2 of the License, or
7 // (at your option) any later version.
8 //
9 // This program is distributed in the hope that it will be useful,
10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 // GNU General Public License for more details.
14 // You should have received a copy of the GNU General Public License
15 // along with this program; if not, write to the Free Software
16 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 module clkgen(clk_o, clk2_o);
19 output clk_o;
20 output clk2_o;
22 reg clk_o;
23 reg clk2_o;
25 initial begin
26 clk_o = 0;
27 clk2_o = 0;
28 end
30 always begin
31 #5 clk2_o = ~clk2_o;
32 #5 clk2_o = ~clk2_o;
33 clk_o = ~clk_o;
34 end
35 endmodule