Top level Atosm chip and its initial firmware
[AtosmChip.git] / antic.v
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1 // Atosm Chip
2 // Copyright (C) 2008 Tomasz Malesinski <tmal@mimuw.edu.pl>
3 //
4 // This program is free software; you can redistribute it and/or modify
5 // it under the terms of the GNU General Public License as published by
6 // the Free Software Foundation; either version 2 of the License, or
7 // (at your option) any later version.
8 //
9 // This program is distributed in the hope that it will be useful,
10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 // GNU General Public License for more details.
14 // You should have received a copy of the GNU General Public License
15 // along with this program; if not, write to the Free Software
16 // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 module antic_ms_hcount_seq(clk_i, ms_hcount,
19 new_block, dma_block, char_block, dma_pf_width, ir,
20 shift_reg_shift, load_pf, load_char, load_out,
21 out_reg_shift);
22 input clk_i, ms_hcount;
23 input new_block, dma_block, char_block, dma_pf_width, ir;
24 output shift_reg_shift, load_pf, load_char, load_out, out_reg_shift;
26 wire clk_i;
27 wire [7:0] ms_hcount;
28 wire new_block, dma_block, char_block;
29 wire [1:0] dma_pf_width;
30 wire [7:0] ir;
31 wire shift_reg_shift;
32 reg load_pf, load_char;
33 wire load_out;
34 wire out_reg_shift;
36 reg load_pf_0, load_char_0;
37 reg [3:0] pf_byte_mod;
38 reg [1:0] pf_pixel_mod;
40 integer pf_cyc;
42 always @ (ir)
43 case (ir[3:0])
44 'h2: begin
45 pf_byte_mod = 3;
46 pf_pixel_mod = 0;
47 end
48 'h3: begin
49 pf_byte_mod = 3;
50 pf_pixel_mod = 0;
51 end
52 'h4: begin
53 pf_byte_mod = 3;
54 pf_pixel_mod = 0;
55 end
56 'h5: begin
57 pf_byte_mod = 3;
58 pf_pixel_mod = 0;
59 end
60 'h6: begin
61 pf_byte_mod = 7;
62 pf_pixel_mod = 0;
63 end
64 'h7: begin
65 pf_byte_mod = 7;
66 pf_pixel_mod = 0;
67 end
68 'h8: begin
69 pf_byte_mod = 15;
70 pf_pixel_mod = 3;
71 end
72 'h9: begin
73 pf_byte_mod = 15;
74 pf_pixel_mod = 1;
75 end
76 'ha: begin
77 pf_byte_mod = 7;
78 pf_pixel_mod = 1;
79 end
80 'hb: begin
81 pf_byte_mod = 7;
82 pf_pixel_mod = 0;
83 end
84 'hc: begin
85 pf_byte_mod = 7;
86 pf_pixel_mod = 0;
87 end
88 'hd: begin
89 pf_byte_mod = 3;
90 pf_pixel_mod = 0;
91 end
92 'he: begin
93 pf_byte_mod = 3;
94 pf_pixel_mod = 0;
95 end
96 'hf: begin
97 pf_byte_mod = 3;
98 pf_pixel_mod = 0;
99 end
100 default: begin
101 pf_byte_mod = 3;
102 pf_pixel_mod = 0;
104 endcase
106 assign shift_reg_shift = (ms_hcount >= 3) && (ms_hcount < 192 + 3) &&
107 (ms_hcount[1:0] == 3);
109 assign out_reg_shift = ((ms_hcount[1:0] & pf_pixel_mod) ==
110 (2'd2 & pf_pixel_mod));
112 always @ (new_block or dma_block or dma_pf_width or ms_hcount or
113 pf_byte_mod or ir) begin
114 pf_cyc = char_block ? 3 : 7;
115 load_pf_0 = 0;
116 if (new_block && dma_block) begin
117 if (dma_pf_width == 1 && !ir[4])
118 load_pf_0 = ((ms_hcount & pf_byte_mod) == (pf_cyc & pf_byte_mod)) &&
119 (ms_hcount >= 32 + pf_cyc) &&
120 (ms_hcount < 160 + pf_cyc);
121 else if (dma_pf_width == (ir[4] ? 1 : 2))
122 load_pf_0 = ((ms_hcount & pf_byte_mod) == (pf_cyc & pf_byte_mod)) &&
123 (ms_hcount >= 16 + pf_cyc) &&
124 (ms_hcount < 176 + pf_cyc);
125 else if (dma_pf_width == 3 || (ir[4] && dma_pf_width == 2))
126 load_pf_0 = ((ms_hcount & pf_byte_mod) == (pf_cyc & pf_byte_mod)) &&
127 (ms_hcount >= pf_cyc) && (ms_hcount < 192 + pf_cyc);
131 always @ (char_block or dma_block or dma_pf_width or ms_hcount or
132 pf_byte_mod) begin
133 load_char_0 = 0;
134 if (char_block && dma_block) begin
135 if (dma_pf_width == 1 && !ir[4])
136 load_char_0 = ((ms_hcount & pf_byte_mod) == (9 & pf_byte_mod)) &&
137 (ms_hcount >= 32 + 9 && ms_hcount < 160 + 9);
138 else if (dma_pf_width == (ir[4] ? 1 : 2))
139 load_char_0 = ((ms_hcount & pf_byte_mod) == (9 & pf_byte_mod)) &&
140 (ms_hcount >= 16 + 9 && ms_hcount < 176 + 9);
141 else if (dma_pf_width == 3 || (ir[4] && dma_pf_width == 2))
142 load_char_0 = ((ms_hcount & pf_byte_mod) == (9 & pf_byte_mod)) &&
143 (ms_hcount >= 9 && ms_hcount < 192 + 9);
147 assign load_out = ((ms_hcount[3:0] & pf_byte_mod) == (4'd14 & pf_byte_mod));
149 always @ (posedge clk_i) begin
150 load_pf <= load_pf_0;
151 load_char <= load_char_0;
153 endmodule
155 module antic_shift_reg(clk_i, shift, load, in, out);
156 input clk_i;
157 input shift;
158 input load;
159 input in;
161 output out;
163 wire clk_i;
164 wire shift;
165 wire load;
166 wire [7:0] in;
167 wire [7:0] out;
169 reg [7:0] shift_reg [0:47];
171 integer i;
173 assign out = shift_reg[1];
175 always @ (posedge clk_i) begin
176 if (shift)
177 for (i = 0; i < 47; i = i + 1)
178 shift_reg[i + 1] <= shift_reg[i];
179 if (load)
180 shift_reg[0] <= in;
181 else if (shift)
182 shift_reg[0] <= shift_reg[47];
184 endmodule
186 module antic(rst_i, clk_i,
187 adr_i, adr_o,
188 slavedat_i, masterdat_i,
189 dat_o,
190 we_i,
191 stb_i, stb_o,
192 ack_i, ack_o,
193 cyc_o,
194 clk2_i,
195 nmi,
196 antic_out);
197 input rst_i;
198 input clk_i;
199 input adr_i;
200 input slavedat_i;
201 input masterdat_i;
202 input we_i;
203 input stb_i;
204 input ack_i;
205 input clk2_i;
207 output adr_o;
208 output dat_o;
209 output stb_o;
210 output ack_o;
211 output cyc_o;
212 output nmi;
213 output antic_out;
215 wire rst_i, clk_i;
216 wire [3:0] adr_i;
217 wire [7:0] slavedat_i;
218 wire [7:0] masterdat_i;
219 wire we_i;
220 wire stb_i;
221 wire ack_i;
222 wire clk2_i;
224 reg [15:0] adr_o;
225 reg [7:0] dat_o;
226 wire stb_o;
227 wire ack_o;
228 wire cyc_o;
229 wire nmi;
230 reg [2:0] pf_antic_out, pf_antic_out_d;
231 reg [2:0] antic_out;
233 reg [1:0] dma_pf_width;
234 reg dma_mis_en;
235 reg dma_ply_en;
236 reg dma_pm_1res;
237 reg dma_instr_en;
239 reg [6:0] chbase;
240 reg [2:0] chactl;
241 reg [5:0] pmbase;
242 reg [3:0] hscrol;
243 reg [3:0] vscrol;
245 wire nmireq_dli, nmireq_vbi;
246 reg nmist_dli, nmist_vbi;
247 reg nmien_dli, nmien_vbi;
249 reg [15:0] dlist_ctr;
250 reg [7:0] dlist_ctr_tmp;
251 wire dl_load;
253 reg [15:0] memscan_ctr;
255 reg [7:0] hcount;
256 reg [8:0] vcount;
257 reg [3:0] dcount;
258 wire [3:0] chr_dcount;
259 reg [7:0] ms_hcount;
261 reg [7:0] ir;
262 reg new_block;
263 reg [3:0] maxline;
264 wire dli;
265 wire wait_vblank;
266 wire dma_block;
267 reg char_block;
268 reg one_bit_pixel;
269 wire vscrol_en;
270 reg last_vscrol_en;
272 reg wsync;
274 wire load_instr;
275 wire load_dlptrl;
276 wire load_dlptrh;
277 wire load_memscanl;
278 wire load_memscanh;
279 wire load_mis;
280 wire load_ply;
281 wire load_pf;
282 wire load_char;
284 reg refresh_req;
285 reg refresh_ack;
287 wire [1:0] dma_ply_num;
289 wire load_out_p, load_out;
291 wire hblank, vblank, vsync;
292 reg dwin;
294 wire shift_reg_shift;
295 wire [7:0] shift_reg_out;
296 wire char_blank;
297 reg [7:0] char_data, out_reg;
298 wire out_reg_shift;
299 reg [1:0] char_color_p, char_color;
301 assign ack_o = stb_i;
303 // Read registers.
304 always @ (adr_i or vcount or nmist_dli or nmist_vbi)
305 case (adr_i)
306 'hb:
307 dat_o = vcount[8:1];
308 'hf:
309 dat_o = {nmist_dli, nmist_vbi, 6'b0};
310 default:
311 dat_o = 'hff;
312 endcase
314 // DMACTL
315 always @ (posedge clk_i)
316 if (stb_i && we_i && adr_i == 'h0) begin
317 dma_pf_width <= slavedat_i[1:0];
318 dma_mis_en <= slavedat_i[2];
319 dma_ply_en <= slavedat_i[3];
320 dma_pm_1res <= slavedat_i[4];
321 dma_instr_en <= slavedat_i[5];
324 // CHACTL
325 always @ (posedge clk_i)
326 if (stb_i && we_i && adr_i == 'h1)
327 chactl <= slavedat_i[2:0];
329 // DLISTL/H
330 always @ (posedge clk_i)
331 if (stb_i && we_i && adr_i == 'h2)
332 dlist_ctr[7:0] <= slavedat_i;
333 else if (stb_i && we_i && adr_i == 'h3)
334 dlist_ctr[15:8] <= slavedat_i;
335 else if (dl_load) begin
336 if (!load_dlptrh)
337 dlist_ctr[9:0] <= dlist_ctr[9:0] + 1;
338 else begin
339 dlist_ctr[15:8] <= masterdat_i;
340 dlist_ctr[7:0] <= dlist_ctr_tmp;
342 if (load_dlptrl)
343 dlist_ctr_tmp <= masterdat_i;
346 // HSCROL
347 always @ (posedge clk_i)
348 if (stb_i && we_i && adr_i == 'h4)
349 hscrol <= slavedat_i[3:0];
351 // VSCROL
352 always @ (posedge clk_i)
353 if (stb_i && we_i && adr_i == 'h5)
354 vscrol <= slavedat_i[3:0];
356 // PMBASE
357 always @ (posedge clk_i)
358 if (stb_i && we_i && adr_i == 'h7)
359 pmbase <= slavedat_i[7:2];
361 // CHBASE
362 always @ (posedge clk_i)
363 if (stb_i && we_i && adr_i == 'h9)
364 chbase <= slavedat_i[7:1];
366 // WSYNC
367 always @ (posedge clk_i)
368 if (rst_i || hcount == 206)
369 wsync <= 0;
370 else if (stb_i && we_i && adr_i == 'ha)
371 wsync <= 1;
373 // NMIEN
374 always @ (posedge clk_i)
375 if (rst_i) begin
376 nmien_vbi <= 0;
377 nmien_dli <= 0;
378 end else if (stb_i && we_i && adr_i == 'he) begin
379 nmien_vbi <= slavedat_i[6];
380 nmien_dli <= slavedat_i[7];
383 // HCOUNT
384 always @ (posedge clk2_i)
385 if (rst_i && !clk_i)
386 hcount <= 0;
387 else if (hcount == 227)
388 hcount <= 0;
389 else
390 hcount <= hcount + 1;
392 // VCOUNT
393 always @ (posedge clk2_i)
394 if (rst_i && !clk_i)
395 vcount <= 0;
396 else if (hcount == 227)
397 if (vcount == 311)
398 vcount <= 0;
399 else
400 vcount <= vcount + 1;
402 // Display list interrupt.
403 assign nmireq_dli = (hcount == 16 && dcount == maxline && dli &&
404 nmien_dli && !vblank && !wait_vblank);
406 // Vertical blank interrupt.
407 assign nmireq_vbi = (hcount == 16 && vcount == 240 && nmien_vbi);
409 always @ (posedge clk_i)
410 if (rst_i) begin
411 nmist_vbi <= 0;
412 nmist_dli <= 0;
413 end else if (nmireq_vbi) begin
414 nmist_vbi <= 1;
415 nmist_dli <= 0;
416 end else if (nmireq_dli) begin
417 nmist_vbi <= 0;
418 nmist_dli <= 1;
419 end else if (stb_i && we_i && adr_i =='hf) begin
420 nmist_vbi <= 0;
421 nmist_dli <= 0;
424 assign nmi = nmireq_dli | nmireq_vbi;
426 always @ (posedge clk2_i)
427 if (hcount == 227)
428 if (dma_instr_en &&
429 (vcount == 7 ||
430 (dcount == ((last_vscrol_en && !vscrol_en) ? vscrol : maxline) &&
431 !wait_vblank && !vblank && dma_instr_en)))
432 new_block <= 1;
433 else
434 new_block <= 0;
436 assign load_instr = new_block && (hcount == 2);
438 assign vscrol_en = dma_block && ir[5];
440 always @ (posedge clk2_i)
441 if (hcount == 0 && new_block)
442 last_vscrol_en <= vscrol_en;
444 // DCOUNT
445 always @ (posedge clk2_i)
446 if (vcount == 0)
447 dcount <= 0;
448 else if (hcount == 6)
449 if (new_block)
450 dcount <= (!last_vscrol_en && vscrol_en) ? vscrol : 0;
451 else
452 dcount <= dcount + 1;
454 // Memory Scan Counter.
455 always @ (posedge clk_i)
456 if (load_pf)
457 memscan_ctr[11:0] <= memscan_ctr[11:0] + 1;
458 else if (load_memscanl)
459 memscan_ctr[7:0] <= masterdat_i;
460 else if (load_memscanh)
461 memscan_ctr[15:8] <= masterdat_i;
463 // Instruction register.
464 always @ (posedge clk_i)
465 if (load_instr)
466 ir <= masterdat_i;
467 else if (vcount == 0)
468 ir <= 0;
470 // Instruction decoder.
471 always @ (ir) begin
472 maxline = 0;
473 char_block = 0;
474 one_bit_pixel = 0;
475 case (ir[3:0])
476 'h0: maxline = ir[6:4];
477 'h1: maxline = 0;
478 'h2: begin
479 maxline = 7;
480 char_block = 1;
481 one_bit_pixel = 0;
483 'h3: begin
484 maxline = 9;
485 char_block = 1;
486 one_bit_pixel = 0;
488 'h4: begin
489 maxline = 7;
490 char_block = 1;
491 one_bit_pixel = 0;
493 'h5: begin
494 maxline = 15;
495 char_block = 1;
496 one_bit_pixel = 0;
498 'h6: begin
499 maxline = 7;
500 char_block = 1;
501 one_bit_pixel = 1;
503 'h7: begin
504 maxline = 15;
505 char_block = 1;
506 one_bit_pixel = 1;
508 'h8: begin
509 maxline = 7;
510 char_block = 0;
511 one_bit_pixel = 0;
513 'h9: begin
514 maxline = 3;
515 char_block = 0;
516 one_bit_pixel = 1;
518 'ha: begin
519 maxline = 3;
520 char_block = 0;
521 one_bit_pixel = 0;
523 'hb: begin
524 maxline = 1;
525 char_block = 0;
526 one_bit_pixel = 1;
528 'hc: begin
529 maxline = 0;
530 char_block = 0;
531 one_bit_pixel = 1;
533 'hd: begin
534 maxline = 1;
535 char_block = 0;
536 one_bit_pixel = 0;
538 'he: begin
539 maxline = 0;
540 char_block = 0;
541 one_bit_pixel = 0;
543 'hf: begin
544 maxline = 0;
545 char_block = 0;
546 one_bit_pixel = 0;
548 endcase
551 assign dli = ir[7];
552 assign wait_vblank = (ir == 'h41);
553 assign dma_block = (ir[3:0] != 0 && ir[3:0] != 1);
555 assign load_dlptrl = new_block && (ir[3:0] == 1) && (hcount == 12);
556 assign load_dlptrh = new_block && (ir[3:0] == 1) && (hcount == 14);
558 assign load_memscanl = new_block && dma_block && ir[6] && (hcount == 12);
559 assign load_memscanh = new_block && dma_block && ir[6] && (hcount == 14);
561 assign load_mis = !vblank && dma_mis_en && (hcount == 0);
562 assign load_ply = !vblank && dma_ply_en &&
563 (hcount == 4 || hcount == 6 ||
564 hcount == 8 || hcount == 10);
565 assign dma_ply_num = (hcount >> 1) - 2;
567 assign dl_load = load_instr || load_memscanh || load_memscanl ||
568 load_dlptrh || load_dlptrl;
570 always @ (posedge clk2_i)
571 if (hcount == 16 + (ir[4] ? (hscrol & ~1) : 0))
572 ms_hcount <= 0;
573 else
574 ms_hcount <= ms_hcount + 1;
576 antic_ms_hcount_seq u_ms_hcount_seq(.clk_i(clk_i),
577 .ms_hcount(ms_hcount),
578 .new_block(new_block),
579 .dma_block(dma_block),
580 .char_block(char_block),
581 .dma_pf_width(dma_pf_width),
582 .ir(ir),
583 .shift_reg_shift(shift_reg_shift),
584 .load_pf(load_pf),
585 .load_char(load_char),
586 .load_out(load_out),
587 .out_reg_shift(out_reg_shift));
589 always @ (hcount or dma_pf_width or dma_instr_en or vblank) begin
590 if (!dma_instr_en || vblank)
591 dwin = 0;
592 else
593 case (dma_pf_width)
594 0: dwin = 0;
595 1: dwin = (hcount >= 64 && hcount < 192);
596 2: dwin = (hcount >= 48 && hcount < 208);
597 3: dwin = (hcount >= 44 && hcount < 220);
598 endcase
601 assign hblank = (hcount < 34 || hcount >= 222);
602 assign vblank = (vcount < 8 || vcount >= 240);
604 // TODO: lines here are approximate.
605 assign vsync = (vcount >= 300 && vcount < 303);
607 assign char_blank = (ir[3:0] == 3) &&
608 (((chr_dcount == 0 || chr_dcount == 1) &&
609 shift_reg_out[6:5] == 2'b11) ||
610 ((chr_dcount == 8 || chr_dcount == 9) &&
611 shift_reg_out[6:5] != 2'b11));
613 always @ (posedge clk_i)
614 if (load_char) begin
615 char_data <= char_blank ? 0 : masterdat_i;
616 char_color_p <= shift_reg_out[7:6];
619 always @ (posedge clk2_i)
620 if (load_out) begin
621 out_reg <= char_block ? char_data : shift_reg_out;
622 char_color <= char_color_p;
624 else if (out_reg_shift)
625 if (one_bit_pixel)
626 out_reg <= {out_reg[6:0], 1'b0};
627 else
628 out_reg <= {out_reg[5:0], 2'b00};
630 always @ (ir or out_reg or char_color or chactl)
631 if (ir[3:0] == 2 || ir[3:0] == 3)
632 if (char_color[1])
633 pf_antic_out = {1'b1,
634 (out_reg[7:6] & ~{2{chactl[0]}}) ^ {2{chactl[1]}}};
635 else
636 pf_antic_out = {1'b1, out_reg[7:6]};
637 else if (ir[3:0] == 'hf)
638 pf_antic_out = {1'b1, out_reg[7:6]};
639 else if (ir[3:0] == 4 || ir[3:0] == 5)
640 case (out_reg[7:6])
641 0: pf_antic_out = 3'b000;
642 1: pf_antic_out = 3'b100;
643 2: pf_antic_out = 3'b101;
644 3: pf_antic_out = char_color[1] ? 3'b111 : 3'b110;
645 endcase
646 else if (ir[3:0] == 6 || ir[3:0] == 7)
647 if (out_reg[7])
648 pf_antic_out = {1'b1, char_color};
649 else
650 pf_antic_out = 3'b000;
651 else if (ir[3:0] == 8 || ir[3:0] == 'ha || ir[3:0] == 'hd ||
652 ir[3:0] == 'he)
653 case (out_reg[7:6])
654 0: pf_antic_out = 3'b000;
655 1: pf_antic_out = 3'b100;
656 2: pf_antic_out = 3'b101;
657 3: pf_antic_out = 3'b110;
658 endcase
659 else if (ir[3:0] == 9 || ir[3:0] == 'hb || ir[3:0] == 'hc)
660 pf_antic_out = out_reg[7] ? 3'b100 : 3'b000;
661 else
662 pf_antic_out = 3'b000;
664 always @ (posedge clk2_i)
665 pf_antic_out_d <= pf_antic_out;
667 always @ (vsync or vblank or hblank or dwin or ir or pf_antic_out or
668 pf_antic_out_d) begin
669 if (vsync)
670 antic_out = 3'b001;
671 else if (hblank || vblank)
672 if (ir[3:0] == 2 || ir[3:0] == 3 || ir[3:0] == 'hf)
673 antic_out = 3'b011;
674 else
675 antic_out = 3'b010;
676 else if (dwin)
677 antic_out = (dma_block && ir[4] && hscrol[0]) ?
678 pf_antic_out_d : pf_antic_out;
679 else
680 antic_out = 3'b000;
683 always @ (posedge clk_i)
684 if (hcount >= 50 && hcount <= 82 && (hcount & 7) == 2)
685 refresh_req <= 1;
686 else if (refresh_ack)
687 refresh_req <= 0;
689 assign chr_dcount = dcount ^ {4{chactl[2]}};
691 always @ (dl_load or dlist_ctr or load_mis or load_ply or
692 pmbase or vcount or dma_ply_num or
693 load_pf or memscan_ctr or
694 load_char or chbase or shift_reg_out or chr_dcount or
695 refresh_req) begin
696 refresh_ack = 0;
697 if (dl_load)
698 adr_o = dlist_ctr;
699 else if (load_mis)
700 adr_o = dma_pm_1res ?
701 {pmbase[5:1], 3'b011, vcount[7:0]} :
702 {pmbase[5:0], 3'b011, vcount[7:1]};
703 else if (load_ply)
704 adr_o = dma_pm_1res ?
705 {pmbase[5:1], 1'b1, dma_ply_num, vcount[7:0]} :
706 {pmbase[5:0], 1'b1, dma_ply_num, vcount[7:1]};
707 else if (load_pf)
708 adr_o = memscan_ctr;
709 else if (load_char)
710 case (ir[3:0])
711 2: adr_o = {chbase[6:1], shift_reg_out[6:0], chr_dcount[2:0]};
712 3: adr_o = {chbase[6:1], shift_reg_out[6:0], chr_dcount[2:0]};
713 4: adr_o = {chbase[6:1], shift_reg_out[6:0], chr_dcount[2:0]};
714 5: adr_o = {chbase[6:1], shift_reg_out[6:0], chr_dcount[3:1]};
715 6: adr_o = {chbase[6:0], shift_reg_out[5:0], chr_dcount[2:0]};
716 7: adr_o = {chbase[6:0], shift_reg_out[5:0], chr_dcount[3:1]};
717 endcase
718 else if (refresh_req) begin
719 refresh_ack = 1;
720 adr_o = memscan_ctr;
721 end else
722 adr_o = memscan_ctr;
725 assign stb_o = dl_load || load_mis || load_ply || load_pf || load_char ||
726 wsync || refresh_req;
727 assign cyc_o = stb_o;
729 antic_shift_reg u_shift_reg(.clk_i(clk_i),
730 .shift(shift_reg_shift),
731 .load(load_pf),
732 .in(masterdat_i),
733 .out(shift_reg_out));
734 endmodule