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Partly reverted r40090: DMA is enabled for ATAPI devices again.
[AROS.git] / rom / devs / ata / lowlevel.c
blob5f62bd7637188204cdc1e5dc9f770d8ef481ee12
1 /*
2 Copyright © 2004-2012, The AROS Development Team. All rights reserved.
3 $Id$
4
5 Desc:
6 Lang: English
7 */
8
9 /*
10 * PARTIAL CHANGELOG:
11 * DATE NAME ENTRY
12 * ---------- ------------------ -------------------------------------------------------------------
13 * 2006-12-20 T. Wiszkowski Updated ATA Packet Interface to handle ATAPI/SCSI Commands
14 * 2008-01-06 T. Wiszkowski Corrected and completed ATA Packet Interface handling. PIO transfers fully operational.
15 * 2008-01-07 T. Wiszkowski Added initial DMA support for Direct SCSI commands. Corrected atapi
16 * READ and WRITE commands to pass proper transfer size to the atapi_SendPacket
17 * as discovered by mschulz
18 * 2008-01-25 T. Wiszkowski Rebuilt, rearranged and partially fixed 60% of the code here
19 * Enabled implementation to scan for other PCI IDE controllers
20 * Implemented ATAPI Packet Support for both read and write
21 * Corrected ATAPI DMA handling
22 * Fixed major IDE enumeration bugs severely handicapping transfers with more than one controller
23 * Compacted source and implemented major ATA support procedure
24 * Improved DMA and Interrupt management
25 * Removed obsolete code
26 * 2008-01-26 T. Wiszkowski Restored 32bit io
27 * Removed memory dump upon RequestSense
28 * 2008-02-08 T. Wiszkowski Fixed DMA accesses for direct scsi devices,
29 * Corrected IO Areas to allow ATA to talk to PCI controllers
30 * 2008-03-03 T. Wiszkowski Added drive reselection + setup delay on Init
31 * 2008-03-29 T. Wiszkowski Restored error on 64bit R/W access to non-64bit capable atapi devices
32 * cleared debug flag
33 * 2008-03-30 T. Wiszkowski Added workaround for interrupt collision handling; fixed SATA in LEGACY mode.
34 * nForce and Intel SATA chipsets should now be operational (nForce confirmed)
35 * 2008-03-31 M. Schulz The ins/outs function definitions used only in case of x86 and x86_64 architectures.
36 * Otherwise, function declaratons are emitted.
37 * 2008-04-01 M. Schulz Use C functions ata_ins[wl] ata_outs[wl]
38 * 2008-04-03 T. Wiszkowski Fixed IRQ flood issue, eliminated and reduced obsolete / redundant code
39 * 2008-04-05 T. Wiszkowski Improved IRQ management
40 * 2008-04-07 T. Wiszkowski Changed bus timeout mechanism
41 * increased failure timeout values to cover rainy day scenarios
42 * 2008-04-20 T. Wiszkowski Corrected the flaw in drive identification routines leading to ocassional system hangups
43 * 2008-05-11 T. Wiszkowski Remade the ata trannsfers altogether, corrected the pio/irq handling
44 * medium removal, device detection, bus management and much more
45 * 2008-05-12 P. Fedin Explicitly enable multisector transfers on the drive
46 * 2008-05-18 T. Wiszkowski Added extra checks to prevent duplicating drive0 in drive0 only configs
47 * 2008-05-18 T. Wiszkowski Replaced static C/H/S with more accurate calcs, should make HDTB and other tools see right capacity
48 * 2008-05-19 T. Wiszkowski Updated ATA DMA handling and transfer wait operation to allow complete transfer before dma_StopDMA()
49 * 2008-05-30 T. Wiszkowski Corrected CHS calculation for larger disks
50 * 2008-06-03 K. Smiechowicz Added 400ns delay in ata_WaitBusyTO before read of device status.
51 * 2008-06-25 P. Fedin Added "nomulti" flag
52 * PIO works correctly again
53 * 2008-11-28 T. Wiszkowski updated test unit ready to suit individual taste of hw manufacturers
54 * 2009-01-20 J. Koivisto Modified bus reseting scheme
55 * 2009-02-04 T. Wiszkowski Disabled ATA debug on official builds
56 * 2009-03-05 T. Wiszkowski remade timeouts, added timer-based and benchmark-based delays.
57 * 2011-05-19 P. Fedin The Big Rework. Separated bus-specific code. Made 64-bit-friendly.
58 * 2012-02-12 T. Wilen DEVHEAD_VAL, ata_HandleIRQ returns BOOL.
59 * 2012-03-17 T. Wilen AckInterrupt(). Required by A600/A1200 Gayle IDE hardware.
60 */
61 /*
62 * TODO:
63 * - put a critical section around DMA transfers (shared dma channels)
64 */
65
66 // use #define xxx(a) D(a) to enable particular sections.
67 #if DEBUG
68 #define DIRQ(a) D(a)
69 #define DIRQ_MORE(a)
70 #define DUMP(a) D(a)
71 #define DUMP_MORE(a)
72 #define DATA(a) D(a)
73 #define DATAPI(a) D(a)
74 #define DINIT(a) (a)
75 #else
76 #define DIRQ(a) do { } while (0)
77 #define DIRQ_MORE(a) do { } while (0)
78 #define DUMP(a) do { } while (0)
79 #define DUMP_MORE(a) do { } while (0)
80 #define DATA(a) do { } while (0)
81 #define DATAPI(a) do { } while (0)
82 #define DINIT(a) do { } while (0)
83 #endif
84 /* Errors that shouldn't happen */
85 #define DERROR(a) a
86
87 #include <aros/debug.h>
88 #include <exec/types.h>
89 #include <exec/exec.h>
90 #include <exec/resident.h>
91 #include <utility/utility.h>
92 #include <oop/oop.h>
93
94 #include <proto/exec.h>
95 #include <devices/timer.h>
96
97 #include "ata.h"
98 #include "timer.h"
99
100 /*
101 Prototypes of static functions from lowlevel.c. I do not want to make them
102 non-static as I'd like to remove as much symbols from global table as possible.
103 Besides some of this functions could conflict with old ide.device or any other
104 device.
105 */
106 static BYTE ata_ReadSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
107 static BYTE ata_ReadSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
108 static BYTE ata_ReadMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
109 static BYTE ata_ReadMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
110 static BYTE ata_ReadDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
111 static BYTE ata_ReadDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
112 static BYTE ata_WriteSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
113 static BYTE ata_WriteSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
114 static BYTE ata_WriteMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
115 static BYTE ata_WriteMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
116 static BYTE ata_WriteDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
117 static BYTE ata_WriteDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
118 static BYTE ata_Eject(struct ata_Unit *);
119 static BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq, UBYTE *stout);
120
121 static BYTE atapi_EndCmd(struct ata_Unit *unit);
122
123 static BYTE atapi_Read(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
124 static BYTE atapi_Write(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
125 static BYTE atapi_Eject(struct ata_Unit *);
126
127 static void common_SetBestXferMode(struct ata_Unit* unit);
128
129 #define DEVHEAD_VAL 0x40
130
131 #if DEBUG
132 static void dump(APTR mem, ULONG len)
133 {
134 register int i, j = 0;
135
136 DUMP_MORE(for (j=0; j<(len+15)>>4; ++j))
137 {
138 bug("[ATA ] %06lx: ", j<<4);
139
140 for (i=0; i<len-(j<<4); i++)
141 {
142 bug("%02lx ", ((unsigned char*)mem)[(j<<4)|i]);
143 if (i == 15)
144 break;
145 }
146
147 for (i=0; i<len-(j<<4); i++)
148 {
149 unsigned char c = ((unsigned char*)mem)[(j<<4)|i];
150
151 bug("%c", c >= 0x20 ? c<=0x7f ? c : '.' : '.');
152 if (i == 15)
153 break;
154 }
155 bug("\n");
156 }
157 }
158 #endif
159
160 static void ata_strcpy(const UBYTE *str1, UBYTE *str2, ULONG size)
161 {
162 register int i = size;
163
164 while (size--)
165 str2[size ^ 1] = str1[size];
166
167 while (i > 0 && str2[--i] <= ' ')
168 str2[i] = '\0';
169 }
170
171 /*
172 * a STUB function for commands not supported by this particular device
173 */
174 static BYTE ata_STUB(struct ata_Unit *au)
175 {
176 DERROR(bug("[ATA%02ld] CALLED STUB FUNCTION (GENERIC). THIS OPERATION IS NOT "
177 "SUPPORTED BY DEVICE\n", au->au_UnitNum));
178 return CDERR_NOCMD;
179 }
180
181 static BYTE ata_STUB_IO32(struct ata_Unit *au, ULONG blk, ULONG len,
182 APTR buf, ULONG* act)
183 {
184 DERROR(bug("[ATA%02ld] CALLED STUB FUNCTION (IO32). THIS OPERATION IS NOT "
185 "SUPPORTED BY DEVICE\n", au->au_UnitNum));
186 return CDERR_NOCMD;
187 }
188
189 static BYTE ata_STUB_IO64(struct ata_Unit *au, UQUAD blk, ULONG len,
190 APTR buf, ULONG* act)
191 {
192 DERROR(bug("[ATA%02ld] CALLED STUB FUNCTION -- IO ACCESS TO BLOCK %08lx:%08lx, LENGTH %08lx. THIS OPERATION IS NOT SUPPORTED BY DEVICE\n", au->au_UnitNum, (blk >> 32), (blk & 0xffffffff), len));
193 return CDERR_NOCMD;
194 }
195
196 static BYTE ata_STUB_SCSI(struct ata_Unit *au, struct SCSICmd* cmd)
197 {
198 DERROR(bug("[ATA%02ld] CALLED STUB FUNCTION. THIS OPERATION IS NOT SUPPORTED BY DEVICE\n", au->au_UnitNum));
199 return CDERR_NOCMD;
200 }
201
202 static inline struct ata_Unit* ata_GetSelectedUnit(struct ata_Bus* bus)
203 {
204 return bus->ab_SelectedUnit;
205 }
206
207 static inline UBYTE ata_ReadStatus(struct ata_Bus *bus)
208 {
209 return bus->ab_Driver->ata_in(ata_Status, bus->ab_Port, bus->ab_DriverData);
210 }
211
212 static inline UBYTE ata_ReadAltStatus(struct ata_Bus *bus)
213 {
214 return bus->ab_Driver->ata_in(ata_AltStatus, bus->ab_Alt, bus->ab_DriverData);
215 }
216
217 static inline BOOL ata_SelectUnit(struct ata_Unit* unit)
218 {
219 struct ata_Bus *bus = unit->au_Bus;
220
221 if (unit == bus->ab_SelectedUnit)
222 return TRUE;
223
224 ATA_OUT(unit->au_DevMask, ata_DevHead, bus->ab_Port);
225
226 do
227 {
228 ata_WaitNano(400, bus->ab_Base);
229 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
230 }
231 while (0 != (ATAF_BUSY & ata_ReadStatus(bus)));
232
233 bus->ab_SelectedUnit = unit;
234
235 return TRUE;
236 }
237
238 /*
239 * handle IRQ; still fast and efficient, supposed to verify if this irq is for us and take adequate steps
240 * part of code moved here from ata.c to reduce containment
241 */
242 void ata_IRQSignalTask(struct ata_Bus *bus)
243 {
244 bus->ab_IntCnt++;
245 Signal(bus->ab_Task, 1UL << bus->ab_SleepySignal);
246 }
247
248 /* PIO-only: IDE doublers don't have real AltStatus register.
249 * Do not assume reading AltStatus does not clear interrupt request.
250 */
251 BOOL ata_HandleIRQ(struct ata_Bus *bus)
252 {
253 struct ata_Unit *unit = ata_GetSelectedUnit(bus);
254 UBYTE status;
255 BOOL for_us = FALSE;
256
257 /*
258 * don't waste your time on checking other devices.
259 * pass irq ONLY if task is expecting one;
260 */
261 if ((unit != NULL) && (0 != bus->ab_HandleIRQ))
262 {
263 /*
264 * The DMA status register indicates all interrupt types, not
265 * just DMA interrupts. However, if there's no DMA port, we have
266 * to rely on the busy flag, which is incompatible with IRQ sharing.
267 */
268 if (unit->au_DMAPort != 0) {
269 status = ata_ReadAltStatus(bus);
270 for_us =
271 (ATA_IN(dma_Status, unit->au_DMAPort) & DMAF_Interrupt) != 0;
272 } else {
273 status = ata_ReadStatus(bus);
274 for_us = (status & ATAF_BUSY) == 0;
275 }
276 }
277
278 if (for_us)
279 {
280 /*
281 * Acknowledge interrupt (note that the DMA interrupt bit should be
282 * cleared for all interrupt types)
283 */
284 if (unit->au_DMAPort != 0) {
285 ATA_OUT(ATA_IN(dma_Status, unit->au_DMAPort) |
286 DMAF_Error | DMAF_Interrupt, dma_Status, unit->au_DMAPort);
287 status = ata_ReadStatus(bus);
288 } else {
289 /* Acknowledge PIO hardware interrupt (Amiga A600/A1200 Gayle) */
290 if (bus->ab_Driver->AckInterrupt)
291 bus->ab_Driver->AckInterrupt(bus);
292 }
293
294 /*
295 * ok, we have a routine to handle any form of transmission etc.
296 */
297 DIRQ(bug("[ATA ] IRQ: Calling dedicated handler... \n"));
298 bus->ab_HandleIRQ(unit, status);
299
300 return TRUE;
301 }
302
303 DIRQ_MORE({
304 /*
305 * if we got *here* then device is most likely not expected to have an irq.
306 */
307 status = ata_ReadAltStatus(bus);
308 bug("[ATA%02ld] IRQ: Checking busy flag: ", unit->au_UnitNum);
309
310 if (0 == (ATAF_BUSY & status))
311 {
312 bug("device ready. Dumping details:\n");
313
314 bug("[ATA ] STATUS: %02lx\n", status);
315 bug("[ATA ] ALT STATUS: %02lx\n", ata_ReadAltStatus(bus));
316 bug("[ATA ] ERROR: %02lx\n", BUS_IN(ata_Error, bus->ab_Port));
317 bug("[ATA ] IRQ: REASON: %02lx\n", BUS_IN(atapi_Reason, bus->ab_Port));
318 }
319 else
320 {
321 bug("device still busy. ignoring irq.\n");
322 }
323 });
324 return FALSE;
325 }
326
327 void ata_IRQSetHandler(struct ata_Unit *unit, void (*handler)(struct ata_Unit*, UBYTE), APTR piomem, ULONG blklen, ULONG piolen)
328 {
329 if (NULL != handler)
330 unit->au_cmd_error = 0;
331
332 unit->au_cmd_data = piomem;
333 unit->au_cmd_length = (piolen < blklen) ? piolen : blklen;
334 unit->au_cmd_total = piolen;
335 unit->au_Bus->ab_HandleIRQ = handler;
336 }
337
338 void ata_IRQNoData(struct ata_Unit *unit, UBYTE status)
339 {
340 if (status & ATAF_BUSY)
341 return;
342
343 if ((unit->au_cmd_error == 0) && (status & ATAF_ERROR))
344 unit->au_cmd_error = HFERR_BadStatus;
345
346 DIRQ(bug("[ATA%02ld] IRQ: NoData - done; status %02lx.\n", unit->au_UnitNum, status));
347 ata_IRQSetHandler(unit, NULL, NULL, 0, 0);
348 ata_IRQSignalTask(unit->au_Bus);
349 }
350
351 void ata_IRQPIORead(struct ata_Unit *unit, UBYTE status)
352 {
353 if (status & ATAF_DATAREQ) {
354 DIRQ(bug("[ATA ] IRQ: PIOReadData - DRQ.\n"));
355 unit->au_ins(unit->au_cmd_data, unit->au_Bus->ab_Port, unit->au_cmd_length, unit->au_Bus->ab_DriverData);
356
357 /*
358 * indicate it's all done here
359 */
360 unit->au_cmd_data += unit->au_cmd_length;
361 unit->au_cmd_total -= unit->au_cmd_length;
362 if (unit->au_cmd_total) {
363 if (unit->au_cmd_length > unit->au_cmd_total)
364 unit->au_cmd_length = unit->au_cmd_total;
365 return;
366 }
367 DIRQ(bug("[ATA ] IRQ: PIOReadData - transfer completed.\n"));
368 }
369 ata_IRQNoData(unit, status);
370 }
371
372 void ata_PIOWriteBlk(struct ata_Unit *unit)
373 {
374 unit->au_outs(unit->au_cmd_data, unit->au_Bus->ab_Port, unit->au_cmd_length, unit->au_Bus->ab_DriverData);
375
376 /*
377 * indicate it's all done here
378 */
379 unit->au_cmd_data += unit->au_cmd_length;
380 unit->au_cmd_total -= unit->au_cmd_length;
381 if (unit->au_cmd_length > unit->au_cmd_total)
382 unit->au_cmd_length = unit->au_cmd_total;
383 }
384
385 void ata_IRQPIOWrite(struct ata_Unit *unit, UBYTE status)
386 {
387 if (status & ATAF_DATAREQ) {
388 DIRQ(bug("[ATA ] IRQ: PIOWriteData - DRQ.\n"));
389 ata_PIOWriteBlk(unit);
390 return;
391 }
392 DIRQ(bug("[ATA ] IRQ: PIOWriteData - done.\n"));
393 ata_IRQNoData(unit, status);
394 }
395
396 void ata_IRQDMAReadWrite(struct ata_Unit *unit, UBYTE status)
397 {
398 UBYTE stat = ATA_IN(dma_Status, unit->au_DMAPort);
399
400 DIRQ(bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %02lx\n", unit->au_UnitNum, status, stat));
401
402 if ((status & ATAF_ERROR) || (stat & DMAF_Error))
403 {
404 /* This is turned on in order to help Phantom - Pavel Fedin <sonic_amiga@rambler.ru> */
405 DERROR(bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %02lx\n", unit->au_UnitNum, status, stat));
406 DERROR(bug("[ATA%02ld] IRQ: ERROR %02lx\n", unit->au_UnitNum, ATA_IN(atapi_Error, unit->au_Bus->ab_Port)));
407 DERROR(bug("[ATA ] IRQ: DMA Failed.\n"));
408
409 unit->au_cmd_error = HFERR_DMA;
410 ata_IRQNoData(unit, status);
411 }
412 else if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
413 {
414 DIRQ(bug("[ATA ] IRQ: DMA Done.\n"));
415 ata_IRQNoData(unit, status);
416 }
417 }
418
419 void ata_IRQPIOReadAtapi(struct ata_Unit *unit, UBYTE status)
420 {
421 ULONG port = unit->au_Bus->ab_Port;
422 ULONG size = 0;
423 LONG remainder = 0;
424 UBYTE reason = ATA_IN(atapi_Reason, port);
425 DIRQ(bug("[DSCSI] Current status: %ld during READ\n", reason));
426
427 /* have we failed yet? */
428 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
429 ata_IRQNoData(unit, status);
430 if (status & ATAF_ERROR)
431 {
432 ata_IRQNoData(unit, status);
433 return;
434 }
435
436 /* anything for us please? */
437 if (ATAPIF_READ != (reason & ATAPIF_MASK))
438 return;
439
440 size = ATA_IN(atapi_ByteCntH, port) << 8 | ATA_IN(atapi_ByteCntL, port);
441 DIRQ(bug("[ATAPI] IRQ: data available for read (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
442
443 if (size > unit->au_cmd_total)
444 {
445 DERROR(bug("[ATAPI] IRQ: CRITICAL! MORE DATA OFFERED THAN STORAGE CAN TAKE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total));
446 remainder = size - unit->au_cmd_total;
447 size = unit->au_cmd_total;
448 }
449
450 unit->au_ins(unit->au_cmd_data, port, size, unit->au_Bus->ab_DriverData);
451 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
452 unit->au_cmd_total -= size;
453
454 DIRQ(bug("[ATAPI] IRQ: %lu bytes read.\n", size));
455
456 for (; remainder > 0; remainder -= 2)
457 unit->au_ins(&size, port, 2, unit->au_Bus->ab_DriverData);
458
459 if (unit->au_cmd_total == 0)
460 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
461 }
462
463 void ata_IRQPIOWriteAtapi(struct ata_Unit *unit, UBYTE status)
464 {
465 ULONG port = unit->au_Bus->ab_Port;
466 ULONG size = 0;
467 UBYTE reason = ATA_IN(atapi_Reason, port);
468 DIRQ(bug("[ATAPI] IRQ: Current status: %ld during WRITE\n", reason));
469
470 /* have we failed yet? */
471 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
472 ata_IRQNoData(unit, status);
473 if (status & ATAF_ERROR)
474 {
475 ata_IRQNoData(unit, status);
476 return;
477 }
478
479 /* anything for us please? */
480 if (ATAPIF_WRITE != (reason & ATAPIF_MASK))
481 return;
482
483 size = ATA_IN(atapi_ByteCntH, port) << 8 | ATA_IN(atapi_ByteCntL, port);
484 DIRQ(bug("[ATAPI] IRQ: data requested for write (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
485
486 if (size > unit->au_cmd_total)
487 {
488 DERROR(bug("[ATAPI] IRQ: CRITICAL! MORE DATA REQUESTED THAN STORAGE CAN GIVE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total));
489 size = unit->au_cmd_total;
490 }
491
492 unit->au_outs(unit->au_cmd_data, port, size, unit->au_Bus->ab_DriverData);
493 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
494 unit->au_cmd_total -= size;
495
496 DIRQ(bug("[ATAPI] IRQ: %lu bytes written.\n", size));
497
498 if (unit->au_cmd_total == 0)
499 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
500 }
501
502 /*
503 * wait for timeout or drive ready
504 */
505 BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq, UBYTE *stout)
506 {
507 struct ata_Bus *bus = unit->au_Bus;
508 UBYTE status;
509 ULONG sigs = SIGBREAKF_CTRL_C;
510 ULONG step = 0;
511 BOOL res = TRUE;
512
513 if (unit->au_Bus->ab_Base->ata_Poll)
514 irq = FALSE;
515
516 /* FIXME: This shouldn't happen but it could explain reported random -6 (IOERR_UNITBUSY) problem */
517 if (SetSignal(0, SIGBREAKF_CTRL_C) & SIGBREAKF_CTRL_C)
518 DERROR(bug("[ATA%02ld] SIGBREAKF_CTRL_C was already set!?\n", unit->au_UnitNum));
519
520 /*
521 * set up bus timeout
522 */
523 Forbid();
524 unit->au_Bus->ab_Timeout = tout;
525 Permit();
526
527 sigs |= (irq ? (1 << unit->au_Bus->ab_SleepySignal) : 0);
528 status = ATA_IN(ata_AltStatus, unit->au_Bus->ab_Alt);
529
530 if (irq)
531 {
532 /*
533 * wait for either IRQ or TIMEOUT (unless device seems to be a
534 * phantom SATAPI drive, in which case we fake a timeout)
535 */
536 DIRQ(bug("[ATA%02ld] Waiting (Current status: %02lx)...\n",
537 unit->au_UnitNum, status));
538 if (status != 0)
539 step = Wait(sigs);
540 else
541 step = SIGBREAKF_CTRL_C;
542
543 /*
544 * now if we did reach timeout, then there's no point in going ahead.
545 */
546 if (SIGBREAKF_CTRL_C & step)
547 {
548 DERROR(bug("[ATA%02ld] Timeout while waiting for device to complete"
549 " operation\n", unit->au_UnitNum));
550 res = FALSE;
551
552 /*
553 * do nothing if the interrupt eventually arrives
554 */
555 Disable();
556 ata_IRQSetHandler(unit, NULL, NULL, 0, 0);
557 Enable();
558 }
559 }
560 else
561 {
562 while (status & ATAF_BUSY)
563 {
564 ++step;
565
566 /*
567 * every 16n rounds do some extra stuff
568 */
569 if ((step & 15) == 0)
570 {
571 /*
572 * huhm. so it's been 16n rounds already. any timeout yet?
573 */
574 if (SetSignal(0, SIGBREAKF_CTRL_C) & SIGBREAKF_CTRL_C)
575 {
576 DERROR(bug("[ATA%02ld] Device still busy after timeout."
577 " Aborting\n", unit->au_UnitNum));
578 res = FALSE;
579 break;
580 }
581
582 /*
583 * no timeout just yet, but it's not a good idea to keep
584 * spinning like that. let's give the system some time.
585 */
586 ata_WaitNano(400, bus->ab_Base);
587 }
588
589 status = ATA_IN(ata_AltStatus, unit->au_Bus->ab_Alt);
590 }
591 }
592
593 /*
594 * clear up all our expectations
595 */
596 Forbid();
597 unit->au_Bus->ab_Timeout = -1;
598 Permit();
599
600 /*
601 * get final status and clear any interrupt (may be neccessary if we
602 * were polling, for example)
603 */
604 status = ATA_IN(ata_Status, unit->au_Bus->ab_Port);
605
606 /*
607 * be nice to frustrated developer
608 */
609 DIRQ(bug("[ATA%02ld] WaitBusy status: %lx / %ld\n", unit->au_UnitNum,
610 status, res));
611
612 /*
613 * release old junk
614 */
615 SetSignal(0, sigs);
616
617 /*
618 * and say it went fine (i mean it)
619 */
620 if (stout)
621 *stout = status;
622 return res;
623 }
624
625 /*
626 * Procedure for sending ATA command blocks
627 * it appears LARGE but there's a lot of COMMENTS here :)
628 * handles *all* ata commands (no data, pio and dma)
629 * naturally could be split at some point in the future
630 * depends if anyone believes that the change for 50 lines
631 * would make slow ATA transfers any faster
632 */
633 static BYTE ata_exec_cmd(struct ata_Unit* unit, ata_CommandBlock *block)
634 {
635 struct ata_Bus *bus = unit->au_Bus;
636 ULONG port = unit->au_Bus->ab_Port;
637 BYTE err = 0;
638 APTR mem = block->buffer;
639 UBYTE status;
640
641 if (FALSE == ata_SelectUnit(unit))
642 return IOERR_UNITBUSY;
643
644 switch (block->type)
645 {
646 case CT_LBA28:
647 if (block->sectors > 256)
648 {
649 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 256 sectors. Aborting.\n", unit->au_UnitNum, block->sectors));
650 return IOERR_BADLENGTH;
651 }
652
653 /* note:
654 * we want the above to fall in here!
655 * we really do (checking for secmul)
656 */
657
658 case CT_LBA48:
659 if (block->sectors > 65536)
660 {
661 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 65536 sectors. Aborting.\n", unit->au_UnitNum, block->sectors));
662 return IOERR_BADLENGTH;
663 }
664 if (block->secmul == 0)
665 {
666 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid transfer multiplier. Should be at least set to 1 (correcting)\n", unit->au_UnitNum));
667 block->secmul = 1;
668 }
669 break;
670
671 case CT_NoBlock:
672 break;
673
674 default:
675 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid command type %lx. Aborting.\n", unit->au_UnitNum, block->type));
676 return IOERR_NOCMD;
677 }
678
679 block->actual = 0;
680 D(bug("[ATA%02ld] ata_exec_cmd: Executing command %02lx\n", unit->au_UnitNum, block->command));
681
682 if (block->feature != 0)
683 ATA_OUT(block->feature, ata_Feature, port);
684
685 /*
686 * - set LBA and sector count
687 */
688 switch (block->type)
689 {
690 case CT_LBA28:
691 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 28bit LBA addressing (OLD)\n", unit->au_UnitNum));
692
693 ATA_OUT(((block->blk >> 24) & 0x0f) | DEVHEAD_VAL | unit->au_DevMask, ata_DevHead, port);
694 ATA_OUT(block->blk >> 16, ata_LBAHigh, port);
695 ATA_OUT(block->blk >> 8, ata_LBAMid, port);
696 ATA_OUT(block->blk, ata_LBALow, port);
697 ATA_OUT(block->sectors, ata_Count, port);
698 break;
699
700 case CT_LBA48:
701 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 48bit LBA addressing (NEW)\n", unit->au_UnitNum));
702
703 ATA_OUT(0x40 | unit->au_DevMask, ata_DevHead, port);
704 ATA_OUT(block->blk >> 40, ata_LBAHigh, port);
705 ATA_OUT(block->blk >> 32, ata_LBAMid, port);
706 ATA_OUT(block->blk >> 24, ata_LBALow, port);
707
708 ATA_OUT(block->blk >> 16, ata_LBAHigh, port);
709 ATA_OUT(block->blk >> 8, ata_LBAMid, port);
710 ATA_OUT(block->blk, ata_LBALow, port);
711
712 ATA_OUT(block->sectors >> 8, ata_Count, port);
713 ATA_OUT(block->sectors, ata_Count, port);
714 break;
715
716 case CT_NoBlock:
717 DATA(bug("[ATA%02ld] ata_exec_cmd: Command does not address any block\n", unit->au_UnitNum));
718 break;
719 }
720
721 switch (block->method)
722 {
723 case CM_PIOWrite:
724 ata_IRQSetHandler(unit, &ata_IRQPIOWrite, mem, block->secmul << unit->au_SectorShift, block->length);
725 break;
726
727 case CM_PIORead:
728 ata_IRQSetHandler(unit, &ata_IRQPIORead, mem, block->secmul << unit->au_SectorShift, block->length);
729 break;
730
731 case CM_DMARead:
732 if (FALSE == dma_SetupPRDSize(unit, mem, block->length, TRUE))
733 return IOERR_ABORTED;
734 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
735 dma_StartDMA(unit);
736 break;
737
738 case CM_DMAWrite:
739 if (FALSE == dma_SetupPRDSize(unit, mem, block->length, FALSE))
740 return IOERR_ABORTED;
741 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
742 dma_StartDMA(unit);
743 break;
744
745 case CM_NoData:
746 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
747 break;
748
749 default:
750 return IOERR_NOCMD;
751 break;
752 };
753
754 /*
755 * send command now
756 * let drive propagate its signals
757 */
758 DATA(bug("[ATA%02ld] ata_exec_cmd: Sending command\n", unit->au_UnitNum));
759 ATA_OUT(block->command, ata_Command, port);
760 ata_WaitNano(400, bus->ab_Base);
761 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
762
763 /*
764 * In case of PIO write the drive won't issue an IRQ before first
765 * data transfer, so we should poll the status and send the first
766 * block upon request.
767 */
768 if (block->method == CM_PIOWrite)
769 {
770 if (FALSE == ata_WaitBusyTO(unit, TIMEOUT, FALSE, &status)) {
771 DERROR(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - no response from device. Status %02X\n", unit->au_UnitNum, status));
772 return IOERR_UNITBUSY;
773 }
774 if (status & ATAF_DATAREQ) {
775 DATA(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - DRQ.\n", unit->au_UnitNum));
776 ata_PIOWriteBlk(unit);
777 }
778 else
779 {
780 DERROR(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - bad status: %02X\n", status));
781 return HFERR_BadStatus;
782 }
783 }
784
785 /*
786 * wait for drive to complete what it has to do
787 */
788 if (FALSE == ata_WaitBusyTO(unit, TIMEOUT, TRUE, NULL))
789 {
790 DERROR(bug("[ATA%02ld] ata_exec_cmd: Device is late - no response\n", unit->au_UnitNum));
791 err = IOERR_UNITBUSY;
792 }
793 else
794 err = unit->au_cmd_error;
795
796 DATA(bug("[ATA%02ld] ata_exec_cmd: Command done\n", unit->au_UnitNum));
797 /*
798 * clean up DMA
799 * don't use 'mem' pointer here as it's already invalid.
800 */
801 if (block->method == CM_DMARead)
802 {
803 dma_StopDMA(unit);
804 dma_Cleanup(block->buffer, block->length, TRUE);
805 }
806 else if (block->method == CM_DMAWrite)
807 {
808 dma_StopDMA(unit);
809 dma_Cleanup(block->buffer, block->length, FALSE);
810 }
811
812 D(bug("[ATA%02ld] ata_exec_cmd: return code %ld\n", unit->au_UnitNum, err));
813 return err;
814 }
815
816 /*
817 * atapi packet iface
818 */
819 BYTE atapi_SendPacket(struct ata_Unit *unit, APTR packet, APTR data, LONG datalen, BOOL *dma, BOOL write)
820 {
821 struct ata_Bus *bus = unit->au_Bus;
822 *dma = *dma && (unit->au_XferModes & AF_XFER_DMA) ? TRUE : FALSE;
823 LONG err = 0;
824
825 UBYTE cmd[12] = {
826 0
827 };
828 register int t=5,l=0;
829 ULONG port = unit->au_Bus->ab_Port;
830
831 if (((UBYTE*)packet)[0] > 0x1f)
832 t+= 4;
833 if (((UBYTE*)packet)[0] > 0x5f)
834 t+= 2;
835
836 switch (((UBYTE*)packet)[0])
837 {
838 case 0x28: // read10
839 case 0xa8: // read12
840 case 0xbe: // readcd
841 case 0xb9: // readcdmsf
842 case 0x2f: // verify
843 case 0x2a: // write
844 case 0xaa: // write12
845 case 0x2e: // writeverify
846 case 0xad: // readdvdstructure
847 case 0xa4: // reportkey
848 case 0xa3: // sendkey
849 break;
850 default:
851 *dma = FALSE;
852 }
853
854 while (l<=t)
855 {
856 cmd[l] = ((UBYTE*)packet)[l];
857 ++l;
858 }
859
860 DATAPI({
861 bug("[ATA%02lx] Sending %s ATA packet: ", unit->au_UnitNum, (*dma) ? "DMA" : "PIO");
862 l=0;
863 while (l<=t)
864 {
865 bug("%02lx ", ((UBYTE*)cmd)[l]);
866 ++l;
867 }
868 bug("\n");
869
870 if (datalen & 1)
871 bug("[ATAPI] ERROR: DATA LENGTH NOT EVEN! Rounding Up! (%ld bytes requested)\n", datalen);
872 });
873
874 datalen = (datalen+1)&~1;
875
876 if (FALSE == ata_SelectUnit(unit))
877 {
878 DATAPI(bug("[ATAPI] WaitBusy failed at first check\n"));
879 return IOERR_UNITBUSY;
880 }
881
882 /*
883 * tell device whether we want to read or write and if we want a dma transfer
884 */
885 ATA_OUT(((*dma) ? 1 : 0) |
886 (((unit->au_Drive->id_DMADir & 0x8000) && !write) ? 4 : 0),
887 atapi_Features, port);
888 ATA_OUT((datalen & 0xff), atapi_ByteCntL, port);
889 ATA_OUT((datalen >> 8) & 0xff, atapi_ByteCntH, port);
890
891 /*
892 * once we're done with that, we can go ahead and inform device that we're about to send atapi packet
893 * after command is dispatched, we are obliged to give 400ns for the unit to parse command and set status
894 */
895 DATAPI(bug("[ATAPI] Issuing ATA_PACKET command.\n"));
896 ata_IRQSetHandler(unit, &ata_IRQNoData, 0, 0, 0);
897 ATA_OUT(ATA_PACKET, atapi_Command, port);
898 ata_WaitNano(400, bus->ab_Base);
899 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
900
901 ata_WaitBusyTO(unit, TIMEOUT, (unit->au_Drive->id_General & 0x60) == 0x20,
902 NULL);
903 if (0 == (ata_ReadStatus(unit->au_Bus) & ATAF_DATAREQ))
904 return HFERR_BadStatus;
905
906 /*
907 * setup appropriate hooks
908 */
909 if (datalen == 0)
910 ata_IRQSetHandler(unit, &ata_IRQNoData, 0, 0, 0);
911 else if (*dma)
912 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
913 else if (write)
914 ata_IRQSetHandler(unit, &ata_IRQPIOWriteAtapi, data, 0, datalen);
915 else
916 ata_IRQSetHandler(unit, &ata_IRQPIOReadAtapi, data, 0, datalen);
917
918 if (*dma)
919 {
920 DATAPI(bug("[ATAPI] Starting DMA\n"));
921 dma_StartDMA(unit);
922 }
923
924 DATAPI(bug("[ATAPI] Sending packet\n"));
925 unit->au_outs(cmd, unit->au_Bus->ab_Port, 12, unit->au_Bus->ab_DriverData);
926 ata_WaitNano(400, bus->ab_Base);
927 DATAPI(bug("[ATAPI] Status after packet: %lx\n",
928 ata_ReadAltStatus(unit->au_Bus)));
929
930 /*
931 * Wait for command to complete. Note that two interrupts will occur
932 * before we wake up if this is a PIO data transfer
933 */
934 if (ata_WaitTO(unit->au_Bus->ab_Timer, TIMEOUT, 0,
935 1 << unit->au_Bus->ab_SleepySignal) == 0)
936 {
937 DATAPI(bug("[DSCSI] Command timed out.\n"));
938 err = IOERR_UNITBUSY;
939 }
940 else
941 err = atapi_EndCmd(unit);
942
943 if (*dma)
944 {
945 dma_StopDMA(unit);
946 dma_Cleanup(data, datalen, !write);
947 }
948
949 DATAPI(bug("[ATAPI] IO error code %ld\n", err));
950 return err;
951 }
952
953 BYTE atapi_DirectSCSI(struct ata_Unit *unit, struct SCSICmd *cmd)
954 {
955 APTR buffer = cmd->scsi_Data;
956 ULONG length = cmd->scsi_Length;
957 BYTE err = 0;
958 BOOL dma = FALSE;
959
960 cmd->scsi_Actual = 0;
961
962 DATAPI(bug("[DSCSI] Sending packet!\n"));
963
964 /*
965 * setup DMA & push command
966 * it does not really mean we will use dma here btw
967 */
968 if ((unit->au_XferModes & AF_XFER_DMA) && (length !=0) && (buffer != 0))
969 {
970 dma = TRUE;
971 if ((cmd->scsi_Flags & SCSIF_READ) != 0)
972 {
973 if (FALSE == dma_SetupPRDSize(unit, buffer, length, TRUE))
974 dma = FALSE;
975 }
976 else
977 {
978 if (FALSE == dma_SetupPRDSize(unit, buffer, length, FALSE))
979 dma = FALSE;
980 }
981 }
982
983 err = atapi_SendPacket(unit, cmd->scsi_Command, cmd->scsi_Data, cmd->scsi_Length, &dma, (cmd->scsi_Flags & SCSIF_READ) == 0);
984
985 DUMP({ if (cmd->scsi_Data != 0) dump(cmd->scsi_Data, cmd->scsi_Length); });
986
987 /*
988 * on check condition - grab sense data
989 */
990 DATAPI(bug("[ATA%02lx] atapi_DirectSCSI: SCSI Flags: %02lx / Error: %ld\n", unit->au_UnitNum, cmd->scsi_Flags, err));
991 if ((err != 0) && (cmd->scsi_Flags & SCSIF_AUTOSENSE))
992 {
993 DATAPI(bug("[DSCSI] atapi_DirectSCSI: Packet Failed. Calling atapi_RequestSense\n"));
994 atapi_RequestSense(unit, cmd->scsi_SenseData, cmd->scsi_SenseLength);
995 DUMP(dump(cmd->scsi_SenseData, cmd->scsi_SenseLength));
996 }
997
998 return err;
999 }
1000
1001 /*
1002 * chops the large transfers into set of smaller transfers
1003 * specifically useful when requested transfer size is >256 sectors for 28bit commands
1004 */
1005 static BYTE ata_exec_blk(struct ata_Unit *unit, ata_CommandBlock *blk)
1006 {
1007 BYTE err = 0;
1008 ULONG part;
1009 ULONG max=256;
1010 ULONG count=blk->sectors;
1011
1012 if (blk->type == CT_LBA48)
1013 max <<= 8;
1014
1015 DATA(bug("[ATA%02ld] ata_exec_blk: Accessing %ld sectors starting from %x%08x\n", unit->au_UnitNum, count, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
1016 while ((count > 0) && (err == 0))
1017 {
1018 part = (count > max) ? max : count;
1019 blk->sectors = part;
1020 blk->length = part << unit->au_SectorShift;
1021
1022 DATA(bug("[ATA%02ld] Transfer of %ld sectors from %x%08x\n", unit->au_UnitNum, part, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
1023 err = ata_exec_cmd(unit, blk);
1024 DATA(bug("[ATA%02ld] ata_exec_blk: ata_exec_cmd returned %lx\n", unit->au_UnitNum, err));
1025
1026 blk->blk += part;
1027 blk->buffer = &((char*)blk->buffer)[part << unit->au_SectorShift];
1028 count -= part;
1029 }
1030 return err;
1031 }
1032
1033 /*
1034 * Initial device configuration that suits *all* cases
1035 */
1036 BOOL ata_init_unit(struct ata_Bus *bus, UBYTE u)
1037 {
1038 struct ata_Unit *unit=NULL;
1039
1040 DINIT(bug("[ATA ] ata_init_unit(%ld)\n", u));
1041
1042 unit = bus->ab_Units[u];
1043 if (NULL == unit)
1044 return FALSE;
1045
1046 unit->au_Bus = bus;
1047 unit->au_Drive = AllocPooled(bus->ab_Base->ata_MemPool, sizeof(struct DriveIdent));
1048 unit->au_UnitNum = bus->ab_BusNum << 1 | u; // b << 8 | u
1049 unit->au_DevMask = 0xa0 | (u << 4);
1050
1051 /*
1052 * 32-bit transfer routines are options.
1053 * If the bus doesn't support this, they will be NULLs.
1054 */
1055 if (bus->ab_Base->ata_32bit && bus->ab_Driver->ata_insl)
1056 {
1057 unit->au_ins = bus->ab_Driver->ata_insl;
1058 unit->au_outs = bus->ab_Driver->ata_outsl;
1059 }
1060 else
1061 {
1062 unit->au_ins = bus->ab_Driver->ata_insw;
1063 unit->au_outs = bus->ab_Driver->ata_outsw;
1064 }
1065 unit->au_SectorShift= 9; /* this really has to be set here. */
1066
1067 NEWLIST(&unit->au_SoftList);
1068
1069 /*
1070 * since the stack is always handled by caller
1071 * it's safe to stub all calls with one function
1072 */
1073 unit->au_Read32 = ata_STUB_IO32;
1074 unit->au_Read64 = ata_STUB_IO64;
1075 unit->au_Write32 = ata_STUB_IO32;
1076 unit->au_Write64 = ata_STUB_IO64;
1077 unit->au_Eject = ata_STUB;
1078 unit->au_DirectSCSI = ata_STUB_SCSI;
1079 unit->au_Identify = ata_STUB;
1080 return TRUE;
1081 }
1082
1083 BOOL ata_setup_unit(struct ata_Bus *bus, UBYTE u)
1084 {
1085 struct ata_Unit *unit=NULL;
1086
1087 /*
1088 * this stuff always goes along the same way
1089 * WARNING: NO INTERRUPTS AT THIS POINT!
1090 */
1091 DINIT(bug("[ATA ] ata_setup_unit(%ld,%ld)\n", bus->ab_BusNum, u));
1092
1093 unit = bus->ab_Units[u];
1094 if (NULL == unit)
1095 return FALSE;
1096
1097 ata_SelectUnit(unit);
1098
1099 if (unit->au_DMAPort != 0
1100 && (ATA_IN(dma_Status, unit->au_DMAPort) & 0x80) != 0)
1101 bug("[ATA%02ld] ata_setup_unit: WARNING: Controller only supports "
1102 "DMA on one bus at a time. DMAStatus=%lx\n", unit->au_UnitNum,
1103 ATA_IN(dma_Status, unit->au_DMAPort));
1104
1105 if (FALSE == ata_WaitBusyTO(unit, 1, FALSE, NULL))
1106 {
1107 DINIT(bug("[ATA%02ld] ata_setup_unit: ERROR: Drive not ready for use. Keeping functions stubbed\n", unit->au_UnitNum));
1108 FreePooled(bus->ab_Base->ata_MemPool, unit->au_Drive, sizeof(struct DriveIdent));
1109 unit->au_Drive = 0;
1110 return FALSE;
1111 }
1112
1113 switch (bus->ab_Dev[u])
1114 {
1115 /*
1116 * safe fallback settings
1117 */
1118 case DEV_SATAPI:
1119 case DEV_ATAPI:
1120 case DEV_SATA:
1121 case DEV_ATA:
1122 unit->au_Identify = ata_Identify;
1123 break;
1124
1125 default:
1126 DINIT(bug("[ATA%02ld] ata_setup_unit: Unsupported device %lx. All functions will remain stubbed.\n", unit->au_UnitNum, bus->ab_Dev[u]));
1127 FreePooled(bus->ab_Base->ata_MemPool, unit->au_Drive, sizeof(struct DriveIdent));
1128 unit->au_Drive = 0;
1129 return FALSE;
1130 }
1131
1132 DINIT(bug("[ATA ] ata_setup_unit: Enabling IRQs\n"));
1133 ATA_OUT(0x0, ata_AltControl, bus->ab_Alt);
1134
1135 /*
1136 * now make unit self diagnose
1137 */
1138 if (unit->au_Identify(unit) != 0)
1139 {
1140 FreePooled(bus->ab_Base->ata_MemPool, unit->au_Drive, sizeof(struct DriveIdent));
1141 unit->au_Drive = NULL;
1142 return FALSE;
1143 }
1144
1145 return TRUE;
1146 }
1147
1148 /*
1149 * ata[pi] identify
1150 */
1151 static void common_SetXferMode(struct ata_Unit* unit, ata_XferMode mode)
1152 {
1153 BOOL dma = FALSE;
1154 #if 0 // We can't set drive modes unless we also set the controller's timing registers
1155 UBYTE type=0;
1156 ata_CommandBlock acb =
1157 {
1158 ATA_SET_FEATURES,
1159 0x03,
1160 0x01,
1161 0x00,
1162 0x00,
1163 0x00,
1164 0x00,
1165 0x00,
1166 0x00,
1167 CM_NoData,
1168 CT_LBA28
1169 };
1170 #endif
1171 DINIT(bug("[ATA%02ld] common_SetXferMode: Trying to set mode %d\n", unit->au_UnitNum, mode));
1172
1173 if ((unit->au_DMAPort == 0) && (mode >= AB_XFER_MDMA0))
1174 {
1175 DINIT(bug("[ATA%02ld] common_SetXferMode: This controller does not own DMA port! Will set best PIO\n", unit->au_UnitNum));
1176 common_SetBestXferMode(unit);
1177 return;
1178 }
1179
1180 /*
1181 * first, ONLY for ATA devices, set new commands
1182 */
1183 if (0 == (unit->au_XferModes & AF_XFER_PACKET))
1184 {
1185 if ((mode >= AB_XFER_PIO0) && (mode <= AB_XFER_PIO4))
1186 {
1187 if ((!unit->au_Bus->ab_Base->ata_NoMulti) && (unit->au_XferModes & AF_XFER_RWMULTI))
1188 {
1189 ata_IRQSetHandler(unit, ata_IRQNoData, NULL, 0, 0);
1190 ATA_OUT(unit->au_Drive->id_RWMultipleSize & 0xFF, ata_Count, unit->au_Bus->ab_Port);
1191 ATA_OUT(ATA_SET_MULTIPLE, ata_Command, unit->au_Bus->ab_Port);
1192 ata_WaitBusyTO(unit, -1, TRUE, NULL);
1193
1194 unit->au_Read32 = ata_ReadMultiple32;
1195 unit->au_Write32 = ata_WriteMultiple32;
1196 if (unit->au_XferModes & AF_XFER_48BIT)
1197 {
1198 unit->au_Read64 = ata_ReadMultiple64;
1199 unit->au_Write64 = ata_WriteMultiple64;
1200 }
1201 }
1202 else
1203 {
1204 unit->au_Read32 = ata_ReadSector32;
1205 unit->au_Write32 = ata_WriteSector32;
1206 if (unit->au_XferModes & AF_XFER_48BIT)
1207 {
1208 unit->au_Read64 = ata_ReadSector64;
1209 unit->au_Write64 = ata_WriteSector64;
1210 }
1211 }
1212 }
1213 else if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_MDMA2))
1214 {
1215 unit->au_Read32 = ata_ReadDMA32;
1216 unit->au_Write32 = ata_WriteDMA32;
1217 if (unit->au_XferModes & AF_XFER_48BIT)
1218 {
1219 unit->au_Read64 = ata_ReadDMA64;
1220 unit->au_Write64 = ata_WriteDMA64;
1221 }
1222 }
1223 else if ((mode >= AB_XFER_UDMA0) && (mode <= AB_XFER_UDMA6))
1224 {
1225 unit->au_Read32 = ata_ReadDMA32;
1226 unit->au_Write32 = ata_WriteDMA32;
1227 if (unit->au_XferModes & AF_XFER_48BIT)
1228 {
1229 unit->au_Read64 = ata_ReadDMA64;
1230 unit->au_Write64 = ata_WriteDMA64;
1231 }
1232 }
1233 else
1234 {
1235 unit->au_Read32 = ata_ReadSector32;
1236 unit->au_Write32 = ata_WriteSector32;
1237 if (unit->au_XferModes & AF_XFER_48BIT)
1238 {
1239 unit->au_Read64 = ata_ReadSector64;
1240 unit->au_Write64 = ata_WriteSector64;
1241 }
1242 }
1243 }
1244
1245 #if 0 // We can't set drive modes unless we also set the controller's timing registers
1246 if ((mode >= AB_XFER_PIO0) && (mode <= AB_XFER_PIO4))
1247 {
1248 type = 8 + (mode - AB_XFER_PIO0);
1249 }
1250 else if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_MDMA2))
1251 {
1252 type = 32 + (mode - AB_XFER_MDMA0);
1253 dma=TRUE;
1254 }
1255 else if ((mode >= AB_XFER_UDMA0) && (mode <= AB_XFER_UDMA6))
1256 {
1257 type = 64 + (mode - AB_XFER_UDMA0);
1258 dma=TRUE;
1259 }
1260 else
1261 {
1262 type = 0;
1263 }
1264
1265 acb.sectors = type;
1266 if (0 != ata_exec_cmd(unit, &acb))
1267 {
1268 DINIT(bug("[ATA%02ld] common_SetXferMode: ERROR: Failed to apply new xfer mode.\n", unit->au_UnitNum));
1269 }
1270
1271 if (unit->au_DMAPort)
1272 {
1273 type = ATA_IN(dma_Status, unit->au_DMAPort);
1274 type &= 0x60;
1275 if (dma)
1276 {
1277 type |= 1 << (5 + (unit->au_UnitNum & 1));
1278 }
1279 else
1280 {
1281 type &= ~(1 << (5 + (unit->au_UnitNum & 1)));
1282 }
1283
1284 DINIT(bug("[DSCSI] common_SetXferMode: Trying to apply new DMA (%lx) status: %02lx (unit %ld)\n", unit->au_DMAPort, type, unit->au_UnitNum & 1));
1285
1286 ata_SelectUnit(unit);
1287 ATA_OUT(type, dma_Status, unit->au_DMAPort);
1288 if (type == (ATA_IN(dma_Status, unit->au_DMAPort) & 0x60))
1289 {
1290 DINIT(bug("[DSCSI] common_SetXferMode: New DMA Status: %02lx\n", type));
1291 }
1292 else
1293 {
1294 DINIT(bug("[DSCSI] common_SetXferMode: Failed to modify DMA state for this device\n"));
1295 dma = FALSE;
1296 }
1297 }
1298 #else
1299 if (mode >= AB_XFER_MDMA0)
1300 dma = TRUE;
1301 #endif
1302
1303 if (dma)
1304 unit->au_XferModes |= AF_XFER_DMA;
1305 else
1306 unit->au_XferModes &= ~AF_XFER_DMA;
1307 }
1308
1309 static void common_SetBestXferMode(struct ata_Unit* unit)
1310 {
1311 int iter;
1312 int max = AB_XFER_UDMA6;
1313
1314 if (unit->au_Bus->ab_Base->ata_NoDMA || (unit->au_DMAPort == 0)
1315 || ( !(unit->au_Drive->id_MWDMASupport & 0x0700)
1316 && !(unit->au_Drive->id_UDMASupport & 0x7f00)))
1317 {
1318 /*
1319 * make sure you reduce scan search to pio here!
1320 * otherwise this and above function will fall into infinite loop
1321 */
1322 DINIT(bug("[ATA%02ld] common_SetBestXferMode: DMA is disabled for"
1323 " this drive.\n", unit->au_UnitNum));
1324 max = AB_XFER_PIO4;
1325 }
1326 else if (!(unit->au_Flags & AF_80Wire))
1327 {
1328 DINIT(bug("[ATA%02ld] common_SetBestXferMode: "
1329 "An 80-wire cable has not been detected for this drive. "
1330 "Disabling modes above UDMA2.\n", unit->au_UnitNum));
1331 max = AB_XFER_UDMA2;
1332 }
1333
1334 for (iter=max; iter>=AB_XFER_PIO0; --iter)
1335 {
1336 if (unit->au_XferModes & (1<<iter))
1337 {
1338 common_SetXferMode(unit, iter);
1339 return;
1340 }
1341 }
1342 bug("[ATA%02ld] common_SetBestXferMode: ERROR: device never reported any valid xfer modes. will continue at default\n", unit->au_UnitNum);
1343 common_SetXferMode(unit, AB_XFER_PIO0);
1344 }
1345
1346 void common_DetectXferModes(struct ata_Unit* unit)
1347 {
1348 int iter;
1349
1350 DINIT(bug("[ATA%02ld] common_DetectXferModes: Supports\n", unit->au_UnitNum));
1351
1352 if (unit->au_Drive->id_Commands4 & (1 << 4))
1353 {
1354 DINIT(bug("[ATA%02ld] common_DetectXferModes: - Packet interface\n", unit->au_UnitNum));
1355 unit->au_XferModes |= AF_XFER_PACKET;
1356 unit->au_DirectSCSI = atapi_DirectSCSI;
1357 }
1358 else if (unit->au_Drive->id_Commands5 & (1 << 10))
1359 {
1360 /* ATAPI devices do not use this bit. */
1361 DINIT(bug("[ATA%02ld] common_DetectXferModes: - 48bit I/O\n", unit->au_UnitNum));
1362 unit->au_XferModes |= AF_XFER_48BIT;
1363 }
1364
1365 if ((unit->au_XferModes & AF_XFER_PACKET) || (unit->au_Drive->id_Capabilities & (1<< 9)))
1366 {
1367 DINIT(bug("[ATA%02ld] common_DetectXferModes: - LBA Addressing\n", unit->au_UnitNum));
1368 unit->au_XferModes |= AF_XFER_LBA;
1369 }
1370 else
1371 {
1372 DINIT(bug("[ATA%02ld] common_DetectXferModes: - DEVICE DOES NOT SUPPORT LBA ADDRESSING >> THIS IS A POTENTIAL PROBLEM <<\n", unit->au_UnitNum));
1373 }
1374
1375 if (unit->au_Drive->id_RWMultipleSize & 0xff)
1376 {
1377 DINIT(bug("[ATA%02ld] common_DetectXferModes: - R/W Multiple (%ld sectors per xfer)\n", unit->au_UnitNum, unit->au_Drive->id_RWMultipleSize & 0xff));
1378 unit->au_XferModes |= AF_XFER_RWMULTI;
1379 }
1380
1381 DINIT(bug("[ATA%02ld] common_DetectXferModes: - PIO0 PIO1 PIO2 ",
1382 unit->au_UnitNum));
1383 unit->au_XferModes |= AF_XFER_PIO(0) | AF_XFER_PIO(1) | AF_XFER_PIO(2);
1384 if (unit->au_Drive->id_ConfigAvailable & (1 << 1))
1385 {
1386 for (iter = 0; iter < 2; iter++)
1387 {
1388 if (unit->au_Drive->id_PIOSupport & (1 << iter))
1389 {
1390 DINIT(bug("PIO%ld ", 3 + iter));
1391 unit->au_XferModes |= AF_XFER_PIO(3 + iter);
1392 }
1393 }
1394 DINIT(bug("\n"));
1395 }
1396
1397 if ((unit->au_Drive->id_ConfigAvailable & (1 << 1)) &&
1398 (unit->au_Drive->id_Capabilities & (1<<8)))
1399 {
1400 DINIT(bug("[ATA%02ld] common_DetectXferModes: DMA:\n", unit->au_UnitNum));
1401 if (unit->au_Drive->id_MWDMASupport & 0xff)
1402 {
1403 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1404 for (iter = 0; iter < 3; iter++)
1405 {
1406 if (unit->au_Drive->id_MWDMASupport & (1 << iter))
1407 {
1408 unit->au_XferModes |= AF_XFER_MDMA(iter);
1409 if (unit->au_Drive->id_MWDMASupport & (256 << iter))
1410 {
1411 DINIT(bug("[MDMA%ld] ", iter));
1412 }
1413 else
1414 {
1415 DINIT(bug("MDMA%ld ", iter));
1416 }
1417 }
1418 }
1419 DINIT(bug("\n"));
1420 }
1421
1422 if (unit->au_Drive->id_UDMASupport & 0xff)
1423 {
1424 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1425 for (iter = 0; iter < 7; iter++)
1426 {
1427 if (unit->au_Drive->id_UDMASupport & (1 << iter))
1428 {
1429 unit->au_XferModes |= AF_XFER_UDMA(iter);
1430 if (unit->au_Drive->id_UDMASupport & (256 << iter))
1431 {
1432 DINIT(bug("[UDMA%ld] ", iter));
1433 }
1434 else
1435 {
1436 DINIT(bug("UDMA%ld ", iter));
1437 }
1438 }
1439 }
1440 DINIT(bug("\n"));
1441 }
1442 }
1443 }
1444
1445 #define SWAP_LE_WORD(x) (x) = AROS_LE2WORD((x))
1446 #define SWAP_LE_LONG(x) (x) = AROS_LE2LONG((x))
1447 #define SWAP_LE_QUAD(x) (x) = AROS_LE2LONG((x) >> 32) | (((QUAD)(AROS_LE2LONG((x) & 0xffffffff))) << 32)
1448
1449 BYTE ata_Identify(struct ata_Unit* unit)
1450 {
1451 BOOL atapi = unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] & 0x80;
1452 ata_CommandBlock acb =
1453 {
1454 atapi ? ATA_IDENTIFY_ATAPI : ATA_IDENTIFY_DEVICE,
1455 0,
1456 1,
1457 0,
1458 0,
1459 0,
1460 unit->au_Drive,
1461 sizeof(struct DriveIdent),
1462 0,
1463 CM_PIORead,
1464 CT_NoBlock
1465 };
1466
1467 /* If the right command fails, try the wrong one. If both fail, abort */
1468 DINIT(bug("[ATA%02ld] ata_Identify: Executing ATA_IDENTIFY_%s command\n",
1469 unit->au_UnitNum, atapi ? "ATAPI" : "DEVICE"));
1470 if (ata_exec_cmd(unit, &acb))
1471 {
1472 acb.command = atapi ? ATA_IDENTIFY_DEVICE : ATA_IDENTIFY_ATAPI;
1473 DINIT(bug("[ATA%02ld] ata_Identify: Executing ATA_IDENTIFY_%s command"
1474 " instead\n", unit->au_UnitNum, atapi ? "DEVICE" : "ATAPI"));
1475 if (ata_exec_cmd(unit, &acb))
1476 {
1477 DINIT(bug("[ATA%02ld] ata_Identify: Both command variants failed\n",
1478 unit->au_UnitNum));
1479 return IOERR_OPENFAIL;
1480 }
1481 unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] ^= 0x82;
1482 atapi = unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] & 0x80;
1483 DINIT(bug("[ATA%02ld] ata_Identify:"
1484 " Incorrect device signature detected."
1485 " Switching device type to %lx.\n", unit->au_UnitNum,
1486 unit->au_Bus->ab_Dev[unit->au_UnitNum & 1]));
1487 }
1488
1489 /*
1490 * If every second word is zero with 32-bit reads, switch to 16-bit
1491 * accesses for this drive and try again
1492 */
1493 if (unit->au_Bus->ab_Base->ata_32bit)
1494 {
1495 UWORD n = 0, *p, *limit;
1496
1497 for (p = (UWORD *)unit->au_Drive, limit = p + 256; p < limit; p++)
1498 n |= *++p;
1499
1500 if (n == 0)
1501 {
1502 DINIT(bug("[ATA%02ld] Identify data was invalid with 32-bit reads."
1503 " Switching to 16-bit mode.\n", unit->au_UnitNum));
1504
1505 unit->au_ins = unit->au_Bus->ab_Driver->ata_insw;
1506 unit->au_outs = unit->au_Bus->ab_Driver->ata_outsw;
1507
1508 if (ata_exec_cmd(unit, &acb))
1509 return IOERR_OPENFAIL;
1510 }
1511 }
1512
1513 #if (AROS_BIG_ENDIAN != 0)
1514 SWAP_LE_WORD(unit->au_Drive->id_General);
1515 SWAP_LE_WORD(unit->au_Drive->id_OldCylinders);
1516 SWAP_LE_WORD(unit->au_Drive->id_SpecificConfig);
1517 SWAP_LE_WORD(unit->au_Drive->id_OldHeads);
1518 SWAP_LE_WORD(unit->au_Drive->id_OldSectors);
1519 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleSize);
1520 SWAP_LE_WORD(unit->au_Drive->id_Capabilities);
1521 SWAP_LE_WORD(unit->au_Drive->id_OldCaps);
1522 SWAP_LE_WORD(unit->au_Drive->id_OldPIO);
1523 SWAP_LE_WORD(unit->au_Drive->id_ConfigAvailable);
1524 SWAP_LE_WORD(unit->au_Drive->id_OldLCylinders);
1525 SWAP_LE_WORD(unit->au_Drive->id_OldLHeads);
1526 SWAP_LE_WORD(unit->au_Drive->id_OldLSectors);
1527 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleTrans);
1528 SWAP_LE_WORD(unit->au_Drive->id_MWDMASupport);
1529 SWAP_LE_WORD(unit->au_Drive->id_PIOSupport);
1530 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_MinCycleTime);
1531 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_DefCycleTime);
1532 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTime);
1533 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTImeIORDY);
1534 SWAP_LE_WORD(unit->au_Drive->id_QueueDepth);
1535 SWAP_LE_WORD(unit->au_Drive->id_ATAVersion);
1536 SWAP_LE_WORD(unit->au_Drive->id_ATARevision);
1537 SWAP_LE_WORD(unit->au_Drive->id_Commands1);
1538 SWAP_LE_WORD(unit->au_Drive->id_Commands2);
1539 SWAP_LE_WORD(unit->au_Drive->id_Commands3);
1540 SWAP_LE_WORD(unit->au_Drive->id_Commands4);
1541 SWAP_LE_WORD(unit->au_Drive->id_Commands5);
1542 SWAP_LE_WORD(unit->au_Drive->id_Commands6);
1543 SWAP_LE_WORD(unit->au_Drive->id_UDMASupport);
1544 SWAP_LE_WORD(unit->au_Drive->id_SecurityEraseTime);
1545 SWAP_LE_WORD(unit->au_Drive->id_ESecurityEraseTime);
1546 SWAP_LE_WORD(unit->au_Drive->id_CurrentAdvPowerMode);
1547 SWAP_LE_WORD(unit->au_Drive->id_MasterPwdRevision);
1548 SWAP_LE_WORD(unit->au_Drive->id_HWResetResult);
1549 SWAP_LE_WORD(unit->au_Drive->id_AcousticManagement);
1550 SWAP_LE_WORD(unit->au_Drive->id_StreamMinimunReqSize);
1551 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimeDMA);
1552 SWAP_LE_WORD(unit->au_Drive->id_StreamingLatency);
1553 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimePIO);
1554 SWAP_LE_WORD(unit->au_Drive->id_PhysSectorSize);
1555 SWAP_LE_WORD(unit->au_Drive->id_RemMediaStatusNotificationFeatures);
1556 SWAP_LE_WORD(unit->au_Drive->id_SecurityStatus);
1557
1558 SWAP_LE_LONG(unit->au_Drive->id_WordsPerLogicalSector);
1559 SWAP_LE_LONG(unit->au_Drive->id_LBASectors);
1560 SWAP_LE_LONG(unit->au_Drive->id_StreamingGranularity);
1561
1562 SWAP_LE_QUAD(unit->au_Drive->id_LBA48Sectors);
1563 #endif
1564
1565 DUMP(dump(unit->au_Drive, sizeof(struct DriveIdent)));
1566
1567 if (atapi)
1568 {
1569 unit->au_SectorShift = 11;
1570 unit->au_Read32 = atapi_Read;
1571 unit->au_Write32 = atapi_Write;
1572 unit->au_DirectSCSI = atapi_DirectSCSI;
1573 unit->au_Eject = atapi_Eject;
1574 unit->au_Flags |= AF_DiscChanged;
1575 unit->au_DevType = (unit->au_Drive->id_General >>8) & 0x1f;
1576 unit->au_XferModes = AF_XFER_PACKET;
1577 }
1578 else
1579 {
1580 unit->au_SectorShift = 9;
1581 unit->au_DevType = DG_DIRECT_ACCESS;
1582 unit->au_Read32 = ata_ReadSector32;
1583 unit->au_Write32 = ata_WriteSector32;
1584 unit->au_Eject = ata_Eject;
1585 unit->au_XferModes = 0;
1586 unit->au_Flags |= AF_DiscPresent | AF_DiscChanged;
1587 }
1588
1589 ata_strcpy(unit->au_Drive->id_Model, unit->au_Model, 40);
1590 ata_strcpy(unit->au_Drive->id_SerialNumber, unit->au_SerialNumber, 20);
1591 ata_strcpy(unit->au_Drive->id_FirmwareRev, unit->au_FirmwareRev, 8);
1592
1593 bug("[ATA%02ld] ata_Identify: Unit info: %s / %s / %s\n", unit->au_UnitNum, unit->au_Model, unit->au_SerialNumber, unit->au_FirmwareRev);
1594 common_DetectXferModes(unit);
1595 common_SetBestXferMode(unit);
1596
1597 if (unit->au_Drive->id_General & 0x80)
1598 {
1599 DINIT(bug("[ATA%02ld] ata_Identify: Device is removable.\n", unit->au_UnitNum));
1600 unit->au_Flags |= AF_Removable;
1601 }
1602
1603 unit->au_Capacity = unit->au_Drive->id_LBASectors;
1604 unit->au_Capacity48 = unit->au_Drive->id_LBA48Sectors;
1605 bug("[ATA%02ld] ata_Identify: Unit info: %07lx 28bit / %04lx:%08lx 48bit addressable blocks\n", unit->au_UnitNum, unit->au_Capacity, (ULONG)(unit->au_Capacity48 >> 32), (ULONG)(unit->au_Capacity48 & 0xfffffffful));
1606
1607 if (atapi)
1608 {
1609 /*
1610 * ok, this is not very original, but quite compatible :P
1611 */
1612 switch (unit->au_DevType)
1613 {
1614 case DG_CDROM:
1615 case DG_WORM:
1616 case DG_OPTICAL_DISK:
1617 unit->au_SectorShift = 11;
1618 unit->au_Heads = 1;
1619 unit->au_Sectors = 75;
1620 unit->au_Cylinders = 4440;
1621 break;
1622
1623 case DG_DIRECT_ACCESS:
1624 unit->au_SectorShift = 9;
1625 if (!strcmp("LS-120", &unit->au_Model[0]))
1626 {
1627 unit->au_Heads = 2;
1628 unit->au_Sectors = 18;
1629 unit->au_Cylinders = 6848;
1630 }
1631 else if (!strcmp("ZIP 100 ", &unit->au_Model[8]))
1632 {
1633 unit->au_Heads = 1;
1634 unit->au_Sectors = 64;
1635 unit->au_Cylinders = 3072;
1636 }
1637 break;
1638 }
1639
1640 atapi_TestUnitOK(unit);
1641 }
1642 else
1643 {
1644 /*
1645 For drive capacities > 8.3GB assume maximal possible layout.
1646 It really doesn't matter here, as BIOS will not handle them in
1647 CHS way anyway :)
1648 i guess this just solves that weirdo div-by-zero crash, if nothing
1649 else...
1650 */
1651 if ((unit->au_Drive->id_LBA48Sectors > (63 * 255 * 1024)) ||
1652 (unit->au_Drive->id_LBASectors > (63 * 255 * 1024)))
1653 {
1654 ULONG div = 1;
1655 /*
1656 * TODO: this shouldn't be casted down here.
1657 */
1658 ULONG sec = unit->au_Capacity48;
1659
1660 if (sec < unit->au_Capacity48)
1661 sec = ~((ULONG)0);
1662
1663 if (sec < unit->au_Capacity)
1664 sec = unit->au_Capacity;
1665
1666 unit->au_Sectors = 63;
1667 sec /= 63;
1668 /*
1669 * keep dividing by 2
1670 */
1671 do
1672 {
1673 if (((sec >> 1) << 1) != sec)
1674 break;
1675 if ((div << 1) > 255)
1676 break;
1677 div <<= 1;
1678 sec >>= 1;
1679 } while (1);
1680
1681 do
1682 {
1683 if (((sec / 3) * 3) != sec)
1684 break;
1685 if ((div * 3) > 255)
1686 break;
1687 div *= 3;
1688 sec /= 3;
1689 } while (1);
1690
1691 unit->au_Cylinders = sec;
1692 unit->au_Heads = div;
1693 }
1694 else
1695 {
1696 unit->au_Cylinders = unit->au_Drive->id_OldLCylinders;
1697 unit->au_Heads = unit->au_Drive->id_OldLHeads;
1698 unit->au_Sectors = unit->au_Drive->id_OldLSectors;
1699 }
1700 }
1701
1702 return 0;
1703 }
1704
1705 /*
1706 * ata read32 commands
1707 */
1708 static BYTE ata_ReadSector32(struct ata_Unit *unit, ULONG block,
1709 ULONG count, APTR buffer, ULONG *act)
1710 {
1711 ata_CommandBlock acb =
1712 {
1713 ATA_READ,
1714 0,
1715 1,
1716 0,
1717 block,
1718 count,
1719 buffer,
1720 count << unit->au_SectorShift,
1721 0,
1722 CM_PIORead,
1723 CT_LBA28
1724 };
1725 BYTE err;
1726
1727 D(bug("[ATA%02ld] ata_ReadSector32()\n", unit->au_UnitNum));
1728
1729 *act = 0;
1730 if (0 != (err = ata_exec_blk(unit, &acb)))
1731 return err;
1732
1733 *act = count << unit->au_SectorShift;
1734 return 0;
1735 }
1736
1737 static BYTE ata_ReadMultiple32(struct ata_Unit *unit, ULONG block,
1738 ULONG count, APTR buffer, ULONG *act)
1739 {
1740 ata_CommandBlock acb =
1741 {
1742 ATA_READ_MULTIPLE,
1743 0,
1744 unit->au_Drive->id_RWMultipleSize & 0xff,
1745 0,
1746 block,
1747 count,
1748 buffer,
1749 count << unit->au_SectorShift,
1750 0,
1751 CM_PIORead,
1752 CT_LBA28
1753 };
1754 BYTE err;
1755
1756 D(bug("[ATA%02ld] ata_ReadMultiple32()\n", unit->au_UnitNum));
1757
1758 *act = 0;
1759 if (0 != (err = ata_exec_blk(unit, &acb)))
1760 return err;
1761
1762 *act = count << unit->au_SectorShift;
1763 return 0;
1764 }
1765
1766 static BYTE ata_ReadDMA32(struct ata_Unit *unit, ULONG block,
1767 ULONG count, APTR buffer, ULONG *act)
1768 {
1769 BYTE err;
1770 ata_CommandBlock acb =
1771 {
1772 ATA_READ_DMA,
1773 0,
1774 1,
1775 0,
1776 block,
1777 count,
1778 buffer,
1779 count << unit->au_SectorShift,
1780 0,
1781 CM_DMARead,
1782 CT_LBA28
1783 };
1784
1785 D(bug("[ATA%02ld] ata_ReadDMA32()\n", unit->au_UnitNum));
1786
1787 *act = 0;
1788 if (0 != (err = ata_exec_blk(unit, &acb)))
1789 return err;
1790
1791 *act = count << unit->au_SectorShift;
1792 return 0;
1793 }
1794
1795 /*
1796 * ata read64 commands
1797 */
1798 static BYTE ata_ReadSector64(struct ata_Unit *unit, UQUAD block,
1799 ULONG count, APTR buffer, ULONG *act)
1800 {
1801 ata_CommandBlock acb =
1802 {
1803 ATA_READ64,
1804 0,
1805 1,
1806 0,
1807 block,
1808 count,
1809 buffer,
1810 count << unit->au_SectorShift,
1811 0,
1812 CM_PIORead,
1813 CT_LBA48
1814 };
1815 BYTE err = 0;
1816
1817 D(bug("[ATA%02ld] ata_ReadSector64()\n", unit->au_UnitNum));
1818
1819 *act = 0;
1820 if (0 != (err = ata_exec_blk(unit, &acb)))
1821 return err;
1822
1823 *act = count << unit->au_SectorShift;
1824 return 0;
1825 }
1826
1827 static BYTE ata_ReadMultiple64(struct ata_Unit *unit, UQUAD block,
1828 ULONG count, APTR buffer, ULONG *act)
1829 {
1830 ata_CommandBlock acb =
1831 {
1832 ATA_READ_MULTIPLE64,
1833 0,
1834 unit->au_Drive->id_RWMultipleSize & 0xff,
1835 0,
1836 block,
1837 count,
1838 buffer,
1839 count << unit->au_SectorShift,
1840 0,
1841 CM_PIORead,
1842 CT_LBA48
1843 };
1844 BYTE err;
1845
1846 D(bug("[ATA%02ld] ata_ReadMultiple64()\n", unit->au_UnitNum));
1847
1848 *act = 0;
1849 if (0 != (err = ata_exec_blk(unit, &acb)))
1850 return err;
1851
1852 *act = count << unit->au_SectorShift;
1853 return 0;
1854 }
1855
1856 static BYTE ata_ReadDMA64(struct ata_Unit *unit, UQUAD block,
1857 ULONG count, APTR buffer, ULONG *act)
1858 {
1859 ata_CommandBlock acb =
1860 {
1861 ATA_READ_DMA64,
1862 0,
1863 1,
1864 0,
1865 block,
1866 count,
1867 buffer,
1868 count << unit->au_SectorShift,
1869 0,
1870 CM_DMARead,
1871 CT_LBA48
1872 };
1873 BYTE err;
1874
1875 D(bug("[ATA%02ld] ata_ReadDMA64()\n", unit->au_UnitNum));
1876
1877 *act = 0;
1878 if (0 != (err = ata_exec_blk(unit, &acb)))
1879 return err;
1880
1881 *act = count << unit->au_SectorShift;
1882 return 0;
1883 }
1884
1885 /*
1886 * ata write32 commands
1887 */
1888 static BYTE ata_WriteSector32(struct ata_Unit *unit, ULONG block,
1889 ULONG count, APTR buffer, ULONG *act)
1890 {
1891 ata_CommandBlock acb =
1892 {
1893 ATA_WRITE,
1894 0,
1895 1,
1896 0,
1897 block,
1898 count,
1899 buffer,
1900 count << unit->au_SectorShift,
1901 0,
1902 CM_PIOWrite,
1903 CT_LBA28
1904 };
1905 BYTE err;
1906
1907 D(bug("[ATA%02ld] ata_WriteSector32()\n", unit->au_UnitNum));
1908
1909 *act = 0;
1910 if (0 != (err = ata_exec_blk(unit, &acb)))
1911 return err;
1912
1913 *act = count << unit->au_SectorShift;
1914 return 0;
1915 }
1916
1917 static BYTE ata_WriteMultiple32(struct ata_Unit *unit, ULONG block,
1918 ULONG count, APTR buffer, ULONG *act)
1919 {
1920 ata_CommandBlock acb =
1921 {
1922 ATA_WRITE_MULTIPLE,
1923 0,
1924 unit->au_Drive->id_RWMultipleSize & 0xff,
1925 0,
1926 block,
1927 count,
1928 buffer,
1929 count << unit->au_SectorShift,
1930 0,
1931 CM_PIOWrite,
1932 CT_LBA28
1933 };
1934 BYTE err;
1935
1936 D(bug("[ATA%02ld] ata_WriteMultiple32()\n", unit->au_UnitNum));
1937
1938 *act = 0;
1939 if (0 != (err = ata_exec_blk(unit, &acb)))
1940 return err;
1941
1942 *act = count << unit->au_SectorShift;
1943 return 0;
1944 }
1945
1946 static BYTE ata_WriteDMA32(struct ata_Unit *unit, ULONG block,
1947 ULONG count, APTR buffer, ULONG *act)
1948 {
1949 ata_CommandBlock acb =
1950 {
1951 ATA_WRITE_DMA,
1952 0,
1953 1,
1954 0,
1955 block,
1956 count,
1957 buffer,
1958 count << unit->au_SectorShift,
1959 0,
1960 CM_DMAWrite,
1961 CT_LBA28
1962 };
1963 BYTE err;
1964
1965 D(bug("[ATA%02ld] ata_WriteDMA32()\n", unit->au_UnitNum));
1966
1967 *act = 0;
1968 if (0 != (err = ata_exec_blk(unit, &acb)))
1969 return err;
1970
1971 *act = count << unit->au_SectorShift;
1972 return 0;
1973 }
1974
1975 /*
1976 * ata write64 commands
1977 */
1978 static BYTE ata_WriteSector64(struct ata_Unit *unit, UQUAD block,
1979 ULONG count, APTR buffer, ULONG *act)
1980 {
1981 ata_CommandBlock acb =
1982 {
1983 ATA_WRITE64,
1984 0,
1985 1,
1986 0,
1987 block,
1988 count,
1989 buffer,
1990 count << unit->au_SectorShift,
1991 0,
1992 CM_PIOWrite,
1993 CT_LBA48
1994 };
1995 BYTE err;
1996
1997 D(bug("[ATA%02ld] ata_WriteSector64()\n", unit->au_UnitNum));
1998
1999 *act = 0;
2000 if (0 != (err = ata_exec_blk(unit, &acb)))
2001 return err;
2002
2003 *act = count << unit->au_SectorShift;
2004 return 0;
2005 }
2006
2007 static BYTE ata_WriteMultiple64(struct ata_Unit *unit, UQUAD block,
2008 ULONG count, APTR buffer, ULONG *act)
2009 {
2010 ata_CommandBlock acb =
2011 {
2012 ATA_WRITE_MULTIPLE64,
2013 0,
2014 unit->au_Drive->id_RWMultipleSize & 0xff,
2015 0,
2016 block,
2017 count,
2018 buffer,
2019 count << unit->au_SectorShift,
2020 0,
2021 CM_PIOWrite,
2022 CT_LBA48
2023 };
2024 BYTE err;
2025
2026 D(bug("[ATA%02ld] ata_WriteMultiple64()\n", unit->au_UnitNum));
2027
2028 *act = 0;
2029 if (0 != (err = ata_exec_blk(unit, &acb)))
2030 return err;
2031
2032 *act = count << unit->au_SectorShift;
2033 return 0;
2034 }
2035
2036 static BYTE ata_WriteDMA64(struct ata_Unit *unit, UQUAD block,
2037 ULONG count, APTR buffer, ULONG *act)
2038 {
2039 ata_CommandBlock acb =
2040 {
2041 ATA_WRITE_DMA64,
2042 0,
2043 1,
2044 0,
2045 block,
2046 count,
2047 buffer,
2048 count << unit->au_SectorShift,
2049 0,
2050 CM_DMAWrite,
2051 CT_LBA48
2052 };
2053 BYTE err;
2054
2055 D(bug("[ATA%02ld] ata_WriteDMA64()\n", unit->au_UnitNum));
2056
2057 *act = 0;
2058 if (0 != (err = ata_exec_blk(unit, &acb)))
2059 return err;
2060
2061 *act = count << unit->au_SectorShift;
2062 return 0;
2063 }
2064
2065 /*
2066 * ata miscellaneous commands
2067 */
2068 static BYTE ata_Eject(struct ata_Unit *unit)
2069 {
2070 ata_CommandBlock acb =
2071 {
2072 ATA_MEDIA_EJECT,
2073 0,
2074 0,
2075 0,
2076 0,
2077 0,
2078 0,
2079 0,
2080 0,
2081 CM_NoData,
2082 CT_NoBlock
2083 };
2084
2085 D(bug("[ATA%02ld] ata_Eject()\n", unit->au_UnitNum));
2086
2087 return ata_exec_cmd(unit, &acb);
2088 }
2089
2090 /*
2091 * atapi commands
2092 */
2093 int atapi_TestUnitOK(struct ata_Unit *unit)
2094 {
2095 UBYTE cmd[6] = {
2096 0
2097 };
2098 UBYTE sense[16] = {
2099 0
2100 };
2101 struct SCSICmd sc = {
2102 0
2103 };
2104
2105 D(bug("[ATA%02ld] atapi_TestUnitOK()\n", unit->au_UnitNum));
2106
2107 sc.scsi_Command = (void*) &cmd;
2108 sc.scsi_CmdLength = sizeof(cmd);
2109 sc.scsi_SenseData = (void*)&sense;
2110 sc.scsi_SenseLength = sizeof(sense);
2111 sc.scsi_Flags = SCSIF_AUTOSENSE;
2112
2113 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Testing Unit Ready sense...\n", unit->au_UnitNum));
2114 unit->au_DirectSCSI(unit, &sc);
2115 unit->au_SenseKey = sense[2];
2116
2117 /*
2118 * we may have just lost the disc...?
2119 */
2120 /*
2121 * per MMC, drives are expected to return 02-3a-0# status, when disc is not present
2122 * that would translate into following code:
2123 * int p1 = ((sense[2] == 2) && (sense[12] == 0x3a)) ? 1 : 0;
2124 * unfortunately, it's what MMC says, not what vendors code.
2125 */
2126 int p1 = (sense[2] == 2) ? 1 : 0;
2127 int p2 = (0 != (AF_DiscPresent & unit->au_Flags)) ? 1 : 0;
2128
2129 if (p1 == p2)
2130 {
2131 //unit->au_Flags ^= AF_DiscPresent;
2132 if (p1 == 0)
2133 unit->au_Flags |= AF_DiscPresent;
2134 else
2135 unit->au_Flags &= ~AF_DiscPresent;
2136
2137 unit->au_Flags |= AF_DiscChanged;
2138 }
2139
2140 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Test Unit Ready sense: %02lx, Media %s\n", unit->au_UnitNum, sense[2], unit->au_Flags & AF_DiscPresent ? "PRESENT" : "ABSENT"));
2141 return sense[2];
2142 }
2143
2144 static BYTE atapi_Read(struct ata_Unit *unit, ULONG block, ULONG count,
2145 APTR buffer, ULONG *act)
2146 {
2147 UBYTE cmd[] = {
2148 SCSI_READ10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
2149 };
2150 struct SCSICmd sc = {
2151 0
2152 };
2153
2154 D(bug("[ATA%02ld] atapi_Read()\n", unit->au_UnitNum));
2155
2156 sc.scsi_Command = (void*) &cmd;
2157 sc.scsi_CmdLength = sizeof(cmd);
2158 sc.scsi_Data = buffer;
2159 sc.scsi_Length = count << unit->au_SectorShift;
2160 sc.scsi_Flags = SCSIF_READ;
2161
2162 return unit->au_DirectSCSI(unit, &sc);
2163 }
2164
2165 static BYTE atapi_Write(struct ata_Unit *unit, ULONG block, ULONG count,
2166 APTR buffer, ULONG *act)
2167 {
2168 UBYTE cmd[] = {
2169 SCSI_WRITE10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
2170 };
2171 struct SCSICmd sc = {
2172 0
2173 };
2174
2175 D(bug("[ATA%02ld] atapi_Write()\n", unit->au_UnitNum));
2176
2177 sc.scsi_Command = (void*) &cmd;
2178 sc.scsi_CmdLength = sizeof(cmd);
2179 sc.scsi_Data = buffer;
2180 sc.scsi_Length = count << unit->au_SectorShift;
2181 sc.scsi_Flags = SCSIF_WRITE;
2182
2183 return unit->au_DirectSCSI(unit, &sc);
2184 }
2185
2186 static BYTE atapi_Eject(struct ata_Unit *unit)
2187 {
2188 struct atapi_StartStop cmd = {
2189 command: SCSI_STARTSTOP,
2190 immediate: 1,
2191 flags: ATAPI_SS_EJECT,
2192 };
2193
2194 struct SCSICmd sc = {
2195 0
2196 };
2197
2198 D(bug("[ATA%02ld] atapi_Eject()\n", unit->au_UnitNum));
2199
2200 sc.scsi_Command = (void*) &cmd;
2201 sc.scsi_CmdLength = sizeof(cmd);
2202 sc.scsi_Flags = SCSIF_READ;
2203
2204 return unit->au_DirectSCSI(unit, &sc);
2205 }
2206
2207 ULONG atapi_RequestSense(struct ata_Unit* unit, UBYTE* sense, ULONG senselen)
2208 {
2209 UBYTE cmd[] = {
2210 3, 0, 0, 0, senselen & 0xfe, 0
2211 };
2212 struct SCSICmd sc = {
2213 0
2214 };
2215
2216 D(bug("[ATA%02ld] atapi_RequestSense()\n", unit->au_UnitNum));
2217
2218 if ((senselen == 0) || (sense == 0))
2219 {
2220 return 0;
2221 }
2222 sc.scsi_Data = (void*)sense;
2223 sc.scsi_Length = senselen & 0xfe;
2224 sc.scsi_Command = (void*)&cmd;
2225 sc.scsi_CmdLength = 6;
2226 sc.scsi_Flags = SCSIF_READ;
2227
2228 unit->au_DirectSCSI(unit, &sc);
2229
2230 DATAPI(dump(sense, senselen));
2231 DATAPI(bug("[SENSE] atapi_RequestSense: sensed data: %lx %lx %lx\n", sense[2]&0xf, sense[12], sense[13]));
2232 return ((sense[2]&0xf)<<16) | (sense[12]<<8) | (sense[13]);
2233 }
2234
2235 ULONG ata_ReadSignature(struct ata_Bus *bus, int unit, BOOL *DiagExecuted)
2236 {
2237 ULONG port = bus->ab_Port;
2238 UBYTE tmp1, tmp2;
2239
2240 D(bug("[ATA ] ata_ReadSignature(%02ld)\n", unit));
2241
2242 BUS_OUT(DEVHEAD_VAL | (unit << 4), ata_DevHead, port);
2243 ata_WaitNano(400, bus->ab_Base);
2244 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2245
2246 DINIT(bug("[ATA ] ata_ReadSignature: Status %02lx Device %02lx\n",
2247 ata_ReadStatus(bus), BUS_IN(ata_DevHead, port)));
2248
2249 /* Ok, ATA/ATAPI device. Get detailed signature */
2250 DINIT(bug("[ATA ] ata_ReadSignature: ATA[PI] device present. Attempting to detect specific subtype\n"));
2251
2252 tmp1 = BUS_IN(ata_LBAMid, port);
2253 tmp2 = BUS_IN(ata_LBAHigh, port);
2254
2255 DINIT(bug("[ATA ] ata_ReadSignature: Subtype check returned %02lx:%02lx (%04lx)\n", tmp1, tmp2, (tmp1 << 8) | tmp2));
2256
2257 switch ((tmp1 << 8) | tmp2)
2258 {
2259 case 0x14eb:
2260 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for ATAPI device\n"));
2261 return DEV_ATAPI;
2262
2263 case 0x3cc3:
2264 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATA device\n"));
2265 return DEV_SATA;
2266
2267 case 0x6996:
2268 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATAPI device\n"));
2269 return DEV_SATAPI;
2270
2271 default:
2272 if (0 == (ata_ReadStatus(bus) & 0xfe)) {
2273 DINIT(bug("[ATA ] ata_ReadSignature: Found NONE\n"));
2274 return DEV_NONE;
2275 }
2276 /* ATA_EXECUTE_DIAG is executed by both devices, do it only once */
2277 if (!*DiagExecuted)
2278 {
2279 DINIT(bug("[ATA ] ata_ReadSignature: ATA_EXECUTE_DIAG\n"));
2280 BUS_OUT(ATA_EXECUTE_DIAG, ata_Command, port);
2281 *DiagExecuted = TRUE;
2282 }
2283
2284 ata_WaitTO(bus->ab_Timer, 0, 2000, 0);
2285 while (ata_ReadStatus(bus) & ATAF_BUSY)
2286 ata_WaitNano(400, bus->ab_Base);
2287 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2288
2289 DINIT(bug("[ATA ] ata_ReadSignature: ATAF_BUSY wait finished\n"));
2290
2291 BUS_OUT(DEVHEAD_VAL | (unit << 4), ata_DevHead, port);
2292 do
2293 {
2294 ata_WaitNano(400, bus->ab_Base);
2295 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
2296 }
2297 while (0 != (ATAF_BUSY & ata_ReadStatus(bus)));
2298 DINIT(bug("[ATA ] ata_ReadSignature: Further validating ATA signature: %lx & 0x7f = 1, %lx & 0x10 = unit\n", BUS_IN(ata_Error, port), BUS_IN(ata_DevHead, port)));
2299
2300 if ((BUS_IN(ata_Error, port) & 0x7f) == 1)
2301 {
2302 DINIT(bug("[ATA ] ata_ReadSignature: Found *valid* signature for ATA device\n"));
2303 /* this might still be an (S)ATAPI device, but we correct that in ata_Identify */
2304 return DEV_ATA;
2305 }
2306 DERROR(bug("[ATA ] ata_ReadSignature: Found signature for ATA "
2307 "device, but further validation failed\n"));
2308 return DEV_NONE;
2309 }
2310 }
2311
2312 void ata_ResetBus(struct ata_Bus *bus)
2313 {
2314 ULONG alt = bus->ab_Alt;
2315 ULONG port = bus->ab_Port;
2316 ULONG TimeOut;
2317 BOOL DiagExecuted = FALSE;
2318
2319 /* Set and then reset the soft reset bit in the Device Control
2320 * register. This causes device 0 be selected */
2321 DINIT(bug("[ATA ] ata_ResetBus(%d)\n", bus->ab_BusNum));
2322 BUS_OUT(DEVHEAD_VAL | (0 << 4), ata_DevHead, port); /* Select it never the less */
2323 ata_WaitNano(400, bus->ab_Base);
2324 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2325
2326 BUS_OUT(0x04 | 0x02, ata_AltControl, alt);
2327 ata_WaitTO(bus->ab_Timer, 0, 10, 0); /* sleep 10us; min: 5us */
2328 BUS_OUT(0x02, ata_AltControl, alt);
2329 ata_WaitTO(bus->ab_Timer, 0, 20000, 0); /* sleep 20ms; min: 2ms */
2330
2331 /* If there is a device 0, wait for device 0 to clear BSY */
2332 if (DEV_NONE != bus->ab_Dev[0]) {
2333 DINIT(bug("[ATA%02ld] ata_ResetBus: Wait for Device to clear BSY\n",
2334 ((bus->ab_BusNum << 1 ) + 0)));
2335 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2336 while ( 1 ) {
2337 if ((ata_ReadStatus(bus) & ATAF_BUSY) == 0)
2338 break;
2339 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2340 if (!(--TimeOut)) {
2341 DINIT(bug("[ATA%02ld] ata_ResetBus: Device Timed Out!\n",
2342 ((bus->ab_BusNum << 1 ) + 0)));
2343 bus->ab_Dev[0] = DEV_NONE;
2344 break;
2345 }
2346 }
2347 DINIT(bug("[ATA%02ld] ata_ResetBus: Wait left after %d ms\n",
2348 ((bus->ab_BusNum << 1 ) + 0), (1000 - TimeOut)));
2349 }
2350
2351 /* If there is a device 1, wait some time until device 1 allows
2352 * register access, but fail only if BSY isn't cleared */
2353 if (DEV_NONE != bus->ab_Dev[1]) {
2354 DINIT(bug("[ATA ] ata_ResetBus: Wait DEV1 to allow access\n"));
2355 BUS_OUT(DEVHEAD_VAL | (1 << 4), ata_DevHead, port);
2356 ata_WaitNano(400, bus->ab_Base);
2357 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2358
2359 TimeOut = 50; /* Timeout 50ms (1ms x 50) */
2360 while ( 1 ) {
2361 if ( (BUS_IN(ata_Count, port) == 0x01) && (BUS_IN(ata_LBALow, port) == 0x01) )
2362 break;
2363 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2364 if (!(--TimeOut)) {
2365 DINIT(bug("[ATA ] ata_ResetBus: DEV1 1/2 TimeOut!\n"));
2366 break;
2367 }
2368 }
2369 DINIT(bug("[ATA ] ata_ResetBus: DEV1 1/2 Wait left after %d ms\n",
2370 (1000 - TimeOut)));
2371
2372 if (DEV_NONE != bus->ab_Dev[1]) {
2373 DINIT(bug("[ATA%02ld] ata_ResetBus: Wait for Device to clear BSY\n",
2374 ((bus->ab_BusNum << 1 ) + 1)));
2375 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2376 while ( 1 ) {
2377 if ((ata_ReadStatus(bus) & ATAF_BUSY) == 0)
2378 break;
2379 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2380 if (!(--TimeOut)) {
2381 DINIT(bug("[ATA%02ld] ata_ResetBus: Device Timed Out!\n",
2382 ((bus->ab_BusNum << 1 ) + 1)));
2383 bus->ab_Dev[1] = DEV_NONE;
2384 break;
2385 }
2386 }
2387 DINIT(bug("[ATA%02ld] ata_ResetBus: Wait left after %d ms\n",
2388 ((bus->ab_BusNum << 1 ) + 1), 1000 - TimeOut));
2389 }
2390 }
2391
2392 if (DEV_NONE != bus->ab_Dev[0])
2393 bus->ab_Dev[0] = ata_ReadSignature(bus, 0, &DiagExecuted);
2394 if (DEV_NONE != bus->ab_Dev[1])
2395 bus->ab_Dev[1] = ata_ReadSignature(bus, 1, &DiagExecuted);
2396 }
2397
2398 void ata_InitBus(struct ata_Bus *bus)
2399 {
2400 ULONG port = bus->ab_Port;
2401 UBYTE tmp1, tmp2;
2402 UWORD i;
2403
2404 /*
2405 * initialize timer for the sake of scanning
2406 */
2407 bus->ab_Timer = ata_OpenTimer(bus->ab_Base);
2408
2409 DINIT(bug("[ATA ] ata_InitBus(%d)\n", bus->ab_BusNum));
2410
2411 bus->ab_Dev[0] = DEV_NONE;
2412 bus->ab_Dev[1] = DEV_NONE;
2413
2414 for (i = 0; i < MAX_BUSUNITS; i++)
2415 {
2416 /* Select device and disable IRQs */
2417 BUS_OUT(DEVHEAD_VAL | (i << 4), ata_DevHead, port);
2418 ata_WaitTO(bus->ab_Timer, 0, 100, 0);
2419 BUS_OUT(0x2, ata_AltControl, bus->ab_Alt);
2420
2421 /* Write some pattern to registers */
2422 BUS_OUT(0x55, ata_Count, port);
2423 BUS_OUT(0xaa, ata_LBALow, port);
2424 BUS_OUT(0xaa, ata_Count, port);
2425 BUS_OUT(0x55, ata_LBALow, port);
2426 BUS_OUT(0x55, ata_Count, port);
2427 BUS_OUT(0xaa, ata_LBALow, port);
2428
2429 tmp1 = BUS_IN(ata_Count, port);
2430 tmp2 = BUS_IN(ata_LBALow, port);
2431
2432 if ((tmp1 == 0x55) && (tmp2 == 0xaa))
2433 bus->ab_Dev[i] = DEV_UNKNOWN;
2434 DINIT(bug("[ATA%02ld] ata_InitBus: Device type = %x\n",
2435 (bus->ab_BusNum << 1 ) + i, bus->ab_Dev[i]));
2436 }
2437
2438 ata_ResetBus(bus);
2439 ata_CloseTimer(bus->ab_Timer);
2440 DINIT(bug("[ATA ] ata_InitBus: Finished\n"));
2441 }
2442
2443 /*
2444 * not really sure what this is meant to be - TO BE REPLACED
2445 */
2446 static const ULONG ErrorMap[] = {
2447 CDERR_NotSpecified,
2448 CDERR_NoSecHdr,
2449 CDERR_NoDisk,
2450 CDERR_NoSecHdr,
2451 CDERR_NoSecHdr,
2452 CDERR_NOCMD,
2453 CDERR_NoDisk,
2454 CDERR_WriteProt,
2455 CDERR_NotSpecified,
2456 CDERR_NotSpecified,
2457 CDERR_NotSpecified,
2458 CDERR_ABORTED,
2459 CDERR_NotSpecified,
2460 CDERR_NotSpecified,
2461 CDERR_NoSecHdr,
2462 CDERR_NotSpecified,
2463 };
2464
2465 static BYTE atapi_EndCmd(struct ata_Unit *unit)
2466 {
2467 UBYTE status;
2468
2469 DATAPI(bug("[ATA%02ld] atapi_EndCmd()\n", unit->au_UnitNum));
2470
2471 /*
2472 * read alternate status register (per specs)
2473 */
2474 status = ATA_IN(ata_AltStatus, unit->au_Bus->ab_Alt);
2475 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Alternate status: %lx\n", unit->au_UnitNum, status));
2476
2477 status = ATA_IN(atapi_Status, unit->au_Bus->ab_Port);
2478
2479 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Command complete. Status: %lx\n",
2480 unit->au_UnitNum, status));
2481
2482 if (!(status & ATAPIF_CHECK))
2483 {
2484 return 0;
2485 }
2486 else
2487 {
2488 status = ATA_IN(atapi_Error, unit->au_Bus->ab_Port);
2489 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Error code 0x%lx\n", unit->au_UnitNum, status >> 4));
2490 return ErrorMap[status >> 4];
2491 }
2492 }
2493
2494 /*
2495 * vim: ts=4 et sw=4 fdm=marker fmr={,}
2496 */
Mirror of AROS' svn.