forwarding: The intel code has been updated to version 8.0.35, and the rx queue hang...
[AROS.git] / workbench / devs / networks / e1000 / e1000_manage.h
blob2b92438290fc10579ab89538707cec22ef406108
1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #ifndef _E1000_MANAGE_H_
30 #define _E1000_MANAGE_H_
32 bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
33 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
34 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
35 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
36 u16 length, u16 offset, u8 *sum);
37 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
38 struct e1000_host_mng_command_header *hdr);
39 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
40 u8 *buffer, u16 length);
41 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
43 enum e1000_mng_mode {
44 e1000_mng_mode_none = 0,
45 e1000_mng_mode_asf,
46 e1000_mng_mode_pt,
47 e1000_mng_mode_ipmi,
48 e1000_mng_mode_host_if_only
51 #define E1000_FACTPS_MNGCG 0x20000000
53 #define E1000_FWSM_MODE_MASK 0xE
54 #define E1000_FWSM_MODE_SHIFT 1
56 #define E1000_MNG_IAMT_MODE 0x3
57 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
58 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
59 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
60 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
61 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
62 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
64 #define E1000_VFTA_ENTRY_SHIFT 5
65 #define E1000_VFTA_ENTRY_MASK 0x7F
66 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
68 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */
69 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */
70 #define E1000_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */
71 #define E1000_HICR_EN 0x01 /* Enable bit - RO */
72 /* Driver sets this bit when done to put command in RAM */
73 #define E1000_HICR_C 0x02
74 #define E1000_HICR_SV 0x04 /* Status Validity */
75 #define E1000_HICR_FW_RESET_ENABLE 0x40
76 #define E1000_HICR_FW_RESET 0x80
78 /* Intel(R) Active Management Technology signature */
79 #define E1000_IAMT_SIGNATURE 0x544D4149
81 #endif