rom/devs/ahci/ahci_attach.c

   1 /*
   2  * (MPSAFE)
   3  *
   4  * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *
  19  * Copyright (c) 2009 The DragonFly Project.  All rights reserved.
  20  *
  21  * This code is derived from software contributed to The DragonFly Project
  22  * by Matthew Dillon <dillon@backplane.com>
  23  *
  24  * Redistribution and use in source and binary forms, with or without
  25  * modification, are permitted provided that the following conditions
  26  * are met:
  27  *
  28  * 1. Redistributions of source code must retain the above copyright
  29  *    notice, this list of conditions and the following disclaimer.
  30  * 2. Redistributions in binary form must reproduce the above copyright
  31  *    notice, this list of conditions and the following disclaimer in
  32  *    the documentation and/or other materials provided with the
  33  *    distribution.
  34  * 3. Neither the name of The DragonFly Project nor the names of its
  35  *    contributors may be used to endorse or promote products derived
  36  *    from this software without specific, prior written permission.
  37  *
  38  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  39  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  40  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  41  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  42  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  43  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  44  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  45  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  46  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  47  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  48  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  49  * SUCH DAMAGE.
  50  *
  51  * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
  52  */
  53
  54 #include "ahci.h"
  55
  56 static int      ahci_vt8251_attach(device_t);
  57 static int      ahci_ati_sb600_attach(device_t);
  58 static int      ahci_ati_sb700_attach(device_t);
  59 static int      ahci_nvidia_mcp_attach(device_t);
  60 static int      ahci_pci_attach(device_t);
  61 static int      ahci_pci_detach(device_t);
  62
  63 static const struct ahci_device ahci_devices[] = {
  64         { PCI_VENDOR_VIATECH,   PCI_PRODUCT_VIATECH_VT8251_SATA,
  65             ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
  66         { PCI_VENDOR_ATI,       PCI_PRODUCT_ATI_SB600_SATA,
  67             ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
  68         { PCI_VENDOR_ATI,       PCI_PRODUCT_ATI_SB700_SATA,
  69             ahci_ati_sb700_attach, ahci_pci_detach, "ATI-SB700-SATA" },
  70         { PCI_VENDOR_NVIDIA,    PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
  71             ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
  72         { PCI_VENDOR_NVIDIA,    PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
  73             ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
  74         { PCI_VENDOR_NVIDIA,    PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
  75             ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
  76         { 0, 0,
  77             ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
  78 };
  79
  80 /*
  81  * Match during probe and attach.  The device does not yet have a softc.
  82  */
  83 const struct ahci_device *
  84 ahci_lookup_device(device_t dev)
  85 {
  86         const struct ahci_device *ad;
  87         u_int16_t vendor = pci_get_vendor(dev);
  88         u_int16_t product = pci_get_device(dev);
  89         u_int8_t class = pci_get_class(dev);
  90         u_int8_t subclass = pci_get_subclass(dev);
  91         u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
  92         int is_ahci;
  93
  94         /*
  95          * Generally speaking if the pci device does not identify as
  96          * AHCI we skip it.
  97          */
  98         if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
  99             progif == PCIP_STORAGE_SATA_AHCI_1_0) {
 100                 is_ahci = 1;
 101         } else {
 102                 is_ahci = 0;
 103         }
 104
 105         for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
 106                 if (ad->ad_vendor == vendor && ad->ad_product == product)
 107                         return (ad);
 108         }
 109
 110         /*
 111          * Last ad is the default match if the PCI device matches SATA.
 112          */
 113         if (is_ahci == 0)
 114                 ad = NULL;
 115         return (ad);
 116 }
 117
 118 /*
 119  * Attach functions.  They all eventually fall through to ahci_pci_attach().
 120  */
 121 static int
 122 ahci_vt8251_attach(device_t dev)
 123 {
 124         struct ahci_softc *sc = device_get_softc(dev);
 125
 126         sc->sc_flags |= AHCI_F_NO_NCQ;
 127         return (ahci_pci_attach(dev));
 128 }
 129
 130 static int
 131 ahci_ati_sb600_attach(device_t dev)
 132 {
 133         struct ahci_softc *sc = device_get_softc(dev);
 134         pcireg_t magic;
 135         u_int8_t subclass = pci_get_subclass(dev);
 136         u_int8_t revid;
 137
 138         if (subclass == PCIS_STORAGE_IDE) {
 139                 revid = pci_read_config(dev, PCIR_REVID, 1);
 140                 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
 141                 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
 142                                  magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
 143                 pci_write_config(dev, PCIR_REVID,
 144                                  (PCIC_STORAGE << 24) |
 145                                  (PCIS_STORAGE_SATA << 16) |
 146                                  (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
 147                                  revid, 4);
 148                 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
 149         }
 150
 151         sc->sc_flags |= AHCI_F_IGN_FR;
 152         return (ahci_pci_attach(dev));
 153 }
 154
 155 static int
 156 ahci_ati_sb700_attach(device_t dev)
 157 {
 158         struct ahci_softc *sc = device_get_softc(dev);
 159
 160         sc->sc_flags |= AHCI_F_IGN_FR;
 161         sc->sc_flags |= AHCI_F_NO_PM;
 162         return (ahci_pci_attach(dev));
 163 }
 164
 165 static int
 166 ahci_nvidia_mcp_attach(device_t dev)
 167 {
 168         struct ahci_softc *sc = device_get_softc(dev);
 169
 170         sc->sc_flags |= AHCI_F_IGN_FR;
 171         return (ahci_pci_attach(dev));
 172 }
 173
 174 static int
 175 ahci_pci_attach(device_t dev)
 176 {
 177         struct ahci_softc *sc = device_get_softc(dev);
 178         struct ahci_port *ap;
 179         const char *gen;
 180         u_int32_t cap, pi, reg;
 181         bus_addr_t addr;
 182         int i;
 183         int error;
 184         const char *revision;
 185
 186         if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
 187                 device_printf(dev, "BIOS disabled PCI interrupt, "
 188                                    "re-enabling\n");
 189                 pci_write_config(dev, PCIR_COMMAND,
 190                         pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
 191         }
 192
 193
 194         /*
 195          * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
 196          */
 197         sc->sc_dev = dev;
 198         sc->sc_rid_irq = AHCI_IRQ_RID;
 199         sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
 200                                             RF_SHAREABLE | RF_ACTIVE);
 201         if (sc->sc_irq == NULL) {
 202                 device_printf(dev, "unable to map interrupt\n");
 203                 ahci_pci_detach(dev);
 204                 return (ENXIO);
 205         }
 206
 207         /*
 208          * When mapping the register window store the tag and handle
 209          * separately so we can use the tag with per-port bus handle
 210          * sub-spaces.
 211          */
 212         sc->sc_rid_regs = PCIR_BAR(5);
 213         sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 214                                              &sc->sc_rid_regs, RF_ACTIVE);
 215         if (sc->sc_regs == NULL) {
 216                 device_printf(dev, "unable to map registers\n");
 217                 ahci_pci_detach(dev);
 218                 return (ENXIO);
 219         }
 220         sc->sc_iot = rman_get_bustag(sc->sc_regs);
 221         sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
 222
 223         /*
 224          * Initialize the chipset and then set the interrupt vector up
 225          */
 226         device_printf(dev, "device flags 0x%x\n", sc->sc_flags);
 227         error = ahci_init(sc);
 228         if (error) {
 229                 ahci_pci_detach(dev);
 230                 return (ENXIO);
 231         }
 232
 233         /*
 234          * Get the AHCI capabilities and max number of concurrent
 235          * command tags and set up the DMA tags.
 236          */
 237         cap = ahci_read(sc, AHCI_REG_CAP);
 238         if (sc->sc_flags & AHCI_F_NO_NCQ)
 239                 cap &= ~AHCI_REG_CAP_SNCQ;
 240         if (sc->sc_flags & AHCI_F_NO_PM)
 241                 cap &= ~AHCI_REG_CAP_SPM;
 242         sc->sc_cap = cap;
 243
 244         /*
 245          * We assume at least 4 commands.
 246          */
 247         sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
 248         if (sc->sc_ncmds < 4) {
 249                 device_printf(dev, "NCS must probe a value >= 4\n");
 250                 ahci_pci_detach(dev);
 251                 return (ENXIO);
 252         }
 253
 254         addr = (cap & AHCI_REG_CAP_S64A) ?
 255                 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
 256
 257         /*
 258          * DMA tags for allocation of DMA memory buffers, lists, and so
 259          * forth.  These are typically per-port.
 260          */
 261         error = 0;
 262         error += bus_dma_tag_create(
 263                         NULL,                           /* parent tag */
 264                         256,                            /* alignment */
 265                         PAGE_SIZE,                      /* boundary */
 266                         addr,                           /* loaddr? */
 267                         BUS_SPACE_MAXADDR,              /* hiaddr */
 268                         NULL,                           /* filter */
 269                         NULL,                           /* filterarg */
 270                         sizeof(struct ahci_rfis),       /* [max]size */
 271                         1,                              /* maxsegs */
 272                         sizeof(struct ahci_rfis),       /* maxsegsz */
 273                         0,                              /* flags */
 274                         &sc->sc_tag_rfis);              /* return tag */
 275
 276         error += bus_dma_tag_create(
 277                         NULL,                           /* parent tag */
 278                         32,                             /* alignment */
 279                         1024,                           /* boundary */
 280                         addr,                           /* loaddr? */
 281                         BUS_SPACE_MAXADDR,              /* hiaddr */
 282                         NULL,                           /* filter */
 283                         NULL,                           /* filterarg */
 284                         sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
 285                         1,                              /* maxsegs */
 286                         sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
 287                         0,                              /* flags */
 288                         &sc->sc_tag_cmdh);              /* return tag */
 289
 290         /*
 291          * NOTE: ahci_cmd_table is sized to a power of 2
 292          */
 293         error += bus_dma_tag_create(
 294                         NULL,                           /* parent tag */
 295                         sizeof(struct ahci_cmd_table),  /* alignment */
 296                         1024,                           /* boundary */
 297                         addr,                           /* loaddr? */
 298                         BUS_SPACE_MAXADDR,              /* hiaddr */
 299                         NULL,                           /* filter */
 300                         NULL,                           /* filterarg */
 301                         sc->sc_ncmds * sizeof(struct ahci_cmd_table),
 302                         1,                              /* maxsegs */
 303                         sc->sc_ncmds * sizeof(struct ahci_cmd_table),
 304                         0,                              /* flags */
 305                         &sc->sc_tag_cmdt);              /* return tag */
 306
 307         /*
 308          * The data tag is used for later dmamaps and not immediately
 309          * allocated.
 310          */
 311         error += bus_dma_tag_create(
 312                         NULL,                           /* parent tag */
 313                         4,                              /* alignment */
 314                         0,                              /* boundary */
 315                         addr,                           /* loaddr? */
 316                         BUS_SPACE_MAXADDR,              /* hiaddr */
 317                         NULL,                           /* filter */
 318                         NULL,                           /* filterarg */
 319                         4096 * 1024,                    /* maxiosize */
 320                         AHCI_MAX_PRDT,                  /* maxsegs */
 321                         65536,                          /* maxsegsz */
 322                         0,                              /* flags */
 323                         &sc->sc_tag_data);              /* return tag */
 324
 325         if (error) {
 326                 device_printf(dev, "unable to create dma tags\n");
 327                 ahci_pci_detach(dev);
 328                 return (ENXIO);
 329         }
 330
 331         switch (cap & AHCI_REG_CAP_ISS) {
 332         case AHCI_REG_CAP_ISS_G1:
 333                 gen = "1 (1.5Gbps)";
 334                 break;
 335         case AHCI_REG_CAP_ISS_G2:
 336                 gen = "2 (3Gbps)";
 337                 break;
 338         case AHCI_REG_CAP_ISS_G3:
 339                 gen = "3 (6Gbps)";
 340                 break;
 341         default:
 342                 gen = "unknown";
 343                 break;
 344         }
 345
 346         /* check the revision */
 347         reg = ahci_read(sc, AHCI_REG_VS);
 348         switch (reg) {
 349         case AHCI_REG_VS_0_95:
 350                 revision = "AHCI 0.95";
 351                 break;
 352         case AHCI_REG_VS_1_0:
 353                 revision = "AHCI 1.0";
 354                 break;
 355         case AHCI_REG_VS_1_1:
 356                 revision = "AHCI 1.1";
 357                 break;
 358         case AHCI_REG_VS_1_2:
 359                 revision = "AHCI 1.2";
 360                 break;
 361         case AHCI_REG_VS_1_3:
 362                 revision = "AHCI 1.3";
 363                 break;
 364         case AHCI_REG_VS_1_4:
 365                 revision = "AHCI 1.4";
 366                 break;
 367         case AHCI_REG_VS_1_5:
 368                 revision = "AHCI 1.5";  /* future will catch up to us */
 369                 break;
 370         default:
 371                 device_printf(sc->sc_dev,
 372                               "Warning: Unknown AHCI revision 0x%08x\n", reg);
 373                 revision = "AHCI <unknown>";
 374                 break;
 375         }
 376
 377         device_printf(dev,
 378                       "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n",
 379                       revision,
 380                       cap, AHCI_FMT_CAP,
 381                       AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
 382
 383         pi = ahci_read(sc, AHCI_REG_PI);
 384         DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
 385             DEVNAME(sc), pi);
 386
 387 #ifdef AHCI_COALESCE
 388         /* Naive coalescing support - enable for all ports. */
 389         if (cap & AHCI_REG_CAP_CCCS) {
 390                 u_int16_t               ccc_timeout = 20;
 391                 u_int8_t                ccc_numcomplete = 12;
 392                 u_int32_t               ccc_ctl;
 393
 394                 /* disable coalescing during reconfiguration. */
 395                 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
 396                 ccc_ctl &= ~0x00000001;
 397                 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
 398
 399                 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
 400                 if (pi & sc->sc_ccc_mask) {
 401                         /* A conflict with the implemented port list? */
 402                         kprintf("%s: coalescing interrupt/implemented port list "
 403                             "conflict, PI: %08x, ccc_mask: %08x\n",
 404                             DEVNAME(sc), pi, sc->sc_ccc_mask);
 405                         sc->sc_ccc_mask = 0;
 406                         goto noccc;
 407                 }
 408
 409                 /* ahci_port_start will enable each port when it starts. */
 410                 sc->sc_ccc_ports = pi;
 411                 sc->sc_ccc_ports_cur = 0;
 412
 413                 /* program thresholds and enable overall coalescing. */
 414                 ccc_ctl &= ~0xffffff00;
 415                 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
 416                 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
 417                 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
 418                 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
 419         }
 420 noccc:
 421 #endif
 422         /*
 423          * Allocate per-port resources
 424          *
 425          * Ignore attach errors, leave the port intact for
 426          * rescan and continue the loop.
 427          *
 428          * All ports are attached in parallel but the CAM scan-bus
 429          * is held up until all ports are attached so we get a deterministic
 430          * order.
 431          */
 432         for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
 433                 if ((pi & (1 << i)) == 0) {
 434                         /* dont allocate stuff if the port isnt implemented */
 435                         continue;
 436                 }
 437                 error = ahci_port_alloc(sc, i);
 438         }
 439
 440         /*
 441          * Setup the interrupt vector and enable interrupts.  Note that
 442          * since the irq may be shared we do not set it up until we are
 443          * ready to go.
 444          */
 445         if (error == 0) {
 446                 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
 447                                        ahci_intr, sc,
 448                                        &sc->sc_irq_handle, NULL);
 449         }
 450
 451         if (error) {
 452                 device_printf(dev, "unable to install interrupt\n");
 453                 ahci_pci_detach(dev);
 454                 return (ENXIO);
 455         }
 456
 457         /*
 458          * Before marking the sc as good, which allows the interrupt
 459          * subsystem to operate on the ports, wait for all the port threads
 460          * to get past their initial pre-probe init.  Otherwise an interrupt
 461          * may try to process the port before it has been initialized.
 462          */
 463         for (i = 0; i < AHCI_MAX_PORTS; i++) {
 464                 if ((ap = sc->sc_ports[i]) != NULL) {
 465                         while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
 466                                 ahci_os_sleep(100);
 467                 }
 468         }
 469
 470         /*
 471          * Master interrupt enable, and call ahci_intr() in case we race
 472          * our AHCI_F_INT_GOOD flag.
 473          */
 474         crit_enter();
 475         ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
 476         sc->sc_flags |= AHCI_F_INT_GOOD;
 477         crit_exit();
 478         ahci_intr(sc);
 479
 480         /*
 481          * All ports are probing in parallel.  Wait for them to finish
 482          * and then issue the cam attachment and bus scan serially so
 483          * the 'da' assignments are deterministic.
 484          */
 485         for (i = 0; i < AHCI_MAX_PORTS; i++) {
 486                 if ((ap = sc->sc_ports[i]) != NULL) {
 487                         while (ap->ap_signal & AP_SIGF_INIT)
 488                             ahci_os_sleep(100);
 489                         ahci_os_lock_port(ap);
 490                         if (ahci_cam_attach(ap) == 0) {
 491                                 ahci_cam_changed(ap, NULL, -1);
 492                                 ahci_os_unlock_port(ap);
 493                                 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
 494                                         ahci_os_sleep(100);
 495                                 }
 496                         } else {
 497                                 ahci_os_unlock_port(ap);
 498                         }
 499                 }
 500         }
 501
 502         return(0);
 503 }
 504
 505 /*
 506  * Device unload / detachment
 507  */
 508 static int
 509 ahci_pci_detach(device_t dev)
 510 {
 511         struct ahci_softc *sc = device_get_softc(dev);
 512         struct ahci_port *ap;
 513         int     i;
 514
 515         /*
 516          * Disable the controller and de-register the interrupt, if any.
 517          *
 518          * XXX interlock last interrupt?
 519          */
 520         sc->sc_flags &= ~AHCI_F_INT_GOOD;
 521         if (sc->sc_regs)
 522                 ahci_write(sc, AHCI_REG_GHC, 0);
 523
 524         if (sc->sc_irq_handle) {
 525                 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
 526                 sc->sc_irq_handle = NULL;
 527         }
 528
 529         /*
 530          * Free port structures and DMA memory
 531          */
 532         for (i = 0; i < AHCI_MAX_PORTS; i++) {
 533                 ap = sc->sc_ports[i];
 534                 if (ap) {
 535                         ahci_cam_detach(ap);
 536                         ahci_port_free(sc, i);
 537                 }
 538         }
 539
 540         /*
 541          * Clean up the bus space
 542          */
 543         if (sc->sc_irq) {
 544                 bus_release_resource(dev, SYS_RES_IRQ,
 545                                      sc->sc_rid_irq, sc->sc_irq);
 546                 sc->sc_irq = NULL;
 547         }
 548         if (sc->sc_regs) {
 549                 bus_release_resource(dev, SYS_RES_MEMORY,
 550                                      sc->sc_rid_regs, sc->sc_regs);
 551                 sc->sc_regs = NULL;
 552         }
 553
 554         if (sc->sc_tag_rfis) {
 555                 bus_dma_tag_destroy(sc->sc_tag_rfis);
 556                 sc->sc_tag_rfis = NULL;
 557         }
 558         if (sc->sc_tag_cmdh) {
 559                 bus_dma_tag_destroy(sc->sc_tag_cmdh);
 560                 sc->sc_tag_cmdh = NULL;
 561         }
 562         if (sc->sc_tag_cmdt) {
 563                 bus_dma_tag_destroy(sc->sc_tag_cmdt);
 564                 sc->sc_tag_cmdt = NULL;
 565         }
 566         if (sc->sc_tag_data) {
 567                 bus_dma_tag_destroy(sc->sc_tag_data);
 568                 sc->sc_tag_data = NULL;
 569         }
 570
 571         return (0);
 572 }