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Minor fixes to comments.
[AROS.git] / rom / devs / ahci / ahci.h
blob448b9a36a11175b88ce13583d0e4886ebefb2101
1 /*
2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
17 */
18
19 #if defined(__DragonFly__)
20 #include "ahci_dragonfly.h"
21 #elif defined(__AROS__)
22 #include "ahci_aros.h"
23 #else
24 #error "build for OS unknown"
25 #endif
26 #include "pmreg.h"
27 #include "atascsi.h"
28
29 /* change to AHCI_DEBUG for dmesg spam */
30 #define NO_AHCI_DEBUG
31
32 #ifdef AHCI_DEBUG
33 #define DPRINTF(m, f...) do { if ((ahcidebug & (m)) == (m)) kprintf(f); } \
34 while (0)
35 #define AHCI_D_TIMEOUT 0x00
36 #define AHCI_D_VERBOSE 0x01
37 #define AHCI_D_INTR 0x02
38 #define AHCI_D_XFER 0x08
39 static const int ahcidebug = 0xff;
40 #else
41 #define DPRINTF(m, f...)
42 #endif
43
44 #define AHCI_PCI_ATI_SB600_MAGIC 0x40
45 #define AHCI_PCI_ATI_SB600_LOCKED 0x01
46
47 #define AHCI_REG_CAP 0x000 /* HBA Capabilities */
48 #define AHCI_REG_CAP_NP(_r) (((_r) & 0x1f)+1) /* Number of Ports */
49 #define AHCI_REG_CAP_SXS (1<<5) /* External SATA */
50 #define AHCI_REG_CAP_EMS (1<<6) /* Enclosure Mgmt */
51 #define AHCI_REG_CAP_CCCS (1<<7) /* Cmd Coalescing */
52 #define AHCI_REG_CAP_NCS(_r) ((((_r) & 0x1f00)>>8)+1) /* NCmds*/
53 #define AHCI_REG_CAP_PSC (1<<13) /* Partial State Capable */
54 #define AHCI_REG_CAP_SSC (1<<14) /* Slumber State Capable */
55 #define AHCI_REG_CAP_PMD (1<<15) /* PIO Multiple DRQ Block */
56 #define AHCI_REG_CAP_FBSS (1<<16) /* FIS-Based Switching */
57 #define AHCI_REG_CAP_SPM (1<<17) /* Port Multiplier */
58 #define AHCI_REG_CAP_SAM (1<<18) /* AHCI Only mode */
59 #define AHCI_REG_CAP_SNZO (1<<19) /* Non Zero DMA Offsets */
60 #define AHCI_REG_CAP_ISS (0xf<<20) /* Interface Speed Support */
61 #define AHCI_REG_CAP_ISS_G1 (0x1<<20) /* Gen 1 (1.5 Gbps) */
62 #define AHCI_REG_CAP_ISS_G2 (0x2<<20) /* Gen 2 (3 Gbps) */
63 #define AHCI_REG_CAP_ISS_G3 (0x3<<20) /* Gen 3 (6 Gbps) */
64 #define AHCI_REG_CAP_SCLO (1<<24) /* Cmd List Override */
65 #define AHCI_REG_CAP_SAL (1<<25) /* Activity LED */
66 #define AHCI_REG_CAP_SALP (1<<26) /* Aggressive Link Pwr Mgmt */
67 #define AHCI_REG_CAP_SSS (1<<27) /* Staggered Spinup */
68 #define AHCI_REG_CAP_SMPS (1<<28) /* Mech Presence Switch */
69 #define AHCI_REG_CAP_SSNTF (1<<29) /* SNotification Register */
70 #define AHCI_REG_CAP_SNCQ (1<<30) /* Native Cmd Queuing */
71 #define AHCI_REG_CAP_S64A (1<<31) /* 64bit Addressing */
72 #define AHCI_FMT_CAP "\020" "\040S64A" "\037NCQ" "\036SSNTF" \
73 "\035SMPS" "\034SSS" "\033SALP" "\032SAL" \
74 "\031SCLO" "\024SNZO" "\023SAM" "\022SPM" \
75 "\021FBSS" "\020PMD" "\017SSC" "\016PSC" \
76 "\010CCCS" "\007EMS" "\006SXS"
77
78 #define AHCI_REG_GHC 0x004 /* Global HBA Control */
79 #define AHCI_REG_GHC_HR (1<<0) /* HBA Reset */
80 #define AHCI_REG_GHC_IE (1<<1) /* Interrupt Enable */
81 #define AHCI_REG_GHC_MRSM (1<<2) /* MSI Revert to Single Msg */
82 #define AHCI_REG_GHC_AE (1<<31) /* AHCI Enable */
83 #define AHCI_FMT_GHC "\020" "\040AE" "\003MRSM" "\002IE" "\001HR"
84
85 #define AHCI_REG_IS 0x008 /* Interrupt Status */
86 #define AHCI_REG_PI 0x00c /* Ports Implemented */
87
88 #define AHCI_REG_VS 0x010 /* AHCI Version */
89 #define AHCI_REG_VS_0_95 0x00000905 /* 0.95 */
90 #define AHCI_REG_VS_1_0 0x00010000 /* 1.0 */
91 #define AHCI_REG_VS_1_1 0x00010100 /* 1.1 */
92 #define AHCI_REG_VS_1_2 0x00010200 /* 1.2 */
93 #define AHCI_REG_VS_1_3 0x00010300 /* 1.3 */
94 #define AHCI_REG_VS_1_4 0x00010400 /* 1.4 */
95 #define AHCI_REG_VS_1_5 0x00010500 /* 1.5 (future...) */
96
97 #define AHCI_REG_CCC_CTL 0x014 /* Coalescing Control */
98 #define AHCI_REG_CCC_CTL_INT(_r) (((_r) & 0xf8) >> 3) /* CCC INT slot */
99
100 #define AHCI_REG_CCC_PORTS 0x018 /* Coalescing Ports */
101 #define AHCI_REG_EM_LOC 0x01c /* Enclosure Mgmt Location */
102 #define AHCI_REG_EM_CTL 0x020 /* Enclosure Mgmt Control */
103
104 #define AHCI_PORT_REGION(_p) (0x100 + ((_p) * 0x80))
105 #define AHCI_PORT_SIZE 0x80
106
107 #define AHCI_PREG_CLB 0x00 /* Cmd List Base Addr */
108 #define AHCI_PREG_CLBU 0x04 /* Cmd List Base Hi Addr */
109 #define AHCI_PREG_FB 0x08 /* FIS Base Addr */
110 #define AHCI_PREG_FBU 0x0c /* FIS Base Hi Addr */
111
112 #define AHCI_PREG_IS 0x10 /* Interrupt Status */
113 #define AHCI_PREG_IS_DHRS (1<<0) /* Device to Host FIS */
114 #define AHCI_PREG_IS_PSS (1<<1) /* PIO Setup FIS */
115 #define AHCI_PREG_IS_DSS (1<<2) /* DMA Setup FIS */
116 #define AHCI_PREG_IS_SDBS (1<<3) /* Set Device Bits FIS */
117 #define AHCI_PREG_IS_UFS (1<<4) /* Unknown FIS */
118 #define AHCI_PREG_IS_DPS (1<<5) /* Descriptor Processed */
119 #define AHCI_PREG_IS_PCS (1<<6) /* Port Change */
120 #define AHCI_PREG_IS_DMPS (1<<7) /* Device Mechanical Presence */
121 #define AHCI_PREG_IS_PRCS (1<<22) /* PhyRdy Change */
122 #define AHCI_PREG_IS_IPMS (1<<23) /* Incorrect Port Multiplier */
123 #define AHCI_PREG_IS_OFS (1<<24) /* Overflow */
124 #define AHCI_PREG_IS_INFS (1<<26) /* Interface Non-fatal Error */
125 #define AHCI_PREG_IS_IFS (1<<27) /* Interface Fatal Error */
126 #define AHCI_PREG_IS_HBDS (1<<28) /* Host Bus Data Error */
127 #define AHCI_PREG_IS_HBFS (1<<29) /* Host Bus Fatal Error */
128 #define AHCI_PREG_IS_TFES (1<<30) /* Task File Error */
129 #define AHCI_PREG_IS_CPDS (1<<31) /* Cold Presence Detect */
130 #define AHCI_PFMT_IS "\20" "\040CPDS" "\037TFES" "\036HBFS" \
131 "\035HBDS" "\034IFS" "\033INFS" "\031OFS" \
132 "\030IPMS" "\027PRCS" "\010DMPS" "\006DPS" \
133 "\007PCS" "\005UFS" "\004SDBS" "\003DSS" \
134 "\002PSS" "\001DHRS"
135
136 #define AHCI_PREG_IE 0x14 /* Interrupt Enable */
137 #define AHCI_PREG_IE_DHRE (1<<0) /* Device to Host FIS */
138 #define AHCI_PREG_IE_PSE (1<<1) /* PIO Setup FIS */
139 #define AHCI_PREG_IE_DSE (1<<2) /* DMA Setup FIS */
140 #define AHCI_PREG_IE_SDBE (1<<3) /* Set Device Bits FIS */
141 #define AHCI_PREG_IE_UFE (1<<4) /* Unknown FIS */
142 #define AHCI_PREG_IE_DPE (1<<5) /* Descriptor Processed */
143 #define AHCI_PREG_IE_PCE (1<<6) /* Port Change */
144 #define AHCI_PREG_IE_DMPE (1<<7) /* Device Mechanical Presence */
145 #define AHCI_PREG_IE_PRCE (1<<22) /* PhyRdy Change */
146 #define AHCI_PREG_IE_IPME (1<<23) /* Incorrect Port Multiplier */
147 #define AHCI_PREG_IE_OFE (1<<24) /* Overflow */
148 #define AHCI_PREG_IE_INFE (1<<26) /* Interface Non-fatal Error */
149 #define AHCI_PREG_IE_IFE (1<<27) /* Interface Fatal Error */
150 #define AHCI_PREG_IE_HBDE (1<<28) /* Host Bus Data Error */
151 #define AHCI_PREG_IE_HBFE (1<<29) /* Host Bus Fatal Error */
152 #define AHCI_PREG_IE_TFEE (1<<30) /* Task File Error */
153 #define AHCI_PREG_IE_CPDE (1<<31) /* Cold Presence Detect */
154 #define AHCI_PFMT_IE "\20" "\040CPDE" "\037TFEE" "\036HBFE" \
155 "\035HBDE" "\034IFE" "\033INFE" "\031OFE" \
156 "\030IPME" "\027PRCE" "\010DMPE" "\007PCE" \
157 "\006DPE" "\005UFE" "\004SDBE" "\003DSE" \
158 "\002PSE" "\001DHRE"
159
160 #define AHCI_PREG_CMD 0x18 /* Command and Status */
161 #define AHCI_PREG_CMD_ST (1<<0) /* Start */
162 #define AHCI_PREG_CMD_SUD (1<<1) /* Spin Up Device */
163 #define AHCI_PREG_CMD_POD (1<<2) /* Power On Device */
164 #define AHCI_PREG_CMD_CLO (1<<3) /* Command List Override */
165 #define AHCI_PREG_CMD_FRE (1<<4) /* FIS Receive Enable */
166 #define AHCI_PREG_CMD_CCS(_r) (((_r) >> 8) & 0x1f) /* Curr CmdSlot# */
167 #define AHCI_PREG_CMD_MPSS (1<<13) /* Mech Presence State */
168 #define AHCI_PREG_CMD_FR (1<<14) /* FIS Receive Running */
169 #define AHCI_PREG_CMD_CR (1<<15) /* Command List Running */
170 #define AHCI_PREG_CMD_CPS (1<<16) /* Cold Presence State */
171 #define AHCI_PREG_CMD_PMA (1<<17) /* Port Multiplier Attached */
172 #define AHCI_PREG_CMD_HPCP (1<<18) /* Hot Plug Capable */
173 #define AHCI_PREG_CMD_MPSP (1<<19) /* Mech Presence Switch */
174 #define AHCI_PREG_CMD_CPD (1<<20) /* Cold Presence Detection */
175 #define AHCI_PREG_CMD_ESP (1<<21) /* External SATA Port */
176 #define AHCI_PREG_CMD_ATAPI (1<<24) /* Device is ATAPI */
177 #define AHCI_PREG_CMD_DLAE (1<<25) /* Drv LED on ATAPI Enable */
178 #define AHCI_PREG_CMD_ALPE (1<<26) /* Aggro Pwr Mgmt Enable */
179 #define AHCI_PREG_CMD_ASP (1<<27) /* Aggro Slumber/Partial */
180 #define AHCI_PREG_CMD_ICC 0xf0000000 /* Interface Comm Ctrl */
181 #define AHCI_PREG_CMD_ICC_SLUMBER 0x60000000
182 #define AHCI_PREG_CMD_ICC_PARTIAL 0x20000000
183 #define AHCI_PREG_CMD_ICC_ACTIVE 0x10000000
184 #define AHCI_PREG_CMD_ICC_IDLE 0x00000000
185 #define AHCI_PFMT_CMD "\020" "\034ASP" "\033ALPE" "\032DLAE" \
186 "\031ATAPI" "\026ESP" "\025CPD" "\024MPSP" \
187 "\023HPCP" "\022PMA" "\021CPS" "\020CR" \
188 "\017FR" "\016MPSS" "\005FRE" "\004CLO" \
189 "\003POD" "\002SUD" "\001ST"
190
191 #define AHCI_PREG_TFD 0x20 /* Task File Data*/
192 #define AHCI_PREG_TFD_STS 0xff
193 #define AHCI_PREG_TFD_STS_ERR (1<<0)
194 #define AHCI_PREG_TFD_STS_DRQ (1<<3)
195 #define AHCI_PREG_TFD_STS_BSY (1<<7)
196 #define AHCI_PREG_TFD_ERR 0xff00
197
198 #define AHCI_PFMT_TFD_STS "\20" "\010BSY" "\004DRQ" "\001ERR"
199 #define AHCI_PREG_SIG 0x24 /* Signature */
200
201 #define AHCI_PREG_SSTS 0x28 /* SATA Status */
202 #define AHCI_PREG_SSTS_DET 0xf /* Device Detection */
203 #define AHCI_PREG_SSTS_DET_NONE 0x0
204 #define AHCI_PREG_SSTS_DET_DEV_NE 0x1
205 #define AHCI_PREG_SSTS_DET_DEV 0x3
206 #define AHCI_PREG_SSTS_DET_PHYOFFLINE 0x4
207 #define AHCI_PREG_SSTS_SPD 0xf0 /* Current Interface Speed */
208 #define AHCI_PREG_SSTS_SPD_NONE 0x00
209 #define AHCI_PREG_SSTS_SPD_GEN1 0x10
210 #define AHCI_PREG_SSTS_SPD_GEN2 0x20
211 #define AHCI_PREG_SSTS_SPD_GEN3 0x30
212 #define AHCI_PREG_SSTS_IPM 0xf00 /* Interface Power Management */
213 #define AHCI_PREG_SSTS_IPM_NONE 0x000
214 #define AHCI_PREG_SSTS_IPM_ACTIVE 0x100
215 #define AHCI_PREG_SSTS_IPM_PARTIAL 0x200
216 #define AHCI_PREG_SSTS_IPM_SLUMBER 0x600
217
218 #define AHCI_PREG_SCTL 0x2c /* SATA Control */
219 #define AHCI_PREG_SCTL_DET 0xf /* Device Detection */
220 #define AHCI_PREG_SCTL_DET_NONE 0x0
221 #define AHCI_PREG_SCTL_DET_INIT 0x1
222 #define AHCI_PREG_SCTL_DET_DISABLE 0x4
223 #define AHCI_PREG_SCTL_SPD 0xf0 /* Speed Allowed */
224 #define AHCI_PREG_SCTL_SPD_ANY 0x00
225 #define AHCI_PREG_SCTL_SPD_GEN1 0x10
226 #define AHCI_PREG_SCTL_SPD_GEN2 0x20
227 #define AHCI_PREG_SCTL_SPD_GEN3 0x30
228 #define AHCI_PREG_SCTL_IPM 0xf00 /* Interface Power Management */
229 #define AHCI_PREG_SCTL_IPM_NONE 0x000
230 #define AHCI_PREG_SCTL_IPM_NOPARTIAL 0x100
231 #define AHCI_PREG_SCTL_IPM_NOSLUMBER 0x200
232 #define AHCI_PREG_SCTL_IPM_DISABLED 0x300
233 #define AHCI_PREG_SCTL_SPM 0xf000 /* Select Power Management */
234 #define AHCI_PREG_SCTL_SPM_NONE 0x0000
235 #define AHCI_PREG_SCTL_SPM_NOPARTIAL 0x1000
236 #define AHCI_PREG_SCTL_SPM_NOSLUMBER 0x2000
237 #define AHCI_PREG_SCTL_SPM_DISABLED 0x3000
238 #define AHCI_PREG_SCTL_PMP 0xf0000 /* Set PM port for xmit FISes */
239 #define AHCI_PREG_SCTL_PMP_SHIFT 16
240
241 #define AHCI_PREG_SERR 0x30 /* SATA Error */
242 #define AHCI_PREG_SERR_ERR_I (1<<0) /* Recovered Data Integrity */
243 #define AHCI_PREG_SERR_ERR_M (1<<1) /* Recovered Communications */
244 #define AHCI_PREG_SERR_ERR_T (1<<8) /* Transient Data Integrity */
245 #define AHCI_PREG_SERR_ERR_C (1<<9) /* Persistent Comm/Data */
246 #define AHCI_PREG_SERR_ERR_P (1<<10) /* Protocol */
247 #define AHCI_PREG_SERR_ERR_E (1<<11) /* Internal */
248 #define AHCI_PREG_SERR_DIAG_N (1<<16) /* PhyRdy Change */
249 #define AHCI_PREG_SERR_DIAG_I (1<<17) /* Phy Internal Error */
250 #define AHCI_PREG_SERR_DIAG_W (1<<18) /* Comm Wake */
251 #define AHCI_PREG_SERR_DIAG_B (1<<19) /* 10B to 8B Decode Error */
252 #define AHCI_PREG_SERR_DIAG_D (1<<20) /* Disparity Error */
253 #define AHCI_PREG_SERR_DIAG_C (1<<21) /* CRC Error */
254 #define AHCI_PREG_SERR_DIAG_H (1<<22) /* Handshake Error */
255 #define AHCI_PREG_SERR_DIAG_S (1<<23) /* Link Sequence Error */
256 #define AHCI_PREG_SERR_DIAG_T (1<<24) /* Transport State Trans Err */
257 #define AHCI_PREG_SERR_DIAG_F (1<<25) /* Unknown FIS Type */
258 #define AHCI_PREG_SERR_DIAG_X (1<<26) /* Exchanged */
259
260 #define AHCI_PFMT_SERR "\020" \
261 "\033DIAG.X" "\032DIAG.F" "\031DIAG.T" "\030DIAG.S" \
262 "\027DIAG.H" "\026DIAG.C" "\025DIAG.D" "\024DIAG.B" \
263 "\023DIAG.W" "\022DIAG.I" "\021DIAG.N" \
264 "\014ERR.E" "\013ERR.P" "\012ERR.C" "\011ERR.T" \
265 "\002ERR.M" "\001ERR.I"
266
267 #define AHCI_PREG_SACT 0x34 /* SATA Active */
268 #define AHCI_PREG_CI 0x38 /* Command Issue */
269 #define AHCI_PREG_CI_ALL_SLOTS 0xffffffff
270 #define AHCI_PREG_SNTF 0x3c /* SNotification */
271
272 /*
273 * AHCI mapped structures
274 */
275 struct ahci_cmd_hdr {
276 u_int16_t flags;
277 #define AHCI_CMD_LIST_FLAG_CFL 0x001f /* Command FIS Length */
278 #define AHCI_CMD_LIST_FLAG_A (1<<5) /* ATAPI */
279 #define AHCI_CMD_LIST_FLAG_W (1<<6) /* Write */
280 #define AHCI_CMD_LIST_FLAG_P (1<<7) /* Prefetchable */
281 #define AHCI_CMD_LIST_FLAG_R (1<<8) /* Reset */
282 #define AHCI_CMD_LIST_FLAG_B (1<<9) /* BIST */
283 #define AHCI_CMD_LIST_FLAG_C (1<<10) /* Clear Busy upon R_OK */
284 #define AHCI_CMD_LIST_FLAG_PMP 0xf000 /* Port Multiplier Port */
285 #define AHCI_CMD_LIST_FLAG_PMP_SHIFT 12
286 u_int16_t prdtl; /* sgl len */
287
288 u_int32_t prdbc; /* transferred byte count */
289
290 u_int32_t ctba_lo;
291 u_int32_t ctba_hi;
292
293 u_int32_t reserved[4];
294 } __packed;
295
296 struct ahci_rfis {
297 u_int8_t dsfis[28];
298 u_int8_t reserved1[4];
299 u_int8_t psfis[24];
300 u_int8_t reserved2[8];
301 u_int8_t rfis[24];
302 u_int8_t reserved3[4];
303 u_int8_t sdbfis[4];
304 u_int8_t ufis[64];
305 u_int8_t reserved4[96];
306 } __packed;
307
308 struct ahci_prdt {
309 u_int32_t dba_lo;
310 u_int32_t dba_hi;
311 u_int32_t reserved;
312 u_int32_t flags;
313 #define AHCI_PRDT_FLAG_INTR (1<<31) /* interrupt on completion */
314 } __packed;
315
316 /*
317 * The base command table structure is 128 bytes. Each prdt is 16 bytes.
318 * We need to accomodate MAXPHYS (128K) which is at least 32 entries,
319 * plus one for page slop.
320 *
321 * Making the ahci_cmd_table 1024 bytes (a reasonable power of 2)
322 * thus requires MAX_PRDT to be set to 56.
323 */
324 #define AHCI_MAX_PRDT 56
325 #define AHCI_MAX_PMPORTS 16
326
327 #if MAXPHYS / PAGE_SIZE + 1 > AHCI_MAX_PRDT
328 #error "AHCI_MAX_PRDT is not big enough"
329 #endif
330
331 struct ahci_cmd_table {
332 u_int8_t cfis[64]; /* Command FIS */
333 u_int8_t acmd[16]; /* ATAPI Command */
334 u_int8_t reserved[48];
335
336 struct ahci_prdt prdt[AHCI_MAX_PRDT];
337 } __packed;
338
339 #define AHCI_MAX_PORTS 32
340
341 struct ahci_dmamem {
342 bus_dma_tag_t adm_tag;
343 bus_dmamap_t adm_map;
344 bus_dma_segment_t adm_seg;
345 bus_addr_t adm_busaddr;
346 caddr_t adm_kva;
347 };
348 #define AHCI_DMA_MAP(_adm) ((_adm)->adm_map)
349 #define AHCI_DMA_DVA(_adm) ((_adm)->adm_busaddr)
350 #define AHCI_DMA_KVA(_adm) ((void *)(_adm)->adm_kva)
351
352 struct ahci_softc;
353 struct ahci_port;
354 struct ahci_device;
355
356 struct ahci_ccb {
357 /* ATA xfer associated with this CCB. Must be 1st struct member. */
358 struct ata_xfer ccb_xa;
359 struct callout ccb_timeout;
360
361 int ccb_slot;
362 struct ahci_port *ccb_port;
363
364 bus_dmamap_t ccb_dmamap;
365 struct ahci_cmd_hdr *ccb_cmd_hdr;
366 struct ahci_cmd_table *ccb_cmd_table;
367
368 void (*ccb_done)(struct ahci_ccb *);
369
370 TAILQ_ENTRY(ahci_ccb) ccb_entry;
371 };
372
373 struct ahci_port {
374 struct ahci_softc *ap_sc;
375 bus_space_handle_t ap_ioh;
376
377 int ap_num;
378 int ap_pmcount;
379 int ap_flags;
380 #define AP_F_BUS_REGISTERED 0x0001
381 #define AP_F_CAM_ATTACHED 0x0002
382 #define AP_F_IN_RESET 0x0004
383 #define AP_F_SCAN_RUNNING 0x0008
384 #define AP_F_SCAN_REQUESTED 0x0010
385 #define AP_F_SCAN_COMPLETED 0x0020
386 #define AP_F_IGNORE_IFS 0x0040
387 #define AP_F_IFS_IGNORED 0x0080
388 #define AP_F_UNUSED_0100 0x0100
389 #define AP_F_EXCLUSIVE_ACCESS 0x0200
390 #define AP_F_ERR_CCB_RESERVED 0x0400
391 #define AP_F_HARSH_REINIT 0x0800
392 int ap_signal; /* os per-port thread sig */
393 thread_t ap_thread; /* os per-port thread */
394 struct lock ap_lock; /* os per-port lock */
395 struct lock ap_sim_lock; /* cam sim lock */
396 struct lock ap_sig_lock; /* signal thread */
397 #define AP_SIGF_INIT 0x0001
398 #define AP_SIGF_TIMEOUT 0x0002
399 #define AP_SIGF_PORTINT 0x0004
400 #define AP_SIGF_THREAD_SYNC 0x0008
401 #define AP_SIGF_STOP 0x8000
402 struct cam_sim *ap_sim;
403
404 struct ahci_rfis *ap_rfis;
405 struct ahci_dmamem *ap_dmamem_rfis;
406
407 struct ahci_dmamem *ap_dmamem_cmd_list;
408 struct ahci_dmamem *ap_dmamem_cmd_table;
409
410 u_int32_t ap_active; /* active CI command bmask */
411 u_int32_t ap_active_cnt; /* active CI command count */
412 u_int32_t ap_sactive; /* active SACT command bmask */
413 u_int32_t ap_expired; /* deferred expired bmask */
414 u_int32_t ap_intmask; /* interrupts we care about */
415 struct ahci_ccb *ap_ccbs;
416 struct ahci_ccb *ap_err_ccb; /* always CCB SLOT 1 */
417 int ap_run_flags; /* used to check excl mode */
418
419 TAILQ_HEAD(, ahci_ccb) ap_ccb_free;
420 TAILQ_HEAD(, ahci_ccb) ap_ccb_pending;
421 struct lock ap_ccb_lock;
422
423 int ap_type; /* ATA_PORT_T_xxx */
424 int ap_probe; /* ATA_PROBE_xxx */
425 struct ata_port *ap_ata[AHCI_MAX_PMPORTS];
426
427 u_int32_t ap_state;
428 #define AP_S_NORMAL 0
429 #define AP_S_FATAL_ERROR 1
430
431 /* For error recovery. */
432 u_int32_t ap_err_saved_sactive;
433 u_int32_t ap_err_saved_active;
434 u_int32_t ap_err_saved_active_cnt;
435
436 u_int8_t *ap_err_scratch;
437
438 int link_pwr_mgmt;
439
440 struct sysctl_ctx_list sysctl_ctx;
441 struct sysctl_oid *sysctl_tree;
442
443 char ap_name[16];
444 };
445
446 #define PORTNAME(_ap) ((_ap)->ap_name)
447 #define ATANAME(_ap, _at) ((_at) ? (_at)->at_name : (_ap)->ap_name)
448
449 struct ahci_softc {
450 device_t sc_dev;
451 const struct ahci_device *sc_ad; /* special casing */
452
453 struct resource *sc_irq; /* bus resources */
454 struct resource *sc_regs; /* bus resources */
455 bus_space_tag_t sc_iot; /* split from sc_regs */
456 bus_space_handle_t sc_ioh; /* split from sc_regs */
457
458 int sc_rid_irq; /* saved bus RIDs */
459 int sc_rid_regs;
460 u_int32_t sc_cap; /* capabilities */
461 int sc_numports;
462 u_int32_t sc_portmask;
463
464 void *sc_irq_handle; /* installed irq vector */
465
466 bus_dma_tag_t sc_tag_rfis; /* bus DMA tags */
467 bus_dma_tag_t sc_tag_cmdh;
468 bus_dma_tag_t sc_tag_cmdt;
469 bus_dma_tag_t sc_tag_data;
470
471 int sc_flags;
472 #define AHCI_F_NO_NCQ (1<<0)
473 #define AHCI_F_IGN_FR (1<<1) /* Ignore FIS errors */
474 #define AHCI_F_INT_GOOD (1<<2)
475 #define AHCI_F_NO_PM (1<<3) /* Broken port multiplier */
476
477 u_int sc_ncmds;
478
479 struct ahci_port *sc_ports[AHCI_MAX_PORTS];
480
481 #ifdef AHCI_COALESCE
482 u_int32_t sc_ccc_mask;
483 u_int32_t sc_ccc_ports;
484 u_int32_t sc_ccc_ports_cur;
485 #endif
486
487 struct sysctl_ctx_list sysctl_ctx;
488 struct sysctl_oid *sysctl_tree;
489 };
490 #define DEVNAME(_s) "ahci.device"
491
492 struct ahci_device {
493 pci_vendor_id_t ad_vendor;
494 pci_product_id_t ad_product;
495 int (*ad_attach)(device_t dev);
496 int (*ad_detach)(device_t dev);
497 char *name;
498 };
499
500 /* Wait for all bits in _b to be cleared */
501 #define ahci_pwait_clr(_ap, _r, _b) \
502 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), 0)
503 #define ahci_pwait_clr_to(_ap, _to, _r, _b) \
504 ahci_pwait_eq((_ap), _to, (_r), (_b), 0)
505
506 /* Wait for all bits in _b to be set */
507 #define ahci_pwait_set(_ap, _r, _b) \
508 ahci_pwait_eq((_ap), AHCI_PWAIT_TIMEOUT, (_r), (_b), (_b))
509 #define ahci_pwait_set_to(_ap, _to, _r, _b) \
510 ahci_pwait_eq((_ap), _to, (_r), (_b), (_b))
511
512 #define AHCI_PWAIT_TIMEOUT 1000
513
514 const struct ahci_device *ahci_lookup_device(device_t dev);
515 int ahci_init(struct ahci_softc *);
516 int ahci_port_init(struct ahci_port *ap);
517 int ahci_port_alloc(struct ahci_softc *, u_int);
518 void ahci_port_state_machine(struct ahci_port *ap, int initial);
519 void ahci_port_free(struct ahci_softc *, u_int);
520 int ahci_port_reset(struct ahci_port *, struct ata_port *at, int);
521 void ahci_port_link_pwr_mgmt(struct ahci_port *, int link_pwr_mgmt);
522 int ahci_port_link_pwr_state(struct ahci_port *);
523
524 u_int32_t ahci_read(struct ahci_softc *, bus_size_t);
525 void ahci_write(struct ahci_softc *, bus_size_t, u_int32_t);
526 int ahci_wait_ne(struct ahci_softc *, bus_size_t, u_int32_t, u_int32_t);
527 u_int32_t ahci_pread(struct ahci_port *, bus_size_t);
528 void ahci_pwrite(struct ahci_port *, bus_size_t, u_int32_t);
529 int ahci_pwait_eq(struct ahci_port *, int, bus_size_t,
530 u_int32_t, u_int32_t);
531 void ahci_intr(void *);
532 void ahci_port_intr(struct ahci_port *ap, int blockable);
533
534 int ahci_port_start(struct ahci_port *ap);
535 int ahci_port_stop(struct ahci_port *ap, int stop_fis_rx);
536 int ahci_port_clo(struct ahci_port *ap);
537 void ahci_flush_tfd(struct ahci_port *ap);
538 int ahci_set_feature(struct ahci_port *ap, struct ata_port *atx,
539 int feature, int enable);
540
541 int ahci_cam_attach(struct ahci_port *ap);
542 void ahci_cam_changed(struct ahci_port *ap, struct ata_port *at, int found);
543 void ahci_cam_detach(struct ahci_port *ap);
544 int ahci_cam_probe(struct ahci_port *ap, struct ata_port *at);
545
546 struct ata_xfer *ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at);
547 void ahci_ata_put_xfer(struct ata_xfer *xa);
548 int ahci_ata_cmd(struct ata_xfer *xa);
549
550 int ahci_pm_port_probe(struct ahci_port *ap, int);
551 int ahci_pm_port_init(struct ahci_port *ap, struct ata_port *at);
552 int ahci_pm_identify(struct ahci_port *ap);
553 int ahci_pm_hardreset(struct ahci_port *ap, int target, int hard);
554 int ahci_pm_softreset(struct ahci_port *ap, int target);
555 int ahci_pm_phy_status(struct ahci_port *ap, int target, u_int32_t *datap);
556 int ahci_pm_read(struct ahci_port *ap, int target,
557 int which, u_int32_t *res);
558 int ahci_pm_write(struct ahci_port *ap, int target,
559 int which, u_int32_t data);
560 void ahci_pm_check_good(struct ahci_port *ap, int target);
561 void ahci_ata_cmd_timeout(struct ahci_ccb *ccb);
562 void ahci_quick_timeout(struct ahci_ccb *ccb);
563 struct ahci_ccb *ahci_get_ccb(struct ahci_port *ap);
564 void ahci_put_ccb(struct ahci_ccb *ccb);
565 struct ahci_ccb *ahci_get_err_ccb(struct ahci_port *);
566 void ahci_put_err_ccb(struct ahci_ccb *);
567 int ahci_poll(struct ahci_ccb *ccb, int timeout,
568 void (*timeout_fn)(struct ahci_ccb *));
569
570 int ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at);
571 void ahci_port_thread_core(struct ahci_port *ap, int mask);
572
573 void ahci_os_sleep(int ms);
574 void ahci_os_hardsleep(int us);
575 int ahci_os_softsleep(void);
576 void ahci_os_start_port(struct ahci_port *ap);
577 void ahci_os_stop_port(struct ahci_port *ap);
578 void ahci_os_signal_port_thread(struct ahci_port *ap, int mask);
579 void ahci_os_lock_port(struct ahci_port *ap);
580 int ahci_os_lock_port_nb(struct ahci_port *ap);
581 void ahci_os_unlock_port(struct ahci_port *ap);
582
583 extern u_int32_t AhciForceGen;
584 extern u_int32_t AhciNoFeatures;
585
586 enum {AHCI_LINK_PWR_MGMT_NONE, AHCI_LINK_PWR_MGMT_MEDIUM,
587 AHCI_LINK_PWR_MGMT_AGGR};
Mirror of AROS' svn.