arch/arm-sun4i/include/hardware/ccm.h

   1 /*
   2     Copyright © 2014, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: sun4i clock control module
   6     Lang: english
   7 */
   8
   9 #ifndef HARDWARE_SUN4I_CCM_H
  10 #define HARDWARE_SUN4I_CCM_H
  11
  12 #ifndef EXEC_TYPES_H
  13 #include <exec/types.h>
  14 #endif
  15
  16 #ifndef _INTTYPES_H
  17 #include <inttypes.h>
  18 #endif
  19
  20 #define SUN4I_CCM_BASE                  0x01c20000
  21
  22 struct CCM {
  23         uint32_t PLL1_CFG;
  24         uint32_t PLL1_TUN;
  25         uint32_t PLL2_CFG;
  26         uint32_t PLL2_TUN;
  27         uint32_t PLL3_CFG;
  28         uint32_t CCM_RESERVED_1;
  29         uint32_t PLL4_CFG;
  30         uint32_t CCM_RESERVED_2;
  31         uint32_t PLL5_CFG;
  32         uint32_t PLL5_TUN;
  33         uint32_t PLL6_CFG;
  34         uint32_t PLL6_TUN;
  35         uint32_t PLL7_CFG;
  36         uint32_t CCM_RESERVED_3;
  37         uint32_t PLL1_TUN2;
  38         uint32_t PLL5_TUN2;
  39         uint8_t  CCM_RESERVED_4[12];
  40         uint32_t PLL_LOCK_DBG;
  41         uint32_t OSC24M_CFG;
  42         uint32_t CPU_AHB_APB0_CFG;
  43         uint32_t APB1_CLK_DIV;
  44         uint32_t AXI_GATING;
  45         uint32_t AHB_GATING0;
  46         uint32_t AHB_GATING1;
  47         uint32_t APB0_GATING;
  48         uint32_t APB1_GATING;
  49         uint8_t  CCM_RESERVED_5[16];
  50         uint32_t NAND_SCLK_CFG;
  51         uint32_t MS_SCLK_CFG;
  52         uint32_t MMC0_SCLK_CFG;
  53         uint32_t MMC1_SCLK_CFG;
  54         uint32_t MMC2_SCLK_CFG;
  55         uint32_t MMC3_SCLK_CFG;
  56         uint32_t TS_CLK;
  57         uint32_t SS_CLK;
  58         uint32_t SPI0_CLK;
  59         uint32_t SPI1_CLK;
  60         uint32_t SPI2_CLK;
  61         uint32_t PATA_CLK;
  62         uint32_t IR0_CLK;
  63         uint32_t IR1_CLK;
  64         uint32_t IIS_CLK;
  65         uint32_t AC97_CLK;
  66         uint32_t SPDIF_CLK;
  67         uint32_t KEYPAD_CLK;
  68         uint32_t SATA_CLK;
  69         uint32_t USB_CLK;
  70         uint32_t GPS_CLK;
  71         uint32_t SPI3_CLK;
  72         uint8_t  CCM_RESERVED_6[40];
  73         uint32_t DRAM_CLK;
  74         uint32_t BE0_SCLK;
  75         uint32_t BE1_SCLK;
  76         uint32_t FE0_CLK;
  77         uint32_t FE1_CLK;
  78         uint32_t MP_CLK;
  79         uint32_t LCD0_CH0_CLK;
  80         uint32_t LCD1_CH0_CLK;
  81         uint32_t CSI_ISP_CLK;
  82         uint32_t CCM_RESERVED_7[12];
  83         uint32_t TVD_CLK;
  84         uint32_t LCD0_CH1_CLK;
  85         uint32_t LCD1_CH1_CLK;
  86         uint32_t CS0_CLK;
  87         uint32_t CS1_CLK;
  88         uint32_t VE_CLK;
  89         uint32_t AUDIO_CODEC_CLK;
  90         uint32_t AVS_CLK;
  91         uint32_t ACE_CLK;
  92         uint32_t LVDS_CLK;
  93         uint32_t HDMI_CLK;
  94         uint32_t MALI400_CLK;
  95         uint32_t MBUS_CLK;
  96         uint32_t GMAC_CLK;
  97         uint32_t HDMI1_RST_CLK;
  98         uint32_t HDMI1_CTRL_CLK;
  99         uint32_t HDMI1_SLOW_CLK;
 100         uint32_t HDMI1_REPEAT_CLK;
 101         uint32_t OUTA_CLK;
 102         uint32_t OUTB_CLK;
 103 }__attribute__((__packed__));
 104
 105 #endif