workbench/devs/AHI/Drivers/HDAudio/regs.h

   1 #ifndef _REGS_H
   2 #define _REGS_H
   3
   4 #define HD_GCAP 0x0 // word
   5   #define HD_GCAP_ISS_MASK 0x0F00
   6   #define HD_GCAP_OSS_MASK 0xF000
   7 #define HD_VMIN 0x2
   8 #define HD_VMAJ 0x3
   9 #define HD_GCTL 0x8
  10 #define HD_STATESTS 0xE
  11
  12 #define HD_INTCTL 0x20 // interrupt control
  13   #define HD_INTCTL_GLOBAL 0x80000000
  14   #define HD_INTCTL_CIE    0x40000000
  15 #define HD_INTSTS 0x24 // interrupt status
  16
  17
  18 // CORB
  19 #define HD_CORB_LOW 0x40
  20 #define HD_CORB_HIGH 0x44
  21 #define HD_CORBWP 0x48 // write pointer
  22 #define HD_CORBRP 0x4A
  23   #define HD_CORBRPRST 0x8000 // corb read pointer reset
  24 #define HD_CORBCTL 0x4C // CORB Control
  25   #define HD_CORBRUN 0x2 // DMA Run
  26 #define HD_CORBSIZE 0x4E
  27
  28
  29 // RIRB
  30 #define HD_RIRB_LOW 0x50
  31 #define HD_RIRB_HIGH 0x54
  32 #define HD_RIRBWP 0x58 // write pointer
  33   #define HD_RIRBWPRST 0x8000
  34 #define HD_RINTCNT 0x5A // repsonse interrupt count, 2 bytes
  35   #define HD_RINTCNT_MASK 0xFF
  36 #define HD_RIRBCTL 0x5C // RIRB Control
  37   #define HD_RIRBRUN 0x2 // DMA Run
  38   #define HD_RINTCTL 0x1
  39 #define HD_RIRBSTS 0x5D // RIRB status
  40 #define HD_RIRBSIZE 0x5E
  41
  42 // DMA position
  43 #define HD_DPLBASE 0x70
  44   #define HD_DPLBASE_ENABLE 0x1
  45 #define HD_DPUBASE 0x74
  46
  47
  48 // 3.3.35 I/O/B stream descriptor n control
  49
  50 #define HD_SD_BASE_OFFSET 0x80 // 0x80: input stream descriptor 0, 0x80 + (ISS * 0x20) = output stream descriptor 0, descriptor size = 0x20
  51 #define HD_SD_DESCRIPTOR_SIZE 0x20
  52
  53 #define HD_SD_OFFSET_CONTROL 0x00 // 3 bytes
  54   #define HD_SD_CONTROL_IOCE 0x4 // interrupt on completion enable
  55   #define HD_SD_CONTROL_STREAM_RUN 0x2
  56 #define HD_SD_OFFSET_STATUS  0x03
  57   #define HD_SD_STATUS_MASK 0x1C
  58 #define HD_SD_OFFSET_LINKPOS 0x04 // read only
  59 #define HD_SD_OFFSET_CYCLIC_BUFFER_LEN 0x08 // 4 bytes
  60 #define HD_SD_OFFSET_LAST_VALID_INDEX 0x0C // 2 bytes
  61 #define HD_SD_OFFSET_FIFO_SIZE 0x10 // 2 bytes
  62 #define HD_SD_OFFSET_FORMAT 0x12 // 2 bytes
  63 #define HD_SD_OFFSET_BDL_ADDR_LOW 0x18 // 4 bytes
  64 #define HD_SD_OFFSET_BDL_ADDR_HIGH 0x1C // 4 bytes
  65
  66 // verbs
  67 #define VERB_GET_PARMS 0xF00
  68   #define VERB_GET_PARMS_VENDOR_DEVICE 0x0
  69   #define VERB_GET_PARMS_NODE_COUNT 0x04
  70   #define VERB_GET_PARMS_FUNCTION_GROUP_TYPE 0x5
  71   #define VERB_GET_PARMS_AUDIO_WIDGET_CAPS 0x9
  72     #define AUDIO_WIDGET_CAPS(x) ((x >> 20) & 0xF)
  73     #define AUDIO_WIDGET_POWER_CONTROL(x) ((x >> 10) & 0x1)
  74   #define VERB_GET_PARMS_SUPPORTED_PCM_SIZE_RATE 0xA
  75   #define VERB_GET_PARMS_PIN_CAPS 0xC
  76     #define PIN_CAPS_EAPD_CAPABLE (1 << 16)
  77   #define VERB_GET_PARMS_OUTPUT_AMP_CAPS 0x12
  78   #define AUDIO_FUNCTION 0x01
  79
  80
  81 #define VERB_SET_CONVERTER_FORMAT 0x2
  82   #define BASE44 (1 << 14)
  83   #define FORMAT_24BITS (0x3 << 4)
  84   #define FORMAT_16BITS (0x1 << 4)
  85   #define FORMAT_STEREO 0x1
  86
  87 #define VERB_SET_AMP_GAIN 0x3
  88   #define OUTPUT_AMP_GAIN (1 << 15)
  89   #define INPUT_AMP_GAIN (1 << 14)
  90   #define AMP_GAIN_LR (3 << 12)
  91
  92 #define VERB_SET_CONNECTION_SELECT 0x701
  93 #define VERB_SET_POWER_STATE 0x705
  94 #define VERB_SET_CONVERTER_STREAM_CHANNEL 0x706
  95 #define VERB_SET_PIN_WIDGET_CONTROL 0x707
  96 #define VERB_SET_EAPD 0x70C
  97
  98 #define VERB_GET_CONNECTION_SELECT 0xF01
  99 #define VERB_GET_CONNECTION_LIST_ENTRY 0xF02
 100 #define VERB_GET_POWER_STATE 0xF05
 101 #define VERB_GET_PIN_WIDGET_CONTROL 0xF07
 102 #define VERB_GET_PIN_SENSE 0xF09
 103 #define VERB_EXECUTE_PIN_SENSE 0x709
 104 #define VERB_GET_CONFIG_DEFAULT 0xF1C
 105 #define VERB_FUNCTION_RESET 0x7FF
 106
 107 #endif /* _REGS_H */