workbench/devs/AHI/Drivers/SB128/SB128/regs.h

   1 /*
   2
   3 The contents of this file are subject to the AROS Public License Version 1.1 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at
   4 http://www.aros.org/license.html
   5
   6 Software distributed under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF
   7 ANY KIND, either express or implied. See the License for the specific language governing rights and
   8 limitations under the License.
   9
  10 The Original Code is (C) Copyright 2004-2011 Ross Vumbaca.
  11
  12 The Initial Developer of the Original Code is Ross Vumbaca.
  13
  14 All Rights Reserved.
  15
  16 */
  17
  18 #ifndef _REGS_H
  19 #define _REGS_H
  20
  21 #define CACHELINE_SIZE 32
  22
  23 /* Basic registers */
  24
  25 #define SB128_CONTROL   0x00
  26 #define SB128_STATUS    0x04
  27
  28 #define SB128_MIDI_DATA     0x08
  29 #define SB128_MIDI_STATUS   0x09
  30 #define SB128_MIDI_TEST     0x0A
  31
  32 #define SB128_MEMPAGE   0x0C
  33
  34 #define SB128_SRC       0x10
  35
  36 #define SB128_CODEC     0x14
  37
  38 #define SB128_LEGACY    0x18
  39
  40 #define SB128_SCON      0x20
  41
  42 #define SB128_DAC1_SCOUNT   0x24
  43 #define SB128_DAC2_SCOUNT   0x28
  44 #define SB128_ADC_SCOUNT    0x2C
  45
  46 #define SB128_PAGE_DAC      0x0C
  47 #define SB128_PAGE_ADC      0x0D
  48
  49 #define SB128_DAC1_FRAME    0x30
  50 #define SB128_DAC1_COUNT    0x34
  51 #define SB128_DAC2_FRAME    0x38
  52 #define SB128_DAC2_COUNT    0x3C
  53 #define SB128_ADC_FRAME     0x30
  54 #define SB128_ADC_COUNT     0x34
  55
  56   /* ES1370 specific, not present on other chips */
  57
  58   #define ES1370_SB128_CODEC  0x10
  59
  60
  61
  62 /* DAC/ADC and misc Control */
  63
  64 #define CTRL_DAC1_EN    0x00000040 /* Enable DAC1 */
  65 #define CTRL_DAC2_EN    0x00000020 /* Enable DAC2 */
  66 #define CTRL_ADC_EN     0x00000010 /* Enable ADC */
  67
  68   /* ES1370 specific, not present on other chips */
  69
  70   #define CTRL_CDC_EN    0x00000002 /* Enable Codec Control */
  71
  72     /* Magical formula for DAC2 frequency */
  73   #define DAC2_SRTODIV(x) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff)
  74
  75   #define DAC2_DIV_SHIFT 16
  76
  77   #define DAC2_DIV_MASK  0x1fff0000
  78
  79
  80 /* Codec Control */
  81
  82 #define CODEC_RESET     0x00004000
  83
  84 #define CODEC_WIP       0x40000000
  85 #define CODEC_RDY       0x80000000
  86
  87 #define CODEC_ADD_SHIFT 16
  88 #define CODEC_ADD_MASK  0x007F0000
  89 #define CODEC_READ      0x00800000
  90
  91   /* ES1370 specific, not present on other chips */
  92
  93   #define CODEC_CSTAT            0x00000200
  94
  95   #define ES1370_CODEC_ADD_SHIFT 8
  96
  97 /* Sample Rate Converter */
  98
  99 #define SRC_DISABLE     0x00400000
 100 #define SRC_BUSY        0x00800000
 101 #define SRC_DIS_DAC1    0x00200000
 102 #define SRC_DIS_DAC2    0x00100000
 103 #define SRC_DIS_ADC     0x00080000
 104
 105 #define SRC_DAC1        0x70
 106 #define SRC_DAC2        0x74
 107 #define SRC_ADC         0x78
 108
 109 #define SRC_VOL_ADC     0x6C
 110 #define SRC_VOL_DAC1    0x7C
 111 #define SRC_VOL_DAC2    0x7E
 112
 113
 114 /* Offsets for some "Magic" SRC bits */
 115
 116 #define SRC_TRUNC       0x00
 117 #define SRC_INT         0x01
 118 #define SRC_VF          0x03
 119
 120 #define SRC_ADDR_SHIFT  25
 121 #define SRC_WE          0x01000000
 122
 123
 124 /* Interrupts */
 125
 126 #define SB128_IRQ_MASK    0xFFFFF8FF /* To disable all playback/record interrupts */
 127 #define SB128_INT_PENDING 0x80000000 /* Interrupt pending */
 128 #define SB128_INT_DAC1    0x00000004 /* DAC1 Interrupt pending */
 129 #define SB128_INT_DAC2    0x00000002 /* DAC2 Interrupt pending */
 130 #define SB128_INT_ADC     0x00000001 /* ADC Interrupt pending */
 131 #define SB128_DAC1_INTEN  0x00000100 /* Enable DAC1 Interrupts */
 132 #define SB128_DAC2_INTEN  0x00000200 /* Enable DAC2 Interrupts */
 133 #define SB128_ADC_INTEN   0x00000400 /* Enable ADC Interrupts */
 134
 135
 136 /* Data Format */
 137
 138 #define SB128_STEREO      0x1
 139 #define SB128_16BIT       0x2
 140
 141
 142
 143 /* ES1370 specific - AK4531 registers */
 144
 145   /* Output volumes */
 146
 147 #define AK4531_MASTER_VOL_L     0x00 /* -62 dB to 0 dB attentuation */
 148 #define AK4531_MASTER_VOL_R     0x01 /* -62 dB to 0 dB attentuation */
 149
 150 #define AK4531_MASTER_VOL_MONO  0x0F /* -28 dB to 0 dB attentuation */
 151
 152   /* Input gain */
 153
 154 #define AK4531_PCMOUT_VOL_L     0x02 /* Adjustable gain from -50 dB to +12 dB for all below */
 155 #define AK4531_PCMOUT_VOL_R     0x03
 156 #define AK4531_CD_VOL_L         0x06
 157 #define AK4531_CD_VOL_R         0x07
 158 #define AK4531_LINEIN_VOL_L     0x08
 159 #define AK4531_LINEIN_VOL_R     0x09
 160 #define AK4531_AUX_VOL_L        0x0A
 161 #define AK4531_AUX_VOL_R        0x0B
 162 #define AK4531_PHONE_VOL_L      0x0C
 163 #define AK4531_PHONE_VOL_R      0x0D
 164 #define AK4531_MIC_VOL          0x0E
 165
 166   /* Mixer registers */
 167
 168 #define AK4531_OUTPUT_MUX_1     0x10
 169 #define AK4531_OUTPUT_MUX_2     0x11
 170
 171 #define AK4531_INPUT_MUX_L_1    0x12
 172 #define AK4531_INPUT_MUX_R_1    0x13
 173
 174 #define AK4531_INPUT_MUX_L_2    0x14
 175 #define AK4531_INPUT_MUX_R_2    0x15
 176
 177   /* Output MUX bits */
 178
 179 #define AK4531_OUTPUT_CD        0x06
 180 #define AK4531_OUTPUT_LINE      0x18
 181 #define AK4531_OUTPUT_AUX       0x30
 182
 183   /* Other stuff */
 184
 185 #define AK4531_MUTE             0x80
 186
 187 #define AK4531_RECORD_SELECT    0x18 /* Input from mixer or external pins */
 188
 189 #define AK4531_RECORD_GAIN_MIC  0x19 /* Either 0 dB or 30 dB gain */
 190
 191 #define AK4531_RESET            0x16
 192 #define AK4531_CLOCK_SEL        0x17
 193
 194
 195
 196 /* AC97 Registers */
 197
 198 #define AC97_RESET               0x0000
 199
 200
 201 /* Play master volume registers */
 202
 203 #define AC97_MASTER_VOL_STEREO   0x0002 /* -94.5 to 0.0 dB attenuation */
 204 #define AC97_AUXOUT_VOL          0x0004 /* "" + can be impl. as line level out, headphone out or 4ch out. Most likely 4ch out vol. */
 205 #define AC97_MASTER_VOL_MONO     0x0006 /* "" */
 206
 207 #define AC97_MASTER_TONE         0x0008 /* bass / treble */
 208 #define AC97_PCBEEP_VOL          0x000a
 209
 210
 211 /* Analog mixer input gain registers
 212    5-bit gain: -32.5 dB attenuation to +12.0 dB gain
 213    0x0008 is 0dB gain, 0x8008 is 0dB gain with mute on */
 214
 215 #define AC97_PHONE_VOL           0x000c /* mono: only bits 0-4 */
 216 #define AC97_MIC_VOL             0x000e /* mono + bit 6 is 20dB boost switch */
 217 #define AC97_LINEIN_VOL          0x0010 /* stereo */
 218 #define AC97_CD_VOL              0x0012
 219 #define AC97_VIDEO_VOL           0x0014
 220 #define AC97_AUX_VOL             0x0016
 221 #define AC97_PCMOUT_VOL          0x0018
 222
 223 #define AC97_RECORD_SELECT       0x001a
 224
 225
 226 /* 0dB to 22.5 dB gain on the stereo input */
 227
 228 #define AC97_RECORD_GAIN         0x001c
 229 #define AC97_RECORD_GAIN_MIC     0x001e
 230
 231 #define AC97_GENERAL_PURPOSE     0x0020
 232 #define AC97_3D_CONTROL          0x0022
 233
 234
 235 /* Mostly a read-only register (except D5 and D4 which control optional DAC slot assignment)
 236    controls variable SRC, double-rate output, multi-channel output and S/PDIF output */
 237
 238 #define AC97_EXTENDED_ID         0x0028
 239 #define AC97_EXTENDED_CTRL       0x002a
 240
 241 #define AC97_SPDIF_CTRL          0x003a
 242
 243 #define AC97_SURROUND_MASTER     0x0038
 244
 245 #define AC97_VENDOR_ID0          0x007C
 246 #define AC97_VENDOR_ID1          0x007E
 247
 248 #define AC97_MUTE                0x8000
 249
 250 #define AC97_RECMUX_MIC          0x0000
 251 #define AC97_RECMUX_CD           0x0101
 252 #define AC97_RECMUX_VIDEO        0x0202
 253 #define AC97_RECMUX_AUX          0x0303
 254 #define AC97_RECMUX_LINE         0x0404
 255 #define AC97_RECMUX_STEREO_MIX   0x0505
 256 #define AC97_RECMUX_MONO_MIX     0x0606
 257 #define AC97_RECMUX_PHONE        0x0707
 258
 259
 260 #endif /* _REGS_H */